Tests: Fix t_fork_join_none_capture for other simulators
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// DESCRIPTION: Verilator: Verilog Test module
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// DESCRIPTION: Verilator: Verilog Test module
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//
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// This file ONLY is placed under the Creative Commons Public Domain.
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// any use, without warranty, 2026 by Antmicro Ltd.
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// SPDX-FileCopyrightText: 2026 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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// SPDX-License-Identifier: CC0-1.0
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module test;
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module test;
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@ -11,14 +11,13 @@ module test;
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mbox.put(10);
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mbox.put(10);
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mbox.put(30);
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mbox.put(30);
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repeat(2) begin
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repeat (2) begin
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int item;
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automatic int item;
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mbox.get(item);
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mbox.get(item);
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fork
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fork
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begin
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begin
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$display("got", item);
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$display("got", item);
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if(item==10)
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if (item == 10) $finish;
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$finish;
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end
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end
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join_none
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join_none
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end
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end
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