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test: Added test for failing instrumentation

This commit is contained in:
Jonathan Schröter 2025-10-22 11:28:38 +02:00
parent f50d72eb9e
commit 37ad722bb8
8 changed files with 60 additions and 7 deletions
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1
test_regress/t/t_instrument.v
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@ -31,6 +31,7 @@ module module_b (
input logic [7:0] in2,
output logic [7:0] out
);
reg [127:0] bigRegister;
always_comb begin
out = in1 + in2;
end

1
test_regress/t/t_instrument_bad.out
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@ -1 +0,0 @@

2
test_regress/t/t_instrument_bad1.out Normal file
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@ -0,0 +1,2 @@
%Error: In .vlt defined target tries to instrument the highest MODULE, is not possible! ... Target string: top_module.outa
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

14
test_regress/t/t_instrument_bad.py → test_regress/t/t_instrument_bad1.py
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@ -9,10 +9,16 @@
import vltest_bootstrap
test.scenarios('linter')
test.scenarios('simulator')
test.top_filename = "t/t_instrument.v"
test.flag = "--instrument"
test.lint(fails=True, expect_filename=test.golden_filename)
sim_filename = "t/t_instrument.cpp"
dpi_filename = "t/t_instrumentDPI.cpp"
vlt_filename = "t/" + test.name + ".vlt"
test.passes()
test.compile(fails=True, make_top_shell=False,
make_main=False,
v_flags2=["--trace --timing --exe --instrument", sim_filename, vlt_filename, dpi_filename],
expect_filename=test.golden_filename)
test.passes()

9
test_regress/t/t_instrument_bad1.vlt Normal file
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@ -0,0 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`verilator_config
instrument -callback "instrument_var" -id 0 -target "top_module.outa"

12
test_regress/t/t_instrument_bad2.out Normal file
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@ -0,0 +1,12 @@
%Error: Verilator-configfile': could not find initial 'module' in 'module.instance.__' ... Target: 'top.a1.b1'
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Verilator-configfile: target variable 'bigRegister' in 'top_module.a1.b1' must be a supported type!
%Error: Verilator-configfile': could not find defined 'var' in 'topModule.instance.var' ... Target string: 'top_module.a1.b1.clk'
%Error: Verilator-configfile': could not find '.var' in '__.module.var' ... Target: 'top_module.a1.b1'
%Error: Verilator-configfile: could not find 'instance' in '__.instance.__' ... Target string: 'top_module.a1.b3'
%Error: Verilator-configfile': could not find initial 'instance' in 'topModule.instance.__' ... Target string: 'top_module.a3.b1'
%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top.a1.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a1.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a1.b3'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a3.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
%Error: Exiting due to

24
test_regress/t/t_instrument_bad2.py Executable file
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@ -0,0 +1,24 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_instrument.v"
sim_filename = "t/t_instrument.cpp"
dpi_filename = "t/t_instrumentDPI.cpp"
vlt_filename = "t/" + test.name + ".vlt"
test.compile(fails=True, make_top_shell=False,
make_main=False,
v_flags2=["--trace --timing --exe --instrument", sim_filename, vlt_filename, dpi_filename],
expect_filename=test.golden_filename)
test.passes()

4
test_regress/t/t_instrument_bad.vlt → test_regress/t/t_instrument_bad2.vlt
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@ -6,8 +6,6 @@
`verilator_config
instrument -callback "instrument_var" -id 0 -target "top_module.outa"
instrument -callback "instrument_var" -id 0 -target "top.a1.b1.out"
instrument -callback "instrument_var" -id 0 -target "top_module.a3.b1.out"
@ -15,3 +13,5 @@ instrument -callback "instrument_var" -id 0 -target "top_module.a3.b1.out"
instrument -callback "instrument_var" -id 0 -target "top_module.a1.b3.out"
instrument -callback "instrument_var" -id 0 -target "top_module.a1.b1.clk"
instrument -callback "instrument_var" -id 0 -target "top_module.a1.b1.bigRegister"