diff --git a/test_regress/t/t_instrument.v b/test_regress/t/t_instrument.v
index 5a7a8a2b8..71471aed9 100644
--- a/test_regress/t/t_instrument.v
+++ b/test_regress/t/t_instrument.v
@@ -31,6 +31,7 @@ module module_b (
     input logic [7:0] in2,
     output logic [7:0] out
 );
+    reg [127:0] bigRegister;
     always_comb begin
         out = in1 + in2;
     end
diff --git a/test_regress/t/t_instrument_bad.out b/test_regress/t/t_instrument_bad.out
deleted file mode 100644
index 136d06384..000000000
--- a/test_regress/t/t_instrument_bad.out
+++ /dev/null
@@ -1 +0,0 @@
-  
\ No newline at end of file
diff --git a/test_regress/t/t_instrument_bad1.out b/test_regress/t/t_instrument_bad1.out
new file mode 100644
index 000000000..e228e30a1
--- /dev/null
+++ b/test_regress/t/t_instrument_bad1.out
@@ -0,0 +1,2 @@
+%Error: In .vlt defined target tries to instrument the highest MODULE, is not possible! ... Target string: top_module.outa
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
diff --git a/test_regress/t/t_instrument_bad.py b/test_regress/t/t_instrument_bad1.py
similarity index 54%
rename from test_regress/t/t_instrument_bad.py
rename to test_regress/t/t_instrument_bad1.py
index c372b22fd..e16d792f7 100755
--- a/test_regress/t/t_instrument_bad.py
+++ b/test_regress/t/t_instrument_bad1.py
@@ -9,10 +9,16 @@
 
 import vltest_bootstrap
 
-test.scenarios('linter')
+test.scenarios('simulator')
 test.top_filename = "t/t_instrument.v"
-test.flag = "--instrument"
 
-test.lint(fails=True, expect_filename=test.golden_filename)
+sim_filename = "t/t_instrument.cpp"
+dpi_filename = "t/t_instrumentDPI.cpp"
+vlt_filename = "t/" + test.name + ".vlt"
 
-test.passes()
\ No newline at end of file
+test.compile(fails=True, make_top_shell=False,
+    make_main=False,
+    v_flags2=["--trace --timing --exe --instrument", sim_filename, vlt_filename, dpi_filename],
+    expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_instrument_bad1.vlt b/test_regress/t/t_instrument_bad1.vlt
new file mode 100644
index 000000000..2a34c9bd0
--- /dev/null
+++ b/test_regress/t/t_instrument_bad1.vlt
@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+instrument -callback "instrument_var" -id 0 -target "top_module.outa"
diff --git a/test_regress/t/t_instrument_bad2.out b/test_regress/t/t_instrument_bad2.out
new file mode 100644
index 000000000..9b6c5cc9f
--- /dev/null
+++ b/test_regress/t/t_instrument_bad2.out
@@ -0,0 +1,12 @@
+%Error: Verilator-configfile': could not find initial 'module' in 'module.instance.__' ... Target: 'top.a1.b1'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Verilator-configfile: target variable 'bigRegister' in 'top_module.a1.b1' must be a supported type!
+%Error: Verilator-configfile': could not find defined 'var' in 'topModule.instance.var' ... Target string: 'top_module.a1.b1.clk'
+%Error: Verilator-configfile': could not find '.var' in '__.module.var' ... Target: 'top_module.a1.b1'
+%Error: Verilator-configfile: could not find 'instance' in '__.instance.__' ... Target string: 'top_module.a1.b3'
+%Error: Verilator-configfile': could not find initial 'instance' in 'topModule.instance.__' ... Target string: 'top_module.a3.b1'
+%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top.a1.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
+%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a1.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
+%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a1.b3'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
+%Error: Verilator-configfile: Incomplete instrumentation configuration for target 'top_module.a3.b1'. Please check previous Errors from V3Instrument:findTargets and ensure all necessary components are correct defined.
+%Error: Exiting due to
diff --git a/test_regress/t/t_instrument_bad2.py b/test_regress/t/t_instrument_bad2.py
new file mode 100755
index 000000000..e16d792f7
--- /dev/null
+++ b/test_regress/t/t_instrument_bad2.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_instrument.v"
+
+sim_filename = "t/t_instrument.cpp"
+dpi_filename = "t/t_instrumentDPI.cpp"
+vlt_filename = "t/" + test.name + ".vlt"
+
+test.compile(fails=True, make_top_shell=False,
+    make_main=False,
+    v_flags2=["--trace --timing --exe --instrument", sim_filename, vlt_filename, dpi_filename],
+    expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_instrument_bad.vlt b/test_regress/t/t_instrument_bad2.vlt
similarity index 96%
rename from test_regress/t/t_instrument_bad.vlt
rename to test_regress/t/t_instrument_bad2.vlt
index 1fd81f390..cad5d1bfe 100644
--- a/test_regress/t/t_instrument_bad.vlt
+++ b/test_regress/t/t_instrument_bad2.vlt
@@ -6,8 +6,6 @@
 
 `verilator_config
 
-instrument -callback "instrument_var" -id 0 -target "top_module.outa"
-
 instrument -callback "instrument_var" -id 0 -target "top.a1.b1.out"
 
 instrument -callback "instrument_var" -id 0 -target "top_module.a3.b1.out"
@@ -15,3 +13,5 @@ instrument -callback "instrument_var" -id 0 -target "top_module.a3.b1.out"
 instrument -callback "instrument_var" -id 0 -target "top_module.a1.b3.out"
 
 instrument -callback "instrument_var" -id 0 -target "top_module.a1.b1.clk"
+
+instrument -callback "instrument_var" -id 0 -target "top_module.a1.b1.bigRegister"