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Tests: Backward port from threads branch.

This commit is contained in:
Wilson Snyder 2018-06-15 06:28:33 -04:00
parent efb2801eeb
commit 35654b5355
4 changed files with 20 additions and 19 deletions
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2
test_regress/t/t_detectarray_1.pl
View File

@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
verilator_flags2 => ["-Wno-CLKDATA"]
verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"]
);
execute(

2
test_regress/t/t_detectarray_2.pl
View File

@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
verilator_flags2 => ["-Wno-CLKDATA"]
verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"]
);
execute(

14
test_regress/t/t_order_clkinst.pl
View File

@ -9,15 +9,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
# On Verilator, we expect this to pass.
#
# TBD: Will event-based simulators match Verilator's behavior
# closely enough to pass the same test?
# If not -- probably we should switch this to be vlt-only.
compile(
);
compile();
execute(
check_finished => !$fail,
fails => $fail,
);
execute(check_finished => 1);
ok(1);
1;

21
test_regress/t/t_order_clkinst.v
View File

@ -12,12 +12,13 @@ module t (/*AUTOARG*/
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off BLKANDNBLK
reg c1_start; initial c1_start = 0;
wire [31:0] c1_count;
comb_loop c1 (.count(c1_count), .start(c1_start));
wire s2_start = (c1_count==0 && c1_start);
wire s2_start = c1_start;
wire [31:0] s2_count;
seq_loop s2 (.count(s2_count), .start(s2_start));
@ -40,9 +41,13 @@ module t (/*AUTOARG*/
endcase
case (cyc)
8'd02: begin
// On Verilator, we expect these comparisons to match exactly,
// confirming that our settle loop repeated the exact number of
// iterations we expect. No '$stop' should be called here, and we
// should reach the normal '$finish' below on the next cycle.
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h6) $stop;
if (c3_count!=32'h5) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
@ -64,10 +69,8 @@ module comb_loop (/*AUTOARG*/
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner = 3;
end
always @ (posedge start) begin
runner = 3;
end
always @ (/*AS*/runner) begin
@ -95,10 +98,8 @@ module seq_loop (/*AUTOARG*/
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner <= 3;
end
always @ (posedge start) begin
runner <= 3;
end
always @ (/*AS*/runner) begin