From 35654b53558c0cb3c9ceb90c33fea5ced3c055c3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 15 Jun 2018 06:28:33 -0400
Subject: [PATCH] Tests: Backward port from threads branch.

---
 test_regress/t/t_detectarray_1.pl |  2 +-
 test_regress/t/t_detectarray_2.pl |  2 +-
 test_regress/t/t_order_clkinst.pl | 14 +++++++-------
 test_regress/t/t_order_clkinst.v  | 21 +++++++++++----------
 4 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/test_regress/t/t_detectarray_1.pl b/test_regress/t/t_detectarray_1.pl
index 0a3b50107..97d65733b 100755
--- a/test_regress/t/t_detectarray_1.pl
+++ b/test_regress/t/t_detectarray_1.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    verilator_flags2 => ["-Wno-CLKDATA"]
+    verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"]
     );
 
 execute(
diff --git a/test_regress/t/t_detectarray_2.pl b/test_regress/t/t_detectarray_2.pl
index 0a3b50107..97d65733b 100755
--- a/test_regress/t/t_detectarray_2.pl
+++ b/test_regress/t/t_detectarray_2.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    verilator_flags2 => ["-Wno-CLKDATA"]
+    verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"]
     );
 
 execute(
diff --git a/test_regress/t/t_order_clkinst.pl b/test_regress/t/t_order_clkinst.pl
index 1bb3331e9..d151aacb9 100755
--- a/test_regress/t/t_order_clkinst.pl
+++ b/test_regress/t/t_order_clkinst.pl
@@ -9,15 +9,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
+# On Verilator, we expect this to pass.
+#
+# TBD: Will event-based simulators match Verilator's behavior
+# closely enough to pass the same test?
+# If not -- probably we should switch this to be vlt-only.
 
-compile(
-    );
+compile();
 
-execute(
-    check_finished => !$fail,
-    fails => $fail,
-    );
+execute(check_finished => 1);
 
 ok(1);
 1;
diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v
index ea2428e84..92f873c9a 100644
--- a/test_regress/t/t_order_clkinst.v
+++ b/test_regress/t/t_order_clkinst.v
@@ -12,12 +12,13 @@ module t (/*AUTOARG*/
    // verilator lint_off COMBDLY
    // verilator lint_off UNOPT
    // verilator lint_off UNOPTFLAT
+   // verilator lint_off BLKANDNBLK
 
    reg 	       c1_start; initial c1_start = 0;
    wire [31:0] c1_count;
    comb_loop c1 (.count(c1_count), .start(c1_start));
 
-   wire        s2_start = (c1_count==0 && c1_start);
+   wire        s2_start = c1_start;
    wire [31:0] s2_count;
    seq_loop  s2 (.count(s2_count), .start(s2_start));
 
@@ -40,9 +41,13 @@ module t (/*AUTOARG*/
       endcase
       case (cyc)
 	8'd02: begin
+           // On Verilator, we expect these comparisons to match exactly,
+           // confirming that our settle loop repeated the exact number of
+           // iterations we expect. No '$stop' should be called here, and we
+           // should reach the normal '$finish' below on the next cycle.
 	   if (c1_count!=32'h3) $stop;
 	   if (s2_count!=32'h3) $stop;
-	   if (c3_count!=32'h6) $stop;
+           if (c3_count!=32'h5) $stop;
 	end
 	8'd03: begin
 	   $write("*-* All Finished *-*\n");
@@ -64,10 +69,8 @@ module comb_loop (/*AUTOARG*/
 
    reg [31:0] 	 runnerm1, runner; initial runner = 0;
 
-   always @ (start) begin
-      if (start) begin
-	 runner = 3;
-      end
+   always @ (posedge start) begin
+      runner = 3;
    end
 
    always @ (/*AS*/runner) begin
@@ -95,10 +98,8 @@ module seq_loop (/*AUTOARG*/
 
    reg [31:0] 	 runnerm1, runner; initial runner = 0;
 
-   always @ (start) begin
-      if (start) begin
-	 runner <= 3;
-      end
+   always @ (posedge start) begin
+      runner <= 3;
    end
 
    always @ (/*AS*/runner) begin