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test: Add regression tests for instrumentation

This commit is contained in:
Jonathan Schröter 2025-10-01 13:05:02 +02:00
parent 5f2cb6545a
commit 300001bcdd
6 changed files with 244 additions and 0 deletions
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42
test_regress/t/t_instrumentation.cpp Normal file
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// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <fstream>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::commandArgs(argc, argv);
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
std::ofstream logFile("obj_vlt/t_instrumentation/simulation_output.log");
if (!logFile.is_open()) {
printf("Error: Could not open log file\n");
return 1;
}
while (main_time <= 100) {
top->eval();
logFile << "$time: " << main_time << " | "
<< "Output outa: " << static_cast<int>(top->outa) << " | "
<< "Output outb: " << static_cast<int>(top->outb) << std::endl;
++main_time;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

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test_regress/t/t_instrumentation.out Normal file
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$time: 0 | Output outa: 0 | Output outb: 50
$time: 1 | Output outa: 0 | Output outb: 50
$time: 2 | Output outa: 0 | Output outb: 50
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$time: 99 | Output outa: 0 | Output outb: 50
$time: 100 | Output outa: 0 | Output outb: 50

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test_regress/t/t_instrumentation.py Executable file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_instrumentation.v"
sim_filename = "t/" + test.name + ".cpp"
dpi_filename = "t/t_instrumentationDPI.cpp"
vlt_filename = "t/" + test.name + ".vlt"
log_filename = "obj_vlt/t_instrumentation/simulation_output.log"
test.compile(make_top_shell=False,
make_main=False,
v_flags2=["--trace --exe --instrument", sim_filename, vlt_filename, dpi_filename])
test.execute()
test.files_identical(log_filename, test.golden_filename)
test.passes()

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test_regress/t/t_instrumentation.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module top_module(
output logic [7:0] outa,
output logic [7:0] outb
);
logic [7:0] in1a = 8'd5;
logic [7:0] in2a = 8'd10;
logic [7:0] in1b = 8'd20;
logic [7:0] in2b = 8'd30;
module_a a1 (.in1(in1a), .in2(in2a), .out(outa));
module_a a2 (.in1(in1b), .in2(in2b), .out(outb));
endmodule
module module_a(
input logic [7:0] in1,
input logic [7:0] in2,
output logic [7:0] out
);
module_b b1 (.in1(in1), .in2(in2), .out(out));
endmodule
module module_b (
input logic [7:0] in1,
input logic [7:0] in2,
output logic [7:0] out
);
always_comb begin
out = in1 + in2;
end
endmodule

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test_regress/t/t_instrumentation.vlt Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`verilator_config
instrument -model "instrument_var" -id 0 -target "top_module.a1.b1.out"

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test_regress/t/t_instrumentationDPI.cpp Normal file
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// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <iostream>
#include <svdpi.h>
extern "C" short instrument_var(int id, const svLogic *x) {
switch (id)
{
case 0:
return 0;
case 1:
// Stuck at 1 Fault Injection
return 1;
case 2:
// Inverter/Bit flip Fault injection (provisional)
return !x;
default:
return *x;
}
}