From 300001bcdd0ac77cc94c52eea6dba25cf8f60c6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Schr=C3=B6ter?= Date: Wed, 1 Oct 2025 13:05:02 +0200 Subject: [PATCH] test: Add regression tests for instrumentation --- test_regress/t/t_instrumentation.cpp | 42 ++++++++++ test_regress/t/t_instrumentation.out | 101 ++++++++++++++++++++++++ test_regress/t/t_instrumentation.py | 27 +++++++ test_regress/t/t_instrumentation.v | 37 +++++++++ test_regress/t/t_instrumentation.vlt | 9 +++ test_regress/t/t_instrumentationDPI.cpp | 28 +++++++ 6 files changed, 244 insertions(+) create mode 100644 test_regress/t/t_instrumentation.cpp create mode 100644 test_regress/t/t_instrumentation.out create mode 100755 test_regress/t/t_instrumentation.py create mode 100644 test_regress/t/t_instrumentation.v create mode 100644 test_regress/t/t_instrumentation.vlt create mode 100644 test_regress/t/t_instrumentationDPI.cpp diff --git a/test_regress/t/t_instrumentation.cpp b/test_regress/t/t_instrumentation.cpp new file mode 100644 index 000000000..d88813e15 --- /dev/null +++ b/test_regress/t/t_instrumentation.cpp @@ -0,0 +1,42 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::commandArgs(argc, argv); + + std::unique_ptr top{new VM_PREFIX{"top"}}; + + std::ofstream logFile("obj_vlt/t_instrumentation/simulation_output.log"); + if (!logFile.is_open()) { + printf("Error: Could not open log file\n"); + return 1; + } + + while (main_time <= 100) { + top->eval(); + logFile << "$time: " << main_time << " | " + << "Output outa: " << static_cast(top->outa) << " | " + << "Output outb: " << static_cast(top->outb) << std::endl; + ++main_time; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_instrumentation.out b/test_regress/t/t_instrumentation.out new file mode 100644 index 000000000..7ba39071f --- /dev/null +++ b/test_regress/t/t_instrumentation.out @@ -0,0 +1,101 @@ +$time: 0 | Output outa: 0 | Output outb: 50 +$time: 1 | Output outa: 0 | Output outb: 50 +$time: 2 | Output outa: 0 | Output outb: 50 +$time: 3 | Output outa: 0 | Output outb: 50 +$time: 4 | Output outa: 0 | Output outb: 50 +$time: 5 | Output outa: 0 | Output outb: 50 +$time: 6 | Output outa: 0 | Output outb: 50 +$time: 7 | Output outa: 0 | Output outb: 50 +$time: 8 | Output outa: 0 | Output outb: 50 +$time: 9 | Output outa: 0 | Output outb: 50 +$time: 10 | Output outa: 0 | Output outb: 50 +$time: 11 | Output outa: 0 | Output outb: 50 +$time: 12 | Output outa: 0 | Output outb: 50 +$time: 13 | Output outa: 0 | Output outb: 50 +$time: 14 | Output outa: 0 | Output outb: 50 +$time: 15 | Output outa: 0 | Output outb: 50 +$time: 16 | Output outa: 0 | Output outb: 50 +$time: 17 | Output outa: 0 | Output outb: 50 +$time: 18 | Output outa: 0 | Output outb: 50 +$time: 19 | Output outa: 0 | Output outb: 50 +$time: 20 | Output outa: 0 | Output outb: 50 +$time: 21 | Output outa: 0 | Output outb: 50 +$time: 22 | Output outa: 0 | Output outb: 50 +$time: 23 | Output outa: 0 | Output outb: 50 +$time: 24 | Output outa: 0 | Output outb: 50 +$time: 25 | Output outa: 0 | Output outb: 50 +$time: 26 | Output outa: 0 | Output outb: 50 +$time: 27 | Output outa: 0 | Output outb: 50 +$time: 28 | Output outa: 0 | Output outb: 50 +$time: 29 | Output outa: 0 | Output outb: 50 +$time: 30 | Output outa: 0 | Output outb: 50 +$time: 31 | Output outa: 0 | Output outb: 50 +$time: 32 | Output outa: 0 | Output outb: 50 +$time: 33 | Output outa: 0 | Output outb: 50 +$time: 34 | Output outa: 0 | Output outb: 50 +$time: 35 | Output outa: 0 | Output outb: 50 +$time: 36 | Output outa: 0 | Output outb: 50 +$time: 37 | Output outa: 0 | Output outb: 50 +$time: 38 | Output outa: 0 | Output outb: 50 +$time: 39 | Output outa: 0 | Output outb: 50 +$time: 40 | Output outa: 0 | Output outb: 50 +$time: 41 | Output outa: 0 | Output outb: 50 +$time: 42 | Output outa: 0 | Output outb: 50 +$time: 43 | Output outa: 0 | Output outb: 50 +$time: 44 | Output outa: 0 | Output outb: 50 +$time: 45 | Output outa: 0 | Output outb: 50 +$time: 46 | Output outa: 0 | Output outb: 50 +$time: 47 | Output outa: 0 | Output outb: 50 +$time: 48 | Output outa: 0 | Output outb: 50 +$time: 49 | Output outa: 0 | Output outb: 50 +$time: 50 | Output outa: 0 | Output outb: 50 +$time: 51 | Output outa: 0 | Output outb: 50 +$time: 52 | Output outa: 0 | Output outb: 50 +$time: 53 | Output outa: 0 | Output outb: 50 +$time: 54 | Output outa: 0 | Output outb: 50 +$time: 55 | Output outa: 0 | Output outb: 50 +$time: 56 | Output outa: 0 | Output outb: 50 +$time: 57 | Output outa: 0 | Output outb: 50 +$time: 58 | Output outa: 0 | Output outb: 50 +$time: 59 | Output outa: 0 | Output outb: 50 +$time: 60 | Output outa: 0 | Output outb: 50 +$time: 61 | Output outa: 0 | Output outb: 50 +$time: 62 | Output outa: 0 | Output outb: 50 +$time: 63 | Output outa: 0 | Output outb: 50 +$time: 64 | Output outa: 0 | Output outb: 50 +$time: 65 | Output outa: 0 | Output outb: 50 +$time: 66 | Output outa: 0 | Output outb: 50 +$time: 67 | Output outa: 0 | Output outb: 50 +$time: 68 | Output outa: 0 | Output outb: 50 +$time: 69 | Output outa: 0 | Output outb: 50 +$time: 70 | Output outa: 0 | Output outb: 50 +$time: 71 | Output outa: 0 | Output outb: 50 +$time: 72 | Output outa: 0 | Output outb: 50 +$time: 73 | Output outa: 0 | Output outb: 50 +$time: 74 | Output outa: 0 | Output outb: 50 +$time: 75 | Output outa: 0 | Output outb: 50 +$time: 76 | Output outa: 0 | Output outb: 50 +$time: 77 | Output outa: 0 | Output outb: 50 +$time: 78 | Output outa: 0 | Output outb: 50 +$time: 79 | Output outa: 0 | Output outb: 50 +$time: 80 | Output outa: 0 | Output outb: 50 +$time: 81 | Output outa: 0 | Output outb: 50 +$time: 82 | Output outa: 0 | Output outb: 50 +$time: 83 | Output outa: 0 | Output outb: 50 +$time: 84 | Output outa: 0 | Output outb: 50 +$time: 85 | Output outa: 0 | Output outb: 50 +$time: 86 | Output outa: 0 | Output outb: 50 +$time: 87 | Output outa: 0 | Output outb: 50 +$time: 88 | Output outa: 0 | Output outb: 50 +$time: 89 | Output outa: 0 | Output outb: 50 +$time: 90 | Output outa: 0 | Output outb: 50 +$time: 91 | Output outa: 0 | Output outb: 50 +$time: 92 | Output outa: 0 | Output outb: 50 +$time: 93 | Output outa: 0 | Output outb: 50 +$time: 94 | Output outa: 0 | Output outb: 50 +$time: 95 | Output outa: 0 | Output outb: 50 +$time: 96 | Output outa: 0 | Output outb: 50 +$time: 97 | Output outa: 0 | Output outb: 50 +$time: 98 | Output outa: 0 | Output outb: 50 +$time: 99 | Output outa: 0 | Output outb: 50 +$time: 100 | Output outa: 0 | Output outb: 50 diff --git a/test_regress/t/t_instrumentation.py b/test_regress/t/t_instrumentation.py new file mode 100755 index 000000000..83bcaed16 --- /dev/null +++ b/test_regress/t/t_instrumentation.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_instrumentation.v" + +sim_filename = "t/" + test.name + ".cpp" +dpi_filename = "t/t_instrumentationDPI.cpp" +vlt_filename = "t/" + test.name + ".vlt" +log_filename = "obj_vlt/t_instrumentation/simulation_output.log" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace --exe --instrument", sim_filename, vlt_filename, dpi_filename]) +test.execute() + +test.files_identical(log_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_instrumentation.v b/test_regress/t/t_instrumentation.v new file mode 100644 index 000000000..674f8293e --- /dev/null +++ b/test_regress/t/t_instrumentation.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module top_module( + output logic [7:0] outa, + output logic [7:0] outb +); + logic [7:0] in1a = 8'd5; + logic [7:0] in2a = 8'd10; + + logic [7:0] in1b = 8'd20; + logic [7:0] in2b = 8'd30; + + module_a a1 (.in1(in1a), .in2(in2a), .out(outa)); + module_a a2 (.in1(in1b), .in2(in2b), .out(outb)); +endmodule + +module module_a( + input logic [7:0] in1, + input logic [7:0] in2, + output logic [7:0] out +); + module_b b1 (.in1(in1), .in2(in2), .out(out)); +endmodule + +module module_b ( + input logic [7:0] in1, + input logic [7:0] in2, + output logic [7:0] out +); + always_comb begin + out = in1 + in2; + end +endmodule diff --git a/test_regress/t/t_instrumentation.vlt b/test_regress/t/t_instrumentation.vlt new file mode 100644 index 000000000..e96535c09 --- /dev/null +++ b/test_regress/t/t_instrumentation.vlt @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +instrument -model "instrument_var" -id 0 -target "top_module.a1.b1.out" diff --git a/test_regress/t/t_instrumentationDPI.cpp b/test_regress/t/t_instrumentationDPI.cpp new file mode 100644 index 000000000..d74027ab9 --- /dev/null +++ b/test_regress/t/t_instrumentationDPI.cpp @@ -0,0 +1,28 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include +#include + +extern "C" short instrument_var(int id, const svLogic *x) { + switch (id) + { + case 0: + return 0; + case 1: + // Stuck at 1 Fault Injection + return 1; + case 2: + // Inverter/Bit flip Fault injection (provisional) + return !x; + default: + return *x; + } +}