Merge from master

Changes

@@ -12,6 +12,10 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix internals to avoid 'using namespace std'.
 
+****  Report interface ports connected to wrong interface, bug1294. [Todd Strader]
+
+****  Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
+
 
 * Verilator 3.922 2018-03-17
 

bin/verilator

@@ -1062,7 +1062,7 @@ block or wire statement.  (Note this will slow down the executable by ~5%.)
 Furthermore, the function name will be suffixed with the basename of the
 Verilog module and line number the statement came from.  This allows gprof
 or oprofile reports to be correlated with the original Verilog source
-statements.
+statements. See also L<verilator_profcfunc>.
 
 =item --private
 

bin/verilator_profcfunc

@@ -73,6 +73,14 @@ sub profcfunc {
 	    $funcs{$func}{sec} += $sec;
 	    $funcs{$func}{calls} += $calls;
 	}
+        # Older gprofs have no call column for single-call functions
+        #                  %time      cumesec   selfsec      {stuff}   name
+        elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
+            my $pct=$1; my $sec=$2; my $calls=1; my $func=$3;
+            $funcs{$func}{pct} += $pct;
+            $funcs{$func}{sec} += $sec;
+            $funcs{$func}{calls} += $calls;
+        }
     }
     $fh->close;
 

src/V3LifePost.cpp

@@ -110,7 +110,7 @@ class LifePostDlyVisitor : public LifePostBaseVisitor {
 private:
     // NODE STATE
     // Cleared on entire tree
-    //  AstVarScope::user()	-> Sequence # of first virtex setting this var.
+    //  AstVarScope::user()     -> Sequence # of first vertex setting this var.
     //  AstVarScope::user2()	-> Sequence # of last consumption of this var
     //  AstVarScope::user4()	-> AstVarScope*: Passed to LifePostElim to substitute this var
     AstUser1InUse	m_inuser1;

src/V3Param.cpp

@@ -652,6 +652,14 @@ void ParamVisitor::visitCell(AstCell* nodep) {
 			longname += "_" + paramSmallName(srcModp, pinp->modVarp()) + paramValueNumber(pinIrefp);
 			any_overrides = true;
 			ifaceRefRefs.push_back(make_pair(portIrefp,pinIrefp));
+                        if (portIrefp->ifacep() != pinIrefp->ifacep()
+                            // Might be different only due to param cloning, so check names too
+                            && portIrefp->ifaceName() != pinIrefp->ifaceName()) {
+                            pinp->v3error("Port '"<<pinp->prettyName()<<"' expects '"
+                                          <<AstNode::prettyName(portIrefp->ifaceName())
+                                          <<"' interface but pin connects '"
+                                          <<AstNode::prettyName(pinIrefp->ifaceName())<<"' interface");
+                        }
 		    }
 		}
 	    }

src/V3String.cpp

@@ -220,7 +220,8 @@ uint64_t VHashSha1::digestUInt64() {
     const string& binhash = digestBinary();
     uint64_t out = 0;
     for (size_t byte=0; byte<sizeof(uint64_t); ++byte) {
-	out = (out<<8) | binhash[byte];
+        unsigned char c = binhash[byte];
+        out = (out<<8) | c;
     }
     return out;
 }

src/verilog.y

@@ -948,6 +948,8 @@ port<nodep>:			// ==IEEE: port
 			{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
 	|	portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
 			{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
+	|	portDirNetE signing             portSig variable_dimensionListE sigAttrListE
+			{ $$=$3; VARDTYPE(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2)); $$->addNextNull(VARDONEP($$,$4,$5)); }
 	|	portDirNetE signingE rangeList  portSig variable_dimensionListE sigAttrListE
 			{ $$=$4; VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2), $3,true)); $$->addNextNull(VARDONEP($$,$5,$6)); }
 	|	portDirNetE /*implicit*/        portSig variable_dimensionListE sigAttrListE

test_regress/t/t_inst_signed1.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_signed1.v

@@ -0,0 +1,51 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   reg signed i;
+   wire signed o1;
+   wire signed o2;
+
+   integer cyc; initial cyc=0;
+
+   sub1 sub1 (.i(i), .o(o1));
+   sub2 sub2 (.i(o1), .o(o2));
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+         i <= 1'b0;
+      end
+      else if (cyc==1) begin
+         if (o2 != 1'b0) $stop;
+         i <= 1'b1;
+      end
+      else if (cyc==2) begin
+         if (o2 != 1'b1) $stop;
+      end
+      if (cyc==3) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
+
+//msg2540
+module sub1 (
+             input signed  i,
+             output signed o);
+   wire signed o = ~i;
+endmodule
+
+module sub2 (i,o);
+   input signed  i;
+   output signed o;
+   wire signed o = ~i;
+endmodule

test_regress/t/t_interface_wrong_bad.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    fails=>1,
+    expect =>
+q{%Error: t/t_interface_wrong_bad.v:\d+: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface},
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_wrong_bad.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap
+// should cause an error
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Todd Strader.
+
+interface foo_intf;
+   logic [7:0] a;
+endinterface
+
+interface bar_intf;
+   logic [7:0] a;
+endinterface
+
+module foo_mod (foo_intf foo_port);
+//  initial begin
+//      $display("a = %0d", foo_port.a);
+//  end
+endmodule
+
+module t (/*AUTOARG*/);
+
+   foo_intf foo ();
+   bar_intf bar ();
+
+//   assign foo.a = 8'd1;
+//   assign bar.a = 8'd2;
+
+   foo_mod
+   foo_mod (
+      .foo_port (bar)
+   );
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_sys_sformat_noopt.pl

@@ -14,7 +14,8 @@ compile (
     verilator_flags2 => ["-O0"],
     );
 
-if ($Self->cxx_version =~ /clang version 3.8/) {
+if ($Self->cxx_version =~ /clang version ([0-9]+\.[0-9]+)/
+    && ($1 >= 3.8 && $1 <= 5.0)) {
     $Self->skip("Known clang bug");
     #Here:   if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str)))
 } else{