From c7c99d8553c64e08711c7ae861582c2202bae3f4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 29 Mar 2018 20:10:27 -0400 Subject: [PATCH 1/4] Fix parsing "output signed" in V2K port list, msg2540. --- Changes | 2 ++ src/verilog.y | 2 ++ test_regress/t/t_inst_signed1.pl | 18 +++++++++++ test_regress/t/t_inst_signed1.v | 51 ++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100755 test_regress/t/t_inst_signed1.pl create mode 100644 test_regress/t/t_inst_signed1.v diff --git a/Changes b/Changes index bb75e3ea9..b0a38c614 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.923 devel +**** Fix parsing "output signed" in V2K port list, msg2540. [James Jung] + * Verilator 3.922 2018-03-17 diff --git a/src/verilog.y b/src/verilog.y index d30a5e484..ab1bc264d 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -948,6 +948,8 @@ port: // ==IEEE: port { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } | portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } + | portDirNetE signing portSig variable_dimensionListE sigAttrListE + { $$=$3; VARDTYPE(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2)); $$->addNextNull(VARDONEP($$,$4,$5)); } | portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE { $$=$4; VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2), $3,true)); $$->addNextNull(VARDONEP($$,$5,$6)); } | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE diff --git a/test_regress/t/t_inst_signed1.pl b/test_regress/t/t_inst_signed1.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_inst_signed1.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_inst_signed1.v b/test_regress/t/t_inst_signed1.v new file mode 100644 index 000000000..69fe5da63 --- /dev/null +++ b/test_regress/t/t_inst_signed1.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg signed i; + wire signed o1; + wire signed o2; + + integer cyc; initial cyc=0; + + sub1 sub1 (.i(i), .o(o1)); + sub2 sub2 (.i(o1), .o(o2)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + i <= 1'b0; + end + else if (cyc==1) begin + if (o2 != 1'b0) $stop; + i <= 1'b1; + end + else if (cyc==2) begin + if (o2 != 1'b1) $stop; + end + if (cyc==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +//msg2540 +module sub1 ( + input signed i, + output signed o); + wire signed o = ~i; +endmodule + +module sub2 (i,o); + input signed i; + output signed o; + wire signed o = ~i; +endmodule From 9219ddaece55ce26340ab7cdca9e36b4e448a41f Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Wed, 4 Apr 2018 21:03:43 -0400 Subject: [PATCH 2/4] Report interface ports connected to wrong interface, bug1294. --- Changes | 2 ++ src/V3Param.cpp | 8 +++++ test_regress/t/t_interface_wrong_bad.pl | 17 +++++++++++ test_regress/t/t_interface_wrong_bad.v | 39 +++++++++++++++++++++++++ 4 files changed, 66 insertions(+) create mode 100755 test_regress/t/t_interface_wrong_bad.pl create mode 100644 test_regress/t/t_interface_wrong_bad.v diff --git a/Changes b/Changes index b0a38c614..de8932d59 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.923 devel +**** Report interface ports connected to wrong interface, bug1294. [Todd Strader] + **** Fix parsing "output signed" in V2K port list, msg2540. [James Jung] diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 12f27b179..adbbcc93e 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -652,6 +652,14 @@ void ParamVisitor::visitCell(AstCell* nodep) { longname += "_" + paramSmallName(srcModp, pinp->modVarp()) + paramValueNumber(pinIrefp); any_overrides = true; ifaceRefRefs.push_back(make_pair(portIrefp,pinIrefp)); + if (portIrefp->ifacep() != pinIrefp->ifacep() + // Might be different only due to param cloning, so check names too + && portIrefp->ifaceName() != pinIrefp->ifaceName()) { + pinp->v3error("Port '"<prettyName()<<"' expects '" + <ifaceName()) + <<"' interface but pin connects '" + <ifaceName())<<"' interface"); + } } } } diff --git a/test_regress/t/t_interface_wrong_bad.pl b/test_regress/t/t_interface_wrong_bad.pl new file mode 100755 index 000000000..c773241b2 --- /dev/null +++ b/test_regress/t/t_interface_wrong_bad.pl @@ -0,0 +1,17 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + fails=>1, + expect => +q{%Error: t/t_interface_wrong_bad.v:\d+: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_wrong_bad.v b/test_regress/t/t_interface_wrong_bad.v new file mode 100644 index 000000000..233b9a656 --- /dev/null +++ b/test_regress/t/t_interface_wrong_bad.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap +// should cause an error +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Todd Strader. + +interface foo_intf; + logic [7:0] a; +endinterface + +interface bar_intf; + logic [7:0] a; +endinterface + +module foo_mod (foo_intf foo_port); +// initial begin +// $display("a = %0d", foo_port.a); +// end +endmodule + +module t (/*AUTOARG*/); + + foo_intf foo (); + bar_intf bar (); + +// assign foo.a = 8'd1; +// assign bar.a = 8'd2; + + foo_mod + foo_mod ( + .foo_port (bar) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule From a46aa2d62b78e50050191f16d1b6e24520cae149 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 10 Apr 2018 22:05:17 -0400 Subject: [PATCH 3/4] Fix verilator_profcfunc on old gprofs. --- bin/verilator | 2 +- bin/verilator_profcfunc | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/bin/verilator b/bin/verilator index 7cbe723f9..901a9f0e3 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1062,7 +1062,7 @@ block or wire statement. (Note this will slow down the executable by ~5%.) Furthermore, the function name will be suffixed with the basename of the Verilog module and line number the statement came from. This allows gprof or oprofile reports to be correlated with the original Verilog source -statements. +statements. See also L. =item --private diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 808b36d7d..3856c2401 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -73,6 +73,14 @@ sub profcfunc { $funcs{$func}{sec} += $sec; $funcs{$func}{calls} += $calls; } + # Older gprofs have no call column for single-call functions + # %time cumesec selfsec {stuff} name + elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) { + my $pct=$1; my $sec=$2; my $calls=1; my $func=$3; + $funcs{$func}{pct} += $pct; + $funcs{$func}{sec} += $sec; + $funcs{$func}{calls} += $calls; + } } $fh->close; From 767ac2547d63009a7f0117af4a9afd760a156748 Mon Sep 17 00:00:00 2001 From: John Coiner Date: Tue, 10 Apr 2018 22:05:55 -0400 Subject: [PATCH 4/4] Misc clang warning fixes. Signed-off-by: Wilson Snyder --- src/V3LifePost.cpp | 2 +- src/V3String.cpp | 3 ++- test_regress/t/t_sys_sformat_noopt.pl | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 10c69396c..c5e37af8a 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -110,7 +110,7 @@ class LifePostDlyVisitor : public LifePostBaseVisitor { private: // NODE STATE // Cleared on entire tree - // AstVarScope::user() -> Sequence # of first virtex setting this var. + // AstVarScope::user() -> Sequence # of first vertex setting this var. // AstVarScope::user2() -> Sequence # of last consumption of this var // AstVarScope::user4() -> AstVarScope*: Passed to LifePostElim to substitute this var AstUser1InUse m_inuser1; diff --git a/src/V3String.cpp b/src/V3String.cpp index 4562ca9f8..ab06bc4d5 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -220,7 +220,8 @@ uint64_t VHashSha1::digestUInt64() { const string& binhash = digestBinary(); uint64_t out = 0; for (size_t byte=0; byte ["-O0"], ); -if ($Self->cxx_version =~ /clang version 3.8/) { +if ($Self->cxx_version =~ /clang version ([0-9]+\.[0-9]+)/ + && ($1 >= 3.8 && $1 <= 5.0)) { $Self->skip("Known clang bug"); #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) } else{