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Tests: Use top. instead of TOP. to match other sims

This commit is contained in:
Wilson Snyder 2009-12-05 09:58:09 -05:00
parent a3c1724d17
commit 2dc7b7ad78
15 changed files with 47 additions and 51 deletions
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2
test_regress/driver.pl
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@ -747,7 +747,7 @@ sub _make_main {
print $fh " Verilated::commandArgs(argc, argv);\n"; print $fh " Verilated::commandArgs(argc, argv);\n";
print $fh " Verilated::debug(".($self->{verilated_debug}?1:0).");\n"; print $fh " Verilated::debug(".($self->{verilated_debug}?1:0).");\n";
print $fh " Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset}; print $fh " Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset};
print $fh " topp = new $VM_PREFIX (\"TOP\");\n"; print $fh " topp = new $VM_PREFIX (\"top\");\n";
my $set; my $set;
if ($self->sp) { if ($self->sp) {
print $fh " SP_PIN(topp,fastclk,fastclk);\n" if $self->{inputs}{fastclk}; print $fh " SP_PIN(topp,fastclk,fastclk);\n" if $self->{inputs}{fastclk};

2
test_regress/t/t_assert_synth_full.pl
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@ -18,7 +18,7 @@ execute (
check_finished=>0, check_finished=>0,
fails=>1, fails=>1,
expect=> expect=>
'%Error: t_assert_synth.v:\d+: Assertion failed in TOP.v: synthesis full_case' '%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis full_case'
); );
ok(1); ok(1);

2
test_regress/t/t_assert_synth_parallel.pl
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@ -18,7 +18,7 @@ execute (
check_finished=>0, check_finished=>0,
fails=>1, fails=>1,
expect=> expect=>
'%Error: t_assert_synth.v:\d+: Assertion failed in TOP.v: synthesis parallel_case' '%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis parallel_case'
); );
ok(1); ok(1);

12
test_regress/t/t_cover_line.v
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@ -72,7 +72,7 @@ module alpha (/*AUTOARG*/
input toggle; input toggle;
always @ (posedge clk) begin always @ (posedge clk) begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"TOP.v.a*",2) // CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2 // t.a1 and t.a2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -95,11 +95,11 @@ module beta (/*AUTOARG*/
always @ (posedge clk) begin always @ (posedge clk) begin
if (0) begin if (0) begin
// CHECK_COVER(-1,"TOP.v.b*",0) // CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets // Make sure that we don't optimize away zero buckets
end end
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"TOP.v.b*",2) // CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2 // t.b1 and t.b2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -128,10 +128,10 @@ module tsk (/*AUTOARG*/
input external; input external;
begin begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"TOP.v.t1",1) // CHECK_COVER(-1,"top.v.t1",1)
end end
if (external) begin if (external) begin
// CHECK_COVER(-1,"TOP.v.t1",1) // CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time); $write("[%0t] Got external pulse\n", $time);
end end
end end
@ -156,7 +156,7 @@ module off (/*AUTOARG*/
// verilator coverage_on // verilator coverage_on
always @ (posedge clk) begin always @ (posedge clk) begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"TOP.v.o1",1) // CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off // because under coverage_module_off
end end
end end

2
test_regress/t/t_cover_sva_notflat.pl
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@ -20,7 +20,7 @@ execute (
# Allow old Perl format dump, or new binary dump # Allow old Perl format dump, or new binary dump
# Check that the hierarchy doesn't include __PVT__ # Check that the hierarchy doesn't include __PVT__
# Otherwise our coverage reports would look really ugly # Otherwise our coverage reports would look really ugly
file_grep ($Self->{coverage_filename}, qr/(TOP\.v\.sub.*.cyc_eq_5)/); file_grep ($Self->{coverage_filename}, qr/(top\.v\.sub.*.cyc_eq_5)/);
ok(1); ok(1);
1; 1;

26
test_regress/t/t_cover_toggle.v
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@ -78,25 +78,25 @@ module alpha (/*AUTOARG*/
input clk; input clk;
input toggle; input toggle;
// CHECK_COVER(-1,"TOP.v.a*",4) // CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
input [7:0] cyc_copy; input [7:0] cyc_copy;
// CHECK_COVER(-1,"TOP.v.a*","cyc_copy[0]",22) // CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22)
// CHECK_COVER(-2,"TOP.v.a*","cyc_copy[1]",10) // CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10)
// CHECK_COVER(-3,"TOP.v.a*","cyc_copy[2]",4) // CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4)
// CHECK_COVER(-4,"TOP.v.a*","cyc_copy[3]",2) // CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2)
// CHECK_COVER(-5,"TOP.v.a*","cyc_copy[4]",0) // CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0)
// CHECK_COVER(-6,"TOP.v.a*","cyc_copy[5]",0) // CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0)
// CHECK_COVER(-7,"TOP.v.a*","cyc_copy[6]",0) // CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0)
// CHECK_COVER(-8,"TOP.v.a*","cyc_copy[7]",0) // CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0)
reg toggle_internal; reg toggle_internal;
// CHECK_COVER(-1,"TOP.v.a*",4) // CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
output reg toggle_up; output reg toggle_up;
// CHECK_COVER(-1,"TOP.v.a*",4) // CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
always @ (posedge clk) begin always @ (posedge clk) begin
@ -113,7 +113,7 @@ module beta (/*AUTOARG*/
input clk; input clk;
input toggle_up; input toggle_up;
// CHECK_COVER(-1,"TOP.v.b1","toggle_up",2) // CHECK_COVER(-1,"top.v.b1","toggle_up",2)
/* verilator public_module */ /* verilator public_module */
@ -133,6 +133,6 @@ module off (/*AUTOARG*/
// verilator coverage_on // verilator coverage_on
input toggle; input toggle;
// CHECK_COVER(-1,"TOP.v.o1","toggle",2) // CHECK_COVER(-1,"top.v.o1","toggle",2)
endmodule endmodule

10
test_regress/t/t_display.pl
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@ -13,11 +13,11 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=>quotemeta(dequote( expect=>quotemeta(dequote(
'[0] In TOP.v: Hi '[0] In top.v: Hi
[0] In TOP.v.sub [0] In top.v.sub
[0] In TOP.v.sub.subblock [0] In top.v.sub.subblock
[0] In TOP.v.sub2 [0] In top.v.sub2
[0] In TOP.v.sub2.subblock2 [0] In top.v.sub2.subblock2
[0] Back \ Quote " [0] Back \ Quote "
[0] %X=0c %D=12 %0X=c %0O=14 %B=001100 [0] %X=0c %D=12 %0X=c %0O=14 %B=001100
[0] %x=0c %d=12 %0x=c %0o=14 %b=001100 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100

10
test_regress/t/t_display_noopt.pl
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@ -16,11 +16,11 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=>quotemeta(dequote( expect=>quotemeta(dequote(
'[0] In TOP.v: Hi '[0] In top.v: Hi
[0] In TOP.v.sub [0] In top.v.sub
[0] In TOP.v.sub.subblock [0] In top.v.sub.subblock
[0] In TOP.v.sub2 [0] In top.v.sub2
[0] In TOP.v.sub2.subblock2 [0] In top.v.sub2.subblock2
[0] Back \ Quote " [0] Back \ Quote "
[0] %X=0c %D=12 %0X=c %0O=14 %B=001100 [0] %X=0c %D=12 %0X=c %0O=14 %B=001100
[0] %x=0c %d=12 %0x=c %0o=14 %b=001100 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100

6
test_regress/t/t_sys_sformat.v
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@ -31,11 +31,7 @@ module t;
$swrite(str2, "mod=%m"); $swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator if (str2 !== "mod=top.v") $stop;
if (str2 !== "mod=TOP.v") $stop;
`else
if (str2 !== "mod=top.t") $stop;
`endif
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

2
test_regress/t/t_trace_public.out
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@ -3,7 +3,7 @@ $date Tue Nov 3 09:34:23 2009
$end $end
$timescale 1ns $end $timescale 1ns $end
$scope module TOP $end $scope module top $end
$var wire 1 6 CLK $end $var wire 1 6 CLK $end
$var wire 1 7 RESET $end $var wire 1 7 RESET $end
$scope module v $end $scope module v $end

2
test_regress/t/t_trace_public_func.cpp
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@ -18,7 +18,7 @@ double sc_time_stamp() {
const unsigned long long dt_2 = 3; const unsigned long long dt_2 = 3;
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
Vt_trace_public_func *top = new Vt_trace_public_func(); Vt_trace_public_func *top = new Vt_trace_public_func("top");
Verilated::debug(0); Verilated::debug(0);
Verilated::traceEverOn(true); Verilated::traceEverOn(true);

2
test_regress/t/t_trace_public_sig.cpp
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@ -18,7 +18,7 @@ double sc_time_stamp() {
const unsigned long long dt_2 = 3; const unsigned long long dt_2 = 3;
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
Vt_trace_public_sig *top = new Vt_trace_public_sig(); Vt_trace_public_sig *top = new Vt_trace_public_sig("top");
Verilated::debug(0); Verilated::debug(0);
Verilated::traceEverOn(true); Verilated::traceEverOn(true);

2
test_regress/t/t_var_escape.out
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@ -3,7 +3,7 @@ $date Fri Nov 13 19:14:12 2009
$end $end
$timescale 1ns $end $timescale 1ns $end
$scope module TOP $end $scope module top $end
$var wire 1 * 9num $end $var wire 1 * 9num $end
$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
$var wire 1 ' clk $end $var wire 1 ' clk $end

2
test_regress/t/t_var_nonamebegin.out
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@ -3,7 +3,7 @@ $date Sun Oct 11 20:21:49 2009
$end $end
$timescale 1ns $end $timescale 1ns $end
$scope module TOP $end $scope module top $end
$var wire 1 # clk $end $var wire 1 # clk $end
$var wire 1 $ reset_l $end $var wire 1 $ reset_l $end
$scope module v $end $scope module v $end

16
test_regress/t/t_var_nonamebegin.pl
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@ -13,14 +13,14 @@ compile (
execute ( execute (
expect=>quotemeta( expect=>quotemeta(
'ingen: {mod}.genblk1 TOP.v.genblk1 'ingen: {mod}.genblk1 top.v.genblk1
d3a: {mod}.d3nameda TOP.v.d3nameda d3a: {mod}.d3nameda top.v.d3nameda
b2: {mod} TOP.v b2: {mod} top.v
b3n: {mod}.b3named: TOP.v.b3named b3n: {mod}.b3named: top.v.b3named
b3: {mod} TOP.v b3: {mod} top.v
b4: {mod} TOP.v b4: {mod} top.v
t1 {mod}.tsk TOP.v t1 {mod}.tsk top.v
t2 {mod}.tsk TOP.v t2 {mod}.tsk top.v
*-* All Finished *-*'), *-* All Finished *-*'),
); );