From 2dc7b7ad78805dd220051f8a8a8cf43b5f77bf63 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 5 Dec 2009 09:58:09 -0500 Subject: [PATCH] Tests: Use top. instead of TOP. to match other sims --- test_regress/driver.pl | 2 +- test_regress/t/t_assert_synth_full.pl | 2 +- test_regress/t/t_assert_synth_parallel.pl | 2 +- test_regress/t/t_cover_line.v | 12 +++++------ test_regress/t/t_cover_sva_notflat.pl | 2 +- test_regress/t/t_cover_toggle.v | 26 +++++++++++------------ test_regress/t/t_display.pl | 10 ++++----- test_regress/t/t_display_noopt.pl | 10 ++++----- test_regress/t/t_sys_sformat.v | 6 +----- test_regress/t/t_trace_public.out | 2 +- test_regress/t/t_trace_public_func.cpp | 2 +- test_regress/t/t_trace_public_sig.cpp | 2 +- test_regress/t/t_var_escape.out | 2 +- test_regress/t/t_var_nonamebegin.out | 2 +- test_regress/t/t_var_nonamebegin.pl | 16 +++++++------- 15 files changed, 47 insertions(+), 51 deletions(-) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 2dfd62be5..639e744f4 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -747,7 +747,7 @@ sub _make_main { print $fh " Verilated::commandArgs(argc, argv);\n"; print $fh " Verilated::debug(".($self->{verilated_debug}?1:0).");\n"; print $fh " Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset}; - print $fh " topp = new $VM_PREFIX (\"TOP\");\n"; + print $fh " topp = new $VM_PREFIX (\"top\");\n"; my $set; if ($self->sp) { print $fh " SP_PIN(topp,fastclk,fastclk);\n" if $self->{inputs}{fastclk}; diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl index 43e145106..308f0aa32 100755 --- a/test_regress/t/t_assert_synth_full.pl +++ b/test_regress/t/t_assert_synth_full.pl @@ -18,7 +18,7 @@ execute ( check_finished=>0, fails=>1, expect=> -'%Error: t_assert_synth.v:\d+: Assertion failed in TOP.v: synthesis full_case' +'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis full_case' ); ok(1); diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl index b196b76cc..762a3dc9e 100755 --- a/test_regress/t/t_assert_synth_parallel.pl +++ b/test_regress/t/t_assert_synth_parallel.pl @@ -18,7 +18,7 @@ execute ( check_finished=>0, fails=>1, expect=> -'%Error: t_assert_synth.v:\d+: Assertion failed in TOP.v: synthesis parallel_case' +'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis parallel_case' ); ok(1); diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 15d8165ee..4a57dff9c 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -72,7 +72,7 @@ module alpha (/*AUTOARG*/ input toggle; always @ (posedge clk) begin if (toggle) begin - // CHECK_COVER(-1,"TOP.v.a*",2) + // CHECK_COVER(-1,"top.v.a*",2) // t.a1 and t.a2 collapse to a count of 2 end if (toggle) begin @@ -95,11 +95,11 @@ module beta (/*AUTOARG*/ always @ (posedge clk) begin if (0) begin - // CHECK_COVER(-1,"TOP.v.b*",0) + // CHECK_COVER(-1,"top.v.b*",0) // Make sure that we don't optimize away zero buckets end if (toggle) begin - // CHECK_COVER(-1,"TOP.v.b*",2) + // CHECK_COVER(-1,"top.v.b*",2) // t.b1 and t.b2 collapse to a count of 2 end if (toggle) begin @@ -128,10 +128,10 @@ module tsk (/*AUTOARG*/ input external; begin if (toggle) begin - // CHECK_COVER(-1,"TOP.v.t1",1) + // CHECK_COVER(-1,"top.v.t1",1) end if (external) begin - // CHECK_COVER(-1,"TOP.v.t1",1) + // CHECK_COVER(-1,"top.v.t1",1) $write("[%0t] Got external pulse\n", $time); end end @@ -156,7 +156,7 @@ module off (/*AUTOARG*/ // verilator coverage_on always @ (posedge clk) begin if (toggle) begin - // CHECK_COVER(-1,"TOP.v.o1",1) + // CHECK_COVER(-1,"top.v.o1",1) // because under coverage_module_off end end diff --git a/test_regress/t/t_cover_sva_notflat.pl b/test_regress/t/t_cover_sva_notflat.pl index 30fc94574..b398e38ad 100755 --- a/test_regress/t/t_cover_sva_notflat.pl +++ b/test_regress/t/t_cover_sva_notflat.pl @@ -20,7 +20,7 @@ execute ( # Allow old Perl format dump, or new binary dump # Check that the hierarchy doesn't include __PVT__ # Otherwise our coverage reports would look really ugly -file_grep ($Self->{coverage_filename}, qr/(TOP\.v\.sub.*.cyc_eq_5)/); +file_grep ($Self->{coverage_filename}, qr/(top\.v\.sub.*.cyc_eq_5)/); ok(1); 1; diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index 728f0396f..21d8ed66e 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -78,25 +78,25 @@ module alpha (/*AUTOARG*/ input clk; input toggle; - // CHECK_COVER(-1,"TOP.v.a*",4) + // CHECK_COVER(-1,"top.v.a*",4) // 2 edges * (t.a1 and t.a2) input [7:0] cyc_copy; - // CHECK_COVER(-1,"TOP.v.a*","cyc_copy[0]",22) - // CHECK_COVER(-2,"TOP.v.a*","cyc_copy[1]",10) - // CHECK_COVER(-3,"TOP.v.a*","cyc_copy[2]",4) - // CHECK_COVER(-4,"TOP.v.a*","cyc_copy[3]",2) - // CHECK_COVER(-5,"TOP.v.a*","cyc_copy[4]",0) - // CHECK_COVER(-6,"TOP.v.a*","cyc_copy[5]",0) - // CHECK_COVER(-7,"TOP.v.a*","cyc_copy[6]",0) - // CHECK_COVER(-8,"TOP.v.a*","cyc_copy[7]",0) + // CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22) + // CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10) + // CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4) + // CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2) + // CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0) + // CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0) + // CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0) + // CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0) reg toggle_internal; - // CHECK_COVER(-1,"TOP.v.a*",4) + // CHECK_COVER(-1,"top.v.a*",4) // 2 edges * (t.a1 and t.a2) output reg toggle_up; - // CHECK_COVER(-1,"TOP.v.a*",4) + // CHECK_COVER(-1,"top.v.a*",4) // 2 edges * (t.a1 and t.a2) always @ (posedge clk) begin @@ -113,7 +113,7 @@ module beta (/*AUTOARG*/ input clk; input toggle_up; - // CHECK_COVER(-1,"TOP.v.b1","toggle_up",2) + // CHECK_COVER(-1,"top.v.b1","toggle_up",2) /* verilator public_module */ @@ -133,6 +133,6 @@ module off (/*AUTOARG*/ // verilator coverage_on input toggle; - // CHECK_COVER(-1,"TOP.v.o1","toggle",2) + // CHECK_COVER(-1,"top.v.o1","toggle",2) endmodule diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl index 6920c0b18..c8da91857 100755 --- a/test_regress/t/t_display.pl +++ b/test_regress/t/t_display.pl @@ -13,11 +13,11 @@ compile ( execute ( check_finished=>1, expect=>quotemeta(dequote( -'[0] In TOP.v: Hi -[0] In TOP.v.sub -[0] In TOP.v.sub.subblock -[0] In TOP.v.sub2 -[0] In TOP.v.sub2.subblock2 +'[0] In top.v: Hi +[0] In top.v.sub +[0] In top.v.sub.subblock +[0] In top.v.sub2 +[0] In top.v.sub2.subblock2 [0] Back \ Quote " [0] %X=0c %D=12 %0X=c %0O=14 %B=001100 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100 diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl index 0ed664dab..3bbecb87d 100755 --- a/test_regress/t/t_display_noopt.pl +++ b/test_regress/t/t_display_noopt.pl @@ -16,11 +16,11 @@ compile ( execute ( check_finished=>1, expect=>quotemeta(dequote( -'[0] In TOP.v: Hi -[0] In TOP.v.sub -[0] In TOP.v.sub.subblock -[0] In TOP.v.sub2 -[0] In TOP.v.sub2.subblock2 +'[0] In top.v: Hi +[0] In top.v.sub +[0] In top.v.sub.subblock +[0] In top.v.sub2 +[0] In top.v.sub2.subblock2 [0] Back \ Quote " [0] %X=0c %D=12 %0X=c %0O=14 %B=001100 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100 diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index 1d470cd20..786fe567b 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -31,11 +31,7 @@ module t; $swrite(str2, "mod=%m"); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif -`ifdef verilator - if (str2 !== "mod=TOP.v") $stop; -`else - if (str2 !== "mod=top.t") $stop; -`endif + if (str2 !== "mod=top.v") $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_trace_public.out b/test_regress/t/t_trace_public.out index 9a12118bb..75cb651c4 100644 --- a/test_regress/t/t_trace_public.out +++ b/test_regress/t/t_trace_public.out @@ -3,7 +3,7 @@ $date Tue Nov 3 09:34:23 2009 $end $timescale 1ns $end - $scope module TOP $end + $scope module top $end $var wire 1 6 CLK $end $var wire 1 7 RESET $end $scope module v $end diff --git a/test_regress/t/t_trace_public_func.cpp b/test_regress/t/t_trace_public_func.cpp index cd184e5d4..b638dfcf5 100644 --- a/test_regress/t/t_trace_public_func.cpp +++ b/test_regress/t/t_trace_public_func.cpp @@ -18,7 +18,7 @@ double sc_time_stamp() { const unsigned long long dt_2 = 3; int main(int argc, char **argv, char **env) { - Vt_trace_public_func *top = new Vt_trace_public_func(); + Vt_trace_public_func *top = new Vt_trace_public_func("top"); Verilated::debug(0); Verilated::traceEverOn(true); diff --git a/test_regress/t/t_trace_public_sig.cpp b/test_regress/t/t_trace_public_sig.cpp index 0523f3b93..6cc17a6c2 100644 --- a/test_regress/t/t_trace_public_sig.cpp +++ b/test_regress/t/t_trace_public_sig.cpp @@ -18,7 +18,7 @@ double sc_time_stamp() { const unsigned long long dt_2 = 3; int main(int argc, char **argv, char **env) { - Vt_trace_public_sig *top = new Vt_trace_public_sig(); + Vt_trace_public_sig *top = new Vt_trace_public_sig("top"); Verilated::debug(0); Verilated::traceEverOn(true); diff --git a/test_regress/t/t_var_escape.out b/test_regress/t/t_var_escape.out index 8248ee119..62d12fa80 100644 --- a/test_regress/t/t_var_escape.out +++ b/test_regress/t/t_var_escape.out @@ -3,7 +3,7 @@ $date Fri Nov 13 19:14:12 2009 $end $timescale 1ns $end - $scope module TOP $end + $scope module top $end $var wire 1 * 9num $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 ' clk $end diff --git a/test_regress/t/t_var_nonamebegin.out b/test_regress/t/t_var_nonamebegin.out index 5ad36b686..179a00a3b 100644 --- a/test_regress/t/t_var_nonamebegin.out +++ b/test_regress/t/t_var_nonamebegin.out @@ -3,7 +3,7 @@ $date Sun Oct 11 20:21:49 2009 $end $timescale 1ns $end - $scope module TOP $end + $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module v $end diff --git a/test_regress/t/t_var_nonamebegin.pl b/test_regress/t/t_var_nonamebegin.pl index d271e4b3a..4280fbef3 100755 --- a/test_regress/t/t_var_nonamebegin.pl +++ b/test_regress/t/t_var_nonamebegin.pl @@ -13,14 +13,14 @@ compile ( execute ( expect=>quotemeta( -'ingen: {mod}.genblk1 TOP.v.genblk1 -d3a: {mod}.d3nameda TOP.v.d3nameda -b2: {mod} TOP.v -b3n: {mod}.b3named: TOP.v.b3named -b3: {mod} TOP.v -b4: {mod} TOP.v -t1 {mod}.tsk TOP.v -t2 {mod}.tsk TOP.v +'ingen: {mod}.genblk1 top.v.genblk1 +d3a: {mod}.d3nameda top.v.d3nameda +b2: {mod} top.v +b3n: {mod}.b3named: top.v.b3named +b3: {mod} top.v +b4: {mod} top.v +t1 {mod}.tsk top.v +t2 {mod}.tsk top.v *-* All Finished *-*'), );