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Fix coredump on constant connect

This commit is contained in:
Wilson Snyder 2012-04-25 22:51:31 -04:00
parent 5b532a1812
commit 24e79ecc68
3 changed files with 51 additions and 6 deletions
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14
src/V3Tristate.cpp
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@ -548,12 +548,14 @@ class TristateVisitor : public TristateBaseVisitor {
} }
// Propagate any pullups/pulldowns upwards if necessary // Propagate any pullups/pulldowns upwards if necessary
if (AstPull* pullp = (AstPull*) nodep->modVarp()->user3p()) { if (refp) {
if (refp && !refp->varp()->user3p()) { if (AstPull* pullp = (AstPull*) nodep->modVarp()->user3p()) {
refp->varp()->user3p(pullp); if (!refp->varp()->user3p()) {
} else { refp->varp()->user3p(pullp);
//selp: Note we don't currently obey selects; all bits must be consistently pulled } else {
checkPullDirection(pullp, (AstPull*) refp->varp()->user3p()); //selp: Note we don't currently obey selects; all bits must be consistently pulled
checkPullDirection(pullp, (AstPull*) refp->varp()->user3p());
}
} }
} }
// Don't need to visit the created assigns, as it was added at the end of the next links // Don't need to visit the created assigns, as it was added at the end of the next links

20
test_regress/t/t_tri_pin0_bad.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
fails=>$Self->{v3},
expect=>
qr{%Error: t/t_tri_pin0_bad.v:\d+: Unsupported tristate port expression: CONST '1'h0'
%Error: t/t_tri_pin0_bad.v:\d+: Output port is connected to a constant pin, electrical short
%Error: Exiting due to},
);
ok(1);
1;

23
test_regress/t/t_tri_pin0_bad.v Normal file
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@ -0,0 +1,23 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
t_tri4 t_tri4 (.t4(1'b0));
endmodule
module t_tri4 (/*AUTOARG*/
// Inputs
t4
);
input t4;
tri0 t4;
initial if (t4 !== 1'b0) $stop;
endmodule