From 24e79ecc6884e4339ac30ad5bf84d81d4a05d5b2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 25 Apr 2012 22:51:31 -0400
Subject: [PATCH] Fix coredump on constant connect

---
 src/V3Tristate.cpp               | 14 ++++++++------
 test_regress/t/t_tri_pin0_bad.pl | 20 ++++++++++++++++++++
 test_regress/t/t_tri_pin0_bad.v  | 23 +++++++++++++++++++++++
 3 files changed, 51 insertions(+), 6 deletions(-)
 create mode 100755 test_regress/t/t_tri_pin0_bad.pl
 create mode 100644 test_regress/t/t_tri_pin0_bad.v

diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index d964e0ad4..dfe191526 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -548,12 +548,14 @@ class TristateVisitor : public TristateBaseVisitor {
 	}
 
 	// Propagate any pullups/pulldowns upwards if necessary
-	if (AstPull* pullp = (AstPull*) nodep->modVarp()->user3p()) {
-	    if (refp && !refp->varp()->user3p()) {
-		refp->varp()->user3p(pullp);
-	    } else {
-		//selp: Note we don't currently obey selects; all bits must be consistently pulled
-		checkPullDirection(pullp, (AstPull*) refp->varp()->user3p());
+	if (refp) {
+	    if (AstPull* pullp = (AstPull*) nodep->modVarp()->user3p()) {
+		if (!refp->varp()->user3p()) {
+		    refp->varp()->user3p(pullp);
+		} else {
+		    //selp: Note we don't currently obey selects; all bits must be consistently pulled
+		    checkPullDirection(pullp, (AstPull*) refp->varp()->user3p());
+		}
 	    }
 	}
 	// Don't need to visit the created assigns, as it was added at the end of the next links
diff --git a/test_regress/t/t_tri_pin0_bad.pl b/test_regress/t/t_tri_pin0_bad.pl
new file mode 100755
index 000000000..26989db72
--- /dev/null
+++ b/test_regress/t/t_tri_pin0_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 fails=>$Self->{v3},
+	 expect=>
+qr{%Error: t/t_tri_pin0_bad.v:\d+: Unsupported tristate port expression: CONST '1'h0'
+%Error: t/t_tri_pin0_bad.v:\d+: Output port is connected to a constant pin, electrical short
+%Error: Exiting due to},
+    );
+
+ok(1);
+1;
+
diff --git a/test_regress/t/t_tri_pin0_bad.v b/test_regress/t/t_tri_pin0_bad.v
new file mode 100644
index 000000000..b162133ba
--- /dev/null
+++ b/test_regress/t/t_tri_pin0_bad.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   t_tri4 t_tri4 (.t4(1'b0));
+
+endmodule
+
+module t_tri4 (/*AUTOARG*/
+   // Inputs
+   t4
+   );
+   input t4;
+   tri0  t4;
+   initial if (t4 !== 1'b0) $stop;
+endmodule