From 1f67080a1f8f158522c8ce69605ff54769a009b3 Mon Sep 17 00:00:00 2001 From: Veripool API Bot <57024651+veripoolbot@users.noreply.github.com> Date: Mon, 9 Mar 2026 21:38:29 -0400 Subject: [PATCH] Tests: Verilog format --- docs/gen/ex_PINMISSING_faulty.rst | 8 +- docs/gen/ex_PINMISSING_msg.rst | 2 +- test_regress/t/t_class_new_scoped.v | 2 + test_regress/t/t_class_param_bad_paren.out | 8 +- test_regress/t/t_class_param_bad_paren.v | 24 +- test_regress/t/t_clocking_out_on_change.v | 100 +- test_regress/t/t_constraint_state.v | 94 +- test_regress/t/t_flag_parameter.v | 5 +- test_regress/t/t_flag_parameter_hier.v | 5 +- test_regress/t/t_flag_topmodule.v | 36 +- test_regress/t/t_flag_topmodule_inline.v | 34 +- test_regress/t/t_func_arg_complex.v | 5 +- test_regress/t/t_func_const3_bad.out | 6 +- test_regress/t/t_func_const3_bad.v | 40 +- test_regress/t/t_hier_block.v | 524 +++++----- test_regress/t/t_inside3.v | 40 +- test_regress/t/t_langext_1.v | 59 +- test_regress/t/t_langext_1_bad.out | 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test_regress/t/t_opt_table_same.v | 74 +- test_regress/t/t_opt_table_signed.v | 50 +- test_regress/t/t_opt_table_sparse.v | 54 +- test_regress/t/t_opt_table_string.v | 50 +- test_regress/t/t_opt_table_struct.v | 58 +- test_regress/t/t_order.v | 172 ++-- test_regress/t/t_order_2d.v | 111 ++- test_regress/t/t_order_a.v | 79 +- test_regress/t/t_order_b.v | 18 +- test_regress/t/t_order_blkandnblk_bad.out | 52 +- test_regress/t/t_order_blkandnblk_bad.v | 44 +- test_regress/t/t_order_blkloopinit_bad.out | 6 +- test_regress/t/t_order_blkloopinit_bad.v | 34 +- test_regress/t/t_order_clkinst.v | 224 +++-- test_regress/t/t_order_comboclkloop.v | 121 +-- test_regress/t/t_order_comboloop.v | 89 +- test_regress/t/t_order_doubleloop.v | 175 ++-- test_regress/t/t_order_dpi_export_1.v | 38 +- test_regress/t/t_order_dpi_export_2.v | 52 +- test_regress/t/t_order_dpi_export_3.v | 75 +- test_regress/t/t_order_dpi_export_4.v | 75 +- test_regress/t/t_order_dpi_export_5.v | 55 +- test_regress/t/t_order_dpi_export_6.v | 64 +- test_regress/t/t_order_dpi_export_7.v | 47 +- test_regress/t/t_order_dpi_export_8.v | 57 +- test_regress/t/t_order_first.v | 75 +- test_regress/t/t_order_loop_bad.v | 44 +- test_regress/t/t_order_multialways.v | 92 +- test_regress/t/t_order_multidriven.v | 249 +++-- test_regress/t/t_order_quad.v | 19 +- test_regress/t/t_order_wireloop.v | 18 +- test_regress/t/t_package.v | 95 +- test_regress/t/t_package_abs.v | 38 +- test_regress/t/t_package_ddecl.v | 38 +- test_regress/t/t_package_dimport.v | 76 +- test_regress/t/t_package_dot.v | 25 +- test_regress/t/t_package_dup_bad.out | 8 +- test_regress/t/t_package_dup_bad.v | 20 +- test_regress/t/t_package_enum.v | 41 +- test_regress/t/t_package_export.v | 59 +- test_regress/t/t_package_export_bad.out | 42 +- test_regress/t/t_package_export_bad2.out | 6 +- test_regress/t/t_package_export_bad2.v | 4 +- test_regress/t/t_package_identifier_bad.out | 6 +- test_regress/t/t_package_identifier_bad.v | 4 +- test_regress/t/t_package_import_bad2.out | 6 +- test_regress/t/t_package_import_bad2.v | 4 +- test_regress/t/t_package_local_bad.out | 6 +- test_regress/t/t_package_local_bad.v | 8 +- test_regress/t/t_package_param.v | 38 +- test_regress/t/t_package_twodeep.v | 22 +- test_regress/t/t_package_using_dollar_unit.v | 69 +- test_regress/t/t_package_verb.v | 22 +- test_regress/t/t_packed_concat.v | 26 +- test_regress/t/t_packed_concat_bad.out | 18 +- test_regress/t/t_packed_concat_bad.v | 24 +- test_regress/t/t_param.v | 117 +-- test_regress/t/t_param_array.v | 129 +-- test_regress/t/t_param_array2.v | 25 +- test_regress/t/t_param_array3.v | 50 +- test_regress/t/t_param_array4.v | 62 +- test_regress/t/t_param_array5.v | 48 +- test_regress/t/t_param_array6.v | 87 +- test_regress/t/t_param_array7.v | 86 +- test_regress/t/t_param_array8.v | 28 +- test_regress/t/t_param_avec.v | 63 +- test_regress/t/t_param_bit_sel.v | 34 +- test_regress/t/t_param_bracket.v | 22 +- test_regress/t/t_param_ceil.v | 65 +- test_regress/t/t_param_chain.v | 50 +- test_regress/t/t_param_circ_bad.out | 6 +- test_regress/t/t_param_circ_bad.v | 8 +- test_regress/t/t_param_concat.v | 34 +- test_regress/t/t_param_concat_bad.out | 18 +- test_regress/t/t_param_const_part.v | 34 +- test_regress/t/t_param_ddeep_width.v | 33 +- test_regress/t/t_param_default.v | 10 +- test_regress/t/t_param_default_2.v | 62 +- test_regress/t/t_param_default_bad.out | 6 +- test_regress/t/t_param_default_bad.v | 6 +- test_regress/t/t_param_default_override.v | 60 +- test_regress/t/t_param_default_presv_bad.out | 12 +- test_regress/t/t_param_first.v | 224 ++--- test_regress/t/t_param_first_a.v | 33 +- test_regress/t/t_param_first_b.v | 23 +- test_regress/t/t_param_func.v | 34 +- test_regress/t/t_param_func2.v | 72 +- test_regress/t/t_param_if_blk.v | 205 ++-- test_regress/t/t_param_implicit_local_bad.out | 42 +- test_regress/t/t_param_implicit_local_bad.v | 48 +- test_regress/t/t_param_in_func.v | 187 ++-- test_regress/t/t_param_local.v | 38 +- test_regress/t/t_param_long.v | 312 +++--- test_regress/t/t_param_mem_attr.v | 29 +- test_regress/t/t_param_mintypmax.v | 34 +- test_regress/t/t_param_module.v | 52 +- test_regress/t/t_param_named.v | 83 +- test_regress/t/t_param_named_2.v | 78 +- test_regress/t/t_param_no_parentheses.v | 96 +- test_regress/t/t_param_noval_bad.out | 30 +- test_regress/t/t_param_noval_bad.v | 10 +- test_regress/t/t_param_package.v | 28 +- test_regress/t/t_param_passed_to_port.v | 22 +- test_regress/t/t_param_pattern.v | 50 +- test_regress/t/t_param_pattern2.v | 24 +- test_regress/t/t_param_pattern_init.v | 134 ++- test_regress/t/t_param_public.v | 30 +- test_regress/t/t_param_real.v | 26 +- test_regress/t/t_param_real2.v | 43 +- test_regress/t/t_param_repl.v | 74 +- test_regress/t/t_param_scope_bad.out | 12 +- test_regress/t/t_param_scope_bad.v | 40 +- test_regress/t/t_param_seg.v | 33 +- test_regress/t/t_param_sel.v | 144 +-- test_regress/t/t_param_sel_range.v | 60 +- test_regress/t/t_param_sel_range_bad.out | 6 +- test_regress/t/t_param_shift.v | 36 +- test_regress/t/t_param_store_bad.out | 6 +- test_regress/t/t_param_store_bad.v | 16 +- test_regress/t/t_param_type.v | 114 ++- test_regress/t/t_param_type2.v | 48 +- test_regress/t/t_param_type3.v | 71 +- test_regress/t/t_param_type4.v | 86 +- test_regress/t/t_param_type5.v | 53 +- test_regress/t/t_param_type6.v | 51 +- test_regress/t/t_param_type_bad.out | 6 +- test_regress/t/t_param_type_bad.v | 4 +- test_regress/t/t_param_type_bad2.out | 12 +- test_regress/t/t_param_type_bad2.v | 4 +- test_regress/t/t_param_type_bad3.out | 6 +- test_regress/t/t_param_type_bad3.v | 4 +- test_regress/t/t_param_type_bit.v | 16 +- test_regress/t/t_param_type_cmp.v | 68 +- test_regress/t/t_param_type_fwd.v | 28 +- test_regress/t/t_param_type_fwd_bad.out | 60 +- test_regress/t/t_param_type_fwd_bad.v | 28 +- test_regress/t/t_param_typedef.v | 59 +- test_regress/t/t_param_unreachable.v | 52 +- test_regress/t/t_param_up_bad.out | 6 +- test_regress/t/t_param_up_bad.v | 25 +- test_regress/t/t_param_value.v | 80 +- test_regress/t/t_param_while.v | 31 +- test_regress/t/t_param_wide_io.v | 16 +- test_regress/t/t_param_width.v | 49 +- test_regress/t/t_param_width_loc_bad.out | 4 +- test_regress/t/t_param_width_loc_bad.v | 17 +- test_regress/t/t_param_x_unique.v | 14 +- test_regress/t/t_paramgraph_minimal_sibling.v | 5 +- test_regress/t/t_parse_delay.v | 21 +- test_regress/t/t_parse_sync_bad.out | 12 +- test_regress/t/t_parse_sync_bad.v | 24 +- test_regress/t/t_parse_sync_bad2.out | 6 +- test_regress/t/t_parse_sync_bad2.v | 16 +- test_regress/t/t_past.v | 195 ++-- test_regress/t/t_past_bad.out | 26 +- test_regress/t/t_past_bad.v | 22 +- test_regress/t/t_past_funcs.v | 222 +++-- test_regress/t/t_past_strobe.v | 58 +- test_regress/t/t_past_unsup.out | 18 +- test_regress/t/t_past_unsup.v | 22 +- test_regress/t/t_pgo_profoutofdate_bad.v | 26 +- test_regress/t/t_pli_bad.out | 38 +- test_regress/t/t_pli_bad.v | 20 +- test_regress/t/t_pp_display.v | 58 +- test_regress/t/t_pp_dupdef.v | 2 +- test_regress/t/t_pp_lib.v | 4 +- test_regress/t/t_pp_lib_library.v | 14 +- test_regress/t/t_pp_misdef_bad.out | 8 +- test_regress/t/t_pp_misdef_bad.v | 1 + test_regress/t/t_pp_pragmas.v | 8 +- test_regress/t/t_pp_recursedef_bad.out | 2 +- test_regress/t/t_pp_recursedef_bad.v | 7 +- test_regress/t/t_pp_underline_bad.out | 12 +- test_regress/t/t_pp_underline_bad.v | 16 +- test_regress/t/t_pp_underline_bad_vlt.out | 6 +- test_regress/t/t_premit_rw.v | 42 +- test_regress/t/t_preproc_ifdef.v | 24 +- test_regress/t/t_preproc_kwd.v | 26 +- test_regress/t/t_probdist.v | 180 ++-- test_regress/t/t_probdist_bad.v | 42 +- test_regress/t/t_process.v | 40 +- test_regress/t/t_process_bad.out | 12 +- test_regress/t/t_process_bad.v | 18 +- test_regress/t/t_process_compare.v | 54 +- test_regress/t/t_process_copy_constr.v | 30 +- test_regress/t/t_process_finished.v | 28 +- test_regress/t/t_process_fork.v | 44 +- test_regress/t/t_process_kill.v | 40 +- test_regress/t/t_process_notiming.out | 78 +- test_regress/t/t_process_rand.v | 74 +- test_regress/t/t_process_redecl.v | 25 +- test_regress/t/t_process_task.v | 45 +- test_regress/t/t_prof.v | 100 +- test_regress/t/t_property.v | 67 +- test_regress/t/t_property_named.v | 124 +-- test_regress/t/t_property_negated.v | 54 +- test_regress/t/t_property_pexpr_unsup.out | 196 ++-- test_regress/t/t_property_pexpr_unsup.v | 200 ++-- test_regress/t/t_property_recursive_unsup.out | 6 +- test_regress/t/t_property_recursive_unsup.v | 48 +- test_regress/t/t_property_sexpr_disable.v | 12 +- ...t_property_sexpr_disable_sampled_unsup.out | 4 +- .../t_property_sexpr_disable_sampled_unsup.v | 12 +- test_regress/t/t_property_untyped.v | 50 +- test_regress/t/t_property_untyped_unsup.out | 6 +- test_regress/t/t_property_untyped_unsup.v | 40 +- test_regress/t/t_property_var_unsup.out | 18 +- test_regress/t/t_property_var_unsup.v | 49 +- test_regress/t/t_protect_ids.v | 121 +-- test_regress/t/t_public_clk.v | 20 +- test_regress/t/t_public_seq.v | 44 +- test_regress/t/t_public_unpacked_port.v | 71 +- test_regress/t/t_randc.v | 196 ++-- test_regress/t/t_randc_oversize_bad.out | 6 +- test_regress/t/t_randc_oversize_bad.v | 12 +- test_regress/t/t_randcase.v | 134 +-- test_regress/t/t_randcase_bad.v | 14 +- test_regress/t/t_randomize.v | 106 +- .../t/t_randomize_inline_var_ctl_bad.out | 36 +- .../t/t_randomize_inline_var_ctl_bad.v | 26 +- .../t/t_randomize_inline_var_ctl_unsup_1.out | 18 +- .../t/t_randomize_inline_var_ctl_unsup_1.v | 24 +- .../t/t_randomize_inline_var_ctl_unsup_2.out | 12 +- .../t/t_randomize_inline_var_ctl_unsup_2.v | 12 +- test_regress/t/t_randomize_method.v | 280 +++--- test_regress/t/t_randomize_method_bad.out | 18 +- test_regress/t/t_randomize_method_bad.v | 14 +- .../t/t_randomize_method_complex_bad.out | 12 +- .../t/t_randomize_method_complex_bad.v | 17 +- .../t/t_randomize_method_constraints.v | 116 +-- .../t/t_randomize_method_nclass_bad.out | 6 +- .../t/t_randomize_method_nclass_bad.v | 8 +- test_regress/t/t_randomize_method_std.v | 16 +- .../t/t_randomize_method_types_unsup.out | 24 +- .../t/t_randomize_method_types_unsup.v | 58 +- .../t/t_randomize_method_with_scoping.v | 168 ++-- test_regress/t/t_randomize_param_with.v | 60 +- test_regress/t/t_randomize_prepost.v | 2 + test_regress/t/t_randomize_queue_size.v | 118 +-- test_regress/t/t_randomize_rand_mode.v | 166 ++-- test_regress/t/t_randomize_rand_mode_bad.out | 36 +- test_regress/t/t_randomize_rand_mode_bad.v | 30 +- .../t/t_randomize_rand_mode_unsup.out | 38 +- test_regress/t/t_randomize_rand_mode_unsup.v | 26 +- test_regress/t/t_randomize_srandom.v | 232 ++--- test_regress/t/t_randomize_this.v | 54 +- test_regress/t/t_randomize_union.v | 231 ++--- test_regress/t/t_randomize_union_bad.v | 36 +- test_regress/t/t_randstate_func.v | 46 +- test_regress/t/t_randstate_seed_bad.v | 30 +- test_regress/t/t_real_cast.v | 49 +- test_regress/t/t_real_param.v | 43 +- test_regress/t/t_recursive_method.v | 84 +- test_regress/t/t_recursive_module_bug.v | 71 +- test_regress/t/t_recursive_module_bug_2.v | 19 +- test_regress/t/t_reloop_cam.v | 290 +++--- test_regress/t/t_reloop_local.v | 114 +-- test_regress/t/t_reloop_offset.v | 64 +- test_regress/t/t_repeat.v | 44 +- test_regress/t/t_rnd.v | 67 +- test_regress/t/t_runflag.v | 8 +- test_regress/t/t_runflag_bad.v | 8 +- test_regress/t/t_runflag_errorlimit_bad.v | 18 +- .../t/t_runflag_errorlimit_fatal_bad.v | 20 +- test_regress/t/t_runflag_quiet.v | 13 +- test_regress/t/t_runflag_seed.v | 18 +- test_regress/t/t_runflag_uninit_bad.v | 2 +- test_regress/t/t_sampled_expr.v | 77 +- test_regress/t/t_sampled_expr_unsup.out | 6 +- test_regress/t/t_sampled_expr_unsup.v | 20 +- test_regress/t/t_sampled_sensitivity.out | 4 +- test_regress/t/t_sampled_sensitivity.v | 7 +- test_regress/t/t_savable.v | 172 ++-- test_regress/t/t_savable_class_bad.v | 20 +- test_regress/t/t_sc_names.v | 6 +- test_regress/t/t_sc_vl_assign_sbw.v | 36 +- test_regress/t/t_scheduling_5.v | 65 +- test_regress/t/t_scheduling_6.v | 10 +- test_regress/t/t_scheduling_many_clocks.v | 27 +- test_regress/t/t_scope_map.v | 75 +- test_regress/t/t_select_2d.v | 113 ++- test_regress/t/t_select_ascending.v | 115 ++- test_regress/t/t_select_bad_msb.out | 12 +- test_regress/t/t_select_bad_msb.v | 21 +- test_regress/t/t_select_bad_range.out | 12 +- test_regress/t/t_select_bad_range.v | 23 +- test_regress/t/t_select_bad_range2.out | 6 +- test_regress/t/t_select_bad_range2.v | 74 +- test_regress/t/t_select_bad_range3.out | 6 +- test_regress/t/t_select_bad_range3.v | 22 +- test_regress/t/t_select_bad_range4.out | 120 +-- test_regress/t/t_select_bad_range4.v | 39 +- test_regress/t/t_select_bad_range5.out | 30 +- test_regress/t/t_select_bad_range5.v | 18 +- test_regress/t/t_select_bad_range6.out | 12 +- test_regress/t/t_select_bad_range6.v | 23 +- test_regress/t/t_select_bad_tri.out | 12 +- test_regress/t/t_select_bad_tri.v | 8 +- test_regress/t/t_select_bad_width0.out | 24 +- test_regress/t/t_select_bad_width0.v | 22 +- test_regress/t/t_select_bound1.v | 145 +-- test_regress/t/t_select_bound2.v | 141 +-- test_regress/t/t_select_bound3.v | 26 +- test_regress/t/t_select_c.v | 34 +- test_regress/t/t_select_crazy.v | 44 +- test_regress/t/t_select_index.v | 68 +- test_regress/t/t_select_index2.v | 41 +- test_regress/t/t_select_lhs_oob.v | 151 ++- test_regress/t/t_select_lhs_oob2.v | 233 ++--- test_regress/t/t_select_little.v | 115 ++- test_regress/t/t_select_little_pack.v | 28 +- test_regress/t/t_select_loop.v | 81 +- test_regress/t/t_select_mul_extend.v | 162 +-- test_regress/t/t_select_negative.v | 104 +- test_regress/t/t_select_out_of_range.v | 24 +- test_regress/t/t_select_param.v | 18 +- test_regress/t/t_select_plus.v | 155 ++- test_regress/t/t_select_plus_mul_pow2.v | 85 +- test_regress/t/t_select_plusloop.v | 116 +-- test_regress/t/t_select_runtime_range.v | 126 +-- test_regress/t/t_select_set.v | 78 +- test_regress/t/t_select_width.v | 35 +- test_regress/t/t_semaphore.v | 66 +- test_regress/t/t_semaphore_always.v | 27 +- test_regress/t/t_semaphore_bad.out | 6 +- test_regress/t/t_semaphore_bad.v | 14 +- test_regress/t/t_semaphore_concurrent.v | 44 +- .../t/t_sequence_first_match_unsup.out | 36 +- test_regress/t/t_sequence_first_match_unsup.v | 15 +- test_regress/t/t_sequence_sexpr_unsup.out | 354 +++---- test_regress/t/t_sequence_sexpr_unsup.v | 218 ++-- test_regress/t/t_setuphold.v | 134 +-- test_regress/t/t_slice_cmp.v | 26 +- test_regress/t/t_slice_cond.v | 52 +- test_regress/t/t_slice_cond_2d_side_effect.v | 42 +- test_regress/t/t_slice_cond_side_effect.v | 38 +- test_regress/t/t_slice_init.v | 82 +- test_regress/t/t_split_var_0.v | 770 +++++++-------- test_regress/t/t_split_var_1_bad.out | 118 +-- test_regress/t/t_split_var_1_bad.v | 117 ++- test_regress/t/t_split_var_3_wreal.v | 80 +- test_regress/t/t_split_var_4.v | 124 +-- test_regress/t/t_split_var_issue.v | 48 +- test_regress/t/t_split_var_types.v | 69 +- test_regress/t/t_srandom_class_dep.v | 32 +- test_regress/t/t_stack_check.v | 8 +- test_regress/t/t_static_elab.v | 60 +- test_regress/t/t_std_identifier.v | 8 +- test_regress/t/t_std_identifier_bad.out | 12 +- test_regress/t/t_std_randomize.v | 226 ++--- test_regress/t/t_std_randomize_bad1.out | 12 +- test_regress/t/t_std_randomize_bad1.v | 26 +- test_regress/t/t_std_randomize_no_args.v | 30 +- test_regress/t/t_stmt_incr_unsup.out | 6 +- test_regress/t/t_stmt_incr_unsup.v | 14 +- test_regress/t/t_stop_bad.v | 8 +- test_regress/t/t_stop_winos_bad.v | 14 +- test_regress/t/t_stream.v | 534 +++++----- test_regress/t/t_stream2.v | 128 +-- test_regress/t/t_stream3.v | 143 +-- test_regress/t/t_stream4.v | 54 +- test_regress/t/t_stream5.v | 68 +- test_regress/t/t_stream_dynamic.v | 304 +++--- test_regress/t/t_stream_integer_type.v | 568 +++++------ test_regress/t/t_stream_string_array.v | 38 +- test_regress/t/t_stream_struct.v | 102 +- test_regress/t/t_stream_trace.v | 34 +- test_regress/t/t_stream_unpack.v | 420 ++++---- test_regress/t/t_stream_unpack_lhs.out | 30 +- test_regress/t/t_stream_unpack_lhs.v | 235 +++-- test_regress/t/t_stream_unpack_wider.v | 112 +-- test_regress/t/t_strength_2_uneq_assign.out | 12 +- test_regress/t/t_strength_2_uneq_assign.v | 24 +- test_regress/t/t_strength_bufif1.out | 6 +- test_regress/t/t_strength_bufif1.v | 16 +- test_regress/t/t_strength_equal_strength.v | 62 +- test_regress/t/t_strength_highz.out | 24 +- test_regress/t/t_strength_highz.v | 20 +- .../t/t_strength_strong1_strong1_bad.out | 6 +- .../t/t_strength_strong1_strong1_bad.v | 8 +- .../t/t_strength_strongest_constant.v | 47 +- .../t/t_strength_strongest_non_tristate.v | 46 +- test_regress/t/t_string.v | 214 ++-- test_regress/t/t_string_byte.v | 32 +- test_regress/t/t_string_convert2.v | 75 +- test_regress/t/t_string_dyn_num.v | 86 +- test_regress/t/t_string_octal.v | 58 +- test_regress/t/t_string_repl.v | 44 +- test_regress/t/t_string_sel.v | 80 +- test_regress/t/t_string_size.v | 130 +-- test_regress/t/t_string_to_bit.v | 158 +-- test_regress/t/t_string_type_methods.v | 290 +++--- test_regress/t/t_string_type_methods_bad.out | 24 +- test_regress/t/t_string_type_methods_bad.v | 20 +- test_regress/t/t_struct_anon.v | 16 +- test_regress/t/t_struct_array.v | 49 +- .../t/t_struct_array_assignment_delayed.v | 40 +- test_regress/t/t_struct_assign.v | 50 +- test_regress/t/t_struct_clk.v | 69 +- test_regress/t/t_struct_cons_cast.v | 68 +- test_regress/t/t_struct_contents.v | 79 +- test_regress/t/t_struct_contents_bad.out | 66 +- test_regress/t/t_struct_contents_bad.v | 51 +- test_regress/t/t_struct_genfor.v | 30 +- test_regress/t/t_struct_init.v | 206 ++-- test_regress/t/t_struct_init_bad.out | 6 +- test_regress/t/t_struct_initial_assign.v | 102 +- test_regress/t/t_struct_literal_param.v | 30 +- test_regress/t/t_struct_nest.v | 40 +- test_regress/t/t_struct_nest_uarray.v | 45 +- test_regress/t/t_struct_notfound_bad.out | 6 +- test_regress/t/t_struct_notfound_bad.v | 12 +- test_regress/t/t_struct_packed_init_bad.out | 6 +- test_regress/t/t_struct_packed_init_bad.v | 18 +- test_regress/t/t_struct_packed_sysfunct.v | 88 +- test_regress/t/t_struct_packed_value_list.v | 246 +++-- test_regress/t/t_struct_packed_write_read.v | 278 ++++-- test_regress/t/t_struct_param_overflow.v | 8 +- test_regress/t/t_struct_pat.v | 180 ++-- test_regress/t/t_struct_pat_width.v | 49 +- test_regress/t/t_struct_port.v | 116 +-- test_regress/t/t_struct_portsel.v | 149 ++- test_regress/t/t_struct_type_bad.out | 6 +- test_regress/t/t_struct_type_bad.v | 10 +- test_regress/t/t_struct_unaligned.v | 44 +- test_regress/t/t_struct_unpacked.v | 82 +- test_regress/t/t_struct_unpacked_array.v | 52 +- test_regress/t/t_struct_unpacked_clean.v | 28 +- test_regress/t/t_struct_unused.v | 22 +- .../t/t_structu_dataType_assignment_bad.out | 4 +- .../t/t_structu_dataType_assignment_bad.v | 8 +- test_regress/t/t_structu_wide.v | 23 +- test_regress/t/t_sv_bus_mux_demux.v | 274 +++--- test_regress/t/t_sv_conditional.v | 719 +++++++------- test_regress/t/t_sv_cpu.v | 175 ++-- test_regress/t/t_sys_delta_monitor.v | 32 +- test_regress/t/t_sys_file_basic.v | 584 +++++------ test_regress/t/t_sys_file_basic_mcd.v | 2 + test_regress/t/t_sys_file_eof.v | 40 +- test_regress/t/t_sys_file_null.v | 20 +- test_regress/t/t_sys_file_scan.v | 36 +- test_regress/t/t_sys_file_scan2.v | 42 +- test_regress/t/t_sys_file_zero.v | 60 +- test_regress/t/t_sys_fmonitor.v | 89 +- test_regress/t/t_sys_fscanf_bad.out | 12 +- test_regress/t/t_sys_fscanf_bad.v | 16 +- test_regress/t/t_sys_fstrobe.v | 85 +- test_regress/t/t_sys_monitor.v | 71 +- test_regress/t/t_sys_monitor_changes.v | 40 +- test_regress/t/t_sys_monitor_dotted.v | 119 ++- test_regress/t/t_sys_plusargs.v | 196 ++-- test_regress/t/t_sys_plusargs_bad.v | 22 +- test_regress/t/t_sys_psprintf.v | 32 +- test_regress/t/t_sys_psprintf_warn_bad.out | 6 +- test_regress/t/t_sys_readmem.v | 406 ++++---- test_regress/t/t_sys_readmem_4state.v | 24 +- test_regress/t/t_sys_readmem_assoc.v | 58 +- test_regress/t/t_sys_readmem_assoc_bad.out | 12 +- test_regress/t/t_sys_readmem_assoc_bad.v | 16 +- test_regress/t/t_sys_readmem_bad_addr.v | 12 +- test_regress/t/t_sys_readmem_bad_addr2.v | 12 +- test_regress/t/t_sys_readmem_bad_digit.v | 12 +- test_regress/t/t_sys_readmem_bad_end.v | 20 +- test_regress/t/t_sys_readmem_bad_notfound.v | 12 +- test_regress/t/t_sys_readmem_eof.v | 22 +- test_regress/t/t_sys_sformat.v | 162 +-- test_regress/t/t_sys_strobe.v | 71 +- test_regress/t/t_sys_system.v | 48 +- test_regress/t/t_sys_time.v | 44 +- test_regress/t/t_tagged.out | 128 +-- test_regress/t/t_tagged.v | 74 +- test_regress/t/t_tagged_case.out | 200 ++-- test_regress/t/t_tagged_case.v | 2 + test_regress/t/t_tagged_if.out | 16 +- test_regress/t/t_tagged_if.v | 2 + test_regress/t/t_tagged_union.out | 198 ++-- test_regress/t/t_tagged_union.v | 2 + test_regress/t/t_threads_counter.v | 27 +- test_regress/t/t_threads_crazy.v | 27 +- test_regress/t/t_time.v | 2 + test_regress/t/t_time_literals.v | 2 + test_regress/t/t_time_passed.v | 8 +- test_regress/t/t_timescale_parse.v | 1 + test_regress/t/t_timing_always.v | 58 +- test_regress/t/t_timing_class.v | 425 ++++---- test_regress/t/t_timing_clkgen1.v | 52 +- test_regress/t/t_timing_clkgen2.v | 42 +- test_regress/t/t_timing_clkgen3.v | 52 +- test_regress/t/t_timing_clkgen_unsup.out | 6 +- test_regress/t/t_timing_debug1.out | 90 +- test_regress/t/t_timing_debug2.out | 928 +++++++++--------- test_regress/t/t_timing_delay_callstack.v | 54 +- test_regress/t/t_timing_dlyassign.v | 42 +- test_regress/t/t_timing_dpi_unsup.out | 6 +- test_regress/t/t_timing_dpi_unsup.v | 44 +- test_regress/t/t_timing_events.v | 54 +- test_regress/t/t_timing_finish2.v | 32 +- test_regress/t/t_timing_fork_comb.v | 83 +- test_regress/t/t_timing_fork_join.v | 151 +-- test_regress/t/t_timing_fork_many.v | 40 +- test_regress/t/t_timing_fork_nba.v | 23 +- test_regress/t/t_timing_fork_no_timing_ctrl.v | 14 +- test_regress/t/t_timing_fork_rec_method.v | 30 +- test_regress/t/t_timing_func_bad.out | 36 +- test_regress/t/t_timing_func_bad.v | 60 +- test_regress/t/t_timing_func_fork_bad.out | 60 +- test_regress/t/t_timing_func_fork_bad.v | 58 +- test_regress/t/t_timing_func_join.v | 38 +- test_regress/t/t_timing_localevent.v | 60 +- test_regress/t/t_timing_nba_1.v | 52 +- test_regress/t/t_timing_nba_2.v | 50 +- .../t/t_timing_nested_assignment_on_lhs.v | 34 +- test_regress/t/t_timing_off.v | 59 +- test_regress/t/t_timing_osc.v | 84 +- test_regress/t/t_timing_pong.v | 44 +- test_regress/t/t_timing_reentry.v | 54 +- test_regress/t/t_timing_sched.v | 83 +- test_regress/t/t_timing_sched_if.v | 103 +- test_regress/t/t_timing_sched_nba.v | 67 +- test_regress/t/t_timing_split.v | 36 +- test_regress/t/t_timing_strobe.v | 38 +- test_regress/t/t_timing_timescale.v | 86 +- test_regress/t/t_timing_trace.v | 68 +- test_regress/t/t_timing_unset1.out | 88 +- test_regress/t/t_timing_unset2.out | 36 +- test_regress/t/t_timing_wait1.v | 84 +- test_regress/t/t_timing_wait2.v | 44 +- test_regress/t/t_timing_wait3.v | 58 +- test_regress/t/t_timing_wait_long.v | 61 +- test_regress/t/t_timing_write_expr.v | 26 +- test_regress/t/t_trace_abort.v | 20 +- test_regress/t/t_trace_array.v | 32 +- test_regress/t/t_trace_ascendingrange.v | 168 ++-- test_regress/t/t_trace_binary.v | 20 +- test_regress/t/t_trace_cat.v | 16 +- test_regress/t/t_trace_cat_fst.v | 19 +- test_regress/t/t_trace_class.v | 34 +- test_regress/t/t_trace_complex.v | 196 ++-- test_regress/t/t_trace_decoration.v | 28 +- test_regress/t/t_trace_dumporder_bad.v | 12 +- test_regress/t/t_trace_dumpvars_dyn.v | 56 +- test_regress/t/t_trace_empty.v | 26 +- test_regress/t/t_trace_ena.v | 58 +- test_regress/t/t_trace_enum.v | 35 +- test_regress/t/t_trace_event.v | 45 +- test_regress/t/t_trace_flag_off.v | 12 +- test_regress/t/t_trace_fst.v | 183 ++-- test_regress/t/t_trace_fst_cmake.v | 153 ++- test_regress/t/t_trace_fst_sc.v | 148 ++- test_regress/t/t_trace_fst_sc_cmake.v | 148 ++- test_regress/t/t_trace_iface.v | 118 +-- test_regress/t/t_trace_no_top_name.v | 16 +- test_regress/t/t_trace_no_top_name2.v | 41 +- test_regress/t/t_trace_noflag_bad.v | 12 +- test_regress/t/t_trace_open_wrong_order_bad.v | 4 +- test_regress/t/t_trace_packed_struct.v | 48 +- test_regress/t/t_trace_param.v | 35 +- test_regress/t/t_trace_param_override.v | 18 +- test_regress/t/t_trace_primitive.v | 50 +- test_regress/t/t_trace_public.v | 96 +- test_regress/t/t_trace_sc_empty.v | 9 +- test_regress/t/t_trace_scope_no_inline.v | 50 +- test_regress/t/t_trace_scope_vlt.v | 56 +- test_regress/t/t_trace_scstruct.v | 17 +- test_regress/t/t_trace_split_cfuncs.v | 8 +- .../t/t_trace_split_cfuncs_dpi_export.v | 14 +- test_regress/t/t_trace_string.v | 62 +- test_regress/t/t_trace_timescale.v | 29 +- test_regress/t/t_trace_timing1.v | 40 +- test_regress/t/t_trace_two_a.v | 104 +- test_regress/t/t_trace_two_b.v | 30 +- test_regress/t/t_trace_wide_struct.v | 20 +- test_regress/t/t_tri_and_eqcase.out | 12 +- test_regress/t/t_tri_and_eqcase.v | 21 +- test_regress/t/t_tri_array.out | 12 +- test_regress/t/t_tri_array.v | 108 +- test_regress/t/t_tri_array_bufif.v | 181 ++-- test_regress/t/t_tri_array_pull.v | 53 +- test_regress/t/t_tri_compass_bad.out | 8 +- test_regress/t/t_tri_compass_bad.v | 28 +- test_regress/t/t_tri_cond_eqcase_with_1.v | 24 +- test_regress/t/t_tri_dangle.v | 51 +- test_regress/t/t_tri_eqcase.v | 197 ++-- test_regress/t/t_tri_eqcase_input.v | 23 +- test_regress/t/t_tri_gate.v | 34 +- test_regress/t/t_tri_gen.v | 59 +- test_regress/t/t_tri_graph.v | 22 +- test_regress/t/t_tri_ifbegin.v | 67 +- test_regress/t/t_tri_inout.v | 149 +-- test_regress/t/t_tri_inout2.v | 95 +- test_regress/t/t_tri_inz.v | 21 +- test_regress/t/t_tri_no_top.v | 68 +- test_regress/t/t_tri_public.v | 116 ++- test_regress/t/t_tri_pull01.v | 152 +-- test_regress/t/t_tri_pull2_bad.out | 12 +- test_regress/t/t_tri_pull2_bad.v | 22 +- test_regress/t/t_tri_pull_bad.out | 12 +- test_regress/t/t_tri_pull_bad.v | 11 +- test_regress/t/t_tri_pull_implicit.v | 18 +- test_regress/t/t_tri_pull_unsup.out | 24 +- test_regress/t/t_tri_pull_unsup.v | 24 +- test_regress/t/t_tri_pullup.v | 19 +- test_regress/t/t_tri_pullvec_bad.out | 24 +- test_regress/t/t_tri_pullvec_bad.v | 25 +- test_regress/t/t_tri_select.v | 25 +- test_regress/t/t_tri_select_eqcase.v | 33 +- test_regress/t/t_tri_select_unsized.v | 32 +- test_regress/t/t_tri_struct.v | 32 +- test_regress/t/t_tri_struct_packed.out | 2 +- test_regress/t/t_tri_struct_packed.v | 36 +- test_regress/t/t_tri_top_en_out.v | 344 +++---- test_regress/t/t_tri_unconn.v | 186 ++-- test_regress/t/t_tri_various.v | 78 +- test_regress/t/t_type.v | 58 +- test_regress/t/t_type_array.v | 22 +- test_regress/t/t_type_compare.v | 94 +- test_regress/t/t_type_compare_bad.out | 6 +- test_regress/t/t_type_compare_bad.v | 18 +- test_regress/t/t_type_match.v | 88 +- test_regress/t/t_type_non_type.v | 40 +- test_regress/t/t_type_param.v | 213 ++-- test_regress/t/t_type_param_circ_bad.out | 14 +- test_regress/t/t_type_param_circ_bad.v | 17 +- test_regress/t/t_typedef_array.v | 28 +- test_regress/t/t_typedef_consistency_0.v | 38 +- test_regress/t/t_typedef_fwd_nested.v | 59 +- test_regress/t/t_typedef_no_bad.out | 6 +- test_regress/t/t_typedef_no_bad.v | 2 +- test_regress/t/t_typedef_param.v | 157 +-- test_regress/t/t_typedef_port.v | 153 +-- test_regress/t/t_typedef_signed.v | 119 +-- test_regress/t/t_typename.v | 123 +-- test_regress/t/t_typename_min.v | 42 +- test_regress/t/t_udp_bad.out | 24 +- test_regress/t/t_udp_bad.v | 20 +- test_regress/t/t_udp_bad_comb_trigger.out | 8 +- test_regress/t/t_udp_bad_comb_trigger.v | 26 +- test_regress/t/t_udp_bad_first_input.out | 6 +- test_regress/t/t_udp_bad_first_input.v | 26 +- test_regress/t/t_udp_bad_illegal_output.out | 52 +- test_regress/t/t_udp_bad_illegal_output.v | 50 +- test_regress/t/t_udp_bad_input_num.out | 6 +- test_regress/t/t_udp_bad_input_num.v | 26 +- test_regress/t/t_udp_bad_multi_output.out | 6 +- test_regress/t/t_udp_bad_multi_output.v | 26 +- test_regress/t/t_udp_noname.v | 66 +- test_regress/t/t_udp_param_bad.v | 20 +- test_regress/t/t_udp_sequential.v | 108 +- test_regress/t/t_udp_sequential_bad.out | 8 +- test_regress/t/t_udp_sequential_bad.v | 29 +- test_regress/t/t_unbounded_bad.out | 14 +- test_regress/t/t_unbounded_bad.v | 6 +- test_regress/t/t_unconnected.v | 59 +- test_regress/t/t_union_hard_bad.out | 6 +- test_regress/t/t_union_hard_bad.v | 31 +- test_regress/t/t_union_soft.v | 48 +- test_regress/t/t_union_unpacked.v | 30 +- test_regress/t/t_uniqueif.v | 137 ++- test_regress/t/t_uniqueif_fail1.out | 4 +- test_regress/t/t_uniqueif_fail2.out | 4 +- test_regress/t/t_uniqueif_fail3.out | 4 +- test_regress/t/t_uniqueif_fail4.out | 4 +- test_regress/t/t_unopt_array.v | 138 +-- test_regress/t/t_unopt_bound.v | 43 +- test_regress/t/t_unopt_combo.v | 224 ++--- test_regress/t/t_unopt_combo_bad.out | 16 +- test_regress/t/t_unopt_converge.v | 26 +- test_regress/t/t_unopt_converge_initial.v | 26 +- test_regress/t/t_unopt_converge_unopt_bad.out | 12 +- test_regress/t/t_unoptflat_simple.v | 26 +- test_regress/t/t_unoptflat_simple_2.v | 36 +- test_regress/t/t_unoptflat_simple_2_bad.out | 16 +- test_regress/t/t_unoptflat_simple_3.v | 94 +- test_regress/t/t_unoptflat_simple_3_bad.out | 16 +- test_regress/t/t_unoptflat_simple_bad.out | 12 +- test_regress/t/t_unpack_array_no_expand.v | 51 +- test_regress/t/t_unpacked_array_order.v | 38 +- test_regress/t/t_unpacked_array_p_fmt.v | 24 +- test_regress/t/t_unpacked_concat.v | 156 +-- test_regress/t/t_unpacked_concat_bad.out | 12 +- test_regress/t/t_unpacked_concat_bad.v | 24 +- test_regress/t/t_unpacked_concat_bad2.out | 22 +- test_regress/t/t_unpacked_concat_bad2.v | 34 +- test_regress/t/t_unpacked_concat_bad3.out | 12 +- test_regress/t/t_unpacked_concat_bad3.v | 10 +- test_regress/t/t_unpacked_init.v | 44 +- test_regress/t/t_unpacked_slice.v | 86 +- test_regress/t/t_unpacked_slice_range.v | 104 +- test_regress/t/t_unpacked_str_init.v | 38 +- test_regress/t/t_unpacked_str_init2.v | 50 +- test_regress/t/t_unpacked_str_pair.v | 63 +- test_regress/t/t_unpacked_struct_eq.v | 83 +- test_regress/t/t_unpacked_struct_redef.v | 30 +- test_regress/t/t_unpacked_struct_sel.v | 18 +- test_regress/t/t_unpacked_to_packed_param.v | 35 +- test_regress/t/t_unpacked_to_queue.v | 152 ++- test_regress/t/t_unroll_complexcond.v | 59 +- test_regress/t/t_unroll_delay.v | 34 +- test_regress/t/t_unroll_forfor.v | 42 +- test_regress/t/t_unroll_genf.v | 25 +- test_regress/t/t_unroll_pragma.v | 44 +- test_regress/t/t_unroll_signed.v | 255 +++-- test_regress/t/t_unroll_unopt_io.v | 30 +- test_regress/t/t_upd_nonsequential.v | 111 +-- test_regress/t/t_urandom.v | 128 +-- test_regress/t/t_user_type_xassign.v | 53 +- test_regress/t/t_vams_basic.v | 76 +- test_regress/t/t_vams_kwd_bad.out | 396 ++++---- test_regress/t/t_vams_kwd_bad.v | 132 +-- test_regress/t/t_vams_wreal.v | 207 ++-- test_regress/t/t_var_assign_landr.v | 136 +-- test_regress/t/t_var_bad_hide.out | 22 +- test_regress/t/t_var_bad_hide.v | 27 +- test_regress/t/t_var_bad_hide2.out | 6 +- test_regress/t/t_var_bad_hide2.v | 14 +- test_regress/t/t_var_bad_sameas.out | 54 +- test_regress/t/t_var_bad_sameas.v | 27 +- test_regress/t/t_var_bad_sv.out | 18 +- test_regress/t/t_var_bad_sv.v | 4 +- test_regress/t/t_var_const.v | 29 +- test_regress/t/t_var_const_bad.out | 6 +- test_regress/t/t_var_const_bad.v | 23 +- test_regress/t/t_var_dotted1.v | 276 +++--- test_regress/t/t_var_dotted2.v | 214 ++-- test_regress/t/t_var_dotted_dup_bad.out | 12 +- test_regress/t/t_var_dotted_dup_bad.v | 16 +- test_regress/t/t_var_dup2.v | 12 +- test_regress/t/t_var_dup2_bad.out | 48 +- test_regress/t/t_var_dup2_bad.v | 20 +- test_regress/t/t_var_dup3.v | 32 +- test_regress/t/t_var_dup_bad.out | 216 ++-- test_regress/t/t_var_dup_bad.v | 98 +- test_regress/t/t_var_escape.v | 120 +-- test_regress/t/t_var_in_assign.v | 98 +- test_regress/t/t_var_in_assign_bad.out | 12 +- test_regress/t/t_var_in_assign_bad.v | 26 +- test_regress/t/t_var_init.v | 41 +- test_regress/t/t_var_local.v | 102 +- test_regress/t/t_var_nonamebegin.v | 121 ++- test_regress/t/t_var_notfound_bad.out | 38 +- test_regress/t/t_var_notfound_bad.v | 39 +- test_regress/t/t_var_outoforder.v | 114 +-- test_regress/t/t_var_overcmp.v | 244 ++--- test_regress/t/t_var_overwidth_bad.v | 17 +- test_regress/t/t_var_overzero.v | 290 +++--- test_regress/t/t_var_pinsizes.v | 157 ++- test_regress/t/t_var_port2_bad.out | 12 +- test_regress/t/t_var_port2_bad.v | 6 +- test_regress/t/t_var_port_bad.out | 6 +- test_regress/t/t_var_port_bad.v | 21 +- test_regress/t/t_var_ref.v | 132 +-- test_regress/t/t_var_ref_bad1.out | 8 +- test_regress/t/t_var_ref_bad1.v | 9 +- test_regress/t/t_var_ref_bad2.out | 12 +- test_regress/t/t_var_ref_bad2.v | 22 +- test_regress/t/t_var_ref_bad3.out | 6 +- test_regress/t/t_var_ref_bad3.v | 4 +- test_regress/t/t_var_ref_static.out | 12 +- test_regress/t/t_var_ref_static.v | 10 +- test_regress/t/t_var_rsvd.v | 34 +- test_regress/t/t_var_rsvd_bad.out | 12 +- test_regress/t/t_var_rsvd_port.v | 24 +- test_regress/t/t_var_sc_bv.v | 394 ++++---- test_regress/t/t_var_sc_double.v | 16 +- test_regress/t/t_var_set_link.v | 34 +- test_regress/t/t_var_static.v | 237 +++-- test_regress/t/t_var_static_param.v | 45 +- test_regress/t/t_var_suggest_bad.out | 14 +- test_regress/t/t_var_suggest_bad.v | 13 +- test_regress/t/t_var_tieout.v | 63 +- test_regress/t/t_var_top_struct.v | 34 +- test_regress/t/t_var_types.v | 360 +++---- test_regress/t/t_var_types_bad.out | 40 +- test_regress/t/t_var_types_bad.v | 85 +- test_regress/t/t_var_vec_sel.v | 32 +- test_regress/t/t_var_xref_bad.out | 6 +- test_regress/t/t_var_xref_bad.v | 6 +- test_regress/t/t_var_xref_gen.v | 51 +- test_regress/t/t_varref_scope_in_interface.v | 8 +- test_regress/t/t_verilated_all.v | 55 +- test_regress/t/t_verilated_debug.v | 31 +- test_regress/t/t_verilated_header.v | 14 +- test_regress/t/t_virtual_interface_delayed.v | 46 +- .../t/t_virtual_interface_member_trigger.v | 116 +-- .../t_virtual_interface_member_trigger_real.v | 216 ++-- test_regress/t/t_virtual_interface_pkg.v | 79 +- test_regress/t/t_vlt_match_contents.out | 8 +- test_regress/t/t_vlt_match_contents.v | 4 +- test_regress/t/t_vlt_match_error.v | 20 +- test_regress/t/t_vlt_match_error_1.out | 6 +- test_regress/t/t_vlt_match_error_2.out | 6 +- test_regress/t/t_vlt_match_error_3.out | 6 +- test_regress/t/t_vlt_warn.v | 28 +- test_regress/t/t_vlt_warn_bad.out | 6 +- test_regress/t/t_vlt_warn_file_bad.out | 6 +- test_regress/t/t_vlt_warn_file_bad.v | 4 +- test_regress/t/t_vpi_cb_iter.v | 32 +- test_regress/t/t_vpi_const_type.v | 36 +- test_regress/t/t_vpi_dump.v | 163 +-- test_regress/t/t_vpi_dump_missing_scopes.v | 36 +- test_regress/t/t_vpi_escape.v | 136 +-- test_regress/t/t_vpi_finish.v | 10 +- test_regress/t/t_vpi_get.v | 74 +- test_regress/t/t_vpi_get_value_array.v | 118 +-- test_regress/t/t_vpi_memory.v | 74 +- test_regress/t/t_vpi_module.v | 138 +-- test_regress/t/t_vpi_module_empty.v | 18 +- test_regress/t/t_vpi_multidim.v | 40 +- test_regress/t/t_vpi_package.v | 43 +- test_regress/t/t_vpi_param.v | 32 +- test_regress/t/t_vpi_public_depth.v | 140 +-- test_regress/t/t_vpi_public_params.v | 32 +- test_regress/t/t_vpi_put_value_array.v | 74 +- test_regress/t/t_vpi_release_dup_bad.v | 10 +- test_regress/t/t_vpi_repetitive_cbs.v | 23 +- test_regress/t/t_vpi_sc.v | 12 +- test_regress/t/t_vpi_stop_bad.v | 14 +- test_regress/t/t_vpi_time_cb.v | 42 +- test_regress/t/t_vpi_unimpl.v | 35 +- test_regress/t/t_vpi_var.v | 302 +++--- test_regress/t/t_vpi_var2.v | 308 +++--- test_regress/t/t_vpi_var3.v | 298 +++--- test_regress/t/t_vpi_zero_time_cb.v | 36 +- 1199 files changed, 39894 insertions(+), 39281 deletions(-) diff --git a/docs/gen/ex_PINMISSING_faulty.rst b/docs/gen/ex_PINMISSING_faulty.rst index a8172dea9..85f6f0580 100644 --- a/docs/gen/ex_PINMISSING_faulty.rst +++ b/docs/gen/ex_PINMISSING_faulty.rst @@ -4,8 +4,8 @@ :emphasize-lines: 2 module t; - sub sub(); // <--- Warning - endmodule - module sub - (output port); + sub sub (); // <--- Warning endmodule + module sub ( + output port + ); diff --git a/docs/gen/ex_PINMISSING_msg.rst b/docs/gen/ex_PINMISSING_msg.rst index eef3cdb1a..f469307ae 100644 --- a/docs/gen/ex_PINMISSING_msg.rst +++ b/docs/gen/ex_PINMISSING_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_lint_pinmissing_bad .. code-block:: - %Warning-PINMISSING: example.v:1:8 Instance has missing pin: 'port' + %Warning-PINMISSING: example.v:1:7 Instance has missing pin: 'port' diff --git a/test_regress/t/t_class_new_scoped.v b/test_regress/t/t_class_new_scoped.v index 620e2c524..005fccc9a 100644 --- a/test_regress/t/t_class_new_scoped.v +++ b/test_regress/t/t_class_new_scoped.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on class Base; int m_ia = 10; diff --git a/test_regress/t/t_class_param_bad_paren.out b/test_regress/t/t_class_param_bad_paren.out index 481229934..f1c1f267f 100644 --- a/test_regress/t/t_class_param_bad_paren.out +++ b/test_regress/t/t_class_param_bad_paren.out @@ -1,6 +1,6 @@ -%Error: t/t_class_param_bad_paren.v:28:11: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) - : ... Suggest use 'Cls#()' - 28 | if (Cls::OTHER != 12) $stop; - | ^~~ +%Error: t/t_class_param_bad_paren.v:30:9: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) + : ... Suggest use 'Cls#()' + 30 | if (Cls::OTHER != 12) $stop; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_param_bad_paren.v b/test_regress/t/t_class_param_bad_paren.v index 8f943d2a8..297c5cdf8 100644 --- a/test_regress/t/t_class_param_bad_paren.v +++ b/test_regress/t/t_class_param_bad_paren.v @@ -4,11 +4,13 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Cls #(int PARAM = 1); - parameter OTHER = 12; +class Cls #( + int PARAM = 1 +); + parameter OTHER = 12; endclass -class Other extends Cls#(); // Ok +class Other extends Cls #(); // Ok endclass class OtherMaybe extends Cls; // Questionable but others do not warn @@ -16,16 +18,16 @@ endclass module t; - typedef Cls#(2) Cls2_t; // Ok - typedef Cls ClsNone_t; // Ok + typedef Cls#(2) Cls2_t; // Ok + typedef Cls ClsNone_t; // Ok - Cls c; // Ok + Cls c; // Ok - initial begin - if (Cls#()::OTHER != 12) $stop; // Ok - if (Cls2_t::OTHER != 12) $stop; // ok + initial begin + if (Cls#()::OTHER != 12) $stop; // Ok + if (Cls2_t::OTHER != 12) $stop; // ok - if (Cls::OTHER != 12) $stop; // Bad #() required - end + if (Cls::OTHER != 12) $stop; // Bad #() required + end endmodule diff --git a/test_regress/t/t_clocking_out_on_change.v b/test_regress/t/t_clocking_out_on_change.v index 63e35e1a7..1fba170db 100644 --- a/test_regress/t/t_clocking_out_on_change.v +++ b/test_regress/t/t_clocking_out_on_change.v @@ -5,57 +5,59 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic clk = 0; - initial forever #5 clk = ~clk; - int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 4) begin - $write("*-* All Finished *-*\n"); - $finish(); - end - end + logic clk = 0; + initial forever #5 clk = ~clk; + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end - // Skew 0 - logic ok1 = 1; - always @(posedge clk) - if (cyc == 0) begin - if (!ok1) $stop; - #1 cb.ok1 <= 0; - #1 if (!ok1) $stop; - end else if (cyc == 1) begin - if (!ok1) $stop; - #1 if (ok1) $stop; - end - else if (cyc == 2) ok1 <= 1; - else if (!ok1) $stop; + // Skew 0 + logic ok1 = 1; + always @(posedge clk) + if (cyc == 0) begin + if (!ok1) $stop; + #1 cb.ok1 <= 0; + #1 if (!ok1) $stop; + end + else if (cyc == 1) begin + if (!ok1) $stop; + #1 if (ok1) $stop; + end + else if (cyc == 2) ok1 <= 1; + else if (!ok1) $stop; - // Skew > 0 - logic ok2 = 1; - always @(posedge clk) - if (cyc == 0) begin - if (!ok2) $stop; - #1 cb.ok2 <= 0; - #2 if (!ok2) $stop; - #3 if (!ok2) $stop; - end else if (cyc == 1) begin - if (!ok2) $stop; - #1 if (!ok2) $stop; - #2 if (ok2) $stop; - end - else if (cyc == 2) ok2 <= 1; - else if (!ok2) $stop; + // Skew > 0 + logic ok2 = 1; + always @(posedge clk) + if (cyc == 0) begin + if (!ok2) $stop; + #1 cb.ok2 <= 0; + #2 if (!ok2) $stop; + #3 if (!ok2) $stop; + end + else if (cyc == 1) begin + if (!ok2) $stop; + #1 if (!ok2) $stop; + #2 if (ok2) $stop; + end + else if (cyc == 2) ok2 <= 1; + else if (!ok2) $stop; - // No timing - logic ok3 = 0; - always @(posedge clk) - if (cyc == 0) ok3 <= 1; - else if (cyc == 1) if (!ok3) $stop; + // No timing + logic ok3 = 0; + always @(posedge clk) + if (cyc == 0) ok3 <= 1; + else if (cyc == 1) if (!ok3) $stop; - // Clocking (used in all tests) - clocking cb @(posedge clk); - output ok1; - output #1 ok2; - output ok3; - endclocking + // Clocking (used in all tests) + clocking cb @(posedge clk); + output ok1; + output #1 ok2; + output ok3; + endclocking endmodule diff --git a/test_regress/t/t_constraint_state.v b/test_regress/t/t_constraint_state.v index 6a6af40ac..b7cb13c74 100644 --- a/test_regress/t/t_constraint_state.v +++ b/test_regress/t/t_constraint_state.v @@ -7,71 +7,71 @@ `define check_rand(cl, field, cond) \ begin \ - automatic longint prev_result; \ - automatic int ok; \ - if (!bit'(cl.randomize())) $stop; \ - prev_result = longint'(field); \ - if (!(cond)) $stop; \ - repeat(9) begin \ - longint result; \ - if (!bit'(cl.randomize())) $stop; \ - result = longint'(field); \ - if (!(cond)) $stop; \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end class Foo; - int x; + int x; endclass class Bar; - rand int y; + rand int y; endclass class Packet; - rand int rf; - int state; - rand int a; - rand Foo foo; - Bar bar; + rand int rf; + int state; + rand int a; + rand Foo foo; + Bar bar; - constraint c1 { rf == state; } - constraint c2 { a > foo.x; a < bar.y; } + constraint c1 { rf == state; } + constraint c2 { a > foo.x; a < bar.y; } - function new(int s, int x, int y); - state = s; - foo = new; - foo.x = x; - bar = new; - bar.y = y; - endfunction + function new(int s, int x, int y); + state = s; + foo = new; + foo.x = x; + bar = new; + bar.y = y; + endfunction endclass module t; - Packet p; + Packet p; - int v; + int v; - initial begin - p = new(123, 10, 20); - v = p.randomize(); - if (v != 1) $stop; - if (p.rf != 123) $stop; + initial begin + p = new(123, 10, 20); + v = p.randomize(); + if (v != 1) $stop; + if (p.rf != 123) $stop; - `check_rand(p, p.a, p.a > 10 && p.a < 20) - if (p.foo.x != 10) $stop; - if (p.bar.y != 20) $stop; + `check_rand(p, p.a, p.a > 10 && p.a < 20) + if (p.foo.x != 10) $stop; + if (p.bar.y != 20) $stop; - p.state = 234; - v = p.randomize(); - if (v != 1) $stop; - if (p.rf != 234) $stop; + p.state = 234; + v = p.randomize(); + if (v != 1) $stop; + if (p.rf != 234) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_parameter.v b/test_regress/t/t_flag_parameter.v index 7ef322eff..a37b828a3 100644 --- a/test_regress/t/t_flag_parameter.v +++ b/test_regress/t/t_flag_parameter.v @@ -20,9 +20,10 @@ // | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D| // | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED | +// verilog_format: off `define stop $stop -`define check(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0); +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0); +// verilog_format: on typedef enum logic [1:0] { enum_val_0 = 2'd0, diff --git a/test_regress/t/t_flag_parameter_hier.v b/test_regress/t/t_flag_parameter_hier.v index 78cfc5a77..94d671930 100644 --- a/test_regress/t/t_flag_parameter_hier.v +++ b/test_regress/t/t_flag_parameter_hier.v @@ -4,9 +4,10 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); +// verilog_format: on module t ( input clk diff --git a/test_regress/t/t_flag_topmodule.v b/test_regress/t/t_flag_topmodule.v index 68d3bd085..68b9b3b54 100644 --- a/test_regress/t/t_flag_topmodule.v +++ b/test_regress/t/t_flag_topmodule.v @@ -5,34 +5,34 @@ // SPDX-License-Identifier: CC0-1.0 module a; - c c (); - initial begin - $write("Bad top modules\n"); - $stop; - end + c c (); + initial begin + $write("Bad top modules\n"); + $stop; + end endmodule module a2; - initial begin - $write("Bad top modules\n"); - $stop; - end + initial begin + $write("Bad top modules\n"); + $stop; + end endmodule module b; - d d (); + d d (); endmodule module c; - initial begin - $write("Bad mid modules\n"); - $stop; - end + initial begin + $write("Bad mid modules\n"); + $stop; + end endmodule module d; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_topmodule_inline.v b/test_regress/t/t_flag_topmodule_inline.v index f27b3f2ea..96aac3d7a 100644 --- a/test_regress/t/t_flag_topmodule_inline.v +++ b/test_regress/t/t_flag_topmodule_inline.v @@ -5,26 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 module a; - a2 a2 (.tmp(1'b0)); - initial begin - $write("Bad top modules\n"); - $stop; - end + a2 a2 (.tmp(1'b0)); + initial begin + $write("Bad top modules\n"); + $stop; + end endmodule -module a2 (input tmp); - l3 l3 (.tmp(tmp)); +module a2 ( + input tmp +); + l3 l3 (.tmp(tmp)); endmodule module b; - l3 l3 (.tmp(1'b1)); + l3 l3 (.tmp(1'b1)); endmodule -module l3 (input tmp); - initial begin - if (tmp) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end +module l3 ( + input tmp +); + initial begin + if (tmp) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_func_arg_complex.v b/test_regress/t/t_func_arg_complex.v index 816166d96..a608132ca 100644 --- a/test_regress/t/t_func_arg_complex.v +++ b/test_regress/t/t_func_arg_complex.v @@ -4,9 +4,10 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkd(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; enum { diff --git a/test_regress/t/t_func_const3_bad.out b/test_regress/t/t_func_const3_bad.out index 4c996d982..bddad7985 100644 --- a/test_regress/t/t_func_const3_bad.out +++ b/test_regress/t/t_func_const3_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: Replication of more that --replication-limit 8192 is suspect: 9000 +%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:13:27: Replication of more that --replication-limit 8192 is suspect: 9000 : ... note: In instance 't.b9k.c9' - 12 | localparam SOMEP = {BITS{1'b0}}; - | ^ + 13 | localparam SOMEP = {BITS{1'b0}}; + | ^ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_const3_bad.v b/test_regress/t/t_func_const3_bad.v index 65a46a6c1..5e81e6a38 100644 --- a/test_regress/t/t_func_const3_bad.v +++ b/test_regress/t/t_func_const3_bad.v @@ -4,34 +4,36 @@ // SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module c9 - #(parameter A = 1, - parameter B = 1); +module c9 #( + parameter A = 1, + parameter B = 1 +); - localparam BITS = A*B; - localparam SOMEP = {BITS{1'b0}}; + localparam BITS = A * B; + localparam SOMEP = {BITS{1'b0}}; endmodule -module b9 - #(parameter A = 1); +module b9 #( + parameter A = 1 +); - c9 - #(.A (A), - .B (9)) - c9(); + c9 #( + .A(A), + .B(9) + ) c9 (); endmodule module t; - b9 b9(); - b9 #(.A (100)) b900(); - b9 #(.A (1000)) b9k(); + b9 b9 (); + b9 #(.A(100)) b900 (); + b9 #(.A(1000)) b9k (); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_hier_block.v b/test_regress/t/t_hier_block.v index 16bc20b2f..664007531 100644 --- a/test_regress/t/t_hier_block.v +++ b/test_regress/t/t_hier_block.v @@ -26,9 +26,9 @@ logic global_flag = 1'b0; `endif interface byte_ifs(input clk); - logic [7:0] data; - modport sender(input clk, output data); - modport receiver(input clk, input data); + logic [7:0] data; + modport sender(input clk, output data); + modport receiver(input clk, input data); endinterface; typedef enum logic [1:0] { @@ -47,74 +47,74 @@ typedef enum logic [1:0] { `ifdef AS_PROT_LIB module secret ( - clk - ); + clk + ); `else module t #( parameter int PARAM_A = 33, parameter int PARAM_B = 44 ) (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `endif - input clk; + input clk; `ifdef PROTLIB_TOP - secret i_secred(.clk(clk)); + secret i_secred(.clk(clk)); `else - wire [7:0] out0; - wire [7:0] out1; - wire [7:0] out2; - wire [7:0] out3; - wire [7:0] out3_2; - wire [7:0] out5; - wire [7:0] out6; - int count = 0; + wire [7:0] out0; + wire [7:0] out1; + wire [7:0] out2; + wire [7:0] out3; + wire [7:0] out3_2; + wire [7:0] out5; + wire [7:0] out6; + int count = 0; - non_hier_sub0 i_sub0(.clk(clk), .in(out3), .out(out0)); - sub1 i_sub1(.clk(clk), .in(out0), .out(out1)); - sub2 i_sub2(.clk(clk), .in(out1), .out(out2)); - sub3 #(.P0(1)) i_sub3(.clk(clk), .in(out2), .out(out3)); - // Must not use the same wrapper - sub3 #(.STR("abc"), .P0(1)) i_sub3_2(.clk(clk), .in(out2), .out(out3_2)); - delay #(.N(2), 8) i_delay0(clk, out3, out5); - delay #(.N(3), 8) i_delay1(clk, out5, out6); + non_hier_sub0 i_sub0(.clk(clk), .in(out3), .out(out0)); + sub1 i_sub1(.clk(clk), .in(out0), .out(out1)); + sub2 i_sub2(.clk(clk), .in(out1), .out(out2)); + sub3 #(.P0(1)) i_sub3(.clk(clk), .in(out2), .out(out3)); + // Must not use the same wrapper + sub3 #(.STR("abc"), .P0(1)) i_sub3_2(.clk(clk), .in(out2), .out(out3_2)); + delay #(.N(2), 8) i_delay0(clk, out3, out5); + delay #(.N(3), 8) i_delay1(clk, out5, out6); - always_ff @(posedge clk) begin - if (out3 != out3_2) $stop; + always_ff @(posedge clk) begin + if (out3 != out3_2) $stop; `ifndef AS_PROT_LIB `ifdef PARAM_OVERRIDE - if (PARAM_A != 100) $stop; - if (PARAM_B != 200) $stop; + if (PARAM_A != 100) $stop; + if (PARAM_B != 200) $stop; `else - if (PARAM_A != 33) $stop; - if (PARAM_B != 44) $stop; + if (PARAM_A != 33) $stop; + if (PARAM_B != 44) $stop; `endif `endif - $display("%d %m out0:%d %d %d %d %d", count, out0, out1, out2, out3, out5, out6); - $display("%d %m child input ports: %d %d %d", count, i_sub1.in, i_sub2.in, i_sub3.in); - $display("%d %m child output ports: %d %d %d", count, i_sub1.out, i_sub2.out, i_sub3.out); - if (count == 16) begin - if (out6 == 19) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - $write("Missmatch\n"); - $stop; - end + $display("%d %m out0:%d %d %d %d %d", count, out0, out1, out2, out3, out5, out6); + $display("%d %m child input ports: %d %d %d", count, i_sub1.in, i_sub2.in, i_sub3.in); + $display("%d %m child output ports: %d %d %d", count, i_sub1.out, i_sub2.out, i_sub3.out); + if (count == 16) begin + if (out6 == 19) begin + $write("*-* All Finished *-*\n"); + $finish; + end else begin + $write("Missmatch\n"); + $stop; end - count <= count + 1; + end + count <= count + 1; `ifdef STATEFUL_PKG - global_flag <= ~global_flag; + global_flag <= ~global_flag; `endif - end + end `ifdef CPP_MACRO - initial begin - $display("Macro for C++ compiler is defined for Verilator"); - $stop; - end + initial begin + $display("Macro for C++ compiler is defined for Verilator"); + $stop; + end `endif `systemc_implementation @@ -123,9 +123,9 @@ module t #( #define STRINGIFY(str) STRINGIFY_IMPL(str) namespace { struct statically_initialized { - statically_initialized() { - std::cout << "MACRO:" << STRINGIFY(CPP_MACRO) << " is defined" << std::endl; - } + statically_initialized() { + std::cout << "MACRO:" << STRINGIFY(CPP_MACRO) << " is defined" << std::endl; + } } g_statically_initialized; } `verilog @@ -135,285 +135,285 @@ struct statically_initialized { endmodule module non_hier_sub0( - input wire clk, - input wire[7:0] in, - output wire [7:0] out); + input wire clk, + input wire[7:0] in, + output wire [7:0] out); - sub0 i_sub0(.*); + sub0 i_sub0(.*); endmodule module sub0( - input wire clk, - input wire [7:0] in, - output wire [7:0] out); `HIER_BLOCK + input wire clk, + input wire [7:0] in, + output wire [7:0] out); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - logic [7:0] ff; + logic [7:0] ff; - always_ff @(posedge clk) ff <= in; - assign out = ff; + always_ff @(posedge clk) ff <= in; + assign out = ff; `ifdef STATEFUL_PKG - always_ff @(posedge clk) if (ff[0]) global_flag <= ff[1]; + always_ff @(posedge clk) if (ff[0]) global_flag <= ff[1]; `endif endmodule module sub1( - input wire clk, - input wire [11:4] in, // Uses higher LSB to cover bug3539 - output wire [7:0] out); `HIER_BLOCK + input wire clk, + input wire [11:4] in, // Uses higher LSB to cover bug3539 + output wire [7:0] out); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - logic [7:0] ff; - enum_t enum_v; + logic [7:0] ff; + enum_t enum_v; - always_ff @(posedge clk) ff <= in + 8'(stateless_pkg::ONE); - always_ff @(posedge clk) enum_v <= enum_v.next(); - assign out = ff; + always_ff @(posedge clk) ff <= in + 8'(stateless_pkg::ONE); + always_ff @(posedge clk) enum_v <= enum_v.next(); + assign out = ff; endmodule module sub2( - input wire clk, - input wire [7:0] in, - output wire [7:0] out); `HIER_BLOCK + input wire clk, + input wire [7:0] in, + output wire [7:0] out); `HIER_BLOCK - logic [7:0] ff; - alt_enum_t alt_enum_v; + logic [7:0] ff; + alt_enum_t alt_enum_v; - // dpi_import_func returns (dpi_eport_func(v) -1) - import "DPI-C" context function int dpi_import_func(int v); - export "DPI-C" function dpi_export_func; + // dpi_import_func returns (dpi_eport_func(v) -1) + import "DPI-C" context function int dpi_import_func(int v); + export "DPI-C" function dpi_export_func; - function int dpi_export_func(int v); - return v + 1; - endfunction + function int dpi_export_func(int v); + return v + 1; + endfunction - always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2; - always_ff @(posedge clk) alt_enum_v <= alt_enum_v.next(); + always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2; + always_ff @(posedge clk) alt_enum_v <= alt_enum_v.next(); - byte_ifs in_ifs(.clk(clk)); - byte_ifs out_ifs(.clk(clk)); - assign in_ifs.data = ff; - assign out = out_ifs.data; - non_hier_sub3 i_sub3(.in(in_ifs), .out(out_ifs)); + byte_ifs in_ifs(.clk(clk)); + byte_ifs out_ifs(.clk(clk)); + assign in_ifs.data = ff; + assign out = out_ifs.data; + non_hier_sub3 i_sub3(.in(in_ifs), .out(out_ifs)); - always @(posedge clk) - // dotted access within a hierarchical block should be OK - if (i_sub3.in_wire != ff) begin - $display("Error mismatch in %m"); - $stop; - end + always @(posedge clk) + // dotted access within a hierarchical block should be OK + if (i_sub3.in_wire != ff) begin + $display("Error mismatch in %m"); + $stop; + end endmodule module non_hier_sub3( - byte_ifs.receiver in, - byte_ifs.sender out); + byte_ifs.receiver in, + byte_ifs.sender out); - wire [7:0] in_wire, out_1, out_2; - assign in_wire = in.data; - localparam string sparam = "single quote escape comma:'\\,"; - // Parameter appears in the different order from module declaration - sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3(.clk(in.clk), .in(in.data), .out(out_1)); - // Instantiate again, should use the same wrapper - sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3_2(.clk(in.clk), .in(in.data), .out(out_2)); - always @(posedge in.clk) - if (out_1 != out_2) $stop; + wire [7:0] in_wire, out_1, out_2; + assign in_wire = in.data; + localparam string sparam = "single quote escape comma:'\\,"; + // Parameter appears in the different order from module declaration + sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3(.clk(in.clk), .in(in.data), .out(out_1)); + // Instantiate again, should use the same wrapper + sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3_2(.clk(in.clk), .in(in.data), .out(out_2)); + always @(posedge in.clk) + if (out_1 != out_2) $stop; - assign out.data = out_1; + assign out.data = out_1; endmodule module sub3 #( - parameter logic [7:0] P0 = 2 + 1, - type TYPE = logic, - parameter int UNPACKED_ARRAY[2] = '{0, 1}, - parameter logic signed [15:0] UNUSED = -3, - parameter string STR = "str", - parameter enum_t ENUM = enum_val_0) ( - input wire clk, - input wire [7:0] in, - output wire [7:0] out); `HIER_BLOCK + parameter logic [7:0] P0 = 2 + 1, + type TYPE = logic, + parameter int UNPACKED_ARRAY[2] = '{0, 1}, + parameter logic signed [15:0] UNUSED = -3, + parameter string STR = "str", + parameter enum_t ENUM = enum_val_0) ( + input wire clk, + input wire [7:0] in, + output wire [7:0] out); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM); + initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM); - TYPE [7:0] ff; - always_ff @(posedge clk) ff <= in + P0; - always_ff @(posedge clk) if (out4 != out4_2) $stop; + TYPE [7:0] ff; + always_ff @(posedge clk) ff <= in + P0; + always_ff @(posedge clk) if (out4 != out4_2) $stop; - wire [7:0] out4; - wire [7:0] out4_2; - assign out = out4; - /* verilator lint_off REALCVT */ - sub4 #(.P0(1.6), .P1(3.1), .P3(4.1)) i_sub4_0(.clk(clk), .in(ff), .out(out4)); // incr 2 - sub4 #(.P0(2.4), .P1(3.1), .P3(5)) i_sub4_1(.clk(clk), .in(), .out(out4_2)); - /* verilator lint_on REALCVT */ - /* verilator lint_off ASSIGNIN */ - assign i_sub4_1.in = ff; // Hierarchical reference to port of hier_block is OK - /* verilator lint_off ASSIGNIN */ + wire [7:0] out4; + wire [7:0] out4_2; + assign out = out4; + /* verilator lint_off REALCVT */ + sub4 #(.P0(1.6), .P1(3.1), .P3(4.1)) i_sub4_0(.clk(clk), .in(ff), .out(out4)); // incr 2 + sub4 #(.P0(2.4), .P1(3.1), .P3(5)) i_sub4_1(.clk(clk), .in(), .out(out4_2)); + /* verilator lint_on REALCVT */ + /* verilator lint_off ASSIGNIN */ + assign i_sub4_1.in = ff; // Hierarchical reference to port of hier_block is OK + /* verilator lint_off ASSIGNIN */ - always @(posedge clk) begin - $display("%d %m child input ports: %d %d", $time, i_sub4_0.in, i_sub4_1.in); - $display("%d %m child output ports: %d %d", $time, i_sub4_0.out, i_sub4_1.out); - end + always @(posedge clk) begin + $display("%d %m child input ports: %d %d", $time, i_sub4_0.in, i_sub4_1.in); + $display("%d %m child output ports: %d %d", $time, i_sub4_0.out, i_sub4_1.out); + end endmodule module sub4 #( - parameter int P0 = 1.1, - parameter P1 = 2, - parameter real P3 = 3) ( - input wire clk, - input wire [7:0] in, - output wire[7:0] out); `HIER_BLOCK + parameter int P0 = 1.1, + parameter P1 = 2, + parameter real P3 = 3) ( + input wire clk, + input wire [7:0] in, + output wire[7:0] out); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - initial begin - if (P1 == 2) begin - $display("P1(%f) is not properly set", P1); - $stop; + initial begin + if (P1 == 2) begin + $display("P1(%f) is not properly set", P1); + $stop; + end + end + + reg [7:0] ff; + always_ff @(posedge clk) ff <= in + 8'(P0); + assign out = ff; + + logic [127:0] sub5_in[2][3]; + wire [7:0] sub5_out[2][3]; + sub5 i_sub5(.clk(clk), .in(sub5_in), .out(sub5_out)); + + int count = 0; + always @(posedge clk) begin + if (!count[0]) begin + sub5_in[0][0] <= 128'd0; + sub5_in[0][1] <= 128'd1; + sub5_in[0][2] <= 128'd2; + sub5_in[1][0] <= 128'd3; + sub5_in[1][1] <= 128'd4; + sub5_in[1][2] <= 128'd5; + end else begin + sub5_in[0][0] <= 128'd0; + sub5_in[0][1] <= 128'd0; + sub5_in[0][2] <= 128'd0; + sub5_in[1][0] <= 128'd0; + sub5_in[1][1] <= 128'd0; + sub5_in[1][2] <= 128'd0; + end + end + + int driven_from_bind = 0; + + always @(posedge clk) begin + count <= count + 1; + if (count > 0) begin + for (int i = 0; i < 2; ++i) begin + for (int j = 0; j < 3; ++j) begin + automatic byte exp = !count[0] ? 8'(3 * (1 - i) + (2- j) + 1) : 8'b0; + if (sub5_out[i][j] != exp) begin + $display("in[%d][%d] act:%d exp:%d", i, j, sub5_out[i][j], exp); + $stop; + end + if (i_sub5.out[i][j] != exp) begin + $display("in[%d][%d] act:%d exp:%d", i, j, i_sub5.out[i][j], exp); + $stop; + end + end end - end - reg [7:0] ff; - always_ff @(posedge clk) ff <= in + 8'(P0); - assign out = ff; - - logic [127:0] sub5_in[2][3]; - wire [7:0] sub5_out[2][3]; - sub5 i_sub5(.clk(clk), .in(sub5_in), .out(sub5_out)); - - int count = 0; - always @(posedge clk) begin - if (!count[0]) begin - sub5_in[0][0] <= 128'd0; - sub5_in[0][1] <= 128'd1; - sub5_in[0][2] <= 128'd2; - sub5_in[1][0] <= 128'd3; - sub5_in[1][1] <= 128'd4; - sub5_in[1][2] <= 128'd5; - end else begin - sub5_in[0][0] <= 128'd0; - sub5_in[0][1] <= 128'd0; - sub5_in[0][2] <= 128'd0; - sub5_in[1][0] <= 128'd0; - sub5_in[1][1] <= 128'd0; - sub5_in[1][2] <= 128'd0; + if (driven_from_bind != int'(2*P1)) begin + $display("%m driven_from_bind: %0d != %0d", driven_from_bind, int'(2*P1)); + $stop; end - end - - int driven_from_bind = 0; - - always @(posedge clk) begin - count <= count + 1; - if (count > 0) begin - for (int i = 0; i < 2; ++i) begin - for (int j = 0; j < 3; ++j) begin - automatic byte exp = !count[0] ? 8'(3 * (1 - i) + (2- j) + 1) : 8'b0; - if (sub5_out[i][j] != exp) begin - $display("in[%d][%d] act:%d exp:%d", i, j, sub5_out[i][j], exp); - $stop; - end - if (i_sub5.out[i][j] != exp) begin - $display("in[%d][%d] act:%d exp:%d", i, j, i_sub5.out[i][j], exp); - $stop; - end - end - end - - if (driven_from_bind != int'(2*P1)) begin - $display("%m driven_from_bind: %0d != %0d", driven_from_bind, int'(2*P1)); - $stop; - end - end - end + end + end endmodule module sub5 (input wire clk, input wire [127:0] in[2][3], output logic [7:0] out[2][3]); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - int count = 0; - always @(posedge clk) begin - count <= count + 1; - if (count > 0) begin - for (int i = 0; i < 2; ++i) begin - for (int j = 0; j < 3; ++j) begin - automatic bit [127:0] exp = count[0] ? 128'(3 * i + 128'(j)) : 128'd0; - if (in[i][j] != exp) begin - $display("in[%d][%d] act:%d exp:%d", i, j, in[i][j], exp); - $stop; - end - end - end + int count = 0; + always @(posedge clk) begin + count <= count + 1; + if (count > 0) begin + for (int i = 0; i < 2; ++i) begin + for (int j = 0; j < 3; ++j) begin + automatic bit [127:0] exp = count[0] ? 128'(3 * i + 128'(j)) : 128'd0; + if (in[i][j] != exp) begin + $display("in[%d][%d] act:%d exp:%d", i, j, in[i][j], exp); + $stop; + end + end end - end + end + end - always @(posedge clk) begin - if (count[0]) begin - out[0][0] <= 8'd6; - out[0][1] <= 8'd5; - out[0][2] <= 8'd4; - out[1][0] <= 8'd3; - out[1][1] <= 8'd2; - out[1][2] <= 8'd1; - end else begin - out[0][0] <= 8'd0; - out[0][1] <= 8'd0; - out[0][2] <= 8'd0; - out[1][0] <= 8'd0; - out[1][1] <= 8'd0; - out[1][2] <= 8'd0; - end - end + always @(posedge clk) begin + if (count[0]) begin + out[0][0] <= 8'd6; + out[0][1] <= 8'd5; + out[0][2] <= 8'd4; + out[1][0] <= 8'd3; + out[1][1] <= 8'd2; + out[1][2] <= 8'd1; + end else begin + out[0][0] <= 8'd0; + out[0][1] <= 8'd0; + out[0][2] <= 8'd0; + out[1][0] <= 8'd0; + out[1][1] <= 8'd0; + out[1][2] <= 8'd0; + end + end - wire [7:0] val0[2]; - wire [7:0] val1[2]; - wire [7:0] val2[2]; - wire [7:0] val3[2]; - sub6 i_sub0(.out(val0)); - sub6 #(.P0(1)) i_sub1(.out(val1)); // Setting the default value - sub6 #(.P0(1), .P1(2)) i_sub2(.out(val2)); // Setting the default value - sub6 #(.P0(1), .P1(3)) i_sub3(.out(val3)); + wire [7:0] val0[2]; + wire [7:0] val1[2]; + wire [7:0] val2[2]; + wire [7:0] val3[2]; + sub6 i_sub0(.out(val0)); + sub6 #(.P0(1)) i_sub1(.out(val1)); // Setting the default value + sub6 #(.P0(1), .P1(2)) i_sub2(.out(val2)); // Setting the default value + sub6 #(.P0(1), .P1(3)) i_sub3(.out(val3)); - always @(posedge clk) begin - if (val0[0] != 1 || val0[1] != 2) $stop; - if (val1[0] != 1 || val1[1] != 2) $stop; - if (val2[0] != 1 || val2[1] != 2) $stop; - if (val3[0] != 1 || val3[1] != 3) $stop; - end + always @(posedge clk) begin + if (val0[0] != 1 || val0[1] != 2) $stop; + if (val1[0] != 1 || val1[1] != 2) $stop; + if (val2[0] != 1 || val2[1] != 2) $stop; + if (val3[0] != 1 || val3[1] != 3) $stop; + end endmodule module sub6 #(parameter P0 = 1, parameter P1 = 2) (output wire [7:0] out[2]); `HIER_BLOCK `ifdef NO_INLINE - /* verilator no_inline_module */ + /* verilator no_inline_module */ `endif - assign out[0] = 8'(P0); - assign out[1] = 8'(P1); + assign out[0] = 8'(P0); + assign out[1] = 8'(P1); endmodule module delay #( - parameter N = 1, - parameter WIDTH = 8) ( - input wire clk, - input wire[WIDTH-1:0] in, - output wire [WIDTH-1:0]out); `HIER_BLOCK + parameter N = 1, + parameter WIDTH = 8) ( + input wire clk, + input wire[WIDTH-1:0] in, + output wire [WIDTH-1:0]out); `HIER_BLOCK - reg [WIDTH-1:0] tmp; - always_ff @(posedge clk) tmp <= in; - if (N > 1) begin - delay #(.N(N - 1), WIDTH) i_delay(clk, tmp, out); - end else begin - assign out = tmp; - end + reg [WIDTH-1:0] tmp; + always_ff @(posedge clk) tmp <= in; + if (N > 1) begin + delay #(.N(N - 1), WIDTH) i_delay(clk, tmp, out); + end else begin + assign out = tmp; + end endmodule // Module bound into parametrized hier_block that undergoes name mangling diff --git a/test_regress/t/t_inside3.v b/test_regress/t/t_inside3.v index 0629c8bb1..db488ce1e 100644 --- a/test_regress/t/t_inside3.v +++ b/test_regress/t/t_inside3.v @@ -14,24 +14,24 @@ class Foo; endclass module t; - Foo foo; - Foo array[100]; - Foo res[$]; - initial begin - foo = new; - for (int i = 0; i < 100; ++i) begin - array[i] = new; - end - if (!(foo.get() inside {3,4,5,6,7,8,9})) $stop; - if (foo.callCount != 1) $stop; - if (!(foo.get() inside {[3:9]})) $stop; - if (foo.callCount != 2) $stop; - res = array.find(x) with (x.get() inside {5,7,8,9}); - if (res.size() != 0) $stop; - for (int i = 0; i < 100; ++i) begin - if (array[i].callCount != 1) $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + Foo foo; + Foo array[100]; + Foo res[$]; + initial begin + foo = new; + for (int i = 0; i < 100; ++i) begin + array[i] = new; + end + if (!(foo.get() inside {3, 4, 5, 6, 7, 8, 9})) $stop; + if (foo.callCount != 1) $stop; + if (!(foo.get() inside {[3 : 9]})) $stop; + if (foo.callCount != 2) $stop; + res = array.find(x) with (x.get() inside {5, 7, 8, 9}); + if (res.size() != 0) $stop; + for (int i = 0; i < 100; ++i) begin + if (array[i].callCount != 1) $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_langext_1.v b/test_regress/t/t_langext_1.v index c2d68eff0..2f2508e14 100644 --- a/test_regress/t/t_langext_1.v +++ b/test_regress/t/t_langext_1.v @@ -12,40 +12,41 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + // Inputs + clk +); + input clk; - wire [1:0] res; + wire [1:0] res; - // Instantiate the test - test test_i (// Outputs - .res (res[1:0]), - // Inputs - .clk (clk), - .in (1'b1)); + // Instantiate the test + test test_i ( // Outputs + .res(res[1:0]), + // Inputs + .clk(clk), + .in(1'b1) + ); endmodule -module test (// Outputs - res, - // Inputs - clk, - in - ); - output reg [1:0] res; - input clk; - input in; +module test ( // Outputs + res, + // Inputs + clk, + in +); + output reg [1:0] res; + input clk; + input in; - // This is a Verilog 2001 test - generate - genvar i; - for (i=0; i<2; i=i+1) begin - always @(posedge clk) begin - res[i:i] <= in; - end + // This is a Verilog 2001 test + generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin + always @(posedge clk) begin + res[i:i] <= in; end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_langext_1_bad.out b/test_regress/t/t_langext_1_bad.out index c0416843a..9e5379438 100644 --- a/test_regress/t/t_langext_1_bad.out +++ b/test_regress/t/t_langext_1_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type - 44 | genvar i; - | ^~~~~~ +%Error: t/t_langext_1.v:45:5: syntax error, unexpected IDENTIFIER-for-type + 45 | genvar i; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' - 51 | endmodule +%Error: t/t_langext_1.v:52:1: syntax error, unexpected endmodule, expecting '(' + 52 | endmodule | ^~~~~~~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_1d_bad.out b/test_regress/t/t_langext_1d_bad.out index c0416843a..9e5379438 100644 --- a/test_regress/t/t_langext_1d_bad.out +++ b/test_regress/t/t_langext_1d_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type - 44 | genvar i; - | ^~~~~~ +%Error: t/t_langext_1.v:45:5: syntax error, unexpected IDENTIFIER-for-type + 45 | genvar i; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' - 51 | endmodule +%Error: t/t_langext_1.v:52:1: syntax error, unexpected endmodule, expecting '(' + 52 | endmodule | ^~~~~~~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_2.v b/test_regress/t/t_langext_2.v index 7d2e895c4..667c52112 100644 --- a/test_regress/t/t_langext_2.v +++ b/test_regress/t/t_langext_2.v @@ -12,45 +12,46 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - reg [1:0] res; + reg [1:0] res; - // Instantiate the test - test test_i (/*AUTOINST*/ - // Outputs - .res (res), - // Inputs - .clk (clk), - .in (1'b1)); + // Instantiate the test + test test_i ( /*AUTOINST*/ + // Outputs + .res(res), + // Inputs + .clk(clk), + .in(1'b1) + ); endmodule -module test (// Outputs - res, - // Inputs - clk, - in - ); - output [1:0] res; - input clk; - input in; +module test ( // Outputs + res, + // Inputs + clk, + in +); + output [1:0] res; + input clk; + input in; - // This is a SystemVerilog 2009 only test - generate - genvar i; - for (i=0; i<2; i=i+1) begin - always @(posedge clk) begin - unique0 case (i) - 0: res[0:0] <= in; - 1: res[1:1] <= in; - endcase - end + // This is a SystemVerilog 2009 only test + generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin + always @(posedge clk) begin + unique0 case (i) + 0: res[0:0] <= in; + 1: res[1:1] <= in; + endcase end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_langext_2_bad.out b/test_regress/t/t_langext_2_bad.out index 74b9a1dfa..194f3d72a 100644 --- a/test_regress/t/t_langext_2_bad.out +++ b/test_regress/t/t_langext_2_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_langext_2.v:46:7: syntax error, unexpected IDENTIFIER-for-type - 46 | genvar i; - | ^~~~~~ +%Error: t/t_langext_2.v:47:5: syntax error, unexpected IDENTIFIER-for-type + 47 | genvar i; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_langext_2.v:49:21: syntax error, unexpected case - 49 | unique0 case (i) - | ^~~~ +%Error: t/t_langext_2.v:50:17: syntax error, unexpected case + 50 | unique0 case (i) + | ^~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_3.v b/test_regress/t/t_langext_3.v index 60488ea3d..b1e5550d1 100644 --- a/test_regress/t/t_langext_3.v +++ b/test_regress/t/t_langext_3.v @@ -11,12 +11,12 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - uwire w; // Only in Verilog 2005 + uwire w; // Only in Verilog 2005 endmodule diff --git a/test_regress/t/t_langext_3_bad.out b/test_regress/t/t_langext_3_bad.out index c9a25f506..667beb312 100644 --- a/test_regress/t/t_langext_3_bad.out +++ b/test_regress/t/t_langext_3_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire' - 20 | uwire w; - | ^~~~~ +%Error: t/t_langext_3.v:20:3: Can't find typedef/interface: 'uwire' + 20 | uwire w; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_langext_4_bad.out b/test_regress/t/t_langext_4_bad.out index a34467385..1b3e0a5bd 100644 --- a/test_regress/t/t_langext_4_bad.out +++ b/test_regress/t/t_langext_4_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_langext_2.v:49:21: syntax error, unexpected case - 49 | unique0 case (i) - | ^~~~ +%Error: t/t_langext_2.v:50:17: syntax error, unexpected case + 50 | unique0 case (i) + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_order.v b/test_regress/t/t_langext_order.v index 083bc67c3..978d3974b 100644 --- a/test_regress/t/t_langext_order.v +++ b/test_regress/t/t_langext_order.v @@ -9,5 +9,5 @@ // verilator lint_off SYMRSVDWORD module t(input do); - t_langext_order_sub sub (.do(do)); + t_langext_order_sub sub (.do(do)); endmodule diff --git a/test_regress/t/t_leak.v b/test_regress/t/t_leak.v index 624801ae7..af80158d4 100644 --- a/test_regress/t/t_leak.v +++ b/test_regress/t/t_leak.v @@ -4,22 +4,24 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); +module t ( + clk +); - sub sub (); + sub sub (); - input clk; - integer cyc=1; + input clk; + integer cyc = 1; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==2) begin - // Not $finish; as we don't want a message to scroll by - $c("Verilated::threadContextp()->gotFinish(true);"); - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + // Not $finish; as we don't want a message to scroll by + $c("Verilated::threadContextp()->gotFinish(true);"); + end + end endmodule module sub; - /* verilator public_module */ + /* verilator public_module */ endmodule diff --git a/test_regress/t/t_let.v b/test_regress/t/t_let.v index 3bc4b49b2..33a1326ea 100644 --- a/test_regress/t/t_let.v +++ b/test_regress/t/t_let.v @@ -5,35 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - let P = 11; - let PP(a) = 30 + a; + let P = 11; + let PP(a) = 30 + a; endpackage module t; - let A = 10; - let B() = 20; - let C(a) = 30 + a; - let D(a, b) = 30 + a + b; - let E(a=1, b=7) = 30 + a + b; - let F(untyped a) = 30 + a; + let A = 10; + let B() = 20; + let C(a) = 30 + a; + let D(a, b) = 30 + a + b; + let E(a=1, b=7) = 30 + a + b; + let F(untyped a) = 30 + a; - initial begin - if (A != 10) $stop; - if (A() != 10) $stop; - if (B != 20) $stop; - if (B() != 20) $stop; - if (C(1) != (30 + 1)) $stop; - if (C(.a(1)) != (30 + 1)) $stop; - if (D(1, 2) != (30 + 1 + 2)) $stop; - if (D(.a(1), .b(2)) != (30 + 1 + 2)) $stop; - if (E(2) != (30 + 2 + 7)) $stop; - if (E(.b(1)) != (30 + 1 + 1)) $stop; - if (F(1) != (30 + 1)) $stop; - if (Pkg::P != 11) $stop; - if (Pkg::PP(6) != (30 + 6)) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (A != 10) $stop; + if (A() != 10) $stop; + if (B != 20) $stop; + if (B() != 20) $stop; + if (C(1) != (30 + 1)) $stop; + if (C(.a(1)) != (30 + 1)) $stop; + if (D(1, 2) != (30 + 1 + 2)) $stop; + if (D(.a(1), .b(2)) != (30 + 1 + 2)) $stop; + if (E(2) != (30 + 2 + 7)) $stop; + if (E(.b(1)) != (30 + 1 + 1)) $stop; + if (F(1) != (30 + 1)) $stop; + if (Pkg::P != 11) $stop; + if (Pkg::PP(6) != (30 + 6)) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_let_arg_bad.out b/test_regress/t/t_let_arg_bad.out index 1dccafd20..b10000c02 100644 --- a/test_regress/t/t_let_arg_bad.out +++ b/test_regress/t/t_let_arg_bad.out @@ -1,29 +1,29 @@ -%Error: t/t_let_arg_bad.v:13:18: Too many arguments in call to let 'NO_ARG' - 13 | if (NO_ARG(10) != 10) $stop; - | ^~~~~~ - : ... Location of let 'NO_ARG' declaration: - 9 | let NO_ARG = 10; - | ^~~~~~ +%Error: t/t_let_arg_bad.v:13:16: Too many arguments in call to let 'NO_ARG' + 13 | if (NO_ARG(10) != 10) $stop; + | ^~~~~~ + : ... Location of let 'NO_ARG' declaration: + 9 | let NO_ARG = 10; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_let_arg_bad.v:14:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' - 14 | if (ONE_ARG != 10) $stop; - | ^~~~~~~ -%Error: t/t_let_arg_bad.v:15:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' - 15 | if (ONE_ARG() != 10) $stop; - | ^~~~~~~ -%Error: t/t_let_arg_bad.v:16:23: Too many arguments in call to let 'ONE_ARG' - 16 | if (ONE_ARG(10, 20) != 10) $stop; - | ^~~~~~~ - : ... Location of let 'ONE_ARG' declaration: - 10 | let ONE_ARG(a) = 10; - | ^~~~~~~ -%Error: t/t_let_arg_bad.v:17:20: No such argument 'b' in call to let 'ONE_ARG' - 17 | if (ONE_ARG(.b(1)) != 10) $stop; - | ^~~~~~~ - : ... Location of let 'ONE_ARG' declaration - 10 | let ONE_ARG(a) = 10; - | ^~~~~~~ -%Error: t/t_let_arg_bad.v:17:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' - 17 | if (ONE_ARG(.b(1)) != 10) $stop; - | ^~~~~~~ +%Error: t/t_let_arg_bad.v:14:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' + 14 | if (ONE_ARG != 10) $stop; + | ^~~~~~~ +%Error: t/t_let_arg_bad.v:15:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' + 15 | if (ONE_ARG() != 10) $stop; + | ^~~~~~~ +%Error: t/t_let_arg_bad.v:16:21: Too many arguments in call to let 'ONE_ARG' + 16 | if (ONE_ARG(10, 20) != 10) $stop; + | ^~~~~~~ + : ... Location of let 'ONE_ARG' declaration: + 10 | let ONE_ARG(a) = 10; + | ^~~~~~~ +%Error: t/t_let_arg_bad.v:17:18: No such argument 'b' in call to let 'ONE_ARG' + 17 | if (ONE_ARG(.b(1)) != 10) $stop; + | ^~~~~~~ + : ... Location of let 'ONE_ARG' declaration + 10 | let ONE_ARG(a) = 10; + | ^~~~~~~ +%Error: t/t_let_arg_bad.v:17:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' + 17 | if (ONE_ARG(.b(1)) != 10) $stop; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_let_arg_bad.v b/test_regress/t/t_let_arg_bad.v index 801d29cd2..47b1f3dc2 100644 --- a/test_regress/t/t_let_arg_bad.v +++ b/test_regress/t/t_let_arg_bad.v @@ -6,17 +6,17 @@ module t; - let NO_ARG = 10; - let ONE_ARG(a) = 10; + let NO_ARG = 10; + let ONE_ARG(a) = 10; - initial begin - if (NO_ARG(10) != 10) $stop; // BAD extra arg - if (ONE_ARG != 10) $stop; // BAD need arg - if (ONE_ARG() != 10) $stop; // BAD need arg - if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg - if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (NO_ARG(10) != 10) $stop; // BAD extra arg + if (ONE_ARG != 10) $stop; // BAD need arg + if (ONE_ARG() != 10) $stop; // BAD need arg + if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg + if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_let_recurse_bad.out b/test_regress/t/t_let_recurse_bad.out index b03fdbacd..dc1496ddf 100644 --- a/test_regress/t/t_let_recurse_bad.out +++ b/test_regress/t/t_let_recurse_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_let_recurse_bad.v:9:36: Recursive let substitution 'RECURSE' - 9 | let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); - | ^~~~~~~ +%Error: t/t_let_recurse_bad.v:9:35: Recursive let substitution 'RECURSE' + 9 | let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_let_recurse_bad.v b/test_regress/t/t_let_recurse_bad.v index 1114cc110..a2a47e2e4 100644 --- a/test_regress/t/t_let_recurse_bad.v +++ b/test_regress/t/t_let_recurse_bad.v @@ -6,12 +6,12 @@ module t; - let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12 + let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12 - initial begin - if (RECURSE(1) != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (RECURSE(1) != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_let_stmt_bad.out b/test_regress/t/t_let_stmt_bad.out index cb25be2a6..8f23e3190 100644 --- a/test_regress/t/t_let_stmt_bad.out +++ b/test_regress/t/t_let_stmt_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_let_stmt_bad.v:15:14: Expected statement, not let substitution 'letf' - 15 | 0: letf(0); - | ^~~~ +%Error: t/t_let_stmt_bad.v:15:10: Expected statement, not let substitution 'letf' + 15 | 0: letf(0); + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_let_stmt_bad.v b/test_regress/t/t_let_stmt_bad.v index 0bb6c8751..99576818f 100644 --- a/test_regress/t/t_let_stmt_bad.v +++ b/test_regress/t/t_let_stmt_bad.v @@ -6,14 +6,14 @@ module t; - wire clk; + wire clk; - let letf(x) = (x << 1); + let letf(x) = (x << 1); - always @(posedge clk) begin - case (0) - 0: letf(0); // Bad, need a statement - endcase - end + always @(posedge clk) begin + case (0) + 0: letf(0); // Bad, need a statement + endcase + end endmodule diff --git a/test_regress/t/t_let_unsup.out b/test_regress/t/t_let_unsup.out index 66e9536c0..840808d76 100644 --- a/test_regress/t/t_let_unsup.out +++ b/test_regress/t/t_let_unsup.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_let_unsup.v:10:10: Unsupported: let typed ports - 10 | let G(int a) = 30 + a; - | ^~~ +%Error-UNSUPPORTED: t/t_let_unsup.v:10:9: Unsupported: let typed ports + 10 | let G(int a) = 30 + a; + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_let_unsup.v:11:10: Unsupported: let typed ports - 11 | let H(signed a) = 30 + a; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_let_unsup.v:11:9: Unsupported: let typed ports + 11 | let H(signed a) = 30 + a; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_let_unsup.v b/test_regress/t/t_let_unsup.v index 69ccd680b..553f10ea4 100644 --- a/test_regress/t/t_let_unsup.v +++ b/test_regress/t/t_let_unsup.v @@ -6,16 +6,16 @@ module t; - let F(untyped a) = 30 + a; - let G(int a) = 30 + a; - let H(signed a) = 30 + a; + let F(untyped a) = 30 + a; + let G(int a) = 30 + a; + let H(signed a) = 30 + a; - initial begin - if (F(1) != (30 + 1)) $stop; - if (G(1) != (30 + 1)) $stop; - if (H(1) != (30 + 1)) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (F(1) != (30 + 1)) $stop; + if (G(1) != (30 + 1)) $stop; + if (H(1) != (30 + 1)) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_lib_prot.v b/test_regress/t/t_lib_prot.v index 25c1d7894..cb68cb78e 100644 --- a/test_regress/t/t_lib_prot.v +++ b/test_regress/t/t_lib_prot.v @@ -10,187 +10,187 @@ sig``_in <= {8{crc}}; \ /* verilator lint_on WIDTH */ `define CHECK(sig) \ if (cyc > 0 && sig``_in != sig``_out) begin \ - $display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \ - sig``_in, sig``_out); \ - $stop; \ - end + $display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \ + sig``_in, sig``_out); \ + $stop; \ + end module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - localparam last_cyc = + localparam last_cyc = `ifdef TEST_BENCHMARK - `TEST_BENCHMARK; + `TEST_BENCHMARK; `else - 10; + 10; `endif - genvar x; - generate - for (x = 0; x < 2; x = x + 1) begin: gen_loop - integer cyc = 0; - reg [63:0] crc = 64'h5aef0c8d_d70a4497; - logic [31:0] accum_in; - logic [31:0] accum_out; - logic accum_bypass; - logic [31:0] accum_bypass_out; - logic [31:0] accum_out_expect; - logic [31:0] accum_bypass_out_expect; - logic s1_in; - logic s1_out; - logic s1up_in[2]; - logic s1up_out[2]; - logic [1:0] s2_in; - logic [1:0] s2_out; - logic [7:0] s8_in; - logic [7:0] s8_out; - logic [32:0] s33_in; - logic [32:0] s33_out; - logic [63:0] s64_in; - logic [63:0] s64_out; - logic [64:0] s65_in; - logic [64:0] s65_out; - logic [128:0] s129_in; - logic [128:0] s129_out; - logic [3:0] [31:0] s4x32_in; - logic [3:0] [31:0] s4x32_out; - /*verilator lint_off ASCRANGE*/ - logic [0:15] s6x16up_in[0:1][2:0]; - logic [0:15] s6x16up_out[0:1][2:0]; - /*verilator lint_on ASCRANGE*/ - logic [15:0] s8x16up_in[1:0][0:3]; - logic [15:0] s8x16up_out[1:0][0:3]; - logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; - logic [15:0] s8x16up_3d_out[1:0][0:1][0:1]; + genvar x; + generate + for (x = 0; x < 2; x = x + 1) begin: gen_loop + integer cyc = 0; + reg [63:0] crc = 64'h5aef0c8d_d70a4497; + logic [31:0] accum_in; + logic [31:0] accum_out; + logic accum_bypass; + logic [31:0] accum_bypass_out; + logic [31:0] accum_out_expect; + logic [31:0] accum_bypass_out_expect; + logic s1_in; + logic s1_out; + logic s1up_in[2]; + logic s1up_out[2]; + logic [1:0] s2_in; + logic [1:0] s2_out; + logic [7:0] s8_in; + logic [7:0] s8_out; + logic [32:0] s33_in; + logic [32:0] s33_out; + logic [63:0] s64_in; + logic [63:0] s64_out; + logic [64:0] s65_in; + logic [64:0] s65_out; + logic [128:0] s129_in; + logic [128:0] s129_out; + logic [3:0] [31:0] s4x32_in; + logic [3:0] [31:0] s4x32_out; + /*verilator lint_off ASCRANGE*/ + logic [0:15] s6x16up_in[0:1][2:0]; + logic [0:15] s6x16up_out[0:1][2:0]; + /*verilator lint_on ASCRANGE*/ + logic [15:0] s8x16up_in[1:0][0:3]; + logic [15:0] s8x16up_out[1:0][0:3]; + logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; + logic [15:0] s8x16up_3d_out[1:0][0:1][0:1]; - wire clk_en = crc[0]; + wire clk_en = crc[0]; - secret - secret ( - .accum_in, - .accum_out, - .accum_bypass, - .accum_bypass_out, - .s1_in, - .s1_out, - .s1up_in, - .s1up_out, - .s2_in, - .s2_out, - .s8_in, - .s8_out, - .s33_in, - .s33_out, - .s64_in, - .s64_out, - .s65_in, - .s65_out, - .s129_in, - .s129_out, - .s4x32_in, - .s4x32_out, - .s6x16up_in, - .s6x16up_out, - .s8x16up_in, - .s8x16up_out, - .s8x16up_3d_in, - .s8x16up_3d_out, - .clk_en, - .clk); + secret + secret ( + .accum_in, + .accum_out, + .accum_bypass, + .accum_bypass_out, + .s1_in, + .s1_out, + .s1up_in, + .s1up_out, + .s2_in, + .s2_out, + .s8_in, + .s8_out, + .s33_in, + .s33_out, + .s64_in, + .s64_out, + .s65_in, + .s65_out, + .s129_in, + .s129_out, + .s4x32_in, + .s4x32_out, + .s6x16up_in, + .s6x16up_out, + .s8x16up_in, + .s8x16up_out, + .s8x16up_3d_in, + .s8x16up_3d_out, + .clk_en, + .clk); - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d", - $time, x, cyc, accum_in, accum_out, accum_bypass_out); + $display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d", + $time, x, cyc, accum_in, accum_out, accum_bypass_out); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - accum_in <= accum_in + 5; - `DRIVE(s1) - `DRIVE(s2) - `DRIVE(s8) - `DRIVE(s33) - `DRIVE(s64) - `DRIVE(s65) - `DRIVE(s129) - `DRIVE(s4x32) - {s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)}; - {s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0]; - {s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16]; - {s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc; - {s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc; - {s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0]; - {s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32]; - {s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0]; - {s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32]; - if (cyc == 0) begin - accum_in <= x*100; - accum_bypass <= '0; - end else if (cyc > 0) begin - if (accum_out_expect != accum_out) begin - $display("%%Error: (%m) accum_out expected %0d got %0d", - accum_out_expect, accum_out); - $stop; - end - if (accum_bypass_out_expect != accum_bypass_out) begin - $display("%%Error: (%m) accum_bypass_out expected %0d got %0d", - accum_bypass_out_expect, accum_bypass_out); - $stop; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + accum_in <= accum_in + 5; + `DRIVE(s1) + `DRIVE(s2) + `DRIVE(s8) + `DRIVE(s33) + `DRIVE(s64) + `DRIVE(s65) + `DRIVE(s129) + `DRIVE(s4x32) + {s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)}; + {s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0]; + {s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16]; + {s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc; + {s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc; + {s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0]; + {s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32]; + {s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0]; + {s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32]; + if (cyc == 0) begin + accum_in <= x*100; + accum_bypass <= '0; + end else if (cyc > 0) begin + if (accum_out_expect != accum_out) begin + $display("%%Error: (%m) accum_out expected %0d got %0d", + accum_out_expect, accum_out); + $stop; + end + if (accum_bypass_out_expect != accum_bypass_out) begin + $display("%%Error: (%m) accum_bypass_out expected %0d got %0d", + accum_bypass_out_expect, accum_bypass_out); + $stop; + end + end - if (cyc == 5) accum_bypass <= '1; + if (cyc == 5) accum_bypass <= '1; - if (x == 0 && cyc == last_cyc) begin - $display("final cycle = %0d", cyc); - $write("*-* All Finished *-*\n"); - $finish; - end - end - - logic possibly_gated_clk; - if (GATED_CLK != 0) begin: yes_gated_clock - logic clk_en_latch; - // verilator lint_off COMBDLY,LATCH - always_comb if (clk == '0) clk_en_latch <= clk_en; - // verilator lint_on COMBDLY,LATCH - assign possibly_gated_clk = clk & clk_en_latch; - end else begin: no_gated_clock - assign possibly_gated_clk = clk; - end - - always @(posedge possibly_gated_clk) begin - // 7 is the secret_value inside the secret module - accum_out_expect <= accum_in + accum_out_expect + 7; - end - - always @(*) begin - // XSim (and maybe all event simulators?) sees the moment where - // s1_in has not yet propagated to s1_out, however, they do always - // both change at the same time - /* verilator lint_off STMTDLY */ - #1; - /* verilator lint_on STMTDLY */ - `CHECK(s1) - `CHECK(s1up) - `CHECK(s2) - `CHECK(s8) - `CHECK(s33) - `CHECK(s64) - `CHECK(s65) - `CHECK(s129) - `CHECK(s4x32) - `CHECK(s6x16up) - `CHECK(s8x16up) - `CHECK(s8x16up_3d) - end - - assign accum_bypass_out_expect = accum_bypass ? accum_in : - accum_out_expect; + if (x == 0 && cyc == last_cyc) begin + $display("final cycle = %0d", cyc); + $write("*-* All Finished *-*\n"); + $finish; + end end - endgenerate + + logic possibly_gated_clk; + if (GATED_CLK != 0) begin: yes_gated_clock + logic clk_en_latch; + // verilator lint_off COMBDLY,LATCH + always_comb if (clk == '0) clk_en_latch <= clk_en; + // verilator lint_on COMBDLY,LATCH + assign possibly_gated_clk = clk & clk_en_latch; + end else begin: no_gated_clock + assign possibly_gated_clk = clk; + end + + always @(posedge possibly_gated_clk) begin + // 7 is the secret_value inside the secret module + accum_out_expect <= accum_in + accum_out_expect + 7; + end + + always @(*) begin + // XSim (and maybe all event simulators?) sees the moment where + // s1_in has not yet propagated to s1_out, however, they do always + // both change at the same time + /* verilator lint_off STMTDLY */ + #1; + /* verilator lint_on STMTDLY */ + `CHECK(s1) + `CHECK(s1up) + `CHECK(s2) + `CHECK(s8) + `CHECK(s33) + `CHECK(s64) + `CHECK(s65) + `CHECK(s129) + `CHECK(s4x32) + `CHECK(s6x16up) + `CHECK(s8x16up) + `CHECK(s8x16up_3d) + end + + assign accum_bypass_out_expect = accum_bypass ? accum_in : + accum_out_expect; + end + endgenerate endmodule diff --git a/test_regress/t/t_lib_prot_comb.v b/test_regress/t/t_lib_prot_comb.v index 31f6fdf6b..3ad98f0e5 100644 --- a/test_regress/t/t_lib_prot_comb.v +++ b/test_regress/t/t_lib_prot_comb.v @@ -4,53 +4,71 @@ // SPDX-License-Identifier: CC0-1.0 `ifdef PROCESS_TOP +// verilog_format: off `define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2__under != (in0 & in1)) begin \ $display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2__under); \ $stop; \ end +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - logic in0, in1; - logic out0, out1, out2__under; - logic [31:0] count = 0; - // actually XOR and OR and AND - secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2__under(out2__under)); + logic in0, in1; + logic out0, out1, out2__under; + logic [31:0] count = 0; + // actually XOR and OR and AND + secret i_secret ( + .in0(in0), + .in1(in1), + .out0(out0), + .out1(out1), + .out2__under(out2__under) + ); - always @(posedge clk) begin - count <= count + 32'd1; - if (count == 32'd1) begin - in0 <= 1'b0; - in1 <= 1'b0; - end else if (count == 32'd2) begin - `CHECK - in0 <= 1'b1; - in1 <= 1'b0; - end else if (count == 32'd3) begin - `CHECK - in0 <= 1'b0; - in1 <= 1'b1; - end else if (count == 32'd4) begin - `CHECK - in0 <= 1'b1; - in1 <= 1'b1; - end else if (count == 32'd5) begin - `CHECK - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + count <= count + 32'd1; + if (count == 32'd1) begin + in0 <= 1'b0; + in1 <= 1'b0; + end + else if (count == 32'd2) begin + `CHECK + in0 <= 1'b1; + in1 <= 1'b0; + end + else if (count == 32'd3) begin + `CHECK + in0 <= 1'b0; + in1 <= 1'b1; + end + else if (count == 32'd4) begin + `CHECK + in0 <= 1'b1; + in1 <= 1'b1; + end + else if (count == 32'd5) begin + `CHECK + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule `else -module secret(input in0, input in1, output out0, output out1, output out2__under); - assign out0 = in0 ^ in1; - assign out1 = in0 | in1; - assign out2__under = in0 & in1; +module secret ( + input in0, + input in1, + output out0, + output out1, + output out2__under +); + assign out0 = in0 ^ in1; + assign out1 = in0 | in1; + assign out2__under = in0 & in1; endmodule `endif diff --git a/test_regress/t/t_lib_prot_delay_bad.v b/test_regress/t/t_lib_prot_delay_bad.v index 090249c20..b15013793 100644 --- a/test_regress/t/t_lib_prot_delay_bad.v +++ b/test_regress/t/t_lib_prot_delay_bad.v @@ -4,8 +4,8 @@ // SPDX-License-Identifier: CC0-1.0 module secret_impl; - initial begin - #10; - $stop; - end + initial begin + #10; + $stop; + end endmodule diff --git a/test_regress/t/t_lib_prot_inout_bad.out b/test_regress/t/t_lib_prot_inout_bad.out index d2ff6d8e6..b308d4e0b 100644 --- a/test_regress/t/t_lib_prot_inout_bad.out +++ b/test_regress/t/t_lib_prot_inout_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_lib_prot_inout_bad.v:9:28: Unsupported: --lib-create port direction: INOUT - 9 | inout z, - | ^ +%Error-UNSUPPORTED: t/t_lib_prot_inout_bad.v:9:11: Unsupported: --lib-create port direction: INOUT + 9 | inout z, + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lib_prot_inout_bad.v b/test_regress/t/t_lib_prot_inout_bad.v index bf946a116..a517b68ed 100644 --- a/test_regress/t/t_lib_prot_inout_bad.v +++ b/test_regress/t/t_lib_prot_inout_bad.v @@ -4,12 +4,13 @@ // SPDX-License-Identifier: CC0-1.0 module secret_impl ( - input a, - input oe, - inout z, - output y); + input a, + input oe, + inout z, + output y +); - assign z = oe ? a : 1'bz; - assign y = z; + assign z = oe ? a : 1'bz; + assign y = z; endmodule diff --git a/test_regress/t/t_lib_prot_secret.v b/test_regress/t/t_lib_prot_secret.v index 5e1be331a..37af30039 100644 --- a/test_regress/t/t_lib_prot_secret.v +++ b/test_regress/t/t_lib_prot_secret.v @@ -3,108 +3,115 @@ // SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module secret #(parameter GATED_CLK = 0) - ( - input [31:0] accum_in, - output wire [31:0] accum_out, - input accum_bypass, - output [31:0] accum_bypass_out, - input s1_in, - output logic s1_out, - input s1up_in[2], - output logic s1up_out[2], - input [1:0] s2_in, - output logic [1:0] s2_out, - input [7:0] s8_in, - output logic [7:0] s8_out, - input [32:0] s33_in, - output logic [32:0] s33_out, - input [63:0] s64_in, - output logic [63:0] s64_out, - input [64:0] s65_in, - output logic [64:0] s65_out, - input [128:0] s129_in, - output logic [128:0] s129_out, - input [3:0] [31:0] s4x32_in, - output logic [3:0] [31:0] s4x32_out, +module secret #( + parameter GATED_CLK = 0 +) ( + input [31:0] accum_in, + output wire [31:0] accum_out, + input accum_bypass, + output [31:0] accum_bypass_out, + input s1_in, + output logic s1_out, + input s1up_in[2], + output logic s1up_out[2], + input [1:0] s2_in, + output logic [1:0] s2_out, + input [7:0] s8_in, + output logic [7:0] s8_out, + input [32:0] s33_in, + output logic [32:0] s33_out, + input [63:0] s64_in, + output logic [63:0] s64_out, + input [64:0] s65_in, + output logic [64:0] s65_out, + input [128:0] s129_in, + output logic [128:0] s129_out, + input [3:0][31:0] s4x32_in, + output logic [3:0][31:0] s4x32_out, /*verilator lint_off ASCRANGE*/ - input [0:15] s6x16up_in[0:1][2:0], - output logic [0:15] s6x16up_out[0:1][2:0], + input [0:15] s6x16up_in[0:1][2:0], + output logic [0:15] s6x16up_out[0:1][2:0], /*verilator lint_on ASCRANGE*/ - input [15:0] s8x16up_in[1:0][0:3], - output logic [15:0] s8x16up_out[1:0][0:3], - input [15:0] s8x16up_3d_in[1:0][0:1][0:1], - output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1], - input clk_en, - input clk); + input [15:0] s8x16up_in[1:0][0:3], + output logic [15:0] s8x16up_out[1:0][0:3], + input [15:0] s8x16up_3d_in[1:0][0:1][0:1], + output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1], + input clk_en, + input clk +); - logic [31:0] secret_accum_q = 0; - logic [31:0] secret_value = 7; + logic [31:0] secret_accum_q = 0; + logic [31:0] secret_value = 7; - initial $display("created %m"); + initial $display("created %m"); - logic the_clk; - generate - if (GATED_CLK != 0) begin: yes_gated_clock - logic clk_en_latch; - /* verilator lint_off COMBDLY */ - /* verilator lint_off LATCH */ - always_comb if (clk == '0) clk_en_latch <= clk_en; - /* verilator lint_on LATCH */ - /* verilator lint_on COMBDLY */ - assign the_clk = clk & clk_en_latch; - end else begin: no_gated_clock - assign the_clk = clk; - end - endgenerate + logic the_clk; + generate + if (GATED_CLK != 0) begin : yes_gated_clock + logic clk_en_latch; + /* verilator lint_off COMBDLY */ + /* verilator lint_off LATCH */ + always_comb if (clk == '0) clk_en_latch <= clk_en; + /* verilator lint_on LATCH */ + /* verilator lint_on COMBDLY */ + assign the_clk = clk & clk_en_latch; + end + else begin : no_gated_clock + assign the_clk = clk; + end + endgenerate - always @(posedge the_clk) begin - secret_accum_q <= secret_accum_q + accum_in + secret_value; - end + always @(posedge the_clk) begin + secret_accum_q <= secret_accum_q + accum_in + secret_value; + end - // Test combinatorial paths of different sizes - always @(*) begin - s1_out = s1_in; - s1up_out = s1up_in; - s2_out = s2_in; - s8_out = s8_in; - s64_out = s64_in; - s65_out = s65_in; - s129_out = s129_in; - s4x32_out = s4x32_in; - end + // Test combinatorial paths of different sizes + always @(*) begin + s1_out = s1_in; + s1up_out = s1up_in; + s2_out = s2_in; + s8_out = s8_in; + s64_out = s64_in; + s65_out = s65_in; + s129_out = s129_in; + s4x32_out = s4x32_in; + end - for (genvar i = 0; i < 3; ++i) begin - assign s6x16up_out[0][i] = s6x16up_in[0][i]; - assign s6x16up_out[1][i] = s6x16up_in[1][i]; - end - for (genvar i = 0; i < 4; ++i) begin - assign s8x16up_out[0][i] = s8x16up_in[0][i]; - assign s8x16up_out[1][i] = s8x16up_in[1][i]; - end - for (genvar i = 0; i < 8; ++i) begin - assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]]; - end + for (genvar i = 0; i < 3; ++i) begin + assign s6x16up_out[0][i] = s6x16up_in[0][i]; + assign s6x16up_out[1][i] = s6x16up_in[1][i]; + end + for (genvar i = 0; i < 4; ++i) begin + assign s8x16up_out[0][i] = s8x16up_in[0][i]; + assign s8x16up_out[1][i] = s8x16up_in[1][i]; + end + for (genvar i = 0; i < 8; ++i) begin + assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]]; + end - sub sub (.sub_in(s33_in), .sub_out(s33_out)); + sub sub ( + .sub_in(s33_in), + .sub_out(s33_out) + ); - // Test sequential path - assign accum_out = secret_accum_q; + // Test sequential path + assign accum_out = secret_accum_q; - // Test mixed combinatorial/sequential path - assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; + // Test mixed combinatorial/sequential path + assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; - final $display("destroying %m"); + final $display("destroying %m"); endmodule module sub ( - input [32:0] sub_in, - output [32:0] sub_out); + input [32:0] sub_in, + output [32:0] sub_out +); - /*verilator no_inline_module*/ + /*verilator no_inline_module*/ - assign sub_out = sub_in; + assign sub_out = sub_in; endmodule diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out index 11fffe4b5..9aefafaf9 100644 --- a/test_regress/t/t_lint_always_comb_bad.out +++ b/test_regress/t/t_lint_always_comb_bad.out @@ -1,20 +1,20 @@ -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' - 29 | temp1 = 'h0; - | ^~~~~ + 29 | temp1 = 'h0; + | ^~~~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' - 31 | temp1 = (temp1_d1r - 'h1); - | ^~~~~ -%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid' + 31 | temp1 = (temp1_d1r - 'h1); + | ^~~~~ +%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:5: Always_comb variable driven after use: 'mid' : ... note: In instance 't' - 32 | mid = (temp1_d1r == 'h0); - | ^~~ + 32 | mid = (temp1_d1r == 'h0); + | ^~~ ... For warning description see https://verilator.org/warn/ALWCOMBORDER?v=latest ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r' +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r' : ... note: In instance 't' - 46 | temp1_d1r <= temp1; - | ^~~~~~~~~ + 46 | temp1_d1r <= temp1; + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_bad.v b/test_regress/t/t_lint_always_comb_bad.v index f89b5da51..19764ff61 100644 --- a/test_regress/t/t_lint_always_comb_bad.v +++ b/test_regress/t/t_lint_always_comb_bad.v @@ -5,45 +5,45 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - mid, o3, - // Inputs - clk, i3 - ); - input clk; - output logic mid; - input i3; - output logic o3; + // Outputs + mid, o3, + // Inputs + clk, i3 + ); + input clk; + output logic mid; + input i3; + output logic o3; - wire [15:0] temp1; - wire [15:0] temp1_d1r; + wire [15:0] temp1; + wire [15:0] temp1_d1r; - logic setbefore; - always_comb begin - setbefore = 1'b1; - if (setbefore) setbefore = 1'b0; // fine - end + logic setbefore; + always_comb begin + setbefore = 1'b1; + if (setbefore) setbefore = 1'b0; // fine + end - always_comb begin - if (mid) - temp1 = 'h0; - else - temp1 = (temp1_d1r - 'h1); - mid = (temp1_d1r == 'h0); // BAD - end + always_comb begin + if (mid) + temp1 = 'h0; + else + temp1 = (temp1_d1r - 'h1); + mid = (temp1_d1r == 'h0); // BAD + end - always_comb begin - o3 = 'h0; - case (i3) - 1'b1: begin - o3 = i3; - end - default: ; - endcase - end + always_comb begin + o3 = 'h0; + case (i3) + 1'b1: begin + o3 = i3; + end + default: ; + endcase + end - always_ff @ (posedge clk) begin - temp1_d1r <= temp1; - end + always_ff @ (posedge clk) begin + temp1_d1r <= temp1; + end endmodule diff --git a/test_regress/t/t_lint_always_comb_iface.v b/test_regress/t/t_lint_always_comb_iface.v index 56c06940d..ad8b67f03 100644 --- a/test_regress/t/t_lint_always_comb_iface.v +++ b/test_regress/t/t_lint_always_comb_iface.v @@ -6,89 +6,80 @@ interface my_if; - logic valid; - logic [7:0] data ; + logic valid; + logic [7:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); endinterface -module t - ( - input wire in_valid, - input wire [7:0] in_data - ); +module t ( + input wire in_valid, + input wire [7:0] in_data +); - my_if in_i (); - my_if out1_i (); - my_if out2_i (); - my_if out3_i (); + my_if in_i (); + my_if out1_i (); + my_if out2_i (); + my_if out3_i (); - assign in_i.valid = in_valid; - assign in_i.data = in_data ; + assign in_i.valid = in_valid; + assign in_i.data = in_data; - my_module1 my_module1_i ( - .in_i (in_i ), - .out_i (out1_i) - ); + my_module1 my_module1_i ( + .in_i(in_i), + .out_i(out1_i) + ); - my_module2 my_module2_i ( - .in_i (in_i ), - .out_i (out2_i) - ); + my_module2 my_module2_i ( + .in_i(in_i), + .out_i(out2_i) + ); - my_module3 my_module3_i ( - .in_i (in_i ), - .out_i (out3_i) - ); + my_module3 my_module3_i ( + .in_i(in_i), + .out_i(out3_i) + ); endmodule module my_module1 ( - my_if.slave_mp in_i, - my_if.master_mp out_i - ); + my_if.slave_mp in_i, + my_if.master_mp out_i +); - // Gives ALWCOMBORDER warning - always_comb - begin - out_i.valid = in_i.valid; - out_i.data = in_i.data ; - end + // Gives ALWCOMBORDER warning + always_comb begin + out_i.valid = in_i.valid; + out_i.data = in_i.data; + end endmodule module my_module2 ( - my_if.slave_mp in_i, - my_if.master_mp out_i - ); + my_if.slave_mp in_i, + my_if.master_mp out_i +); - // Works if you initialise to non-interface signal first - always_comb - begin - out_i.valid = '0; - out_i.data = 'X; - out_i.valid = in_i.valid; - out_i.data = in_i.data ; - end + // Works if you initialise to non-interface signal first + always_comb begin + out_i.valid = '0; + out_i.data = 'X; + out_i.valid = in_i.valid; + out_i.data = in_i.data; + end endmodule module my_module3 ( - my_if.slave_mp in_i, - my_if.master_mp out_i - ); + my_if.slave_mp in_i, + my_if.master_mp out_i +); - // Works if you use assign signal - assign out_i.valid = in_i.valid; - assign out_i.data = in_i.data ; + // Works if you use assign signal + assign out_i.valid = in_i.valid; + assign out_i.data = in_i.data; endmodule diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.out b/test_regress/t/t_lint_always_comb_multidriven_bad.out index 25b66bffc..21f5d90b1 100644 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.out +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.out @@ -1,83 +1,83 @@ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1' +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:26:16: - 26 | always_comb out1 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write - 25 | assign out1 = 1'b0; - | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:26:15: + 26 | always_comb out1 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:25:10: ... Location of other write + 25 | assign out1 = 1'b0; + | ^~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2' +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:29:16: - 29 | always_comb out2 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write - 28 | assign out2 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3' + t/t_lint_always_comb_multidriven_bad.v:29:15: + 29 | always_comb out2 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:28:10: ... Location of other write + 28 | assign out2 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:32:11: - 32 | assign out3 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write - 31 | always_comb out3 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4' + t/t_lint_always_comb_multidriven_bad.v:32:10: + 32 | assign out3 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:31:15: ... Location of always_comb write + 31 | always_comb out3 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:35:11: - 35 | assign out4 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write - 34 | always_comb out4 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5' + t/t_lint_always_comb_multidriven_bad.v:35:10: + 35 | assign out4 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:34:15: ... Location of always_comb write + 34 | always_comb out4 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:38:16: - 38 | always_comb out5 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write - 37 | always_comb out5 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6' + t/t_lint_always_comb_multidriven_bad.v:38:15: + 38 | always_comb out5 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:37:15: ... Location of other write + 37 | always_comb out5 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:41:16: - 41 | always_comb out6 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write - 40 | always_comb out6 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:41:15: + 41 | always_comb out6 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:40:15: ... Location of other write + 40 | always_comb out6 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of offending driver - 28 | assign out2 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of offending driver - 29 | always_comb out2 = 1'b0; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver + 28 | assign out2 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver + 29 | always_comb out2 = 1'b0; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:14: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of offending driver - 34 | always_comb out4 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of offending driver - 35 | assign out4 = d; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:34:20: ... Location of offending driver + 34 | always_comb out4 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:35:15: ... Location of offending driver + 35 | assign out4 = d; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of offending driver - 37 | always_comb out5 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of offending driver - 38 | always_comb out5 = d; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver + 37 | always_comb out5 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver + 38 | always_comb out5 = d; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of offending driver - 40 | always_comb out6 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of offending driver - 41 | always_comb out6 = 1'b0; - | ^ + t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver + 40 | always_comb out6 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver + 41 | always_comb out6 = 1'b0; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.v b/test_regress/t/t_lint_always_comb_multidriven_bad.v index f8d0e4879..53f17c0a3 100644 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.v +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.v @@ -5,72 +5,72 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - out1, out2, out3, out4, out5, out6, out7, out8, - // Inputs - clk, d - ); + // Outputs + out1, out2, out3, out4, out5, out6, out7, out8, + // Inputs + clk, d + ); - input clk; - input d; - output reg out1; - output reg out2; - output reg out3; - output reg out4; - output reg out5; - output reg out6; - output reg out7; - output reg out8; + input clk; + input d; + output reg out1; + output reg out2; + output reg out3; + output reg out4; + output reg out5; + output reg out6; + output reg out7; + output reg out8; - assign out1 = 1'b0; - always_comb out1 = d; // <--- Warning + assign out1 = 1'b0; + always_comb out1 = d; // <--- Warning - assign out2 = d; - always_comb out2 = 1'b0; // <--- Warning + assign out2 = d; + always_comb out2 = 1'b0; // <--- Warning - always_comb out3 = d; - assign out3 = 1'b0; // <--- Warning + always_comb out3 = d; + assign out3 = 1'b0; // <--- Warning - always_comb out4 = 1'b0; - assign out4 = d; // <--- Warning + always_comb out4 = 1'b0; + assign out4 = d; // <--- Warning - always_comb out5 = 1'b0; - always_comb out5 = d; // <--- Warning + always_comb out5 = 1'b0; + always_comb out5 = d; // <--- Warning - always_comb out6 = d; - always_comb out6 = 1'b0; // <--- Warning + always_comb out6 = d; + always_comb out6 = 1'b0; // <--- Warning - always_comb begin - out7 = 1'b0; - out7 = d; - end + always_comb begin + out7 = 1'b0; + out7 = d; + end - always_comb begin - out8 = d; - out8 = 1'b0; - end + always_comb begin + out8 = d; + out8 = 1'b0; + end - reg [1:0] arr_packed; - reg arr_unpacked [0:1]; - reg [1:0] gen_arr_packed; - reg gen_arr_unpacked [0:1]; - genvar g; + reg [1:0] arr_packed; + reg arr_unpacked [0:1]; + reg [1:0] gen_arr_packed; + reg gen_arr_unpacked [0:1]; + genvar g; - always_comb begin - arr_packed[0] = d; - arr_packed[1] = d; - end + always_comb begin + arr_packed[0] = d; + arr_packed[1] = d; + end - always_comb begin - arr_unpacked[0] = d; - arr_unpacked[1] = d; - end + always_comb begin + arr_unpacked[0] = d; + arr_unpacked[1] = d; + end - generate - for (g=0; g<2; ++g) begin - always_comb gen_arr_packed[g] = d; - always_comb gen_arr_unpacked[g] = d; - end - endgenerate + generate + for (g=0; g<2; ++g) begin + always_comb gen_arr_packed[g] = d; + always_comb gen_arr_unpacked[g] = d; + end + endgenerate endmodule diff --git a/test_regress/t/t_lint_always_comb_multidriven_public_bad.out b/test_regress/t/t_lint_always_comb_multidriven_public_bad.out index 25b66bffc..21f5d90b1 100644 --- a/test_regress/t/t_lint_always_comb_multidriven_public_bad.out +++ b/test_regress/t/t_lint_always_comb_multidriven_public_bad.out @@ -1,83 +1,83 @@ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1' +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:26:16: - 26 | always_comb out1 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write - 25 | assign out1 = 1'b0; - | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:26:15: + 26 | always_comb out1 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:25:10: ... Location of other write + 25 | assign out1 = 1'b0; + | ^~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2' +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:29:16: - 29 | always_comb out2 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write - 28 | assign out2 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3' + t/t_lint_always_comb_multidriven_bad.v:29:15: + 29 | always_comb out2 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:28:10: ... Location of other write + 28 | assign out2 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:32:11: - 32 | assign out3 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write - 31 | always_comb out3 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4' + t/t_lint_always_comb_multidriven_bad.v:32:10: + 32 | assign out3 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:31:15: ... Location of always_comb write + 31 | always_comb out3 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:35:11: - 35 | assign out4 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write - 34 | always_comb out4 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5' + t/t_lint_always_comb_multidriven_bad.v:35:10: + 35 | assign out4 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:34:15: ... Location of always_comb write + 34 | always_comb out4 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:38:16: - 38 | always_comb out5 = d; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write - 37 | always_comb out5 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6' + t/t_lint_always_comb_multidriven_bad.v:38:15: + 38 | always_comb out5 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:37:15: ... Location of other write + 37 | always_comb out5 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6' : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:41:16: - 41 | always_comb out6 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write - 40 | always_comb out6 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:41:15: + 41 | always_comb out6 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:40:15: ... Location of other write + 40 | always_comb out6 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of offending driver - 28 | assign out2 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of offending driver - 29 | always_comb out2 = 1'b0; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver + 28 | assign out2 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver + 29 | always_comb out2 = 1'b0; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:14: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of offending driver - 34 | always_comb out4 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of offending driver - 35 | assign out4 = d; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:34:20: ... Location of offending driver + 34 | always_comb out4 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:35:15: ... Location of offending driver + 35 | assign out4 = d; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of offending driver - 37 | always_comb out5 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of offending driver - 38 | always_comb out5 = d; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver + 37 | always_comb out5 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver + 38 | always_comb out5 = d; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of offending driver - 40 | always_comb out6 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of offending driver - 41 | always_comb out6 = 1'b0; - | ^ + t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver + 40 | always_comb out6 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver + 41 | always_comb out6 = 1'b0; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_blkseq_loop.v b/test_regress/t/t_lint_blkseq_loop.v index 57e90af27..099a27c60 100644 --- a/test_regress/t/t_lint_blkseq_loop.v +++ b/test_regress/t/t_lint_blkseq_loop.v @@ -4,106 +4,106 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - data_out, - // Inputs - wr, wa, rst_l, rd, ra, data_in, clk - ); - input clk; +module t ( /*AUTOARG*/ + // Outputs + data_out, + // Inputs + wr, wa, rst_l, rd, ra, data_in, clk + ); + input clk; - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input [31:0] data_in; // To sub of reg_1r1w.v - input [7:0] ra; // To sub of reg_1r1w.v - input rd; // To sub of reg_1r1w.v - input rst_l; // To sub of reg_1r1w.v - input [7:0] wa; // To sub of reg_1r1w.v - input wr; // To sub of reg_1r1w.v - // End of automatics - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [31:0] data_out; // From sub of reg_1r1w.v - // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input [31:0] data_in; // To sub of reg_1r1w.v + input [7:0] ra; // To sub of reg_1r1w.v + input rd; // To sub of reg_1r1w.v + input rst_l; // To sub of reg_1r1w.v + input [7:0] wa; // To sub of reg_1r1w.v + input wr; // To sub of reg_1r1w.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [31:0] data_out; // From sub of reg_1r1w.v + // End of automatics - reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) - sub - (/*AUTOINST*/ - // Outputs - .data_out (data_out[31:0]), - // Inputs - .data_in (data_in[31:0]), - .ra (ra[7:0]), - .wa (wa[7:0]), - .wr (wr), - .rd (rd), - .clk (clk), - .rst_l (rst_l)); + reg_1r1w #( + .WIDTH(32), + .DEPTH(256), + .ADRWID(8) + ) sub ( /*AUTOINST*/ + // Outputs + .data_out (data_out[31:0]), + // Inputs + .data_in (data_in[31:0]), + .ra (ra[7:0]), + .wa (wa[7:0]), + .wr (wr), + .rd (rd), + .clk (clk), + .rst_l (rst_l)); endmodule -module reg_1r1w - #( - parameter WIDTH=32, - parameter ADRWID=10, - parameter DEPTH=1024, - parameter RST=0 - ) - (/*AUTOARG*/ - // Outputs - data_out, - // Inputs - data_in, ra, wa, wr, rd, clk, rst_l - ); +module reg_1r1w #( + parameter WIDTH = 32, + parameter ADRWID = 10, + parameter DEPTH = 1024, + parameter RST = 0 +) ( /*AUTOARG*/ + // Outputs + data_out, + // Inputs + data_in, ra, wa, wr, rd, clk, rst_l + ); - input [WIDTH-1:0] data_in; - input [ADRWID-1:0] ra; - input [ADRWID-1:0] wa; - input wr; - input rd; - input clk; - input rst_l; + input [WIDTH-1:0] data_in; + input [ADRWID-1:0] ra; + input [ADRWID-1:0] wa; + input wr; + input rd; + input clk; + input rst_l; - output [WIDTH-1:0] data_out; + output [WIDTH-1:0] data_out; - reg [WIDTH-1:0] array [DEPTH-1:0]; - reg [ADRWID-1:0] ra_r, wa_r; - reg [WIDTH-1:0] data_in_r; - reg wr_r; - reg rd_r; + reg [WIDTH-1:0] array[DEPTH-1:0]; + reg [ADRWID-1:0] ra_r, wa_r; + reg [WIDTH-1:0] data_in_r; + reg wr_r; + reg rd_r; - integer x; + integer x; - // Message 679 - always @(posedge clk) begin - // verilator lint_off IMPLICITSTATIC - int tmp = x + 1; - // verilator lint_on IMPLICITSTATIC - if (tmp !== x + 1) $stop; + // Message 679 + always @(posedge clk) begin + // verilator lint_off IMPLICITSTATIC + int tmp = x + 1; + // verilator lint_on IMPLICITSTATIC + if (tmp !== x + 1) $stop; + end + + always @(posedge clk or negedge rst_l) begin + if (!rst_l) begin + for (x = 0; x < DEPTH; x = x + 1) begin // <== VERILATOR FLAGS THIS LINE + if (RST == 1) begin + array[x] <= 0; + end + end + ra_r <= 0; + wa_r <= 0; + wr_r <= 0; + rd_r <= 0; + data_in_r <= 0; end - - always @(posedge clk or negedge rst_l) begin - if (!rst_l) begin - for (x=0; x 3'b111) $stop; - | ^ + 13 | if (uns > 3'b111) $stop; + | ^ ... For warning description see https://verilator.org/warn/CMPCONST?v=latest ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_cmpconst_bad.v b/test_regress/t/t_lint_cmpconst_bad.v index 34d6cdc00..4229197a4 100644 --- a/test_regress/t/t_lint_cmpconst_bad.v +++ b/test_regress/t/t_lint_cmpconst_bad.v @@ -6,10 +6,10 @@ module t; - bit [2:0] uns; + bit [2:0] uns; - initial begin - uns = 1; - if (uns > 3'b111) $stop; - end + initial begin + uns = 1; + if (uns > 3'b111) $stop; + end endmodule diff --git a/test_regress/t/t_lint_colonplus_bad.out b/test_regress/t/t_lint_colonplus_bad.out index afd366f72..285d6a3b3 100644 --- a/test_regress/t/t_lint_colonplus_bad.out +++ b/test_regress/t/t_lint_colonplus_bad.out @@ -1,6 +1,6 @@ -%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? - 13 | output [2:1] z = r[2 :+ 1]; - | ^~ +%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:24: Perhaps instead of ':+' the intent was '+:'? + 13 | output [2:1] z = r[2 :+ 1]; + | ^~ ... For warning description see https://verilator.org/warn/COLONPLUS?v=latest ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_colonplus_bad.v b/test_regress/t/t_lint_colonplus_bad.v index 49b2af74b..b4d4f1b6b 100644 --- a/test_regress/t/t_lint_colonplus_bad.v +++ b/test_regress/t/t_lint_colonplus_bad.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - z - ); + // Outputs + z + ); - reg [3:0] r = 4'b1010; - output [2:1] z = r[2 :+ 1]; + reg [3:0] r = 4'b1010; + output [2:1] z = r[2 :+ 1]; endmodule diff --git a/test_regress/t/t_lint_comb_bad.out b/test_regress/t/t_lint_comb_bad.out index e204359af..2094dac4f 100644 --- a/test_regress/t/t_lint_comb_bad.out +++ b/test_regress/t/t_lint_comb_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_comb_bad.v:14:4: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2) +%Error: t/t_lint_comb_bad.v:14:3: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2) : ... Suggest use a normal 'always' - 14 | always_comb @(*) begin - | ^~~~~~~~~~~ + 14 | always_comb @(*) begin + | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_lint_comb_bad.v b/test_regress/t/t_lint_comb_bad.v index 5e6cfb34b..4fa91b013 100644 --- a/test_regress/t/t_lint_comb_bad.v +++ b/test_regress/t/t_lint_comb_bad.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - input clk; + input clk; - always_comb @(*) begin - $stop; - end + always_comb @(*) begin + $stop; + end endmodule diff --git a/test_regress/t/t_lint_comb_use.v b/test_regress/t/t_lint_comb_use.v index def83e983..49d562f15 100644 --- a/test_regress/t/t_lint_comb_use.v +++ b/test_regress/t/t_lint_comb_use.v @@ -4,28 +4,28 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - hval, - // Inputs - sel - ); +module t ( /*AUTOARG*/ + // Outputs + hval, + // Inputs + sel +); - input logic [2:0] sel; - output logic [3:0] hval; + input logic [2:0] sel; + output logic [3:0] hval; - /*AUTOINPUT*/ - /*AUTOOUTPUT*/ + /*AUTOINPUT*/ + /*AUTOOUTPUT*/ - always_comb begin - unique case (sel) - 3'h0: hval = 4'hd; - 3'h1: hval = 4'hc; - 3'h7: hval = 4'hf; - default: begin - $ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel)); - hval = 4'bx; - end - endcase - end + always_comb begin + unique case (sel) + 3'h0: hval = 4'hd; + 3'h1: hval = 4'hc; + 3'h7: hval = 4'hf; + default: begin + $ignore("ERROR : %s [%m]", $sformatf("Illegal sel = %x", sel)); + hval = 4'bx; + end + endcase + end endmodule diff --git a/test_regress/t/t_lint_const_func_dpi_bad.out b/test_regress/t/t_lint_const_func_dpi_bad.out index f99b56df9..9be445bc4 100644 --- a/test_regress/t/t_lint_const_func_dpi_bad.out +++ b/test_regress/t/t_lint_const_func_dpi_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_lint_const_func_dpi_bad.v:8:32: Constant function may not be DPI import (IEEE 1800-2023 13.4.3) +%Error: t/t_lint_const_func_dpi_bad.v:8:31: Constant function may not be DPI import (IEEE 1800-2023 13.4.3) : ... note: In instance 't' - 8 | import "DPI-C" function int dpiFunc(); - | ^~~~~~~ + 8 | import "DPI-C" function int dpiFunc(); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_lint_const_func_dpi_bad.v:9:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'dpiFunc' +%Error: t/t_lint_const_func_dpi_bad.v:9:22: Expecting expression to be constant, but can't determine constant for FUNCREF 'dpiFunc' : ... note: In instance 't' - t/t_lint_const_func_dpi_bad.v:8:32: ... Location of non-constant FUNC 'dpiFunc': DPI import functions aren't simulatable - t/t_lint_const_func_dpi_bad.v:9:23: ... Called from 'dpiFunc()' with parameters: - 9 | localparam PARAM = dpiFunc(); - | ^~~~~~~ + t/t_lint_const_func_dpi_bad.v:8:31: ... Location of non-constant FUNC 'dpiFunc': DPI import functions aren't simulatable + t/t_lint_const_func_dpi_bad.v:9:22: ... Called from 'dpiFunc()' with parameters: + 9 | localparam PARAM = dpiFunc(); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_const_func_dpi_bad.v b/test_regress/t/t_lint_const_func_dpi_bad.v index 538f63ad4..1dcb30699 100644 --- a/test_regress/t/t_lint_const_func_dpi_bad.v +++ b/test_regress/t/t_lint_const_func_dpi_bad.v @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - import "DPI-C" function int dpiFunc(); - localparam PARAM = dpiFunc(); + import "DPI-C" function int dpiFunc(); + localparam PARAM = dpiFunc(); endmodule diff --git a/test_regress/t/t_lint_const_func_gen_bad.out b/test_regress/t/t_lint_const_func_gen_bad.out index db0c04d96..31fd6751d 100644 --- a/test_regress/t/t_lint_const_func_gen_bad.out +++ b/test_regress/t/t_lint_const_func_gen_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_lint_const_func_gen_bad.v:11:30: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3) +%Error: t/t_lint_const_func_gen_bad.v:11:28: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3) : ... note: In instance 't' - 11 | function automatic bit constFunc(); - | ^~~~~~~~~ + 11 | function automatic bit constFunc(); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_lint_const_func_gen_bad.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc' +%Error: t/t_lint_const_func_gen_bad.v:15:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc' : ... note: In instance 't' - t/t_lint_const_func_gen_bad.v:11:30: ... Location of non-constant FUNC 'constFunc': Constant function called under generate - t/t_lint_const_func_gen_bad.v:15:26: ... Called from 'constFunc()' with parameters: - 15 | localparam PARAM = constFunc(); - | ^~~~~~~~~ + t/t_lint_const_func_gen_bad.v:11:28: ... Location of non-constant FUNC 'constFunc': Constant function called under generate + t/t_lint_const_func_gen_bad.v:15:24: ... Called from 'constFunc()' with parameters: + 15 | localparam PARAM = constFunc(); + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_const_func_gen_bad.v b/test_regress/t/t_lint_const_func_gen_bad.v index 12013395b..e14768a5f 100644 --- a/test_regress/t/t_lint_const_func_gen_bad.v +++ b/test_regress/t/t_lint_const_func_gen_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - if (1) begin: GenConstFunc - // IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a - //generate block - function automatic bit constFunc(); - constFunc = 1'b1; - endfunction + if (1) begin: GenConstFunc + // IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a + //generate block + function automatic bit constFunc(); + constFunc = 1'b1; + endfunction - localparam PARAM = constFunc(); - end + localparam PARAM = constFunc(); + end endmodule diff --git a/test_regress/t/t_lint_contassreg_bad.out b/test_regress/t/t_lint_contassreg_bad.out index 21f3b5ec4..455ea686b 100644 --- a/test_regress/t/t_lint_contassreg_bad.out +++ b/test_regress/t/t_lint_contassreg_bad.out @@ -1,6 +1,6 @@ -%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:11: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r' +%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:10: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r' : ... note: In instance 't' - 14 | assign r = 1'b0; - | ^ + 14 | assign r = 1'b0; + | ^ ... For error description see https://verilator.org/warn/CONTASSREG?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lint_contassreg_bad.v b/test_regress/t/t_lint_contassreg_bad.v index b102e8243..275d41729 100644 --- a/test_regress/t/t_lint_contassreg_bad.v +++ b/test_regress/t/t_lint_contassreg_bad.v @@ -7,10 +7,10 @@ module t(r); - output r; + output r; - reg r; + reg r; - assign r = 1'b0; // Bad + assign r = 1'b0; // Bad endmodule diff --git a/test_regress/t/t_lint_declfilename.v b/test_regress/t/t_lint_declfilename.v index fe1b63720..3d3c38d4e 100644 --- a/test_regress/t/t_lint_declfilename.v +++ b/test_regress/t/t_lint_declfilename.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - t_lint_declfilename sub (); + t_lint_declfilename sub (); endmodule module t_lint_declfilename; diff --git a/test_regress/t/t_lint_declfilename_bbox.v b/test_regress/t/t_lint_declfilename_bbox.v index 76799025f..f4a82d80d 100644 --- a/test_regress/t/t_lint_declfilename_bbox.v +++ b/test_regress/t/t_lint_declfilename_bbox.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t_lint_declfilename_bbox (); - parameter IN = 0; - if (IN) begin : gen_hasbbox - // Should not warn, see bug2430 - BLACKBOXED bboxed (); - end + parameter IN = 0; + if (IN) begin : gen_hasbbox + // Should not warn, see bug2430 + BLACKBOXED bboxed (); + end endmodule diff --git a/test_regress/t/t_lint_defparam.v b/test_regress/t/t_lint_defparam.v index fc32e74a7..53cd18dfa 100644 --- a/test_regress/t/t_lint_defparam.v +++ b/test_regress/t/t_lint_defparam.v @@ -6,12 +6,12 @@ module t; - sub sub (); - defparam sub.P = 2; + sub sub (); + defparam sub.P = 2; endmodule module sub; - parameter P = 6; - if (P != 0) ; // Prevent unused + parameter P = 6; + if (P != 0); // Prevent unused endmodule diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index b87c43f2e..e73c11da0 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -1,7 +1,7 @@ -%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: defparam is deprecated (IEEE 1800-2023 C.4.1) +%Warning-DEFPARAM: t/t_lint_defparam.v:10:18: defparam is deprecated (IEEE 1800-2023 C.4.1) : ... Suggest use instantiation with #(.P(...etc...)) - 10 | defparam sub.P = 2; - | ^ + 10 | defparam sub.P = 2; + | ^ ... For warning description see https://verilator.org/warn/DEFPARAM?v=latest ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_edge_real_bad.out b/test_regress/t/t_lint_edge_real_bad.out index e8d3a3892..96acff7b4 100644 --- a/test_regress/t/t_lint_edge_real_bad.out +++ b/test_regress/t/t_lint_edge_real_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_lint_edge_real_bad.v:19:22: Edge event control not legal on real type (IEEE 1800-2023 6.12.1) +%Error: t/t_lint_edge_real_bad.v:19:21: Edge event control not legal on real type (IEEE 1800-2023 6.12.1) : ... note: In instance 't' - 19 | always @ (posedge rbad) $stop; - | ^~~~ + 19 | always @ (posedge rbad) $stop; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_lint_edge_real_bad.v:20:22: Edge event control not legal on non-integral type (IEEE 1800-2023 9.4.2) +%Error: t/t_lint_edge_real_bad.v:20:21: Edge event control not legal on non-integral type (IEEE 1800-2023 9.4.2) : ... note: In instance 't' - 20 | always @ (posedge ebad) $stop; - | ^~~~ + 20 | always @ (posedge ebad) $stop; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_edge_real_bad.v b/test_regress/t/t_lint_edge_real_bad.v index 83d4ad16b..95b23e5f7 100644 --- a/test_regress/t/t_lint_edge_real_bad.v +++ b/test_regress/t/t_lint_edge_real_bad.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - rbad, rok - ); - input real rbad; - input real rok; - event ebad; - struct packed { int a; } sok; + // Inputs + rbad, rok + ); + input real rbad; + input real rok; + event ebad; + struct packed { int a; } sok; - always @ (rok) $stop; - always @ (sok) $stop; + always @ (rok) $stop; + always @ (sok) $stop; - always @ (posedge rbad) $stop; - always @ (posedge ebad) $stop; + always @ (posedge rbad) $stop; + always @ (posedge ebad) $stop; endmodule diff --git a/test_regress/t/t_lint_genunnamed_bad.out b/test_regress/t/t_lint_genunnamed_bad.out index 0736b971f..c77495a9b 100644 --- a/test_regress/t/t_lint_genunnamed_bad.out +++ b/test_regress/t/t_lint_genunnamed_bad.out @@ -1,27 +1,27 @@ -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:14:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:14:5: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 14 | begin - | ^~~~~ + 14 | begin + | ^~~~~ ... For warning description see https://verilator.org/warn/GENUNNAMED?v=latest ... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message. -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:18:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:18:5: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 18 | begin - | ^~~~~ -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:22:4: Unnamed generate block 'genblk3' (IEEE 1800-2023 27.6) + 18 | begin + | ^~~~~ +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:22:3: Unnamed generate block 'genblk3' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 22 | for (genvar v = 0; v < P; ++v) ; - | ^~~ -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:24:4: Unnamed generate block 'genblk4' (IEEE 1800-2023 27.6) + 22 | for (genvar v = 0; v < P; ++v) ; + | ^~~ +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:24:3: Unnamed generate block 'genblk4' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 24 | for (genvar v = 0; v < P; ++v) - | ^~~ -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:30:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) + 24 | for (genvar v = 0; v < P; ++v) + | ^~~ +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:30:8: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 30 | 1: initial begin end - | ^~~~~~~ -%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:31:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) + 30 | 1: initial begin end + | ^~~~~~~ +%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:31:8: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' - 31 | 2: begin - | ^~~~~ + 31 | 2: begin + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_genunnamed_bad.v b/test_regress/t/t_lint_genunnamed_bad.v index c39ac02e5..98d629aab 100644 --- a/test_regress/t/t_lint_genunnamed_bad.v +++ b/test_regress/t/t_lint_genunnamed_bad.v @@ -6,31 +6,31 @@ module t; - parameter P = 1; + parameter P = 1; - if (P) ; + if (P) ; - if (P) - begin - initial $display; - end - else - begin - initial $display; - end + if (P) + begin + initial $display; + end + else + begin + initial $display; + end - for (genvar v = 0; v < P; ++v) ; + for (genvar v = 0; v < P; ++v) ; - for (genvar v = 0; v < P; ++v) - begin - initial $display; - end + for (genvar v = 0; v < P; ++v) + begin + initial $display; + end - case (P) - 1: initial begin end - 2: begin - initial begin end - end - endcase + case (P) + 1: initial begin end + 2: begin + initial begin end + end + endcase endmodule diff --git a/test_regress/t/t_lint_historical.v b/test_regress/t/t_lint_historical.v index 573c429cf..ac72beaca 100644 --- a/test_regress/t/t_lint_historical.v +++ b/test_regress/t/t_lint_historical.v @@ -5,124 +5,124 @@ // SPDX-License-Identifier: CC0-1.0 module t; - // Test all warnings, including those that are historically removed still parse - // verilator lint_off ALWCOMBORDER - // verilator lint_off ALWNEVER - // verilator lint_off ASCRANGE - // verilator lint_off ASSIGNDLY - // verilator lint_off ASSIGNEQEXPR - // verilator lint_off ASSIGNIN - // verilator lint_off BADSTDPRAGMA - // verilator lint_off BADVLTPRAGMA - // verilator lint_off BLKANDNBLK - // verilator lint_off BLKLOOPINIT - // verilator lint_off BLKSEQ - // verilator lint_off BSSPACE - // verilator lint_off CASEINCOMPLETE - // verilator lint_off CASEOVERLAP - // verilator lint_off CASEWITHX - // verilator lint_off CASEX - // verilator lint_off CASTCONST - // verilator lint_off CDCRSTLOGIC - // verilator lint_off CLKDATA - // verilator lint_off CMPCONST - // verilator lint_off COLONPLUS - // verilator lint_off COMBDLY - // verilator lint_off CONSTRAINTIGN - // verilator lint_off CONTASSREG - // verilator lint_off COVERIGN - // verilator lint_off DECLFILENAME - // verilator lint_off DEFOVERRIDE - // verilator lint_off DEFPARAM - // verilator lint_off DEPRECATED - // verilator lint_off ENCAPSULATED - // verilator lint_off ENDLABEL - // verilator lint_off ENUMITEMWIDTH - // verilator lint_off ENUMVALUE - // verilator lint_off EOFNEWLINE - // verilator lint_off FUNCTIMECTL - // verilator lint_off GENCLK - // verilator lint_off GENUNNAMED - // verilator lint_off HIERBLOCK - // verilator lint_off HIERPARAM - // verilator lint_off IFDEPTH - // verilator lint_off IGNOREDRETURN - // verilator lint_off IMPERFECTSCH - // verilator lint_off IMPLICIT - // verilator lint_off IMPLICITSTATIC - // verilator lint_off IMPORTSTAR - // verilator lint_off IMPURE - // verilator lint_off INCABSPATH - // verilator lint_off INFINITELOOP - // verilator lint_off INITIALDLY - // verilator lint_off INSECURE - // verilator lint_off INSIDETRUE - // verilator lint_off LATCH - // verilator lint_off LITENDIAN - // verilator lint_off MINTYPMAXDLY - // verilator lint_off MISINDENT - // verilator lint_off MODDUP - // verilator lint_off MODMISSING - // verilator lint_off MULTIDRIVEN - // verilator lint_off MULTITOP - // verilator lint_off NEWERSTD - // verilator lint_off NOEFFECT - // verilator lint_off NOLATCH - // verilator lint_off NONSTD - // verilator lint_off NORETURN - // verilator lint_off NULLPORT - // verilator lint_off PARAMNODEFAULT - // verilator lint_off PINCONNECTEMPTY - // verilator lint_off PINMISSING - // verilator lint_off PINNOCONNECT - // verilator lint_off PINNOTFOUND - // verilator lint_off PKGNODECL - // verilator lint_off PREPROCZERO - // verilator lint_off PROCASSINIT - // verilator lint_off PROCASSWIRE - // verilator lint_off PROFOUTOFDATE - // verilator lint_off PROTECTED - // verilator lint_off PROTOTYPEMIS - // verilator lint_off RANDC - // verilator lint_off REALCVT - // verilator lint_off REDEFMACRO - // verilator lint_off RISEFALLDLY - // verilator lint_off SELRANGE - // verilator lint_off SHORTREAL - // verilator lint_off SIDEEFFECT - // verilator lint_off SPECIFYIGN - // verilator lint_off SPLITVAR - // verilator lint_off STATICVAR - // verilator lint_off STMTDLY - // verilator lint_off SUPERNFIRST - // verilator lint_off SYMRSVDWORD - // verilator lint_off SYNCASYNCNET - // verilator lint_off TICKCOUNT - // verilator lint_off TIMESCALEMOD - // verilator lint_off UNDRIVEN - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - // verilator lint_off UNOPTTHREADS - // verilator lint_off UNPACKED - // verilator lint_off UNSATCONSTR - // verilator lint_off UNSIGNED - // verilator lint_off UNUSED - // verilator lint_off UNUSEDGENVAR - // verilator lint_off UNUSEDLOOP - // verilator lint_off UNUSEDPARAM - // verilator lint_off UNUSEDSIGNAL - // verilator lint_off USERERROR - // verilator lint_off USERFATAL - // verilator lint_off USERINFO - // verilator lint_off USERWARN - // verilator lint_off VARHIDDEN - // verilator lint_off WAITCONST - // verilator lint_off WIDTH - // verilator lint_off WIDTHCONCAT - // verilator lint_off WIDTHEXPAND - // verilator lint_off WIDTHTRUNC - // verilator lint_off WIDTHXZEXPAND - // verilator lint_off ZERODLY - // verilator lint_off ZEROREPL + // Test all warnings, including those that are historically removed still parse + // verilator lint_off ALWCOMBORDER + // verilator lint_off ALWNEVER + // verilator lint_off ASCRANGE + // verilator lint_off ASSIGNDLY + // verilator lint_off ASSIGNEQEXPR + // verilator lint_off ASSIGNIN + // verilator lint_off BADSTDPRAGMA + // verilator lint_off BADVLTPRAGMA + // verilator lint_off BLKANDNBLK + // verilator lint_off BLKLOOPINIT + // verilator lint_off BLKSEQ + // verilator lint_off BSSPACE + // verilator lint_off CASEINCOMPLETE + // verilator lint_off CASEOVERLAP + // verilator lint_off CASEWITHX + // verilator lint_off CASEX + // verilator lint_off CASTCONST + // verilator lint_off CDCRSTLOGIC + // verilator lint_off CLKDATA + // verilator lint_off CMPCONST + // verilator lint_off COLONPLUS + // verilator lint_off COMBDLY + // verilator lint_off CONSTRAINTIGN + // verilator lint_off CONTASSREG + // verilator lint_off COVERIGN + // verilator lint_off DECLFILENAME + // verilator lint_off DEFOVERRIDE + // verilator lint_off DEFPARAM + // verilator lint_off DEPRECATED + // verilator lint_off ENCAPSULATED + // verilator lint_off ENDLABEL + // verilator lint_off ENUMITEMWIDTH + // verilator lint_off ENUMVALUE + // verilator lint_off EOFNEWLINE + // verilator lint_off FUNCTIMECTL + // verilator lint_off GENCLK + // verilator lint_off GENUNNAMED + // verilator lint_off HIERBLOCK + // verilator lint_off HIERPARAM + // verilator lint_off IFDEPTH + // verilator lint_off IGNOREDRETURN + // verilator lint_off IMPERFECTSCH + // verilator lint_off IMPLICIT + // verilator lint_off IMPLICITSTATIC + // verilator lint_off IMPORTSTAR + // verilator lint_off IMPURE + // verilator lint_off INCABSPATH + // verilator lint_off INFINITELOOP + // verilator lint_off INITIALDLY + // verilator lint_off INSECURE + // verilator lint_off INSIDETRUE + // verilator lint_off LATCH + // verilator lint_off LITENDIAN + // verilator lint_off MINTYPMAXDLY + // verilator lint_off MISINDENT + // verilator lint_off MODDUP + // verilator lint_off MODMISSING + // verilator lint_off MULTIDRIVEN + // verilator lint_off MULTITOP + // verilator lint_off NEWERSTD + // verilator lint_off NOEFFECT + // verilator lint_off NOLATCH + // verilator lint_off NONSTD + // verilator lint_off NORETURN + // verilator lint_off NULLPORT + // verilator lint_off PARAMNODEFAULT + // verilator lint_off PINCONNECTEMPTY + // verilator lint_off PINMISSING + // verilator lint_off PINNOCONNECT + // verilator lint_off PINNOTFOUND + // verilator lint_off PKGNODECL + // verilator lint_off PREPROCZERO + // verilator lint_off PROCASSINIT + // verilator lint_off PROCASSWIRE + // verilator lint_off PROFOUTOFDATE + // verilator lint_off PROTECTED + // verilator lint_off PROTOTYPEMIS + // verilator lint_off RANDC + // verilator lint_off REALCVT + // verilator lint_off REDEFMACRO + // verilator lint_off RISEFALLDLY + // verilator lint_off SELRANGE + // verilator lint_off SHORTREAL + // verilator lint_off SIDEEFFECT + // verilator lint_off SPECIFYIGN + // verilator lint_off SPLITVAR + // verilator lint_off STATICVAR + // verilator lint_off STMTDLY + // verilator lint_off SUPERNFIRST + // verilator lint_off SYMRSVDWORD + // verilator lint_off SYNCASYNCNET + // verilator lint_off TICKCOUNT + // verilator lint_off TIMESCALEMOD + // verilator lint_off UNDRIVEN + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off UNOPTTHREADS + // verilator lint_off UNPACKED + // verilator lint_off UNSATCONSTR + // verilator lint_off UNSIGNED + // verilator lint_off UNUSED + // verilator lint_off UNUSEDGENVAR + // verilator lint_off UNUSEDLOOP + // verilator lint_off UNUSEDPARAM + // verilator lint_off UNUSEDSIGNAL + // verilator lint_off USERERROR + // verilator lint_off USERFATAL + // verilator lint_off USERINFO + // verilator lint_off USERWARN + // verilator lint_off VARHIDDEN + // verilator lint_off WAITCONST + // verilator lint_off WIDTH + // verilator lint_off WIDTHCONCAT + // verilator lint_off WIDTHEXPAND + // verilator lint_off WIDTHTRUNC + // verilator lint_off WIDTHXZEXPAND + // verilator lint_off ZERODLY + // verilator lint_off ZEROREPL endmodule diff --git a/test_regress/t/t_lint_iface_array_topmodule1.v b/test_regress/t/t_lint_iface_array_topmodule1.v index 5e55cd37c..1334d2777 100644 --- a/test_regress/t/t_lint_iface_array_topmodule1.v +++ b/test_regress/t/t_lint_iface_array_topmodule1.v @@ -6,43 +6,35 @@ interface my_if; - logic valid; - logic [7:0] data ; + logic valid; + logic [7:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); endinterface -module t - ( - input wire clk, - my_if.slave_mp in_if [2], - my_if.master_mp out_if [2] - ); +module t ( + input wire clk, + my_if.slave_mp in_if[2], + my_if.master_mp out_if[2] +); - my_if my_i [2] (); + my_if my_i[2] (); - always @(posedge clk) - begin - my_i[0].valid <= in_if[0].valid; - my_i[0].data <= in_if[0].data; + always @(posedge clk) begin + my_i[0].valid <= in_if[0].valid; + my_i[0].data <= in_if[0].data; - my_i[1].valid <= in_if[1].valid; - my_i[1].data <= in_if[1].data; - end + my_i[1].valid <= in_if[1].valid; + my_i[1].data <= in_if[1].data; + end - assign out_if[0].valid = my_i[0].valid; - assign out_if[0].data = my_i[0].data; + assign out_if[0].valid = my_i[0].valid; + assign out_if[0].data = my_i[0].data; - assign out_if[1].valid = my_i[1].valid; - assign out_if[1].data = my_i[1].data; + assign out_if[1].valid = my_i[1].valid; + assign out_if[1].data = my_i[1].data; endmodule diff --git a/test_regress/t/t_lint_iface_array_topmodule2.v b/test_regress/t/t_lint_iface_array_topmodule2.v index 7507ddbcd..6b684914f 100644 --- a/test_regress/t/t_lint_iface_array_topmodule2.v +++ b/test_regress/t/t_lint_iface_array_topmodule2.v @@ -5,35 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 interface my_if #( - parameter DW = 8 - ) (); + parameter DW = 8 +) (); - logic valid; - logic [DW-1:0] data ; + logic valid; + logic [DW-1:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); endinterface -module t - ( - input wire clk, - my_if.slave_mp in_if [2], - my_if.master_mp out_if [2] - ); +module t ( + input wire clk, + my_if.slave_mp in_if[2], + my_if.master_mp out_if[2] +); - assign out_if[0].valid = in_if[0].valid; - assign out_if[0].data = in_if[0].data; + assign out_if[0].valid = in_if[0].valid; + assign out_if[0].data = in_if[0].data; - assign out_if[1].valid = in_if[1].valid; - assign out_if[1].data = in_if[1].data; + assign out_if[1].valid = in_if[1].valid; + assign out_if[1].data = in_if[1].data; endmodule diff --git a/test_regress/t/t_lint_iface_array_topmodule3.v b/test_regress/t/t_lint_iface_array_topmodule3.v index dcaea4940..e6d4bae81 100644 --- a/test_regress/t/t_lint_iface_array_topmodule3.v +++ b/test_regress/t/t_lint_iface_array_topmodule3.v @@ -4,74 +4,68 @@ // SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 -interface my_if #( parameter integer DW = 8 ) (input clk); +interface my_if #( + parameter integer DW = 8 +) ( + input clk +); - localparam DW_LOCAL = DW; + localparam DW_LOCAL = DW; - logic valid; - logic [DW-1:0] data; + logic valid; + logic [DW-1:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); - function automatic integer width(); - return $bits(data); - endfunction + function automatic integer width(); + return $bits(data); + endfunction - generate - if (DW < 4) - begin: dw_lt_4_G - function automatic integer min_width(); - return 4; - endfunction - end - else - begin: dw_ge_4_G - function automatic integer min_width(); - return 8; - endfunction - end - endgenerate + generate + if (DW < 4) begin : dw_lt_4_G + function automatic integer min_width(); + return 4; + endfunction + end + else begin : dw_ge_4_G + function automatic integer min_width(); + return 8; + endfunction + end + endgenerate endinterface -module t - ( - input wire clk, - my_if in_if [2], - my_if out_if [2] - ); +module t ( + input wire clk, + my_if in_if[2], + my_if out_if[2] +); - assign out_if[0].valid = in_if[0].valid; - assign out_if[0].data = in_if[0].data; + assign out_if[0].valid = in_if[0].valid; + assign out_if[0].data = in_if[0].data; - assign out_if[1].valid = in_if[1].valid; - assign out_if[1].data = in_if[1].data; + assign out_if[1].valid = in_if[1].valid; + assign out_if[1].data = in_if[1].data; - my_if my_i (.clk(clk)); + my_if my_i (.clk(clk)); - initial - begin - $display(in_if[0].DW_LOCAL); - $display(in_if[0].width()); - $display(in_if[0].dw_ge_4_G.min_width()); - $display(out_if[0].DW_LOCAL); - $display(out_if[0].width()); - $display(out_if[0].dw_ge_4_G.min_width()); + initial begin + $display(in_if[0].DW_LOCAL); + $display(in_if[0].width()); + $display(in_if[0].dw_ge_4_G.min_width()); + $display(out_if[0].DW_LOCAL); + $display(out_if[0].width()); + $display(out_if[0].dw_ge_4_G.min_width()); - $display(in_if[1].DW_LOCAL); - $display(in_if[1].width()); - $display(in_if[1].dw_ge_4_G.min_width()); - $display(out_if[1].DW_LOCAL); - $display(out_if[1].width()); - $display(out_if[1].dw_ge_4_G.min_width()); - end + $display(in_if[1].DW_LOCAL); + $display(in_if[1].width()); + $display(in_if[1].dw_ge_4_G.min_width()); + $display(out_if[1].DW_LOCAL); + $display(out_if[1].width()); + $display(out_if[1].dw_ge_4_G.min_width()); + end endmodule diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.out b/test_regress/t/t_lint_iface_array_topmodule_bad.out index 3c577338d..86ed769cf 100644 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.out +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_iface_array_topmodule_bad.v:8:24: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' +%Error: t/t_lint_iface_array_topmodule_bad.v:8:23: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' : ... note: In instance 't' - 8 | parameter integer DW - | ^~ + 8 | parameter integer DW + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.v b/test_regress/t/t_lint_iface_array_topmodule_bad.v index 398c9ef6e..dba6f6224 100644 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.v +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.v @@ -5,46 +5,46 @@ // SPDX-License-Identifier: CC0-1.0 interface my_if #( - parameter integer DW - ) (); + parameter integer DW + ) (); - logic valid; - logic [7:0] data ; + logic valid; + logic [7:0] data ; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp ( + input valid, + input data + ); - modport master_mp ( - output valid, - output data - ); + modport master_mp ( + output valid, + output data + ); endinterface module t ( - input wire clk, - my_if.slave_mp in_if [2], - my_if.master_mp out_if [2] - ); + input wire clk, + my_if.slave_mp in_if [2], + my_if.master_mp out_if [2] + ); - my_if my_i [2] (); + my_if my_i [2] (); - always @(posedge clk) - begin - my_i[0].valid <= in_if[0].valid; - my_i[0].data <= in_if[0].data; + always @(posedge clk) + begin + my_i[0].valid <= in_if[0].valid; + my_i[0].data <= in_if[0].data; - my_i[1].valid <= in_if[1].valid; - my_i[1].data <= in_if[1].data; - end + my_i[1].valid <= in_if[1].valid; + my_i[1].data <= in_if[1].data; + end - assign out_if[0].valid = my_i[0].valid; - assign out_if[0].data = my_i[0].data; + assign out_if[0].valid = my_i[0].valid; + assign out_if[0].data = my_i[0].data; - assign out_if[1].valid = my_i[1].valid; - assign out_if[1].data = my_i[1].data; + assign out_if[1].valid = my_i[1].valid; + assign out_if[1].data = my_i[1].data; endmodule diff --git a/test_regress/t/t_lint_iface_topmodule1.v b/test_regress/t/t_lint_iface_topmodule1.v index 0fce52ec9..e0da864d3 100644 --- a/test_regress/t/t_lint_iface_topmodule1.v +++ b/test_regress/t/t_lint_iface_topmodule1.v @@ -6,37 +6,29 @@ interface my_if; - logic valid; - logic [7:0] data ; + logic valid; + logic [7:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); endinterface -module t - ( - input wire clk, - my_if.slave_mp in_if, - my_if.master_mp out_if - ); +module t ( + input wire clk, + my_if.slave_mp in_if, + my_if.master_mp out_if +); - my_if my_i (); + my_if my_i (); - always @(posedge clk) - begin - my_i.valid <= in_if.valid; - my_i.data <= in_if.data; - end + always @(posedge clk) begin + my_i.valid <= in_if.valid; + my_i.data <= in_if.data; + end - assign out_if.valid = my_i.valid; - assign out_if.data = my_i.data; + assign out_if.valid = my_i.valid; + assign out_if.data = my_i.data; endmodule diff --git a/test_regress/t/t_lint_iface_topmodule2.v b/test_regress/t/t_lint_iface_topmodule2.v index e06c6f30f..8ab21f470 100644 --- a/test_regress/t/t_lint_iface_topmodule2.v +++ b/test_regress/t/t_lint_iface_topmodule2.v @@ -6,30 +6,23 @@ interface my_if #( parameter integer DW = 8 - ) (); - logic valid; - logic [DW-1:0] data; +) (); + logic valid; + logic [DW-1:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); endinterface -module t - ( - input wire clk, - my_if.slave_mp in_if, - my_if.master_mp out_if - ); +module t ( + input wire clk, + my_if.slave_mp in_if, + my_if.master_mp out_if +); - assign out_if.valid = in_if.valid; - assign out_if.data = in_if.data; + assign out_if.valid = in_if.valid; + assign out_if.data = in_if.data; endmodule diff --git a/test_regress/t/t_lint_iface_topmodule3.v b/test_regress/t/t_lint_iface_topmodule3.v index 712fdce13..fc71f12df 100644 --- a/test_regress/t/t_lint_iface_topmodule3.v +++ b/test_regress/t/t_lint_iface_topmodule3.v @@ -4,64 +4,58 @@ // SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 -interface my_if #( parameter integer DW = 8 ) (input clk); +interface my_if #( + parameter integer DW = 8 +) ( + input clk +); - localparam DW_LOCAL = DW; + localparam DW_LOCAL = DW; - logic valid; - logic [DW-1:0] data; + logic valid; + logic [DW-1:0] data; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp(input valid, input data); - modport master_mp ( - output valid, - output data - ); + modport master_mp(output valid, output data); - function automatic integer width(); - return $bits(data); - endfunction + function automatic integer width(); + return $bits(data); + endfunction - generate - if (DW < 4) - begin: dw_lt_4_G - function automatic integer min_width(); - return 4; - endfunction - end - else - begin: dw_ge_4_G - function automatic integer min_width(); - return 8; - endfunction - end - endgenerate + generate + if (DW < 4) begin : dw_lt_4_G + function automatic integer min_width(); + return 4; + endfunction + end + else begin : dw_ge_4_G + function automatic integer min_width(); + return 8; + endfunction + end + endgenerate endinterface -module t - ( - input wire clk, - my_if in_if, - my_if out_if - ); +module t ( + input wire clk, + my_if in_if, + my_if out_if +); - assign out_if.valid = in_if.valid; - assign out_if.data = in_if.data; + assign out_if.valid = in_if.valid; + assign out_if.data = in_if.data; - my_if my_i (.clk(clk)); + my_if my_i (.clk(clk)); - initial - begin - $display(in_if.DW_LOCAL); - $display(in_if.width()); - $display(in_if.dw_ge_4_G.min_width()); - $display(out_if.DW_LOCAL); - $display(out_if.width()); - $display(out_if.dw_ge_4_G.min_width()); - end + initial begin + $display(in_if.DW_LOCAL); + $display(in_if.width()); + $display(in_if.dw_ge_4_G.min_width()); + $display(out_if.DW_LOCAL); + $display(out_if.width()); + $display(out_if.dw_ge_4_G.min_width()); + end endmodule diff --git a/test_regress/t/t_lint_iface_topmodule_bad.out b/test_regress/t/t_lint_iface_topmodule_bad.out index 26ccff508..a6c5b0a9c 100644 --- a/test_regress/t/t_lint_iface_topmodule_bad.out +++ b/test_regress/t/t_lint_iface_topmodule_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_iface_topmodule_bad.v:8:23: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' +%Error: t/t_lint_iface_topmodule_bad.v:8:22: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' : ... note: In instance 't' - 8 | parameter integer DW - | ^~ + 8 | parameter integer DW + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_lint_iface_topmodule_bad.v b/test_regress/t/t_lint_iface_topmodule_bad.v index 41cf70dac..c5c29e840 100644 --- a/test_regress/t/t_lint_iface_topmodule_bad.v +++ b/test_regress/t/t_lint_iface_topmodule_bad.v @@ -5,40 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 interface my_if #( - parameter integer DW - ) (); + parameter integer DW + ) (); - logic valid; - logic [DW-1:0] data ; + logic valid; + logic [DW-1:0] data ; - modport slave_mp ( - input valid, - input data - ); + modport slave_mp ( + input valid, + input data + ); - modport master_mp ( - output valid, - output data - ); + modport master_mp ( + output valid, + output data + ); endinterface module t ( - input wire clk, - my_if.slave_mp in_if, - my_if.master_mp out_if - ); + input wire clk, + my_if.slave_mp in_if, + my_if.master_mp out_if + ); - my_if my_i (); + my_if my_i (); - always @(posedge clk) - begin - my_i.valid <= in_if.valid; - my_i.data <= in_if.data; - end + always @(posedge clk) + begin + my_i.valid <= in_if.valid; + my_i.data <= in_if.data; + end - assign out_if.valid = my_i.valid; - assign out_if.data = my_i.data; + assign out_if.valid = my_i.valid; + assign out_if.data = my_i.data; endmodule diff --git a/test_regress/t/t_lint_ifdepth_bad.out b/test_regress/t/t_lint_ifdepth_bad.out index 43e2eca53..fa6cec570 100644 --- a/test_regress/t/t_lint_ifdepth_bad.out +++ b/test_regress/t/t_lint_ifdepth_bad.out @@ -1,7 +1,7 @@ -%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:12: Deep 'if' statement; suggest unique/priority to avoid slow logic +%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:10: Deep 'if' statement; suggest unique/priority to avoid slow logic : ... note: In instance 't' - 22 | else if (value==11) begin end - | ^~ + 22 | else if (value==11) begin end + | ^~ ... For warning description see https://verilator.org/warn/IFDEPTH?v=latest ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_ifdepth_bad.v b/test_regress/t/t_lint_ifdepth_bad.v index 9eb6ac4a8..661326f7a 100644 --- a/test_regress/t/t_lint_ifdepth_bad.v +++ b/test_regress/t/t_lint_ifdepth_bad.v @@ -6,36 +6,36 @@ module t; - integer value = 19; + integer value = 19; - initial begin - if (value==1) begin end - else if (value==2) begin end - else if (value==3) begin end - else if (value==4) begin end - else if (value==5) begin end - else if (value==6) begin end - else if (value==7) begin end - else if (value==8) begin end - else if (value==9) begin end - else if (value==10) begin end - else if (value==11) begin end // Warn about this one - else if (value==12) begin end - end + initial begin + if (value==1) begin end + else if (value==2) begin end + else if (value==3) begin end + else if (value==4) begin end + else if (value==5) begin end + else if (value==6) begin end + else if (value==7) begin end + else if (value==8) begin end + else if (value==9) begin end + else if (value==10) begin end + else if (value==11) begin end // Warn about this one + else if (value==12) begin end + end - initial begin - unique0 if (value==1) begin end - else if (value==2) begin end - else if (value==3) begin end - else if (value==4) begin end - else if (value==5) begin end - else if (value==6) begin end - else if (value==7) begin end - else if (value==8) begin end - else if (value==9) begin end - else if (value==10) begin end - else if (value==11) begin end // Warn about this one - else if (value==12) begin end - end + initial begin + unique0 if (value==1) begin end + else if (value==2) begin end + else if (value==3) begin end + else if (value==4) begin end + else if (value==5) begin end + else if (value==6) begin end + else if (value==7) begin end + else if (value==8) begin end + else if (value==9) begin end + else if (value==10) begin end + else if (value==11) begin end // Warn about this one + else if (value==12) begin end + end endmodule diff --git a/test_regress/t/t_lint_implicit.v b/test_regress/t/t_lint_implicit.v index 34d04a194..635529b94 100644 --- a/test_regress/t/t_lint_implicit.v +++ b/test_regress/t/t_lint_implicit.v @@ -4,16 +4,19 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (a,z); - input a; - output z; +module t ( + a, + z +); + input a; + output z; - assign b = 1'b1; + assign b = 1'b1; - or OR0 (nt0, a, b); + or OR0 (nt0, a, b); - logic [1:0] dummy_ip; - assign {dummy1, dummy2} = dummy_ip; + logic [1:0] dummy_ip; + assign {dummy1, dummy2} = dummy_ip; - assign z = nt0; + assign z = nt0; endmodule diff --git a/test_regress/t/t_lint_implicit_bad.out b/test_regress/t/t_lint_implicit_bad.out index 95dda11c3..e3c7ef54d 100644 --- a/test_regress/t/t_lint_implicit_bad.out +++ b/test_regress/t/t_lint_implicit_bad.out @@ -1,17 +1,17 @@ -%Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' - 11 | assign b = 1'b1; - | ^ +%Warning-IMPLICIT: t/t_lint_implicit.v:14:10: Signal definition not found, creating implicitly: 'b' + 14 | assign b = 1'b1; + | ^ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' - 13 | or OR0 (nt0, a, b); - | ^~~ -%Warning-IMPLICIT: t/t_lint_implicit.v:16:12: Signal definition not found, creating implicitly: 'dummy1' +%Warning-IMPLICIT: t/t_lint_implicit.v:16:11: Signal definition not found, creating implicitly: 'nt0' + 16 | or OR0 (nt0, a, b); + | ^~~ +%Warning-IMPLICIT: t/t_lint_implicit.v:19:11: Signal definition not found, creating implicitly: 'dummy1' : ... Suggested alternative: 'dummy_ip' - 16 | assign {dummy1, dummy2} = dummy_ip; - | ^~~~~~ -%Warning-IMPLICIT: t/t_lint_implicit.v:16:20: Signal definition not found, creating implicitly: 'dummy2' + 19 | assign {dummy1, dummy2} = dummy_ip; + | ^~~~~~ +%Warning-IMPLICIT: t/t_lint_implicit.v:19:19: Signal definition not found, creating implicitly: 'dummy2' : ... Suggested alternative: 'dummy1' - 16 | assign {dummy1, dummy2} = dummy_ip; - | ^~~~~~ + 19 | assign {dummy1, dummy2} = dummy_ip; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out index 9e3922d13..165cf7048 100644 --- a/test_regress/t/t_lint_implicit_def_bad.out +++ b/test_regress/t/t_lint_implicit_def_bad.out @@ -1,10 +1,10 @@ -%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' - 13 | assign imp_warn = 1'b1; - | ^~~~~~~~ +%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:10: Signal definition not found, creating implicitly: 'imp_warn' + 13 | assign imp_warn = 1'b1; + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' - 18 | assign imp_err = 1'b1; - | ^~~~~~~ +%Error: t/t_lint_implicit_def_bad.v:18:10: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' + 18 | assign imp_err = 1'b1; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_def_bad.v b/test_regress/t/t_lint_implicit_def_bad.v index 34f8563ad..76bb75971 100644 --- a/test_regress/t/t_lint_implicit_def_bad.v +++ b/test_regress/t/t_lint_implicit_def_bad.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t (a,z); - input a; - output z; + input a; + output z; - sub sub (); + sub sub (); - assign imp_warn = 1'b1; - // verilator lint_off IMPLICIT - assign imp_ok = 1'b1; + assign imp_warn = 1'b1; + // verilator lint_off IMPLICIT + assign imp_ok = 1'b1; `default_nettype none - assign imp_err = 1'b1; + assign imp_err = 1'b1; `default_nettype wire - assign imp_ok2 = 1'b1; + assign imp_ok2 = 1'b1; endmodule `default_nettype none `resetall module sub; - assign imp_ok3 = 1'b1; + assign imp_ok3 = 1'b1; endmodule diff --git a/test_regress/t/t_lint_implicit_func_bad.out b/test_regress/t/t_lint_implicit_func_bad.out index 40cc8b0ca..bdeb0ad4d 100644 --- a/test_regress/t/t_lint_implicit_func_bad.out +++ b/test_regress/t/t_lint_implicit_func_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_implicit_func_bad.v:12:11: Cannot call a task/void-function as a function: 'imp_func_conflict' +%Error: t/t_lint_implicit_func_bad.v:12:10: Cannot call a task/void-function as a function: 'imp_func_conflict' : ... note: In instance 't' - 12 | assign imp_func_conflict = 1'b1; - | ^~~~~~~~~~~~~~~~~ + 12 | assign imp_func_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_func_bad.v b/test_regress/t/t_lint_implicit_func_bad.v index 0e79e153c..1c054539e 100644 --- a/test_regress/t/t_lint_implicit_func_bad.v +++ b/test_regress/t/t_lint_implicit_func_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t; - function void imp_func_conflict(); - endfunction + function void imp_func_conflict(); + endfunction `default_nettype wire - assign imp_func_conflict = 1'b1; + assign imp_func_conflict = 1'b1; endmodule diff --git a/test_regress/t/t_lint_implicit_port.v b/test_regress/t/t_lint_implicit_port.v index c57b8c5b2..fb83663e3 100644 --- a/test_regress/t/t_lint_implicit_port.v +++ b/test_regress/t/t_lint_implicit_port.v @@ -4,30 +4,37 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - logic oe; + logic oe; - read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) ); - sets s (.clk(clk), .enable(implicit_write)); - read u (.clk(clk), .data(~implicit_also)); + read r ( + .clk(clk), + .data(((oe == 1'd001) && implicit_write)) + ); + sets s ( + .clk(clk), + .enable(implicit_write) + ); + read u ( + .clk(clk), + .data(~implicit_also) + ); endmodule module sets ( - input clk, - output enable - ); - assign enable = 1'b0; + input clk, + output enable +); + assign enable = 1'b0; endmodule module read ( - input clk, - input data - ); + input clk, + input data +); endmodule diff --git a/test_regress/t/t_lint_implicit_type_bad.out b/test_regress/t/t_lint_implicit_type_bad.out index 3d0241a7e..85e7e76b1 100644 --- a/test_regress/t/t_lint_implicit_type_bad.out +++ b/test_regress/t/t_lint_implicit_type_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_lint_implicit_type_bad.v:15:11: Data type used where a non-data type is expected: 'imp_typedef_conflict' - 15 | assign imp_typedef_conflict = 1'b1; - | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_lint_implicit_type_bad.v:15:10: Data type used where a non-data type is expected: 'imp_typedef_conflict' + 15 | assign imp_typedef_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_lint_implicit_type_bad.v:16:11: Data type used where a non-data type is expected: 'imp_Cls_conflict' - 16 | assign imp_Cls_conflict = 1'b1; - | ^~~~~~~~~~~~~~~~ -%Error: t/t_lint_implicit_type_bad.v:17:11: Data type used where a non-data type is expected: 'imp_PARAM_conflict' - 17 | assign imp_PARAM_conflict = 1'b1; - | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_lint_implicit_type_bad.v:16:10: Data type used where a non-data type is expected: 'imp_Cls_conflict' + 16 | assign imp_Cls_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~ +%Error: t/t_lint_implicit_type_bad.v:17:10: Data type used where a non-data type is expected: 'imp_PARAM_conflict' + 17 | assign imp_PARAM_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_type_bad.v b/test_regress/t/t_lint_implicit_type_bad.v index 4a878b3ae..0b3183224 100644 --- a/test_regress/t/t_lint_implicit_type_bad.v +++ b/test_regress/t/t_lint_implicit_type_bad.v @@ -8,11 +8,11 @@ class imp_Cls_conflict; endclass module t; - typedef int imp_typedef_conflict; - localparam type imp_PARAM_conflict; + typedef int imp_typedef_conflict; + localparam type imp_PARAM_conflict; `default_nettype wire - assign imp_typedef_conflict = 1'b1; - assign imp_Cls_conflict = 1'b1; - assign imp_PARAM_conflict = 1'b1; + assign imp_typedef_conflict = 1'b1; + assign imp_Cls_conflict = 1'b1; + assign imp_PARAM_conflict = 1'b1; endmodule diff --git a/test_regress/t/t_lint_import_name_bad.v b/test_regress/t/t_lint_import_name_bad.v index b1852bd1b..eed92ec7b 100644 --- a/test_regress/t/t_lint_import_name_bad.v +++ b/test_regress/t/t_lint_import_name_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 package defs; - int sig; + int sig; endpackage import defs::sigs; diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index d3b522660..6dc9a6738 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -3,10 +3,10 @@ | ^~~~ ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=latest ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. -%Warning-UNUSEDPARAM: t/t_lint_importstar_bad.v:8:15: Parameter is not used: 'PAR' +%Warning-UNUSEDPARAM: t/t_lint_importstar_bad.v:8:14: Parameter is not used: 'PAR' : ... note: In instance 't' - 8 | localparam PAR = 1; - | ^~~ + 8 | localparam PAR = 1; + | ^~~ ... For warning description see https://verilator.org/warn/UNUSEDPARAM?v=latest ... Use "/* verilator lint_off UNUSEDPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_importstar_bad.v b/test_regress/t/t_lint_importstar_bad.v index 4dc7f6818..681df7c9b 100644 --- a/test_regress/t/t_lint_importstar_bad.v +++ b/test_regress/t/t_lint_importstar_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 package defs; - localparam PAR = 1; + localparam PAR = 1; endpackage import defs::*; diff --git a/test_regress/t/t_lint_infinite.v b/test_regress/t/t_lint_infinite.v index 62a8667e3..0a684863e 100644 --- a/test_regress/t/t_lint_infinite.v +++ b/test_regress/t/t_lint_infinite.v @@ -6,31 +6,31 @@ module t; - mailbox #(int) mbox; + mailbox #(int) mbox; - task main(); - // See issue #4323; not an INFINITELOOP due to delay inside get() - forever begin - int i; - mbox.get(i); - $display("[%0t] Got %0d", $time, i); - end - endtask + task main(); + // See issue #4323; not an INFINITELOOP due to delay inside get() + forever begin + int i; + mbox.get(i); + $display("[%0t] Got %0d", $time, i); + end + endtask - initial begin - mbox = new (1); + initial begin + mbox = new(1); - #10; - fork - main(); - join_none + #10; + fork + main(); + join_none - #10; - mbox.put(10); - mbox.put(11); + #10; + mbox.put(10); + mbox.put(11); - #10; - $write("*-* All Finished *-*\n"); - $finish; - end + #10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_lint_infinite_bad.out b/test_regress/t/t_lint_infinite_bad.out index 3a324846d..3f6e9a80b 100644 --- a/test_regress/t/t_lint_infinite_bad.out +++ b/test_regress/t/t_lint_infinite_bad.out @@ -1,11 +1,11 @@ -%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:7: Infinite loop (condition always true) +%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:5: Infinite loop (condition always true) : ... note: In instance 't' - 10 | forever begin end - | ^~~~~~~ + 10 | forever begin end + | ^~~~~~~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. -%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:7: Infinite loop (condition always true) +%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:5: Infinite loop (condition always true) : ... note: In instance 't' - 12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end - | ^~~ + 12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_infinite_bad.v b/test_regress/t/t_lint_infinite_bad.v index 0b74bcef1..f907a991d 100644 --- a/test_regress/t/t_lint_infinite_bad.v +++ b/test_regress/t/t_lint_infinite_bad.v @@ -6,10 +6,10 @@ module t; - initial begin - forever begin end - // verilator lint_off UNSIGNED - for (reg [31:0] i=0; i>=0; i=i+1) begin end - $display; // So loop not eaten - end + initial begin + forever begin end + // verilator lint_off UNSIGNED + for (reg [31:0] i=0; i>=0; i=i+1) begin end + $display; // So loop not eaten + end endmodule diff --git a/test_regress/t/t_lint_inherit.v b/test_regress/t/t_lint_inherit.v index 4a8ccac95..3ae631711 100644 --- a/test_regress/t/t_lint_inherit.v +++ b/test_regress/t/t_lint_inherit.v @@ -4,59 +4,60 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - q, - // Inputs - clk, d - ); - input clk; - input d; - output wire [1:0] q; +module t ( /*AUTOARG*/ + // Outputs + q, + // Inputs + clk, + d +); + input clk; + input d; + output wire [1:0] q; - // This demonstrates how warning disables should be propagated across module boundaries. + // This demonstrates how warning disables should be propagated across module boundaries. - m1 m1 (/*AUTOINST*/ - // Outputs - .q (q[1:0]), - // Inputs - .clk (clk), - .d (d)); + m1 m1 ( /*AUTOINST*/ + // Outputs + .q(q[1:0]), + // Inputs + .clk(clk), + .d(d) + ); endmodule -module m1 - ( - input clk, - input d, - output wire [1:0] q - ); +module m1 ( + input clk, + input d, + output wire [1:0] q +); - m2 m2 (/*AUTOINST*/ - // Outputs - .q (q[1:0]), - // Inputs - .clk (clk), - .d (d)); + m2 m2 ( /*AUTOINST*/ + // Outputs + .q(q[1:0]), + // Inputs + .clk(clk), + .d(d) + ); endmodule -module m2 - ( - input clk, - input d, - // Due to bug the below disable used to be ignored. - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - output reg [1:0] q - // verilator lint_on UNOPT - // verilator lint_on UNOPTFLAT - ); +module m2 ( + input clk, + input d, + // Due to bug the below disable used to be ignored. + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + output reg [1:0] q + // verilator lint_on UNOPT + // verilator lint_on UNOPTFLAT +); - always @* begin - q[1] = d; - end + always @* begin + q[1] = d; + end - always @* begin - q[0] = q[1]; - end + always @* begin + q[0] = q[1]; + end endmodule diff --git a/test_regress/t/t_lint_input_eq_good.v b/test_regress/t/t_lint_input_eq_good.v index 6e7600492..ea4235858 100644 --- a/test_regress/t/t_lint_input_eq_good.v +++ b/test_regress/t/t_lint_input_eq_good.v @@ -4,10 +4,9 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - ( - input wire i, - input wire i2 = i // Good under IEEE 1800-2009 - ); +module t ( + input wire i, + input wire i2 = i // Good under IEEE 1800-2009 +); endmodule diff --git a/test_regress/t/t_lint_latch_1.v b/test_regress/t/t_lint_latch_1.v index a7a802c4e..208c131a9 100644 --- a/test_regress/t/t_lint_latch_1.v +++ b/test_regress/t/t_lint_latch_1.v @@ -4,14 +4,16 @@ // SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ a, b, o); - input a; - input b; - output reg o; +module t ( /*AUTOARG*/ + a, + b, + o +); + input a; + input b; + output reg o; - // verilator lint_off LATCH - always @(a or b) - if (a) - o <= b; + // verilator lint_off LATCH + always @(a or b) if (a) o <= b; endmodule diff --git a/test_regress/t/t_lint_latch_2.v b/test_regress/t/t_lint_latch_2.v index c4e12e201..d3678a807 100644 --- a/test_regress/t/t_lint_latch_2.v +++ b/test_regress/t/t_lint_latch_2.v @@ -4,18 +4,21 @@ // SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ i, o); +module t ( /*AUTOARG*/ + i, + o +); - input [1:0] i; - output reg [1:0] o; + input [1:0] i; + output reg [1:0] o; - // This should not detect a latch as all options are covered - always @* begin - if (i==2'b00) o = 2'b11; - else if (i==2'b01) o = 2'b10; - else if (i==2'b10) o = 2'b01; - else if (i==2'b11) o = 2'b00; - else o = 2'b00; // Without this else a latch is (falsely) detected - end + // This should not detect a latch as all options are covered + always @* begin + if (i == 2'b00) o = 2'b11; + else if (i == 2'b01) o = 2'b10; + else if (i == 2'b10) o = 2'b01; + else if (i == 2'b11) o = 2'b00; + else o = 2'b00; // Without this else a latch is (falsely) detected + end endmodule diff --git a/test_regress/t/t_lint_latch_3.v b/test_regress/t/t_lint_latch_3.v index 840054b93..d15d96a97 100644 --- a/test_regress/t/t_lint_latch_3.v +++ b/test_regress/t/t_lint_latch_3.v @@ -4,48 +4,52 @@ // SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ out, out2, in ); +module t ( /*AUTOARG*/ + out, + out2, + in +); - input [9:0] in; - output reg [3:0] out; - output reg [3:0] out2; + input [9:0] in; + output reg [3:0] out; + output reg [3:0] out2; - // Should be no latch here since the input space is fully covered + // Should be no latch here since the input space is fully covered - always @* begin - casez (in) - 10'b0000000000 : out = 4'h0; - 10'b?????????1 : out = 4'h0; - 10'b????????10 : out = 4'h1; - 10'b???????100 : out = 4'h2; - 10'b??????1000 : out = 4'h3; - 10'b?????10000 : out = 4'h4; - 10'b????100000 : out = 4'h5; - 10'b???1000000 : out = 4'h6; - 10'b??10000000 : out = 4'h7; - 10'b?100000000 : out = 4'h8; - 10'b1000000000 : out = 4'h9; - endcase - end + always @* begin + casez (in) + 10'b0000000000: out = 4'h0; + 10'b?????????1: out = 4'h0; + 10'b????????10: out = 4'h1; + 10'b???????100: out = 4'h2; + 10'b??????1000: out = 4'h3; + 10'b?????10000: out = 4'h4; + 10'b????100000: out = 4'h5; + 10'b???1000000: out = 4'h6; + 10'b??10000000: out = 4'h7; + 10'b?100000000: out = 4'h8; + 10'b1000000000: out = 4'h9; + endcase + end - // Should detect a latch here since not all paths assign - // BUT we don't because warnOff(LATCH) is set for any always containing a - // complex case statement + // Should detect a latch here since not all paths assign + // BUT we don't because warnOff(LATCH) is set for any always containing a + // complex case statement - always @* begin - casez (in) - 10'b0000000000 : out2 = 4'h0; - 10'b?????????1 : out2 = 4'h0; - 10'b????????10 : out2 = 4'h1; - 10'b???????100 : out2 = 4'h2; - 10'b??????1000 : out2 = 4'h3; - 10'b?????10000 : /* No assignement */ ; - 10'b????100000 : out2 = 4'h5; - 10'b???1000000 : out2 = 4'h6; - 10'b??10000000 : out2 = 4'h7; - 10'b?100000000 : out2 = 4'h8; - 10'b1000000000 : out2 = 4'h9; - endcase - end + always @* begin + casez (in) + 10'b0000000000: out2 = 4'h0; + 10'b?????????1: out2 = 4'h0; + 10'b????????10: out2 = 4'h1; + 10'b???????100: out2 = 4'h2; + 10'b??????1000: out2 = 4'h3; + 10'b?????10000: /* No assignement */; + 10'b????100000: out2 = 4'h5; + 10'b???1000000: out2 = 4'h6; + 10'b??10000000: out2 = 4'h7; + 10'b?100000000: out2 = 4'h8; + 10'b1000000000: out2 = 4'h9; + endcase + end endmodule diff --git a/test_regress/t/t_lint_latch_4.v b/test_regress/t/t_lint_latch_4.v index 2c954d9e4..ec9fc4680 100644 --- a/test_regress/t/t_lint_latch_4.v +++ b/test_regress/t/t_lint_latch_4.v @@ -5,30 +5,29 @@ // SPDX-License-Identifier: Unlicense module test ( - input [2:0] a, - input [3:0] c, + input [2:0] a, + input [3:0] c, - output reg [7:0] o1, - output reg [7:0] o2 + output reg [7:0] o1, + output reg [7:0] o2 ); - integer i; + integer i; - always @ (*) begin - case(a) - {3'b000}: o1 = 8'd1; - {3'b001}: - for(i=0;i<4;i=i+1) o1[i*2+:2] = 2'(c[i]); - {3'b010}: o1 = 8'd3; - {3'b011}: o1 = 8'd4; - default : o1 = 0; - endcase - end + always @(*) begin + case (a) + {3'b000} : o1 = 8'd1; + {3'b001} : for (i = 0; i < 4; i = i + 1) o1[i*2+:2] = 2'(c[i]); + {3'b010} : o1 = 8'd3; + {3'b011} : o1 = 8'd4; + default: o1 = 0; + endcase + end - always_comb begin - unique if (a[0]) o2 = 1; - else if (a[1]) o2 = 2; - else o2 = 3; - end + always_comb begin + unique if (a[0]) o2 = 1; + else if (a[1]) o2 = 2; + else o2 = 3; + end endmodule diff --git a/test_regress/t/t_lint_latch_5.v b/test_regress/t/t_lint_latch_5.v index a0a6482b5..7aa588ab5 100644 --- a/test_regress/t/t_lint_latch_5.v +++ b/test_regress/t/t_lint_latch_5.v @@ -4,17 +4,14 @@ // SPDX-FileCopyrightText: 2021 Julien Margetts (Originally provided by Thomas Sailer) // SPDX-License-Identifier: Unlicense -module test - (input logic [1:0] a, - input logic e, - output logic [1:0] z); +module test ( + input logic [1:0] a, + input logic e, + output logic [1:0] z +); - always_latch - if (e) - z[0] = a[0]; + always_latch if (e) z[0] = a[0]; - always_latch - if (e) - z[1] = a[1]; + always_latch if (e) z[1] = a[1]; endmodule diff --git a/test_regress/t/t_lint_latch_6.v b/test_regress/t/t_lint_latch_6.v index 19e6bcde9..6c376f59b 100644 --- a/test_regress/t/t_lint_latch_6.v +++ b/test_regress/t/t_lint_latch_6.v @@ -4,23 +4,21 @@ // SPDX-FileCopyrightText: 2023 Julien Margetts (Originally provided by Adrien Le Masle) // SPDX-License-Identifier: Unlicense -module verilator_latch -( - input logic state, - output logic [31:0] b +module verilator_latch ( + input logic state, + output logic [31:0] b ); - function logic [31:0 ] toto (); - logic [31:0] res; - res = 10; - return res; - endfunction + function logic [31:0] toto(); + logic [31:0] res; + res = 10; + return res; + endfunction - always_comb - begin - b = 0; - if (state) - b = toto(); - end + always_comb begin + b = 0; + if (state) b = toto(); + end -endmodule; +endmodule +; diff --git a/test_regress/t/t_lint_latch_7.v b/test_regress/t/t_lint_latch_7.v index 3367ad606..4f3f8d821 100644 --- a/test_regress/t/t_lint_latch_7.v +++ b/test_regress/t/t_lint_latch_7.v @@ -4,18 +4,18 @@ // SPDX-FileCopyrightText: 2021 Julien Margetts // SPDX-License-Identifier: Unlicense -module test #(parameter W = 65) - (input logic [W-1:0] a, - input logic e, - output logic [W-1:0] z); +module test #( + parameter W = 65 +) ( + input logic [W-1:0] a, + input logic e, + output logic [W-1:0] z +); - integer i; + integer i; - always @(*) - if (e) - for (i=0;i 0); - end + // inlined - no warning + do begin + param_unused_do_while = 1; + end while (param_unused_do_while > 0); + end - const logic always_false = 0; - // loops with empty bodies - warning - initial begin - while(0); - while(always_false); - while(always_zero < 0); - do ; while(0); + const logic always_false = 0; + // loops with empty bodies - warning + initial begin + while(0); + while(always_false); + while(always_zero < 0); + do ; while(0); - // unrolled - no warning - for (int i = 0; i < 1; i++); - end + // unrolled - no warning + for (int i = 0; i < 1; i++); + end endmodule // warning for all unused loops under always module with_always(input clk); - const logic always_false = 0; - always @(posedge clk) begin - while(0); + const logic always_false = 0; + always @(posedge clk) begin + while(0); - while(always_false) begin - $write("Test"); - end - end + while(always_false) begin + $write("Test"); + end + end endmodule module const_condition; - const logic always_zero = 0; - // loops with const false condition - warning - initial begin - while(always_zero) begin - $write("This will not be printed\n"); - end + const logic always_zero = 0; + // loops with const false condition - warning + initial begin + while(always_zero) begin + $write("This will not be printed\n"); + end - for (int i = 0; always_zero; i++) - begin - $write("This will not be printed\n"); - end + for (int i = 0; always_zero; i++) + begin + $write("This will not be printed\n"); + end - for (int i = 0; i < always_zero; i++) - begin - $write("This will not be printed\n"); - end + for (int i = 0; i < always_zero; i++) + begin + $write("This will not be printed\n"); + end - // inlined - no warning - do begin - $write("This will be printed\n"); - end while (always_zero); - end + // inlined - no warning + do begin + $write("This will be printed\n"); + end while (always_zero); + end endmodule // loop with param - no warning module loop_with_param; - parameter ZERO_PARAM = 0; - int prints = 2; + parameter ZERO_PARAM = 0; + int prints = 2; - initial begin - for (int i = 0; ZERO_PARAM; i++) begin - $write("This will not be printed\n"); - end + initial begin + for (int i = 0; ZERO_PARAM; i++) begin + $write("This will not be printed\n"); + end - while (ZERO_PARAM != ZERO_PARAM) begin - $write("This will not be printed\n"); - end + while (ZERO_PARAM != ZERO_PARAM) begin + $write("This will not be printed\n"); + end - while(prints > ZERO_PARAM) begin - prints--; - end - end + while(prints > ZERO_PARAM) begin + prints--; + end + end endmodule module if_with_param; - parameter ZERO_PARAM = 0; - parameter ONE_PARAM = 1; + parameter ZERO_PARAM = 0; + parameter ONE_PARAM = 1; - initial begin - if (ZERO_PARAM) begin - // loop under false parameterized if - no warning - int prints; - while(prints < 5) begin - prints++; - end - $write("Prints %d\n", prints); - end else if (!ONE_PARAM) begin - // loop under false parameterized if - no warning - int prints; - while(prints < 5) begin - prints++; - end - $write("Prints %d\n", prints); - end else begin - // loop under true parameterized if - no warning - int prints; - while(prints < 5) begin - prints++; - end - $write("Prints %d\n", prints); + initial begin + if (ZERO_PARAM) begin + // loop under false parameterized if - no warning + int prints; + while(prints < 5) begin + prints++; end - end + $write("Prints %d\n", prints); + end else if (!ONE_PARAM) begin + // loop under false parameterized if - no warning + int prints; + while(prints < 5) begin + prints++; + end + $write("Prints %d\n", prints); + end else begin + // loop under true parameterized if - no warning + int prints; + while(prints < 5) begin + prints++; + end + $write("Prints %d\n", prints); + end + end endmodule module clock_init_race(input clk, input reset_l); - logic m_2_clock; - logic m_3_clock; - logic m_2_reset = reset_l; - logic m_3_reset = reset_l; - assign m_2_clock = clk; - assign m_3_clock = clk; - int m_3_counter; - initial begin - $write("*-* START TEST *-*\n"); - end + logic m_2_clock; + logic m_3_clock; + logic m_2_reset = reset_l; + logic m_3_reset = reset_l; + assign m_2_clock = clk; + assign m_3_clock = clk; + int m_3_counter; + initial begin + $write("*-* START TEST *-*\n"); + end - always @(posedge clk) begin - if (m_3_counter == 25) begin - $write("*-* All Finished *-*\n"); - $finish(); - end - end + always @(posedge clk) begin + if (m_3_counter == 25) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end - bit m_2_ticked; - always @(posedge m_2_clock) if (!m_2_reset) begin - m_2_ticked = 1'b1; - end - always @(negedge m_2_clock) m_2_ticked = 1'b0; + bit m_2_ticked; + always @(posedge m_2_clock) if (!m_2_reset) begin + m_2_ticked = 1'b1; + end + always @(negedge m_2_clock) m_2_ticked = 1'b0; - always @(posedge m_3_clock) if (!m_3_reset) begin - $write("*-* m_3_clocked *-*\n"); - // loop empty - unused loop warning - while (m_2_ticked); - m_3_counter += 1; - end + always @(posedge m_3_clock) if (!m_3_reset) begin + $write("*-* m_3_clocked *-*\n"); + // loop empty - unused loop warning + while (m_2_ticked); + m_3_counter += 1; + end endmodule diff --git a/test_regress/t/t_lint_vcmarker_bad.v b/test_regress/t/t_lint_vcmarker_bad.v index 217a9d6aa..b1026ae10 100644 --- a/test_regress/t/t_lint_vcmarker_bad.v +++ b/test_regress/t/t_lint_vcmarker_bad.v @@ -7,9 +7,9 @@ module t; <<<<<<< HEAD // Intentional test: This conflict marker should be here - initial $display("Hello"); + initial $display("Hello"); ======= // Intentional test: This conflict marker should be here - initial $display("Goodbye"); + initial $display("Goodbye"); >>>>>>> MERGE // Intentional test: This conflict marker should be here endmodule diff --git a/test_regress/t/t_lint_waitconst_bad.out b/test_regress/t/t_lint_waitconst_bad.out index b108720dc..7060265ec 100644 --- a/test_regress/t/t_lint_waitconst_bad.out +++ b/test_regress/t/t_lint_waitconst_bad.out @@ -1,12 +1,12 @@ -%Warning-WAITCONST: t/t_timing_wait1.v:52:12: Wait statement condition is constant - 52 | wait(1); - | ^ +%Warning-WAITCONST: t/t_timing_wait1.v:52:10: Wait statement condition is constant + 52 | wait(1); + | ^ ... For warning description see https://verilator.org/warn/WAITCONST?v=latest ... Use "/* verilator lint_off WAITCONST */" and lint_on around source to disable this message. -%Warning-WAITCONST: t/t_timing_wait1.v:54:14: Wait statement condition is constant - 54 | wait(0 < 1) $write("*-* All Finished *-*\n"); - | ^ -%Warning-WAITCONST: t/t_timing_wait1.v:59:19: Wait statement condition is constant - 59 | initial wait(1 == 0) $stop; - | ^~ +%Warning-WAITCONST: t/t_timing_wait1.v:54:12: Wait statement condition is constant + 54 | wait(0 < 1) $write("*-* All Finished *-*\n"); + | ^ +%Warning-WAITCONST: t/t_timing_wait1.v:59:18: Wait statement condition is constant + 59 | initial wait(1 == 0) $stop; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_warn_incfile2_bad.out b/test_regress/t/t_lint_warn_incfile2_bad.out index bea3e325b..dcbe96a25 100644 --- a/test_regress/t/t_lint_warn_incfile2_bad.out +++ b/test_regress/t/t_lint_warn_incfile2_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTHTRUNC: t/t_lint_warn_incfile2_bad.v:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. +%Warning-WIDTHTRUNC: t/t_lint_warn_incfile2_bad.v:13:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' - 13 | int warn_t = 64'h1; - | ^~~~~ + 13 | int warn_t = 64'h1; + | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_warn_incfile2_bad.v b/test_regress/t/t_lint_warn_incfile2_bad.v index 20c0136f5..11a542880 100644 --- a/test_regress/t/t_lint_warn_incfile2_bad.v +++ b/test_regress/t/t_lint_warn_incfile2_bad.v @@ -9,6 +9,6 @@ `include "t_lint_warn_incfile2_bad_b.vh" module t; - sub sub(); - int warn_t = 64'h1; // Not suppressed - should warn + sub sub (); + int warn_t = 64'h1; // Not suppressed - should warn endmodule diff --git a/test_regress/t/t_lint_warn_line_bad.out b/test_regress/t/t_lint_warn_line_bad.out index eec0f2982..828109df8 100644 --- a/test_regress/t/t_lint_warn_line_bad.out +++ b/test_regress/t/t_lint_warn_line_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTHTRUNC: the_line_file:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. +%Warning-WIDTHTRUNC: the_line_file:13:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' - 13 | int warn_t = 64'h1; - | ^~~~~ + 13 | int warn_t = 64'h1; + | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_warn_line_bad.v b/test_regress/t/t_lint_warn_line_bad.v index 8a0bee3be..7c90ee857 100644 --- a/test_regress/t/t_lint_warn_line_bad.v +++ b/test_regress/t/t_lint_warn_line_bad.v @@ -10,5 +10,5 @@ `line `__LINE__ "the_line_file" 2 module t; - int warn_t = 64'h1; // Not suppressed - should warn + int warn_t = 64'h1; // Not suppressed - should warn endmodule diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index 707f06911..ffea8f4ce 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -6,28 +6,28 @@ module t; - // This isn't a width violation, as +/- 1'b1 is a common idiom - // that's fairly harmless - wire [4:0] five = 5'd5; - wire [4:0] suma = five + 1'b1; - wire [4:0] sumb = 1'b1 + five; - wire [4:0] sumc = five - 1'b1; + // This isn't a width violation, as +/- 1'b1 is a common idiom + // that's fairly harmless + wire [4:0] five = 5'd5; + wire [4:0] suma = five + 1'b1; + wire [4:0] sumb = 1'b1 + five; + wire [4:0] sumc = five - 1'b1; - wire [4:0] neg5 = - five; - wire [5:0] neg6 = - five; + wire [4:0] neg5 = -five; + wire [5:0] neg6 = -five; - wire inc = 1'b1; - wire dec = 1'b1; - wire [4:0] sumd = inc + five; - wire [4:0] sume = five + inc; - wire [4:0] nege = five - dec; - wire [4:0] nsume = five + inc - dec; - wire [4:0] nsumf = five - dec + inc; + wire inc = 1'b1; + wire dec = 1'b1; + wire [4:0] sumd = inc + five; + wire [4:0] sume = five + inc; + wire [4:0] nege = five - dec; + wire [4:0] nsume = five + inc - dec; + wire [4:0] nsumf = five - dec + inc; - // Relatively harmless < or <= compared with something less wide - localparam [1:0] THREE = 3; - int a; - initial for (a = 0; a < THREE; ++a) $display(a); - initial for (a = 0; a <= THREE; ++a) $display(a); + // Relatively harmless < or <= compared with something less wide + localparam [1:0] THREE = 3; + int a; + initial for (a = 0; a < THREE; ++a) $display(a); + initial for (a = 0; a <= THREE; ++a) $display(a); endmodule diff --git a/test_regress/t/t_lint_width_arraydecl.v b/test_regress/t/t_lint_width_arraydecl.v index e11d737df..7c52a8306 100644 --- a/test_regress/t/t_lint_width_arraydecl.v +++ b/test_regress/t/t_lint_width_arraydecl.v @@ -9,37 +9,36 @@ localparam UROM_WIDTH = 5'd17; localparam UROM_DEPTH = 11'd1024; -module t( - input clk, - input [UADDR_WIDTH-1:0] mAddr, - output logic [UROM_WIDTH-1:0] mOutput); +module t ( + input clk, + input [UADDR_WIDTH-1:0] mAddr, + output logic [UROM_WIDTH-1:0] mOutput +); - // Issue #3959 - reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH]; + // Issue #3959 + reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH]; - always @(posedge clk) mOutput <= uRam[mAddr]; + always @(posedge clk) mOutput <= uRam[mAddr]; - // Issue #6045 - typedef enum logic [1:0] { e_0, e_1, e_2, e_3 } enum_e; + // Issue #6045 + typedef enum logic [1:0] { + e_0, + e_1, + e_2, + e_3 + } enum_e; - typedef struct packed { - integer unsigned x; - integer unsigned y; - } foo_s; + typedef struct packed { + integer unsigned x; + integer unsigned y; + } foo_s; - typedef struct packed { - integer unsigned y; - } bar_s; + typedef struct packed {integer unsigned y;} bar_s; - // Warning due to concatenation, but this is actually a member assignment - localparam foo_s FOO = '{ - y: (1 << e_0) | (1 << e_3) - , default: '0 - }; + // Warning due to concatenation, but this is actually a member assignment + localparam foo_s FOO = '{y: (1 << e_0) | (1 << e_3), default: '0}; - // No warning - localparam bar_s BAR = '{ - y: (1 << e_0) | (1 << e_3) - }; + // No warning + localparam bar_s BAR = '{y: (1 << e_0) | (1 << e_3)}; endmodule diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index 73155ef1b..928095988 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -1,49 +1,49 @@ -%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:17:20: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. : ... note: In instance 't' - 17 | localparam [3:0] XS = 'hx; - | ^~ + 17 | localparam [3:0] XS = 'hx; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:49:18: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. : ... note: In instance 't.p4' - 47 | wire [4:0] out = in; - | ^ + 49 | wire [4:0] out = in; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:21:24: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. : ... note: In instance 't' - 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; - | ^~ -%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. + 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; + | ^~ +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:27:27: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. : ... note: In instance 't' - 27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. + 27 | wire [WIDTH-1:0] masked = (({{(WIDTH) {1'b0}}, one_bit}) << shifter); + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:25: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' - 32 | wire [2:0] cnt = (one + one + one + one); - | ^ + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:25: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... note: In instance 't' + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... note: In instance 't' + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' - 32 | wire [2:0] cnt = (one + one + one + one); + 32 | wire [2:0] cnt = (one + one + one + one); | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:37:25: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... note: In instance 't' - 32 | wire [2:0] cnt = (one + one + one + one); - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + 37 | initial for (a = 0; a > THREE; ++a) $display(a); + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:38:25: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... note: In instance 't' - 32 | wire [2:0] cnt = (one + one + one + one); - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... note: In instance 't' - 37 | initial for (a = 0; a > THREE; ++a) $display(a); - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... note: In instance 't' - 38 | initial for (a = 0; a >= THREE; ++a) $display(a); - | ^~ -%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits. + 38 | initial for (a = 0; a >= THREE; ++a) $display(a); + | ^~ +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:40:11: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits. : ... note: In instance 't' - 40 | initial if (THREE) $stop; - | ^~ + 40 | initial if (THREE) $stop; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v index b2c4db6c6..1be22258f 100644 --- a/test_regress/t/t_lint_width_bad.v +++ b/test_regress/t/t_lint_width_bad.v @@ -6,43 +6,45 @@ module t; - // See also t_math_width + // See also t_math_width - // This shows the uglyness in width warnings across param modules - // TODO: Would be nice to also show relevant parameter settings - p #(.WIDTH(4)) p4 (.in(4'd0)); - p #(.WIDTH(5)) p5 (.in(5'd0)); + // This shows the uglyness in width warnings across param modules + // TODO: Would be nice to also show relevant parameter settings + p #(.WIDTH(4)) p4 (.in(4'd0)); + p #(.WIDTH(5)) p5 (.in(5'd0)); - //==== - localparam [3:0] XS = 'hx; // User presumably intended to use 'x + //==== + localparam [3:0] XS = 'hx; // User presumably intended to use 'x - //==== - wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax - wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is + //==== + wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax + wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is - //==== - localparam WIDTH = 6; - wire one_bit; - wire [2:0] shifter = 1; - wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + //==== + localparam WIDTH = 6; + wire one_bit; + wire [2:0] shifter = 1; + wire [WIDTH-1:0] masked = (({{(WIDTH) {1'b0}}, one_bit}) << shifter); - //==== - // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS - wire one = 1; - wire [2:0] cnt = (one + one + one + one); + //==== + // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS + wire one = 1; + wire [2:0] cnt = (one + one + one + one); - // Not harmless > or >= compared with something wider (as different results if "a" wider) - localparam [40:0] THREE = 3; - int a; - initial for (a = 0; a > THREE; ++a) $display(a); - initial for (a = 0; a >= THREE; ++a) $display(a); + // Not harmless > or >= compared with something wider (as different results if "a" wider) + localparam [40:0] THREE = 3; + int a; + initial for (a = 0; a > THREE; ++a) $display(a); + initial for (a = 0; a >= THREE; ++a) $display(a); - initial if (THREE) $stop; + initial if (THREE) $stop; endmodule -module p - #(parameter WIDTH=64) - (input [WIDTH-1:0] in); - wire [4:0] out = in; +module p #( + parameter WIDTH = 64 +) ( + input [WIDTH-1:0] in +); + wire [4:0] out = in; endmodule diff --git a/test_regress/t/t_lint_width_cast.v b/test_regress/t/t_lint_width_cast.v index 15883ea97..446372fa5 100644 --- a/test_regress/t/t_lint_width_cast.v +++ b/test_regress/t/t_lint_width_cast.v @@ -4,27 +4,29 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - wire [5:0] b1 = 6'b101101; - wire [5:0] b2 = 6'b011110; - logic [5:0] a6; - logic [9:0] a10; + wire [5:0] b1 = 6'b101101; + wire [5:0] b2 = 6'b011110; + logic [5:0] a6; + logic [9:0] a10; - initial begin - // issue #3417 - a6 = b2 - b1; - `checkh(a6, 6'h31); - a10 = 10'(b2 - b1); - `checkh(a10, 10'h3f1); // This being not 31 indicates operator expands - `checkh($bits(10'(b1)), 10); - `checkh($bits(10'(b2 - b1)), 10); - `checkh($bits(b2 - b1), 6); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // issue #3417 + a6 = b2 - b1; + `checkh(a6, 6'h31); + a10 = 10'(b2 - b1); + `checkh(a10, 10'h3f1); // This being not 31 indicates operator expands + `checkh($bits(10'(b1)), 10); + `checkh($bits(10'(b2 - b1)), 10); + `checkh($bits(b2 - b1), 6); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_lint_width_genfor.v b/test_regress/t/t_lint_width_genfor.v index 3ba744748..33bef88be 100644 --- a/test_regress/t/t_lint_width_genfor.v +++ b/test_regress/t/t_lint_width_genfor.v @@ -4,33 +4,33 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - rc, rg, ri, rp - ); +module t ( /*AUTOARG*/ + // Outputs + rc, rg, ri, rp + ); - parameter P = 15; + parameter P = 15; - output reg [3:0] rc; - output reg [3:0] rg; - output reg [3:0] ri; - output reg [3:0] rp; + output reg [3:0] rc; + output reg [3:0] rg; + output reg [3:0] ri; + output reg [3:0] rp; - for (genvar g=0; g < 15; ++g) begin - // bug1487 - // This isn't a width violation, as genvars are generally 32 bits - initial begin - rg = g; - rp = P; - rc = 1; - end - end - initial begin - for (integer i=0; i < 15; ++i) begin - /* verilator lint_off WIDTH */ - ri = i; - /* verilator lint_on WIDTH */ - end - end + for (genvar g = 0; g < 15; ++g) begin + // bug1487 + // This isn't a width violation, as genvars are generally 32 bits + initial begin + rg = g; + rp = P; + rc = 1; + end + end + initial begin + for (integer i = 0; i < 15; ++i) begin + /* verilator lint_off WIDTH */ + ri = i; + /* verilator lint_on WIDTH */ + end + end endmodule diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index f3eee67d3..0a607b55a 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -1,23 +1,23 @@ -%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. : ... note: In instance 't' - 25 | rg = g; - | ^ + 25 | rg = g; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... note: In instance 't' - 26 | rp = P; - | ^ -%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. + 26 | rp = P; + | ^ +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. : ... note: In instance 't' - 27 | rw = w; - | ^ -%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + 27 | rw = w; + | ^ +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' - 28 | rc = 64'h1; - | ^ -%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. + 28 | rc = 64'h1; + | ^ +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. : ... note: In instance 't' - 33 | ri = i; - | ^ + 33 | ri = i; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_genfor_bad.v b/test_regress/t/t_lint_width_genfor_bad.v index b0aa12ec5..96db28481 100644 --- a/test_regress/t/t_lint_width_genfor_bad.v +++ b/test_regress/t/t_lint_width_genfor_bad.v @@ -4,34 +4,34 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - rc, rg, ri, rp, rw - ); +module t ( /*AUTOARG*/ + // Outputs + rc, rg, ri, rp, rw + ); - parameter P = 17; - wire [4:0] w = 5'd1; + parameter P = 17; + wire [4:0] w = 5'd1; - output reg [3:0] rc; - output reg [3:0] rg; - output reg [3:0] ri; - output reg [3:0] rp; + output reg [3:0] rc; + output reg [3:0] rg; + output reg [3:0] ri; + output reg [3:0] rp; - output reg [3:0] rw; + output reg [3:0] rw; - for (genvar g=16; g < 17; ++g) begin - // Index 17 makes a width violation - initial begin - rg = g; // WidthMin mismatch - rp = P; // WidthMin mismatch - rw = w; // Always a mismatch - rc = 64'h1; // Always a mismatch (as sized) - end - end - initial begin - for (integer i=16; i < 17; ++i) begin - ri = i; // WidthMin mismatch - end - end + for (genvar g = 16; g < 17; ++g) begin + // Index 17 makes a width violation + initial begin + rg = g; // WidthMin mismatch + rp = P; // WidthMin mismatch + rw = w; // Always a mismatch + rc = 64'h1; // Always a mismatch (as sized) + end + end + initial begin + for (integer i = 16; i < 17; ++i) begin + ri = i; // WidthMin mismatch + end + end endmodule diff --git a/test_regress/t/t_lint_width_shift_bad.out b/test_regress/t/t_lint_width_shift_bad.out index e2ae64428..ef651556d 100644 --- a/test_regress/t/t_lint_width_shift_bad.out +++ b/test_regress/t/t_lint_width_shift_bad.out @@ -1,25 +1,25 @@ -%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:19:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTL generates 4 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:20:14: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTL generates 4 bits. : ... note: In instance 't' - 19 | assign ol3 = i4 << 1; - | ^ + 20 | assign ol3 = i4 << 1; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:23:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTR generates 4 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:24:14: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTR generates 4 bits. : ... note: In instance 't' - 23 | assign or3 = i4 >> 1; - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:25:20: Operator SHIFTR expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. + 24 | assign or3 = i4 >> 1; + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:26:19: Operator SHIFTR expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. : ... note: In instance 't' - 25 | assign or5 = i4 >> 1; - | ^~ + 26 | assign or5 = i4 >> 1; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:27:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTRS generates 4 bits. +%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:28:14: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTRS generates 4 bits. : ... note: In instance 't' - 27 | assign os3 = i4 >>> 1; - | ^ -%Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:29:20: Operator SHIFTRS expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. + 28 | assign os3 = i4 >>> 1; + | ^ +%Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:30:19: Operator SHIFTRS expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. : ... note: In instance 't' - 29 | assign os5 = i4 >>> 1; - | ^~~ + 30 | assign os5 = i4 >>> 1; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_shift_bad.v b/test_regress/t/t_lint_width_shift_bad.v index 007ac282d..c4870bc0c 100644 --- a/test_regress/t/t_lint_width_shift_bad.v +++ b/test_regress/t/t_lint_width_shift_bad.v @@ -4,28 +4,29 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - (input signed [3:0] i4, - output signed [2:0] ol3, - output signed [3:0] ol4, - output signed [4:0] ol5, - output signed [2:0] or3, - output signed [3:0] or4, - output signed [4:0] or5, - output signed [2:0] os3, - output signed [3:0] os4, - output signed [4:0] os5); +module t ( + input signed [3:0] i4, + output signed [2:0] ol3, + output signed [3:0] ol4, + output signed [4:0] ol5, + output signed [2:0] or3, + output signed [3:0] or4, + output signed [4:0] or5, + output signed [2:0] os3, + output signed [3:0] os4, + output signed [4:0] os5 +); - assign ol3 = i4 << 1; // WIDTHTRUNC - assign ol4 = i4 << 1; - assign ol5 = i4 << 1; // WIDTHEXPAND, but ok due to shift amount 1 + assign ol3 = i4 << 1; // WIDTHTRUNC + assign ol4 = i4 << 1; + assign ol5 = i4 << 1; // WIDTHEXPAND, but ok due to shift amount 1 - assign or3 = i4 >> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? - assign or4 = i4 >> 1; - assign or5 = i4 >> 1; // WIDTHEXPAND + assign or3 = i4 >> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? + assign or4 = i4 >> 1; + assign or5 = i4 >> 1; // WIDTHEXPAND - assign os3 = i4 >>> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? - assign os4 = i4 >>> 1; - assign os5 = i4 >>> 1; // WIDTHEXPAND + assign os3 = i4 >>> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? + assign os4 = i4 >>> 1; + assign os5 = i4 >>> 1; // WIDTHEXPAND endmodule diff --git a/test_regress/t/t_mailbox.v b/test_regress/t/t_mailbox.v index f6913ca89..ce69db73b 100644 --- a/test_regress/t/t_mailbox.v +++ b/test_regress/t/t_mailbox.v @@ -17,75 +17,75 @@ // endclass `ifndef MAILBOX_T - `define MAILBOX_T mailbox +`define MAILBOX_T mailbox `endif // verilator lint_off DECLFILENAME module t; - `MAILBOX_T #(int) m; - int msg; - int out; + `MAILBOX_T #(int) m; + int msg; + int out; - initial begin - m = new(4); - if (m.num() != 0) $stop; - if (m.try_get(msg) > 0) $stop; + initial begin + m = new(4); + if (m.num() != 0) $stop; + if (m.try_get(msg) > 0) $stop; - msg = 123; - m.put(msg); - msg = 0; - if (m.num() != 1) $stop; - if (m.try_peek(out) <= 0) $stop; - if (out != 123) $stop; - if (m.num() != 1) $stop; - out = 0; - if (m.try_peek(out) <= 0) $stop; - if (out != 123) $stop; - out = 0; - if (m.try_get(out) <= 0) $stop; - if (out != 123) $stop; - if (m.num() != 0) $stop; + msg = 123; + m.put(msg); + msg = 0; + if (m.num() != 1) $stop; + if (m.try_peek(out) <= 0) $stop; + if (out != 123) $stop; + if (m.num() != 1) $stop; + out = 0; + if (m.try_peek(out) <= 0) $stop; + if (out != 123) $stop; + out = 0; + if (m.try_get(out) <= 0) $stop; + if (out != 123) $stop; + if (m.num() != 0) $stop; - msg = 124; - m.put(msg); - out = 0; - m.get(out); - if (out != 124) $stop; + msg = 124; + m.put(msg); + out = 0; + m.get(out); + if (out != 124) $stop; - msg = 125; - m.put(msg); - m.put(msg); - if (m.try_put(msg) == 0) $stop; - if (m.try_put(msg) == 0) $stop; - if (m.num() != 4) $stop; - if (m.try_put(msg) != 0) $stop; - if (m.num() != 4) $stop; - m.get(out); - m.get(out); - m.get(out); - m.get(out); - if (m.num() != 0) $stop; + msg = 125; + m.put(msg); + m.put(msg); + if (m.try_put(msg) == 0) $stop; + if (m.try_put(msg) == 0) $stop; + if (m.num() != 4) $stop; + if (m.try_put(msg) != 0) $stop; + if (m.num() != 4) $stop; + m.get(out); + m.get(out); + m.get(out); + m.get(out); + if (m.num() != 0) $stop; - fork - begin - #10; // So later then get() starts below - msg = 130; - m.put(msg); - msg = 131; - m.put(msg); - end - begin - if (m.try_get(msg) != 0) $stop; - out = 0; - m.get(out); // Blocks until put - if (out != 130) $stop; - out = 0; - m.get(out); - if (out != 131) $stop; - end - join + fork + begin + #10; // So later then get() starts below + msg = 130; + m.put(msg); + msg = 131; + m.put(msg); + end + begin + if (m.try_get(msg) != 0) $stop; + out = 0; + m.get(out); // Blocks until put + if (out != 130) $stop; + out = 0; + m.get(out); + if (out != 131) $stop; + end + join - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mailbox_array.v b/test_regress/t/t_mailbox_array.v index f4d753e82..4d1618888 100644 --- a/test_regress/t/t_mailbox_array.v +++ b/test_regress/t/t_mailbox_array.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - localparam DWIDTH = 6; - typedef int my_type_t [2**DWIDTH]; - mailbox #(my_type_t) m_mbx; + localparam DWIDTH = 6; + typedef int my_type_t[2**DWIDTH]; + mailbox #(my_type_t) m_mbx; - function new(); - this.m_mbx = new(1); - endfunction + function new(); + this.m_mbx = new(1); + endfunction endclass -module tb_top(); - Cls c; - initial begin - c = new(); - $display("%p", c); - $write("*-* All Finished *-*\n"); - $finish; - end +module tb_top (); + Cls c; + initial begin + c = new(); + $display("%p", c); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mailbox_bad.out b/test_regress/t/t_mailbox_bad.out index b63fb1256..e0d32b705 100644 --- a/test_regress/t/t_mailbox_bad.out +++ b/test_regress/t/t_mailbox_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_mailbox_bad.v:12:13: Class method 'bad_method' not found in class 'mailbox__Tz1' +%Error: t/t_mailbox_bad.v:12:11: Class method 'bad_method' not found in class 'mailbox__Tz1' : ... note: In instance 't' - 12 | if (m.bad_method() != 0) $stop; - | ^~~~~~~~~~ + 12 | if (m.bad_method() != 0) $stop; + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_mailbox_bad.v b/test_regress/t/t_mailbox_bad.v index a3166be6c..58e244a9c 100644 --- a/test_regress/t/t_mailbox_bad.v +++ b/test_regress/t/t_mailbox_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - mailbox #(int) m; + mailbox #(int) m; - initial begin - m = new(4); - if (m.bad_method() != 0) $stop; + initial begin + m = new(4); + if (m.bad_method() != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mailbox_concurrent.v b/test_regress/t/t_mailbox_concurrent.v index 308c91877..1321f3187 100644 --- a/test_regress/t/t_mailbox_concurrent.v +++ b/test_regress/t/t_mailbox_concurrent.v @@ -5,45 +5,45 @@ // SPDX-License-Identifier: CC0-1.0 module t; - mailbox #(int) m; + mailbox #(int) m; - task automatic test_get; - int v; - m.get(v); - // Only one thread should be here at a time (mailbox empty) - $display("mailbox read %0t", $time); - #1; - m.put(v); - endtask + task automatic test_get; + int v; + m.get(v); + // Only one thread should be here at a time (mailbox empty) + $display("mailbox read %0t", $time); + #1; + m.put(v); + endtask - task automatic test_put; - int v; - m.put(42); - // Only one thread should be here at a time (mailbox full) - $display("mailbox write %0t", $time); - #1; - m.get(v); - endtask + task automatic test_put; + int v; + m.put(42); + // Only one thread should be here at a time (mailbox full) + $display("mailbox write %0t", $time); + #1; + m.get(v); + endtask - initial begin - m = new(1); - m.put(42); + initial begin + m = new(1); + m.put(42); - fork - test_get(); - test_get(); - test_get(); - join + fork + test_get(); + test_get(); + test_get(); + join - m = new(1); + m = new(1); - fork - test_put(); - test_put(); - test_put(); - join + fork + test_put(); + test_put(); + test_put(); + join - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mailbox_notiming.v b/test_regress/t/t_mailbox_notiming.v index a6435eeab..5cde2e427 100644 --- a/test_regress/t/t_mailbox_notiming.v +++ b/test_regress/t/t_mailbox_notiming.v @@ -17,17 +17,17 @@ // endclass `ifndef MAILBOX_T - `define MAILBOX_T mailbox +`define MAILBOX_T mailbox `endif // verilator lint_off DECLFILENAME module t; - `MAILBOX_T #(int) m; + `MAILBOX_T #(int) m; - initial begin - m = new(4); - if (m.num() != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + m = new(4); + if (m.num() != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mailbox_unbounded.v b/test_regress/t/t_mailbox_unbounded.v index a7799ad25..28ab2d8b1 100644 --- a/test_regress/t/t_mailbox_unbounded.v +++ b/test_regress/t/t_mailbox_unbounded.v @@ -6,25 +6,25 @@ // verilator lint_off DECLFILENAME module t; - mailbox #(int) m; - int msg = 0; - int out = 0; + mailbox #(int) m; + int msg = 0; + int out = 0; - initial begin - m = new; - fork - begin - #10; // So later then get() starts below - msg = 1; - if (m.try_put(msg) != 1) $stop; - end - begin - m.get(out); - if (out != 1) $stop; - end - join + initial begin + m = new; + fork + begin + #10; // So later then get() starts below + msg = 1; + if (m.try_put(msg) != 1) $stop; + end + begin + m.get(out); + if (out != 1) $stop; + end + join - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v index ccb474d43..207ef98de 100644 --- a/test_regress/t/t_math_arith.v +++ b/test_regress/t/t_math_arith.v @@ -4,202 +4,209 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg _ranit; +module t ( + input clk +); - reg [2:0] xor3; - reg [1:0] xor2; - reg [0:0] xor1; - reg [2:0] ma, mb; - reg [9:0] mc; - reg [4:0] mr1; - reg [30:0] mr2; + reg _ranit; - reg [67:0] sh1; - reg [67:0] shq; + reg [2:0] xor3; + reg [1:0] xor2; + reg [0:0] xor1; + reg [2:0] ma, mb; + reg [9:0] mc; + reg [4:0] mr1; + reg [30:0] mr2; - wire foo, bar; assign {foo,bar} = 2'b1_0; + reg [67:0] sh1; + reg [67:0] shq; - // surefire lint_off STMINI - initial _ranit = 0; + wire foo, bar; + assign {foo, bar} = 2'b1_0; - wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1 + // surefire lint_off STMINI + initial _ranit = 0; + + wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1 : (xor2 == 2'b00) ? 5'h2 : (xor2 == 2'b01) ? 5'h3 : 5'h4); - wire ctrue = 1'b1 ? cond_check[1] : cond_check[0]; - wire cfalse = 1'b0 ? cond_check[1] : cond_check[0]; - wire cif = cond_check[2] ? cond_check[1] : cond_check[0]; - wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0]; + wire ctrue = 1'b1 ? cond_check[1] : cond_check[0]; + wire cfalse = 1'b0 ? cond_check[1] : cond_check[0]; + wire cif = cond_check[2] ? cond_check[1] : cond_check[0]; + wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0]; - wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1}; + wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1}; - wire zero = 1'b0; - wire one = 1'b1; - wire [5:0] rep6 = {6{one}}; + wire zero = 1'b0; + wire one = 1'b1; + wire [5:0] rep6 = {6{one}}; - // verilator lint_off WIDTH - localparam [3:0] bug764_p11 = 1'bx; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + localparam [3:0] bug764_p11 = 1'bx; + // verilator lint_on WIDTH - always @ (posedge clk) begin - if (!_ranit) begin - _ranit <= 1; + always @(posedge clk) begin + if (!_ranit) begin + _ranit <= 1; - if (rep6 != 6'b111111) $stop; - if (!one) $stop; - if (~one) $stop; + if (rep6 != 6'b111111) $stop; + if (!one) $stop; + if (~one) $stop; - if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop; - // verilator lint_off WIDTH - if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ? - // verilator lint_on WIDTH + if ((1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop; + // verilator lint_off WIDTH + if ((8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ? + // verilator lint_on WIDTH - // surefire lint_off SEQASS - xor1 = 1'b1; - xor2 = 2'b11; - xor3 = 3'b111; - // verilator lint_off WIDTH - if (1'b1 & | (!xor3)) $stop; - // verilator lint_on WIDTH - if ({1{xor1}} != 1'b1) $stop; - if ({4{xor1}} != 4'b1111) $stop; - if (!(~xor1) !== ~(!xor1)) $stop; - if ((^xor1) !== 1'b1) $stop; - if ((^xor2) !== 1'b0) $stop; - if ((^xor3) !== 1'b1) $stop; - if (~(^xor2) !== 1'b1) $stop; - if (~(^xor3) !== 1'b0) $stop; - if ((^~xor1) !== 1'b0) $stop; - if ((^~xor2) !== 1'b1) $stop; - if ((^~xor3) !== 1'b0) $stop; - if ((~^xor1) !== 1'b0) $stop; - if ((~^xor2) !== 1'b1) $stop; - if ((~^xor3) !== 1'b0) $stop; - xor1 = 1'b0; - xor2 = 2'b10; - xor3 = 3'b101; - if ((^xor1) !== 1'b0) $stop; - if ((^xor2) !== 1'b1) $stop; - if ((^xor3) !== 1'b0) $stop; - if (~(^xor2) !== 1'b0) $stop; - if (~(^xor3) !== 1'b1) $stop; - if ((^~xor1) !== 1'b1) $stop; - if ((^~xor2) !== 1'b0) $stop; - if ((^~xor3) !== 1'b1) $stop; - if ((~^xor1) !== 1'b1) $stop; - if ((~^xor2) !== 1'b0) $stop; - if ((~^xor3) !== 1'b1) $stop; + // surefire lint_off SEQASS + xor1 = 1'b1; + xor2 = 2'b11; + xor3 = 3'b111; + // verilator lint_off WIDTH + if (1'b1 & |(!xor3)) $stop; + // verilator lint_on WIDTH + if ({1{xor1}} != 1'b1) $stop; + if ({4{xor1}} != 4'b1111) $stop; + if (!(~xor1) !== ~(!xor1)) $stop; + if ((^xor1) !== 1'b1) $stop; + if ((^xor2) !== 1'b0) $stop; + if ((^xor3) !== 1'b1) $stop; + if (~(^xor2) !== 1'b1) $stop; + if (~(^xor3) !== 1'b0) $stop; + if ((^~xor1) !== 1'b0) $stop; + if ((^~xor2) !== 1'b1) $stop; + if ((^~xor3) !== 1'b0) $stop; + if ((~^xor1) !== 1'b0) $stop; + if ((~^xor2) !== 1'b1) $stop; + if ((~^xor3) !== 1'b0) $stop; + xor1 = 1'b0; + xor2 = 2'b10; + xor3 = 3'b101; + if ((^xor1) !== 1'b0) $stop; + if ((^xor2) !== 1'b1) $stop; + if ((^xor3) !== 1'b0) $stop; + if (~(^xor2) !== 1'b0) $stop; + if (~(^xor3) !== 1'b1) $stop; + if ((^~xor1) !== 1'b1) $stop; + if ((^~xor2) !== 1'b0) $stop; + if ((^~xor3) !== 1'b1) $stop; + if ((~^xor1) !== 1'b1) $stop; + if ((~^xor2) !== 1'b0) $stop; + if ((~^xor3) !== 1'b1) $stop; - // X propagation - if (!1'bx !== 1'bx) $stop; - if (~2'bx !== 2'bx) $stop; - if (-2'bx !== 2'bx) $stop; - if ((2'bxx + 2'b1) !== 2'bxx) $stop; - if ((2'bxx - 2'b1) !== 2'bxx) $stop; - if ((2'bxx * 2'b1) !== 2'bxx) $stop; - if ((2'bxx / 2'b1) !== 2'bxx) $stop; - if ((2'bxx % 2'b1) !== 2'bxx) $stop; - if ((2'sbxx * 2'sb1) !== 2'bxx) $stop; - if ((2'sbxx / 2'sb1) !== 2'bxx) $stop; - if ((2'sbxx % 2'sb1) !== 2'bxx) $stop; - if ((1'bx & 1'b1) !== 1'bx) $stop; - if ((1'bx & 1'b0) !== 1'b0) $stop; - if ((1'bx | 1'b0) !== 1'bx) $stop; - if ((1'bx | 1'b1) !== 1'b1) $stop; - if ((1'bx && 1'b1) !== 1'bx) $stop; - if ((1'bx && 1'b0) !== 1'b0) $stop; - if ((1'bx || 1'b0) !== 1'bx) $stop; - if ((1'bx || 1'b1) !== 1'b1) $stop; - if ((2'bxx ^ 2'b1) !== 2'bxx) $stop; - if ((2'bxx > 2'b1) !== 1'bx) $stop; - if ((2'bxx < 2'b1) !== 1'bx) $stop; - if ((2'bxx == 2'b1) !== 1'bx) $stop; - if ((2'bxx <= 2'b1) !== 1'bx) $stop; - if ((2'bxx >= 2'b1) !== 1'bx) $stop; - if ((2'sbxx <= 2'sb1) !== 1'bx) $stop; - if ((2'sbxx >= 2'sb1) !== 1'bx) $stop; + // X propagation + if (!1'bx !== 1'bx) $stop; + if (~2'bx !== 2'bx) $stop; + if (-2'bx !== 2'bx) $stop; + if ((2'bxx + 2'b1) !== 2'bxx) $stop; + if ((2'bxx - 2'b1) !== 2'bxx) $stop; + if ((2'bxx * 2'b1) !== 2'bxx) $stop; + if ((2'bxx / 2'b1) !== 2'bxx) $stop; + if ((2'bxx % 2'b1) !== 2'bxx) $stop; + if ((2'sbxx * 2'sb1) !== 2'bxx) $stop; + if ((2'sbxx / 2'sb1) !== 2'bxx) $stop; + if ((2'sbxx % 2'sb1) !== 2'bxx) $stop; + if ((1'bx & 1'b1) !== 1'bx) $stop; + if ((1'bx & 1'b0) !== 1'b0) $stop; + if ((1'bx | 1'b0) !== 1'bx) $stop; + if ((1'bx | 1'b1) !== 1'b1) $stop; + if ((1'bx && 1'b1) !== 1'bx) $stop; + if ((1'bx && 1'b0) !== 1'b0) $stop; + if ((1'bx || 1'b0) !== 1'bx) $stop; + if ((1'bx || 1'b1) !== 1'b1) $stop; + if ((2'bxx ^ 2'b1) !== 2'bxx) $stop; + if ((2'bxx > 2'b1) !== 1'bx) $stop; + if ((2'bxx < 2'b1) !== 1'bx) $stop; + if ((2'bxx == 2'b1) !== 1'bx) $stop; + if ((2'bxx <= 2'b1) !== 1'bx) $stop; + if ((2'bxx >= 2'b1) !== 1'bx) $stop; + if ((2'sbxx <= 2'sb1) !== 1'bx) $stop; + if ((2'sbxx >= 2'sb1) !== 1'bx) $stop; - ma = 3'h3; - mb = 3'h4; - mc = 10'h5; + ma = 3'h3; + mb = 3'h4; + mc = 10'h5; - mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch - mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch - if (mr1 !== 5'd12) $stop; - if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch + mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch + mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch + if (mr1 !== 5'd12) $stop; + if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch - sh1 = 68'hf_def1_9abc_5678_1234; - shq = sh1 >> 16; - if (shq !== 68'hf_def1_9abc_5678) $stop; - shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch - if (shq !== 68'h1_9abc_5678_1234_0000) $stop; + sh1 = 68'hf_def1_9abc_5678_1234; + shq = sh1 >> 16; + if (shq !== 68'hf_def1_9abc_5678) $stop; + shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch + if (shq !== 68'h1_9abc_5678_1234_0000) $stop; - // surefire lint_on SEQASS + // surefire lint_on SEQASS - // Test display extraction widthing - $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]); + // Test display extraction widthing + $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0] << 2, xor3[2:0], xor3[2:0]); - // bug736 - //verilator lint_off WIDTH - if ((~| 4'b0000) != 4'b0001) $stop; - if ((~| 4'b0010) != 4'b0000) $stop; - if ((~& 4'b1111) != 4'b0000) $stop; - if ((~& 4'b1101) != 4'b0001) $stop; - //verilator lint_on WIDTH + // bug736 + //verilator lint_off WIDTH + if ((~|4'b0000) != 4'b0001) $stop; + if ((~|4'b0010) != 4'b0000) $stop; + if ((~&4'b1111) != 4'b0000) $stop; + if ((~&4'b1101) != 4'b0001) $stop; + //verilator lint_on WIDTH - // bug764 - //verilator lint_off WIDTH - // X does not sign extend - if (bug764_p11 !== 4'b000x) $stop; - if (~& bug764_p11 !== 1'b1) $stop; - //verilator lint_on WIDTH - // However IEEE 1800-2023 5.7.1 says for constants that smaller-sizes do extend - if (4'bx !== 4'bxxxx) $stop; - if (4'bz !== 4'bzzzz) $stop; - if (4'b1 !== 4'b0001) $stop; + // bug764 + //verilator lint_off WIDTH + // X does not sign extend + if (bug764_p11 !== 4'b000x) $stop; + if (~&bug764_p11 !== 1'b1) $stop; + //verilator lint_on WIDTH + // However IEEE 1800-2023 5.7.1 says for constants that smaller-sizes do extend + if (4'bx !== 4'bxxxx) $stop; + if (4'bz !== 4'bzzzz) $stop; + if (4'b1 !== 4'b0001) $stop; - if ((0 -> 0) != 1'b1) $stop; - if ((0 -> 1) != 1'b1) $stop; - if ((1 -> 0) != 1'b0) $stop; - if ((1 -> 1) != 1'b1) $stop; + if ((0 -> 0) != 1'b1) $stop; + if ((0 -> 1) != 1'b1) $stop; + if ((1 -> 0) != 1'b0) $stop; + if ((1 -> 1) != 1'b1) $stop; - if ((0 <-> 0) != 1'b1) $stop; - if ((0 <-> 1) != 1'b0) $stop; - if ((1 <-> 0) != 1'b0) $stop; - if ((1 <-> 1) != 1'b1) $stop; + if ((0 <-> 0) != 1'b1) $stop; + if ((0 <-> 1) != 1'b0) $stop; + if ((1 <-> 0) != 1'b0) $stop; + if ((1 <-> 1) != 1'b1) $stop; - // bug2912 - // verilator lint_off WIDTH - if (2'(~1'b1) != 2'b10) $stop; - // verilator lint_on WIDTH + // bug2912 + // verilator lint_off WIDTH + if (2'(~1'b1) != 2'b10) $stop; + // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end - reg [63:0] m_data_pipe2_r; - reg [31:0] m_corr_data_w0, m_corr_data_w1; - reg [7:0] m_corr_data_b8; - initial begin - m_data_pipe2_r = 64'h1234_5678_9abc_def0; - {m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0] - m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0] - m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16] - m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8] - m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4] - m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0] - }; - if (m_corr_data_w0 != 32'haf36de00) $stop; - if (m_corr_data_w1 != 32'h1a2b3c4c) $stop; - if (m_corr_data_b8 != 8'h12) $stop; - end + reg [63:0] m_data_pipe2_r; + reg [31:0] m_corr_data_w0, m_corr_data_w1; + reg [7:0] m_corr_data_b8; + initial begin + m_data_pipe2_r = 64'h1234_5678_9abc_def0; + {m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { + m_data_pipe2_r[63:57], + 1'b0, //m_corr_data_b8 [7:0] + m_data_pipe2_r[56:26], + 1'b0, //m_corr_data_w1 [31:0] + m_data_pipe2_r[25:11], + 1'b0, //m_corr_data_w0 [31:16] + m_data_pipe2_r[10:04], + 1'b0, //m_corr_data_w0 [15:8] + m_data_pipe2_r[03:01], + 1'b0, //m_corr_data_w0 [7:4] + m_data_pipe2_r[0], + 3'b000 //m_corr_data_w0 [3:0] + }; + if (m_corr_data_w0 != 32'haf36de00) $stop; + if (m_corr_data_w1 != 32'h1a2b3c4c) $stop; + if (m_corr_data_b8 != 8'h12) $stop; + end endmodule diff --git a/test_regress/t/t_math_clog2.v b/test_regress/t/t_math_clog2.v index a2400a719..c37329f5f 100644 --- a/test_regress/t/t_math_clog2.v +++ b/test_regress/t/t_math_clog2.v @@ -5,96 +5,93 @@ // SPDX-License-Identifier: CC0-1.0 `ifdef verilator - `define CLOG2 $clog2 +`define CLOG2 $clog2 `else - `define CLOG2 clog2_emulate +`define CLOG2 clog2_emulate `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Need temp wires as function has different width rules than $clog2 - wire [127:0] pows = 128'h1<> 1); - end - endfunction + function integer clog2_emulate(input [130:0] arg); + begin + if (arg != 0) arg = arg - 1; + for (clog2_emulate = 0; arg != 0; clog2_emulate = clog2_emulate + 1) arg = (arg >> 1); + end + endfunction endmodule diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v index 19353d964..1dd0b4066 100644 --- a/test_regress/t/t_math_cmp.v +++ b/test_regress/t/t_math_cmp.v @@ -4,166 +4,174 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [2:0] index_a; - reg [2:0] index_b; + reg [2:0] index_a; + reg [2:0] index_b; - prover #(4) p4 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(32) p32 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(63) p63 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(64) p64 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(72) p72 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(126) p126 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); - prover #(128) p128 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + prover #(4) p4 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(32) p32 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(63) p63 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(64) p64 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(72) p72 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(126) p126 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); + prover #(128) p128 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .index_a(index_a), + .index_b(index_b) + ); - integer cyc; initial cyc = 0; - initial index_a = 3'b0; - initial index_b = 3'b0; - always @* begin - index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4; - index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; - end + integer cyc; + initial cyc = 0; + initial index_a = 3'b0; + initial index_b = 3'b0; + always @* begin + index_a = cyc[2:0]; + if (index_a > 3'd4) index_a = 3'd4; + index_b = cyc[5:3]; + if (index_b > 3'd4) index_b = 3'd4; + end - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module prover ( - input clk, - input [2:0] index_a, - input [2:0] index_b - ); + input clk, + input [2:0] index_a, + input [2:0] index_b +); - parameter WIDTH = 4; + parameter WIDTH = 4; - reg signed [WIDTH-1:0] as; - reg signed [WIDTH-1:0] bs; - wire [WIDTH-1:0] b = bs; + reg signed [WIDTH-1:0] as; + reg signed [WIDTH-1:0] bs; + wire [WIDTH-1:0] b = bs; - // verilator lint_off LATCH - always @* begin - casez (index_a) - 3'd0: as = {(WIDTH){1'd0}}; // 0 - 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: as = {(WIDTH){1'd1}}; // -1 - 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; - endcase - casez (index_b) - 3'd0: bs = {(WIDTH){1'd0}}; // 0 - 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: bs = {(WIDTH){1'd1}}; // -1 - 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; - endcase - end - // verilator lint_on LATCH + // verilator lint_off LATCH + always @* begin + casez (index_a) + 3'd0: as = {(WIDTH) {1'd0}}; // 0 + 3'd1: as = {{(WIDTH - 1) {1'd0}}, 1'b1}; // 1 + 3'd2: as = {1'b0, {(WIDTH - 1) {1'd0}}}; // 127 or equiv + 3'd3: as = {(WIDTH) {1'd1}}; // -1 + 3'd4: as = {1'b1, {(WIDTH - 1) {1'd0}}}; // -128 or equiv + default: $stop; + endcase + casez (index_b) + 3'd0: bs = {(WIDTH) {1'd0}}; // 0 + 3'd1: bs = {{(WIDTH - 1) {1'd0}}, 1'b1}; // 1 + 3'd2: bs = {1'b0, {(WIDTH - 1) {1'd0}}}; // 127 or equiv + 3'd3: bs = {(WIDTH) {1'd1}}; // -1 + 3'd4: bs = {1'b1, {(WIDTH - 1) {1'd0}}}; // -128 or equiv + default: $stop; + endcase + end + // verilator lint_on LATCH - reg [7:0] results[4:0][4:0]; + reg [7:0] results[4:0][4:0]; - wire gt = as>b; - wire gts = as>bs; - wire gte = as>=b; - wire gtes = as>=bs; - wire lt = as b; + wire gts = as > bs; + wire gte = as >= b; + wire gtes = as >= bs; + wire lt = as < b; + wire lts = as < bs; + wire lte = as <= b; + wire ltes = as <= bs; - reg [7:0] exp; - reg [7:0] got; + reg [7:0] exp; + reg [7:0] got; - integer cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc>2) begin + integer cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc > 2) begin `ifdef TEST_VERBOSE - $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", - index_a, index_b, - gt, gts, gte, gtes, lt, lts, lte, ltes); + $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", index_a, index_b, gt, gts, gte, + gtes, lt, lts, lte, ltes); `endif - exp = results[index_a][index_b]; - got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; - if (exp !== got) begin - $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); - $stop; - end + exp = results[index_a][index_b]; + got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; + if (exp !== got) begin + $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a, index_b, + got, exp); + $stop; end - end + end + end - // Result table - initial begin - // Indexes: 0, 1, -1, 127, -128 - // Gt Gts Gte Gtes Lt Lts Lte Ltes - results[0][0] = 8'b0_0_1_1_0_0_1_1; - results[0][1] = 8'b0_0_0_0_1_1_1_1; - results[0][2] = 8'b0_0_1_1_0_0_1_1; - results[0][3] = 8'b0_1_0_1_1_0_1_0; - results[0][4] = 8'b0_1_0_1_1_0_1_0; - results[1][0] = 8'b1_1_1_1_0_0_0_0; - results[1][1] = 8'b0_0_1_1_0_0_1_1; - results[1][2] = 8'b1_1_1_1_0_0_0_0; - results[1][3] = 8'b0_1_0_1_1_0_1_0; - results[1][4] = 8'b0_1_0_1_1_0_1_0; - results[2][0] = 8'b0_0_1_1_0_0_1_1; - results[2][1] = 8'b0_0_0_0_1_1_1_1; - results[2][2] = 8'b0_0_1_1_0_0_1_1; - results[2][3] = 8'b0_1_0_1_1_0_1_0; - results[2][4] = 8'b0_1_0_1_1_0_1_0; - results[3][0] = 8'b1_0_1_0_0_1_0_1; - results[3][1] = 8'b1_0_1_0_0_1_0_1; - results[3][2] = 8'b1_0_1_0_0_1_0_1; - results[3][3] = 8'b0_0_1_1_0_0_1_1; - results[3][4] = 8'b1_1_1_1_0_0_0_0; - results[4][0] = 8'b1_0_1_0_0_1_0_1; - results[4][1] = 8'b1_0_1_0_0_1_0_1; - results[4][2] = 8'b1_0_1_0_0_1_0_1; - results[4][3] = 8'b0_0_0_0_1_1_1_1; - results[4][4] = 8'b0_0_1_1_0_0_1_1; - end + // Result table + initial begin + // Indexes: 0, 1, -1, 127, -128 + // Gt Gts Gte Gtes Lt Lts Lte Ltes + results[0][0] = 8'b0_0_1_1_0_0_1_1; + results[0][1] = 8'b0_0_0_0_1_1_1_1; + results[0][2] = 8'b0_0_1_1_0_0_1_1; + results[0][3] = 8'b0_1_0_1_1_0_1_0; + results[0][4] = 8'b0_1_0_1_1_0_1_0; + results[1][0] = 8'b1_1_1_1_0_0_0_0; + results[1][1] = 8'b0_0_1_1_0_0_1_1; + results[1][2] = 8'b1_1_1_1_0_0_0_0; + results[1][3] = 8'b0_1_0_1_1_0_1_0; + results[1][4] = 8'b0_1_0_1_1_0_1_0; + results[2][0] = 8'b0_0_1_1_0_0_1_1; + results[2][1] = 8'b0_0_0_0_1_1_1_1; + results[2][2] = 8'b0_0_1_1_0_0_1_1; + results[2][3] = 8'b0_1_0_1_1_0_1_0; + results[2][4] = 8'b0_1_0_1_1_0_1_0; + results[3][0] = 8'b1_0_1_0_0_1_0_1; + results[3][1] = 8'b1_0_1_0_0_1_0_1; + results[3][2] = 8'b1_0_1_0_0_1_0_1; + results[3][3] = 8'b0_0_1_1_0_0_1_1; + results[3][4] = 8'b1_1_1_1_0_0_0_0; + results[4][0] = 8'b1_0_1_0_0_1_0_1; + results[4][1] = 8'b1_0_1_0_0_1_0_1; + results[4][2] = 8'b1_0_1_0_0_1_0_1; + results[4][3] = 8'b0_0_0_0_1_1_1_1; + results[4][4] = 8'b0_0_1_1_0_0_1_1; + end endmodule diff --git a/test_regress/t/t_math_concat.v b/test_regress/t/t_math_concat.v index efa13e6f8..2b3e16ca5 100644 --- a/test_regress/t/t_math_concat.v +++ b/test_regress/t/t_math_concat.v @@ -4,72 +4,73 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [255:0] i; - wire [255:0] q; + reg [255:0] i; + wire [255:0] q; - assign q = { - i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], - i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], - i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], - i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], - i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], - i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], - i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], - i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], - i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], - i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], - i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], - i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], - i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], - i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], - i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], - i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], - i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], - i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], - i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], - i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], - i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], - i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], - i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], - i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], - i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], - i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], - i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], - i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], - i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], - i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], - i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], - i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] - }; + // verilog_format: off + assign q = { + i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], + i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], + i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], + i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], + i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], + i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], + i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], + i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], + i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], + i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], + i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], + i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], + i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], + i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], + i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], + i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], + i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], + i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], + i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], + i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], + i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], + i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], + i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], + i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], + i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], + i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], + i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], + i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], + i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], + i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], + i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], + i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] + }; + // verilog_format: on - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x %x\n", q, i); + $write("%x %x\n", q, i); `endif - if (cyc==1) begin - i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - end - if (cyc==2) begin - i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; - end - if (cyc==3) begin - if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 1) begin + i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end - end + if (cyc == 2) begin + i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; + end + if (cyc == 3) begin + if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; + end + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v index 5234f74f6..45821f655 100644 --- a/test_regress/t/t_math_concat0.v +++ b/test_regress/t/t_math_concat0.v @@ -3,86 +3,88 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [15:0] in = crc[15:0]; + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [15:0] outa; // From test of Test.v - wire [15:0] outb; // From test of Test.v - wire [15:0] outc; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] outa; // From test of Test.v + wire [15:0] outb; // From test of Test.v + wire [15:0] outc; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .outa (outa[15:0]), - .outb (outb[15:0]), - .outc (outc[15:0]), - // Inputs - .clk (clk), - .in (in[15:0])); + Test test ( /*AUTOINST*/ + // Outputs + .outa(outa[15:0]), + .outb(outb[15:0]), + .outc(outc[15:0]), + // Inputs + .clk(clk), + .in(in[15:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {16'h0, outa, outb, outc}; + // Aggregate outputs into a single result vector + wire [63:0] result = {16'h0, outa, outb, outc}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h09be74b1b0f8c35d - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h09be74b1b0f8c35d + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - outa, outb, outc, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + outa, + outb, + outc, + // Inputs + clk, + in +); - input clk; - input [15:0] in; - output reg [15:0] outa; - output reg [15:0] outb; - output reg [15:0] outc; + input clk; + input [15:0] in; + output reg [15:0] outa; + output reg [15:0] outb; + output reg [15:0] outc; - parameter WIDTH = 0; - always @(posedge clk) begin - outa <= {in}; - outb <= {{WIDTH{1'b0}}, in}; - outc <= {in, {WIDTH{1'b0}}}; - end + parameter WIDTH = 0; + always @(posedge clk) begin + outa <= {in}; + outb <= {{WIDTH{1'b0}}, in}; + outc <= {in, {WIDTH{1'b0}}}; + end endmodule diff --git a/test_regress/t/t_math_cond_clean.v b/test_regress/t/t_math_cond_clean.v index c195ee89b..0de414810 100644 --- a/test_regress/t/t_math_cond_clean.v +++ b/test_regress/t/t_math_cond_clean.v @@ -4,92 +4,92 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] cnt = crc[3:0]; - wire [6:0] decr = crc[14:8]; + // Take CRC data and apply to testblock inputs + wire [3:0] cnt = crc[3:0]; + wire [6:0] decr = crc[14:8]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] next; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] next; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .next (next[3:0]), - // Inputs - .cnt (cnt[3:0]), - .decr (decr[6:0])); + Test test ( /*AUTOINST*/ + // Outputs + .next(next[3:0]), + // Inputs + .cnt(cnt[3:0]), + .decr(decr[6:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, next}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, next}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h7cd85c944415d2ef - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h7cd85c944415d2ef + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - next, - // Inputs - cnt, decr - ); +module Test ( /*AUTOARG*/ + // Outputs + next, + // Inputs + cnt, + decr +); - input [3:0] cnt; - input signed [6:0] decr; - output reg [3:0] next; + input [3:0] cnt; + input signed [6:0] decr; + output reg [3:0] next; - always_comb begin - reg signed [6:0] tmp; - tmp = 0; - // verilator lint_off WIDTH - tmp = ($signed({1'b0, cnt}) - decr); - // verilator lint_on WIDTH - if ((tmp > 15)) begin - next = 15; - end - else if ((tmp < 0)) begin - next = 0; - end - else begin - next = tmp[3:0]; - end - end + always_comb begin + reg signed [6:0] tmp; + tmp = 0; + // verilator lint_off WIDTH + tmp = ($signed({1'b0, cnt}) - decr); + // verilator lint_on WIDTH + if ((tmp > 15)) begin + next = 15; + end + else if ((tmp < 0)) begin + next = 0; + end + else begin + next = tmp[3:0]; + end + end endmodule diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v index 7c35a891c..77080e829 100644 --- a/test_regress/t/t_math_const.v +++ b/test_regress/t/t_math_const.v @@ -4,141 +4,140 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; + reg [39:0] con1,con2, con3; + reg [31:0] w32; + reg [31:0] v32 [2]; - reg [39:0] con1,con2, con3; - reg [31:0] w32; - reg [31:0] v32 [2]; + // surefire lint_off UDDSCN + reg [200:0] conw3, conw4; + // surefire lint_on UDDSCN - // surefire lint_off UDDSCN - reg [200:0] conw3, conw4; - // surefire lint_on UDDSCN + reg [16*8-1:0] con__ascii; - reg [16*8-1:0] con__ascii; + reg [31:0] win; + // Test casting is proper on narrow->wide->narrow conversions + // verilator lint_off WIDTH + wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; + wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; + // verilator lint_on WIDTH + wire [31:0] narrow = wider[31:0]; + wire [31:0] narrow2 = wider2[31:0]; - reg [31:0] win; - // Test casting is proper on narrow->wide->narrow conversions - // verilator lint_off WIDTH - wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; - wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; - // verilator lint_on WIDTH - wire [31:0] narrow = wider[31:0]; - wire [31:0] narrow2 = wider2[31:0]; + // surefire lint_off ASWEMB + // surefire lint_off ASWCMB + // surefire lint_off CWECBB + // surefire lint_off CWECSB + // surefire lint_off STMINI - // surefire lint_off ASWEMB - // surefire lint_off ASWCMB - // surefire lint_off CWECBB - // surefire lint_off CWECSB + // verilog_format: off - // surefire lint_off STMINI - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - $write("[%0t] t_const: Running\n", $time); + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("[%0t] t_const: Running\n", $time); - con1 = 4_0'h1000_0010; // Odd but legal _ in width - con2 = 40'h10_0000_0010; - con3 = con1 + 40'h10_1100_0101; - if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; - $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); - if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; - if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; + con1 = 4_0'h1000_0010; // Odd but legal _ in width + con2 = 40'h10_0000_0010; + con3 = con1 + 40'h10_1100_0101; + if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; + $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); + if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; + if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; - // verilator lint_off WIDTH - con1 = 10'h10 + 40'h80_1100_0131; - // verilator lint_on WIDTH - con2 = 40'h80_0000_0000 + 40'h13_7543_0107; - if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; - if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; + // verilator lint_off WIDTH + con1 = 10'h10 + 40'h80_1100_0131; + // verilator lint_on WIDTH + con2 = 40'h80_0000_0000 + 40'h13_7543_0107; + if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; + if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; - // verilator lint_off WIDTH - conw3 = 94'h000a_5010_4020_3030_2040_1050; - // verilator lint_on WIDTH - if (conw3[31:00]!== 32'h2040_1050 || - conw3[63:32]!== 32'h4020_3030 || - conw3[95:64]!== 32'h000a_5010 || - conw3[128:96]!==33'h0) $stop; - $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); - if ((~| conw3[15:0]) !== 1'h0) $stop; - if ((~& conw3[15:0]) !== 1'h1) $stop; + // verilator lint_off WIDTH + conw3 = 94'h000a_5010_4020_3030_2040_1050; + // verilator lint_on WIDTH + if (conw3[31:00]!== 32'h2040_1050 || + conw3[63:32]!== 32'h4020_3030 || + conw3[95:64]!== 32'h000a_5010 || + conw3[128:96]!==33'h0) $stop; + $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); + if ((~| conw3[15:0]) !== 1'h0) $stop; + if ((~& conw3[15:0]) !== 1'h1) $stop; - // verilator lint_off WIDTH - conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; - // verilator lint_on WIDTH - if (conw4[31:00]!== 32'h2060_1070 || - conw4[63:32]!== 32'h4040_3050 || - conw4[95:64]!== 32'h602a_5030 || - conw4[127:96]!==32'h7010) $stop; - // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; + // verilator lint_off WIDTH + conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; + // verilator lint_on WIDTH + if (conw4[31:00]!== 32'h2060_1070 || + conw4[63:32]!== 32'h4040_3050 || + conw4[95:64]!== 32'h602a_5030 || + conw4[127:96]!==32'h7010) $stop; + // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; - w32 = 12; - win <= 12; - if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; + w32 = 12; + win <= 12; + if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; - con__ascii = "abcdefghijklmnop"; - if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; - con__ascii = "abcdefghijklm"; - if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; + con__ascii = "abcdefghijklmnop"; + if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; + con__ascii = "abcdefghijklm"; + if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; - if ( 3'dx !== 3'hx) $stop; + if ( 3'dx !== 3'hx) $stop; - // Wide decimal - if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; - if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; + // Wide decimal + if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; + if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; - // Increments - w32 = 12; w32++; if (w32 != 13) $stop; - w32 = 12; ++w32; if (w32 != 13) $stop; - w32 = 12; w32--; if (w32 != 11) $stop; - w32 = 12; --w32; if (w32 != 11) $stop; - w32 = 12; w32 += 2; if (w32 != 14) $stop; - w32 = 12; w32 -= 2; if (w32 != 10) $stop; - w32 = 12; w32 *= 2; if (w32 != 24) $stop; - w32 = 12; w32 /= 2; if (w32 != 6) $stop; - w32 = 12; w32 &= 6; if (w32 != 4) $stop; - w32 = 12; w32 |= 15; if (w32 != 15) $stop; - w32 = 12; w32 ^= 15; if (w32 != 3) $stop; - w32 = 12; w32 >>= 1; if (w32 != 6) $stop; - w32 = 12; w32 >>>= 1; if (w32 != 6) $stop; - w32 = 12; w32 <<= 1; if (w32 != 24) $stop; - w32 = 12; w32 %= 5; if (w32 != 2) $stop; + // Increments + w32 = 12; w32++; if (w32 != 13) $stop; + w32 = 12; ++w32; if (w32 != 13) $stop; + w32 = 12; w32--; if (w32 != 11) $stop; + w32 = 12; --w32; if (w32 != 11) $stop; + w32 = 12; w32 += 2; if (w32 != 14) $stop; + w32 = 12; w32 -= 2; if (w32 != 10) $stop; + w32 = 12; w32 *= 2; if (w32 != 24) $stop; + w32 = 12; w32 /= 2; if (w32 != 6) $stop; + w32 = 12; w32 &= 6; if (w32 != 4) $stop; + w32 = 12; w32 |= 15; if (w32 != 15) $stop; + w32 = 12; w32 ^= 15; if (w32 != 3) $stop; + w32 = 12; w32 >>= 1; if (w32 != 6) $stop; + w32 = 12; w32 >>>= 1; if (w32 != 6) $stop; + w32 = 12; w32 <<= 1; if (w32 != 24) $stop; + w32 = 12; w32 %= 5; if (w32 != 2) $stop; - // Increments - v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; - v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; - v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; - v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; - v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; - v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; - v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; - v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; - v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; - v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; - v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; - v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; - v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; - end - if (cyc==2) begin - win <= 32'h123123; - if (narrow !== 32'hfffffefb) $stop; - if (narrow2 !== 32'hffffff9d) $stop; - end - if (cyc==3) begin - if (narrow !== 32'h00123012) $stop; - if (narrow2 !== 32'h001230b4) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Increments + v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; + v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; + v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; + v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; + v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; + v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; + v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; + v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; + v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; + v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; + v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; end - end + if (cyc==2) begin + win <= 32'h123123; + if (narrow !== 32'hfffffefb) $stop; + if (narrow2 !== 32'hffffff9d) $stop; + end + if (cyc==3) begin + if (narrow !== 32'h00123012) $stop; + if (narrow2 !== 32'h001230b4) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_countbits.v b/test_regress/t/t_math_countbits.v index 24818ddfa..82d66937c 100644 --- a/test_regress/t/t_math_countbits.v +++ b/test_regress/t/t_math_countbits.v @@ -4,166 +4,164 @@ // SPDX-FileCopyrightText: 2020 Yossi Nivin // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [15:0] in16; - reg [31:0] in32; - reg [63:0] in64; - // Non-standard size - reg [9:0] in10; - reg [20:0] in21; - reg [58:0] in59; - reg [69:0] in70; + reg [15:0] in16; + reg [31:0] in32; + reg [63:0] in64; + // Non-standard size + reg [9:0] in10; + reg [20:0] in21; + reg [58:0] in59; + reg [69:0] in70; - reg [31:0] ctrl0; - reg [31:0] ctrl1; - reg [31:0] ctrl2; + reg [31:0] ctrl0; + reg [31:0] ctrl1; + reg [31:0] ctrl2; - int result_16_1; - int result_16_2; - int result_16_3; - int result_32_1; - int result_32_2; - int result_32_3; - int result_64_1; - int result_64_2; - int result_64_3; - int result_10_3; - int result_21_3; - int result_59_3; - int result_70_3; + int result_16_1; + int result_16_2; + int result_16_3; + int result_32_1; + int result_32_2; + int result_32_3; + int result_64_1; + int result_64_2; + int result_64_3; + int result_10_3; + int result_21_3; + int result_59_3; + int result_70_3; - initial begin - if ($countbits(32'b111100000000, '1) != 4) $stop; - if ($countbits(32'b111100000000, '0) != 28) $stop; - if ($countbits(32'b111100000000, '0, '1) != 32) $stop; - if ($countbits(4'bxxx0, 'x) != 3) $stop; - if ($countbits(4'bzzz0, 'z) != 3) $stop; - if ($countbits(4'b1zz0, 'z, '0) != 3) $stop; - if ($countbits(4'b1xx0, 'x, '0) != 3) $stop; - if ($countbits(4'b1xx0, 'x, '0, '1) != 4) $stop; - if ($countbits(4'bzzx0, 'x, 'z) != 3) $stop; - end + initial begin + if ($countbits(32'b111100000000, '1) != 4) $stop; + if ($countbits(32'b111100000000, '0) != 28) $stop; + if ($countbits(32'b111100000000, '0, '1) != 32) $stop; + if ($countbits(4'bxxx0, 'x) != 3) $stop; + if ($countbits(4'bzzz0, 'z) != 3) $stop; + if ($countbits(4'b1zz0, 'z, '0) != 3) $stop; + if ($countbits(4'b1xx0, 'x, '0) != 3) $stop; + if ($countbits(4'b1xx0, 'x, '0, '1) != 4) $stop; + if ($countbits(4'bzzx0, 'x, 'z) != 3) $stop; + end - always @* begin - result_16_1 = $countbits(in16, ctrl0); - result_16_2 = $countbits(in16, ctrl0, ctrl1); - result_16_3 = $countbits(in16, ctrl0, ctrl1, ctrl2); + always @* begin + result_16_1 = $countbits(in16, ctrl0); + result_16_2 = $countbits(in16, ctrl0, ctrl1); + result_16_3 = $countbits(in16, ctrl0, ctrl1, ctrl2); - result_32_1 = $countbits(in32, ctrl0); - result_32_2 = $countbits(in32, ctrl0, ctrl1); - result_32_3 = $countbits(in32, ctrl0, ctrl1, ctrl2); + result_32_1 = $countbits(in32, ctrl0); + result_32_2 = $countbits(in32, ctrl0, ctrl1); + result_32_3 = $countbits(in32, ctrl0, ctrl1, ctrl2); - result_64_1 = $countbits(in64, ctrl0); - result_64_2 = $countbits(in64, ctrl0, ctrl1); - result_64_3 = $countbits(in64, ctrl0, ctrl1, ctrl2); + result_64_1 = $countbits(in64, ctrl0); + result_64_2 = $countbits(in64, ctrl0, ctrl1); + result_64_3 = $countbits(in64, ctrl0, ctrl1, ctrl2); - result_10_3 = $countbits(in10, ctrl0, ctrl1, ctrl2); - result_21_3 = $countbits(in21, ctrl0, ctrl1, ctrl2); - result_59_3 = $countbits(in59, ctrl0, ctrl1, ctrl2); - result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2); - end + result_10_3 = $countbits(in10, ctrl0, ctrl1, ctrl2); + result_21_3 = $countbits(in21, ctrl0, ctrl1, ctrl2); + result_59_3 = $countbits(in59, ctrl0, ctrl1, ctrl2); + result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2); + end - logic [31:0] val = 32'h70008421; + logic [31:0] val = 32'h70008421; - integer cyc = 0; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Constants - if ($countbits(32'b11001011101, '1) != 7) $stop; - if ($countbits(32'b11001011101, '1, 'z) != 7) $stop; - if ($countbits(32'b11001011101, '1, '0) != 32) $stop; - if ($countbits(20'b11001011101, '1, '0) != 20) $stop; - if ($countbits(20'b1100x01z101, '1, '0) != 18) $stop; - if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop; - if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop; - if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop; + integer cyc = 0; + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Constants + if ($countbits(32'b11001011101, '1) != 7) $stop; + if ($countbits(32'b11001011101, '1, 'z) != 7) $stop; + if ($countbits(32'b11001011101, '1, '0) != 32) $stop; + if ($countbits(20'b11001011101, '1, '0) != 20) $stop; + if ($countbits(20'b1100x01z101, '1, '0) != 18) $stop; + if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop; + if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop; + if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop; - if ($countbits(val, '1) != 7) $stop; - if ($countones(val) != 7) $stop; - if ($countbits(val, '0) != 25) $stop; - if ($countbits(val, '0, '1) != 32) $stop; - // Optimization may depend on position of X, so need to walk it - if ($countbits(val, 'x) != 0) $stop; - if ($countbits(val, 'x, '1) != 7) $stop; - if ($countbits(val, '1, 'x) != 7) $stop; - if ($countbits(val, '1, '1, 'x) != 7) $stop; - if ($countbits(val, 'x, '0) != 25) $stop; - if ($countbits(val, 'x, '0, '1) != 32) $stop; - // Optimization may depend on position of Z, so need to walk it - if ($countbits(val, 'z) != 0) $stop; - if ($countbits(val, 'z, '1) != 7) $stop; - if ($countbits(val, '1, 'z) != 7) $stop; - if ($countbits(val, '1, '1, 'z) != 7) $stop; - if ($countbits(val, 'z, '0) != 25) $stop; - if ($countbits(val, 'z, '0, '1) != 32) $stop; - // - if ($countbits(val, 'x, 'z) != 0) $stop; - end - else if (cyc == 1) begin - in16 <= 16'h0AF0; - in32 <= 32'hA0F300; - in64 <= 64'hA5A5A5A5A5A5A5A5; - in10 <= 10'b1010_1011; - in21 <= 21'h10F102; - in59 <= 59'h7050137210; - in70 <= 70'hF00030008000; - ctrl0 <= '0; - ctrl1 <= '1; - ctrl2 <= '1; - end - else if (cyc == 2) begin - if (result_16_1 != 10) $stop; - if (result_16_2 != 16) $stop; - if (result_16_3 != 16) $stop; - if (result_32_1 != 24) $stop; - if (result_32_2 != 32) $stop; - if (result_32_3 != 32) $stop; - if (result_64_1 != 32) $stop; - if (result_64_2 != 64) $stop; - if (result_64_3 != 64) $stop; - if (result_10_3 != 10) $stop; - if (result_21_3 != 21) $stop; - if (result_59_3 != 59) $stop; - if (result_70_3 != 70) $stop; + if ($countbits(val, '1) != 7) $stop; + if ($countones(val) != 7) $stop; + if ($countbits(val, '0) != 25) $stop; + if ($countbits(val, '0, '1) != 32) $stop; + // Optimization may depend on position of X, so need to walk it + if ($countbits(val, 'x) != 0) $stop; + if ($countbits(val, 'x, '1) != 7) $stop; + if ($countbits(val, '1, 'x) != 7) $stop; + if ($countbits(val, '1, '1, 'x) != 7) $stop; + if ($countbits(val, 'x, '0) != 25) $stop; + if ($countbits(val, 'x, '0, '1) != 32) $stop; + // Optimization may depend on position of Z, so need to walk it + if ($countbits(val, 'z) != 0) $stop; + if ($countbits(val, 'z, '1) != 7) $stop; + if ($countbits(val, '1, 'z) != 7) $stop; + if ($countbits(val, '1, '1, 'z) != 7) $stop; + if ($countbits(val, 'z, '0) != 25) $stop; + if ($countbits(val, 'z, '0, '1) != 32) $stop; + // + if ($countbits(val, 'x, 'z) != 0) $stop; + end + else if (cyc == 1) begin + in16 <= 16'h0AF0; + in32 <= 32'hA0F300; + in64 <= 64'hA5A5A5A5A5A5A5A5; + in10 <= 10'b1010_1011; + in21 <= 21'h10F102; + in59 <= 59'h7050137210; + in70 <= 70'hF00030008000; + ctrl0 <= '0; + ctrl1 <= '1; + ctrl2 <= '1; + end + else if (cyc == 2) begin + if (result_16_1 != 10) $stop; + if (result_16_2 != 16) $stop; + if (result_16_3 != 16) $stop; + if (result_32_1 != 24) $stop; + if (result_32_2 != 32) $stop; + if (result_32_3 != 32) $stop; + if (result_64_1 != 32) $stop; + if (result_64_2 != 64) $stop; + if (result_64_3 != 64) $stop; + if (result_10_3 != 10) $stop; + if (result_21_3 != 21) $stop; + if (result_59_3 != 59) $stop; + if (result_70_3 != 70) $stop; - in16 <= 16'h82B; - in32 <= 32'h305372; - in64 <= 64'h7777777777777777; - in10 <= 10'b1001_0111; - in21 <= 21'h91040C; - in59 <= 59'h12345678; - in70 <= 70'hF11111111; - // Confirm upper bits of the control arguments are ignored - ctrl0 <= 5; - ctrl1 <= 3; - ctrl2 <= 2; - end - else if (cyc == 3) begin - if (result_16_1 != 5) $stop; - if (result_16_2 != 5) $stop; - if (result_16_3 != 16) $stop; - if (result_32_1 != 10) $stop; - if (result_32_2 != 10) $stop; - if (result_32_3 != 32) $stop; - if (result_64_1 != 48) $stop; - if (result_64_2 != 48) $stop; - if (result_64_3 != 64) $stop; - if (result_10_3 != 10) $stop; - if (result_21_3 != 21) $stop; - if (result_59_3 != 59) $stop; - if (result_70_3 != 70) $stop; - end - else if (cyc == 4) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + in16 <= 16'h82B; + in32 <= 32'h305372; + in64 <= 64'h7777777777777777; + in10 <= 10'b1001_0111; + in21 <= 21'h91040C; + in59 <= 59'h12345678; + in70 <= 70'hF11111111; + // Confirm upper bits of the control arguments are ignored + ctrl0 <= 5; + ctrl1 <= 3; + ctrl2 <= 2; + end + else if (cyc == 3) begin + if (result_16_1 != 5) $stop; + if (result_16_2 != 5) $stop; + if (result_16_3 != 16) $stop; + if (result_32_1 != 10) $stop; + if (result_32_2 != 10) $stop; + if (result_32_3 != 32) $stop; + if (result_64_1 != 48) $stop; + if (result_64_2 != 48) $stop; + if (result_64_3 != 64) $stop; + if (result_10_3 != 10) $stop; + if (result_21_3 != 21) $stop; + if (result_59_3 != 59) $stop; + if (result_70_3 != 70) $stop; + end + else if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_countbits2_bad.out b/test_regress/t/t_math_countbits2_bad.out index 308e188a0..88cee7bb6 100644 --- a/test_regress/t/t_math_countbits2_bad.out +++ b/test_regress/t/t_math_countbits2_bad.out @@ -1,18 +1,18 @@ -%Error: t/t_math_countbits2_bad.v:15:15: Expected numeric type, but got a 'logic$[0:3]' data type +%Error: t/t_math_countbits2_bad.v:15:13: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' - 15 | count = $countones(my_vec); - | ^~~~~~~~~~ + 15 | count = $countones(my_vec); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_math_countbits2_bad.v:16:15: Expected numeric type, but got a 'logic$[0:3]' data type +%Error: t/t_math_countbits2_bad.v:16:13: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' - 16 | count = $countbits(my_vec, '0); - | ^~~~~~~~~~ -%Error: t/t_math_countbits2_bad.v:17:14: Expected numeric type, but got a 'logic$[0:3]' data type + 16 | count = $countbits(my_vec, '0); + | ^~~~~~~~~~ +%Error: t/t_math_countbits2_bad.v:17:12: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' - 17 | bool = $onehot(my_vec); - | ^~~~~~~ -%Error: t/t_math_countbits2_bad.v:18:14: Expected numeric type, but got a 'logic$[0:3]' data type + 17 | bool = $onehot(my_vec); + | ^~~~~~~ +%Error: t/t_math_countbits2_bad.v:18:12: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' - 18 | bool = $onehot0(my_vec); - | ^~~~~~~~ + 18 | bool = $onehot0(my_vec); + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_math_countbits2_bad.v b/test_regress/t/t_math_countbits2_bad.v index 65254bb0e..ed46a2923 100644 --- a/test_regress/t/t_math_countbits2_bad.v +++ b/test_regress/t/t_math_countbits2_bad.v @@ -6,18 +6,18 @@ module t; - logic my_vec [4]; - logic bool; - int count; + logic my_vec[4]; + logic bool; + int count; - initial begin - my_vec = '{1, 0, 1, 0}; - count = $countones(my_vec); // Bad, must be bit vector - count = $countbits(my_vec, '0); // Bad, must be bit vector - bool = $onehot(my_vec); // Bad, must be bit vector - bool = $onehot0(my_vec); // Bad, must be bit vector - bool = $isunknown(my_vec); // Bad, must be bit vector - $stop; - end + initial begin + my_vec = '{1, 0, 1, 0}; + count = $countones(my_vec); // Bad, must be bit vector + count = $countbits(my_vec, '0); // Bad, must be bit vector + bool = $onehot(my_vec); // Bad, must be bit vector + bool = $onehot0(my_vec); // Bad, must be bit vector + bool = $isunknown(my_vec); // Bad, must be bit vector + $stop; + end endmodule diff --git a/test_regress/t/t_math_countbits_bad.out b/test_regress/t/t_math_countbits_bad.out index 479d0b3dc..02320437c 100644 --- a/test_regress/t/t_math_countbits_bad.out +++ b/test_regress/t/t_math_countbits_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_math_countbits_bad.v:10:54: Unsupported: $countbits with more than 3 control fields - 10 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); - | ^~ +%Error-UNSUPPORTED: t/t_math_countbits_bad.v:10:53: Unsupported: $countbits with more than 3 control fields + 10 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); + | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_math_countbits_bad.v b/test_regress/t/t_math_countbits_bad.v index 97237eaed..fa7f9d3ce 100644 --- a/test_regress/t/t_math_countbits_bad.v +++ b/test_regress/t/t_math_countbits_bad.v @@ -6,7 +6,7 @@ module t; - integer count; - assign count = $countbits(32'h123456, '0, '1, 'x, 'z); + integer count; + assign count = $countbits(32'h123456, '0, '1, 'x, 'z); endmodule diff --git a/test_regress/t/t_math_countbits_tri.v b/test_regress/t/t_math_countbits_tri.v index 79c4a77b4..0e61b7743 100644 --- a/test_regress/t/t_math_countbits_tri.v +++ b/test_regress/t/t_math_countbits_tri.v @@ -4,35 +4,39 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - num_zeros, num_ones, - // Inputs - clk, reset_l, vec - ); +module t ( /*AUTOARG*/ + // Outputs + num_zeros, + num_ones, + // Inputs + clk, + reset_l, + vec +); - input logic clk; - input logic reset_l; - input logic [7:0] vec; - output logic [7:0] num_zeros; - output logic [7:0] num_ones; + input logic clk; + input logic reset_l; + input logic [7:0] vec; + output logic [7:0] num_zeros; + output logic [7:0] num_ones; - always_comb begin - num_zeros = '0; - num_ones = '0; - for (int i = 0; i < 8; i++) begin - if (vec[i] == 0) begin - num_zeros++; - end else begin - num_ones++; - end + always_comb begin + num_zeros = '0; + num_ones = '0; + for (int i = 0; i < 8; i++) begin + if (vec[i] == 0) begin + num_zeros++; end - end - assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec))); - assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0))); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + else begin + num_ones++; + end + end + end + assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec))); + assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0))); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_cv_bitop.v b/test_regress/t/t_math_cv_bitop.v index 06ccd2386..c6240d04b 100644 --- a/test_regress/t/t_math_cv_bitop.v +++ b/test_regress/t/t_math_cv_bitop.v @@ -10,85 +10,85 @@ // verilog_format: on module sub ( - input wire clock_4, - input wire clock_8, - output wire [28:5] out63 + input wire clock_4, + input wire clock_8, + output wire [28:5] out63 ); - reg [28:0] reg_12; - reg [28:22] reg_24; + reg [28:0] reg_12; + reg [28:22] reg_24; - wire _0558_ = | reg_24[26:25]; // reg_24 = 0 or 1100110 ---> _0558_ == 0 - wire [28:0] _0670_ = _0558_ ? reg_12 : 29'h00000f93; // _0558_ == 0 ---> _0670_ == 29'h00000f93 - wire [28:0] _0399_= - _0670_; // _0670_ == 29'h00000f93 ---> _0399_ = 29'b11111111111111111000001101101 - wire _0085_ = ~ _0399_[2]; // _0399_[2] == 1 ---> _0085_ == 0 - wire [28:0] _0769_; - assign { _0769_[28:3], _0769_[1:0] } = { _0399_[28:3], _0399_[1:0] }; // _0769_ != 0 - assign _0769_[2] = _0085_; + wire _0558_ = |reg_24[26:25]; // reg_24 = 0 or 1100110 ---> _0558_ == 0 + wire [28:0] _0670_ = _0558_ ? reg_12 : 29'h00000f93; // _0558_ == 0 ---> _0670_ == 29'h00000f93 + wire [28:0] _0399_= - _0670_; // _0670_ == 29'h00000f93 ---> _0399_ = 29'b11111111111111111000001101101 + wire _0085_ = ~_0399_[2]; // _0399_[2] == 1 ---> _0085_ == 0 + wire [28:0] _0769_; + assign {_0769_[28:3], _0769_[1:0]} = {_0399_[28:3], _0399_[1:0]}; // _0769_ != 0 + assign _0769_[2] = _0085_; - // verilator lint_off WIDTH - wire _0305_ = ! _0769_; // _0769_ != 0 ---> _0305_ == 0 - wire [23:0] _0306_ = ! _0305_; // _0305_ == 0 ---> _0306_ == 1 - // verilator lint_on WIDTH + // verilator lint_off WIDTH + wire _0305_ = !_0769_; // _0769_ != 0 ---> _0305_ == 0 + wire [23:0] _0306_ = !_0305_; // _0305_ == 0 ---> _0306_ == 1 + // verilator lint_on WIDTH - assign out63 = _0306_; // out63 == 1 + assign out63 = _0306_; // out63 == 1 - always @(posedge clock_4, posedge clock_8) - if (clock_8) reg_12 <= 29'h00000066; - else reg_12 <= { reg_12[28:27], 25'h0000001, reg_12[1:0] }; + always @(posedge clock_4, posedge clock_8) + if (clock_8) reg_12 <= 29'h00000066; + else reg_12 <= {reg_12[28:27], 25'h0000001, reg_12[1:0]}; - always @(posedge clock_4, posedge clock_8) - if (clock_8) reg_24 <= 7'h66; - else reg_24 <= reg_24; + always @(posedge clock_4, posedge clock_8) + if (clock_8) reg_24 <= 7'h66; + else reg_24 <= reg_24; endmodule module t; - reg clock_4; - reg clock_8; - wire signed [28:5] out63; - reg signed [7:0] tmp = -1; - reg signed [0:0] one = 1; - reg signed [0:0] onert = 1; + reg clock_4; + reg clock_8; + wire signed [28:5] out63; + reg signed [7:0] tmp = -1; + reg signed [0:0] one = 1; + reg signed [0:0] onert = 1; - sub sub ( - .clock_4 (clock_4), - .clock_8 (clock_8), - .out63 (out63) - ); + sub sub ( + .clock_4(clock_4), + .clock_8(clock_8), + .out63(out63) + ); - initial begin - // All simulators agree: 1'sb1 really shows as decimal -1 - $display("one 'd=%d 'b=%b", one, one); + initial begin + // All simulators agree: 1'sb1 really shows as decimal -1 + $display("one 'd=%d 'b=%b", one, one); `ifdef VERILATOR - onert = $c(1); + onert = $c(1); `endif - $display("ort 'd=%d 'b=%b", onert, onert); + $display("ort 'd=%d 'b=%b", onert, onert); - $display("tmp 'd=%d 'b=%b", tmp, tmp); + $display("tmp 'd=%d 'b=%b", tmp, tmp); - clock_4 = 0; - clock_8 = 0; - #2000; + clock_4 = 0; + clock_8 = 0; + #2000; - sub.reg_24 = 0; - sub.reg_12 = 0; - #2000; + sub.reg_24 = 0; + sub.reg_12 = 0; + #2000; - clock_4 = 0; - clock_8 = 0; - #10; - $display("out63 'd=%d 'b=%b", out63, out63); + clock_4 = 0; + clock_8 = 0; + #10; + $display("out63 'd=%d 'b=%b", out63, out63); - #2000; - clock_4 = 1; - clock_8 = 1; - #10; - $display("out63 'd=%d 'b=%b", out63, out63); + #2000; + clock_4 = 1; + clock_8 = 1; + #10; + $display("out63 'd=%d 'b=%b", out63, out63); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_cv_concat.v b/test_regress/t/t_math_cv_concat.v index 60d88be0b..09da3fcb3 100644 --- a/test_regress/t/t_math_cv_concat.v +++ b/test_regress/t/t_math_cv_concat.v @@ -10,35 +10,35 @@ // verilog_format: on module t; - // Issue #5972 + // Issue #5972 - reg clk; - reg signed [28:28] in1; - reg signed [21:8] reg_10; + reg clk; + reg signed [28:28] in1; + reg signed [21:8] reg_10; - // verilator lint_off WIDTHEXPAND - always @(negedge clk) begin - // Issue #5972 - reg_10[14:8] <= {1'b1, ~((in1[28:28] & ~(in1[28:28])))}; - end + // verilator lint_off WIDTHEXPAND + always @(negedge clk) begin + // Issue #5972 + reg_10[14:8] <= {1'b1, ~((in1[28:28] & ~(in1[28:28])))}; + end - initial begin - clk = 1; - in1 = 1'b0; - reg_10 = '0; - #2; - clk = 0; - #2; - `checkh(reg_10, 3); + initial begin + clk = 1; + in1 = 1'b0; + reg_10 = '0; + #2; + clk = 0; + #2; + `checkh(reg_10, 3); - in1 = 1'b1; - clk = 1; - #2; - clk = 0; - #2; - `checkh(reg_10, 3); + in1 = 1'b1; + clk = 1; + #2; + clk = 0; + #2; + `checkh(reg_10, 3); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_cv_format.v b/test_regress/t/t_math_cv_format.v index 650c6f168..ee6ffc37c 100644 --- a/test_regress/t/t_math_cv_format.v +++ b/test_regress/t/t_math_cv_format.v @@ -10,71 +10,71 @@ // verilog_format: on module t; - wire signed [21:10] out0; + wire signed [21:10] out0; - sub sub ( - .out0(out0) - ); + sub sub (.out0(out0)); - sub2 sub2 (); + sub2 sub2 (); - string s; + string s; - initial begin - #20; - // Bug with sformat, so can't just number-compare - s = $sformatf("out0=%0d", out0); - `checks(s, "out0=-12"); - if (out0 > 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #20; + // Bug with sformat, so can't just number-compare + s = $sformatf("out0=%0d", out0); + `checks(s, "out0=-12"); + if (out0 > 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub (out0); - reg signed [27:20] reg_4; - output wire [21:10] out0; +module sub ( + out0 +); + reg signed [27:20] reg_4; + output wire [21:10] out0; - initial begin - #1; - reg_4 = 0; - end + initial begin + #1; + reg_4 = 0; + end - wire [11:0] w55; - wire [11:0] w23; - // verilator lint_off WIDTHEXPAND - assign w55 = ~reg_4[20]; - // verilator lint_on WIDTHEXPAND - assign { w23[3], w23[1:0] } = 3'h0; - assign { w23[11:4], w23[2] } = { w55[11:4], w55[2] }; - assign out0 = w23; + wire [11:0] w55; + wire [11:0] w23; + // verilator lint_off WIDTHEXPAND + assign w55 = ~reg_4[20]; + // verilator lint_on WIDTHEXPAND + assign {w23[3], w23[1:0]} = 3'h0; + assign {w23[11:4], w23[2]} = {w55[11:4], w55[2]}; + assign out0 = w23; endmodule module sub2; - reg [27:5] in0; - reg [26:11] in1; - wire [24:14] wire_0; - wire [26:5] out1; - wire w085; - wire w082; - wire [10:0] w092; - wire [9:0] w028; + reg [27:5] in0; + reg [26:11] in1; + wire [24:14] wire_0; + wire [26:5] out1; + wire w085; + wire w082; + wire [10:0] w092; + wire [9:0] w028; - string s; + string s; - initial begin - in0 = 6902127; - in1 = 10000; - #10; - s = $sformatf("out0=%0d", out1); - `checks(s, "out0=0"); - end + initial begin + in0 = 6902127; + in1 = 10000; + #10; + s = $sformatf("out0=%0d", out1); + `checks(s, "out0=0"); + end - assign w028 = ~ { 9'h000, in0[23] }; - assign w092[1] = 1'h0; - assign { w092[10:2], w092[0] } = w028; - assign wire_0 = w092; - assign w082 = | wire_0[18:17]; - assign w085 = w082 ? in1[11] : 1'h0; - assign out1 = { 21'h000000, w085 }; + assign w028 = ~{9'h000, in0[23]}; + assign w092[1] = 1'h0; + assign {w092[10:2], w092[0]} = w028; + assign wire_0 = w092; + assign w082 = |wire_0[18:17]; + assign w085 = w082 ? in1[11] : 1'h0; + assign out1 = {21'h000000, w085}; endmodule diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v index 0656f6db7..8306f3337 100644 --- a/test_regress/t/t_math_div.v +++ b/test_regress/t/t_math_div.v @@ -4,112 +4,118 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - reg [255:0] a; - reg [60:0] divisor; - reg [60:0] qq; - reg [60:0] rq; - reg [60:0] qq4; - reg [60:0] rq4; - reg [60:0] qq5; - reg [60:0] rq5; - reg signed [60:0] qqs; - reg signed [60:0] rqs; + reg [255:0] a; + reg [60:0] divisor; + reg [60:0] qq; + reg [60:0] rq; + reg [60:0] qq4; + reg [60:0] rq4; + reg [60:0] qq5; + reg [60:0] rq5; + reg signed [60:0] qqs; + reg signed [60:0] rqs; - always @* begin - qq = a[60:0] / divisor; - rq = a[60:0] % divisor; - qq4 = a[60:0] / 4; // Check power-of-two constification - rq4 = a[60:0] % 4; - qq5 = a[60:0] / 5; // Non power-of-two - rq5 = a[60:0] % 5; - qqs = $signed(a[60:0]) / $signed(divisor); - rqs = $signed(a[60:0]) % $signed(divisor); - end + always @* begin + qq = a[60:0] / divisor; + rq = a[60:0] % divisor; + qq4 = a[60:0] / 4; // Check power-of-two constification + rq4 = a[60:0] % 4; + qq5 = a[60:0] / 5; // Non power-of-two + rq5 = a[60:0] % 5; + qqs = $signed(a[60:0]) / $signed(divisor); + rqs = $signed(a[60:0]) % $signed(divisor); + end - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); - if (cyc==1) begin - a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - divisor <= 61'h12371; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - end - if (cyc > 1) begin - if (qq4 != {2'b0, a[60:2]}) $stop; - if (rq4 != {59'h0, a[1:0]}) $stop; - end - if (cyc==2) begin - a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - divisor <= 61'h1238123771; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - if (qq!==61'h00000403ad81c0da) $stop; - if (rq!==61'h00000000000090ec) $stop; - if (qqs!==61'h00000403ad81c0da) $stop; - if (rqs!==61'h00000000000090ec) $stop; - if (qq4 != 61'h01247cf6851f9fc9) $stop; - if (rq4 != 61'h0000000000000002) $stop; - end - if (cyc==3) begin - a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; - divisor <= 61'hf1b; - a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed - if (qq!==61'h000000000090832e) $stop; - if (rq!==61'h0000000334becc6a) $stop; - if (qqs!==61'h000000000090832e) $stop; - if (rqs!==61'h0000000334becc6a) $stop; - if (qq4 != 61'h0292380e727ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==4) begin - a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0001eda37cca1be8) $stop; - if (rq!==61'h0000000000000c40) $stop; - if (qqs!==61'h1fffcf5187c76510) $stop; - if (rqs!==61'h1ffffffffffffd08) $stop; - if (qq4 != 61'h07482923803ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==5) begin - a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0000000000000000) $stop; - if (rq!==61'h0d20a48e00f395b8) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h0d20a48e00f395b8) $stop; - end - if (cyc==6) begin - if (qq!==61'h0000000000000001) $stop; - if (rq!==61'h0d20a48e00f3869d) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h1d20a48e00f395b8) $stop; - end - // Div by zero - if (cyc==9) begin - divisor <= 61'd0; - end - if (cyc==10) begin -`ifdef verilator - if (qq !== {61{1'b0}}) $stop; - if (rq !== {61{1'b0}}) $stop; -`else - if (qq !== {61{1'bx}}) $stop; - if (rq !== {61{1'bx}}) $stop; -`endif - if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors - if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors - end - if (cyc==19) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); + if (cyc == 1) begin + a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + divisor <= 61'h12371; + a[60] <= 1'b0; + divisor[60] <= 1'b0; // Unsigned end - end + if (cyc > 1) begin + if (qq4 != {2'b0, a[60:2]}) $stop; + if (rq4 != {59'h0, a[1:0]}) $stop; + end + if (cyc == 2) begin + a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + divisor <= 61'h1238123771; + a[60] <= 1'b0; + divisor[60] <= 1'b0; // Unsigned + if (qq !== 61'h00000403ad81c0da) $stop; + if (rq !== 61'h00000000000090ec) $stop; + if (qqs !== 61'h00000403ad81c0da) $stop; + if (rqs !== 61'h00000000000090ec) $stop; + if (qq4 != 61'h01247cf6851f9fc9) $stop; + if (rq4 != 61'h0000000000000002) $stop; + end + if (cyc == 3) begin + a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; + divisor <= 61'hf1b; + a[60] <= 1'b1; + divisor[60] <= 1'b0; // Signed + if (qq !== 61'h000000000090832e) $stop; + if (rq !== 61'h0000000334becc6a) $stop; + if (qqs !== 61'h000000000090832e) $stop; + if (rqs !== 61'h0000000334becc6a) $stop; + if (qq4 != 61'h0292380e727ce56e) $stop; + if (rq4 != 61'h0000000000000000) $stop; + end + if (cyc == 4) begin + a[60] <= 1'b0; + divisor[60] <= 1'b1; // Signed + if (qq !== 61'h0001eda37cca1be8) $stop; + if (rq !== 61'h0000000000000c40) $stop; + if (qqs !== 61'h1fffcf5187c76510) $stop; + if (rqs !== 61'h1ffffffffffffd08) $stop; + if (qq4 != 61'h07482923803ce56e) $stop; + if (rq4 != 61'h0000000000000000) $stop; + end + if (cyc == 5) begin + a[60] <= 1'b1; + divisor[60] <= 1'b1; // Signed + if (qq !== 61'h0000000000000000) $stop; + if (rq !== 61'h0d20a48e00f395b8) $stop; + if (qqs !== 61'h0000000000000000) $stop; + if (rqs !== 61'h0d20a48e00f395b8) $stop; + end + if (cyc == 6) begin + if (qq !== 61'h0000000000000001) $stop; + if (rq !== 61'h0d20a48e00f3869d) $stop; + if (qqs !== 61'h0000000000000000) $stop; + if (rqs !== 61'h1d20a48e00f395b8) $stop; + end + // Div by zero + if (cyc == 9) begin + divisor <= 61'd0; + end + if (cyc == 10) begin +`ifdef verilator + if (qq !== {61{1'b0}}) $stop; + if (rq !== {61{1'b0}}) $stop; +`else + if (qq !== {61{1'bx}}) $stop; + if (rq !== {61{1'bx}}) $stop; +`endif + if ({16{1'bx}} !== 16'd1 / 16'd0) $stop; // No div by zero errors + if ({16{1'bx}} !== 16'd1 % 16'd0) $stop; // No div by zero errors + end + if (cyc == 19) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_div0.v b/test_regress/t/t_math_div0.v index 22f5a41f9..5390df073 100644 --- a/test_regress/t/t_math_div0.v +++ b/test_regress/t/t_math_div0.v @@ -3,31 +3,35 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - y, d2, m2, d3, m3 - ); - output [3:0] y; - output [31:0] d2; - output [31:0] m2; - output [63:0] d3; - output [63:0] m3; - // bug775 - // verilator lint_off WIDTH - assign y = ((0/0) ? 1 : 2) % 0; +module t ( /*AUTOARG*/ + // Outputs + y, + d2, + m2, + d3, + m3 +); + output [3:0] y; + output [31:0] d2; + output [31:0] m2; + output [63:0] d3; + output [63:0] m3; + // bug775 + // verilator lint_off WIDTH + assign y = ((0 / 0) ? 1 : 2) % 0; - // bug2460 - reg [31:0] b; - assign d2 = $signed(32'h80000000) / $signed(b); - assign m2 = $signed(32'h80000000) % $signed(b); - reg [63:0] b3; - assign d3 = $signed(64'h80000000_00000000) / $signed(b3); - assign m3 = $signed(64'h80000000_00000000) % $signed(b3); + // bug2460 + reg [31:0] b; + assign d2 = $signed(32'h80000000) / $signed(b); + assign m2 = $signed(32'h80000000) % $signed(b); + reg [63:0] b3; + assign d3 = $signed(64'h80000000_00000000) / $signed(b3); + assign m3 = $signed(64'h80000000_00000000) % $signed(b3); - initial begin - b = 32'hffffffff; - b3 = 64'hffffffff_ffffffff; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + b = 32'hffffffff; + b3 = 64'hffffffff_ffffffff; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_divw.v b/test_regress/t/t_math_divw.v index 9406748f8..4167e3146 100644 --- a/test_regress/t/t_math_divw.v +++ b/test_regress/t/t_math_divw.v @@ -4,138 +4,139 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; - // verilator lint_off WIDTH + // verilator lint_off WIDTH - //============================================================ + //============================================================ - reg bad; - initial begin - bad=0; - c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); - c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); - c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); + reg bad; + initial begin + bad=0; + c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); + c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); - c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); - c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); - c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); - c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); - c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); - c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); - c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); - c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); - c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); - c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); - c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); - c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); - c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); - c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); - c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); - c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); - c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); - c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); - c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); - c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); - c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); - c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); - c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); - c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); + c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); + c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); + c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); + c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); + c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); + c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); + c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); + c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); + c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); + c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); + c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); + c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); + c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); + c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); + c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); + c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); + c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); + c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); + c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); + c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); + c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); + c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); + c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); + c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); - c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); - c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); + c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); + c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); - c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); - c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); - c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); - c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); - c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); - c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); - c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); - c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); - c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); - c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); - c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); + c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); + c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); + c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); + c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); + c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); + c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); + c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); + c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); + c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); + c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); - if (bad) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (bad) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - task c96; - input [95:0] u; - input [95:0] v; - input [95:0] expq; - input [95:0] expr; - c96u( u, v, expq, expr); - c96s( u, v, expq, expr); - c96s(-u, v,-expq,-expr); - c96s( u,-v,-expq, expr); - c96s(-u,-v, expq,-expr); - endtask + task c96; + input [95:0] u; + input [95:0] v; + input [95:0] expq; + input [95:0] expr; + c96u( u, v, expq, expr); + c96s( u, v, expq, expr); + c96s(-u, v,-expq,-expr); + c96s( u,-v,-expq, expr); + c96s(-u,-v, expq,-expr); + endtask - task c96u; - input [95:0] u; - input [95:0] v; - input [95:0] expq; - input [95:0] expr; - reg [95:0] gotq; - reg [95:0] gotr; - gotq = u/v; - gotr = u%v; - if (gotq != expq && v!=0) begin - bad = 1; - end - if (gotr != expr && v!=0) begin - bad = 1; - end - if (bad + task c96u; + input [95:0] u; + input [95:0] v; + input [95:0] expq; + input [95:0] expr; + reg [95:0] gotq; + reg [95:0] gotr; + gotq = u/v; + gotr = u%v; + if (gotq != expq && v!=0) begin + bad = 1; + end + if (gotr != expr && v!=0) begin + bad = 1; + end + if (bad `ifdef TEST_VERBOSE - || 1 + || 1 `endif - ) begin - $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); - // Test for v=0 to prevent Xs causing grief - if (gotq != expq && v!=0) $write(" BADQ"); - if (gotr != expr && v!=0) $write(" BADR"); - $write("\n"); - end - endtask + ) begin + $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); + end + endtask - task c96s; - input signed [95:0] u; - input signed [95:0] v; - input signed [95:0] expq; - input signed [95:0] expr; - reg signed [95:0] gotq; - reg signed [95:0] gotr; - gotq = u/v; - gotr = u%v; - if (gotq != expq && v!=0) begin - bad = 1; - end - if (gotr != expr && v!=0) begin - bad = 1; - end - if (bad + task c96s; + input signed [95:0] u; + input signed [95:0] v; + input signed [95:0] expq; + input signed [95:0] expr; + reg signed [95:0] gotq; + reg signed [95:0] gotr; + gotq = u/v; + gotr = u%v; + if (gotq != expq && v!=0) begin + bad = 1; + end + if (gotr != expr && v!=0) begin + bad = 1; + end + if (bad `ifdef TEST_VERBOSE - || 1 + || 1 `endif - ) begin - $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); - // Test for v=0 to prevent Xs causing grief - if (gotq != expq && v!=0) $write(" BADQ"); - if (gotr != expr && v!=0) $write(" BADR"); - $write("\n"); - end - endtask + ) begin + $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); + end + endtask endmodule diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v index fe73d3314..944be3c3b 100644 --- a/test_regress/t/t_math_eq.v +++ b/test_regress/t/t_math_eq.v @@ -4,112 +4,116 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[3:0]), + // Inputs + .clk(clk), + .in(in[31:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out}; - // What checksum will we end up with -`define EXPECTED_SUM 64'h1a0d07009b6a30d2 + // What checksum will we end up with + `define EXPECTED_SUM 64'h1a0d07009b6a30d2 - initial begin - `checkh(3'b101 ==? 3'b100, 1'b0); - `checkh(3'b101 ==? 3'b101, 1'b1); - `checkh(3'b100 ==? 3'b10x, 1'b1); - `checkh(3'b101 ==? 3'b10x, 1'b1); - `checkh(3'b10x ==? 3'b10?, 1'b1); - `checkh(3'b110 ==? 3'b10?, 1'b0); - `checkh(3'b111 ==? 3'b10?, 1'b0); - `checkh(3'b11x ==? 3'b10?, 1'b0); - `checkh(3'b101 !=? 3'b100, !1'b0); - `checkh(3'b101 !=? 3'b101, !1'b1); - `checkh(3'b100 !=? 3'b10x, !1'b1); - `checkh(3'b101 !=? 3'b10x, !1'b1); - `checkh(3'b10x !=? 3'b10?, !1'b1); - `checkh(3'b110 !=? 3'b10?, !1'b0); - `checkh(3'b111 !=? 3'b10?, !1'b0); - `checkh(3'b11x !=? 3'b10?, !1'b0); - end + initial begin + `checkh(3'b101 ==? 3'b100, 1'b0); + `checkh(3'b101 ==? 3'b101, 1'b1); + `checkh(3'b100 ==? 3'b10x, 1'b1); + `checkh(3'b101 ==? 3'b10x, 1'b1); + `checkh(3'b10x ==? 3'b10?, 1'b1); + `checkh(3'b110 ==? 3'b10?, 1'b0); + `checkh(3'b111 ==? 3'b10?, 1'b0); + `checkh(3'b11x ==? 3'b10?, 1'b0); + `checkh(3'b101 !=? 3'b100, !1'b0); + `checkh(3'b101 !=? 3'b101, !1'b1); + `checkh(3'b100 !=? 3'b10x, !1'b1); + `checkh(3'b101 !=? 3'b10x, !1'b1); + `checkh(3'b10x !=? 3'b10?, !1'b1); + `checkh(3'b110 !=? 3'b10?, !1'b0); + `checkh(3'b111 !=? 3'b10?, !1'b0); + `checkh(3'b11x !=? 3'b10?, !1'b0); + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - input clk; - input [31:0] in; - output [3:0] out; + input clk; + input [31:0] in; + output [3:0] out; - assign out[0] = in[3:0] ==? 4'b1001; - assign out[1] = in[3:0] !=? 4'b1001; - assign out[2] = in[3:0] ==? 4'bx01x; - assign out[3] = in[3:0] !=? 4'bx01x; + assign out[0] = in[3:0] ==? 4'b1001; + assign out[1] = in[3:0] !=? 4'b1001; + assign out[2] = in[3:0] ==? 4'bx01x; + assign out[3] = in[3:0] !=? 4'bx01x; - wire signed [3:0] ins = in[3:0]; + wire signed [3:0] ins = in[3:0]; - wire signed [3:0] outs; + wire signed [3:0] outs; - assign outs[0] = ins ==? 4'sb1001; - assign outs[1] = ins !=? 4'sb1001; - assign outs[2] = ins ==? 4'sbx01x; - assign outs[3] = ins !=? 4'sbx01x; + assign outs[0] = ins ==? 4'sb1001; + assign outs[1] = ins !=? 4'sb1001; + assign outs[2] = ins ==? 4'sbx01x; + assign outs[3] = ins !=? 4'sbx01x; - always_comb if (out != outs) $stop; + always_comb if (out != outs) $stop; endmodule diff --git a/test_regress/t/t_math_eq_bad.out b/test_regress/t/t_math_eq_bad.out index 2ade5685a..fde8efc3c 100644 --- a/test_regress/t/t_math_eq_bad.out +++ b/test_regress/t/t_math_eq_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_math_eq_bad.v:13:13: Real is illegal operand to ?== operator +%Error: t/t_math_eq_bad.v:13:11: Real is illegal operand to ?== operator : ... note: In instance 't' - 13 | if (a ==? 1.0) $stop; - | ^~~ + 13 | if (a ==? 1.0) $stop; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_math_eq_bad.v b/test_regress/t/t_math_eq_bad.v index 095d1dd26..3270a6595 100644 --- a/test_regress/t/t_math_eq_bad.v +++ b/test_regress/t/t_math_eq_bad.v @@ -6,11 +6,11 @@ module t; - logic [31:0] a; + logic [31:0] a; - initial begin - a = 1234; - if (a ==? 1.0) $stop; // Bad - end + initial begin + a = 1234; + if (a ==? 1.0) $stop; // Bad + end endmodule diff --git a/test_regress/t/t_math_equal.v b/test_regress/t/t_math_equal.v index 3dfa5b579..60f8bae8f 100644 --- a/test_regress/t/t_math_equal.v +++ b/test_regress/t/t_math_equal.v @@ -4,71 +4,68 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer _mode; - integer _mode; + reg _guard1; + reg [127:0] r_wide0; + reg _guard2; + wire [63:0] r_wide1; + reg _guard3; + reg _guard4; + reg _guard5; + reg _guard6; - reg _guard1; - reg [127:0] r_wide0; - reg _guard2; - wire [63:0] r_wide1; - reg _guard3; - reg _guard4; - reg _guard5; - reg _guard6; + assign r_wide1 = r_wide0[127:64]; - assign r_wide1 = r_wide0[127:64]; + // surefire lint_off STMINI + initial _mode = 0; - // surefire lint_off STMINI - initial _mode = 0; + always @(posedge clk) begin + if (_mode == 0) begin + $write("[%0t] t_equal: Running\n", $time); + _guard1 <= 0; + _guard2 <= 0; + _guard3 <= 0; + _guard4 <= 0; + _guard5 <= 0; + _guard6 <= 0; - always @ (posedge clk) begin - if (_mode==0) begin - $write("[%0t] t_equal: Running\n", $time); - _guard1 <= 0; - _guard2 <= 0; - _guard3 <= 0; - _guard4 <= 0; - _guard5 <= 0; - _guard6 <= 0; - - _mode<=1; - r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; + _mode <= 1; + r_wide0 <= {32'haa111111, 32'hbb222222, 32'hcc333333, 32'hdd444444}; + end + else if (_mode == 1) begin + _mode <= 2; + // + if (5'd10 != 5'b1010) $stop; + if (5'd10 != 5'd10) $stop; + if (5'd10 != 5'd1_0) $stop; + if (5'd10 != 5'ha) $stop; + if (5'd10 != 5'o12) $stop; + if (5'd10 != 5'o1_2) $stop; + if (5'd10 != 5'B1010) $stop; + if (5'd10 != 5'B10_10) $stop; + if (5'd10 != 5'D10) $stop; + if (5'd10 != 5'Ha) $stop; + if (5'd10 != 5'O12) $stop; + if (24'h29cbb8 != 24'o12345670) $stop; + if (24'h29__cbb8 != 24'o123456__70) $stop; + if (6'b111xxx !== 6'o7x) $stop; + if (6'b111??? !== 6'o7?) $stop; + if (6'b111zzz !== 6'o7z) $stop; + // + if (r_wide0 !== {32'haa111111, 32'hbb222222, 32'hcc333333, 32'hdd444444}) $stop; + if (r_wide1 !== {32'haa111111, 32'hbb222222}) $stop; + if (|{_guard1, _guard2, _guard3, _guard4, _guard5, _guard6}) begin + $write("Guard error %x %x %x %x %x\n", _guard1, _guard2, _guard3, _guard4, _guard5); + $stop; end - else if (_mode==1) begin - _mode<=2; - // - if (5'd10 != 5'b1010) $stop; - if (5'd10 != 5'd10) $stop; - if (5'd10 != 5'd1_0) $stop; - if (5'd10 != 5'ha) $stop; - if (5'd10 != 5'o12) $stop; - if (5'd10 != 5'o1_2) $stop; - if (5'd10 != 5'B 1010) $stop; - if (5'd10 != 5'B 10_10) $stop; - if (5'd10 != 5'D10) $stop; - if (5'd10 != 5'H a) $stop; - if (5'd10 != 5 'O 12) $stop; - if (24'h29cbb8 != 24'o12345670) $stop; - if (24'h29__cbb8 != 24'o123456__70) $stop; - if (6'b111xxx !== 6'o7x) $stop; - if (6'b111??? !== 6'o7?) $stop; - if (6'b111zzz !== 6'o7z) $stop; - // - if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; - if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; - if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin - $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v index 0c77528f2..f6959cae0 100644 --- a/test_regress/t/t_math_imm.v +++ b/test_regress/t/t_math_imm.v @@ -11,104 +11,108 @@ // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc = 0; - reg [7:0] crc; - reg [63:0] sum; + integer cyc; + initial cyc = 0; + reg [7:0] crc; + reg [63:0] sum; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] HighLogicImm; // From example of example.v - wire [63:0] LogicImm; // From example of example.v - wire [63:0] LowLogicImm; // From example of example.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] HighLogicImm; // From example of example.v + wire [63:0] LogicImm; // From example of example.v + wire [63:0] LowLogicImm; // From example of example.v + // End of automatics - wire [5:0] LowMaskSel_Top = crc[5:0]; - wire [5:0] LowMaskSel_Bot = crc[5:0]; - wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]}; - wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; + wire [5:0] LowMaskSel_Top = crc[5:0]; + wire [5:0] LowMaskSel_Bot = crc[5:0]; + wire [5:0] HighMaskSel_Top = crc[5:0] + {4'b0, crc[7:6]}; + wire [5:0] HighMaskSel_Bot = crc[5:0] + {4'b0, crc[7:6]}; - example example (/*AUTOINST*/ - // Outputs - .LogicImm (LogicImm[63:0]), - .LowLogicImm (LowLogicImm[63:0]), - .HighLogicImm (HighLogicImm[63:0]), - // Inputs - .LowMaskSel_Top (LowMaskSel_Top[5:0]), - .HighMaskSel_Top (HighMaskSel_Top[5:0]), - .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), - .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); + example example ( /*AUTOINST*/ + // Outputs + .LogicImm(LogicImm[63:0]), + .LowLogicImm(LowLogicImm[63:0]), + .HighLogicImm(HighLogicImm[63:0]), + // Inputs + .LowMaskSel_Top(LowMaskSel_Top[5:0]), + .HighMaskSel_Top(HighMaskSel_Top[5:0]), + .LowMaskSel_Bot(LowMaskSel_Bot[5:0]), + .HighMaskSel_Bot(HighMaskSel_Bot[5:0]) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc, - LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, - LowLogicImm, HighLogicImm, LogicImm); + $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc, LowMaskSel_Top, + HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, LowLogicImm, HighLogicImm, LogicImm); `endif - if (cyc==0) begin - // Single case - crc <= 8'h0; - sum <= 64'h0; - end - else if (cyc==1) begin - // Setup - crc <= 8'hed; - sum <= 64'h0; - end - else if (cyc<90) begin - sum <= {sum[62:0],sum[63]} ^ LogicImm; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); - if (crc !== 8'b00111000) $stop; - if (sum !== 64'h58743ffa61e41075) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 0) begin + // Single case + crc <= 8'h0; + sum <= 64'h0; + end + else if (cyc == 1) begin + // Setup + crc <= 8'hed; + sum <= 64'h0; + end + else if (cyc < 90) begin + sum <= {sum[62:0], sum[63]} ^ LogicImm; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); + if (crc !== 8'b00111000) $stop; + if (sum !== 64'h58743ffa61e41075) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module example (/*AUTOARG*/ - // Outputs - LogicImm, LowLogicImm, HighLogicImm, - // Inputs - LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot - ); +module example ( /*AUTOARG*/ + // Outputs + LogicImm, + LowLogicImm, + HighLogicImm, + // Inputs + LowMaskSel_Top, + HighMaskSel_Top, + LowMaskSel_Bot, + HighMaskSel_Bot +); - input [5:0] LowMaskSel_Top, HighMaskSel_Top; - input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; - output [63:0] LogicImm; + input [5:0] LowMaskSel_Top, HighMaskSel_Top; + input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; - output [63:0] LowLogicImm, HighLogicImm; + output [63:0] LowLogicImm, HighLogicImm; - wire [63:0] LowLogicImm, HighLogicImm; + wire [63:0] LowLogicImm, HighLogicImm; - /* verilator lint_off UNSIGNED */ - /* verilator lint_off CMPCONST */ - genvar i; - generate - for (i=0;i<64;i=i+1) begin : MaskVal - if (i >= 32) begin - assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); - assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); - end - else begin - assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); - assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); - end + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i = 0; i < 64; i = i + 1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); end - endgenerate - /* verilator lint_on UNSIGNED */ - /* verilator lint_on CMPCONST */ + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); + end + end + endgenerate + /* verilator lint_on UNSIGNED */ + /* verilator lint_on CMPCONST */ - assign LogicImm = LowLogicImm & HighLogicImm; + assign LogicImm = LowLogicImm & HighLogicImm; endmodule diff --git a/test_regress/t/t_math_imm2.v b/test_regress/t/t_math_imm2.v index 79ff28c2e..de668e9e3 100644 --- a/test_regress/t/t_math_imm2.v +++ b/test_regress/t/t_math_imm2.v @@ -11,33 +11,38 @@ // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. -module t_math_imm2 (/*AUTOARG*/ - // Outputs - LogicImm, LowLogicImm, HighLogicImm, - // Inputs - LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot - ); - input [4:0] LowMaskSel_Top, HighMaskSel_Top; - input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; - output [63:0] LogicImm; +module t_math_imm2 ( /*AUTOARG*/ + // Outputs + LogicImm, + LowLogicImm, + HighLogicImm, + // Inputs + LowMaskSel_Top, + HighMaskSel_Top, + LowMaskSel_Bot, + HighMaskSel_Bot +); + input [4:0] LowMaskSel_Top, HighMaskSel_Top; + input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; - output [63:0] LowLogicImm, HighLogicImm; + output [63:0] LowLogicImm, HighLogicImm; - /* verilator lint_off UNSIGNED */ - /* verilator lint_off CMPCONST */ - genvar i; - generate - for (i=0;i<64;i=i+1) begin : MaskVal - if (i >= 32) begin - assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); - assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); - end - else begin - assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); - assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); - end + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i = 0; i < 64; i = i + 1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); end - endgenerate + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); + end + end + endgenerate - assign LogicImm = LowLogicImm & HighLogicImm; + assign LogicImm = LowLogicImm & HighLogicImm; endmodule diff --git a/test_regress/t/t_math_insert_bound.v b/test_regress/t/t_math_insert_bound.v index 3937a3919..c162f520a 100644 --- a/test_regress/t/t_math_insert_bound.v +++ b/test_regress/t/t_math_insert_bound.v @@ -12,82 +12,81 @@ // state in the generated C++ struct!). -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 13; + integer cyc = 13; - // These need to be generated/consumed in this testbench so that - // they do not get pruned away when verilated - logic insert = '0; - logic [3:0] used, free; - logic [95:0] data; + // These need to be generated/consumed in this testbench so that + // they do not get pruned away when verilated + logic insert = '0; + logic [3:0] used, free; + logic [95:0] data; - always_ff @(posedge clk) begin - insert <= '1; - cyc <= cyc - 1; + always_ff @(posedge clk) begin + insert <= '1; + cyc <= cyc - 1; `ifdef TEST_VERBOSE - $write("used [4'd%2d], free [4'd%2d], data = [96'h%012x]\n", used, free, data); + $write("used [4'd%2d], free [4'd%2d], data = [96'h%012x]\n", used, free, data); `endif - if (used + free != 12) begin - $write("used [4'd%2d] + free [4'd%2d] != 4'd12\n", used, free); - $stop(); + if (used + free != 12) begin + $write("used [4'd%2d] + free [4'd%2d] != 4'd12\n", used, free); + $stop(); + end + if (used == 0) begin + $write("used [4'd%2d] was clobbered (should always be nonzero).\n", used); + $stop(); + end + if (cyc == 0) begin + if (used == 12 && free == 0 && data == 96'hFF) begin + $write("*-* All Finished *-*\n"); + $finish; end - if (used == 0) begin - $write("used [4'd%2d] was clobbered (should always be nonzero).\n", used); - $stop(); + else begin + $write("Test Failed! used/free/data had unexpected final value(s).\n"); + $stop(); end - if (cyc == 0) begin - if (used == 12 && free == 0 && data == 96'hFF) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - $write("Test Failed! used/free/data had unexpected final value(s).\n"); - $stop(); - end - end - end + end + end - dut dut_i( + dut dut_i ( .clk(clk), .insert(insert), .used(used), .free(free), .data(data) - ); + ); endmodule -module dut( - input logic clk, - input logic insert, - output logic [3:0] used, - output logic [3:0] free, - output logic [95:0] data - ); +module dut ( + input logic clk, + input logic insert, + output logic [3:0] used, + output logic [3:0] free, + output logic [95:0] data +); - // This declaration order matters -- the fact that d_data is *before* d_used/d_free - // means that with the existing bug, writes to d_data that extend beyond its length - // will overwrite other fields in the state struct -- basically an "unsafe writes" - // problem because the existing code wrote beyond the end of the array d_data. - logic [11:0][7:0] d_data = '1, d_data_next; - logic [3:0] d_used = 4'd1, d_free = 4'd11, d_used_next; - assign used = d_used; - assign free = d_free; - assign data = d_data; + // This declaration order matters -- the fact that d_data is *before* d_used/d_free + // means that with the existing bug, writes to d_data that extend beyond its length + // will overwrite other fields in the state struct -- basically an "unsafe writes" + // problem because the existing code wrote beyond the end of the array d_data. + logic [11:0][7:0] d_data = '1, d_data_next; + logic [3:0] d_used = 4'd1, d_free = 4'd11, d_used_next; + assign used = d_used; + assign free = d_free; + assign data = d_data; - always_ff @(posedge clk) begin - d_data <= d_data_next; - d_used <= d_used_next; - d_free <= 12 - d_used_next; - end + always_ff @(posedge clk) begin + d_data <= d_data_next; + d_used <= d_used_next; + d_free <= 12 - d_used_next; + end - always_comb begin + always_comb begin d_data_next = d_data; d_used_next = d_used; diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v index d93eb8950..7e59ebfc5 100644 --- a/test_regress/t/t_math_mul.v +++ b/test_regress/t/t_math_mul.v @@ -4,69 +4,74 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + wire [31:0] out1; + wire [31:0] out2; + sub sub ( + .in1(crc[15:0]), + .in2(crc[31:16]), + .out1(out1), + .out2 + ); - wire [31:0] out1; - wire [31:0] out2; - sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2); - - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n", $time, cyc, crc, sum, out1, out2); + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n", $time, cyc, crc, sum, out1, out2); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; - if (cyc==1) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; - end - else if (cyc==90) begin - if (sum !== 64'he396068aba3898a2) $stop; - end - else if (cyc==91) begin - end - else if (cyc==92) begin - end - else if (cyc==93) begin - end - else if (cyc==94) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {out2, out1}; + if (cyc == 1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc == 90) begin + if (sum !== 64'he396068aba3898a2) $stop; + end + else if (cyc == 91) begin + end + else if (cyc == 92) begin + end + else if (cyc == 93) begin + end + else if (cyc == 94) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub (/*AUTOARG*/ - // Outputs - out1, out2, - // Inputs - in1, in2 - ); +module sub ( /*AUTOARG*/ + // Outputs + out1, + out2, + // Inputs + in1, + in2 +); - input [15:0] in1; - input [15:0] in2; - output reg signed [31:0] out1; - output reg unsigned [31:0] out2; + input [15:0] in1; + input [15:0] in2; + output reg signed [31:0] out1; + output reg unsigned [31:0] out2; - always @* begin - // verilator lint_off WIDTH - out1 = $signed(in1) * $signed(in2); - out2 = $unsigned(in1) * $unsigned(in2); - // verilator lint_on WIDTH - end + always @* begin + // verilator lint_off WIDTH + out1 = $signed(in1) * $signed(in2); + out2 = $unsigned(in1) * $unsigned(in2); + // verilator lint_on WIDTH + end endmodule diff --git a/test_regress/t/t_math_pick.v b/test_regress/t/t_math_pick.v index 697166233..a00192b36 100644 --- a/test_regress/t/t_math_pick.v +++ b/test_regress/t/t_math_pick.v @@ -4,80 +4,78 @@ // SPDX-FileCopyrightText: 2013 // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire pick1 = crc[0]; - wire [13:0][1:0] data1 = crc[27+1:1]; - wire [3:0][2:0][1:0] data2 = crc[23+29:29]; + // Take CRC data and apply to testblock inputs + wire pick1 = crc[0]; + wire [13:0][1:0] data1 = crc[27+1:1]; + wire [3:0][2:0][1:0] data2 = crc[23+29:29]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [15:0] [1:0] datao; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [15:0][1:0] datao; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .datao (datao/*[15:0][1:0]*/), - // Inputs - .pick1 (pick1), - .data1 (data1/*[13:0][1:0]*/), - .data2 (data2/*[2:0][3:0][1:0]*/)); + Test test ( /*AUTOINST*/ + // Outputs + .datao(datao /*[15:0][1:0]*/), + // Inputs + .pick1(pick1), + .data1(data1 /*[13:0][1:0]*/), + .data2(data2 /*[2:0][3:0][1:0]*/) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, datao}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, datao}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h3ff4bf0e6407b281 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h3ff4bf0e6407b281 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test - ( - input logic pick1, - input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits - input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits - output logic [15:0] [1:0] datao // 16 x 2 = 32 bits - ); - // verilator lint_off WIDTH - always_comb datao[13: 0] // 28 bits - = (pick1) - ? {data1} // 28 bits - : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized - // verilator lint_on WIDTH - always_comb datao[15:14] = '0; +module Test ( + input logic pick1, + input logic [13:0][1:0] data1, // 14 x 2 = 28 bits + input logic [3:0][2:0][1:0] data2, // 4 x 3 x 2 = 24 bits + output logic [15:0][1:0] datao // 16 x 2 = 32 bits +); + // verilator lint_off WIDTH + always_comb + datao[13:0] // 28 bits + = (pick1) ? {data1} // 28 bits + : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized + // verilator lint_on WIDTH + always_comb datao[15:14] = '0; endmodule diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index 0fc280c26..72a617697 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -15,345 +15,346 @@ module t ( input clk ); - reg [66:0] a; - reg [66:0] b; + reg [66:0] a; + reg [66:0] b; - wire [15:0] aui = a[15:0]; - wire [34:0] auq = a[34:0]; - wire [66:0] auw = a[66:0]; - wire [15:0] bui = b[15:0]; - wire [34:0] buq = b[34:0]; - wire [66:0] buw = b[66:0]; - wire signed [15:0] asi = a[15:0]; - wire signed [34:0] asq = a[34:0]; - wire signed [66:0] asw = a[66:0]; - wire signed [15:0] bsi = b[15:0]; - wire signed [34:0] bsq = b[34:0]; - wire signed [66:0] bsw = b[66:0]; + wire [15:0] aui = a[15:0]; + wire [34:0] auq = a[34:0]; + wire [66:0] auw = a[66:0]; + wire [15:0] bui = b[15:0]; + wire [34:0] buq = b[34:0]; + wire [66:0] buw = b[66:0]; + wire signed [15:0] asi = a[15:0]; + wire signed [34:0] asq = a[34:0]; + wire signed [66:0] asw = a[66:0]; + wire signed [15:0] bsi = b[15:0]; + wire signed [34:0] bsq = b[34:0]; + wire signed [66:0] bsw = b[66:0]; - // verilator lint_off WIDTH - wire [66:0] shifted = 32'd2 ** b[20:0]; - wire [66:0] shifted_signed = 32'sd2 ** b[20:0]; + // verilator lint_off WIDTH + wire [66:0] shifted = 32'd2 ** b[20:0]; + wire [66:0] shifted_signed = 32'sd2 ** b[20:0]; - wire [15:0] uiii = aui ** bui; - wire [15:0] uiiq = aui ** buq; - wire [15:0] uiiw = aui ** buw; - wire [15:0] uiqi = auq ** bui; - wire [15:0] uiqq = auq ** buq; - wire [15:0] uiqw = auq ** buw; - wire [15:0] uiwi = auw ** bui; - wire [15:0] uiwq = auw ** buq; - wire [15:0] uiww = auw ** buw; - wire [34:0] uqii = aui ** bui; - wire [34:0] uqiq = aui ** buq; - wire [34:0] uqiw = aui ** buw; - wire [34:0] uqqi = auq ** bui; - wire [34:0] uqqq = auq ** buq; - wire [34:0] uqqw = auq ** buw; - wire [34:0] uqwi = auw ** bui; - wire [34:0] uqwq = auw ** buq; - wire [34:0] uqww = auw ** buw; - wire [66:0] uwii = aui ** bui; - wire [66:0] uwiq = aui ** buq; - wire [66:0] uwiw = aui ** buw; - wire [66:0] uwqi = auq ** bui; - wire [66:0] uwqq = auq ** buq; - wire [66:0] uwqw = auq ** buw; - wire [66:0] uwwi = auw ** bui; - wire [66:0] uwwq = auw ** buq; - wire [66:0] uwww = auw ** buw; - wire signed [15:0] siii = asi ** bsi; - wire signed [15:0] siiq = asi ** bsq; - wire signed [15:0] siiw = asi ** bsw; - wire signed [15:0] siqi = asq ** bsi; - wire signed [15:0] siqq = asq ** bsq; - wire signed [15:0] siqw = asq ** bsw; - wire signed [15:0] siwi = asw ** bsi; - wire signed [15:0] siwq = asw ** bsq; - wire signed [15:0] siww = asw ** bsw; - wire signed [34:0] sqii = asi ** bsi; - wire signed [34:0] sqiq = asi ** bsq; - wire signed [34:0] sqiw = asi ** bsw; - wire signed [34:0] sqqi = asq ** bsi; - wire signed [34:0] sqqq = asq ** bsq; - wire signed [34:0] sqqw = asq ** bsw; - wire signed [34:0] sqwi = asw ** bsi; - wire signed [34:0] sqwq = asw ** bsq; - wire signed [34:0] sqww = asw ** bsw; - wire signed [66:0] swii = asi ** bsi; - wire signed [66:0] swiq = asi ** bsq; - wire signed [66:0] swiw = asi ** bsw; - wire signed [66:0] swqi = asq ** bsi; - wire signed [66:0] swqq = asq ** bsq; - wire signed [66:0] swqw = asq ** bsw; - wire signed [66:0] swwi = asw ** bsi; - wire signed [66:0] swwq = asw ** bsq; - wire signed [66:0] swww = asw ** bsw; - // verilator lint_on WIDTH + wire [15:0] uiii = aui ** bui; + wire [15:0] uiiq = aui ** buq; + wire [15:0] uiiw = aui ** buw; + wire [15:0] uiqi = auq ** bui; + wire [15:0] uiqq = auq ** buq; + wire [15:0] uiqw = auq ** buw; + wire [15:0] uiwi = auw ** bui; + wire [15:0] uiwq = auw ** buq; + wire [15:0] uiww = auw ** buw; + wire [34:0] uqii = aui ** bui; + wire [34:0] uqiq = aui ** buq; + wire [34:0] uqiw = aui ** buw; + wire [34:0] uqqi = auq ** bui; + wire [34:0] uqqq = auq ** buq; + wire [34:0] uqqw = auq ** buw; + wire [34:0] uqwi = auw ** bui; + wire [34:0] uqwq = auw ** buq; + wire [34:0] uqww = auw ** buw; + wire [66:0] uwii = aui ** bui; + wire [66:0] uwiq = aui ** buq; + wire [66:0] uwiw = aui ** buw; + wire [66:0] uwqi = auq ** bui; + wire [66:0] uwqq = auq ** buq; + wire [66:0] uwqw = auq ** buw; + wire [66:0] uwwi = auw ** bui; + wire [66:0] uwwq = auw ** buq; + wire [66:0] uwww = auw ** buw; + wire signed [15:0] siii = asi ** bsi; + wire signed [15:0] siiq = asi ** bsq; + wire signed [15:0] siiw = asi ** bsw; + wire signed [15:0] siqi = asq ** bsi; + wire signed [15:0] siqq = asq ** bsq; + wire signed [15:0] siqw = asq ** bsw; + wire signed [15:0] siwi = asw ** bsi; + wire signed [15:0] siwq = asw ** bsq; + wire signed [15:0] siww = asw ** bsw; + wire signed [34:0] sqii = asi ** bsi; + wire signed [34:0] sqiq = asi ** bsq; + wire signed [34:0] sqiw = asi ** bsw; + wire signed [34:0] sqqi = asq ** bsi; + wire signed [34:0] sqqq = asq ** bsq; + wire signed [34:0] sqqw = asq ** bsw; + wire signed [34:0] sqwi = asw ** bsi; + wire signed [34:0] sqwq = asw ** bsq; + wire signed [34:0] sqww = asw ** bsw; + wire signed [66:0] swii = asi ** bsi; + wire signed [66:0] swiq = asi ** bsq; + wire signed [66:0] swiw = asi ** bsw; + wire signed [66:0] swqi = asq ** bsi; + wire signed [66:0] swqq = asq ** bsq; + wire signed [66:0] swqw = asq ** bsw; + wire signed [66:0] swwi = asw ** bsi; + wire signed [66:0] swwq = asw ** bsq; + wire signed [66:0] swww = asw ** bsw; + // verilator lint_on WIDTH - task checkpow(input [66:0] ures, input signed [66:0] sres); + task checkpow(input [66:0] ures, input signed [66:0] sres); `ifdef TEST_VERBOSE - $write("- lastcyc%0d: %0x**%0x = %0x (exp %0x)\n", last_cyc, a, b, uwww, ures); + $write("- lastcyc%0d: %0x**%0x = %0x (exp %0x)\n", last_cyc, a, b, uwww, ures); `endif - // verilator lint_off WIDTH - `checkh(uiii, ures[15:0]); - `checkh(uiiq, ures[15:0]); - `checkh(uiiw, ures[15:0]); - `checkh(uiqi, ures[15:0]); - `checkh(uiqq, ures[15:0]); - `checkh(uiqw, ures[15:0]); - `checkh(uiwi, ures[15:0]); - `checkh(uiwq, ures[15:0]); - `checkh(uiww, ures[15:0]); - `checkh(uqii, ures[15:0]); - `checkh(uqiq, ures[15:0]); - `checkh(uqiw, ures[15:0]); - `checkh(uqqi, ures[34:0]); - `checkh(uqqq, ures[34:0]); - `checkh(uqqw, ures[34:0]); - `checkh(uqwi, ures[34:0]); - `checkh(uqwq, ures[34:0]); - `checkh(uqww, ures[34:0]); - `checkh(uwii, ures[15:0]); - `checkh(uwiq, ures[15:0]); - `checkh(uwiw, ures[15:0]); - `checkh(uwqi, ures[34:0]); - `checkh(uwqq, ures[34:0]); - `checkh(uwqw, ures[34:0]); - `checkh(uwwi, ures[66:0]); - `checkh(uwwq, ures[66:0]); - `checkh(uwww, ures[66:0]); + // verilator lint_off WIDTH + `checkh(uiii, ures[15:0]); + `checkh(uiiq, ures[15:0]); + `checkh(uiiw, ures[15:0]); + `checkh(uiqi, ures[15:0]); + `checkh(uiqq, ures[15:0]); + `checkh(uiqw, ures[15:0]); + `checkh(uiwi, ures[15:0]); + `checkh(uiwq, ures[15:0]); + `checkh(uiww, ures[15:0]); + `checkh(uqii, ures[15:0]); + `checkh(uqiq, ures[15:0]); + `checkh(uqiw, ures[15:0]); + `checkh(uqqi, ures[34:0]); + `checkh(uqqq, ures[34:0]); + `checkh(uqqw, ures[34:0]); + `checkh(uqwi, ures[34:0]); + `checkh(uqwq, ures[34:0]); + `checkh(uqww, ures[34:0]); + `checkh(uwii, ures[15:0]); + `checkh(uwiq, ures[15:0]); + `checkh(uwiw, ures[15:0]); + `checkh(uwqi, ures[34:0]); + `checkh(uwqq, ures[34:0]); + `checkh(uwqw, ures[34:0]); + `checkh(uwwi, ures[66:0]); + `checkh(uwwq, ures[66:0]); + `checkh(uwww, ures[66:0]); `ifdef TEST_VERBOSE - $write("- lastcyc%0d: %0d**%0d = signed %0d (exp %0d)\n", last_cyc, asw, bsw, swww, sres); + $write("- lastcyc%0d: %0d**%0d = signed %0d (exp %0d)\n", last_cyc, asw, bsw, swww, sres); `endif - // verilator lint_off WIDTH - `checkh(siii, sres[15:0]); - `checkh(siiq, sres[15:0]); - `checkh(siiw, sres[15:0]); - `checkh(siqi, sres[15:0]); - `checkh(siqq, sres[15:0]); - `checkh(siqw, sres[15:0]); - `checkh(siwi, sres[15:0]); - `checkh(siwq, sres[15:0]); - `checkh(siww, sres[15:0]); - `checkh(sqii, sres[34:0]); - `checkh(sqiq, sres[34:0]); - `checkh(sqiw, sres[34:0]); - `checkh(sqqi, sres[34:0]); - `checkh(sqqq, sres[34:0]); - `checkh(sqqw, sres[34:0]); - `checkh(sqwi, sres[34:0]); - `checkh(sqwq, sres[34:0]); - `checkh(sqww, sres[34:0]); - `checkh(swii, sres[66:0]); - `checkh(swiq, sres[66:0]); - `checkh(swiw, sres[66:0]); - `checkh(swqi, sres[66:0]); - `checkh(swqq, sres[66:0]); - `checkh(swqw, sres[66:0]); - `checkh(swwi, sres[66:0]); - `checkh(swwq, sres[66:0]); - `checkh(swww, sres[66:0]); - // verilator lint_on WIDTH - endtask + // verilator lint_off WIDTH + `checkh(siii, sres[15:0]); + `checkh(siiq, sres[15:0]); + `checkh(siiw, sres[15:0]); + `checkh(siqi, sres[15:0]); + `checkh(siqq, sres[15:0]); + `checkh(siqw, sres[15:0]); + `checkh(siwi, sres[15:0]); + `checkh(siwq, sres[15:0]); + `checkh(siww, sres[15:0]); + `checkh(sqii, sres[34:0]); + `checkh(sqiq, sres[34:0]); + `checkh(sqiw, sres[34:0]); + `checkh(sqqi, sres[34:0]); + `checkh(sqqq, sres[34:0]); + `checkh(sqqw, sres[34:0]); + `checkh(sqwi, sres[34:0]); + `checkh(sqwq, sres[34:0]); + `checkh(sqww, sres[34:0]); + `checkh(swii, sres[66:0]); + `checkh(swiq, sres[66:0]); + `checkh(swiw, sres[66:0]); + `checkh(swqi, sres[66:0]); + `checkh(swqq, sres[66:0]); + `checkh(swqw, sres[66:0]); + `checkh(swwi, sres[66:0]); + `checkh(swwq, sres[66:0]); + `checkh(swww, sres[66:0]); + // verilator lint_on WIDTH + endtask -`define goldoneu(vu) \ - $write("gold: u %0x**%0x: %s = %0x\n", auw, buw, `STRINGIFY(vu), vu); -`define goldones(vs) \ - $write("gold: s %0d**%0d: %s = %0d\n", asw, bsw, `STRINGIFY(vs), vs); + `define goldoneu(vu) \ + $write("gold: u %0x**%0x: %s = %0x\n", auw, buw, `STRINGIFY(vu), vu); + `define goldones(vs) \ + $write("gold: s %0d**%0d: %s = %0d\n", asw, bsw, `STRINGIFY(vs), vs); - task golddump(); - // verilator lint_off WIDTH - `goldoneu(uiii); - `goldoneu(uiiq); - `goldoneu(uiiw); - `goldoneu(uiqi); - `goldoneu(uiqq); - `goldoneu(uiqw); - `goldoneu(uiwi); - `goldoneu(uiwq); - `goldoneu(uiww); - `goldoneu(uqii); - `goldoneu(uqiq); - `goldoneu(uqiw); - `goldoneu(uqqi); - `goldoneu(uqqq); - `goldoneu(uqqw); - `goldoneu(uqwi); - `goldoneu(uqwq); - `goldoneu(uqww); - `goldoneu(uwii); - `goldoneu(uwiq); - `goldoneu(uwiw); - `goldoneu(uwqi); - `goldoneu(uwqq); - `goldoneu(uwqw); - `goldoneu(uwwi); - `goldoneu(uwwq); - `goldoneu(uwww); - `goldones(siii); - `goldones(siiq); - `goldones(siiw); - `goldones(siqi); - `goldones(siqq); - `goldones(siqw); - `goldones(siwi); - `goldones(siwq); - `goldones(siww); - `goldones(sqii); - `goldones(sqiq); - `goldones(sqiw); - `goldones(sqqi); - `goldones(sqqq); - `goldones(sqqw); - `goldones(sqwi); - `goldones(sqwq); - `goldones(sqww); - `goldones(swii); - `goldones(swiq); - `goldones(swiw); - `goldones(swqi); - `goldones(swqq); - `goldones(swqw); - `goldones(swwi); - `goldones(swwq); - `goldones(swww); - // verilator lint_on WIDTH - endtask + task golddump(); + // verilator lint_off WIDTH + `goldoneu(uiii); + `goldoneu(uiiq); + `goldoneu(uiiw); + `goldoneu(uiqi); + `goldoneu(uiqq); + `goldoneu(uiqw); + `goldoneu(uiwi); + `goldoneu(uiwq); + `goldoneu(uiww); + `goldoneu(uqii); + `goldoneu(uqiq); + `goldoneu(uqiw); + `goldoneu(uqqi); + `goldoneu(uqqq); + `goldoneu(uqqw); + `goldoneu(uqwi); + `goldoneu(uqwq); + `goldoneu(uqww); + `goldoneu(uwii); + `goldoneu(uwiq); + `goldoneu(uwiw); + `goldoneu(uwqi); + `goldoneu(uwqq); + `goldoneu(uwqw); + `goldoneu(uwwi); + `goldoneu(uwwq); + `goldoneu(uwww); + `goldones(siii); + `goldones(siiq); + `goldones(siiw); + `goldones(siqi); + `goldones(siqq); + `goldones(siqw); + `goldones(siwi); + `goldones(siwq); + `goldones(siww); + `goldones(sqii); + `goldones(sqiq); + `goldones(sqiw); + `goldones(sqqi); + `goldones(sqqq); + `goldones(sqqw); + `goldones(sqwi); + `goldones(sqwq); + `goldones(sqww); + `goldones(swii); + `goldones(swiq); + `goldones(swiw); + `goldones(swqi); + `goldones(swqq); + `goldones(swqw); + `goldones(swwi); + `goldones(swwq); + `goldones(swww); + // verilator lint_on WIDTH + endtask - integer cyc; initial cyc=1; - integer last_cyc; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - last_cyc <= cyc; + // verilog_format: off + integer cyc; initial cyc=1; + integer last_cyc; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + last_cyc <= cyc; `ifdef TEST_VERBOSE - $write("- cyc%0d: %0x**%0x = sh %0x\n", cyc, a, b, shifted); + $write("- cyc%0d: %0x**%0x = sh %0x\n", cyc, a, b, shifted); `endif - // Constant versions - `checkh(67'h0 ** 21'h0, 67'h1); - `checkh(67'h1 ** 21'h0, 67'h1); - `checkh(67'h2 ** 21'h0, 67'h1); - `checkh(67'h0 ** 21'h1, 67'h0); - `checkh(67'h0 ** 21'h4, 67'h0); - `checkh(67'h1 ** 21'h31, 67'h1); - `checkh(67'h2 ** 21'h10, 67'h10000); - `checkh(67'd10 ** 21'h3, 67'h3e8); - `checkh(67'h3 ** 21'h7, 67'h88b); - `checkh(67'h0 ** 21'h0, 67'h1); - `checkh(67'sh0 ** 21'sh0, 67'sh1); - `checkh(67'h10 ** 21'h0, 67'h1); + // Constant versions + `checkh(67'h0 ** 21'h0, 67'h1); + `checkh(67'h1 ** 21'h0, 67'h1); + `checkh(67'h2 ** 21'h0, 67'h1); + `checkh(67'h0 ** 21'h1, 67'h0); + `checkh(67'h0 ** 21'h4, 67'h0); + `checkh(67'h1 ** 21'h31, 67'h1); + `checkh(67'h2 ** 21'h10, 67'h10000); + `checkh(67'd10 ** 21'h3, 67'h3e8); + `checkh(67'h3 ** 21'h7, 67'h88b); + `checkh(67'h0 ** 21'h0, 67'h1); + `checkh(67'sh0 ** 21'sh0, 67'sh1); + `checkh(67'h10 ** 21'h0, 67'h1); `ifndef VCS - `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); + `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); `endif - if (cyc==0) begin end - else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end - else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end - else if (cyc==3) begin a <= 67'h1; b <= 67'h31; end - else if (cyc==4) begin a <= 67'h2; b <= 67'h10; end - else if (cyc==5) begin a <= 67'd10; b <= 67'd3; end - else if (cyc==6) begin a <= 67'd3; b <= 67'd7; end - else if (cyc==7) begin a <= 67'h7ab3811219; b <= 67'ha6e30; end + if (cyc==0) begin end + else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end + else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end + else if (cyc==3) begin a <= 67'h1; b <= 67'h31; end + else if (cyc==4) begin a <= 67'h2; b <= 67'h10; end + else if (cyc==5) begin a <= 67'd10; b <= 67'd3; end + else if (cyc==6) begin a <= 67'd3; b <= 67'd7; end + else if (cyc==7) begin a <= 67'h7ab3811219; b <= 67'ha6e30; end - else if (cyc==10) begin a <= 67'h0; b <= 67'h0; end - else if (cyc==11) begin a <= 67'h0; b <= 67'h1; end - else if (cyc==12) begin a <= 67'h0; b <= -67'h1; end - else if (cyc==13) begin a <= 67'h0; b <= 67'h2; end - else if (cyc==14) begin a <= 67'h0; b <= 67'h3; end + else if (cyc==10) begin a <= 67'h0; b <= 67'h0; end + else if (cyc==11) begin a <= 67'h0; b <= 67'h1; end + else if (cyc==12) begin a <= 67'h0; b <= -67'h1; end + else if (cyc==13) begin a <= 67'h0; b <= 67'h2; end + else if (cyc==14) begin a <= 67'h0; b <= 67'h3; end - else if (cyc==20) begin a <= 67'h1; b <= 67'h0; end - else if (cyc==21) begin a <= 67'h1; b <= 67'h1; end - else if (cyc==22) begin a <= 67'h1; b <= -67'h1; end - else if (cyc==23) begin a <= 67'h1; b <= 67'h2; end - else if (cyc==24) begin a <= 67'h1; b <= 67'h3; end + else if (cyc==20) begin a <= 67'h1; b <= 67'h0; end + else if (cyc==21) begin a <= 67'h1; b <= 67'h1; end + else if (cyc==22) begin a <= 67'h1; b <= -67'h1; end + else if (cyc==23) begin a <= 67'h1; b <= 67'h2; end + else if (cyc==24) begin a <= 67'h1; b <= 67'h3; end - else if (cyc==30) begin a <= -67'h1; b <= 67'h0; end - else if (cyc==31) begin a <= -67'h1; b <= 67'h1; end - else if (cyc==32) begin a <= -67'h1; b <= -67'h1; end - else if (cyc==33) begin a <= -67'h1; b <= 67'h2; end - else if (cyc==34) begin a <= -67'h1; b <= 67'h3; end + else if (cyc==30) begin a <= -67'h1; b <= 67'h0; end + else if (cyc==31) begin a <= -67'h1; b <= 67'h1; end + else if (cyc==32) begin a <= -67'h1; b <= -67'h1; end + else if (cyc==33) begin a <= -67'h1; b <= 67'h2; end + else if (cyc==34) begin a <= -67'h1; b <= 67'h3; end - else if (cyc==40) begin a <= 67'h2; b <= 67'h0; end - else if (cyc==41) begin a <= 67'h2; b <= 67'h1; end - else if (cyc==42) begin a <= 67'h2; b <= -67'h1; end - else if (cyc==43) begin a <= 67'h2; b <= 67'h2; end - else if (cyc==44) begin a <= 67'h2; b <= 67'h3; end + else if (cyc==40) begin a <= 67'h2; b <= 67'h0; end + else if (cyc==41) begin a <= 67'h2; b <= 67'h1; end + else if (cyc==42) begin a <= 67'h2; b <= -67'h1; end + else if (cyc==43) begin a <= 67'h2; b <= 67'h2; end + else if (cyc==44) begin a <= 67'h2; b <= 67'h3; end - else if (cyc==50) begin a <= 67'h3; b <= 67'h0; end - else if (cyc==51) begin a <= 67'h3; b <= 67'h1; end - else if (cyc==52) begin a <= 67'h3; b <= -67'h1; end - else if (cyc==53) begin a <= 67'h3; b <= 67'h2; end - else if (cyc==54) begin a <= 67'h3; b <= 67'h3; end + else if (cyc==50) begin a <= 67'h3; b <= 67'h0; end + else if (cyc==51) begin a <= 67'h3; b <= 67'h1; end + else if (cyc==52) begin a <= 67'h3; b <= -67'h1; end + else if (cyc==53) begin a <= 67'h3; b <= 67'h2; end + else if (cyc==54) begin a <= 67'h3; b <= 67'h3; end - else if (cyc==60) begin a <= -67'h2; b <= 67'h0; end - else if (cyc==61) begin a <= -67'h2; b <= 67'h1; end - else if (cyc==62) begin a <= -67'h2; b <= -67'h1; end - else if (cyc==63) begin a <= -67'h2; b <= 67'h2; end - else if (cyc==64) begin a <= -67'h2; b <= 67'h3; end + else if (cyc==60) begin a <= -67'h2; b <= 67'h0; end + else if (cyc==61) begin a <= -67'h2; b <= 67'h1; end + else if (cyc==62) begin a <= -67'h2; b <= -67'h1; end + else if (cyc==63) begin a <= -67'h2; b <= 67'h2; end + else if (cyc==64) begin a <= -67'h2; b <= 67'h3; end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; end - // IEEE: - // op1 < -1 op1 == -1 op1 == 0 op1 == 1 op1 > 1 - // op2 is positive op1 ** op2 op2 is odd -> -1, even -> 1 0 1 op1 ** op2 - // op2 is zero 1 1 1 1 1 - // op2 is negative 0 op2 is odd -> -1, even -> 1 'x 1 0 - case (last_cyc) - 32'd10: checkpow(67'h1, 67'h1); // 0 ** 0 -> 1 - 32'd11: checkpow(67'h0, 67'h0); // 0 ** 1 -> 1 - 32'd12: ; // 0 ** -1 -> x - 32'd13: checkpow(67'h0, 67'h0); // 0 ** 2 -> 0 - 32'd14: checkpow(67'h0, 67'h0); // 0 ** 3 -> 0 + end + // IEEE: + // op1 < -1 op1 == -1 op1 == 0 op1 == 1 op1 > 1 + // op2 is positive op1 ** op2 op2 is odd -> -1, even -> 1 0 1 op1 ** op2 + // op2 is zero 1 1 1 1 1 + // op2 is negative 0 op2 is odd -> -1, even -> 1 'x 1 0 + case (last_cyc) + 32'd10: checkpow(67'h1, 67'h1); // 0 ** 0 -> 1 + 32'd11: checkpow(67'h0, 67'h0); // 0 ** 1 -> 1 + 32'd12: ; // 0 ** -1 -> x + 32'd13: checkpow(67'h0, 67'h0); // 0 ** 2 -> 0 + 32'd14: checkpow(67'h0, 67'h0); // 0 ** 3 -> 0 - 32'd20: checkpow(67'h1, 67'h1); // 1 ** 0 -> 1 - 32'd21: checkpow(67'h1, 67'h1); // 1 ** 1 -> 1 + 32'd20: checkpow(67'h1, 67'h1); // 1 ** 0 -> 1 + 32'd21: checkpow(67'h1, 67'h1); // 1 ** 1 -> 1 `ifndef IVERILOG - 32'd22: checkpow(67'h1, 67'h1); // 1 ** -1 -> 1 + 32'd22: checkpow(67'h1, 67'h1); // 1 ** -1 -> 1 `endif - 32'd23: checkpow(67'h1, 67'h1); // 1 ** 2 -> 1 - 32'd24: checkpow(67'h1, 67'h1); // 1 ** 3 -> 1 + 32'd23: checkpow(67'h1, 67'h1); // 1 ** 2 -> 1 + 32'd24: checkpow(67'h1, 67'h1); // 1 ** 3 -> 1 - 32'd30: checkpow(67'h1, 67'h1); // -1 ** 0 -> 1 - 32'd31: checkpow(-67'h1, -67'h1); // -1 ** 1 -> -1 if odd else 1 - 32'd32: golddump(); // -1 ** -1 SEE GOLDEN - 32'd33: golddump(); // -1 ** 2 SEE GOLDEN - 32'd34: golddump(); // -1 ** 3 SEE GOLDEN + 32'd30: checkpow(67'h1, 67'h1); // -1 ** 0 -> 1 + 32'd31: checkpow(-67'h1, -67'h1); // -1 ** 1 -> -1 if odd else 1 + 32'd32: golddump(); // -1 ** -1 SEE GOLDEN + 32'd33: golddump(); // -1 ** 2 SEE GOLDEN + 32'd34: golddump(); // -1 ** 3 SEE GOLDEN - 32'd40: checkpow(67'h1, 67'h1); // 2 ** 0 -> 1 - 32'd41: checkpow(67'h2, 67'h2); // 2 ** 1 - 32'd42: checkpow(67'h0, 67'h0); // 2 ** -1 -> 0 - 32'd43: checkpow(67'h4, 67'h4); // 2 ** 2 - 32'd44: checkpow(67'h8, 67'h8); // 2 ** 3 + 32'd40: checkpow(67'h1, 67'h1); // 2 ** 0 -> 1 + 32'd41: checkpow(67'h2, 67'h2); // 2 ** 1 + 32'd42: checkpow(67'h0, 67'h0); // 2 ** -1 -> 0 + 32'd43: checkpow(67'h4, 67'h4); // 2 ** 2 + 32'd44: checkpow(67'h8, 67'h8); // 2 ** 3 - 32'd50: checkpow(67'h1, 67'h1); // 3 ** 0 -> 0 - 32'd51: checkpow(67'h3, 67'h3); // 3 ** 1 - 32'd52: golddump(); // 3 ** -1 -> 0 (if negative gives 0) - 32'd53: checkpow(67'h9, 67'h9); // 3 ** 2 - 32'd54: checkpow(67'h1b, 67'h1b); // 3 ** 3 + 32'd50: checkpow(67'h1, 67'h1); // 3 ** 0 -> 0 + 32'd51: checkpow(67'h3, 67'h3); // 3 ** 1 + 32'd52: golddump(); // 3 ** -1 -> 0 (if negative gives 0) + 32'd53: checkpow(67'h9, 67'h9); // 3 ** 2 + 32'd54: checkpow(67'h1b, 67'h1b); // 3 ** 3 - 32'd60: checkpow(67'h1, 67'h1); // -2 ** 0 -> 1 - 32'd61: golddump(); // -2 ** 1 SEE GOLDEN - 32'd62: golddump(); // -2 ** -1 SEE GOLDEN - 32'd63: golddump(); // -2 ** 2 SEE GOLDEN - 32'd64: golddump(); // -2 ** 3 SEE GOLDEN - default: ; - endcase - case (cyc) - 32'd00: ; - 32'd01: ; - 32'd02: `checkh(shifted, 67'h0000000000000001); - 32'd03: `checkh(shifted, 67'h0000000000000008); - 32'd04: `checkh(shifted, 67'h0002000000000000); - 32'd05: `checkh(shifted, 67'h0000000000010000); - 32'd06: `checkh(shifted, 67'h0000000000000008); - 32'd07: `checkh(shifted, 67'h0000000000000080); - 32'd08: `checkh(shifted, 67'h0000000000000000); - 32'd09: `checkh(shifted, 67'h0000000000000000); - default: ; - endcase - `checkh(shifted_signed, shifted); - end + 32'd60: checkpow(67'h1, 67'h1); // -2 ** 0 -> 1 + 32'd61: golddump(); // -2 ** 1 SEE GOLDEN + 32'd62: golddump(); // -2 ** -1 SEE GOLDEN + 32'd63: golddump(); // -2 ** 2 SEE GOLDEN + 32'd64: golddump(); // -2 ** 3 SEE GOLDEN + default: ; + endcase + case (cyc) + 32'd00: ; + 32'd01: ; + 32'd02: `checkh(shifted, 67'h0000000000000001); + 32'd03: `checkh(shifted, 67'h0000000000000008); + 32'd04: `checkh(shifted, 67'h0002000000000000); + 32'd05: `checkh(shifted, 67'h0000000000010000); + 32'd06: `checkh(shifted, 67'h0000000000000008); + 32'd07: `checkh(shifted, 67'h0000000000000080); + 32'd08: `checkh(shifted, 67'h0000000000000000); + 32'd09: `checkh(shifted, 67'h0000000000000000); + default: ; + endcase + `checkh(shifted_signed, shifted); + end endmodule diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v index d5315a1da..12ef6dfb8 100644 --- a/test_regress/t/t_math_pow2.v +++ b/test_regress/t/t_math_pow2.v @@ -4,48 +4,46 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Aggregate outputs into a single result vector - //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows - wire [3:0] pow4b = crc[7:4] ** crc[3:0]; - wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift - wire [63:0] result = {pow2, 28'h0, pow4b}; + // Aggregate outputs into a single result vector + //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows + wire [3:0] pow4b = crc[7:4] ** crc[3:0]; + wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift + wire [63:0] result = {pow2, 28'h0, pow4b}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h056ea1c5a63aff6a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h056ea1c5a63aff6a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v index db40cc664..b591618b3 100644 --- a/test_regress/t/t_math_pow3.v +++ b/test_regress/t/t_math_pow3.v @@ -4,80 +4,83 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) +// verilog_format: on module t; - bit fail; + bit fail; - // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. + // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. - initial begin - // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 - $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); - // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) - $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); - // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 - $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); - // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 - $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); - // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 - $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); - $display("\n"); + // verilog_format: off + initial begin + // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 + $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); + // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) + $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); + // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 + $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); + $display("\n"); - `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); - `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 - `checkh( (-4'd1 ** -4'd2), 4'h1); - `checkh( (4'd15 ** 4'd14), 4'h1); - `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); + `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); + `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 + `checkh( (-4'd1 ** -4'd2), 4'h1); + `checkh( (4'd15 ** 4'd14), 4'h1); + `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); - `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) - `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 - `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 - `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 - `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 - `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) - `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) - `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) - `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) + `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) + `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) - `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b - `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 - `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 - `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 - `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 - `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) - `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) - `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) - `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) + `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b + `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) - `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 - `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug - `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 - `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 + `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug + `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 // `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug - `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 - `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug - `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 + `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug - if (fail) $stop; - else $write("*-* All Finished *-*\n"); - $finish; - end + if (fail) $stop; + else $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v index 4052cfb62..122a92765 100644 --- a/test_regress/t/t_math_pow4.v +++ b/test_regress/t/t_math_pow4.v @@ -4,47 +4,49 @@ // SPDX-FileCopyrightText: 2014 Clifford Wolf // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - wire [31:0] y; - reg a; - test004 sub (/*AUTOINST*/ - // Outputs - .y (y[31:0]), - // Inputs - .a (a)); + wire [31:0] y; + reg a; + test004 sub ( /*AUTOINST*/ + // Outputs + .y(y[31:0]), + // Inputs + .a(a) + ); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y); + $write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y); `endif - cyc <= cyc + 1; - if (cyc==0) begin - a <= 0; - end - else if (cyc==1) begin - a <= 1; - if (y != 32'h0) $stop; - end - else if (cyc==2) begin - if (y != 32'h010000ff) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 0) begin + a <= 0; + end + else if (cyc == 1) begin + a <= 1; + if (y != 32'h0) $stop; + end + else if (cyc == 2) begin + if (y != 32'h010000ff) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module test004(a, y); +module test004 ( + a, + y +); input a; output [31:0] y; @@ -52,15 +54,15 @@ module test004(a, y); wire [7:0] y1; wire [7:0] y2; wire [7:0] y3; - assign y = {y0,y1,y2,y3}; + assign y = {y0, y1, y2, y3}; - localparam [7:0] V0 = +8'sd1 ** -8'sd2; //'h01 - localparam [7:0] V1 = +8'sd2 ** -8'sd2; //'h00 - localparam [7:0] V2 = -8'sd2 ** -8'sd3; //'h00 - localparam [7:0] V3 = -8'sd1 ** -8'sd3; //'hff + localparam [7:0] V0 = +8'sd1 ** -8'sd2; //'h01 + localparam [7:0] V1 = +8'sd2 ** -8'sd2; //'h00 + localparam [7:0] V2 = -8'sd2 ** -8'sd3; //'h00 + localparam [7:0] V3 = -8'sd1 ** -8'sd3; //'hff localparam [7:0] ZERO = 0; - initial $display("V0=%x V1=%x V2=%x V3=%x", V0,V1,V2,V3); + initial $display("V0=%x V1=%x V2=%x V3=%x", V0, V1, V2, V3); assign y0 = a ? V0 : ZERO; assign y1 = a ? V1 : ZERO; diff --git a/test_regress/t/t_math_pow5.v b/test_regress/t/t_math_pow5.v index 861d12176..9955be6e7 100644 --- a/test_regress/t/t_math_pow5.v +++ b/test_regress/t/t_math_pow5.v @@ -4,71 +4,69 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [67:0] q; + reg signed [67:0] qs; - reg [67:0] q; - reg signed [67:0] qs; + initial begin + q = 68'he_12345678_9abcdef0 ** 68'h3; + if (q != 68'hcee3cb96ce96cf000) $stop; + // + q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345; + if (q != 68'h0) $stop; + // + qs = 68'she_12345678_9abcdef0 ** 68'sh3; + if (qs != 68'shcee3cb96ce96cf000) $stop; + // + qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345; + if (qs != 68'h0) $stop; + end - initial begin - q = 68'he_12345678_9abcdef0 ** 68'h3; - if (q != 68'hcee3cb96ce96cf000) $stop; - // - q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345; - if (q != 68'h0) $stop; - // - qs = 68'she_12345678_9abcdef0 ** 68'sh3; - if (qs != 68'shcee3cb96ce96cf000) $stop; - // - qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345; - if (qs != 68'h0) $stop; - end + reg [67:0] left; + reg [67:0] right; - reg [67:0] left; - reg [67:0] right; + wire [67:0] outu = left ** right; + wire signed [67:0] outs = $signed(left) ** $signed(right); - wire [67:0] outu = left ** right; - wire signed [67:0] outs = $signed(left) ** $signed(right); - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); + $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); `endif - if (cyc==1) begin - left <= 68'h1; - right <= '0; - end - if (cyc==2) begin - if (outu != 68'h1) $stop; - if (outs != 68'h1) $stop; - end - if (cyc==3) begin - left <= 68'he_12345678_9abcdef0; - right <= 68'h3; - end - if (cyc==4) begin - if (outu != 68'hcee3cb96ce96cf000) $stop; - if (outs != 68'hcee3cb96ce96cf000) $stop; - end - if (cyc==5) begin - left <= 68'he_12345678_9abcdef0; - right <= 68'h5_6789abcd_ef012345; - end - if (cyc==6) begin - if (outu != 68'h0) $stop; - if (outs != 68'h0) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 1) begin + left <= 68'h1; + right <= '0; end - end + if (cyc == 2) begin + if (outu != 68'h1) $stop; + if (outs != 68'h1) $stop; + end + if (cyc == 3) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h3; + end + if (cyc == 4) begin + if (outu != 68'hcee3cb96ce96cf000) $stop; + if (outs != 68'hcee3cb96ce96cf000) $stop; + end + if (cyc == 5) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h5_6789abcd_ef012345; + end + if (cyc == 6) begin + if (outu != 68'h0) $stop; + if (outs != 68'h0) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_pow6.v b/test_regress/t/t_math_pow6.v index 37c85e770..f78afd1d8 100644 --- a/test_regress/t/t_math_pow6.v +++ b/test_regress/t/t_math_pow6.v @@ -5,43 +5,43 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, - x33, w30, x30, - // Inputs - a, a40, a70 - ); + // Outputs + i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, + x33, w30, x30, + // Inputs + a, a40, a70 + ); - input [3:0] a; - input [39:0] a40; - input [69:0] a70; + input [3:0] a; + input [39:0] a40; + input [69:0] a70; - // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() - // verilator lint_off WIDTH - output [3:0] i65 = 65'd3 ** a; // IWI - output [3:0] j65 = a ** 65'd3; // IIW - output [3:0] i33 = 33'd3 ** a; // QQI - output [3:0] j33 = a ** 33'd3; // IIQ - output [3:0] i30 = 30'd3 ** a; // III - output [3:0] j30 = a ** 30'd3; // III + // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() + // verilator lint_off WIDTH + output [3:0] i65 = 65'd3 ** a; // IWI + output [3:0] j65 = a ** 65'd3; // IIW + output [3:0] i33 = 33'd3 ** a; // QQI + output [3:0] j33 = a ** 33'd3; // IIQ + output [3:0] i30 = 30'd3 ** a; // III + output [3:0] j30 = a ** 30'd3; // III - output [39:0] q65 = 65'd3 ** a40; // WWQ - output [39:0] r65 = a40 ** 65'd3; // WWQ - output [39:0] q33 = 33'd3 ** a40; // QQQ - output [39:0] r33 = a40 ** 33'd3; // QQQ - output [39:0] q30 = 30'd3 ** a40; // QQI - output [39:0] r30 = a40 ** 30'd3; // QQI + output [39:0] q65 = 65'd3 ** a40; // WWQ + output [39:0] r65 = a40 ** 65'd3; // WWQ + output [39:0] q33 = 33'd3 ** a40; // QQQ + output [39:0] r33 = a40 ** 33'd3; // QQQ + output [39:0] q30 = 30'd3 ** a40; // QQI + output [39:0] r30 = a40 ** 30'd3; // QQI - output [69:0] w65 = 65'd3 ** a70; // WWW - output [69:0] x65 = a70 ** 65'd3; // WWW - output [69:0] w33 = 33'd3 ** a70; // WWW - output [69:0] x33 = a70 ** 33'd3; // WWW - output [69:0] w30 = 30'd3 ** a70; // WWW - output [69:0] x30 = a70 ** 30'd3; // WWW - // verilator lint_on WIDTH + output [69:0] w65 = 65'd3 ** a70; // WWW + output [69:0] x65 = a70 ** 65'd3; // WWW + output [69:0] w33 = 33'd3 ** a70; // WWW + output [69:0] x33 = a70 ** 33'd3; // WWW + output [69:0] w30 = 30'd3 ** a70; // WWW + output [69:0] x30 = a70 ** 30'd3; // WWW + // verilator lint_on WIDTH - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_pow7.v b/test_regress/t/t_math_pow7.v index d94e53835..ffdeacf07 100644 --- a/test_regress/t/t_math_pow7.v +++ b/test_regress/t/t_math_pow7.v @@ -11,17 +11,17 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t (/*AUTOARG*/ - // Outputs - out_data - ); +module t ( /*AUTOARG*/ + // Outputs + out_data +); - output [11:0] out_data; - wire [11:0] out_data; - wire [11:0] a; - wire [2:0] b; - assign a = 12'h000 ** { b }; - assign b = 3'b0; - assign out_data = a; + output [11:0] out_data; + wire [11:0] out_data; + wire [11:0] a; + wire [2:0] b; + assign a = 12'h000 ** {b}; + assign b = 3'b0; + assign out_data = a; endmodule diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v index 1d0815f15..c00e74f3e 100644 --- a/test_regress/t/t_math_precedence.v +++ b/test_regress/t/t_math_precedence.v @@ -4,159 +4,163 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [1:0] a = crc[1 +: 2]; - wire [1:0] b = crc[3 +: 2]; - wire [1:0] c = crc[5 +: 2]; - wire [1:0] d = crc[7 +: 2]; - wire [1:0] e = crc[9 +: 2]; - wire [1:0] f = crc[11+: 2]; - wire [1:0] g = crc[13+: 2]; + wire [1:0] a = crc[1+:2]; + wire [1:0] b = crc[3+:2]; + wire [1:0] c = crc[5+:2]; + wire [1:0] d = crc[7+:2]; + wire [1:0] e = crc[9+:2]; + wire [1:0] f = crc[11+:2]; + wire [1:0] g = crc[13+:2]; - // left () [] :: . - // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) - // left ** - // left * / % - // left + - (binary) - // left << >> <<< >>> - // left < <= > >= inside dist - // left == != === !== ==? !=? - // left & (binary) - // left ^ ~^ ^~ (binary) - // left | (binary) - // left && - // left || - // left ? : - // right -> - // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= - // {} {{}} concatenation + // left () [] :: . + // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) + // left ** + // left * / % + // left + - (binary) + // left << >> <<< >>> + // left < <= > >= inside dist + // left == != === !== ==? !=? + // left & (binary) + // left ^ ~^ ^~ (binary) + // left | (binary) + // left && + // left || + // left ? : + // right -> + // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= + // {} {{}} concatenation - wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; - wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; - wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; - wire [1:0] enz = (e==2'b0) ? 2'b11 : e; + wire [1:0] bnz = (b == 2'b0) ? 2'b11 : b; + wire [1:0] cnz = (c == 2'b0) ? 2'b11 : c; + wire [1:0] dnz = (d == 2'b0) ? 2'b11 : d; + wire [1:0] enz = (e == 2'b0) ? 2'b11 : e; - // verilator lint_off WIDTH - // Do a few in each group - wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse - wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse - wire [1:0] o3 = a ** b ** c; // Some simulators botch this + // verilator lint_off WIDTH + // Do a few in each group + wire [1:0] o1 = ~a; // Can't get more than one reduction to parse + wire [1:0] o2 = ^b; // Can't get more than one reduction to parse + wire [1:0] o3 = a ** b ** c; // Some simulators botch this - wire [1:0] o4 = a * b / cnz % dnz * enz; - wire [1:0] o5 = a + b - c + d; - wire [1:0] o6 = a << b >> c <<< d >>> e <<< f; - wire [1:0] o7 = a < b <= c; - wire [1:0] o8 = a == b != c === d == e; - wire [1:0] o9 = a & b & c; - wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a; - wire [1:0] o11 = a | b | c; - wire [1:0] o12 = a && b && c; - wire [1:0] o13 = a || b || c; - wire [1:0] o14 = a ? b ? c : d : e; - wire [1:0] o15 = a ? b : c ? d : e; + wire [1:0] o4 = a * b / cnz % dnz * enz; + wire [1:0] o5 = a + b - c + d; + wire [1:0] o6 = a << b >> c <<< d >>> e <<< f; + wire [1:0] o7 = a < b <= c; + wire [1:0] o8 = a == b != c === d == e; + wire [1:0] o9 = a & b & c; + wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a; + wire [1:0] o11 = a | b | c; + wire [1:0] o12 = a && b && c; + wire [1:0] o13 = a || b || c; + wire [1:0] o14 = a ? b ? c : d : e; + wire [1:0] o15 = a ? b : c ? d : e; - // Now cross each pair of groups - wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this - wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this - wire [1:0] x3 = a + b * c + d; - wire [1:0] x4 = a + b << c + d; - wire [1:0] x5 = a == b << c == d; - wire [1:0] x6 = a & b << c & d; - wire [1:0] x7 = a ^ b & c ^ d; - wire [1:0] x8 = a | b ^ c | d; - wire [1:0] x9 = a && b | c && d; - wire [1:0] x10 = a || b && c || d; - wire [1:0] x11 = a ? b || c : d ? e : f; + // Now cross each pair of groups + wire [1:0] x1 = ~a ** ~b ** ~c; // Some simulators botch this + wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this + wire [1:0] x3 = a + b * c + d; + wire [1:0] x4 = a + b << c + d; + wire [1:0] x5 = a == b << c == d; + wire [1:0] x6 = a & b << c & d; + wire [1:0] x7 = a ^ b & c ^ d; + wire [1:0] x8 = a | b ^ c | d; + wire [1:0] x9 = a && b | c && d; + wire [1:0] x10 = a || b && c || d; + wire [1:0] x11 = a ? b || c : d ? e : f; - // verilator lint_on WIDTH + // verilator lint_on WIDTH - function [1:0] pow (input [1:0] x, input [1:0] y); - casez ({x,y}) - 4'b00_??: pow = 2'b00; - 4'b01_00: pow = 2'b01; - 4'b01_01: pow = 2'b01; - 4'b01_10: pow = 2'b01; - 4'b01_11: pow = 2'b01; - 4'b10_00: pow = 2'b01; - 4'b10_01: pow = 2'b10; - 4'b10_10: pow = 2'b00; - 4'b10_11: pow = 2'b00; - 4'b11_00: pow = 2'b01; - 4'b11_01: pow = 2'b11; - 4'b11_10: pow = 2'b01; - 4'b11_11: pow = 2'b11; - endcase - endfunction + function [1:0] pow(input [1:0] x, input [1:0] y); + casez ({ + x, y + }) + 4'b00_??: pow = 2'b00; + 4'b01_00: pow = 2'b01; + 4'b01_01: pow = 2'b01; + 4'b01_10: pow = 2'b01; + 4'b01_11: pow = 2'b01; + 4'b10_00: pow = 2'b01; + 4'b10_01: pow = 2'b10; + 4'b10_10: pow = 2'b00; + 4'b10_11: pow = 2'b00; + 4'b11_00: pow = 2'b01; + 4'b11_01: pow = 2'b11; + 4'b11_10: pow = 2'b01; + 4'b11_11: pow = 2'b11; + endcase + endfunction - // Aggregate outputs into a single result vector - wire [63:0] result = {12'h0, - x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, - o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; + // Aggregate outputs into a single result vector + // verilog_format: off + wire [63:0] result = {12'h0, + x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, + o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; + // verilog_format: on - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x ", $time, cyc, crc, result); - $write(" %b",o1); - $write(" %b",o2); - $write(" %b",o3); - $write(" %b",o4); - $write(" %b",o5); - $write(" %b",o6); - $write(" %b",o7); - $write(" %b",o8); - $write(" %b",o9); - $write(" %b",o10); - $write(" %b",o11); - $write(" %b",o12); - $write(" %b",o13); - $write(" %b",o14); - $write(" %b",o15); - // Now cross each pair of groups - $write(" %b",x1); - $write(" %b",x2); - $write(" %b",x3); - $write(" %b",x4); - $write(" %b",x5); - $write(" %b",x6); - $write(" %b",x7); - $write(" %b",x8); - $write(" %b",x9); - $write(" %b",x10); - $write(" %b",x11); - $write("\n"); + $write("[%0t] cyc==%0d crc=%x result=%x ", $time, cyc, crc, result); + $write(" %b", o1); + $write(" %b", o2); + $write(" %b", o3); + $write(" %b", o4); + $write(" %b", o5); + $write(" %b", o6); + $write(" %b", o7); + $write(" %b", o8); + $write(" %b", o9); + $write(" %b", o10); + $write(" %b", o11); + $write(" %b", o12); + $write(" %b", o13); + $write(" %b", o14); + $write(" %b", o15); + // Now cross each pair of groups + $write(" %b", x1); + $write(" %b", x2); + $write(" %b", x3); + $write(" %b", x4); + $write(" %b", x5); + $write(" %b", x6); + $write(" %b", x7); + $write(" %b", x8); + $write(" %b", x9); + $write(" %b", x10); + $write(" %b", x11); + $write("\n"); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h2756ea365ec7520e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h2756ea365ec7520e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v index 39892dbd9..0da8395b9 100644 --- a/test_regress/t/t_math_real.v +++ b/test_regress/t/t_math_real.v @@ -6,320 +6,329 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define stop $stop `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer i; - reg [63:0] b; - reg [47:0] i48; - reg signed [47:0] is48; - reg [31:0] ci32; - reg signed [31:0] cis32; - reg [47:0] ci48; - reg signed [47:0] cis48; - reg [63:0] ci64; - reg signed [63:0] cis64; - reg [95:0] ci96; - reg signed [95:0] cis96; - real r, r2; - integer cyc = 0; - string s; + integer i; + reg [63:0] b; + reg [47:0] i48; + reg signed [47:0] is48; + reg [31:0] ci32; + reg signed [31:0] cis32; + reg [47:0] ci48; + reg signed [47:0] cis48; + reg [63:0] ci64; + reg signed [63:0] cis64; + reg [95:0] ci96; + reg signed [95:0] cis96; + real r, r2; + integer cyc = 0; + string s; - realtime uninit; - initial if (uninit != 0.0) $stop; + realtime uninit; + initial if (uninit != 0.0) $stop; - localparam int TWENTY = 20; - localparam real TWENDIV = $ceil((real'(TWENTY)-14.0)/2.0); + localparam int TWENTY = 20; + localparam real TWENDIV = $ceil((real'(TWENTY) - 14.0) / 2.0); - sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); + sub_cast_bug374 sub ( + .cyc5(cyc[4:0]), + .* + ); - initial begin - if (1_00_0.0_1 != 1000.01) $stop; - // rtoi truncates - if ($rtoi(36.7) != 36) $stop; - if ($rtoi(36.5) != 36) $stop; - if ($rtoi(36.4) != 36) $stop; - // casting rounds - if ((integer '(36.7)) != 37) $stop; - if ((integer '(36.5)) != 37) $stop; - if ((integer '(36.4)) != 36) $stop; - // assignment rounds - // verilator lint_off REALCVT - i = 36.7; if (i != 37) $stop; - i = 36.5; if (i != 37) $stop; - i = 36.4; if (i != 36) $stop; - r = 10'd38; if (r!=38.0) $stop; - // verilator lint_on REALCVT - // operators - if ((-(1.5)) != -1.5) $stop; - if ((+(1.5)) != 1.5) $stop; - if (((1.5)+(1.25)) != 2.75) $stop; - if (((1.5)-(1.25)) != 0.25) $stop; - if (((1.5)*(1.25)) != 1.875) $stop; - if (((1.5)/(1.25)) != 1.2) $stop; - // - if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 - if (((1.5)!=(2)) != 1'b1) $stop; - if (((1.5)> (2)) != 1'b0) $stop; - if (((1.5)>=(2)) != 1'b0) $stop; - if (((1.5)< (2)) != 1'b1) $stop; - if (((1.5)<=(2)) != 1'b1) $stop; - if (((1.5)==(1.5)) != 1'b1) $stop; - if (((1.5)!=(1.5)) != 1'b0) $stop; - if (((1.5)> (1.5)) != 1'b0) $stop; - if (((1.5)>=(1.5)) != 1'b1) $stop; - if (((1.5)< (1.5)) != 1'b0) $stop; - if (((1.5)<=(1.5)) != 1'b1) $stop; - if (((1.6)==(1.5)) != 1'b0) $stop; - if (((1.6)!=(1.5)) != 1'b1) $stop; - if (((1.6)> (1.5)) != 1'b1) $stop; - if (((1.6)>=(1.5)) != 1'b1) $stop; - if (((1.6)< (1.5)) != 1'b0) $stop; - if (((1.6)<=(1.5)) != 1'b0) $stop; - // - if (((0.0)?(2.0):(1.1)) != 1.1) $stop; - if (((1.5)?(2.0):(1.1)) != 2.0) $stop; - // - if (!1.7) $stop; - if (!(!0.0)) $stop; - if (1.8 && 0.0) $stop; - if (!(1.8 || 0.0)) $stop; - // - i=0; - for (r=1.0; r<2.0; r=r+0.1) i++; - if (i!=10) $stop; - // bug - ci64 = $realtobits(1.444); - if (ci64 != 64'h3ff71a9fbe76c8b4) $stop; - r = $bitstoreal(64'h3ff71a9fbe76c8b4); - if (r != 1.444) $stop; - r = $bitstoreal($realtobits(1.414)); - if (r != 1.414) $stop; - // bug - r = 32'bxz000_111; // 7 accoding to IEEE - if (r != 7) $stop; - // bug - b = 64'h7fe8000000000000; - $display("%6.3f", $bitstoreal(b)); - // bug - i48 = 48'hff00_00000000; - r = real'(i48); - if (r != 280375465082880.0) $stop; - r = $itor(i48); - if (r != 280375465082880.0) $stop; + initial begin + if (1_00_0.0_1 != 1000.01) $stop; + // rtoi truncates + if ($rtoi(36.7) != 36) $stop; + if ($rtoi(36.5) != 36) $stop; + if ($rtoi(36.4) != 36) $stop; + // casting rounds + if ((integer'(36.7)) != 37) $stop; + if ((integer'(36.5)) != 37) $stop; + if ((integer'(36.4)) != 36) $stop; + // assignment rounds + // verilator lint_off REALCVT + i = 36.7; + if (i != 37) $stop; + i = 36.5; + if (i != 37) $stop; + i = 36.4; + if (i != 36) $stop; + r = 10'd38; + if (r != 38.0) $stop; + // verilator lint_on REALCVT + // operators + if ((-(1.5)) != -1.5) $stop; + if ((+(1.5)) != 1.5) $stop; + if (((1.5) + (1.25)) != 2.75) $stop; + if (((1.5) - (1.25)) != 0.25) $stop; + if (((1.5) * (1.25)) != 1.875) $stop; + if (((1.5) / (1.25)) != 1.2) $stop; + // + if (((1.5) == (2)) != 1'b0) $stop; // note 2 becomes real 2.0 + if (((1.5) != (2)) != 1'b1) $stop; + if (((1.5) > (2)) != 1'b0) $stop; + if (((1.5) >= (2)) != 1'b0) $stop; + if (((1.5) < (2)) != 1'b1) $stop; + if (((1.5) <= (2)) != 1'b1) $stop; + if (((1.5) == (1.5)) != 1'b1) $stop; + if (((1.5) != (1.5)) != 1'b0) $stop; + if (((1.5) > (1.5)) != 1'b0) $stop; + if (((1.5) >= (1.5)) != 1'b1) $stop; + if (((1.5) < (1.5)) != 1'b0) $stop; + if (((1.5) <= (1.5)) != 1'b1) $stop; + if (((1.6) == (1.5)) != 1'b0) $stop; + if (((1.6) != (1.5)) != 1'b1) $stop; + if (((1.6) > (1.5)) != 1'b1) $stop; + if (((1.6) >= (1.5)) != 1'b1) $stop; + if (((1.6) < (1.5)) != 1'b0) $stop; + if (((1.6) <= (1.5)) != 1'b0) $stop; + // + if (((0.0) ? (2.0) : (1.1)) != 1.1) $stop; + if (((1.5) ? (2.0) : (1.1)) != 2.0) $stop; + // + if (!1.7) $stop; + if (!(!0.0)) $stop; + if (1.8 && 0.0) $stop; + if (!(1.8 || 0.0)) $stop; + // + i = 0; + for (r = 1.0; r < 2.0; r = r + 0.1) i++; + if (i != 10) $stop; + // bug + ci64 = $realtobits(1.444); + if (ci64 != 64'h3ff71a9fbe76c8b4) $stop; + r = $bitstoreal(64'h3ff71a9fbe76c8b4); + if (r != 1.444) $stop; + r = $bitstoreal($realtobits(1.414)); + if (r != 1.414) $stop; + // bug + r = 32'bxz000_111; // 7 accoding to IEEE + if (r != 7) $stop; + // bug + b = 64'h7fe8000000000000; + $display("%6.3f", $bitstoreal(b)); + // bug + i48 = 48'hff00_00000000; + r = real'(i48); + if (r != 280375465082880.0) $stop; + r = $itor(i48); + if (r != 280375465082880.0) $stop; - is48 = 48'shff00_00000000; - r = real'(is48); - if (r != -1099511627776.0) $stop; - r = $itor(is48); - if (r != -1099511627776.0) $stop; + is48 = 48'shff00_00000000; + r = real'(is48); + if (r != -1099511627776.0) $stop; + r = $itor(is48); + if (r != -1099511627776.0) $stop; - r = 0; - r = i48; - if (r != 280375465082880.0) $stop; - r = 0; + r = 0; + r = i48; + if (r != 280375465082880.0) $stop; + r = 0; - r = $itor(-10); - if (r != -10.0) $stop; + r = $itor(-10); + if (r != -10.0) $stop; - r = real'(4'sb1111); - if (r != -1) $stop; - r = $itor(4'sb1111); - if (r != -1) $stop; + r = real'(4'sb1111); + if (r != -1) $stop; + r = $itor(4'sb1111); + if (r != -1) $stop; - r = real'(4'b1111); - if (r != 15) $stop; - r = $itor(4'b1111); - if (r != 15) $stop; + r = real'(4'b1111); + if (r != 15) $stop; + r = $itor(4'b1111); + if (r != 15) $stop; - r = real'(96'hf0000000_00000000_00000000); - if (r != 74276402357122816493947453440.0) $stop; - r = real'(96'shf0000000_00000000_00000000); - if (r != -4951760157141521099596496896.0) $stop; + r = real'(96'hf0000000_00000000_00000000); + if (r != 74276402357122816493947453440.0) $stop; + r = real'(96'shf0000000_00000000_00000000); + if (r != -4951760157141521099596496896.0) $stop; - r = 1.5; - if (r++ != 1.5) $stop; - if (r != 2.5) $stop; - if (r-- != 2.5) $stop; - if (r != 1.5) $stop; - if (++r != 2.5) $stop; - if (r != 2.5) $stop; - if (--r != 1.5) $stop; - if (r != 1.5) $stop; + r = 1.5; + if (r++ != 1.5) $stop; + if (r != 2.5) $stop; + if (r-- != 2.5) $stop; + if (r != 1.5) $stop; + if (++r != 2.5) $stop; + if (r != 2.5) $stop; + if (--r != 1.5) $stop; + if (r != 1.5) $stop; - r = 1.23456; - s = $sformatf("%g", r); - `checks(s, "1.23456"); - r = 1.0/0; // inf - s = $sformatf("%g", r); - `checks(s, "inf"); - r = -1.0/0; // -inf - s = $sformatf("%g", r); - `checks(s, "-inf"); - r = $sqrt(-1.0); // NaN - s = $sformatf("%g", r); - if (s == "-nan") s = "nan"; - `checks(s, "nan"); - r = -$sqrt(-1.0); // NaN - s = $sformatf("%g", r); - if (s == "-nan") s = "nan"; - `checks(s, "nan"); + r = 1.23456; + s = $sformatf("%g", r); + `checks(s, "1.23456"); + r = 1.0 / 0; // inf + s = $sformatf("%g", r); + `checks(s, "inf"); + r = -1.0 / 0; // -inf + s = $sformatf("%g", r); + `checks(s, "-inf"); + r = $sqrt(-1.0); // NaN + s = $sformatf("%g", r); + if (s == "-nan") s = "nan"; + `checks(s, "nan"); + r = -$sqrt(-1.0); // NaN + s = $sformatf("%g", r); + if (s == "-nan") s = "nan"; + `checks(s, "nan"); - if (real'(TWENTY) != 20.0) $stop; - if (TWENDIV != 3.0) $stop; - end + if (real'(TWENTY) != 20.0) $stop; + if (TWENDIV != 3.0) $stop; + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - ci48 <= '0; - cis48 <= '0; - ci96 <= '0; - cis96 <= '0; - end - else if (cyc == 1) begin - ci48 <= 48'hff00_00000000; - cis48 <= 48'shff00_00000000; - ci96 <= 96'hf0000000_00000000_00000000; - cis96 <= 96'shf0000000_00000000_00000000; - end - else if (cyc<80) begin - if ($time != {32'h0, $rtoi($realtime)}) $stop; - if ($itor(cyc) != cyc) $stop; - //Unsup: if ((real `($time)) != $realtime) $stop; - r = $itor(cyc*2); - i = $rtoi(r); - if (i!=cyc*2) $stop; - // - r = $itor(cyc)/1.5; - b = $realtobits(r); - r2 = $bitstoreal(b); - if (r != r2) $stop; - // - // Trust the integer math as a comparison - r = $itor(cyc); - if ($rtoi(-r) != -cyc) $stop; - if ($rtoi(+r) != cyc) $stop; - if ($rtoi(r+2.0) != (cyc+2)) $stop; - if ($rtoi(r-2.0) != (cyc-2)) $stop; - if ($rtoi(r*2.0) != (cyc*2)) $stop; - if ($rtoi(r/2.0) != (cyc/2)) $stop; - r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash - // - r2 = $itor(cyc); - case (r) - (r2-1.0): $stop; - r2: ; - default: $stop; - endcase - // - r = $itor(cyc); - if ((r==50.0) != (cyc==50)) $stop; - if ((r!=50.0) != (cyc!=50)) $stop; - if ((r> 50.0) != (cyc> 50)) $stop; - if ((r>=50.0) != (cyc>=50)) $stop; - if ((r< 50.0) != (cyc< 50)) $stop; - if ((r<=50.0) != (cyc<=50)) $stop; - // - if ($rtoi((r-50.0) ? 10.0 : 20.0) - != (((cyc-50)!=0) ? 10 : 20)) $stop; - // - if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; - // - r = real'(ci48); - `checkr(r, 280375465082880.0); - r = real'(cis48); - `checkr(r, -1099511627776.0); - // - r = real'(ci96); - `checkr(r, 74276402357122816493947453440.0); - r = real'(cis96); - `checkr(r, -4951760157141521099596496896.0); - end - else if (cyc==90) begin - ci32 <= '0; - cis32 <= '0; - ci48 <= '0; - cis48 <= '0; - ci64 <= '0; - cis64 <= '0; - ci96 <= '0; - cis96 <= '0; - end - else if (cyc==91) begin - `checkr(real'(ci32), 0.0); - `checkr(real'(cis32), 0.0); - `checkr(real'(ci48), 0.0); - `checkr(real'(cis48), 0.0); - `checkr(real'(ci64), 0.0); - `checkr(real'(cis64), 0.0); - `checkr(real'(ci96), 0.0); - `checkr(real'(cis96), 0.0); - end - else if (cyc==92) begin - ci32 <= 32'b1; - cis32 <= 32'b1; - ci48 <= 48'b1; - cis48 <= 48'b1; - ci64 <= 64'b1; - cis64 <= 64'b1; - ci96 <= 96'b1; - cis96 <= 96'b1; - end - else if (cyc==93) begin - `checkr(real'(ci32), 1.0); - `checkr(real'(cis32), 1.0); - `checkr(real'(ci48), 1.0); - `checkr(real'(cis48), 1.0); - `checkr(real'(ci64), 1.0); - `checkr(real'(cis64), 1.0); - `checkr(real'(ci96), 1.0); - `checkr(real'(cis96), 1.0); - end - else if (cyc==94) begin - ci32 <= ~ '0; - cis32 <= ~ '0; - ci48 <= ~ '0; - cis48 <= ~ '0; - ci64 <= ~ '0; - cis64 <= ~ '0; - ci96 <= ~ '0; - cis96 <= ~ '0; - end - else if (cyc==95) begin - `checkr(real'(ci32), 4294967295.0); - `checkr(real'(cis32), -1.0); - `checkr(real'(ci48), 281474976710655.0); - `checkr(real'(cis48), -1.0); - `checkr(real'(ci64), 18446744073709551616.0); - `checkr(real'(cis64), -1.0); - `checkr(real'(ci96), 79228162514264337593543950336.0); - `checkr(real'(cis96), -1.0); - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub_cast_bug374(input clk, input [4:0] cyc5); - integer i; - - always @(posedge clk) begin - i <= integer'(cyc5); + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + ci48 <= '0; + cis48 <= '0; + ci96 <= '0; + cis96 <= '0; end + else if (cyc == 1) begin + ci48 <= 48'hff00_00000000; + cis48 <= 48'shff00_00000000; + ci96 <= 96'hf0000000_00000000_00000000; + cis96 <= 96'shf0000000_00000000_00000000; + end + else if (cyc < 80) begin + if ($time != {32'h0, $rtoi($realtime)}) $stop; + if ($itor(cyc) != cyc) $stop; + //Unsup: if ((real `($time)) != $realtime) $stop; + r = $itor(cyc * 2); + i = $rtoi(r); + if (i != cyc * 2) $stop; + // + r = $itor(cyc) / 1.5; + b = $realtobits(r); + r2 = $bitstoreal(b); + if (r != r2) $stop; + // + // Trust the integer math as a comparison + r = $itor(cyc); + if ($rtoi(-r) != -cyc) $stop; + if ($rtoi(+r) != cyc) $stop; + if ($rtoi(r + 2.0) != (cyc + 2)) $stop; + if ($rtoi(r - 2.0) != (cyc - 2)) $stop; + if ($rtoi(r * 2.0) != (cyc * 2)) $stop; + if ($rtoi(r / 2.0) != (cyc / 2)) $stop; + r2 = (2.0 / (r - 60)); // When zero, result indeterminate, but no crash + // + r2 = $itor(cyc); + case (r) + (r2 - 1.0): $stop; + r2: ; + default: $stop; + endcase + // + r = $itor(cyc); + if ((r == 50.0) != (cyc == 50)) $stop; + if ((r != 50.0) != (cyc != 50)) $stop; + if ((r > 50.0) != (cyc > 50)) $stop; + if ((r >= 50.0) != (cyc >= 50)) $stop; + if ((r < 50.0) != (cyc < 50)) $stop; + if ((r <= 50.0) != (cyc <= 50)) $stop; + // + if ($rtoi((r - 50.0) ? 10.0 : 20.0) != (((cyc - 50) != 0) ? 10 : 20)) $stop; + // + if ((!(r - 50.0)) != (!((cyc - 50) != 0))) $stop; + // + r = real'(ci48); + `checkr(r, 280375465082880.0); + r = real'(cis48); + `checkr(r, -1099511627776.0); + // + r = real'(ci96); + `checkr(r, 74276402357122816493947453440.0); + r = real'(cis96); + `checkr(r, -4951760157141521099596496896.0); + end + else if (cyc == 90) begin + ci32 <= '0; + cis32 <= '0; + ci48 <= '0; + cis48 <= '0; + ci64 <= '0; + cis64 <= '0; + ci96 <= '0; + cis96 <= '0; + end + else if (cyc == 91) begin + `checkr(real'(ci32), 0.0); + `checkr(real'(cis32), 0.0); + `checkr(real'(ci48), 0.0); + `checkr(real'(cis48), 0.0); + `checkr(real'(ci64), 0.0); + `checkr(real'(cis64), 0.0); + `checkr(real'(ci96), 0.0); + `checkr(real'(cis96), 0.0); + end + else if (cyc == 92) begin + ci32 <= 32'b1; + cis32 <= 32'b1; + ci48 <= 48'b1; + cis48 <= 48'b1; + ci64 <= 64'b1; + cis64 <= 64'b1; + ci96 <= 96'b1; + cis96 <= 96'b1; + end + else if (cyc == 93) begin + `checkr(real'(ci32), 1.0); + `checkr(real'(cis32), 1.0); + `checkr(real'(ci48), 1.0); + `checkr(real'(cis48), 1.0); + `checkr(real'(ci64), 1.0); + `checkr(real'(cis64), 1.0); + `checkr(real'(ci96), 1.0); + `checkr(real'(cis96), 1.0); + end + else if (cyc == 94) begin + ci32 <= ~'0; + cis32 <= ~'0; + ci48 <= ~'0; + cis48 <= ~'0; + ci64 <= ~'0; + cis64 <= ~'0; + ci96 <= ~'0; + cis96 <= ~'0; + end + else if (cyc == 95) begin + `checkr(real'(ci32), 4294967295.0); + `checkr(real'(cis32), -1.0); + `checkr(real'(ci48), 281474976710655.0); + `checkr(real'(cis48), -1.0); + `checkr(real'(ci64), 18446744073709551616.0); + `checkr(real'(cis64), -1.0); + `checkr(real'(ci96), 79228162514264337593543950336.0); + `checkr(real'(cis96), -1.0); + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub_cast_bug374 ( + input clk, + input [4:0] cyc5 +); + integer i; + + always @(posedge clk) begin + i <= integer'(cyc5); + end endmodule diff --git a/test_regress/t/t_math_real_public.v b/test_regress/t/t_math_real_public.v index accf2fe02..4781838d5 100644 --- a/test_regress/t/t_math_real_public.v +++ b/test_regress/t/t_math_real_public.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub #(.REAL_PARAM(2.0)) sub(); + sub #(.REAL_PARAM(2.0)) sub (); endmodule module sub (); - parameter REAL_PARAM = 0.0; // Magic name grepped for in .py file + parameter REAL_PARAM = 0.0; // Magic name grepped for in .py file - initial begin - $display("REAL_PARAM=%g", REAL_PARAM); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("REAL_PARAM=%g", REAL_PARAM); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_real_random.v b/test_regress/t/t_math_real_random.v index 4e9044a90..e507f65c8 100644 --- a/test_regress/t/t_math_real_random.v +++ b/test_regress/t/t_math_real_random.v @@ -4,98 +4,100 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - reg [127:0] in; + reg [127:0] in; - check #(48) check48 (.*); - check #(31) check31 (.*); - check #(32) check32 (.*); - check #(63) check63 (.*); - check #(64) check64 (.*); - check #(96) check96 (.*); - check #(128) check128 (.*); + check #(48) check48 (.*); + check #(31) check31 (.*); + check #(32) check32 (.*); + check #(63) check63 (.*); + check #(64) check64 (.*); + check #(96) check96 (.*); + check #(128) check128 (.*); - always_comb begin - if (crc[2:0] == 0) in = '0; - else if (crc[2:0] == 1) in = ~'0; - else if (crc[2:0] == 2) in = 128'b1; - else if (crc[2:0] == 3) in = ~ 128'b1; - else begin - in = {crc, crc}; - if (crc[3]) in[31:0] = '0; - if (crc[4]) in[63:32] = '0; - if (crc[5]) in[95:64] = '0; - if (crc[6]) in[127:96] = '0; - if (crc[7]) in[31:0] = ~'0; - if (crc[8]) in[63:32] = ~'0; - if (crc[9]) in[95:64] = ~'0; - if (crc[10]) in[127:96] = ~'0; - end - end + always_comb begin + if (crc[2:0] == 0) in = '0; + else if (crc[2:0] == 1) in = ~'0; + else if (crc[2:0] == 2) in = 128'b1; + else if (crc[2:0] == 3) in = ~ 128'b1; + else begin + in = {crc, crc}; + if (crc[3]) in[31:0] = '0; + if (crc[4]) in[63:32] = '0; + if (crc[5]) in[95:64] = '0; + if (crc[6]) in[127:96] = '0; + if (crc[7]) in[31:0] = ~'0; + if (crc[8]) in[63:32] = ~'0; + if (crc[9]) in[95:64] = ~'0; + if (crc[10]) in[127:96] = ~'0; + end + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in); + $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc == 99) begin - `checkr(check48.sum, 14574057015683440.000000); - `checkr(check31.sum, 114141374814.000000); - `checkr(check32.sum, 236547942750.000000); - `checkr(check63.sum, 513694866079917670400.000000); - `checkr(check64.sum, 1002533584033221181440.000000); - `checkr(check96.sum, 4377373669974269260279175970816.000000); - `checkr(check128.sum, 18358899571808044815012294240949812330496.000000); - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc == 99) begin + `checkr(check48.sum, 14574057015683440.000000); + `checkr(check31.sum, 114141374814.000000); + `checkr(check32.sum, 236547942750.000000); + `checkr(check63.sum, 513694866079917670400.000000); + `checkr(check64.sum, 1002533584033221181440.000000); + `checkr(check96.sum, 4377373669974269260279175970816.000000); + `checkr(check128.sum, 18358899571808044815012294240949812330496.000000); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module check(/*AUTOARG*/ - // Inputs - in, clk, cyc - ); - parameter WIDTH = 128; - input [127:0] in; + // Inputs + in, clk, cyc + ); + parameter WIDTH = 128; + input [127:0] in; - wire [WIDTH-1:0] ci = in[WIDTH-1:0]; - wire signed [WIDTH-1:0] cis = in[WIDTH-1:0]; + wire [WIDTH-1:0] ci = in[WIDTH-1:0]; + wire signed [WIDTH-1:0] cis = in[WIDTH-1:0]; - real r; - real rs; - always_comb r = ci; - always_comb rs = cis; + real r; + real rs; + always_comb r = ci; + always_comb rs = cis; - input clk; - input integer cyc; - real sum; + input clk; + input integer cyc; + real sum; - always_ff @ (negedge clk) begin + always_ff @ (negedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum); + $write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum); `endif - if (cyc < 10) sum <= 0; - else sum <= sum + r + rs; - end + if (cyc < 10) sum <= 0; + else sum <= sum + r + rs; + end endmodule diff --git a/test_regress/t/t_math_real_round.v b/test_regress/t/t_math_real_round.v index 1677c0f40..c9830e530 100644 --- a/test_regress/t/t_math_real_round.v +++ b/test_regress/t/t_math_real_round.v @@ -6,97 +6,97 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - real r; - reg [31:0] v32; - reg [63:0] v64; - reg [95:0] v96; + real r; + reg [31:0] v32; + reg [63:0] v64; + reg [95:0] v96; - initial begin + initial begin + // verilator lint_off REALCVT + v32 = -1.5; + v64 = -1.5; + v96 = -1.5; + // verilator lint_on REALCVT + `checkh(v32, 32'hfffffffe); + `checkh(v64, 64'hfffffffffffffffe); + `checkh(v96, 96'hfffffffffffffffffffffffe); + + // verilator lint_off REALCVT + v32 = 12456789012345678912345.5; + v64 = 12456789012345678912345.5; + v96 = 12456789012345678912345.5; + // verilator lint_on REALCVT + `checkh(v32, 32'he5400000); + `checkh(v64, 64'h48acb7d4e5400000); + `checkh(v96, 96'h000002a348acb7d4e5400000); + + // verilator lint_off REALCVT + v32 = -12456789012345678912345.5; + v64 = -12456789012345678912345.5; + v96 = -12456789012345678912345.5; + // verilator lint_on REALCVT + `checkh(v32, 32'h1ac00000); + `checkh(v64, 64'hb753482b1ac00000); + `checkh(v96, 96'hfffffd5cb753482b1ac00000); + end + + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + r <= 0; + end + else if (cyc == 11) begin // verilator lint_off REALCVT - v32 = -1.5; - v64 = -1.5; - v96 = -1.5; + v32 = r; + v64 = r; + v96 = r; // verilator lint_on REALCVT - `checkh(v32, 32'hfffffffe); - `checkh(v64, 64'hfffffffffffffffe); - `checkh(v96, 96'hfffffffffffffffffffffffe); - + `checkh(v32, '0); + `checkh(v64, '0); + `checkh(v96, '0); + end + else if (cyc == 20) begin + r <= -5.24567; + end + else if (cyc == 21) begin // verilator lint_off REALCVT - v32 = 12456789012345678912345.5; - v64 = 12456789012345678912345.5; - v96 = 12456789012345678912345.5; + v32 = r; + v64 = r; + v96 = r; + // verilator lint_on REALCVT + `checkh(v32, 32'hfffffffb); + `checkh(v64, 64'hfffffffffffffffb); + `checkh(v96, 96'hfffffffffffffffffffffffb); + end + else if (cyc == 30) begin + r <= 12456789012345678912345.5; + end + else if (cyc == 31) begin + // verilator lint_off REALCVT + v32 = r; + v64 = r; + v96 = r; // verilator lint_on REALCVT `checkh(v32, 32'he5400000); `checkh(v64, 64'h48acb7d4e5400000); `checkh(v96, 96'h000002a348acb7d4e5400000); - - // verilator lint_off REALCVT - v32 = -12456789012345678912345.5; - v64 = -12456789012345678912345.5; - v96 = -12456789012345678912345.5; - // verilator lint_on REALCVT - `checkh(v32, 32'h1ac00000); - `checkh(v64, 64'hb753482b1ac00000); - `checkh(v96, 96'hfffffd5cb753482b1ac00000); - end - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - r <= 0; - end - else if (cyc == 11) begin - // verilator lint_off REALCVT - v32 = r; - v64 = r; - v96 = r; - // verilator lint_on REALCVT - `checkh(v32, '0); - `checkh(v64, '0); - `checkh(v96, '0); - end - else if (cyc == 20) begin - r <= -5.24567; - end - else if (cyc == 21) begin - // verilator lint_off REALCVT - v32 = r; - v64 = r; - v96 = r; - // verilator lint_on REALCVT - `checkh(v32, 32'hfffffffb); - `checkh(v64, 64'hfffffffffffffffb); - `checkh(v96, 96'hfffffffffffffffffffffffb); - end - else if (cyc == 30) begin - r <= 12456789012345678912345.5; - end - else if (cyc == 31) begin - // verilator lint_off REALCVT - v32 = r; - v64 = r; - v96 = r; - // verilator lint_on REALCVT - `checkh(v32, 32'he5400000); - `checkh(v64, 64'h48acb7d4e5400000); - `checkh(v96, 96'h000002a348acb7d4e5400000); - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_red.v b/test_regress/t/t_math_red.v index a357c471c..018ce0b97 100644 --- a/test_regress/t/t_math_red.v +++ b/test_regress/t/t_math_red.v @@ -4,63 +4,64 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - reg [67:0] r; + reg [67:0] r; - wire and_reduce = &r; - wire or_reduce = |r; - wire xor_reduce = ^r; - wire xnor_reduce = ~^r; - wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; + wire and_reduce = &r; + wire or_reduce = |r; + wire xor_reduce = ^r; + wire xnor_reduce = ~^r; + wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", - cyc, r, and_reduce, or_reduce, xor_reduce, check_equal); + $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", cyc, r, and_reduce, + or_reduce, xor_reduce, check_equal); `endif - cyc <= cyc + 1; - if (cyc == 1) begin - r <= 68'd0; - end - else if (cyc == 10) begin - `checkh(r, 68'h0000_0000_0000_0000_0); - `checkh(and_reduce, '0); - `checkh(or_reduce, '0); - `checkh(xor_reduce, '0); - `checkh(xnor_reduce, '1); - r <= 68'hffff_ffff_ffff_ffff_e; - end - else if (cyc == 11) begin - `checkh(r, 68'hffff_ffff_ffff_ffff_e); - `checkh(and_reduce, '0); - `checkh(or_reduce, '1); - `checkh(xor_reduce, '1); - `checkh(xnor_reduce, '0); - r <= 68'hffff_ffff_ffff_ffff_f; - end - else if (cyc == 12) begin - `checkh(r, 68'hffff_ffff_ffff_ffff_f); - `checkh(and_reduce, '1); - `checkh(or_reduce, '1); - `checkh(xor_reduce, '0); - `checkh(xnor_reduce, '1); - end - else if (cyc == 90) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - r <= 68'd0; - end - end + cyc <= cyc + 1; + if (cyc == 1) begin + r <= 68'd0; + end + else if (cyc == 10) begin + `checkh(r, 68'h0000_0000_0000_0000_0); + `checkh(and_reduce, '0); + `checkh(or_reduce, '0); + `checkh(xor_reduce, '0); + `checkh(xnor_reduce, '1); + r <= 68'hffff_ffff_ffff_ffff_e; + end + else if (cyc == 11) begin + `checkh(r, 68'hffff_ffff_ffff_ffff_e); + `checkh(and_reduce, '0); + `checkh(or_reduce, '1); + `checkh(xor_reduce, '1); + `checkh(xnor_reduce, '0); + r <= 68'hffff_ffff_ffff_ffff_f; + end + else if (cyc == 12) begin + `checkh(r, 68'hffff_ffff_ffff_ffff_f); + `checkh(and_reduce, '1); + `checkh(or_reduce, '1); + `checkh(xor_reduce, '0); + `checkh(xnor_reduce, '1); + end + else if (cyc == 90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + r <= 68'd0; + end + end endmodule diff --git a/test_regress/t/t_math_repl.v b/test_regress/t/t_math_repl.v index 91c7e1230..bdc5449ab 100644 --- a/test_regress/t/t_math_repl.v +++ b/test_regress/t/t_math_repl.v @@ -4,38 +4,38 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [63:0] rf; - reg [63:0] rf2; - reg [63:0] biu; - reg b; + reg [63:0] rf; + reg [63:0] rf2; + reg [63:0] biu; + reg b; - always @* begin - rf[63:32] = biu[63:32] & {32{b}}; - rf[31:0] = {32{b}}; - rf2 = rf; - rf2[31:0] = ~{32{b}}; - end + always @* begin + rf[63:32] = biu[63:32] & {32{b}}; + rf[31:0] = {32{b}}; + rf2 = rf; + rf2[31:0] = ~{32{b}}; + end - reg [31:0] src1, src0, sr, mask; - wire [31:0] dualasr + reg [31:0] src1, src0, sr, mask; + wire [31:0] dualasr = ((| src1[31:4]) ? {{16{src0[31]}}, {16{src0[15]}}} : ( ( sr & {2{mask[31:16]}}) | ( {{16{src0[31]}}, {16{src0[15]}}} & {2{~mask[31:16]}}))); - wire [31:0] sl_mask + wire [31:0] sl_mask = (32'hffffffff << src1[4:0]); - wire [31:0] sr_mask + // verilog_format: off + wire [31:0] sr_mask = {sl_mask[0], sl_mask[1], sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], @@ -49,62 +49,64 @@ module t (/*AUTOARG*/ sl_mask[25], sl_mask[26], sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; + // verilog_format: on - wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; - wire [1:0] w = {2{b}}; + wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; + wire [1:0] w = {2{b}}; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); + $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, + widerep); `endif - if (cyc==1) begin - biu <= 64'h12451282_abadee00; - b <= 1'b0; - src1 <= 32'h00000001; - src0 <= 32'h9a4f1235; - sr <= 32'h0f19f567; - mask <= 32'h7af07ab4; - end - if (cyc==2) begin - biu <= 64'h12453382_abad8801; - b <= 1'b1; - if (rf != 64'h0) $stop; - if (rf2 != 64'h00000000ffffffff) $stop; - src1 <= 32'h0010000f; - src0 <= 32'h028aa336; - sr <= 32'h42ad0377; - mask <= 32'h1ab3b906; - if (dualasr != 32'h8f1f7060) $stop; - if (sl_mask != 32'hfffffffe) $stop; - if (sr_mask != 32'h7fffffff) $stop; - if (widerep != '0) $stop; - end - if (cyc==3) begin - biu <= 64'h12422382_77ad8802; - b <= 1'b1; - if (rf != 64'h12453382ffffffff) $stop; - if (rf2 != 64'h1245338200000000) $stop; - src1 <= 32'h0000000f; - src0 <= 32'h5c158f71; - sr <= 32'h7076c40a; - mask <= 32'h33eb3d44; - if (dualasr != 32'h0000ffff) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - if (widerep != '1) $stop; - end - if (cyc==4) begin - if (rf != 64'h12422382ffffffff) $stop; - if (rf2 != 64'h1242238200000000) $stop; - if (dualasr != 32'h3062cc1e) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - $write("*-* All Finished *-*\n"); - if (widerep != '1) $stop; - $finish; - end + if (cyc == 1) begin + biu <= 64'h12451282_abadee00; + b <= 1'b0; + src1 <= 32'h00000001; + src0 <= 32'h9a4f1235; + sr <= 32'h0f19f567; + mask <= 32'h7af07ab4; end - end + if (cyc == 2) begin + biu <= 64'h12453382_abad8801; + b <= 1'b1; + if (rf != 64'h0) $stop; + if (rf2 != 64'h00000000ffffffff) $stop; + src1 <= 32'h0010000f; + src0 <= 32'h028aa336; + sr <= 32'h42ad0377; + mask <= 32'h1ab3b906; + if (dualasr != 32'h8f1f7060) $stop; + if (sl_mask != 32'hfffffffe) $stop; + if (sr_mask != 32'h7fffffff) $stop; + if (widerep != '0) $stop; + end + if (cyc == 3) begin + biu <= 64'h12422382_77ad8802; + b <= 1'b1; + if (rf != 64'h12453382ffffffff) $stop; + if (rf2 != 64'h1245338200000000) $stop; + src1 <= 32'h0000000f; + src0 <= 32'h5c158f71; + sr <= 32'h7076c40a; + mask <= 32'h33eb3d44; + if (dualasr != 32'h0000ffff) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + if (widerep != '1) $stop; + end + if (cyc == 4) begin + if (rf != 64'h12422382ffffffff) $stop; + if (rf2 != 64'h1242238200000000) $stop; + if (dualasr != 32'h3062cc1e) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + $write("*-* All Finished *-*\n"); + if (widerep != '1) $stop; + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_repl2_bad.out b/test_regress/t/t_math_repl2_bad.out index 9f5fecdc7..b9dad6830 100644 --- a/test_regress/t/t_math_repl2_bad.out +++ b/test_regress/t/t_math_repl2_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_math_repl2_bad.v:28:30: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffffb' +%Error: t/t_math_repl2_bad.v:29:28: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffffb' : ... note: In instance 't' - 28 | out <= {{(P24 - P29){1'b0}}, in}; - | ^ + 29 | out <= {{(P24 - P29) {1'b0}}, in}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHTRUNC: t/t_math_repl2_bad.v:28:14: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS's REPLICATE generates 30 bits. +%Warning-WIDTHTRUNC: t/t_math_repl2_bad.v:29:11: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS's REPLICATE generates 30 bits. : ... note: In instance 't' - 28 | out <= {{(P24 - P29){1'b0}}, in}; - | ^~ + 29 | out <= {{(P24 - P29) {1'b0}}, in}; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_math_repl2_bad.v b/test_regress/t/t_math_repl2_bad.v index a1e7048a5..6f910c5bb 100644 --- a/test_regress/t/t_math_repl2_bad.v +++ b/test_regress/t/t_math_repl2_bad.v @@ -4,28 +4,29 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module t ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - parameter P32 = 32; - parameter P24 = 24; - localparam P29 = P24 + 5; + parameter P32 = 32; + parameter P24 = 24; + localparam P29 = P24 + 5; - input clk; - output reg [P24-1:0] out; + input clk; + output reg [P24-1:0] out; - input [P29 - 1:0] in; + input [P29 - 1:0] in; - always @(posedge clk) begin - if (P29 >= P24) begin - out <= in[P29 - 1 -: P24]; - end - else begin - out <= {{(P24 - P29){1'b0}}, in}; - end - end + always @(posedge clk) begin + if (P29 >= P24) begin + out <= in[P29-1-:P24]; + end + else begin + out <= {{(P24 - P29) {1'b0}}, in}; + end + end endmodule diff --git a/test_regress/t/t_math_repl_bad.out b/test_regress/t/t_math_repl_bad.out index 5183396e3..cbbda29b1 100644 --- a/test_regress/t/t_math_repl_bad.out +++ b/test_regress/t/t_math_repl_bad.out @@ -1,21 +1,21 @@ -%Error-ZEROREPL: t/t_math_repl_bad.v:12:14: Replication value of 0 is only legal under a concatenation (IEEE 1800-2023 11.4.12.1) +%Error-ZEROREPL: t/t_math_repl_bad.v:12:11: Replication value of 0 is only legal under a concatenation (IEEE 1800-2023 11.4.12.1) : ... note: In instance 't' - 12 | o = {0 {1'b1}}; - | ^ + 12 | o = {0{1'b1}}; + | ^ ... For error description see https://verilator.org/warn/ZEROREPL?v=latest -%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. +%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:12:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' - 12 | o = {0 {1'b1}}; - | ^ + 12 | o = {0{1'b1}}; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Error: t/t_math_repl_bad.v:13:43: Replication value isn't a constant. +%Error: t/t_math_repl_bad.v:13:41: Replication value isn't a constant. : ... note: In instance 't' - 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; - | ^ + 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:13:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. +%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:13:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' - 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; - | ^ + 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_math_repl_bad.v b/test_regress/t/t_math_repl_bad.v index 96ad2981e..2609a66d3 100644 --- a/test_regress/t/t_math_repl_bad.v +++ b/test_regress/t/t_math_repl_bad.v @@ -6,11 +6,11 @@ module t; - logic [31:0] o; + logic [31:0] o; - initial begin - o = {0 {1'b1}}; // Bad 0 rep - o = {$test$plusargs("NON-CONSTANT") {1'b1}}; // Bad non-constant rep - $stop; - end + initial begin + o = {0{1'b1}}; // Bad 0 rep + o = {$test$plusargs("NON-CONSTANT") {1'b1}}; // Bad non-constant rep + $stop; + end endmodule diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v index 0cfc3bd1c..12402f814 100644 --- a/test_regress/t/t_math_reverse.v +++ b/test_regress/t/t_math_reverse.v @@ -4,80 +4,79 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [7:0] crc; + reg [7:0] crc; - // Build up assignments - wire [7:0] bitrev; - assign bitrev[7] = crc[0]; - assign bitrev[6] = crc[1]; - assign bitrev[5] = crc[2]; - assign bitrev[4] = crc[3]; - assign bitrev[0] = crc[7]; - assign bitrev[1] = crc[6]; - assign bitrev[2] = crc[5]; - assign bitrev[3] = crc[4]; + // Build up assignments + wire [7:0] bitrev; + assign bitrev[7] = crc[0]; + assign bitrev[6] = crc[1]; + assign bitrev[5] = crc[2]; + assign bitrev[4] = crc[3]; + assign bitrev[0] = crc[7]; + assign bitrev[1] = crc[6]; + assign bitrev[2] = crc[5]; + assign bitrev[3] = crc[4]; - // Build up always assignments - reg [7:0] bitrevb; - always @ (/*AS*/crc) begin - bitrevb[7] = crc[0]; - bitrevb[6] = crc[1]; - bitrevb[5] = crc[2]; - bitrevb[4] = crc[3]; - bitrevb[0] = crc[7]; - bitrevb[1] = crc[6]; - bitrevb[2] = crc[5]; - bitrevb[3] = crc[4]; - end + // Build up always assignments + reg [7:0] bitrevb; + always @( /*AS*/ crc) begin + bitrevb[7] = crc[0]; + bitrevb[6] = crc[1]; + bitrevb[5] = crc[2]; + bitrevb[4] = crc[3]; + bitrevb[0] = crc[7]; + bitrevb[1] = crc[6]; + bitrevb[2] = crc[5]; + bitrevb[3] = crc[4]; + end - // Build up always assignments - reg [7:0] bitrevr; - always @ (posedge clk) begin - bitrevr[7] <= crc[0]; - bitrevr[6] <= crc[1]; - bitrevr[5] <= crc[2]; - bitrevr[4] <= crc[3]; - bitrevr[0] <= crc[7]; - bitrevr[1] <= crc[6]; - bitrevr[2] <= crc[5]; - bitrevr[3] <= crc[4]; - end + // Build up always assignments + reg [7:0] bitrevr; + always @(posedge clk) begin + bitrevr[7] <= crc[0]; + bitrevr[6] <= crc[1]; + bitrevr[5] <= crc[2]; + bitrevr[4] <= crc[3]; + bitrevr[0] <= crc[7]; + bitrevr[1] <= crc[6]; + bitrevr[2] <= crc[5]; + bitrevr[3] <= crc[4]; + end - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==1) begin - crc <= 8'hed; - end - if (cyc==2 && bitrev!=8'hb7) $stop; - if (cyc==3 && bitrev!=8'h5b) $stop; - if (cyc==4 && bitrev!=8'h2d) $stop; - if (cyc==5 && bitrev!=8'h16) $stop; - if (cyc==6 && bitrev!=8'h8b) $stop; - if (cyc==7 && bitrev!=8'hc5) $stop; - if (cyc==8 && bitrev!=8'he2) $stop; - if (cyc==9 && bitrev!=8'hf1) $stop; - if (bitrevb != bitrev) $stop; - if (cyc==3 && bitrevr!=8'hb7) $stop; - if (cyc==4 && bitrevr!=8'h5b) $stop; - if (cyc==5 && bitrevr!=8'h2d) $stop; - if (cyc==6 && bitrevr!=8'h16) $stop; - if (cyc==7 && bitrevr!=8'h8b) $stop; - if (cyc==8 && bitrevr!=8'hc5) $stop; - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + if (cyc == 1) begin + crc <= 8'hed; end - end + if (cyc == 2 && bitrev != 8'hb7) $stop; + if (cyc == 3 && bitrev != 8'h5b) $stop; + if (cyc == 4 && bitrev != 8'h2d) $stop; + if (cyc == 5 && bitrev != 8'h16) $stop; + if (cyc == 6 && bitrev != 8'h8b) $stop; + if (cyc == 7 && bitrev != 8'hc5) $stop; + if (cyc == 8 && bitrev != 8'he2) $stop; + if (cyc == 9 && bitrev != 8'hf1) $stop; + if (bitrevb != bitrev) $stop; + if (cyc == 3 && bitrevr != 8'hb7) $stop; + if (cyc == 4 && bitrevr != 8'h5b) $stop; + if (cyc == 5 && bitrevr != 8'h2d) $stop; + if (cyc == 6 && bitrevr != 8'h16) $stop; + if (cyc == 7 && bitrevr != 8'h8b) $stop; + if (cyc == 8 && bitrevr != 8'hc5) $stop; + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_shift_extend.v b/test_regress/t/t_math_shift_extend.v index 43d75aeca..82ae4a35e 100644 --- a/test_regress/t/t_math_shift_extend.v +++ b/test_regress/t/t_math_shift_extend.v @@ -6,59 +6,59 @@ module t; - logic in1 = 1; - logic [1:0] in2 = 2'b11; - logic [31:0] out; - logic [7:0] ones = 8'b11111111; - logic [9:0] ones10 = 10'b1111111111; + logic in1 = 1; + logic [1:0] in2 = 2'b11; + logic [31:0] out; + logic [7:0] ones = 8'b11111111; + logic [9:0] ones10 = 10'b1111111111; - typedef logic [7:0] data_t; + typedef logic [7:0] data_t; - typedef logic [9:0] ten_t; - ten_t out10; + typedef logic [9:0] ten_t; + ten_t out10; - // verilator lint_off WIDTH - initial begin - in1 = 1; - in2 = 0; - out = data_t'(in1 << in2); - if (out != 8'b1) $stop; + // verilator lint_off WIDTH + initial begin + in1 = 1; + in2 = 0; + out = data_t'(in1 << in2); + if (out != 8'b1) $stop; - in2 = 1; - out = data_t'(in1 << in2); - if (out != 8'b10) $stop; + in2 = 1; + out = data_t'(in1 << in2); + if (out != 8'b10) $stop; - in2 = 2; - out = data_t'(in1 << in2); - if (out != 8'b100) $stop; + in2 = 2; + out = data_t'(in1 << in2); + if (out != 8'b100) $stop; - in2 = 3; - out = data_t'(in1 << in2); - if (out != 8'b1000) $stop; + in2 = 3; + out = data_t'(in1 << in2); + if (out != 8'b1000) $stop; - // Check upper bits get cleared when cast - in2 = 3; - out = data_t'(ones << in2); - if (out != 8'b11111000) $stop; + // Check upper bits get cleared when cast + in2 = 3; + out = data_t'(ones << in2); + if (out != 8'b11111000) $stop; - in2 = 3; - out = data_t'(ones10 << in2); - if (out != 8'b11111000) $stop; + in2 = 3; + out = data_t'(ones10 << in2); + if (out != 8'b11111000) $stop; - // bug2597 - out = data_t'(10'h208 >> 2); - if (out != 8'h82) $stop; + // bug2597 + out = data_t'(10'h208 >> 2); + if (out != 8'h82) $stop; - out = data_t'(10'h208 >> 2); - if (out != 8'h82) $stop; + out = data_t'(10'h208 >> 2); + if (out != 8'h82) $stop; - out = data_t'('h208 >> 2); - if (out != 8'h82) $stop; + out = data_t'('h208 >> 2); + if (out != 8'h82) $stop; - out10 = ten_t'('h404 >> 2); - if (out10 != 10'h101) $stop; + out10 = ten_t'('h404 >> 2); + if (out10 != 10'h101) $stop; - $write("*-* All Finished *-*\n"); - $finish(); - end + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_math_shift_huge.v b/test_regress/t/t_math_shift_huge.v index 51c67da7a..3a4806c65 100644 --- a/test_regress/t/t_math_shift_huge.v +++ b/test_regress/t/t_math_shift_huge.v @@ -4,17 +4,18 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - outl, outr, - // Inputs - lhs - ); - input [95:0] lhs; - output [95:0] outl; - output [95:0] outr; +module t ( /*AUTOARG*/ + // Outputs + outl, + outr, + // Inputs + lhs +); + input [95:0] lhs; + output [95:0] outl; + output [95:0] outr; - assign outl = lhs << 95'hffff_00000000; - assign outr = lhs >> 95'hffff_00000000; + assign outl = lhs << 95'hffff_00000000; + assign outr = lhs >> 95'hffff_00000000; endmodule diff --git a/test_regress/t/t_math_shift_rep.v b/test_regress/t/t_math_shift_rep.v index 5b8921eda..db5a7c259 100644 --- a/test_regress/t/t_math_shift_rep.v +++ b/test_regress/t/t_math_shift_rep.v @@ -4,75 +4,76 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - //bug765; disappears if add this wire - //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values - wire [7:0] a = crc[7:0]; + //bug765; disappears if add this wire + //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values + wire [7:0] a = crc[7:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [15:0] y; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] y; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .y (y[15:0]), - // Inputs - .a (a[7:0])); + Test test ( /*AUTOINST*/ + // Outputs + .y(y[15:0]), + // Inputs + .a(a[7:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {48'h0, y}; + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, y}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - y, - // Inputs - a - ); - input signed [7:0] a; - output [15:0] y; - // verilator lint_off WIDTH - assign y = ~66'd0 <<< {4{a}}; - // verilator lint_on WIDTH +module Test ( /*AUTOARG*/ + // Outputs + y, + // Inputs + a +); + input signed [7:0] a; + output [15:0] y; + // verilator lint_off WIDTH + assign y = ~66'd0 <<< {4{a}}; + // verilator lint_on WIDTH endmodule diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v index 9d6436e9b..23c113910 100644 --- a/test_regress/t/t_math_shift_sel.v +++ b/test_regress/t/t_math_shift_sel.v @@ -4,85 +4,87 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [106:0] in = {~crc[42:0], crc[63:0]}; + // Take CRC data and apply to testblock inputs + wire [106:0] in = {~crc[42:0], crc[63:0]}; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] out1; // From test of Test.v - wire [7:0] out2; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] out1; // From test of Test.v + wire [7:0] out2; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out1 (out1[7:0]), - .out2 (out2[7:0]), - // Inputs - .in (in[106:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out1(out1[7:0]), + .out2(out2[7:0]), + // Inputs + .in(in[106:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {48'h0, out1, out1}; + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, out1, out1}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hc746017202a24ecc - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hc746017202a24ecc + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out1, out2, - // Inputs - in - ); +module Test ( /*AUTOARG*/ + // Outputs + out1, + out2, + // Inputs + in +); - // Replace this module with the device under test. - // - // Change the code in the t module to apply values to the inputs and - // merge the output values into the result vector. + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. - input [106:0] in; - output [7:0] out1, out2; + input [106:0] in; + output [7:0] out1, out2; - // verilator lint_off WIDTH - // Better written as onibble[99 +: 8]. Verilator will convert it. - wire [7:0] out1 = (in >>> 99) & 255; - // verilator lint_on WIDTH - wire [7:0] out2 = in[106:99]; + // verilator lint_off WIDTH + // Better written as onibble[99 +: 8]. Verilator will convert it. + wire [7:0] out1 = (in >>> 99) & 255; + // verilator lint_on WIDTH + wire [7:0] out2 = in[106:99]; endmodule diff --git a/test_regress/t/t_math_shift_side.v b/test_regress/t/t_math_shift_side.v index f08c3b414..d788f89ec 100644 --- a/test_regress/t/t_math_shift_side.v +++ b/test_regress/t/t_math_shift_side.v @@ -5,36 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int m_n_bits; + int m_n_bits; - function int get_n_bytes; - return ((m_n_bits - 1) / 8) + 1; - endfunction + function int get_n_bytes; + return ((m_n_bits - 1) / 8) + 1; + endfunction endclass module t; - int i; + int i; - initial begin - Cls c; - c = new; + initial begin + Cls c; + c = new; - c.m_n_bits = 23; - if (c.get_n_bytes() != 3) $stop; + c.m_n_bits = 23; + if (c.get_n_bytes() != 3) $stop; - i = 1 << c.get_n_bytes(); - if (i != 8) $stop; + i = 1 << c.get_n_bytes(); + if (i != 8) $stop; - i = 32'h1234 >> c.get_n_bytes(); - if (i != 32'h246) $stop; + i = 32'h1234 >> c.get_n_bytes(); + if (i != 32'h246) $stop; - i = 32'shffffffff >>> c.get_n_bytes(); - if (i != 32'hffffffff) $stop; + i = 32'shffffffff >>> c.get_n_bytes(); + if (i != 32'hffffffff) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_shiftls.v b/test_regress/t/t_math_shiftls.v index eb852e804..6cd2c8293 100644 --- a/test_regress/t/t_math_shiftls.v +++ b/test_regress/t/t_math_shiftls.v @@ -9,17 +9,19 @@ `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on -module top (out33); +module top ( + out33 +); -output wire [6:0] out33; + output wire [6:0] out33; - assign out33 = (7'o66 <<< 32'hFFFF_FFFF); + assign out33 = (7'o66 <<< 32'hFFFF_FFFF); - initial begin - #10; - `checkd(out33, '0); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + `checkd(out33, '0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_shiftrs.v b/test_regress/t/t_math_shiftrs.v index 058e99e5e..f79e49a49 100644 --- a/test_regress/t/t_math_shiftrs.v +++ b/test_regress/t/t_math_shiftrs.v @@ -4,54 +4,53 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg signed [64+15:0] data; - integer i; - integer b; - reg signed [64+15:0] srs; + reg signed [64+15:0] data; + integer i; + integer b; + reg signed [64+15:0] srs; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==2) begin - data <= 80'h0; - data[75] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==3) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b==(75-i) || b==(10-i))) $stop; - end - end - end - if (cyc==10) begin - data <= 80'h0; - data[79] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==12) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; - end - end - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 2) begin + data <= 80'h0; + data[75] <= 1'b1; + data[10] <= 1'b1; end - end + if (cyc == 3) begin + for (i = 0; i < 85; i = i + 1) begin + srs = data >>> i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b = 0; b < 80; b = b + 1) begin + if (srs[b] != (b == (75 - i) || b == (10 - i))) $stop; + end + end + end + if (cyc == 10) begin + data <= 80'h0; + data[79] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc == 12) begin + for (i = 0; i < 85; i = i + 1) begin + srs = data >>> i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b = 0; b < 80; b = b + 1) begin + if (srs[b] != (b >= (79 - i) || b == (10 - i))) $stop; + end + end + end + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_shiftrs2.v b/test_regress/t/t_math_shiftrs2.v index e239a918c..f3df398bb 100644 --- a/test_regress/t/t_math_shiftrs2.v +++ b/test_regress/t/t_math_shiftrs2.v @@ -9,16 +9,18 @@ `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on -module top(out35); - output wire [2:0] out35; - wire signed [2:0] wire_4; - assign wire_4 = 3'b011; - assign out35 = (wire_4 >>> 36'hffff_ffff_f); +module top ( + out35 +); + output wire [2:0] out35; + wire signed [2:0] wire_4; + assign wire_4 = 3'b011; + assign out35 = (wire_4 >>> 36'hffff_ffff_f); - initial begin - #10; - `checkd(out35, '0); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + `checkd(out35, '0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_shortcircuit_assocsel.v b/test_regress/t/t_math_shortcircuit_assocsel.v index 3de494fbb..39ad6bbf2 100644 --- a/test_regress/t/t_math_shortcircuit_assocsel.v +++ b/test_regress/t/t_math_shortcircuit_assocsel.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic [31:0] dict [int]; - // verilator lint_off WIDTHTRUNC - function automatic logic f(int a); - int dict_size = dict.size; - logic next_exists = dict.next(a); - // incorrectly inserts element at `a` - logic next_nonzero = !next_exists || (dict[a] != 0); - if (dict_size != dict.size) begin - $display("Assertion failed: dict_size mismatch"); - $display("Initial size: %0d, New size: %0d", dict_size, dict.size); - $display("Dictionary contents:"); - foreach (dict[key]) begin - $display(" Key: %0d, Value: %0d", key, dict[key]); - end - $error; + logic [31:0] dict[int]; + // verilator lint_off WIDTHTRUNC + function automatic logic f(int a); + int dict_size = dict.size; + logic next_exists = dict.next(a); + // incorrectly inserts element at `a` + logic next_nonzero = !next_exists || (dict[a] != 0); + if (dict_size != dict.size) begin + $display("Assertion failed: dict_size mismatch"); + $display("Initial size: %0d, New size: %0d", dict_size, dict.size); + $display("Dictionary contents:"); + foreach (dict[key]) begin + $display(" Key: %0d, Value: %0d", key, dict[key]); end - return next_nonzero; - endfunction - initial begin - automatic logic r = f(0); - $display(r); - $write("*-* All Finished *-*\n"); - $finish; - end + $error; + end + return next_nonzero; + endfunction + initial begin + automatic logic r = f(0); + $display(r); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_shortcircuit_dynsel.v b/test_regress/t/t_math_shortcircuit_dynsel.v index 164f41e02..cca928d72 100644 --- a/test_regress/t/t_math_shortcircuit_dynsel.v +++ b/test_regress/t/t_math_shortcircuit_dynsel.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic [31:0] dict [int] []; - // verilator lint_off WIDTHTRUNC - function automatic logic f(int a); - int dict_size = dict.size; - logic next_exists = dict.next(a); - // incorrectly inserts element at `a` - logic next_nonzero = !next_exists || (dict[a].size != 0); - if (dict_size != dict.size) begin - $display("Assertion failed: dict_size mismatch"); - $display("Initial size: %0d, New size: %0d", dict_size, dict.size); - $display("Dictionary contents:"); - foreach (dict[key]) begin - $display(" Key: %0d, Value: %0d", key, dict[key]); - end - $error; + logic [31:0] dict[int][]; + // verilator lint_off WIDTHTRUNC + function automatic logic f(int a); + int dict_size = dict.size; + logic next_exists = dict.next(a); + // incorrectly inserts element at `a` + logic next_nonzero = !next_exists || (dict[a].size != 0); + if (dict_size != dict.size) begin + $display("Assertion failed: dict_size mismatch"); + $display("Initial size: %0d, New size: %0d", dict_size, dict.size); + $display("Dictionary contents:"); + foreach (dict[key]) begin + $display(" Key: %0d, Value: %0d", key, dict[key]); end - return next_nonzero; - endfunction - initial begin - automatic logic r = f(0); - $display(r); - $write("*-* All Finished *-*\n"); - $finish; - end + $error; + end + return next_nonzero; + endfunction + initial begin + automatic logic r = f(0); + $display(r); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v index 0e525b14d..d8a305268 100644 --- a/test_regress/t/t_math_shortreal.v +++ b/test_regress/t/t_math_shortreal.v @@ -6,138 +6,139 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) +`define is_near_real(a, b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // verilator lint_off SHORTREAL - integer i; - reg [63:0] b; - shortreal r, r2; - integer cyc = 0; + // verilator lint_off SHORTREAL + integer i; + reg [63:0] b; + shortreal r, r2; + integer cyc = 0; - realtime uninit; - initial if (uninit != 0.0) $stop; + realtime uninit; + initial if (uninit != 0.0) $stop; - initial begin - if (1_00_0.0_1 != 1000.01) $stop; - // rtoi truncates - if ($rtoi(36.7) != 36) $stop; - if ($rtoi(36.5) != 36) $stop; - if ($rtoi(36.4) != 36) $stop; - // casting rounds - if ((integer '(36.7)) != 37) $stop; - if ((integer '(36.5)) != 37) $stop; - if ((integer '(36.4)) != 36) $stop; - // assignment rounds - // verilator lint_off REALCVT - i = 36.7; if (i != 37) $stop; - i = 36.5; if (i != 37) $stop; - i = 36.4; if (i != 36) $stop; - r = 10'd38; if (r!=38.0) $stop; - // verilator lint_on REALCVT - // operators - if ((-(1.5)) != -1.5) $stop; - if ((+(1.5)) != 1.5) $stop; - if (((1.5)+(1.25)) != 2.75) $stop; - if (((1.5)-(1.25)) != 0.25) $stop; - if (((1.5)*(1.25)) != 1.875) $stop; - if (((1.5)/(1.25)) != 1.2) $stop; - // - if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 - if (((1.5)!=(2)) != 1'b1) $stop; - if (((1.5)> (2)) != 1'b0) $stop; - if (((1.5)>=(2)) != 1'b0) $stop; - if (((1.5)< (2)) != 1'b1) $stop; - if (((1.5)<=(2)) != 1'b1) $stop; - if (((1.5)==(1.5)) != 1'b1) $stop; - if (((1.5)!=(1.5)) != 1'b0) $stop; - if (((1.5)> (1.5)) != 1'b0) $stop; - if (((1.5)>=(1.5)) != 1'b1) $stop; - if (((1.5)< (1.5)) != 1'b0) $stop; - if (((1.5)<=(1.5)) != 1'b1) $stop; - if (((1.6)==(1.5)) != 1'b0) $stop; - if (((1.6)!=(1.5)) != 1'b1) $stop; - if (((1.6)> (1.5)) != 1'b1) $stop; - if (((1.6)>=(1.5)) != 1'b1) $stop; - if (((1.6)< (1.5)) != 1'b0) $stop; - if (((1.6)<=(1.5)) != 1'b0) $stop; - // - if (((0.0)?(2.0):(1.1)) != 1.1) $stop; - if (((1.5)?(2.0):(1.1)) != 2.0) $stop; - // - if (!1.7) $stop; - if (!(!0.0)) $stop; - if (1.8 && 0.0) $stop; - if (!(1.8 || 0.0)) $stop; - // - i=0; - for (r=1.0; r<2.0; r=r+0.1) i++; - if (i!=10) $stop; - // bug - r = $bitstoshortreal($shortrealtobits(1.414)); - if (r != 1.414) $stop; - end + initial begin + if (1_00_0.0_1 != 1000.01) $stop; + // rtoi truncates + if ($rtoi(36.7) != 36) $stop; + if ($rtoi(36.5) != 36) $stop; + if ($rtoi(36.4) != 36) $stop; + // casting rounds + if ((integer'(36.7)) != 37) $stop; + if ((integer'(36.5)) != 37) $stop; + if ((integer'(36.4)) != 36) $stop; + // assignment rounds + // verilator lint_off REALCVT + i = 36.7; + if (i != 37) $stop; + i = 36.5; + if (i != 37) $stop; + i = 36.4; + if (i != 36) $stop; + r = 10'd38; + if (r != 38.0) $stop; + // verilator lint_on REALCVT + // operators + if ((-(1.5)) != -1.5) $stop; + if ((+(1.5)) != 1.5) $stop; + if (((1.5) + (1.25)) != 2.75) $stop; + if (((1.5) - (1.25)) != 0.25) $stop; + if (((1.5) * (1.25)) != 1.875) $stop; + if (((1.5) / (1.25)) != 1.2) $stop; + // + if (((1.5) == (2)) != 1'b0) $stop; // note 2 becomes real 2.0 + if (((1.5) != (2)) != 1'b1) $stop; + if (((1.5) > (2)) != 1'b0) $stop; + if (((1.5) >= (2)) != 1'b0) $stop; + if (((1.5) < (2)) != 1'b1) $stop; + if (((1.5) <= (2)) != 1'b1) $stop; + if (((1.5) == (1.5)) != 1'b1) $stop; + if (((1.5) != (1.5)) != 1'b0) $stop; + if (((1.5) > (1.5)) != 1'b0) $stop; + if (((1.5) >= (1.5)) != 1'b1) $stop; + if (((1.5) < (1.5)) != 1'b0) $stop; + if (((1.5) <= (1.5)) != 1'b1) $stop; + if (((1.6) == (1.5)) != 1'b0) $stop; + if (((1.6) != (1.5)) != 1'b1) $stop; + if (((1.6) > (1.5)) != 1'b1) $stop; + if (((1.6) >= (1.5)) != 1'b1) $stop; + if (((1.6) < (1.5)) != 1'b0) $stop; + if (((1.6) <= (1.5)) != 1'b0) $stop; + // + if (((0.0) ? (2.0) : (1.1)) != 1.1) $stop; + if (((1.5) ? (2.0) : (1.1)) != 2.0) $stop; + // + if (!1.7) $stop; + if (!(!0.0)) $stop; + if (1.8 && 0.0) $stop; + if (!(1.8 || 0.0)) $stop; + // + i = 0; + for (r = 1.0; r < 2.0; r = r + 0.1) i++; + if (i != 10) $stop; + // bug + r = $bitstoshortreal($shortrealtobits(1.414)); + if (r != 1.414) $stop; + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - end - else if (cyc<90) begin - if ($time != {32'h0, $rtoi($realtime)}) $stop; - if ($itor(cyc) != cyc) $stop; - //Unsup: if ((real `($time)) != $realtime) $stop; - r = $itor(cyc*2); - i = $rtoi(r); - if (i!=cyc*2) $stop; - // - r = $itor(cyc)/1.5; - b = $realtobits(r); - r2 = $bitstoreal(b); - if (r != r2) $stop; - // - // Trust the integer math as a comparison - r = $itor(cyc); - if ($rtoi(-r) != -cyc) $stop; - if ($rtoi(+r) != cyc) $stop; - if ($rtoi(r+2.0) != (cyc+2)) $stop; - if ($rtoi(r-2.0) != (cyc-2)) $stop; - if ($rtoi(r*2.0) != (cyc*2)) $stop; - if ($rtoi(r/2.0) != (cyc/2)) $stop; - r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash - // - r2 = $itor(cyc); - case (r) - (r2-1.0): $stop; - r2: ; - default: $stop; - endcase - // - r = $itor(cyc); - if ((r==50.0) != (cyc==50)) $stop; - if ((r!=50.0) != (cyc!=50)) $stop; - if ((r> 50.0) != (cyc> 50)) $stop; - if ((r>=50.0) != (cyc>=50)) $stop; - if ((r< 50.0) != (cyc< 50)) $stop; - if ((r<=50.0) != (cyc<=50)) $stop; - // - if ($rtoi((r-50.0) ? 10.0 : 20.0) - != (((cyc-50)!=0) ? 10 : 20)) $stop; - // - if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + end + else if (cyc < 90) begin + if ($time != {32'h0, $rtoi($realtime)}) $stop; + if ($itor(cyc) != cyc) $stop; + //Unsup: if ((real `($time)) != $realtime) $stop; + r = $itor(cyc * 2); + i = $rtoi(r); + if (i != cyc * 2) $stop; + // + r = $itor(cyc) / 1.5; + b = $realtobits(r); + r2 = $bitstoreal(b); + if (r != r2) $stop; + // + // Trust the integer math as a comparison + r = $itor(cyc); + if ($rtoi(-r) != -cyc) $stop; + if ($rtoi(+r) != cyc) $stop; + if ($rtoi(r + 2.0) != (cyc + 2)) $stop; + if ($rtoi(r - 2.0) != (cyc - 2)) $stop; + if ($rtoi(r * 2.0) != (cyc * 2)) $stop; + if ($rtoi(r / 2.0) != (cyc / 2)) $stop; + r2 = (2.0 / (r - 60)); // When zero, result indeterminate, but no crash + // + r2 = $itor(cyc); + case (r) + (r2 - 1.0): $stop; + r2: ; + default: $stop; + endcase + // + r = $itor(cyc); + if ((r == 50.0) != (cyc == 50)) $stop; + if ((r != 50.0) != (cyc != 50)) $stop; + if ((r > 50.0) != (cyc > 50)) $stop; + if ((r >= 50.0) != (cyc >= 50)) $stop; + if ((r < 50.0) != (cyc < 50)) $stop; + if ((r <= 50.0) != (cyc <= 50)) $stop; + // + if ($rtoi((r - 50.0) ? 10.0 : 20.0) != (((cyc - 50) != 0) ? 10 : 20)) $stop; + // + if ((!(r - 50.0)) != (!((cyc - 50) != 0))) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_shortreal_unsup_bad.out b/test_regress/t/t_math_shortreal_unsup_bad.out index df3739360..7d1d625b4 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.out +++ b/test_regress/t/t_math_shortreal_unsup_bad.out @@ -1,6 +1,6 @@ -%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) - 9 | shortreal s; - | ^~~~~~~~~ +%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:3: Unsupported: shortreal being promoted to real (suggest use real instead) + 9 | shortreal s; + | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/SHORTREAL?v=latest ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_math_shortreal_unsup_bad.v b/test_regress/t/t_math_shortreal_unsup_bad.v index e01f6b63f..bc732994b 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.v +++ b/test_regress/t/t_math_shortreal_unsup_bad.v @@ -6,8 +6,8 @@ module t; - shortreal s; + shortreal s; - initial s = 1.2345; + initial s = 1.2345; endmodule diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v index ddbd5972f..1b5b707d2 100644 --- a/test_regress/t/t_math_sign_extend.v +++ b/test_regress/t/t_math_sign_extend.v @@ -9,119 +9,119 @@ module t; - localparam [ 0:0] one1_lp = 1; - localparam [ 1:0] one2_lp = 1; - localparam [ 2:0] one3_lp = 1; - localparam [ 3:0] one4_lp = 1; - localparam [ 4:0] one5_lp = 1; - localparam [ 5:0] one6_lp = 1; - localparam [ 6:0] one7_lp = 1; - localparam [ 7:0] one8_lp = 1; - localparam [ 8:0] one9_lp = 1; - localparam [ 9:0] one10_lp = 1; - localparam [19:0] one20_lp = 1; - localparam [29:0] one30_lp = 1; - localparam [30:0] one31_lp = 1; - localparam [31:0] one32_lp = 1; - localparam [32:0] one33_lp = 1; - localparam [33:0] one34_lp = 1; - localparam [34:0] one35_lp = 1; - localparam [35:0] one36_lp = 1; - localparam [36:0] one37_lp = 1; - localparam [37:0] one38_lp = 1; - localparam [38:0] one39_lp = 1; - localparam [39:0] one40_lp = 1; - localparam [49:0] one50_lp = 1; - localparam [59:0] one60_lp = 1; - localparam [60:0] one61_lp = 1; - localparam [61:0] one62_lp = 1; - localparam [62:0] one63_lp = 1; - localparam [63:0] one64_lp = 1; - localparam [64:0] one65_lp = 1; - localparam [65:0] one66_lp = 1; - localparam [66:0] one67_lp = 1; - localparam [67:0] one68_lp = 1; - localparam [68:0] one69_lp = 1; - localparam [69:0] one70_lp = 1; + localparam [0:0] one1_lp = 1; + localparam [1:0] one2_lp = 1; + localparam [2:0] one3_lp = 1; + localparam [3:0] one4_lp = 1; + localparam [4:0] one5_lp = 1; + localparam [5:0] one6_lp = 1; + localparam [6:0] one7_lp = 1; + localparam [7:0] one8_lp = 1; + localparam [8:0] one9_lp = 1; + localparam [9:0] one10_lp = 1; + localparam [19:0] one20_lp = 1; + localparam [29:0] one30_lp = 1; + localparam [30:0] one31_lp = 1; + localparam [31:0] one32_lp = 1; + localparam [32:0] one33_lp = 1; + localparam [33:0] one34_lp = 1; + localparam [34:0] one35_lp = 1; + localparam [35:0] one36_lp = 1; + localparam [36:0] one37_lp = 1; + localparam [37:0] one38_lp = 1; + localparam [38:0] one39_lp = 1; + localparam [39:0] one40_lp = 1; + localparam [49:0] one50_lp = 1; + localparam [59:0] one60_lp = 1; + localparam [60:0] one61_lp = 1; + localparam [61:0] one62_lp = 1; + localparam [62:0] one63_lp = 1; + localparam [63:0] one64_lp = 1; + localparam [64:0] one65_lp = 1; + localparam [65:0] one66_lp = 1; + localparam [66:0] one67_lp = 1; + localparam [67:0] one68_lp = 1; + localparam [68:0] one69_lp = 1; + localparam [69:0] one70_lp = 1; - bit all_ok = 1; + bit all_ok = 1; - initial begin + initial begin `ifdef TEST_VERBOSE - $display("one1_lp : %x %d", one1_lp, one1_lp==1); - $display("one2_lp : %x %d", one2_lp, one2_lp==1); - $display("one3_lp : %x %d", one3_lp, one3_lp==1); - $display("one4_lp : %x %d", one4_lp, one4_lp==1); - $display("one5_lp : %x %d", one5_lp, one5_lp==1); - $display("one6_lp : %x %d", one6_lp, one6_lp==1); - $display("one7_lp : %x %d", one7_lp, one7_lp==1); - $display("one8_lp : %x %d", one8_lp, one8_lp==1); - $display("one9_lp : %x %d", one9_lp, one9_lp==1); - $display("one10_lp: %x %d", one10_lp, one10_lp==1); - $display("one20_lp: %x %d", one20_lp, one20_lp==1); - $display("one30_lp: %x %d", one30_lp, one30_lp==1); - $display("one31_lp: %x %d", one31_lp, one31_lp==1); - $display("one32_lp: %x %d", one32_lp, one32_lp==1); - $display("one33_lp: %x %d", one33_lp, one33_lp==1); - $display("one34_lp: %x %d", one34_lp, one34_lp==1); - $display("one35_lp: %x %d", one35_lp, one35_lp==1); - $display("one36_lp: %x %d", one36_lp, one36_lp==1); - $display("one37_lp: %x %d", one37_lp, one37_lp==1); - $display("one38_lp: %x %d", one38_lp, one38_lp==1); - $display("one39_lp: %x %d", one39_lp, one39_lp==1); - $display("one40_lp: %x %d", one40_lp, one40_lp==1); - $display("one50_lp: %x %d", one50_lp, one50_lp==1); - $display("one60_lp: %x %d", one60_lp, one60_lp==1); - $display("one61_lp: %x %d", one61_lp, one61_lp==1); - $display("one62_lp: %x %d", one62_lp, one62_lp==1); - $display("one63_lp: %x %d", one63_lp, one63_lp==1); - $display("one64_lp: %x %d", one64_lp, one64_lp==1); - $display("one65_lp: %x %d", one65_lp, one65_lp==1); - $display("one66_lp: %x %d", one66_lp, one66_lp==1); - $display("one67_lp: %x %d", one67_lp, one67_lp==1); - $display("one68_lp: %x %d", one68_lp, one68_lp==1); - $display("one69_lp: %x %d", one69_lp, one69_lp==1); - $display("one70_lp: %x %d", one70_lp, one70_lp==1); + $display("one1_lp : %x %d", one1_lp, one1_lp == 1); + $display("one2_lp : %x %d", one2_lp, one2_lp == 1); + $display("one3_lp : %x %d", one3_lp, one3_lp == 1); + $display("one4_lp : %x %d", one4_lp, one4_lp == 1); + $display("one5_lp : %x %d", one5_lp, one5_lp == 1); + $display("one6_lp : %x %d", one6_lp, one6_lp == 1); + $display("one7_lp : %x %d", one7_lp, one7_lp == 1); + $display("one8_lp : %x %d", one8_lp, one8_lp == 1); + $display("one9_lp : %x %d", one9_lp, one9_lp == 1); + $display("one10_lp: %x %d", one10_lp, one10_lp == 1); + $display("one20_lp: %x %d", one20_lp, one20_lp == 1); + $display("one30_lp: %x %d", one30_lp, one30_lp == 1); + $display("one31_lp: %x %d", one31_lp, one31_lp == 1); + $display("one32_lp: %x %d", one32_lp, one32_lp == 1); + $display("one33_lp: %x %d", one33_lp, one33_lp == 1); + $display("one34_lp: %x %d", one34_lp, one34_lp == 1); + $display("one35_lp: %x %d", one35_lp, one35_lp == 1); + $display("one36_lp: %x %d", one36_lp, one36_lp == 1); + $display("one37_lp: %x %d", one37_lp, one37_lp == 1); + $display("one38_lp: %x %d", one38_lp, one38_lp == 1); + $display("one39_lp: %x %d", one39_lp, one39_lp == 1); + $display("one40_lp: %x %d", one40_lp, one40_lp == 1); + $display("one50_lp: %x %d", one50_lp, one50_lp == 1); + $display("one60_lp: %x %d", one60_lp, one60_lp == 1); + $display("one61_lp: %x %d", one61_lp, one61_lp == 1); + $display("one62_lp: %x %d", one62_lp, one62_lp == 1); + $display("one63_lp: %x %d", one63_lp, one63_lp == 1); + $display("one64_lp: %x %d", one64_lp, one64_lp == 1); + $display("one65_lp: %x %d", one65_lp, one65_lp == 1); + $display("one66_lp: %x %d", one66_lp, one66_lp == 1); + $display("one67_lp: %x %d", one67_lp, one67_lp == 1); + $display("one68_lp: %x %d", one68_lp, one68_lp == 1); + $display("one69_lp: %x %d", one69_lp, one69_lp == 1); + $display("one70_lp: %x %d", one70_lp, one70_lp == 1); `endif - all_ok &= one1_lp == 1; - all_ok &= one2_lp == 1; - all_ok &= one3_lp == 1; - all_ok &= one4_lp == 1; - all_ok &= one5_lp == 1; - all_ok &= one6_lp == 1; - all_ok &= one7_lp == 1; - all_ok &= one8_lp == 1; - all_ok &= one9_lp == 1; - all_ok &= one10_lp == 1; - all_ok &= one20_lp == 1; - all_ok &= one30_lp == 1; - all_ok &= one31_lp == 1; - all_ok &= one32_lp == 1; - all_ok &= one33_lp == 1; - all_ok &= one34_lp == 1; - all_ok &= one35_lp == 1; - all_ok &= one36_lp == 1; - all_ok &= one37_lp == 1; - all_ok &= one38_lp == 1; - all_ok &= one39_lp == 1; - all_ok &= one40_lp == 1; - all_ok &= one50_lp == 1; - all_ok &= one60_lp == 1; - all_ok &= one61_lp == 1; - all_ok &= one62_lp == 1; - all_ok &= one63_lp == 1; - all_ok &= one64_lp == 1; - all_ok &= one65_lp == 1; - all_ok &= one66_lp == 1; - all_ok &= one67_lp == 1; - all_ok &= one68_lp == 1; - all_ok &= one69_lp == 1; - all_ok &= one70_lp == 1; + all_ok &= one1_lp == 1; + all_ok &= one2_lp == 1; + all_ok &= one3_lp == 1; + all_ok &= one4_lp == 1; + all_ok &= one5_lp == 1; + all_ok &= one6_lp == 1; + all_ok &= one7_lp == 1; + all_ok &= one8_lp == 1; + all_ok &= one9_lp == 1; + all_ok &= one10_lp == 1; + all_ok &= one20_lp == 1; + all_ok &= one30_lp == 1; + all_ok &= one31_lp == 1; + all_ok &= one32_lp == 1; + all_ok &= one33_lp == 1; + all_ok &= one34_lp == 1; + all_ok &= one35_lp == 1; + all_ok &= one36_lp == 1; + all_ok &= one37_lp == 1; + all_ok &= one38_lp == 1; + all_ok &= one39_lp == 1; + all_ok &= one40_lp == 1; + all_ok &= one50_lp == 1; + all_ok &= one60_lp == 1; + all_ok &= one61_lp == 1; + all_ok &= one62_lp == 1; + all_ok &= one63_lp == 1; + all_ok &= one64_lp == 1; + all_ok &= one65_lp == 1; + all_ok &= one66_lp == 1; + all_ok &= one67_lp == 1; + all_ok &= one68_lp == 1; + all_ok &= one69_lp == 1; + all_ok &= one70_lp == 1; - if (!all_ok) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (!all_ok) $stop; + $write("*-* All Finished *-*\n"); + $finish; - end + end endmodule diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v index 1b51c6f16..6a40b4ec9 100644 --- a/test_regress/t/t_math_signed.v +++ b/test_regress/t/t_math_signed.v @@ -4,203 +4,212 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + by_width #(1) w1 (.clk(clk)); + by_width #(31) w31 (.clk(clk)); + by_width #(32) w32 (.clk(clk)); + by_width #(33) w33 (.clk(clk)); + by_width #(63) w63 (.clk(clk)); + by_width #(64) w64 (.clk(clk)); + by_width #(65) w65 (.clk(clk)); + by_width #(95) w95 (.clk(clk)); + by_width #(96) w96 (.clk(clk)); + by_width #(97) w97 (.clk(clk)); - by_width #(1) w1 (.clk(clk)); - by_width #(31) w31 (.clk(clk)); - by_width #(32) w32 (.clk(clk)); - by_width #(33) w33 (.clk(clk)); - by_width #(63) w63 (.clk(clk)); - by_width #(64) w64 (.clk(clk)); - by_width #(65) w65 (.clk(clk)); - by_width #(95) w95 (.clk(clk)); - by_width #(96) w96 (.clk(clk)); - by_width #(97) w97 (.clk(clk)); + reg signed [15:0] a; + reg signed [4:0] b; - reg signed [15:0] a; - reg signed [4:0] b; + reg signed [15:0] sr, srs, sl, sls; - reg signed [15:0] sr,srs,sl,sls; + reg [15:0] b_s; + reg [15:0] b_us; - reg [15:0] b_s; - reg [15:0] b_us; + task check_s(input signed [7:0] i, input [7:0] expval); + //$display("check_s %x\n", i); + if (i !== expval) $stop; + endtask + task check_us(input signed [7:0] i, input [7:0] expval); + //$display("check_us %x\n", i); + if (i !== expval) $stop; + endtask - task check_s(input signed [7:0] i, input [7:0] expval); - //$display("check_s %x\n", i); - if (i !== expval) $stop; - endtask - task check_us(input signed [7:0] i, input [7:0] expval); - //$display("check_us %x\n", i); - if (i !== expval) $stop; - endtask + always @* begin + sr = a >> b; + srs = copy_signed(a) >>> b; + sl = a << b; + sls = a <<< b; + // verilator lint_off WIDTH + b_s = b >>> 4; // Signed + b_us = b[4:0] >>> 4; // Unsigned, due to extract + check_s(3'b111, 8'h07); + check_s(3'sb111, 8'hff); + check_us(3'b111, 8'h07); + check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements + // verilator lint_on WIDTH + end - always @* begin - sr = a>>b; - srs = copy_signed(a)>>>b; - sl = a<>>4; // Signed - b_us = b[4:0]>>>4; // Unsigned, due to extract - check_s ( 3'b111, 8'h07); - check_s (3'sb111, 8'hff); - check_us( 3'b111, 8'h07); - check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements - // verilator lint_on WIDTH - end + reg signed [32:0] bug349; - reg signed [32:0] bug349; + initial begin + end + integer i; + initial begin + if ((-1 >>> 3) != -1) $stop; // Decimals are signed + // verilator lint_off WIDTH + if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned + if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers + // verilator lint_on WIDTH + if ((3'sb000 > 3'sb000)) $stop; + if (!(3'sb000 > 3'sb111)) $stop; + if ((3'sb111 > 3'sb000)) $stop; + if ((3'sb000 < 3'sb000)) $stop; + if ((3'sb000 < 3'sb111)) $stop; + if (!(3'sb111 < 3'sb000)) $stop; + if (!(3'sb000 >= 3'sb000)) $stop; + if (!(3'sb000 >= 3'sb111)) $stop; + if ((3'sb111 >= 3'sb000)) $stop; + if (!(3'sb000 <= 3'sb000)) $stop; + if ((3'sb000 <= 3'sb111)) $stop; + if (!(3'sb111 <= 3'sb000)) $stop; + // When we multiply overflow, the sign bit stays correct. + if ((4'sd2 * 4'sd8) != 4'd0) $stop; + // From the spec: + // verilator lint_off WIDTH + i = -12 / 3; + if (i !== 32'hfffffffc) $stop; + i = -'d12 / 3; + if (i !== 32'h55555551) $stop; + i = -'sd12 / 3; + if (i !== 32'hfffffffc) $stop; + i = -4'sd12 / 3; + if (i !== 32'h00000001) $stop; + // verilator lint_on WIDTH - initial - begin - end - integer i; - initial begin - if ((-1 >>> 3) != -1) $stop; // Decimals are signed - // verilator lint_off WIDTH - if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned - if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers - // verilator lint_on WIDTH - if ( (3'sb000 > 3'sb000)) $stop; - if (!(3'sb000 > 3'sb111)) $stop; - if ( (3'sb111 > 3'sb000)) $stop; - if ( (3'sb000 < 3'sb000)) $stop; - if ( (3'sb000 < 3'sb111)) $stop; - if (!(3'sb111 < 3'sb000)) $stop; - if (!(3'sb000 >= 3'sb000)) $stop; - if (!(3'sb000 >= 3'sb111)) $stop; - if ( (3'sb111 >= 3'sb000)) $stop; - if (!(3'sb000 <= 3'sb000)) $stop; - if ( (3'sb000 <= 3'sb111)) $stop; - if (!(3'sb111 <= 3'sb000)) $stop; - // When we multiply overflow, the sign bit stays correct. - if ( (4'sd2*4'sd8) != 4'd0) $stop; - // From the spec: - // verilator lint_off WIDTH - i = -12 /3; if (i !== 32'hfffffffc) $stop; - i = -'d12 /3; if (i !== 32'h55555551) $stop; - i = -'sd12 /3; if (i !== 32'hfffffffc) $stop; - i = -4'sd12 /3; if (i !== 32'h00000001) $stop; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + bug349 = 4'sb1111 - 1'b1; + if (bug349 != 32'he) $stop; + end - // verilator lint_off WIDTH - bug349 = 4'sb1111 - 1'b1; - if (bug349 != 32'he) $stop; - end + function signed [15:0] copy_signed; + input [15:0] ai; + copy_signed = ai; + endfunction - function signed [15:0] copy_signed; - input [15:0] ai; - copy_signed = ai; - endfunction - - integer cyc; initial cyc = 0; - wire [31:0] ucyc = cyc; - always @ (posedge clk) begin - cyc <= cyc + 1; + integer cyc; + initial cyc = 0; + wire [31:0] ucyc = cyc; + always @(posedge clk) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us); + $write("%x %x %x %x %x %x %x\n", cyc, sr, srs, sl, sls, b_s, b_us); `endif - case (cyc) - 0: begin - a <= 16'sh8b1b; b <= 5'sh1f; // -1 - end - 1: begin - // Check spaces in constants - a <= 16 'sh 8b1b; b <= 5'sh01; // -1 - end - 2: begin - a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned - if (ucyc / 1 != 32'd2) $stop; - if (ucyc / 2 != 32'd1) $stop; - if (ucyc * 1 != 32'd2) $stop; - if (ucyc * 2 != 32'd4) $stop; - if (ucyc * 3 != 32'd6) $stop; - if (cyc * 32'sd1 != 32'sd2) $stop; - if (cyc * 32'sd2 != 32'sd4) $stop; - if (cyc * 32'sd3 != 32'sd6) $stop; - end - 3: begin - a <= 16'sh0048; b <= 5'sh1f; - if (ucyc * 1 != 32'd3) $stop; - if (ucyc * 2 != 32'd6) $stop; - if (ucyc * 3 != 32'd9) $stop; - if (ucyc * 4 != 32'd12) $stop; - if (cyc * 32'sd1 != 32'sd3) $stop; - if (cyc * 32'sd2 != 32'sd6) $stop; - if (cyc * 32'sd3 != 32'sd9) $stop; - end - 4: begin - a <= 16'sh4154; b <= 5'sh02; - end - 5: begin - a <= 16'shc3e8; b <= 5'sh12; - end - 6: begin - a <= 16'sh488b; b <= 5'sh02; - end - 9: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - case (cyc) - 0: ; - 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; - 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; - 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; - 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; - 8: ; - 9: ; - endcase - end + case (cyc) + 0: begin + a <= 16'sh8b1b; + b <= 5'sh1f; // -1 + end + 1: begin + // Check spaces in constants + a <= 16'sh8b1b; + b <= 5'sh01; // -1 + end + 2: begin + a <= 16'sh8b1b; + b <= 5'sh1e; // shift AMOUNT is really unsigned + if (ucyc / 1 != 32'd2) $stop; + if (ucyc / 2 != 32'd1) $stop; + if (ucyc * 1 != 32'd2) $stop; + if (ucyc * 2 != 32'd4) $stop; + if (ucyc * 3 != 32'd6) $stop; + if (cyc * 32'sd1 != 32'sd2) $stop; + if (cyc * 32'sd2 != 32'sd4) $stop; + if (cyc * 32'sd3 != 32'sd6) $stop; + end + 3: begin + a <= 16'sh0048; + b <= 5'sh1f; + if (ucyc * 1 != 32'd3) $stop; + if (ucyc * 2 != 32'd6) $stop; + if (ucyc * 3 != 32'd9) $stop; + if (ucyc * 4 != 32'd12) $stop; + if (cyc * 32'sd1 != 32'sd3) $stop; + if (cyc * 32'sd2 != 32'sd6) $stop; + if (cyc * 32'sd3 != 32'sd9) $stop; + end + 4: begin + a <= 16'sh4154; + b <= 5'sh02; + end + 5: begin + a <= 16'shc3e8; + b <= 5'sh12; + end + 6: begin + a <= 16'sh488b; + b <= 5'sh02; + end + 9: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 0: ; + 1: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 2: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh458d_c58d_1636_1636_0000_0000) $stop; + 3: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 4: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh0000_0000_0000_0000_ffff_0001) $stop; + 5: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh1055_1055_0550_0550_0000_0000) $stop; + 6: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 7: if ({sr, srs, sl, sls, b_s, b_us} !== 96'sh1222_1222_222c_222c_0000_0000) $stop; + 8: ; + 9: ; + endcase + end endmodule module by_width ( - input clk - ); - parameter WIDTH=1; + input clk +); + parameter WIDTH = 1; - reg signed i1; - reg signed [62:0] i63; - reg signed [64:0] i65; + reg signed i1; + reg signed [62:0] i63; + reg signed [64:0] i65; - // verilator lint_off WIDTH - wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1; - wire signed [WIDTH-1:0] i1ext = i1; - wire signed [WIDTH-1:0] i63ext = i63; - wire signed [WIDTH-1:0] i65ext = i65; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1; + wire signed [WIDTH-1:0] i1ext = i1; + wire signed [WIDTH-1:0] i63ext = i63; + wire signed [WIDTH-1:0] i65ext = i65; + // verilator lint_on WIDTH - integer cyc; initial cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - i1 <= cyc[0]; - i63 <= {63{cyc[0]}}; - i65 <= {65{cyc[0]}}; - case (cyc) - 1: begin - if (i1extp != {WIDTH{1'b0}}) $stop; - if (i1ext != {WIDTH{1'b0}}) $stop; - if (i63ext != {WIDTH{1'b0}}) $stop; - if (i65ext != {WIDTH{1'b0}}) $stop; - end - 2: begin - if (i1extp != {WIDTH{1'b1}}) $stop; - if (i1ext != {WIDTH{1'b1}}) $stop; - if (i63ext != {WIDTH{1'b1}}) $stop; - if (i65ext != {WIDTH{1'b1}}) $stop; - end - default: ; - endcase - end + integer cyc; + initial cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + i1 <= cyc[0]; + i63 <= {63{cyc[0]}}; + i65 <= {65{cyc[0]}}; + case (cyc) + 1: begin + if (i1extp != {WIDTH{1'b0}}) $stop; + if (i1ext != {WIDTH{1'b0}}) $stop; + if (i63ext != {WIDTH{1'b0}}) $stop; + if (i65ext != {WIDTH{1'b0}}) $stop; + end + 2: begin + if (i1extp != {WIDTH{1'b1}}) $stop; + if (i1ext != {WIDTH{1'b1}}) $stop; + if (i63ext != {WIDTH{1'b1}}) $stop; + if (i65ext != {WIDTH{1'b1}}) $stop; + end + default: ; + endcase + end endmodule diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v index e136f6498..ae98cd6ab 100644 --- a/test_regress/t/t_math_signed3.v +++ b/test_regress/t/t_math_signed3.v @@ -4,137 +4,144 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - // verilator lint_off WIDTH - wire [1:0] bug729_au = ~0; - wire signed [1:0] bug729_as = ~0; - wire [2:0] bug729_b = ~0; - // the $signed output is unsigned because the input is unsigned; the signedness does not change. - wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 - wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 - wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 - wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 - wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 - wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 - wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 - wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 + // verilator lint_off WIDTH + wire [1:0] bug729_au = ~0; + wire signed [1:0] bug729_as = ~0; + wire [2:0] bug729_b = ~0; + // the $signed output is unsigned because the input is unsigned; the signedness does not change. + wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 + wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 + wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 + wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 + wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 + wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 - wire [3:0] bug733_a = 4'b0010; - wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned - wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 + wire [3:0] bug733_a = 4'b0010; + wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned + wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 - wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 - wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 + wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 + wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 - // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign + // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign - wire [3:0] bug733_qu = 2'sb11; // 4'b1111 - wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 - reg signed [32:0] bug349_s; - reg signed [32:0] bug349_u; + wire [3:0] bug733_qu = 2'sb11; // 4'b1111 + wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 + reg signed [32:0] bug349_s; + reg signed [32:0] bug349_u; - wire signed [1:0] sb11 = 2'sb11; + wire signed [1:0] sb11 = 2'sb11; - wire [3:0] subout_u; - sub sub (.a(2'sb11), .z(subout_u)); - initial begin - #1; - `checkh(subout_u, 4'b1111); - end + wire [3:0] subout_u; + sub sub ( + .a(2'sb11), + .z(subout_u) + ); + initial begin + #1; + `checkh(subout_u, 4'b1111); + end - wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; - initial begin - #1; - `checkh(cond_a, 6'b111111); - end + wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; + initial begin + #1; + `checkh(cond_a, 6'b111111); + end - wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; - initial begin - #1; - `checkh(cond_b, 6'b111111); - end + wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; + initial begin + #1; + `checkh(cond_b, 6'b111111); + end - bit cmp; + bit cmp; - initial begin - #1; + initial begin + #1; - // verilator lint_on WIDTH - `checkh(bug729_yuu, 1'b0); - `checkh(bug729_ysu, 1'b0); - `checkh(bug729_yus, 1'b1); - `checkh(bug729_yss, 1'b1); + // verilator lint_on WIDTH + `checkh(bug729_yuu, 1'b0); + `checkh(bug729_ysu, 1'b0); + `checkh(bug729_yus, 1'b1); + `checkh(bug729_yss, 1'b1); - `checkh(bug729_zuu, 1'b0); - `checkh(bug729_zsu, 1'b0); - `checkh(bug729_zus, 1'b1); - `checkh(bug729_zss, 1'b1); + `checkh(bug729_zuu, 1'b0); + `checkh(bug729_zsu, 1'b0); + `checkh(bug729_zus, 1'b1); + `checkh(bug729_zss, 1'b1); - `checkh(bug733_yu, 4'b1111); - `checkh(bug733_ys, 4'b1111); + `checkh(bug733_yu, 4'b1111); + `checkh(bug733_ys, 4'b1111); - `checkh(bug733_zu, 4'b1111); - `checkh(bug733_zs, 4'b1111); + `checkh(bug733_zu, 4'b1111); + `checkh(bug733_zs, 4'b1111); - `checkh(bug733_qu, 4'b1111); - `checkh(bug733_qs, 4'b1111); + `checkh(bug733_qu, 4'b1111); + `checkh(bug733_qs, 4'b1111); - // verilator lint_off WIDTH - bug349_s = 4'sb1111; - `checkh(bug349_s, 33'h1ffffffff); - bug349_u = 4'sb1111; - `checkh(bug349_u, 33'h1ffffffff); + // verilator lint_off WIDTH + bug349_s = 4'sb1111; + `checkh(bug349_s, 33'h1ffffffff); + bug349_u = 4'sb1111; + `checkh(bug349_u, 33'h1ffffffff); - bug349_s = 4'sb1111 - 1'b1; - `checkh(bug349_s,33'he); + bug349_s = 4'sb1111 - 1'b1; + `checkh(bug349_s, 33'he); - bug349_s = 4'sb1111 - 5'b00001; - `checkh(bug349_s,33'he); + bug349_s = 4'sb1111 - 5'b00001; + `checkh(bug349_s, 33'he); - cmp = 3'sb111 == 4'b111; - `checkh(cmp, 1); - cmp = 3'sb111 == 4'sb111; - `checkh(cmp, 0); - cmp = 3'sb111 != 4'b111; - `checkh(cmp, 0); - cmp = 3'sb111 != 4'sb111; - `checkh(cmp, 1); + cmp = 3'sb111 == 4'b111; + `checkh(cmp, 1); + cmp = 3'sb111 == 4'sb111; + `checkh(cmp, 0); + cmp = 3'sb111 != 4'b111; + `checkh(cmp, 0); + cmp = 3'sb111 != 4'sb111; + `checkh(cmp, 1); - cmp = 3'sb111 === 4'b111; - `checkh(cmp, 1); - cmp = 3'sb111 === 4'sb111; - `checkh(cmp, 0); + cmp = 3'sb111 === 4'b111; + `checkh(cmp, 1); + cmp = 3'sb111 === 4'sb111; + `checkh(cmp, 0); - case (2'sb11) - 4'b1111: $stop; - default: ; - endcase + case (2'sb11) + 4'b1111: $stop; + default: ; + endcase - case (sb11) - 4'b1111: $stop; - default: ; - endcase + case (sb11) + 4'b1111: $stop; + default: ; + endcase - case (2'sb11) - 4'sb1111: ; - default: $stop; - endcase + case (2'sb11) + 4'sb1111: ; + default: $stop; + endcase - case (sb11) - 4'sb1111: ; - default: $stop; - endcase + case (sb11) + 4'sb1111: ; + default: $stop; + endcase - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub(input [3:0] a, - output [3:0] z); - assign z = a; +module sub ( + input [3:0] a, + output [3:0] z +); + assign z = a; endmodule diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v index 1cf044432..bb5d83602 100644 --- a/test_regress/t/t_math_signed4.v +++ b/test_regress/t/t_math_signed4.v @@ -4,138 +4,140 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) +// verilog_format: on module t; - bit fail; + bit fail; - localparam signed [3:0] bug737_p1 = 4'b1000; + localparam signed [3:0] bug737_p1 = 4'b1000; - wire [3:0] bug737_a = 4'b1010; - reg [5:0] bug737_y; - reg signed [3:0] w4_s; - reg signed [4:0] w5_s; - reg [3:0] w4_u; - reg [4:0] w5_u; - reg signed [8:0] w9_s; - real r; - initial begin - // verilator lint_off WIDTH - bug737_y = bug737_a + (bug737_p1 + 4'sb0); - `checkh(bug737_y, 6'b010010); //bug737 + wire [3:0] bug737_a = 4'b1010; + reg [5:0] bug737_y; + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg signed [8:0] w9_s; + real r; + initial begin + // verilator lint_off WIDTH + bug737_y = bug737_a + (bug737_p1 + 4'sb0); + `checkh(bug737_y, 6'b010010); //bug737 - // 6u +[6u] 4s +[6s] 6s - bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); - `checkh(bug737_y, 6'b010010); //bug737, getx 000010 + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //bug737, getx 000010 - // 6u +[6u] 4s +[6s] 6s - bug737_y = 6'b001010 + (4'b1000 + 6'sb0); - `checkh(bug737_y, 6'b010010); //ok + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'b1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //ok - bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); - `checkh(bug737_y, 6'b000010); //ok + bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok - // v--- sign extends to 6-bits - bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); - `checkh(bug737_y, 6'b000010); //ok + // v--- sign extends to 6-bits + bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok - // From t_math_signed_3 - w4_s = 4'sb1111 - 1'b1; - `checkh(w4_s,33'he); + // From t_math_signed_3 + w4_s = 4'sb1111 - 1'b1; + `checkh(w4_s, 33'he); - w4_s = 4'sb1111 - 5'b00001; - `checkh(w4_s,33'he); + w4_s = 4'sb1111 - 5'b00001; + `checkh(w4_s, 33'he); - w4_s = 4'sb1111 - 1'sb1; - `checkh(w4_s,4'h0); - w5_s = 4'sb1111 - 1'sb1; - `checkh(w5_s,4'h0); + w4_s = 4'sb1111 - 1'sb1; + `checkh(w4_s, 4'h0); + w5_s = 4'sb1111 - 1'sb1; + `checkh(w5_s, 4'h0); - w4_s = 4'sb1111 - 4'sb1111; - `checkh(w4_s,4'h0); - w5_s = 4'sb1111 - 4'sb1111; - `checkh(w5_s,5'h0); + w4_s = 4'sb1111 - 4'sb1111; + `checkh(w4_s, 4'h0); + w5_s = 4'sb1111 - 4'sb1111; + `checkh(w5_s, 5'h0); - // The assign LHS being signed or unsigned does not matter per IEEE - // The upper add being signed DOES matter propagating to lower - w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add - `checkh(w4_s,4'he); - w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend - `checkh(w4_s,4'h0); - w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend - `checkh(w4_s,4'he); // BUG, Verilator says 'h0 + // The assign LHS being signed or unsigned does not matter per IEEE + // The upper add being signed DOES matter propagating to lower + w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add + `checkh(w4_s, 4'he); + w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend + `checkh(w4_s, 4'h0); + w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend + `checkh(w4_s, 4'he); // BUG, Verilator says 'h0 - w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS - `checkh(w5_u, 5'b10000); - w4_u = 4'b1111 + 4'b0001; // Normal case - `checkh(w4_u, 4'b0000); + w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS + `checkh(w5_u, 5'b10000); + w4_u = 4'b1111 + 4'b0001; // Normal case + `checkh(w4_u, 4'b0000); - // Another example of promotion, the add is 4 bits wide - w4_u = 3'b111 + 3'b010; - `checkh(w4_u, 4'b1001); - // - w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter - `checkh(w4_u, 4'sb1111); - w4_s = 3'sb111 * 3'sb001; // Signed output - `checkh(w4_s, 4'sb1111); - w4_s = 3'b111 * 3'sb001; // Unsigned output - `checkh(w4_s, 4'b0111); + // Another example of promotion, the add is 4 bits wide + w4_u = 3'b111 + 3'b010; + `checkh(w4_u, 4'b1001); + // + w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter + `checkh(w4_u, 4'sb1111); + w4_s = 3'sb111 * 3'sb001; // Signed output + `checkh(w4_s, 4'sb1111); + w4_s = 3'b111 * 3'sb001; // Unsigned output + `checkh(w4_s, 4'b0111); - // Conditionals get width from parent; are assignment-like - w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11); - `checkh(w4_u, 4'b0100); - w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000); - `checkh(w4_u, 4'b0000); + // Conditionals get width from parent; are assignment-like + w4_u = 1'b0 ? 4'b0 : (2'b01 + 2'b11); + `checkh(w4_u, 4'b0100); + w4_u = 1'b0 ? 4'b0 : (6'b001000 + 6'b001000); + `checkh(w4_u, 4'b0000); - // If RHS is larger, that larger size is used - w4_u = 5'b10000 / 5'b00100; - `checkh(w4_u, 4'b0100); + // If RHS is larger, that larger size is used + w4_u = 5'b10000 / 5'b00100; + `checkh(w4_u, 4'b0100); - // bug754 - w5_u = 4'sb0010 << -2'sd1; // << 3 + // bug754 + w5_u = 4'sb0010 << -2'sd1; // << 3 `ifdef VCS - `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug + `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug `else - `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug + `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug `endif - w5_u = 4'sb1000 << 0; // Sign extends - `checkh(w5_u, 5'b11000); + w5_u = 4'sb1000 << 0; // Sign extends + `checkh(w5_u, 5'b11000); - // Reals do not propagate to children - r = 1.0 + ( 1 + (1 / 2)); - `checkf(r, 2.0); + // Reals do not propagate to children + r = 1.0 + (1 + (1 / 2)); + `checkf(r, 2.0); - // Self determined sign extension - r = $itor(3'sb111); - `checkf(r, -1.0); + // Self determined sign extension + r = $itor(3'sb111); + `checkf(r, -1.0); - // If any part of case is real, all is real - case (22) - 22.0: ; - 22.1: $stop; - default: $stop; - endcase + // If any part of case is real, all is real + case (22) + 22.0: ; + 22.1: $stop; + default: $stop; + endcase - // bug759 - w5_u = { -4'sd7 }; - `checkh(w5_u, 5'b01001); - w5_u = {2{ -2'sd1 }}; - `checkh(w5_u, 5'b01111); - // Don't break concats.... - w5_u = {{0{1'b1}}, -4'sd7 }; - `checkh(w5_u, 5'b01001); - w9_s = { -4'sd7, -4'sd7 }; - `checkh(w9_s, 9'b010011001); - {w5_u, {w4_u}} = 9'b10101_1100; - `checkh(w5_u, 5'b10101); - `checkh(w4_u, 4'b1100); - {w4_u} = 4'b1011; - `checkh(w4_u, 4'b1011); + // bug759 + w5_u = {-4'sd7}; + `checkh(w5_u, 5'b01001); + w5_u = {2{-2'sd1}}; + `checkh(w5_u, 5'b01111); + // Don't break concats.... + w5_u = {{0{1'b1}}, -4'sd7}; + `checkh(w5_u, 5'b01001); + w9_s = {-4'sd7, -4'sd7}; + `checkh(w9_s, 9'b010011001); + {w5_u, {w4_u}} = 9'b10101_1100; + `checkh(w5_u, 5'b10101); + `checkh(w4_u, 4'b1100); + {w4_u} = 4'b1011; + `checkh(w4_u, 4'b1011); - if (fail) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (fail) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_signed7.v b/test_regress/t/t_math_signed7.v index 0752ba9ba..d3dbdde9b 100644 --- a/test_regress/t/t_math_signed7.v +++ b/test_regress/t/t_math_signed7.v @@ -4,43 +4,44 @@ // SPDX-FileCopyrightText: 2015 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg alu_ltu, alu_lts; - logic [3:0] in_op1; - logic [3:0] in_op2; + reg alu_ltu, alu_lts; + logic [3:0] in_op1; + logic [3:0] in_op2; - reg aaa_ltu, aaa_lts; + reg aaa_ltu, aaa_lts; + always @(posedge clk) begin + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + aaa_ltu = in_op1 < in_op2; + // bug999 + aaa_lts = $signed(in_op1) < $signed(in_op2); + `checkh(aaa_ltu, 1'b0); + `checkh(aaa_lts, 1'b1); + end + + generate + if (1) begin always @(posedge clk) begin - in_op1 = 4'sb1110; - in_op2 = 4'b0010; - aaa_ltu = in_op1 < in_op2; - // bug999 - aaa_lts = $signed(in_op1) < $signed(in_op2); - `checkh (aaa_ltu, 1'b0); - `checkh (aaa_lts, 1'b1); + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + alu_ltu = in_op1 < in_op2; + // bug999 + alu_lts = $signed(in_op1) < $signed(in_op2); + `checkh(alu_ltu, 1'b0); + `checkh(alu_lts, 1'b1); + $write("*-* All Finished *-*\n"); + $finish; end - - generate if (1) begin - always @(posedge clk) begin - in_op1 = 4'sb1110; - in_op2 = 4'b0010; - alu_ltu = in_op1 < in_op2; - // bug999 - alu_lts = $signed(in_op1) < $signed(in_op2); - `checkh (alu_ltu, 1'b0); - `checkh (alu_lts, 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end - end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_math_signed_calc.v b/test_regress/t/t_math_signed_calc.v index 44f9329bd..e7efd7798 100644 --- a/test_regress/t/t_math_signed_calc.v +++ b/test_regress/t/t_math_signed_calc.v @@ -8,40 +8,46 @@ // SPDX-License-Identifier: CC0-1.0 // issure 3294 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [7:0] in0; - reg [7:0] in1; - reg [15:0] out; - initial begin - in0 = 'h2; - in1 = 'hff; - end - Test test(.in0, .in1, .out); + reg [7:0] in0; + reg [7:0] in1; + reg [15:0] out; + initial begin + in0 = 'h2; + in1 = 'hff; + end + Test test ( + .in0, + .in1, + .out + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out); + $display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out); `endif - if (out !== 'hfffe) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (out !== 'hfffe) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test(in0, in1, out); +module Test ( + in0, + in1, + out +); input [7:0] in0; input [7:0] in1; - output [15:0] out; + output [15:0] out; wire signed [7:0] in1; wire signed [7:0] in0; wire signed [15:0] out; - assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication + assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication endmodule diff --git a/test_regress/t/t_math_signed_wire.v b/test_regress/t/t_math_signed_wire.v index a617bd695..ea5640007 100644 --- a/test_regress/t/t_math_signed_wire.v +++ b/test_regress/t/t_math_signed_wire.v @@ -5,50 +5,52 @@ // SPDX-License-Identifier: CC0-1.0 // bug511 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire [7:0] au; - wire [7:0] as; + wire [7:0] au; + wire [7:0] as; - Test1 test1 (.au); - Test2 test2 (.as); + Test1 test1 (.au); + Test2 test2 (.as); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] result=%x %x\n", $time, au, as); + $write("[%0t] result=%x %x\n", $time, au, as); `endif - if (au != 'h12) $stop; - if (as != 'h02) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (au != 'h12) $stop; + if (as != 'h02) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test1 (output [7:0] au); - wire [7:0] b; - wire signed [3:0] c; +module Test1 ( + output [7:0] au +); + wire [7:0] b; + wire signed [3:0] c; - // verilator lint_off WIDTH - assign c=-1; // 'hf - assign b=3; // 'h3 - assign au=b+c; // 'h12 - // verilator lint_on WIDTH + // verilator lint_off WIDTH + assign c = -1; // 'hf + assign b = 3; // 'h3 + assign au = b + c; // 'h12 + // verilator lint_on WIDTH endmodule -module Test2 (output [7:0] as); - wire signed [7:0] b; - wire signed [3:0] c; +module Test2 ( + output [7:0] as +); + wire signed [7:0] b; + wire signed [3:0] c; - // verilator lint_off WIDTH - assign c=-1; // 'hf - assign b=3; // 'h3 - assign as=b+c; // 'h12 - // verilator lint_on WIDTH + // verilator lint_off WIDTH + assign c = -1; // 'hf + assign b = 3; // 'h3 + assign as = b + c; // 'h12 + // verilator lint_on WIDTH endmodule diff --git a/test_regress/t/t_math_strwidth.v b/test_regress/t/t_math_strwidth.v index 17fba34a6..2dec6a7f7 100644 --- a/test_regress/t/t_math_strwidth.v +++ b/test_regress/t/t_math_strwidth.v @@ -6,15 +6,15 @@ module t; - reg [4*8:1] strg; + reg [4*8:1] strg; - initial begin - strg = "CHK"; - if (strg != "CHK") $stop; - if (strg == "JOE") $stop; - $write("String = %s = %x\n", strg, strg); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + strg = "CHK"; + if (strg != "CHK") $stop; + if (strg == "JOE") $stop; + $write("String = %s = %x\n", strg, strg); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 568e94980..503be728f 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -4,147 +4,148 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - reg [15:0] l; - reg [49:0] q; - reg [79:0] w; - int lc; - reg lo; - reg l0; - int qc; - reg qo; - reg q0; - int wc; - reg wo; - reg w0; + reg [15:0] l; + reg [49:0] q; + reg [79:0] w; + int lc; + reg lo; + reg l0; + int qc; + reg qo; + reg q0; + int wc; + reg wo; + reg w0; - always @* begin - lc = $countones(l); - lo = $onehot(l); - l0 = $onehot0(l); - wc = $countones(w); - wo = $onehot(w); - w0 = $onehot0(w); - qc = $countones(q); - qo = $onehot(q); - q0 = $onehot0(q); - end + always @* begin + lc = $countones(l); + lo = $onehot(l); + l0 = $onehot0(l); + wc = $countones(w); + wo = $onehot(w); + w0 = $onehot0(w); + qc = $countones(q); + qo = $onehot(q); + q0 = $onehot0(q); + end - integer cyc; initial cyc=1; - integer cyc_com; - always_comb begin - cyc_com = cyc; - end + integer cyc; + initial cyc = 1; + integer cyc_com; + always_comb begin + cyc_com = cyc; + end - integer cyc_d1; - always_ff @ (posedge clk) begin - cyc_d1 <= cyc_com; - end + integer cyc_d1; + always_ff @(posedge clk) begin + cyc_d1 <= cyc_com; + end - initial begin - // Constification check - if ($countones(32'b11001011101) != 7) $stop; - if ($countones(32'b0) != 0) $stop; - if ($isunknown(32'b11101x11111) != 1) $stop; - if ($isunknown(32'b11101011111) != 0) $stop; - if ($isunknown(32'b10zzzzzzzzz) != 1) $stop; - if ($bits(0) != 32'd32) $stop; - if ($bits(lc) != 32) $stop; - if ($onehot(32'b00000001000000) != 1'b1) $stop; - if ($onehot(32'b00001001000000) != 1'b0) $stop; - if ($onehot(32'b0) != 1'b0) $stop; - if ($onehot0(32'b00000001000000) != 1'b1) $stop; - if ($onehot0(32'b00001001000000) != 1'b0) $stop; - if ($onehot0(32'b0) != 1'b1) $stop; - end + initial begin + // Constification check + if ($countones(32'b11001011101) != 7) $stop; + if ($countones(32'b0) != 0) $stop; + if ($isunknown(32'b11101x11111) != 1) $stop; + if ($isunknown(32'b11101011111) != 0) $stop; + if ($isunknown(32'b10zzzzzzzzz) != 1) $stop; + if ($bits(0) != 32'd32) $stop; + if ($bits(lc) != 32) $stop; + if ($onehot(32'b00000001000000) != 1'b1) $stop; + if ($onehot(32'b00001001000000) != 1'b0) $stop; + if ($onehot(32'b0) != 1'b0) $stop; + if ($onehot0(32'b00000001000000) != 1'b1) $stop; + if ($onehot0(32'b00001001000000) != 1'b0) $stop; + if ($onehot0(32'b0) != 1'b1) $stop; + end - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", - // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); - if (cyc_com != cyc_com) $stop; - if (cyc_d1 != cyc-1) $stop; - if (cyc==1) begin - l <= 16'b0; - q <= 50'h0; - w <= 80'h0; - end - if (cyc==2) begin - l <= ~16'b0; - q <= ~50'h0; - w <= ~80'h0; - // - if ({lc,lo,l0} != {32'd0,1'b0,1'b1}) $stop; - if ({qc,qo,q0} != {32'd0,1'b0,1'b1}) $stop; - if ({wc,wo,w0} != {32'd0,1'b0,1'b1}) $stop; - end - if (cyc==3) begin - l <= 16'b0010110010110111; - q <= 50'h01_1111_0001; - w <= 80'h0100_0000_0f00_00f0_0000; - // - if ({lc,lo,l0} != {32'd16,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {32'd50,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {32'd80,1'b0,1'b0}) $stop; - end - if (cyc==4) begin - l <= 16'b0000010000000000; - q <= 50'h1_0000_0000; - w <= 80'h010_00000000_00000000; - // - if ({lc,lo,l0} != {32'd9,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {32'd6,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {32'd9,1'b0,1'b0}) $stop; - end - if (cyc==5) begin - l <= 16'b0000000100000000; - q <= 50'h8000_0000_0000; - w <= 80'h10_00000000_00000000; - // - if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop; - if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop; - if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop; - end - if (cyc==6) begin - l <= 16'b0000100100000000; - q <= 50'h01_00000100; - w <= 80'h01_00000100_00000000; - // - if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop; - if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop; - if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop; - end - if (cyc==7) begin - // - if ({lc,lo,l0} != {32'd2,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {32'd2,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {32'd2,1'b0,1'b0}) $stop; - end - if (cyc==8) begin - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", + // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); + if (cyc_com != cyc_com) $stop; + if (cyc_d1 != cyc - 1) $stop; + if (cyc == 1) begin + l <= 16'b0; + q <= 50'h0; + w <= 80'h0; end - end + if (cyc == 2) begin + l <= ~16'b0; + q <= ~50'h0; + w <= ~80'h0; + // + if ({lc, lo, l0} != {32'd0, 1'b0, 1'b1}) $stop; + if ({qc, qo, q0} != {32'd0, 1'b0, 1'b1}) $stop; + if ({wc, wo, w0} != {32'd0, 1'b0, 1'b1}) $stop; + end + if (cyc == 3) begin + l <= 16'b0010110010110111; + q <= 50'h01_1111_0001; + w <= 80'h0100_0000_0f00_00f0_0000; + // + if ({lc, lo, l0} != {32'd16, 1'b0, 1'b0}) $stop; + if ({qc, qo, q0} != {32'd50, 1'b0, 1'b0}) $stop; + if ({wc, wo, w0} != {32'd80, 1'b0, 1'b0}) $stop; + end + if (cyc == 4) begin + l <= 16'b0000010000000000; + q <= 50'h1_0000_0000; + w <= 80'h010_00000000_00000000; + // + if ({lc, lo, l0} != {32'd9, 1'b0, 1'b0}) $stop; + if ({qc, qo, q0} != {32'd6, 1'b0, 1'b0}) $stop; + if ({wc, wo, w0} != {32'd9, 1'b0, 1'b0}) $stop; + end + if (cyc == 5) begin + l <= 16'b0000000100000000; + q <= 50'h8000_0000_0000; + w <= 80'h10_00000000_00000000; + // + if ({lc, lo, l0} != {32'd1, 1'b1, 1'b1}) $stop; + if ({qc, qo, q0} != {32'd1, 1'b1, 1'b1}) $stop; + if ({wc, wo, w0} != {32'd1, 1'b1, 1'b1}) $stop; + end + if (cyc == 6) begin + l <= 16'b0000100100000000; + q <= 50'h01_00000100; + w <= 80'h01_00000100_00000000; + // + if ({lc, lo, l0} != {32'd1, 1'b1, 1'b1}) $stop; + if ({qc, qo, q0} != {32'd1, 1'b1, 1'b1}) $stop; + if ({wc, wo, w0} != {32'd1, 1'b1, 1'b1}) $stop; + end + if (cyc == 7) begin + // + if ({lc, lo, l0} != {32'd2, 1'b0, 1'b0}) $stop; + if ({qc, qo, q0} != {32'd2, 1'b0, 1'b0}) $stop; + if ({wc, wo, w0} != {32'd2, 1'b0, 1'b0}) $stop; + end + if (cyc == 8) begin + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - initial begin - if ($isunknown(4'b000x) !== 1'b1) $stop; - if ($isunknown(4'b000z) !== 1'b1) $stop; - if ($isunknown(4'b00xz) !== 1'b1) $stop; - if ($isunknown(4'b0000) !== 1'b0) $stop; - end + initial begin + if ($isunknown(4'b000x) !== 1'b1) $stop; + if ($isunknown(4'b000z) !== 1'b1) $stop; + if ($isunknown(4'b00xz) !== 1'b1) $stop; + if ($isunknown(4'b0000) !== 1'b0) $stop; + end - final begin - $write("Goodbye world, at cycle %0d\n", cyc); - end + final begin + $write("Goodbye world, at cycle %0d\n", cyc); + end endmodule diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v index 8159f586e..b6049d112 100644 --- a/test_regress/t/t_math_svl2.v +++ b/test_regress/t/t_math_svl2.v @@ -4,38 +4,36 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - // New number format - if ('0 !== {66{1'b0}}) $stop; - if ('1 !== {66{1'b1}}) $stop; - if ('x !== {66{1'bx}}) $stop; - if ('z !== {66{1'bz}}) $stop; -`ifndef NC // NC-Verilog 5.50-s09 chokes on this test - if ("\v" != 8'd11) $stop; - if ("\f" != 8'd12) $stop; - if ("\a" != 8'd7) $stop; - if ("\x9a" != 8'h9a) $stop; - if ("\xf1" != 8'hf1) $stop; + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + // New number format + if ('0 !== {66{1'b0}}) $stop; + if ('1 !== {66{1'b1}}) $stop; + if ('x !== {66{1'bx}}) $stop; + if ('z !== {66{1'bz}}) $stop; +`ifndef NC // NC-Verilog 5.50-s09 chokes on this test + if ("\v" != 8'd11) $stop; + if ("\f" != 8'd12) $stop; + if ("\a" != 8'd7) $stop; + if ("\x9a" != 8'h9a) $stop; + if ("\xf1" != 8'hf1) $stop; `endif - end - if (cyc==8) begin - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc == 8) begin + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v index 189ba4c51..3c75e5839 100644 --- a/test_regress/t/t_math_swap.v +++ b/test_regress/t/t_math_swap.v @@ -4,162 +4,165 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] Operand1 = crc[31:0]; - wire [15:0] Operand2 = crc[47:32]; - wire Unsigned = crc[48]; - reg rst; + // Take CRC data and apply to testblock inputs + wire [31:0] Operand1 = crc[31:0]; + wire [15:0] Operand2 = crc[47:32]; + wire Unsigned = crc[48]; + reg rst; - parameter WL = 16; + parameter WL = 16; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [WL-1:0] Quotient; // From test of Test.v - wire [WL-1:0] Remainder; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [WL-1:0] Quotient; // From test of Test.v + wire [WL-1:0] Remainder; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .Quotient (Quotient[WL-1:0]), - .Remainder (Remainder[WL-1:0]), - // Inputs - .Operand1 (Operand1[WL*2-1:0]), - .Operand2 (Operand2[WL-1:0]), - .clk (clk), - .rst (rst), - .Unsigned (Unsigned)); + Test test ( /*AUTOINST*/ + // Outputs + .Quotient(Quotient[WL-1:0]), + .Remainder(Remainder[WL-1:0]), + // Inputs + .Operand1(Operand1[WL*2-1:0]), + .Operand2(Operand2[WL-1:0]), + .clk(clk), + .rst(rst), + .Unsigned(Unsigned) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, Quotient, Remainder}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, Quotient, Remainder}; - // What checksum will we end up with -`define EXPECTED_SUM 64'h98d41f89a8be5693 + // What checksum will we end up with + `define EXPECTED_SUM 64'h98d41f89a8be5693 - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n", $time, cyc, crc, result, test.Iteration); + $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n", $time, cyc, crc, result, test.Iteration); `endif - cyc <= cyc + 1; - if (cyc < 20 || test.Iteration==4'd15) begin - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - end - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - rst <= 1'b1; - end - else if (cyc<20) begin - sum <= 64'h0; - rst <= 1'b0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'h8dd70a44972ad809) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc < 20 || test.Iteration == 4'd15) begin + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + end + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + rst <= 1'b1; + end + else if (cyc < 20) begin + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'h8dd70a44972ad809) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); +module Test ( + clk, + rst, + Operand1, + Operand2, + Unsigned, + Quotient, + Remainder +); - parameter WL = 16; + parameter WL = 16; - input [WL*2-1:0] Operand1; - input [WL-1:0] Operand2; - input clk, rst, Unsigned; - output [WL-1:0] Quotient, Remainder; + input [WL*2-1:0] Operand1; + input [WL-1:0] Operand2; + input clk, rst, Unsigned; + output [WL-1:0] Quotient, Remainder; - reg Cy, Overflow, Sign1, Sign2, Zero, Negative; - reg [WL-1:0] ah,al,Quotient, Remainder; - reg [3:0] Iteration; - reg [WL-1:0] sub_quot,op; - reg ah_ext; + reg Cy, Overflow, Sign1, Sign2, Zero, Negative; + reg [WL-1:0] ah, al, Quotient, Remainder; + reg [3:0] Iteration; + reg [WL-1:0] sub_quot, op; + reg ah_ext; - reg [1:0] a,b,c,d,e; + reg [1:0] a, b, c, d, e; - always @(posedge clk) begin - if (!rst) begin - {a,b,c,d,e} = Operand1[9:0]; - {a,b,c,d,e} = {e,d,c,b,a}; - if (a != Operand1[1:0]) $stop; - if (b != Operand1[3:2]) $stop; - if (c != Operand1[5:4]) $stop; - if (d != Operand1[7:6]) $stop; - if (e != Operand1[9:8]) $stop; + always @(posedge clk) begin + if (!rst) begin + {a, b, c, d, e} = Operand1[9:0]; + {a, b, c, d, e} = {e, d, c, b, a}; + if (a != Operand1[1:0]) $stop; + if (b != Operand1[3:2]) $stop; + if (c != Operand1[5:4]) $stop; + if (d != Operand1[7:6]) $stop; + if (e != Operand1[9:8]) $stop; + end + end + + always @(posedge clk) begin + if (rst) begin + Iteration <= 0; + Quotient <= 0; + Remainder <= 0; + end + else begin + if (Iteration == 0) begin + {ah, al} = Operand1; + op = Operand2; + Cy = 0; + Overflow = 0; + Sign1 = (~Unsigned) & ah[WL-1]; + Sign2 = (~Unsigned) & (ah[WL-1] ^ op[WL-1]); + if (Sign1) {ah, al} = -{ah, al}; end - end - - always @(posedge clk) begin - if (rst) begin - Iteration <= 0; - Quotient <= 0; - Remainder <= 0; + `define BUG1 +`ifdef BUG1 + {ah_ext, ah, al} = {ah, al, Cy}; +`else + ah_ext = ah[15]; + ah[15:1] = ah[14:0]; + ah[0] = al[15]; + al[15:1] = al[14:0]; + al[0] = Cy; +`endif +`ifdef TEST_VERBOSE + $display("%x %x %x %x %x %x %x %x %x", Iteration, ah, al, Quotient, Remainder, Overflow, + ah_ext, sub_quot, Cy); +`endif + {Cy, sub_quot} = (~Unsigned) & op[WL-1] ? {ah_ext, ah} + op : {ah_ext, ah} - {1'b1, op}; + if (Cy) begin + {ah_ext, ah} = {1'b0, sub_quot}; + end + if (Iteration != 15) begin + if (ah_ext) Overflow = 1; end else begin - if (Iteration == 0) begin - {ah,al} = Operand1; - op = Operand2; - Cy = 0; - Overflow = 0; - Sign1 = (~Unsigned)&ah[WL-1]; - Sign2 = (~Unsigned)&(ah[WL-1]^op[WL-1]); - if (Sign1) {ah,al} = -{ah,al}; - end -`define BUG1 -`ifdef BUG1 - {ah_ext,ah,al} = {ah,al,Cy}; -`else - ah_ext = ah[15]; - ah[15:1] = ah[14:0]; - ah[0] = al[15]; - al[15:1] = al[14:0]; - al[0] = Cy; -`endif -`ifdef TEST_VERBOSE - $display("%x %x %x %x %x %x %x %x %x", - Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); -`endif - {Cy,sub_quot} = (~Unsigned)&op[WL-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; - if (Cy) - begin - {ah_ext,ah} = {1'b0,sub_quot}; - end - if (Iteration != 15 ) - begin - if (ah_ext) Overflow = 1; - end - else - begin - if (al[14] && ~Unsigned) Overflow = 1; - Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; - Remainder <= Sign1 ? -ah : ah; - if (Overflow) - begin - Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; - Remainder <= Unsigned ? 16'hffff : 16'h8000; - Zero = 1; - Negative = 1; - end - end - Iteration <= Iteration + 1; // Count number of times this instruction is repeated + if (al[14] && ~Unsigned) Overflow = 1; + Quotient <= Sign2 ? -{al[14:0], Cy} : {al[14:0], Cy}; + Remainder <= Sign1 ? -ah : ah; + if (Overflow) begin + Quotient <= Sign2 ? 16'h8001 : {Unsigned, {15{1'b1}}}; + Remainder <= Unsigned ? 16'hffff : 16'h8000; + Zero = 1; + Negative = 1; + end end - end + Iteration <= Iteration + 1; // Count number of times this instruction is repeated + end + end endmodule diff --git a/test_regress/t/t_math_synmul.v b/test_regress/t/t_math_synmul.v index f8d2098a2..494d71c65 100644 --- a/test_regress/t/t_math_synmul.v +++ b/test_regress/t/t_math_synmul.v @@ -4,11 +4,9 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); integer cyc = 0; reg [63:0] crc; @@ -38,18 +36,19 @@ module t ( /*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [64:0] product_d4; // From test of t_math_synmul_mul.v + wire [64:0] product_d4; // From test of t_math_synmul_mul.v // End of automatics t_math_synmul_mul test ( /*AUTOINST*/ - // Outputs - .product_d4 (product_d4[64:0]), - // Inputs - .clk (clk), - .enable (enable), - .negate (negate), - .datA (datA[31:0]), - .datB (datB[31:0])); + // Outputs + .product_d4(product_d4[64:0]), + // Inputs + .clk(clk), + .enable(enable), + .negate(negate), + .datA(datA[31:0]), + .datB(datB[31:0]) + ); integer cycs_enabled; initial cycs_enabled = 0; diff --git a/test_regress/t/t_math_tri.v b/test_regress/t/t_math_tri.v index 38d20e5fb..523c5b92f 100644 --- a/test_regress/t/t_math_tri.v +++ b/test_regress/t/t_math_tri.v @@ -6,17 +6,17 @@ module t; - reg [3:0] a; - reg [99:0] x; + reg [3:0] a; + reg [99:0] x; - initial begin - a = 4'b010x; - if (a[3:2] !== 2'b01) $stop; - if (|a !== 1'b1) $stop; - if (&a !== 1'b0) $stop; - x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + a = 4'b010x; + if (a[3:2] !== 2'b01) $stop; + if (|a !== 1'b1) $stop; + if (&a !== 1'b0) $stop; + x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_math_trig.v b/test_regress/t/t_math_trig.v index b94ab5a98..e6bf534c0 100644 --- a/test_regress/t/t_math_trig.v +++ b/test_regress/t/t_math_trig.v @@ -6,148 +6,146 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - real r, r2; - integer cyc = 0; + real r, r2; + integer cyc = 0; - task check(integer line, real got, real ex); - if (got != ex) begin - if ((got > ex ? got - ex : ex - got) > 0.000001) begin - $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); - $stop; - end + task check(integer line, real got, real ex); + if (got != ex) begin + if ((got > ex ? got - ex : ex - got) > 0.000001) begin + $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g", line, got, ex); + $stop; end - endtask + end + endtask - initial begin - // Check constant propagation - // Note $abs is not defined in SystemVerilog (as of 2012) - check(`__LINE__, $ceil(-1.2), -1); - check(`__LINE__, $ceil(1.2), 2); - check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); - check(`__LINE__, $exp(0.0), 1); - check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); - check(`__LINE__, $floor(-1.2), -2); - check(`__LINE__, $floor(1.2), 1); - check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); - //check(`__LINE__, $ln(0), 0); // Bad value - //check(`__LINE__, $ln(-1.2), 0); // Bad value - check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); - //check(`__LINE__, $log10(0), 0); // Bad value - //check(`__LINE__, $log10(-1.2), 0); - check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); - check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); - //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value - check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); - //check(`__LINE__, $sqrt(-1.2), 0); // Bad value - check(`__LINE__, ((1.5)**(1.25)), 1.660023); - check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 - check(`__LINE__, $acosh(1.2), 0.622362503); - check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 - check(`__LINE__, $asinh(1.2), 1.015973134); - check(`__LINE__, $atan (0.2), 0.197395559); - check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 - check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 - check(`__LINE__, $cos (1.2), 0.362357754); - check(`__LINE__, $cosh (1.2), 1.810655567); - check(`__LINE__, $hypot(1.2,2.3), 2.594224354); - check(`__LINE__, $sin (1.2), 0.932039085); - check(`__LINE__, $sinh (1.2), 1.509461355); - check(`__LINE__, $tan (1.2), 2.572151622); - check(`__LINE__, $tanh (1.2), 0.833654607); - end + initial begin + // Check constant propagation + // Note $abs is not defined in SystemVerilog (as of 2012) + check(`__LINE__, $ceil(-1.2), -1); + check(`__LINE__, $ceil(1.2), 2); + check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); + check(`__LINE__, $exp(0.0), 1); + check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); + check(`__LINE__, $floor(-1.2), -2); + check(`__LINE__, $floor(1.2), 1); + check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); + //check(`__LINE__, $ln(0), 0); // Bad value + //check(`__LINE__, $ln(-1.2), 0); // Bad value + check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); + //check(`__LINE__, $log10(0), 0); // Bad value + //check(`__LINE__, $log10(-1.2), 0); + check(`__LINE__, $pow(2.3, 1.2), 2.71689843249914897427288451581262052059173583984375); + check(`__LINE__, $pow(2.3, -1.2), 0.368066758785732861536388327294844202697277069091796875); + //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value + check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); + //check(`__LINE__, $sqrt(-1.2), 0); // Bad value + check(`__LINE__, ((1.5) ** (1.25)), 1.660023); + check(`__LINE__, $acos(0.2), 1.369438406); // Arg1 is -1..1 + check(`__LINE__, $acosh(1.2), 0.622362503); + check(`__LINE__, $asin(0.2), 0.201357920); // Arg1 is -1..1 + check(`__LINE__, $asinh(1.2), 1.015973134); + check(`__LINE__, $atan(0.2), 0.197395559); + check(`__LINE__, $atan2(0.2, 2.3), 0.086738338); // Arg1 is -1..1 + check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 + check(`__LINE__, $cos(1.2), 0.362357754); + check(`__LINE__, $cosh(1.2), 1.810655567); + check(`__LINE__, $hypot(1.2, 2.3), 2.594224354); + check(`__LINE__, $sin(1.2), 0.932039085); + check(`__LINE__, $sinh(1.2), 1.509461355); + check(`__LINE__, $tan(1.2), 2.572151622); + check(`__LINE__, $tanh(1.2), 0.833654607); + end - real sum_ceil; - real sum_exp; - real sum_floor; - real sum_ln; - real sum_log10; - real sum_pow1; - real sum_pow2; - real sum_sqrt; + real sum_ceil; + real sum_exp; + real sum_floor; + real sum_ln; + real sum_log10; + real sum_pow1; + real sum_pow2; + real sum_sqrt; - real sum_acos; - real sum_acosh; - real sum_asin; - real sum_asinh; - real sum_atan; - real sum_atan2; - real sum_atanh; - real sum_cos ; - real sum_cosh; - real sum_hypot; - real sum_sin; - real sum_sinh; - real sum_tan; - real sum_tanh; + real sum_acos; + real sum_acosh; + real sum_asin; + real sum_asinh; + real sum_atan; + real sum_atan2; + real sum_atanh; + real sum_cos; + real sum_cosh; + real sum_hypot; + real sum_sin; + real sum_sinh; + real sum_tan; + real sum_tanh; - // Test loop - always @ (posedge clk) begin - r = $itor(cyc)/10.0 - 5.0; // Crosses 0 + // Test loop + always @(posedge clk) begin + r = $itor(cyc) / 10.0 - 5.0; // Crosses 0 `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n", $time, cyc, r, sum_ln); + $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n", $time, cyc, r, sum_ln); `endif - cyc <= cyc + 1; - if (cyc==0) begin - end - else if (cyc<90) begin - // Setup - sum_ceil += 1.0+$ceil(r); - sum_exp += 1.0+$exp(r); - sum_floor += 1.0+$floor(r); - if (r > 0.0) sum_ln += 1.0+$ln(r); - if (r > 0.0) sum_log10 += 1.0+$log10(r); - // Pow requires if arg1<0 then arg1 integral - sum_pow1 += 1.0+$pow(2.3,r); - if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); - if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); + cyc <= cyc + 1; + if (cyc == 0) begin + end + else if (cyc < 90) begin + // Setup + sum_ceil += 1.0 + $ceil(r); + sum_exp += 1.0 + $exp(r); + sum_floor += 1.0 + $floor(r); + if (r > 0.0) sum_ln += 1.0 + $ln(r); + if (r > 0.0) sum_log10 += 1.0 + $log10(r); + // Pow requires if arg1<0 then arg1 integral + sum_pow1 += 1.0 + $pow(2.3, r); + if (r >= 0.0) sum_pow2 += 1.0 + $pow(r, 2.3); + if (r >= 0.0) sum_sqrt += 1.0 + $sqrt(r); - if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); - if (r>=1.0) sum_acosh += 1.0+$acosh(r); - if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); - sum_asinh += 1.0+$asinh(r); - sum_atan += 1.0+$atan (r); - if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); - if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); - sum_cos += 1.0+$cos (r); - sum_cosh += 1.0+$cosh (r); - sum_hypot += 1.0+$hypot(r,2.3); - sum_sin += 1.0+$sin (r); - sum_sinh += 1.0+$sinh (r); - sum_tan += 1.0+$tan (r); - sum_tanh += 1.0+$tanh (r); - end - else if (cyc==99) begin - check (`__LINE__, sum_ceil, 85); - check (`__LINE__, sum_exp, 608.06652950); - check (`__LINE__, sum_floor, 4); - check (`__LINE__, sum_ln, 55.830941633); - check (`__LINE__, sum_log10, 46.309585076); - check (`__LINE__, sum_pow1, 410.98798177); - check (`__LINE__, sum_pow2, 321.94765689); - check (`__LINE__, sum_sqrt, 92.269677253); - check (`__LINE__, sum_acos, 53.986722862); - check (`__LINE__, sum_acosh, 72.685208498); - check (`__LINE__, sum_asin, 21); - check (`__LINE__, sum_asinh, 67.034973416); - check (`__LINE__, sum_atan, 75.511045389); - check (`__LINE__, sum_atan2, 21); - check (`__LINE__, sum_atanh, 0); - check (`__LINE__, sum_cos, 72.042023124); - check (`__LINE__, sum_cosh, 1054.0178222); - check (`__LINE__, sum_hypot, 388.92858406); - check (`__LINE__, sum_sin, 98.264184989); - check (`__LINE__, sum_sinh, -356.9512927); - check (`__LINE__, sum_tan, 1.7007946043); - check (`__LINE__, sum_tanh, 79.003199681); + if (r >= -1.0 && r <= 1.0) sum_acos += 1.0 + $acos(r); + if (r >= 1.0) sum_acosh += 1.0 + $acosh(r); + if (r >= -1.0 && r <= 1.0) sum_asin += 1.0 + $asin(r); + sum_asinh += 1.0 + $asinh(r); + sum_atan += 1.0 + $atan(r); + if (r >= -1.0 && r <= 1.0) sum_atan2 += 1.0 + $atan2(r, 2.3); + if (r >= -1.0 && r <= 1.0) sum_atanh += 1.0 + $atanh(r); + sum_cos += 1.0 + $cos(r); + sum_cosh += 1.0 + $cosh(r); + sum_hypot += 1.0 + $hypot(r, 2.3); + sum_sin += 1.0 + $sin(r); + sum_sinh += 1.0 + $sinh(r); + sum_tan += 1.0 + $tan(r); + sum_tanh += 1.0 + $tanh(r); + end + else if (cyc == 99) begin + check(`__LINE__, sum_ceil, 85); + check(`__LINE__, sum_exp, 608.06652950); + check(`__LINE__, sum_floor, 4); + check(`__LINE__, sum_ln, 55.830941633); + check(`__LINE__, sum_log10, 46.309585076); + check(`__LINE__, sum_pow1, 410.98798177); + check(`__LINE__, sum_pow2, 321.94765689); + check(`__LINE__, sum_sqrt, 92.269677253); + check(`__LINE__, sum_acos, 53.986722862); + check(`__LINE__, sum_acosh, 72.685208498); + check(`__LINE__, sum_asin, 21); + check(`__LINE__, sum_asinh, 67.034973416); + check(`__LINE__, sum_atan, 75.511045389); + check(`__LINE__, sum_atan2, 21); + check(`__LINE__, sum_atanh, 0); + check(`__LINE__, sum_cos, 72.042023124); + check(`__LINE__, sum_cosh, 1054.0178222); + check(`__LINE__, sum_hypot, 388.92858406); + check(`__LINE__, sum_sin, 98.264184989); + check(`__LINE__, sum_sinh, -356.9512927); + check(`__LINE__, sum_tan, 1.7007946043); + check(`__LINE__, sum_tanh, 79.003199681); - $write("*-* All Finished *-*\n"); - $finish; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v index 783ce5d2f..1a23a8ace 100644 --- a/test_regress/t/t_math_vgen.v +++ b/test_regress/t/t_math_vgen.v @@ -4,305 +4,306 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; - reg check; initial check = 1'b0; + integer cyc; + initial cyc = 1; + reg check; + initial check = 1'b0; - // verilator lint_off WIDTH + // verilator lint_off WIDTH + // verilog_format: off - //============================================================ + //============================================================ - reg [ 1:0] W0095; //=3 - reg [ 58:0] W0101; //=0000000FFFFFFFF - always @(posedge clk) begin - if (cyc==1) begin - W0095 = ((2'h3)); - W0101 = ({27'h0,({16{(W0095)}})}); + reg [ 1:0] W0095; //=3 + reg [ 58:0] W0101; //=0000000FFFFFFFF + always @(posedge clk) begin + if (cyc==1) begin + W0095 = ((2'h3)); + W0101 = ({27'h0,({16{(W0095)}})}); + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; + end + end + + //============================================================ + + reg [ 0:0] W1243; //=1 + always @(posedge clk) begin + if (cyc==1) begin + W1243 = ((1'h1)); + end + end + always @(posedge clk) begin + if (cyc==2) begin + // Width violation, but still... + if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; + if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; + end + end + + //============================================================ + + reg [ 0:0] W0344; //=0 + always @(posedge clk) begin + if (cyc==1) begin + W0344 = 1'b0; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0344) != (1'h0)) if (check) $stop; + if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; + end + end + + //============================================================ + + reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF + reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF + reg [115:0] W0421; //=00000000000000000000000000000 + always @(posedge clk) begin + if (cyc==1) begin + W0372 = ({64{((1'h1))}}); + W0421 = 116'h0; + W0420 = ({119{((W0372) <= (W0372))}}); + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; + end + end + + //============================================================ + + // gcc_2_96_bug + reg [ 31:0] W0161; //=FFFFFFFF + reg [ 62:0] W0217; //=0000000000000000 + reg [ 53:0] W0219; //=00000000000000 + always @(posedge clk) begin + if (cyc==1) begin + W0161 = 32'hFFFFFFFF; + W0217 = 63'h0; + W0219 = 54'h0; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; + if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; + end + end + + //============================================================ + + reg [119:0] W0592; //=000000000000000000000000000000 + reg [ 7:0] W0593; //=70 + always @(posedge clk) begin + if (cyc==1) begin + W0593 = (((8'h90)) * ((8'hFF))); + W0592 = 120'h000000000000000000000000000000; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; + end + end + + //============================================================ + + reg [127:0] WA1063 ; //=00000000000000000000000000000001 + reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WA1065 ; //=0000000000000000 + reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WA1067 ; //=7FFFFFFFF + reg [111:0] WA1068; + + always @(check) begin + WA1067 = (~ (35'h0)); + WA1066 = (90'h00000000000000000000001); + WA1065 = (WA1066[89:27]); + WA1064 = (WA1067); + WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); + end + always @(posedge clk) begin + if (cyc==2) begin + if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + end + end + + //============================================================ + + reg [127:0] WB1063 ; //=00000000000000000000000000000001 + reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WB1065 ; //=0000000000000000 + reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WB1067 ; //=7FFFFFFFF + reg [111:0] WB1068; + + always @(posedge clk) begin + if (cyc==1) begin + WB1067 = (~ (35'h0)); + WB1066 = (90'h00000000000000000000001); + end + if (cyc==2) WB1065 <= (WB1066[89:27]); + if (cyc==3) WB1064 <= (WB1067); + if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); + if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]); + end + always @(posedge clk) begin + if (cyc==9) begin + if (WB1068 != 112'h0) if (check) $stop; + if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + end + end + + //============================================================ + + reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF + reg signed [ 6:0] WC0065 ; //=00 + reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF + + always @(check) begin + WC0064 = 61'sh1FFFFFFFFFFFFFFF; + WC0065 = 7'sh0; + if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop; + end + + //============================================================ + + reg signed [ 76:0] W0234 ; //=00000000000000000000 + reg signed [ 7:0] W0235 /*verilator public*/; //=B6 + always @(check) begin + W0235 = 8'shb6; + W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235)); + if ((W0234) != 77'sh0) if (check) $stop; + end + + //============================================================ + + reg signed [ 30:0] W0146 ; //=00000001 + always @(check) begin : Block71 + W0146 = (31'sh00000001); + if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop; + end + + //============================================================ + + reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF + + always @(check) begin : Block405 + W0857 = 55'sh7fffffffffffff; + if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop; + end + + //============================================================ + + always @(posedge clk) begin + if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop; + if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop; + end + + //============================================================ + + reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA + + always_comb begin : Block144 + W0226 = 83'sh47A4301EE3FB4133EE3DA; + if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop; + end + + //============================================================ + + reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C + reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A + + always @(posedge clk) begin + W0793 <= 69'sh1f_ffffffff_4eb1a91a; + W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E); + if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop; + end + + //============================================================ + + reg signed [ 2:0] DW0515 /*verilator public*/; //=7 + + always @(posedge clk) begin + DW0515 <= 3'sh7; + if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop; + end + + //============================================================ + + reg signed [ 62:0] W0753 ; //=004E20004ED93E26 + reg [ 2:0] W0772 /*verilator public*/; //=7 + + always @(posedge clk) begin + W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff))); + W0772 <= 3'h7; + if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; + if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; + end + + //============================================================ + + reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF + always @(posedge clk) begin + W1027 <= ~99'h0; + // verilator lint_off CMPCONST + if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop; + // verilator lint_on CMPCONST + end + + //============================================================ + + reg signed [ 5:0] W123_is_3f ; //=3F + + always @(posedge clk) begin + W123_is_3f <= 6'sh3f; + end + always @(posedge clk) begin + if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop; + end + + //============================================================ + + reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1 + always @(check) begin : Block237 + W0032 = 106'sh3ff0000000100000000bd597bb1; + if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; + if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; + end + + //============================================================ + + reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094 + reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c + always @(posedge clk) begin + W0024 <= 84'h0000000000000e1fe9094; + W0025 <= 84'h0f66afffffffe308b3d7c; + if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop; + end + + //============================================================ + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==18) begin + check <= 1'b1; end - end - always @(posedge clk) begin - if (cyc==2) begin - if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; end - end - - //============================================================ - - reg [ 0:0] W1243; //=1 - always @(posedge clk) begin - if (cyc==1) begin - W1243 = ((1'h1)); - end - end - always @(posedge clk) begin - if (cyc==2) begin - // Width violation, but still... - if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; - if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; - end - end - - //============================================================ - - reg [ 0:0] W0344; //=0 - always @(posedge clk) begin - if (cyc==1) begin - W0344 = 1'b0; - end - end - always @(posedge clk) begin - if (cyc==2) begin - if ((W0344) != (1'h0)) if (check) $stop; - if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; - end - end - - //============================================================ - - reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF - reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF - reg [115:0] W0421; //=00000000000000000000000000000 - always @(posedge clk) begin - if (cyc==1) begin - W0372 = ({64{((1'h1))}}); - W0421 = 116'h0; - W0420 = ({119{((W0372) <= (W0372))}}); - end - end - always @(posedge clk) begin - if (cyc==2) begin - if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; - end - end - - //============================================================ - - // gcc_2_96_bug - reg [ 31:0] W0161; //=FFFFFFFF - reg [ 62:0] W0217; //=0000000000000000 - reg [ 53:0] W0219; //=00000000000000 - always @(posedge clk) begin - if (cyc==1) begin - W0161 = 32'hFFFFFFFF; - W0217 = 63'h0; - W0219 = 54'h0; - end - end - always @(posedge clk) begin - if (cyc==2) begin - if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; - if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; - end - end - - //============================================================ - - reg [119:0] W0592; //=000000000000000000000000000000 - reg [ 7:0] W0593; //=70 - always @(posedge clk) begin - if (cyc==1) begin - W0593 = (((8'h90)) * ((8'hFF))); - W0592 = 120'h000000000000000000000000000000; - end - end - always @(posedge clk) begin - if (cyc==2) begin - if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; - end - end - - //============================================================ - - reg [127:0] WA1063 ; //=00000000000000000000000000000001 - reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF - reg [ 62:0] WA1065 ; //=0000000000000000 - reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 - reg [ 34:0] WA1067 ; //=7FFFFFFFF - reg [111:0] WA1068; - - always @(check) begin - WA1067 = (~ (35'h0)); - WA1066 = (90'h00000000000000000000001); - WA1065 = (WA1066[89:27]); - WA1064 = (WA1067); - WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); - end - always @(posedge clk) begin - if (cyc==2) begin - if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; - end - end - - //============================================================ - - reg [127:0] WB1063 ; //=00000000000000000000000000000001 - reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF - reg [ 62:0] WB1065 ; //=0000000000000000 - reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 - reg [ 34:0] WB1067 ; //=7FFFFFFFF - reg [111:0] WB1068; - - always @(posedge clk) begin - if (cyc==1) begin - WB1067 = (~ (35'h0)); - WB1066 = (90'h00000000000000000000001); - end - if (cyc==2) WB1065 <= (WB1066[89:27]); - if (cyc==3) WB1064 <= (WB1067); - if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); - if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]); - end - always @(posedge clk) begin - if (cyc==9) begin - if (WB1068 != 112'h0) if (check) $stop; - if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; - end - end - - //============================================================ - - reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF - reg signed [ 6:0] WC0065 ; //=00 - reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF - - always @(check) begin - WC0064 = 61'sh1FFFFFFFFFFFFFFF; - WC0065 = 7'sh0; - if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop; - end - - //============================================================ - - reg signed [ 76:0] W0234 ; //=00000000000000000000 - reg signed [ 7:0] W0235 /*verilator public*/; //=B6 - always @(check) begin - W0235 = 8'shb6; - W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235)); - if ((W0234) != 77'sh0) if (check) $stop; - end - - //============================================================ - - reg signed [ 30:0] W0146 ; //=00000001 - always @(check) begin : Block71 - W0146 = (31'sh00000001); - if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop; - end - - //============================================================ - - reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF - - always @(check) begin : Block405 - W0857 = 55'sh7fffffffffffff; - if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop; - end - - //============================================================ - - always @(posedge clk) begin - if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop; - if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop; - end - - //============================================================ - - reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA - - always_comb begin : Block144 - W0226 = 83'sh47A4301EE3FB4133EE3DA; - if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop; - end - - //============================================================ - - reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C - reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A - - always @(posedge clk) begin - W0793 <= 69'sh1f_ffffffff_4eb1a91a; - W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E); - if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop; - end - - //============================================================ - - reg signed [ 2:0] DW0515 /*verilator public*/; //=7 - - always @(posedge clk) begin - DW0515 <= 3'sh7; - if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop; - end - - //============================================================ - - reg signed [ 62:0] W0753 ; //=004E20004ED93E26 - reg [ 2:0] W0772 /*verilator public*/; //=7 - - always @(posedge clk) begin - W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff))); - W0772 <= 3'h7; - if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; - if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; - end - - //============================================================ - - reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF - always @(posedge clk) begin - W1027 <= ~99'h0; - // verilator lint_off CMPCONST - if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop; - // verilator lint_on CMPCONST - end - - //============================================================ - - reg signed [ 5:0] W123_is_3f ; //=3F - - always @(posedge clk) begin - W123_is_3f <= 6'sh3f; - end - always @(posedge clk) begin - if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop; - end - - //============================================================ - - reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1 - always @(check) begin : Block237 - W0032 = 106'sh3ff0000000100000000bd597bb1; - if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; - if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; - end - - //============================================================ - - reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094 - reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c - always @(posedge clk) begin - W0024 <= 84'h0000000000000e1fe9094; - W0025 <= 84'h0f66afffffffe308b3d7c; - if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop; - end - - //============================================================ - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==18) begin - check <= 1'b1; - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end + end + end endmodule diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v index 316d697f1..b879422b3 100644 --- a/test_regress/t/t_math_vliw.v +++ b/test_regress/t/t_math_vliw.v @@ -4,101 +4,102 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc = 0; - reg [7:0] crc; - reg [223:0] sum; + integer cyc; + initial cyc = 0; + reg [7:0] crc; + reg [223:0] sum; - wire [255:0] mglehy = {32{~crc}}; - wire [215:0] drricx = {27{crc}}; - wire [15:0] apqrli = {2{~crc}}; - wire [2:0] szlfpf = crc[2:0]; - wire [15:0] dzosui = {2{crc}}; - wire [31:0] zndrba = {16{crc[1:0]}}; - wire [223:0] bxiouf; + wire [255:0] mglehy = {32{~crc}}; + wire [215:0] drricx = {27{crc}}; + wire [15:0] apqrli = {2{~crc}}; + wire [2:0] szlfpf = crc[2:0]; + wire [15:0] dzosui = {2{crc}}; + wire [31:0] zndrba = {16{crc[1:0]}}; + wire [223:0] bxiouf; - vliw vliw ( - // Outputs - .bxiouf (bxiouf), - // Inputs - .mglehy (mglehy[255:0]), - .drricx (drricx[215:0]), - .apqrli (apqrli[15:0]), - .szlfpf (szlfpf[2:0]), - .dzosui (dzosui[15:0]), - .zndrba (zndrba[31:0])); + vliw vliw ( + // Outputs + .bxiouf(bxiouf), + // Inputs + .mglehy(mglehy[255:0]), + .drricx(drricx[215:0]), + .apqrli(apqrli[15:0]), + .szlfpf(szlfpf[2:0]), + .dzosui(dzosui[15:0]), + .zndrba(zndrba[31:0]) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==0) begin - // Setup - crc <= 8'hed; - sum <= 224'h0; - end - else if (cyc<90) begin - //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf); - sum <= {sum[222:0],sum[223]} ^ bxiouf; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); - if (crc !== 8'b01110000) $stop; - if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + if (cyc == 0) begin + // Setup + crc <= 8'hed; + sum <= 224'h0; + end + else if (cyc < 90) begin + //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf); + sum <= {sum[222:0], sum[223]} ^ bxiouf; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); + if (crc !== 8'b01110000) $stop; + if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module vliw ( - input[255:0] mglehy, - input[215:0] drricx, - input[15:0] apqrli, - input[2:0] szlfpf, - input[15:0] dzosui, - input[31:0] zndrba, - output wire [223:0] bxiouf - ); + input [255:0] mglehy, + input [215:0] drricx, + input [15:0] apqrli, + input [2:0] szlfpf, + input [15:0] dzosui, + input [31:0] zndrba, + output wire [223:0] bxiouf +); - wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) + wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) | ({29{apqrli}} & {mglehy[247:0], drricx}); - wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) - | ({21{dzosui}} & zhknfc[335:0]); - wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; - wire [223:0] rzyeut = viuvoc[335:112]; - assign bxiouf = {rzyeut[7:0], - rzyeut[15:8], - rzyeut[23:16], - rzyeut[31:24], - rzyeut[39:32], - rzyeut[47:40], - rzyeut[55:48], - rzyeut[63:56], - rzyeut[71:64], - rzyeut[79:72], - rzyeut[87:80], - rzyeut[95:88], - rzyeut[103:96], - rzyeut[111:104], - rzyeut[119:112], - rzyeut[127:120], - rzyeut[135:128], - rzyeut[143:136], - rzyeut[151:144], - rzyeut[159:152], - rzyeut[167:160], - rzyeut[175:168], - rzyeut[183:176], - rzyeut[191:184], - rzyeut[199:192], - rzyeut[207:200], - rzyeut[215:208], - rzyeut[223:216]}; + wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) | ({21{dzosui}} & zhknfc[335:0]); + wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; + wire [223:0] rzyeut = viuvoc[335:112]; + assign bxiouf = { + rzyeut[7:0], + rzyeut[15:8], + rzyeut[23:16], + rzyeut[31:24], + rzyeut[39:32], + rzyeut[47:40], + rzyeut[55:48], + rzyeut[63:56], + rzyeut[71:64], + rzyeut[79:72], + rzyeut[87:80], + rzyeut[95:88], + rzyeut[103:96], + rzyeut[111:104], + rzyeut[119:112], + rzyeut[127:120], + rzyeut[135:128], + rzyeut[143:136], + rzyeut[151:144], + rzyeut[159:152], + rzyeut[167:160], + rzyeut[175:168], + rzyeut[183:176], + rzyeut[191:184], + rzyeut[199:192], + rzyeut[207:200], + rzyeut[215:208], + rzyeut[223:216] + }; endmodule diff --git a/test_regress/t/t_math_wallace.v b/test_regress/t/t_math_wallace.v index 5d809a2fc..c83c33952 100644 --- a/test_regress/t/t_math_wallace.v +++ b/test_regress/t/t_math_wallace.v @@ -5,11 +5,9 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); integer cyc = 0; reg [63:0] crc; @@ -35,18 +33,19 @@ module t ( /*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [64:0] product_d3; // From test of t_math_wallace_mul.v + wire [64:0] product_d3; // From test of t_math_wallace_mul.v // End of automatics t_math_wallace_mul test ( /*AUTOINST*/ - // Outputs - .product_d3 (product_d3[64:0]), - // Inputs - .clk (clk), - .enable (enable), - .negate (negate), - .datA (datA[31:0]), - .datB (datB[31:0])); + // Outputs + .product_d3(product_d3[64:0]), + // Inputs + .clk(clk), + .enable(enable), + .negate(negate), + .datA(datA[31:0]), + .datB(datB[31:0]) + ); integer cycs_enabled; initial cycs_enabled = 0; diff --git a/test_regress/t/t_math_wide_bad.out b/test_regress/t/t_math_wide_bad.out index 826015a72..c2e3c3c37 100644 --- a/test_regress/t/t_math_wide_bad.out +++ b/test_regress/t/t_math_wide_bad.out @@ -1,23 +1,23 @@ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:34:19: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 34 | assign r = real'(a); - | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:34:18: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 34 | assign r = real'(a); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_math_wide_bad.v:28:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 28 | assign z2 = a ** 3; - | ^~ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:27:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 27 | assign z = a * b; +%Error-UNSUPPORTED: t/t_math_wide_bad.v:28:17: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 28 | assign z2 = a ** 3; + | ^~ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:27:16: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 27 | assign z = a * b; + | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:29:17: Unsupported: operator DIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 29 | assign z3 = a / b; | ^ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:29:18: Unsupported: operator DIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 29 | assign z3 = a / b; +%Error-UNSUPPORTED: t/t_math_wide_bad.v:30:17: Unsupported: operator MODDIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 30 | assign z4 = a % b; + | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:31:18: Unsupported: operator DIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 31 | assign z5 = ua / ub; | ^ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:30:18: Unsupported: operator MODDIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 30 | assign z4 = a % b; +%Error-UNSUPPORTED: t/t_math_wide_bad.v:32:18: Unsupported: operator MODDIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 32 | assign z6 = ua % ub; | ^ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:31:19: Unsupported: operator DIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 31 | assign z5 = ua / ub; - | ^ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:32:19: Unsupported: operator MODDIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 32 | assign z6 = ua % ub; - | ^ %Error: Exiting due to diff --git a/test_regress/t/t_math_wide_bad.v b/test_regress/t/t_math_wide_bad.v index 75892c1a1..63e604f54 100644 --- a/test_regress/t/t_math_wide_bad.v +++ b/test_regress/t/t_math_wide_bad.v @@ -5,32 +5,32 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - z, z2, z3, z4, z5, z6, r, - // Inputs - a, b, ua, ub - ); + // Outputs + z, z2, z3, z4, z5, z6, r, + // Inputs + a, b, ua, ub + ); - input signed [170*32 : 0] a; - input signed [170*32 : 0] b; - input [170*32 : 0] ua; - input [170*32 : 0] ub; + input signed [170*32 : 0] a; + input signed [170*32 : 0] b; + input [170*32 : 0] ua; + input [170*32 : 0] ub; - output signed [170*32 : 0] z; - output signed [170*32 : 0] z2; - output signed [170*32 : 0] z3; - output signed [170*32 : 0] z4; - output [170*32 : 0] z5; - output [170*32 : 0] z6; - output real r; + output signed [170*32 : 0] z; + output signed [170*32 : 0] z2; + output signed [170*32 : 0] z3; + output signed [170*32 : 0] z4; + output [170*32 : 0] z5; + output [170*32 : 0] z6; + output real r; - assign z = a * b; - assign z2 = a ** 3; - assign z3 = a / b; - assign z4 = a % b; - assign z5 = ua / ub; - assign z6 = ua % ub; + assign z = a * b; + assign z2 = a ** 3; + assign z3 = a / b; + assign z4 = a % b; + assign z5 = ua / ub; + assign z6 = ua % ub; - assign r = real'(a); + assign r = real'(a); endmodule diff --git a/test_regress/t/t_math_wide_inc.v b/test_regress/t/t_math_wide_inc.v index c49ba93e5..88258c947 100644 --- a/test_regress/t/t_math_wide_inc.v +++ b/test_regress/t/t_math_wide_inc.v @@ -6,84 +6,82 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer i; - reg [6:0] w7; - reg [14:0] w15; - reg [30:0] w31; - reg [62:0] w63; - reg [94:0] w95; + integer i; + reg [6:0] w7; + reg [14:0] w15; + reg [30:0] w31; + reg [62:0] w63; + reg [94:0] w95; - integer cyc = 0; + integer cyc = 0; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - w7 = {7{1'b1}}; - w15 = {15{1'b1}}; - w31 = {31{1'b1}}; - w63 = {63{1'b1}}; - w95 = {95{1'b1}}; - end - else if (cyc == 1) begin - if (w7++ != {7{1'b1}}) $stop; - if (w7 != {7{1'b0}}) $stop; - if (w7-- != {7{1'b0}}) $stop; - if (w7 != {7{1'b1}}) $stop; - if (++w7 != {7{1'b0}}) $stop; - if (w7 != {7{1'b0}}) $stop; - if (--w7 != {7{1'b1}}) $stop; - if (w7 != {7{1'b1}}) $stop; + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + w7 = {7{1'b1}}; + w15 = {15{1'b1}}; + w31 = {31{1'b1}}; + w63 = {63{1'b1}}; + w95 = {95{1'b1}}; + end + else if (cyc == 1) begin + if (w7++ != {7{1'b1}}) $stop; + if (w7 != {7{1'b0}}) $stop; + if (w7-- != {7{1'b0}}) $stop; + if (w7 != {7{1'b1}}) $stop; + if (++w7 != {7{1'b0}}) $stop; + if (w7 != {7{1'b0}}) $stop; + if (--w7 != {7{1'b1}}) $stop; + if (w7 != {7{1'b1}}) $stop; - if (w15++ != {15{1'b1}}) $stop; - if (w15 != {15{1'b0}}) $stop; - if (w15-- != {15{1'b0}}) $stop; - if (w15 != {15{1'b1}}) $stop; - if (++w15 != {15{1'b0}}) $stop; - if (w15 != {15{1'b0}}) $stop; - if (--w15 != {15{1'b1}}) $stop; - if (w15 != {15{1'b1}}) $stop; + if (w15++ != {15{1'b1}}) $stop; + if (w15 != {15{1'b0}}) $stop; + if (w15-- != {15{1'b0}}) $stop; + if (w15 != {15{1'b1}}) $stop; + if (++w15 != {15{1'b0}}) $stop; + if (w15 != {15{1'b0}}) $stop; + if (--w15 != {15{1'b1}}) $stop; + if (w15 != {15{1'b1}}) $stop; - if (w31++ != {31{1'b1}}) $stop; - if (w31 != {31{1'b0}}) $stop; - if (w31-- != {31{1'b0}}) $stop; - if (w31 != {31{1'b1}}) $stop; - if (++w31 != {31{1'b0}}) $stop; - if (w31 != {31{1'b0}}) $stop; - if (--w31 != {31{1'b1}}) $stop; - if (w31 != {31{1'b1}}) $stop; + if (w31++ != {31{1'b1}}) $stop; + if (w31 != {31{1'b0}}) $stop; + if (w31-- != {31{1'b0}}) $stop; + if (w31 != {31{1'b1}}) $stop; + if (++w31 != {31{1'b0}}) $stop; + if (w31 != {31{1'b0}}) $stop; + if (--w31 != {31{1'b1}}) $stop; + if (w31 != {31{1'b1}}) $stop; - if (w63++ != {63{1'b1}}) $stop; - if (w63 != {63{1'b0}}) $stop; - if (w63-- != {63{1'b0}}) $stop; - if (w63 != {63{1'b1}}) $stop; - if (++w63 != {63{1'b0}}) $stop; - if (w63 != {63{1'b0}}) $stop; - if (--w63 != {63{1'b1}}) $stop; - if (w63 != {63{1'b1}}) $stop; + if (w63++ != {63{1'b1}}) $stop; + if (w63 != {63{1'b0}}) $stop; + if (w63-- != {63{1'b0}}) $stop; + if (w63 != {63{1'b1}}) $stop; + if (++w63 != {63{1'b0}}) $stop; + if (w63 != {63{1'b0}}) $stop; + if (--w63 != {63{1'b1}}) $stop; + if (w63 != {63{1'b1}}) $stop; - if (w95++ != {95{1'b1}}) $stop; - if (w95 != {95{1'b0}}) $stop; - if (w95-- != {95{1'b0}}) $stop; - if (w95 != {95{1'b1}}) $stop; - if (++w95 != {95{1'b0}}) $stop; - if (w95 != {95{1'b0}}) $stop; - if (--w95 != {95{1'b1}}) $stop; - if (w95 != {95{1'b1}}) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (w95++ != {95{1'b1}}) $stop; + if (w95 != {95{1'b0}}) $stop; + if (w95-- != {95{1'b0}}) $stop; + if (w95 != {95{1'b1}}) $stop; + if (++w95 != {95{1'b0}}) $stop; + if (w95 != {95{1'b0}}) $stop; + if (--w95 != {95{1'b1}}) $stop; + if (w95 != {95{1'b1}}) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v index 603cdc21a..8ceae6095 100644 --- a/test_regress/t/t_math_width.v +++ b/test_regress/t/t_math_width.v @@ -6,54 +6,54 @@ module t; - // See also t_lint_width + // See also t_lint_width - parameter A_ONE = '1; - // verilator lint_off WIDTH - parameter [3:0] A_W4 = A_ONE; - // verilator lint_on WIDTH - initial begin - if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; - if ($bits(A_W4) != 4) $stop; - if (A_W4 != 4'b0001) $stop; - end + parameter A_ONE = '1; + // verilator lint_off WIDTH + parameter [3:0] A_W4 = A_ONE; + // verilator lint_on WIDTH + initial begin + if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; + if ($bits(A_W4) != 4) $stop; + if (A_W4 != 4'b0001) $stop; + end - b #(.B_WIDTH(48)) b (); + b #(.B_WIDTH(48)) b (); - reg [4:0] c; - integer c_i; - initial begin - c_i = 3; - c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax - if (c != 5'b1000) $stop; - end + reg [4:0] c; + integer c_i; + initial begin + c_i = 3; + c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax + if (c != 5'b1000) $stop; + end - localparam D_TT = 32'd23; - localparam D_SIX = 6; - // verilator lint_off WIDTH - localparam [5:0] D_SUB = D_TT - D_SIX; - // verilator lint_on WIDTH - initial begin - if (D_SUB != 17) $stop; - end + localparam D_TT = 32'd23; + localparam D_SIX = 6; + // verilator lint_off WIDTH + localparam [5:0] D_SUB = D_TT - D_SIX; + // verilator lint_on WIDTH + initial begin + if (D_SUB != 17) $stop; + end - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module b; - parameter B_WIDTH = 1; - localparam B_VALUE0 = {B_WIDTH{1'b0}}; - localparam B_VALUE1 = {B_WIDTH{1'b1}}; - reg [47:0] b_val; - initial begin - b_val = B_VALUE0; - if (b_val != 48'b0) $stop; - b_val = B_VALUE1; - if (b_val != ~48'b0) $stop; - end + parameter B_WIDTH = 1; + localparam B_VALUE0 = {B_WIDTH{1'b0}}; + localparam B_VALUE1 = {B_WIDTH{1'b1}}; + reg [47:0] b_val; + initial begin + b_val = B_VALUE0; + if (b_val != 48'b0) $stop; + b_val = B_VALUE1; + if (b_val != ~48'b0) $stop; + end endmodule diff --git a/test_regress/t/t_math_yosys.v b/test_regress/t/t_math_yosys.v index fd7041417..dd7ec0fe0 100644 --- a/test_regress/t/t_math_yosys.v +++ b/test_regress/t/t_math_yosys.v @@ -4,81 +4,91 @@ // SPDX-FileCopyrightText: 2020 Claire Wolf // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] y1; // From d1 of demo_001.v - wire [7:0] y2; // From d1 of demo_001.v - wire [7:0] y3; // From d1 of demo_001.v - wire [7:0] y4; // From d1 of demo_001.v - wire [31:0] z0; // From d2 of demo_002.v - wire [31:0] z1; // From d2 of demo_002.v - wire [31:0] z2; // From d2 of demo_002.v - wire [31:0] z3; // From d2 of demo_002.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] y1; // From d1 of demo_001.v + wire [7:0] y2; // From d1 of demo_001.v + wire [7:0] y3; // From d1 of demo_001.v + wire [7:0] y4; // From d1 of demo_001.v + wire [31:0] z0; // From d2 of demo_002.v + wire [31:0] z1; // From d2 of demo_002.v + wire [31:0] z2; // From d2 of demo_002.v + wire [31:0] z3; // From d2 of demo_002.v + // End of automatics - demo_001 d1(/*AUTOINST*/ - // Outputs - .y1 (y1[7:0]), - .y2 (y2[7:0]), - .y3 (y3[7:0]), - .y4 (y4[7:0])); - demo_002 d2(/*AUTOINST*/ - // Outputs - .z0 (z0[31:0]), - .z1 (z1[31:0]), - .z2 (z2[31:0]), - .z3 (z3[31:0])); + demo_001 d1 ( /*AUTOINST*/ + // Outputs + .y1(y1[7:0]), + .y2(y2[7:0]), + .y3(y3[7:0]), + .y4(y4[7:0]) + ); + demo_002 d2 ( /*AUTOINST*/ + // Outputs + .z0(z0[31:0]), + .z1(z1[31:0]), + .z2(z2[31:0]), + .z3(z3[31:0]) + ); - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (y1 !== 8'h7b) $stop; - if (y2 !== 8'h7c) $stop; - if (y3 !== 8'h7b) $stop; - if (y4 !== 8'h7c) $stop; - if (z0 !== 32'h00000000) $stop; - if (z1 !== 32'hffffffff) $stop; - if (z2 !== 32'hffffffff) $stop; - if (z3 !== 32'hffffffff) $stop; - if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (y1 !== 8'h7b) $stop; + if (y2 !== 8'h7c) $stop; + if (y3 !== 8'h7b) $stop; + if (y4 !== 8'h7c) $stop; + if (z0 !== 32'h00000000) $stop; + if (z1 !== 32'hffffffff) $stop; + if (z2 !== 32'hffffffff) $stop; + if (z3 !== 32'hffffffff) $stop; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module demo_001(y1, y2, y3, y4); - output [7:0] y1, y2, y3, y4; +module demo_001 ( + y1, + y2, + y3, + y4 +); + output [7:0] y1, y2, y3, y4; - // verilator lint_off REALCVT - localparam [7:0] P1 = 123.45; - localparam real P2 = 123.45; - localparam real P3 = 123; - localparam P4 = 123.45; + // verilator lint_off REALCVT + localparam [7:0] P1 = 123.45; + localparam real P2 = 123.45; + localparam real P3 = 123; + localparam P4 = 123.45; - // verilator lint_off WIDTH - assign y1 = P1 + 0.2; - assign y2 = P2 + 0.2; - assign y3 = P3 + 0.2; - assign y4 = P4 + 0.2; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + assign y1 = P1 + 0.2; + assign y2 = P2 + 0.2; + assign y3 = P3 + 0.2; + assign y4 = P4 + 0.2; + // verilator lint_on WIDTH endmodule -module demo_002(z0, z1, z2, z3); - output [31:0] z0, z1, z2, z3; +module demo_002 ( + z0, + z1, + z2, + z3 +); + output [31:0] z0, z1, z2, z3; - // verilator lint_off WIDTH - assign z0 = 1'bx >= (-1 * -1.17); - // verilator lint_on WIDTH - assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0; - assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0; - assign z3 = 1 ? -1 : 'd0; + // verilator lint_off WIDTH + assign z0 = 1'bx >= (-1 * -1.17); + // verilator lint_on WIDTH + assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0; + assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0; + assign z3 = 1 ? -1 : 'd0; endmodule diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v index 4eb216ac2..c4bae59c5 100644 --- a/test_regress/t/t_mem.v +++ b/test_regress/t/t_mem.v @@ -4,70 +4,68 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - logic hugemem [257]; - initial hugemem = '{default:1'b0}; + logic hugemem[257]; + initial hugemem = '{default: 1'b0}; - // [16] is SV syntax for [0:15] - reg [7:0] memory8_16 [16]; + // [16] is SV syntax for [0:15] + reg [7:0] memory8_16[16]; - reg m_we; - reg [3:1] m_addr; - reg [15:0] m_data; + reg m_we; + reg [3:1] m_addr; + reg [15:0] m_data; - always @ (posedge clk) begin - // Load instructions from cache - memory8_16[{m_addr,1'd0}] <= 8'hfe; - if (m_we) begin - {memory8_16[{m_addr,1'd1}], - memory8_16[{m_addr,1'd0}]} <= m_data; + always @(posedge clk) begin + // Load instructions from cache + memory8_16[{m_addr, 1'd0}] <= 8'hfe; + if (m_we) begin + {memory8_16[{m_addr, 1'd1}], memory8_16[{m_addr, 1'd0}]} <= m_data; + end + end + + reg [7:0] memory8_16_4; + reg [7:0] memory8_16_5; + // Test complicated sensitivity lists + always @(memory8_16[4][7:1] or memory8_16[5]) begin + memory8_16_4 = memory8_16[4]; + memory8_16_5 = memory8_16[5]; + end + + always @(posedge clk) begin + m_we <= 0; + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $display(hugemem); + m_we <= 1'b1; + m_addr <= 3'd2; + m_data <= 16'h55_44; end - end - - reg [7:0] memory8_16_4; - reg [7:0] memory8_16_5; - // Test complicated sensitivity lists - always @ (memory8_16[4][7:1] or memory8_16[5]) begin - memory8_16_4 = memory8_16[4]; - memory8_16_5 = memory8_16[5]; - end - - always @ (posedge clk) begin - m_we <= 0; - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - $display(hugemem); - m_we <= 1'b1; - m_addr <= 3'd2; - m_data <= 16'h55_44; - end - if (cyc==2) begin - m_we <= 1'b1; - m_addr <= 3'd3; - m_data <= 16'h77_66; - end - if (cyc==3) begin - m_we <= 0; // Check we really don't write this - m_addr <= 3'd3; - m_data <= 16'h0bad; - end - if (cyc==5) begin - if (memory8_16_4 != 8'h44) $stop; - if (memory8_16_5 != 8'h55) $stop; - if (memory8_16[6] != 8'hfe) $stop; - if (memory8_16[7] != 8'h77) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 2) begin + m_we <= 1'b1; + m_addr <= 3'd3; + m_data <= 16'h77_66; end - end + if (cyc == 3) begin + m_we <= 0; // Check we really don't write this + m_addr <= 3'd3; + m_data <= 16'h0bad; + end + if (cyc == 5) begin + if (memory8_16_4 != 8'h44) $stop; + if (memory8_16_5 != 8'h55) $stop; + if (memory8_16[6] != 8'hfe) $stop; + if (memory8_16[7] != 8'h77) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_mem_banks.v b/test_regress/t/t_mem_banks.v index dafe0c590..b7b78b58d 100644 --- a/test_regress/t/t_mem_banks.v +++ b/test_regress/t/t_mem_banks.v @@ -6,68 +6,67 @@ module t; - reg [5:0] addr; + reg [5:0] addr; - parameter BANKS = 6; - parameter ROWS = 8; + parameter BANKS = 6; + parameter ROWS = 8; - reg [2:0] bank; - reg [2:0] row; + reg [2:0] bank; + reg [2:0] row; - integer a; - integer used[BANKS][ROWS]; + integer a; + integer used[BANKS][ROWS]; - // Test loop - initial begin - for (a = 0; a < BANKS*ROWS; ++a) begin - addr[5:0] = a[5:0]; - hash (addr, bank, row); - used [bank][row] ++; - if (used [bank][row] > 1) begin - $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); - end + // Test loop + initial begin + for (a = 0; a < BANKS * ROWS; ++a) begin + addr[5:0] = a[5:0]; + hash(addr, bank, row); + used[bank][row]++; + if (used[bank][row] > 1) begin + $write("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); end - $write("*-* All Finished *-*\n"); - $finish; - end + end + $write("*-* All Finished *-*\n"); + $finish; + end - task hash (input [5:0] addr, - output [2:0] bank, - output [2:0] row); + task hash(input [5:0] addr, output [2:0] bank, output [2:0] row); - reg [1:0] third; - reg [1:0] fourth; + reg [1:0] third; + reg [1:0] fourth; - third = {addr[5], addr[4]}; - fourth = {addr[3] ^ addr[1], - addr[2] ^ addr[0]}; + third = {addr[5], addr[4]}; + fourth = {addr[3] ^ addr[1], addr[2] ^ addr[0]}; - case (third) - 2'h0: - case (fourth) - 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end - 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end - 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end - 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end - endcase + // verilog_format: off + case (third) + 2'h0: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end + 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end + endcase - 2'h1: - case (fourth) - 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end - 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end - 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end - 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end - endcase + 2'h1: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end + endcase - 2'h2: - case (fourth) - 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end - 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end - 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end - 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end - endcase + 2'h2: + case (fourth) + 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end + endcase - 2'h3: $stop; - endcase - endtask + 2'h3: $stop; + endcase + // verilog_format: on + endtask endmodule diff --git a/test_regress/t/t_mem_big_bad.out b/test_regress/t/t_mem_big_bad.out index c0dc80b82..a0d5db28c 100644 --- a/test_regress/t/t_mem_big_bad.out +++ b/test_regress/t/t_mem_big_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_mem_big_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) +%Error: t/t_mem_big_bad.v:14:17: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't_bigmem' - 14 | if (wen) mem[addr] <= data; - | ^ + 14 | if (wen) mem[addr] <= data; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHTRUNC: t/t_mem_big_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits. +%Warning-WIDTHTRUNC: t/t_mem_big_bad.v:14:24: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits. : ... note: In instance 't_bigmem' - 14 | if (wen) mem[addr] <= data; - | ^~ + 14 | if (wen) mem[addr] <= data; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_mem_big_bad.v b/test_regress/t/t_mem_big_bad.v index d17e085ab..a2150ceb4 100644 --- a/test_regress/t/t_mem_big_bad.v +++ b/test_regress/t/t_mem_big_bad.v @@ -3,14 +3,14 @@ // This file ONLY is placed under the Creative Commons Public Domain. // SPDX-FileCopyrightText: 2021 Zhanglei Wang // SPDX-License-Identifier: CC0-1.0 -module t_bigmem( - input wire clk, - input wire [27:0] addr, - input wire [255:0] data, - input wire wen +module t_bigmem ( + input wire clk, + input wire [27:0] addr, + input wire [255:0] data, + input wire wen ); - reg [(1<<28)-1:0][255:0] mem; - always @(posedge clk) begin - if (wen) mem[addr] <= data; - end + reg [(1<<28)-1:0][255:0] mem; + always @(posedge clk) begin + if (wen) mem[addr] <= data; + end endmodule diff --git a/test_regress/t/t_mem_bound_bad.v b/test_regress/t/t_mem_bound_bad.v index 06d708ead..87bb52aa6 100644 --- a/test_regress/t/t_mem_bound_bad.v +++ b/test_regress/t/t_mem_bound_bad.v @@ -5,21 +5,21 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic [1:0][31:0] tt; - logic [31:0] a; - logic [31:0] b; - logic [31:0] c; + logic [1:0][31:0] tt; + logic [31:0] a; + logic [31:0] b; + logic [31:0] c; - initial begin - a = 1; - b = 2; - c = 3; - tt[0] = a; - tt[1] = b; - tt[2] = c; // Out of bounds - if (tt[0]!=a) $stop; - if (tt[1]!=b) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + a = 1; + b = 2; + c = 3; + tt[0] = a; + tt[1] = b; + tt[2] = c; // Out of bounds + if (tt[0] != a) $stop; + if (tt[1] != b) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mem_cond.v b/test_regress/t/t_mem_cond.v index 0c467f030..22eeffa38 100644 --- a/test_regress/t/t_mem_cond.v +++ b/test_regress/t/t_mem_cond.v @@ -4,28 +4,30 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - b, - // Inputs - clk, en, a - ); +module t ( /*AUTOARG*/ + // Outputs + b, + // Inputs + clk, + en, + a +); - // bug1017 + // bug1017 - input clk; + input clk; - input en; - input a[1]; - output logic b[1]; + input en; + input a[1]; + output logic b[1]; - always_ff @ (posedge clk) begin - b <= en ? a : b; - end + always_ff @(posedge clk) begin + b <= en ? a : b; + end - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index 7e8817db1..c110d49e9 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -4,108 +4,112 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; - integer cyc; initial cyc = 0; - reg [63:0] crc; + wire [65:0] outData; // From fifo of fifo.v + wire [15:0] inData = crc[15:0]; + wire [1:0] inWordPtr = crc[17:16]; + wire wrEn = crc[20]; + wire [1:0] wrPtr = crc[33:32]; + wire [1:0] rdPtr = crc[34:33]; - wire [65:0] outData; // From fifo of fifo.v - wire [15:0] inData = crc[15:0]; - wire [1:0] inWordPtr = crc[17:16]; - wire wrEn = crc[20]; - wire [1:0] wrPtr = crc[33:32]; - wire [1:0] rdPtr = crc[34:33]; + fifo fifo ( + // Outputs + .outData(outData[65:0]), + // Inputs + .clk(clk), + .inWordPtr(inWordPtr[1:0]), + .inData(inData[15:0]), + .rdPtr(rdPtr), + .wrPtr(wrPtr), + .wrEn(wrEn) + ); - fifo fifo ( - // Outputs - .outData (outData[65:0]), - // Inputs - .clk (clk), - .inWordPtr (inWordPtr[1:0]), - .inData (inData[15:0]), - .rdPtr (rdPtr), - .wrPtr (wrPtr), - .wrEn (wrEn)); - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc==90) begin - if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; - end - else if (cyc==91) begin - if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; - end - else if (cyc==92) begin - if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; - end - else if (cyc==93) begin - if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; - end - else if (cyc==94) begin - if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc == 90) begin + if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; + end + else if (cyc == 91) begin + if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; + end + else if (cyc == 92) begin + if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; + end + else if (cyc == 93) begin + if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; + end + else if (cyc == 94) begin + if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module fifo (/*AUTOARG*/ - // Outputs - outData, - // Inputs - clk, inWordPtr, inData, wrPtr, rdPtr, wrEn - ); +module fifo ( /*AUTOARG*/ + // Outputs + outData, + // Inputs + clk, + inWordPtr, + inData, + wrPtr, + rdPtr, + wrEn +); - parameter fifoDepthLog2 = 1; - parameter fifoDepth = 1<10 && cyc<90) begin - sum <= {sum[30:0],sum[31]} ^ {out1, out0}; - end - else if (cyc==99) begin - if (sum !== 32'he8bbd130) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; + end + else if (cyc > 10 && cyc < 90) begin + sum <= {sum[30:0], sum[31]} ^ {out1, out0}; + end + else if (cyc == 99) begin + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module fifo (/*AUTOARG*/ - // Outputs - out0, out1, - // Inputs - clk, wr0a, wr0b, wr1a, wr1b, inData - ); +module fifo ( /*AUTOARG*/ + // Outputs + out0, + out1, + // Inputs + clk, + wr0a, + wr0b, + wr1a, + wr1b, + inData +); - input clk; - input wr0a; - input wr0b; - input wr1a; - input wr1b; - input [15:0] inData; + input clk; + input wr0a; + input wr0b; + input wr1a; + input wr1b; + input [15:0] inData; - output [15:0] out0; - output [15:0] out1; + output [15:0] out0; + output [15:0] out1; - reg [15:0] mem [1:0]; - reg [15:0] memtemp2 [1:0]; - reg [15:0] memtemp3 [1:0]; + reg [15:0] mem[1:0]; + reg [15:0] memtemp2[1:0]; + reg [15:0] memtemp3[1:0]; - assign out0 = {mem[0] ^ memtemp2[0]}; - assign out1 = {mem[1] ^ memtemp3[1]}; + assign out0 = {mem[0] ^ memtemp2[0]}; + assign out1 = {mem[1] ^ memtemp3[1]}; - always @(posedge clk) begin - // These mem assignments must be done in order after processing - if (wr0a) begin - memtemp2[0] <= inData; - mem[0] <= inData; - end - if (wr0b) begin - memtemp3[0] <= inData; - mem[0] <= ~inData; - end - if (wr1a) begin - memtemp3[1] <= inData; - mem[1] <= inData; - end - if (wr1b) begin - memtemp2[1] <= inData; - mem[1] <= ~inData; - end - end + always @(posedge clk) begin + // These mem assignments must be done in order after processing + if (wr0a) begin + memtemp2[0] <= inData; + mem[0] <= inData; + end + if (wr0b) begin + memtemp3[0] <= inData; + mem[0] <= ~inData; + end + if (wr1a) begin + memtemp3[1] <= inData; + mem[1] <= inData; + end + if (wr1b) begin + memtemp2[1] <= inData; + mem[1] <= ~inData; + end + end endmodule diff --git a/test_regress/t/t_mem_multi_io.v b/test_regress/t/t_mem_multi_io.v index b54ce06b6..2ff394023 100644 --- a/test_regress/t/t_mem_multi_io.v +++ b/test_regress/t/t_mem_multi_io.v @@ -4,64 +4,67 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic [7:0] arr[7:0]; + logic [7:0] arri[7:0]; - logic [7:0] arr [7:0]; - logic [7:0] arri [7:0]; + has_array am1 ( + .clk(clk), + .arri(arr), + .arro(arri) + ); - has_array am1 (.clk(clk), .arri(arr), .arro(arri)); + integer cyc; + initial cyc = 0; - integer cyc; initial cyc = 0; + initial begin + for (int i = 0; i < 8; i++) begin + arr[i] = 0; + arri[i] = 0; + end + end - initial begin - for (int i = 0; i < 8; i++) begin - arr[i] = 0; - arri[i] = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5 && arri[1] != 8) begin + $stop; + end + if (cyc >= 2) begin + for (int i = 0; i < 7; ++i) begin + arr[i+1] <= arr[i]; end - end - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5 && arri[1] != 8) begin - $stop; - end - if (cyc >= 2) begin - for (int i = 0; i < 7; ++i) begin - arr[i+1] <= arr[i]; - end - arr[0] <= arr[0] + 1; - end - end + arr[0] <= arr[0] + 1; + end + end endmodule : t module has_array ( - input clk, - input logic [7:0] arri [7:0], - output logic [7:0] arro [7:0] - ); + input clk, + input logic [7:0] arri[7:0], + output logic [7:0] arro[7:0] +); - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - if (arri[0] != 8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + if (arri[0] != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge clk) begin - for (integer i = 0; i < 7; ++i) begin - arro[i+1] <= arro[i]; - end - arro[0] = arro[0] + 2; - end + always @(posedge clk) begin + for (integer i = 0; i < 7; ++i) begin + arro[i+1] <= arro[i]; + end + arro[0] = arro[0] + 2; + end endmodule : has_array diff --git a/test_regress/t/t_mem_multi_io2.v b/test_regress/t/t_mem_multi_io2.v index 6075899c0..90a4096fc 100644 --- a/test_regress/t/t_mem_multi_io2.v +++ b/test_regress/t/t_mem_multi_io2.v @@ -5,36 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - o3, o34, o345, - // Inputs - i3, i34, i345 - ); - input [15:0] i3; - output wire [15:0] o3; - input [15:0] i34 [3:0]; - output wire [15:0] o34 [3:0]; - input [15:0] i345 [3:0][4:0]; - output wire [15:0] o345 [3:0][4:0]; + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; - sub sub (.*); + sub sub (.*); endmodule module sub (/*AUTOARG*/ - // Outputs - o3, o34, o345, - // Inputs - i3, i34, i345 - ); - input [15:0] i3; - output wire [15:0] o3; - input [15:0] i34 [3:0]; - output wire [15:0] o34 [3:0]; - input [15:0] i345 [3:0][4:0]; - output wire [15:0] o345 [3:0][4:0]; + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; - assign o3 = i3; - assign o34 = i34; - assign o345 = i345; + assign o3 = i3; + assign o34 = i34; + assign o345 = i345; endmodule diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v index ca37f3b13..9d751692e 100644 --- a/test_regress/t/t_mem_multi_io3.v +++ b/test_regress/t/t_mem_multi_io3.v @@ -4,54 +4,67 @@ // SPDX-FileCopyrightText: 2013 // SPDX-License-Identifier: CC0-1.0 -module t - ( - input logic clk, - input logic daten, - input logic [8:0] datval, - output logic signed [3:0][3:0][35:0] datao - ); +module t ( + input logic clk, + input logic daten, + input logic [8:0] datval, + output logic signed [3:0][3:0][35:0] datao +); - logic signed [3:0][3:0][3:0][8:0] datat; + logic signed [3:0][3:0][3:0][8:0] datat; - genvar i; - generate - for (i=0; i<4; i++)begin - testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); + genvar i; + generate + for (i = 0; i < 4; i++) begin + testio dut ( + .clk(clk), + .arr3d_in(datat[i]), + .arr2d_out(datao[i]) + ); + end + endgenerate + + genvar j; + generate + for (i = 0; i < 4; i++) begin + for (j = 0; j < 4; j++) begin + always_comb datat[i][j][0] = daten ? 9'h0 : datval; + always_comb datat[i][j][1] = daten ? 9'h1 : datval; + always_comb datat[i][j][2] = daten ? 9'h2 : datval; + always_comb datat[i][j][3] = daten ? 9'h3 : datval; end - endgenerate - - genvar j; - generate - for (i=0; i<4; i++) begin - for (j=0; j<4; j++) begin - always_comb datat[i][j][0] = daten ? 9'h0 : datval; - always_comb datat[i][j][1] = daten ? 9'h1 : datval; - always_comb datat[i][j][2] = daten ? 9'h2 : datval; - always_comb datat[i][j][3] = daten ? 9'h3 : datval; - end - end - endgenerate + end + endgenerate endmodule -module testio - ( - input clk, - input logic signed [3:0] [3:0] [8:0] arr3d_in, - output logic signed [3:0] [35:0] arr2d_out - ); - /* verilator lint_off MULTIDRIVEN */ - logic signed [3:0] [35:0] ar2d_out_pre; - /* verilator lint_on MULTIDRIVEN */ +module testio ( + input clk, + input logic signed [3:0][3:0][8:0] arr3d_in, + output logic signed [3:0][35:0] arr2d_out +); + /* verilator lint_off MULTIDRIVEN */ + logic signed [3:0][35:0] ar2d_out_pre; + /* verilator lint_on MULTIDRIVEN */ - always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; - always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; - always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; - always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb + ar2d_out_pre[0][35:0] = { + arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0] + }; + always_comb + ar2d_out_pre[0][35:0] = { + arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0] + }; + always_comb + ar2d_out_pre[0][35:0] = { + arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0] + }; + always_comb + ar2d_out_pre[0][35:0] = { + arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0] + }; - always_ff @(posedge clk) begin - if (clk) - arr2d_out <= ar2d_out_pre; - end + always_ff @(posedge clk) begin + if (clk) arr2d_out <= ar2d_out_pre; + end endmodule diff --git a/test_regress/t/t_mem_multi_ref_bad.out b/test_regress/t/t_mem_multi_ref_bad.out index 5726709dc..7991320bf 100644 --- a/test_regress/t/t_mem_multi_ref_bad.out +++ b/test_regress/t/t_mem_multi_ref_bad.out @@ -1,40 +1,40 @@ -%Error: t/t_mem_multi_ref_bad.v:15:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... note: In instance 't' - 15 | dimn[1:0] = 0; - | ^ +%Error: t/t_mem_multi_ref_bad.v:15:9: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... note: In instance 't' + 15 | dimn[1:0] = 0; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15:11: Extracting 2 bits from only 1 bit number - : ... note: In instance 't' - 15 | dimn[1:0] = 0; - | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15:9: Extracting 2 bits from only 1 bit number + : ... note: In instance 't' + 15 | dimn[1:0] = 0; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' +%Error: t/t_mem_multi_ref_bad.v:16:12: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 16 | dim0[1][1] = 0; + 16 | dim0[1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16:12: Selection index out of range: 1:1 outside 0:0 + : ... note: In instance 't' + 16 | dim0[1][1] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:17:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... note: In instance 't' + 17 | dim1[1][1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:17:15: Selection index out of range: 1:1 outside 0:0 + : ... note: In instance 't' + 17 | dim1[1][1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:19:15: Selection index out of range: 1 outside 0:0 + : ... note: In instance 't' + 19 | dim2[0+:1][1] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:23:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... note: In instance 't' + 23 | dim0nv[1][1] = 0; | ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16:14: Selection index out of range: 1:1 outside 0:0 +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:23:14: Selection index out of range: 1:1 outside 0:0 : ... note: In instance 't' - 16 | dim0[1][1] = 0; + 23 | dim0nv[1][1] = 0; | ^ -%Error: t/t_mem_multi_ref_bad.v:17:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... note: In instance 't' - 17 | dim1[1][1][1] = 0; - | ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:17:17: Selection index out of range: 1:1 outside 0:0 - : ... note: In instance 't' - 17 | dim1[1][1][1] = 0; - | ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:19:19: Selection index out of range: 1 outside 0:0 - : ... note: In instance 't' - 19 | dim2[0 +: 1][1] = 0; - | ^ -%Error: t/t_mem_multi_ref_bad.v:23:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... note: In instance 't' - 23 | dim0nv[1][1] = 0; - | ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:23:16: Selection index out of range: 1:1 outside 0:0 - : ... note: In instance 't' - 23 | dim0nv[1][1] = 0; - | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_multi_ref_bad.v b/test_regress/t/t_mem_multi_ref_bad.v index b66f7a9c0..2a0f7df2c 100644 --- a/test_regress/t/t_mem_multi_ref_bad.v +++ b/test_regress/t/t_mem_multi_ref_bad.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg dimn; - reg [1:0] dim0; - reg [1:0] dim1 [1:0]; - reg [1:0] dim2 [1:0][1:0]; - reg dim0nv[1:0]; + reg dimn; + reg [1:0] dim0; + reg [1:0] dim1[1:0]; + reg [1:0] dim2[1:0][1:0]; + reg dim0nv[1:0]; - initial begin - dimn[1:0] = 0; // Bad: Not ranged - dim0[1][1] = 0; // Bad: Not arrayed - dim1[1][1][1] = 0; // Bad: Not arrayed to right depth - dim2[1][1][1] = 0; // OK - dim2[0 +: 1][1] = 0; // Bad: Range on non-bits - dim2[1 : 0][1] = 0; // Bad: Range on non-bits - dim2[1][1:0] = 0; // Bad: Bitsel too soon - dim0nv[1:0] = 0; // Bad: Not vectored - dim0nv[1][1] = 0; // Bad: Not arrayed to right depth - end + initial begin + dimn[1:0] = 0; // Bad: Not ranged + dim0[1][1] = 0; // Bad: Not arrayed + dim1[1][1][1] = 0; // Bad: Not arrayed to right depth + dim2[1][1][1] = 0; // OK + dim2[0+:1][1] = 0; // Bad: Range on non-bits + dim2[1 : 0][1] = 0; // Bad: Range on non-bits + dim2[1][1:0] = 0; // Bad: Bitsel too soon + dim0nv[1:0] = 0; // Bad: Not vectored + dim0nv[1][1] = 0; // Bad: Not arrayed to right depth + end endmodule diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index 9ee30eba0..1fc2eb827 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -4,95 +4,94 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilator lint_off ASCRANGE + // 3 3 4 + reg [71:0] memw[2:0][1:3][5:2]; + reg [7:0] memn[2:0][1:3][5:2]; - // verilator lint_off ASCRANGE - // 3 3 4 - reg [71:0] memw [2:0][1:3][5:2]; - reg [7:0] memn [2:0][1:3][5:2]; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [71:0] wide; + reg [7:0] narrow; + reg [1:0] index0; + reg [1:0] index1; + reg [2:0] index2; + integer i0, i1, i2; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [71:0] wide; - reg [7:0] narrow; - reg [1:0] index0; - reg [1:0] index1; - reg [2:0] index2; - integer i0,i1,i2; + integer imem[2:0][1:3]; + reg [2:0] cstyle[2]; + // verilator lint_on ASCRANGE - integer imem[2:0][1:3]; - reg [2:0] cstyle[2]; - // verilator lint_on ASCRANGE - - initial begin - for (i0=0; i0<3; i0=i0+1) begin - for (i1=1; i1<4; i1=i1+1) begin - imem[i0[1:0]] [i1[1:0]] = i1; - for (i2=2; i2<6; i2=i2+1) begin - memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; - memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; - end - end + initial begin + for (i0 = 0; i0 < 3; i0 = i0 + 1) begin + for (i1 = 1; i1 < 4; i1 = i1 + 1) begin + imem[i0[1:0]][i1[1:0]] = i1; + for (i2 = 2; i2 < 6; i2 = i2 + 1) begin + memw[i0[1:0]][i1[1:0]][i2[2:0]] = { + 56'hfe_fee0_fee0_fee0_, 4'b0, i0[3:0], i1[3:0], i2[3:0] + }; + memn[i0[1:0]][i1[1:0]][i2[2:0]] = 8'b1000_0001; + end end - end + end + end - reg [71:0] wread; - reg wreadb; + reg [71:0] wread; + reg wreadb; - always @ (posedge clk) begin - //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - narrow <= 8'h0; - wide <= 72'h0; - index0 <= 2'b0; - index1 <= 2'b0; - index2 <= 3'b0; - end - else if (cyc<90) begin - index0 <= crc[1:0]; - index1 <= crc[3:2]; - index2 <= crc[6:4]; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + always @(posedge clk) begin + //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + narrow <= 8'h0; + wide <= 72'h0; + index0 <= 2'b0; + index1 <= 2'b0; + index2 <= 3'b0; + end + else if (cyc < 90) begin + index0 <= crc[1:0]; + index1 <= crc[3:2]; + index2 <= crc[6:4]; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - // We never read past bounds, or get unspecific results - // We also never read lowest indexes, as writing outside of range may corrupt them - if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin - narrow <= ({narrow[6:0], narrow[7]^narrow[0]} - ^ {memn[index0][index1][index2]}); - wread = memw[index0][index1][index2]; - wreadb = memw[index0][index1][index2][2]; - wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); - //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); - end - // We may write past bounds of memory - memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; - memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; - memw[index0][index1][index2] <= {~crc[7:0],crc}; - //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); - cstyle[cyc[0]] <= cyc[2:0]; - if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; + // We never read past bounds, or get unspecific results + // We also never read lowest indexes, as writing outside of range may corrupt them + if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin + narrow <= ({narrow[6:0], narrow[7] ^ narrow[0]} ^ {memn[index0][index1][index2]}); + wread = memw[index0][index1][index2]; + wreadb = memw[index0][index1][index2][2]; + wide <= ({wide[70:0], wide[71] ^ wide[2] ^ wide[0]} ^ wread); + //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); end - else if (cyc==90) begin - memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; - end - else if (cyc==91) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide); - if (crc != 64'h65e3bddcd9bc2750) $stop; - if (narrow != 8'hca) $stop; - if (wide != 72'h4edafed31ba6873f73) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + // We may write past bounds of memory + memn[index0][index1][index2][crc[10:8]+:3] <= crc[2:0]; + memn[index0][index1][index2] <= {~crc[6:0], crc[7]}; + memw[index0][index1][index2] <= {~crc[7:0], crc}; + //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); + cstyle[cyc[0]] <= cyc[2:0]; + if (cyc > 20) if (cstyle[~cyc[0]] != (cyc[2:0] - 3'b1)) $stop; + end + else if (cyc == 90) begin + memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; + end + else if (cyc == 91) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide); + if (crc != 64'h65e3bddcd9bc2750) $stop; + if (narrow != 8'hca) $stop; + if (wide != 72'h4edafed31ba6873f73) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index bb033afa8..bf4972a26 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -4,84 +4,89 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilator lint_off ASCRANGE + wire [7:0] array[2:0][1:3]; + wire [7:0] arrayNoColon[2][3]; + // verilator lint_on ASCRANGE - // verilator lint_off ASCRANGE - wire [7:0] array [2:0][1:3]; - wire [7:0] arrayNoColon [2][3]; - // verilator lint_on ASCRANGE + integer cyc; + initial cyc = 0; + integer i0, i1, i2; + genvar g0, g1, g2; - integer cyc; initial cyc = 0; - integer i0,i1,i2; - genvar g0,g1,g2; - - generate - for (g0=0; g0<3; g0=g0+1) begin - for (g1=1; g1<4; g1=g1+1) begin - inst inst (.q(array[g0[1:0]] [g1[1:0]]), - .cyc(cyc), - .i0(g0[1:0]), - .i1(g1[1:0])); - end + generate + for (g0 = 0; g0 < 3; g0 = g0 + 1) begin + for (g1 = 1; g1 < 4; g1 = g1 + 1) begin + inst inst ( + .q(array[g0[1:0]][g1[1:0]]), + .cyc(cyc), + .i0(g0[1:0]), + .i1(g1[1:0]) + ); end - endgenerate + end + endgenerate - always @ (posedge clk) begin - //$write("cyc==%0d\n",cyc); - cyc <= cyc + 1; - if (cyc==2) begin - if (array[2][1] !== 8'h92) $stop; - for (i0=0; i0<3; i0=i0+1) begin - for (i1=1; i1<4; i1=i1+1) begin - //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); - if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; - end - end + always @(posedge clk) begin + //$write("cyc==%0d\n",cyc); + cyc <= cyc + 1; + if (cyc == 2) begin + if (array[2][1] !== 8'h92) $stop; + for (i0 = 0; i0 < 3; i0 = i0 + 1) begin + for (i1 = 1; i1 < 4; i1 = i1 + 1) begin + //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); + if (array[i0[1:0]][i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; + end end - else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module inst (/*AUTOARG*/ - // Outputs - q, - // Inputs - cyc, i0, i1 - ); - output reg [7:0] q; - input [31:0] cyc; - input [1:0] i0; - input [1:0] i1; +module inst ( /*AUTOARG*/ + // Outputs + q, + // Inputs + cyc, + i0, + i1 +); + output reg [7:0] q; + input [31:0] cyc; + input [1:0] i0; + input [1:0] i1; - inst2 inst2 (/*AUTOINST*/ - // Inputs - .cyc (cyc[31:0]), - .i0 (i0[1:0]), - .i1 (i1[1:0])); + inst2 inst2 ( /*AUTOINST*/ + // Inputs + .cyc(cyc[31:0]), + .i0(i0[1:0]), + .i1(i1[1:0]) + ); - always @* begin - q = {i0, i1, cyc[3:0]}; - end + always @* begin + q = {i0, i1, cyc[3:0]}; + end endmodule -module inst2 (/*AUTOARG*/ - // Inputs - cyc, i0, i1 - ); - /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining - input [31:0] cyc; - input [1:0] i0; - input [1:0] i1; - initial begin - if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); - end +module inst2 ( /*AUTOARG*/ + // Inputs + cyc, + i0, + i1 +); + /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining + input [31:0] cyc; + input [1:0] i0; + input [1:0] i1; + initial begin + if (cyc == 32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); + end endmodule diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v index 49412fe83..13503ee12 100644 --- a/test_regress/t/t_mem_packed.v +++ b/test_regress/t/t_mem_packed.v @@ -4,177 +4,176 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + //Simple debug: + //wire [1:1] wir_a [3:3] [2:2]; //11 + //logic [1:1] log_a [3:3] [2:2]; //12 + //wire [3:3] [2:2] [1:1] wir_p; //13 + //logic [3:3] [2:2] [1:1] log_p; //14 - //Simple debug: - //wire [1:1] wir_a [3:3] [2:2]; //11 - //logic [1:1] log_a [3:3] [2:2]; //12 - //wire [3:3] [2:2] [1:1] wir_p; //13 - //logic [3:3] [2:2] [1:1] log_p; //14 - - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; `ifdef IVERILOG - reg [7:0] arr [3:0]; - wire [7:0] arr_w [3:0]; + reg [7:0] arr[3:0]; + wire [7:0] arr_w[3:0]; `else - reg [3:0] [7:0] arr; - wire [3:0] [7:0] arr_w; + reg [3:0][7:0] arr; + wire [3:0][7:0] arr_w; `endif - reg [7:0] sum; - reg [7:0] sum_w; - integer i0; + reg [7:0] sum; + reg [7:0] sum_w; + integer i0; - initial begin - for (i0=0; i0<5; i0=i0+1) begin - arr[i0] = 1 << (i0[1:0]*2); - end - end + initial begin + for (i0 = 0; i0 < 5; i0 = i0 + 1) begin + arr[i0] = 1 << (i0[1:0] * 2); + end + end - assign arr_w = arr; + assign arr_w = arr; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - sum <= 0; - sum_w <= 0; - end - else if (cyc >= 10 && cyc < 14) begin - sum <= sum + arr[cyc-10]; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + sum <= 0; + sum_w <= 0; + end + else if (cyc >= 10 && cyc < 14) begin + sum <= sum + arr[cyc-10]; - sum_w <= sum_w + arr_w[cyc-10]; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); - if (sum != 8'h55) $stop; - if (sum != sum_w) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + sum_w <= sum_w + arr_w[cyc-10]; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); + if (sum != 8'h55) $stop; + if (sum != sum_w) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - // Test ordering of packed dimensions - logic [31:0] data_out; - logic [31:0] data_out2; - logic [0:0] [2:0] [31:0] data_in; - logic [31:0] data_in2 [0:0] [2:0]; - assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; - assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; + // Test ordering of packed dimensions + logic [31:0] data_out; + logic [31:0] data_out2; + logic [0:0][2:0][31:0] data_in; + logic [31:0] data_in2[0:0][2:0]; + assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; + assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; - logic [31:0] last_data_out; - always @ (posedge clk) begin - if (cyc <= 2) begin - data_in[0][0] <= 0; - data_in[0][1] <= 0; - data_in[0][2] <= 0; - data_in2[0][0] <= 0; - data_in2[0][1] <= 0; - data_in2[0][2] <= 0; - end - else if (cyc > 2 && cyc < 99) begin - data_in[0][0] <= data_in[0][0] + 1; - data_in[0][1] <= data_in[0][1] + 1; - data_in[0][2] <= data_in[0][2] + 1; - data_in2[0][0] <= data_in2[0][0] + 1; - data_in2[0][1] <= data_in2[0][1] + 1; - data_in2[0][2] <= data_in2[0][2] + 1; - last_data_out <= data_out; + logic [31:0] last_data_out; + always @(posedge clk) begin + if (cyc <= 2) begin + data_in[0][0] <= 0; + data_in[0][1] <= 0; + data_in[0][2] <= 0; + data_in2[0][0] <= 0; + data_in2[0][1] <= 0; + data_in2[0][2] <= 0; + end + else if (cyc > 2 && cyc < 99) begin + data_in[0][0] <= data_in[0][0] + 1; + data_in[0][1] <= data_in[0][1] + 1; + data_in[0][2] <= data_in[0][2] + 1; + data_in2[0][0] <= data_in2[0][0] + 1; + data_in2[0][1] <= data_in2[0][1] + 1; + data_in2[0][2] <= data_in2[0][2] + 1; + last_data_out <= data_out; `ifdef TEST_VERBOSE - $write("data_out %0x %0x\n", data_out, last_data_out); + $write("data_out %0x %0x\n", data_out, last_data_out); `endif - if (cyc > 4 && data_out != last_data_out + 3) $stop; - if (cyc > 4 && data_out != data_out2) $stop; + if (cyc > 4 && data_out != last_data_out + 3) $stop; + if (cyc > 4 && data_out != data_out2) $stop; + end + end + + // Test for mixed implicit/explicit dimensions and all implicit packed + bit [3:0][7:0][1:0] vld[1:0][1:0]; + bit [3:0][7:0][1:0] vld2; + + // There are specific nodes for Or, Xor, Xnor and And + logic vld_or; + logic vld2_or; + assign vld_or = |vld[0][0]; + assign vld2_or = |vld2; + + logic vld_xor; + logic vld2_xor; + assign vld_xor = ^vld[0][0]; + assign vld2_xor = ^vld2; + + logic vld_xnor; + logic vld2_xnor; + assign vld_xnor = ~^vld[0][0]; + assign vld2_xnor = ~^vld2; + + logic vld_and; + logic vld2_and; + assign vld_and = &vld[0][0]; + assign vld2_and = &vld2; + + // Bit reductions should be cloned, other unary operations should clone the + // entire assign. + bit [3:0][7:0][1:0] not_lhs; + bit [3:0][7:0][1:0] not_rhs; + assign not_lhs = ~not_rhs; + + // Test an AstNodeUniop that shouldn't be expanded + bit [3:0][7:0][1:0] vld2_inv; + assign vld2_inv = ~vld2; + + initial begin + for (int i = 0; i < 4; i = i + 2) begin + for (int j = 0; j < 8; j = j + 2) begin + vld[0][0][i][j] = 2'b00; + vld[0][0][i+1][j+1] = 2'b00; + vld2[i][j] = 2'b00; + vld2[i+1][j+1] = 2'b00; + not_rhs[i][j] = i[1:0]; + not_rhs[i+1][j+1] = i[1:0]; end - end + end + end - // Test for mixed implicit/explicit dimensions and all implicit packed - bit [3:0][7:0][1:0] vld [1:0][1:0]; - bit [3:0][7:0][1:0] vld2; - // There are specific nodes for Or, Xor, Xnor and And - logic vld_or; - logic vld2_or; - assign vld_or = |vld[0][0]; - assign vld2_or = |vld2; + logic [3:0] expect_cyc; + initial expect_cyc = 'd15; - logic vld_xor; - logic vld2_xor; - assign vld_xor = ^vld[0][0]; - assign vld2_xor = ^vld2; - - logic vld_xnor; - logic vld2_xnor; - assign vld_xnor = ~^vld[0][0]; - assign vld2_xnor = ~^vld2; - - logic vld_and; - logic vld2_and; - assign vld_and = &vld[0][0]; - assign vld2_and = &vld2; - - // Bit reductions should be cloned, other unary operations should clone the - // entire assign. - bit [3:0][7:0][1:0] not_lhs; - bit [3:0][7:0][1:0] not_rhs; - assign not_lhs = ~not_rhs; - - // Test an AstNodeUniop that shouldn't be expanded - bit [3:0][7:0][1:0] vld2_inv; - assign vld2_inv = ~vld2; - - initial begin - for (int i=0; i<4; i=i+2) begin - for (int j=0; j<8; j=j+2) begin - vld[0][0][i][j] = 2'b00; - vld[0][0][i+1][j+1] = 2'b00; - vld2[i][j] = 2'b00; - vld2[i+1][j+1] = 2'b00; - not_rhs[i][j] = i[1:0]; - not_rhs[i+1][j+1] = i[1:0]; - end + always @(posedge clk) begin + expect_cyc <= expect_cyc + 1; + for (int i = 0; i < 4; i = i + 1) begin + for (int j = 0; j < 8; j = j + 1) begin + vld[0][0][i][j] <= vld[0][0][i][j] + 1; + vld2[i][j] <= vld2[i][j] + 1; + if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; + not_rhs[i][j] <= not_rhs[i][j] + 1; end - end + end + if (cyc % 8 == 0) begin + vld[0][0][0][0] <= vld[0][0][0][0] - 1; + vld2[0][0] <= vld2[0][0] - 1; + end + if (expect_cyc < 8 && !vld_xor) $stop; + else if (expect_cyc > 7 && vld_xor) $stop; + if (expect_cyc < 8 && vld_xnor) $stop; + else if (expect_cyc > 7 && !vld_xnor) $stop; - logic [3:0] expect_cyc; initial expect_cyc = 'd15; + if (expect_cyc == 15 && vld_or) $stop; + else if (expect_cyc == 11 && vld_or) $stop; + else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; - always @(posedge clk) begin - expect_cyc <= expect_cyc + 1; - for (int i=0; i<4; i=i+1) begin - for (int j=0; j<8; j=j+1) begin - vld[0][0][i][j] <= vld[0][0][i][j] + 1; - vld2[i][j] <= vld2[i][j] + 1; - if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; - not_rhs[i][j] <= not_rhs[i][j] + 1; - end - end - if (cyc % 8 == 0) begin - vld[0][0][0][0] <= vld[0][0][0][0] - 1; - vld2[0][0] <= vld2[0][0] - 1; - end - if (expect_cyc < 8 && !vld_xor) $stop; - else if (expect_cyc > 7 && vld_xor) $stop; + if (expect_cyc == 10 && !vld_and) $stop; + else if (expect_cyc == 14 && !vld_and) $stop; + else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; - if (expect_cyc < 8 && vld_xnor) $stop; - else if (expect_cyc > 7 && !vld_xnor) $stop; - - if (expect_cyc == 15 && vld_or) $stop; - else if (expect_cyc == 11 && vld_or) $stop; - else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; - - if (expect_cyc == 10 && !vld_and) $stop; - else if (expect_cyc == 14 && !vld_and) $stop; - else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; - - if (vld_xor != vld2_xor) $stop; - if (vld_xnor != vld2_xnor) $stop; - if (vld_or != vld2_or) $stop; - if (vld_and != vld2_and) $stop; - end + if (vld_xor != vld2_xor) $stop; + if (vld_xnor != vld2_xnor) $stop; + if (vld_or != vld2_or) $stop; + if (vld_and != vld2_and) $stop; + end endmodule diff --git a/test_regress/t/t_mem_packed_assign.v b/test_regress/t/t_mem_packed_assign.v index b6c85b175..d58bddc39 100644 --- a/test_regress/t/t_mem_packed_assign.v +++ b/test_regress/t/t_mem_packed_assign.v @@ -4,36 +4,37 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - /* verilator lint_off WIDTH */ + /* verilator lint_off WIDTH */ - input clk; + integer cyc; + initial cyc = 0; + logic [31:0] arr_c; + initial arr_c = 0; + logic [7:0][3:0] arr; - integer cyc; initial cyc = 0; - logic [31:0] arr_c; initial arr_c = 0; - logic [7:0] [3:0] arr; + logic [31:0] arr2_c; + initial arr2_c = 0; + logic [7:0][3:0] arr2; + assign arr2_c = arr2; - logic [31:0] arr2_c; initial arr2_c = 0; - logic [7:0] [3:0] arr2; - assign arr2_c = arr2; - - always @ (posedge clk) begin - cyc <= cyc + 1; - arr_c <= arr_c + 1; - arr2 <= arr2 + 1; + always @(posedge clk) begin + cyc <= cyc + 1; + arr_c <= arr_c + 1; + arr2 <= arr2 + 1; `ifdef TEST_VERBOSE - $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]); + $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], + arr[3]); `endif - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - /* verilator lint_on WIDTH */ + /* verilator lint_on WIDTH */ endmodule diff --git a/test_regress/t/t_mem_packed_bad.out b/test_regress/t/t_mem_packed_bad.out index f3292a570..25f7ab4db 100644 --- a/test_regress/t/t_mem_packed_bad.out +++ b/test_regress/t/t_mem_packed_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_mem_packed_bad.v:27:32: CONST '28'h0' unexpected in assignment to unpacked array - 27 | ch04 <= 56'd0; - | ^~~~~ +%Error: t/t_mem_packed_bad.v:26:13: CONST '28'h0' unexpected in assignment to unpacked array + 26 | ch04 <= 56'd0; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_mem_packed_bad.v b/test_regress/t/t_mem_packed_bad.v index 440674eac..eb796c920 100644 --- a/test_regress/t/t_mem_packed_bad.v +++ b/test_regress/t/t_mem_packed_bad.v @@ -4,32 +4,31 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - logic [1:0][27:0] ch01; - logic [1:0][27:0] ch02; - logic [1:0][27:0] ch03; - logic [27:0] ch04[1:0]; + logic [1:0][27:0] ch01; + logic [1:0][27:0] ch02; + logic [1:0][27:0] ch03; + logic [27:0] ch04[1:0]; - /* verilator lint_off WIDTH */ - always @ (posedge clk) begin - // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. - ch01 <= {{2{28'd4}}}; - ch02 <= {{2{cyc}}}; - ch03 <= 56'd0; - // LHS is 1D packed, 1D unpacked, this should never work. - ch04 <= 56'd0; - $display("ch01: %0x %0x", ch01[0], ch01[1]); - $display("ch01: %0x %0x", ch02[0], ch02[1]); - $display("ch01: %0x %0x", ch03[0], ch03[1]); - $display("ch01: %0x %0x", ch04[0], ch04[1]); - end - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ + always @(posedge clk) begin + // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. + ch01 <= {{2{28'd4}}}; + ch02 <= {{2{cyc}}}; + ch03 <= 56'd0; + // LHS is 1D packed, 1D unpacked, this should never work. + ch04 <= 56'd0; + $display("ch01: %0x %0x", ch01[0], ch01[1]); + $display("ch01: %0x %0x", ch02[0], ch02[1]); + $display("ch01: %0x %0x", ch03[0], ch03[1]); + $display("ch01: %0x %0x", ch04[0], ch04[1]); + end + /* verilator lint_on WIDTH */ endmodule diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v index 668f88dd0..d4bd6bf40 100644 --- a/test_regress/t/t_mem_shift.v +++ b/test_regress/t/t_mem_shift.v @@ -4,59 +4,57 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; - integer cyc; initial cyc = 0; - reg [63:0] crc; + integer i; + reg [63:0] mem[7:0]; - integer i; - reg [63:0] mem [7:0]; + always @(posedge clk) begin + if (cyc == 1) begin + for (i = 0; i < 8; i = i + 1) begin + mem[i] <= 64'h0; + end + end + else begin + mem[0] <= crc; + for (i = 1; i < 8; i = i + 1) begin + mem[i] <= mem[i-1]; + end + end + end - always @ (posedge clk) begin - if (cyc==1) begin - for (i=0; i<8; i=i+1) begin - mem[i] <= 64'h0; - end - end - else begin - mem[0] <= crc; - for (i=1; i<8; i=i+1) begin - mem[i] <= mem[i-1]; - end - end - end + wire [63:0] outData = mem[7]; - wire [63:0] outData = mem[7]; - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc==90) begin - if (outData != 64'h1265e3bddcd9bc27) $stop; - end - else if (cyc==91) begin - if (outData != 64'h24cbc77bb9b3784e) $stop; - end - else if (cyc==92) begin - end - else if (cyc==93) begin - end - else if (cyc==94) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc == 90) begin + if (outData != 64'h1265e3bddcd9bc27) $stop; + end + else if (cyc == 91) begin + if (outData != 64'h24cbc77bb9b3784e) $stop; + end + else if (cyc == 92) begin + end + else if (cyc == 93) begin + end + else if (cyc == 94) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mem_slice.v b/test_regress/t/t_mem_slice.v index 26c7f8b39..c05a4c88e 100644 --- a/test_regress/t/t_mem_slice.v +++ b/test_regress/t/t_mem_slice.v @@ -4,121 +4,118 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic use_AnB; + logic [1:0] active_command[8:0]; + logic [1:0] command_A[8:0]; + logic [1:0] command_B[8:0]; - logic use_AnB; - logic [1:0] active_command [8:0]; - logic [1:0] command_A [8:0]; - logic [1:0] command_B [8:0]; + logic [1:0] active_command2[8:0]; + logic [1:0] command_A2[8:0]; + logic [1:0] command_B2[8:0]; - logic [1:0] active_command2 [8:0]; - logic [1:0] command_A2 [8:0]; - logic [1:0] command_B2 [8:0]; + logic [1:0] active_command3[1:0][2:0][3:0]; + logic [1:0] command_A3[1:0][2:0][3:0]; + logic [1:0] command_B3[1:0][2:0][3:0]; - logic [1:0] active_command3 [1:0][2:0][3:0]; - logic [1:0] command_A3 [1:0][2:0][3:0]; - logic [1:0] command_B3 [1:0][2:0][3:0]; + logic [2:0] use_A4nB4; + logic [8:0][1:0] active_command4; + logic [8:0][1:0] command_A4; + logic [8:0][1:0] command_B4; - logic [2:0] use_A4nB4; - logic [8:0][1:0] active_command4; - logic [8:0][1:0] command_A4; - logic [8:0][1:0] command_B4; + logic [8:0] pipe1[7:0]; + logic [8:0] pipe1_input; - logic [8:0] pipe1 [7:0]; - logic [8:0] pipe1_input; + integer cyc; - integer cyc; + assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing + assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; - assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; - assign active_command2 = (use_AnB) ? command_A2 : command_B2; - // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing - assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; + // Check we can cope with things other than packed arrays + assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; - // Check we can cope with things other than packed arrays - assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; + always @(posedge clk) begin + pipe1_input <= pipe1_input + 1; + pipe1[0] <= pipe1_input; + pipe1[7:1] <= pipe1[6:0]; + end - always @ (posedge clk) begin - pipe1_input <= pipe1_input + 1; - pipe1[0] <= pipe1_input; - pipe1[7:1] <= pipe1[6:0]; - end + logic [3:0][13:0] iq_read_data[15:0]; + logic [3:0][13:0] iq_data; + logic [3:0] sel; - logic [3:0][13:0] iq_read_data [15:0]; - logic [3:0][13:0] iq_data; - logic [3:0] sel; + assign iq_data = iq_read_data[sel]; - assign iq_data = iq_read_data[sel]; + always @(posedge clk) begin + sel = sel + 1; + end - always @ (posedge clk) begin - sel = sel + 1; - end - - initial begin - cyc = 0; - use_AnB = 0; - for (int i = 0; i < 7; ++i) begin - command_A[i] = 2'b00; - command_B[i] = 2'b11; - command_A2[i] = 2'b00; - command_B2[i] = 2'b11; - pipe1_input = 9'b0; + initial begin + cyc = 0; + use_AnB = 0; + for (int i = 0; i < 7; ++i) begin + command_A[i] = 2'b00; + command_B[i] = 2'b11; + command_A2[i] = 2'b00; + command_B2[i] = 2'b11; + pipe1_input = 9'b0; + end + for (int i = 0; i < 2; ++i) begin + for (int j = 0; j < 3; ++j) begin + for (int k = 0; k < 4; ++k) begin + command_A3[i][j][k] = 2'b00; + command_B3[i][j][k] = 2'b11; + end end - for (int i = 0; i < 2; ++i) begin - for (int j = 0; j < 3; ++j) begin - for (int k = 0; k < 4; ++k) begin - command_A3[i][j][k] = 2'b00; - command_B3[i][j][k] = 2'b11; - end - end - end - end + end + end - always @ (posedge clk) begin - use_AnB <= ~use_AnB; - cyc <= cyc + 1; - if (use_AnB) begin - if (active_command[3] != 2'b00) begin - $stop; - end - if (active_command2[3] != 2'b00) begin - $stop; - end - if (active_command3[0][1][2] != 2'b00) begin - $stop; - end + always @(posedge clk) begin + use_AnB <= ~use_AnB; + cyc <= cyc + 1; + if (use_AnB) begin + if (active_command[3] != 2'b00) begin + $stop; end - if (!use_AnB) begin - if (active_command[3] != 2'b11) begin - $stop; - end - if (active_command2[3] != 2'b11) begin - $stop; - end + if (active_command2[3] != 2'b00) begin + $stop; end - end + if (active_command3[0][1][2] != 2'b00) begin + $stop; + end + end + if (!use_AnB) begin + if (active_command[3] != 2'b11) begin + $stop; + end + if (active_command2[3] != 2'b11) begin + $stop; + end + end + end - logic [8:0] last_pipe; - always @(posedge clk) begin - if (cyc < 3) begin - last_pipe <= pipe1[0]; + logic [8:0] last_pipe; + always @(posedge clk) begin + if (cyc < 3) begin + last_pipe <= pipe1[0]; + end + else begin + if (last_pipe + 1 != pipe1[0]) begin + $stop; end else begin - if (last_pipe + 1 != pipe1[0]) begin - $stop; - end - else begin - last_pipe <= pipe1[0]; - end + last_pipe <= pipe1[0]; end - if (cyc > 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + if (cyc > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule : t diff --git a/test_regress/t/t_mem_slice_bad.out b/test_regress/t/t_mem_slice_bad.out index 3d62544dd..77db71631 100644 --- a/test_regress/t/t_mem_slice_bad.out +++ b/test_regress/t/t_mem_slice_bad.out @@ -1,30 +1,30 @@ -%Error: t/t_mem_slice_bad.v:39:31: Slice selection index '[2:0]' outside data type's '[1:0]' +%Error: t/t_mem_slice_bad.v:36:30: Slice selection index '[2:0]' outside data type's '[1:0]' : ... note: In instance 't' - 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - | ^ + 36 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_mem_slice_bad.v:39:36: Slice selection index '[3:0]' outside data type's '[2:0]' +%Error: t/t_mem_slice_bad.v:36:35: Slice selection index '[3:0]' outside data type's '[2:0]' : ... note: In instance 't' - 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - | ^ -%Error: t/t_mem_slice_bad.v:39:72: Slice selection index '[2:0]' outside data type's '[1:0]' + 36 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:36:71: Slice selection index '[2:0]' outside data type's '[1:0]' : ... note: In instance 't' - 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - | ^ -%Error: t/t_mem_slice_bad.v:39:77: Slice selection index '[3:0]' outside data type's '[2:0]' + 36 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:36:76: Slice selection index '[3:0]' outside data type's '[2:0]' : ... note: In instance 't' - 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - | ^ -%Error: t/t_mem_slice_bad.v:39:105: Slice selection index '[3:0]' outside data type's '[1:0]' + 36 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:36:104: Slice selection index '[3:0]' outside data type's '[1:0]' : ... note: In instance 't' - 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - | ^ -%Error: t/t_mem_slice_bad.v:51:41: Slice selection index '[8:0]' outside data type's '[7:0]' + 36 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:48:39: Slice selection index '[8:0]' outside data type's '[7:0]' : ... note: In instance 't' - 51 | active_command4[7:0] <= command_A4[8:0]; - | ^ -%Error: t/t_mem_slice_bad.v:56:28: Illegal assignment: Unmatched array sizes in dimension 0 (9 vs 8) + 48 | active_command4[7:0] <= command_A4[8:0]; + | ^ +%Error: t/t_mem_slice_bad.v:53:26: Illegal assignment: Unmatched array sizes in dimension 0 (9 vs 8) : ... note: In instance 't' - 56 | active_command5[8:0] = command_A5[7:0]; - | ^ + 53 | active_command5[8:0] = command_A5[7:0]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_bad.v b/test_regress/t/t_mem_slice_bad.v index ca5535af9..a90c5e4d3 100644 --- a/test_regress/t/t_mem_slice_bad.v +++ b/test_regress/t/t_mem_slice_bad.v @@ -4,56 +4,53 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic use_AnB; - logic use_AnB; + logic [1:0] active_command[8:0]; + logic [1:0] command_A[8:0]; + logic [1:0] command_B[8:0]; - logic [1:0] active_command [8:0]; - logic [1:0] command_A [8:0]; - logic [1:0] command_B [8:0]; + logic [1:0] active_command2[8:0]; + logic [1:0] command_A2[7:0]; + logic [1:0] command_B2[8:0]; - logic [1:0] active_command2 [8:0]; - logic [1:0] command_A2 [7:0]; - logic [1:0] command_B2 [8:0]; + logic [1:0] active_command3[1:0][2:0][3:0]; + logic [1:0] command_A3[1:0][2:0][3:0]; + logic [1:0] command_B3[1:0][2:0][3:0]; - logic [1:0] active_command3 [1:0][2:0][3:0]; - logic [1:0] command_A3 [1:0][2:0][3:0]; - logic [1:0] command_B3 [1:0][2:0][3:0]; + logic [1:0] active_command4[8:0]; + logic [1:0] command_A4[7:0]; - logic [1:0] active_command4 [8:0]; - logic [1:0] command_A4 [7:0]; + logic [1:0] active_command5[8:0]; + logic [1:0] command_A5[7:0]; - logic [1:0] active_command5 [8:0]; - logic [1:0] command_A5 [7:0]; + // Single dimension assign + assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0]; + // Assignment of entire arrays + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Multi-dimension assign + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - // Single dimension assign - assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0]; - // Assignment of entire arrays - assign active_command2 = (use_AnB) ? command_A2 : command_B2; - // Multi-dimension assign - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + // Supported: Delayed assigment with RHS Var == LHS Var + logic [7:0] arrd[7:0]; + always_ff @(posedge clk) arrd[7:4] <= arrd[3:0]; - // Supported: Delayed assigment with RHS Var == LHS Var - logic [7:0] arrd [7:0]; - always_ff @(posedge clk) arrd[7:4] <= arrd[3:0]; + // Unsupported: Non-delayed assigment with RHS Var == LHS Var + logic [7:0] arr[7:0]; + assign arr[7:4] = arr[3:0]; - // Unsupported: Non-delayed assigment with RHS Var == LHS Var - logic [7:0] arr [7:0]; - assign arr[7:4] = arr[3:0]; + // Delayed assign + always @(posedge clk) begin + active_command4[7:0] <= command_A4[8:0]; + end - // Delayed assign - always @(posedge clk) begin - active_command4[7:0] <= command_A4[8:0]; - end - - // Combinational assign - always_comb begin - active_command5[8:0] = command_A5[7:0]; - end + // Combinational assign + always_comb begin + active_command5[8:0] = command_A5[7:0]; + end endmodule : t diff --git a/test_regress/t/t_mem_slice_conc_bad.out b/test_regress/t/t_mem_slice_conc_bad.out index 075f73973..915f662d6 100644 --- a/test_regress/t/t_mem_slice_conc_bad.out +++ b/test_regress/t/t_mem_slice_conc_bad.out @@ -1,14 +1,14 @@ -%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:46:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' - : ... note: In instance 't' - 46 | rst <= 1'b0; - | ^~~ +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:44:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 44 | rst <= 1'b0; + | ^~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:50:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' - : ... note: In instance 't' - 50 | rst <= 1'b1; - | ^~~ -%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:53:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' - : ... note: In instance 't' - 53 | rst <= 1'b0; - | ^~~ +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:48:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 48 | rst <= 1'b1; + | ^~~ +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:51:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 51 | rst <= 1'b0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v index f5a2f0c71..1aafbefe2 100644 --- a/test_regress/t/t_mem_slice_conc_bad.v +++ b/test_regress/t/t_mem_slice_conc_bad.v @@ -6,114 +6,112 @@ // // bug354 -typedef logic [5:0] data_t; +typedef logic [5:0] data_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire rst; - data_t iii_in = crc[5:0]; - data_t jjj_in = crc[11:6]; - data_t iii_out; - data_t jjj_out; - logic [1:0] ctl0 = crc[63:62]; + // Take CRC data and apply to testblock inputs + wire rst; + data_t iii_in = crc[5:0]; + data_t jjj_in = crc[11:6]; + data_t iii_out; + data_t jjj_out; + logic [1:0] ctl0 = crc[63:62]; - aaa aaa (.*); + aaa aaa (.*); - // Aggregate outputs into a single result vector - wire [63:0] result = {64'h0}; + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - rst <= 1'b0; - end - else if (cyc<10) begin - sum <= 64'h0; - rst <= 1'b1; - end - else if (cyc<90) begin - rst <= 1'b0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc < 10) begin + sum <= 64'h0; + rst <= 1'b1; + end + else if (cyc < 90) begin + rst <= 1'b0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module bbb - ( - output data_t ggg_out[1:0], - input data_t ggg_in [1:0], - input [1:0] [1:0] ctl, +module bbb ( + output data_t ggg_out[1:0], + input data_t ggg_in[1:0], + input [1:0][1:0] ctl, - input logic clk, - input logic rst - ); + input logic clk, + input logic rst +); - genvar i; + genvar i; - generate - for (i=0; i<2; i++) begin: PPP - always_ff @(posedge clk) begin - if (rst) begin - ggg_out[i] <= 6'b0; + generate + for (i = 0; i < 2; i++) begin : PPP + always_ff @(posedge clk) begin + if (rst) begin + ggg_out[i] <= 6'b0; + end + else begin + if (ctl[i][0]) begin + if (ctl[i][1]) begin + ggg_out[i] <= ~ggg_in[i]; end else begin - if (ctl[i][0]) begin - if (ctl[i][1]) begin - ggg_out[i] <= ~ggg_in[i]; - end else begin - ggg_out[i] <= ggg_in[i]; - end - end + ggg_out[i] <= ggg_in[i]; end - end + end + end end - endgenerate + end + endgenerate endmodule -module aaa - ( - input data_t iii_in, - input data_t jjj_in, - input [1:0] ctl0, +module aaa ( + input data_t iii_in, + input data_t jjj_in, + input [1:0] ctl0, output data_t iii_out, output data_t jjj_out, - input logic clk, - input logic rst - ); + input logic clk, + input logic rst +); - // Below is a bug; {} concat isn't used to make arrays + // Below is a bug; {} concat isn't used to make arrays bbb bbb ( - .ggg_in ({jjj_in, iii_in}), - .ggg_out ({jjj_out, iii_out}), - .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), - .*); + .ggg_in({jjj_in, iii_in}), + .ggg_out({jjj_out, iii_out}), + .ctl({{1'b1, ctl0[1]}, {1'b0, ctl0[0]}}), + .* + ); endmodule diff --git a/test_regress/t/t_mem_slice_dtype_bad.out b/test_regress/t/t_mem_slice_dtype_bad.out index b3b82259d..9b3748af6 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.out +++ b/test_regress/t/t_mem_slice_dtype_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_mem_slice_dtype_bad.v:23:45: ADD unexpected in assignment to unpacked array - 23 | completed_cnt[id] <= completed_cnt_dp + 1; - | ^ +%Error: t/t_mem_slice_dtype_bad.v:22:43: ADD unexpected in assignment to unpacked array + 22 | completed_cnt[id] <= completed_cnt_dp + 1; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_dtype_bad.v b/test_regress/t/t_mem_slice_dtype_bad.v index 75a28431d..8ce56e06d 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.v +++ b/test_regress/t/t_mem_slice_dtype_bad.v @@ -6,36 +6,35 @@ typedef logic [$clog2(26+1)-1:0] way_cnt_t; -module t(/*AUTOARG*/ - // Inputs - clk - ); - input logic clk; - int cyc; +module t ( + input logic clk +); - //bug795 - way_cnt_t completed_cnt [31:0][1:0]; - way_cnt_t completed_cnt_dp [1:0]; + int cyc; - assign completed_cnt_dp = completed_cnt[id]; + //bug795 + way_cnt_t completed_cnt[31:0][1:0]; + way_cnt_t completed_cnt_dp[1:0]; - always_ff @(posedge clk) begin - completed_cnt[id] <= completed_cnt_dp + 1; - end + assign completed_cnt_dp = completed_cnt[id]; - // bug796 - logic [4:0] id; - logic [39:0] way_mask; - logic [39:0] addr[31:0][1:0]; - always_ff @(posedge clk) begin - cyc <= cyc + 1; - id <= cyc[4:0]; - if (cyc==1) begin - way_mask <= '0; - id <= 1; - end - else if (cyc==2) begin - assert((addr[id] & way_mask) == 0); - end + always_ff @(posedge clk) begin + completed_cnt[id] <= completed_cnt_dp + 1; + end + + // bug796 + logic [4:0] id; + logic [39:0] way_mask; + logic [39:0] addr[31:0][1:0]; + always_ff @(posedge clk) begin + cyc <= cyc + 1; + id <= cyc[4:0]; + if (cyc == 1) begin + way_mask <= '0; + id <= 1; + end + else if (cyc == 2) begin + assert ((addr[id] & way_mask) == 0); + end end endmodule diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index be3ea9de8..f72f8b3d6 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -8,19 +8,19 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); - input Clk; - input [1:0] SlotIdx; - input BitToChange; - input BitVal; - input [1:0] SlotToReturn; - output bit [1:0] OutputVal; + input Clk; + input [1:0] SlotIdx; + input BitToChange; + input BitVal; + input [1:0] SlotToReturn; + output bit [1:0] OutputVal; - bit [1:0] Array[2:0]; + bit [1:0] Array[2:0]; - always @(posedge Clk) - begin - Array[SlotIdx][BitToChange] <= #`RegDel BitVal; + always @(posedge Clk) + begin + Array[SlotIdx][BitToChange] <= #`RegDel BitVal; - OutputVal = Array[SlotToReturn]; - end + OutputVal = Array[SlotToReturn]; + end endmodule diff --git a/test_regress/t/t_mem_trace_split.v b/test_regress/t/t_mem_trace_split.v index d83f9ab23..7279d52ed 100644 --- a/test_regress/t/t_mem_trace_split.v +++ b/test_regress/t/t_mem_trace_split.v @@ -4,28 +4,25 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic [31:0] mem_a[32]; + logic [15:0] mem_b[32]; - logic [31:0] mem_a [32]; - logic [15:0] mem_b [32]; + int cyc = 0; - int cyc = 0; - - // finish report - always @ (posedge clk) begin - cyc <= cyc + 1; - mem_a[cyc] <= cyc; - mem_b[cyc] <= 16'(cyc); - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // finish report + always @(posedge clk) begin + cyc <= cyc + 1; + mem_a[cyc] <= cyc; + mem_b[cyc] <= 16'(cyc); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v index f4618640f..cc71aea0f 100644 --- a/test_regress/t/t_mem_twoedge.v +++ b/test_regress/t/t_mem_twoedge.v @@ -4,115 +4,113 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // verilator lint_off MULTIDRIVEN - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - wire [15:0] out2; // From test of Test.v - // End of automatics - // verilator lint_on MULTIDRIVEN + // verilator lint_off MULTIDRIVEN + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + wire [15:0] out2; // From test of Test.v + // End of automatics + // verilator lint_on MULTIDRIVEN - Test test ( - .en (crc[21:20]), - .a1 (crc[19:18]), - .a0 (crc[17:16]), - .d1 (crc[15:8]), - .d0 (crc[7:0]), - /*AUTOINST*/ - // Outputs - .out (out[31:0]), - .out2 (out2[15:0]), - // Inputs - .clk (clk)); + Test test ( + .en(crc[21:20]), + .a1(crc[19:18]), + .a0(crc[17:16]), + .d1(crc[15:8]), + .d0(crc[7:0]), + /*AUTOINST*/ + // Outputs + .out (out[31:0]), + .out2 (out2[15:0]), + // Inputs + .clk (clk)); - // Aggregate outputs into a single result vector - wire [63:0] result = {out2, 16'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {out2, 16'h0, out}; - // Test loop + // Test loop `ifdef TEST_VERBOSE - always @ (negedge clk) begin - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); - end + always @(negedge clk) begin + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + end `endif - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - test.clear(); - end - else if (cyc<10) begin - sum <= 64'h0; - test.clear(); - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hc68a94a34ec970aa - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + test.clear(); + end + else if (cyc < 10) begin + sum <= 64'h0; + test.clear(); + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hc68a94a34ec970aa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, out2, - // Inputs - clk, en, a0, a1, d0, d1 - ); +module Test ( /*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, en, a0, a1, d0, d1 + ); - input clk; - input [1:0] en; - input [1:0] a0; - input [1:0] a1; - input [7:0] d0; - input [7:0] d1; - output reg [31:0] out; - // verilator lint_off MULTIDRIVEN - output reg [15:0] out2; + input clk; + input [1:0] en; + input [1:0] a0; + input [1:0] a1; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + // verilator lint_off MULTIDRIVEN + output reg [15:0] out2; - reg [7:0] mem [4]; - // verilator lint_on MULTIDRIVEN + reg [7:0] mem[4]; + // verilator lint_on MULTIDRIVEN - task clear(); - for (int i=0; i<4; ++i) mem[i] = 0; - endtask + task clear(); + for (int i = 0; i < 4; ++i) mem[i] = 0; + endtask - always @(posedge clk) begin - if (en[0]) begin - mem[a0] <= d0; - out2[7:0] <= d0; - end - end - always @(negedge clk) begin - if (en[1]) begin - mem[a1] <= d1; - out2[15:8] <= d0; - end - end + always @(posedge clk) begin + if (en[0]) begin + mem[a0] <= d0; + out2[7:0] <= d0; + end + end + always @(negedge clk) begin + if (en[1]) begin + mem[a1] <= d1; + out2[15:8] <= d0; + end + end - assign out = {mem[3],mem[2],mem[1],mem[0]}; + assign out = {mem[3], mem[2], mem[1], mem[0]}; endmodule diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 1d5f8006b..df1f870ba 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -1,11 +1,11 @@ -%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:8: Ascending bit range vector: left < right of bit range: [0:1] +%Warning-ASCRANGE: t/t_metacmt_onoff.v:9:7: Ascending bit range vector: left < right of bit range: [0:1] : ... note: In instance 't' - 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; - | ^ + 9 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; + | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. -%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:105: Ascending bit range vector: left < right of bit range: [0:3] +%Warning-ASCRANGE: t/t_metacmt_onoff.v:9:104: Ascending bit range vector: left < right of bit range: [0:3] : ... note: In instance 't' - 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; - | ^ + 9 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_metacmt_onoff.v b/test_regress/t/t_metacmt_onoff.v index 80011e19f..3022af412 100644 --- a/test_regress/t/t_metacmt_onoff.v +++ b/test_regress/t/t_metacmt_onoff.v @@ -4,10 +4,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - // Test turning on and off a message on the same line; only middle reg shouldn't warn - reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Test turning on and off a message on the same line; only middle reg shouldn't warn + // verilog_format: off + reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mod_automatic.v b/test_regress/t/t_mod_automatic.v index d0ad14293..a568c3ab0 100644 --- a/test_regress/t/t_mod_automatic.v +++ b/test_regress/t/t_mod_automatic.v @@ -6,42 +6,42 @@ module automatic t; - task static accum_s(input integer value, output integer result); - static int acc = 1; - acc = acc + value; - result = acc; - endtask + task static accum_s(input integer value, output integer result); + static int acc = 1; + acc = acc + value; + result = acc; + endtask - task accum_a(input integer value, output integer result); - int acc = 1; // automatic - acc = acc + value; - result = acc; - endtask + task accum_a(input integer value, output integer result); + int acc = 1; // automatic + acc = acc + value; + result = acc; + endtask - integer value; + integer value; - reg failed = 0; // Static + reg failed = 0; // Static - initial begin - accum_s(2, value); - $display("%d", value); - if (value !== 3) failed = 1; + initial begin + accum_s(2, value); + $display("%d", value); + if (value !== 3) failed = 1; - accum_s(3, value); - $display("%d", value); - if (value !== 6) failed = 1; + accum_s(3, value); + $display("%d", value); + if (value !== 6) failed = 1; - accum_a(2, value); - $display("%d", value); - if (value !== 3) failed = 1; + accum_a(2, value); + $display("%d", value); + if (value !== 3) failed = 1; - accum_a(3, value); - $display("%d", value); - if (value !== 4) failed = 1; + accum_a(3, value); + $display("%d", value); + if (value !== 4) failed = 1; - if (failed) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (failed) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mod_dup_bad.out b/test_regress/t/t_mod_dup_bad.out index c71620f5e..5bde02c2d 100644 --- a/test_regress/t/t_mod_dup_bad.out +++ b/test_regress/t/t_mod_dup_bad.out @@ -1,8 +1,8 @@ %Warning-MODDUP: t/t_mod_dup_bad.v:14:8: Duplicate declaration of module: 'a' - 14 | module a(); + 14 | module a (); | ^ t/t_mod_dup_bad.v:7:8: ... Location of original declaration - 7 | module a(); + 7 | module a (); | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. @@ -11,9 +11,9 @@ ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'test' - 10 | module test(); + 10 | module test (); | ^~~~ : ... Top module 'b' - 17 | module b(); + 17 | module b (); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_dup_bad.v b/test_regress/t/t_mod_dup_bad.v index 55a20802c..af7d3f918 100644 --- a/test_regress/t/t_mod_dup_bad.v +++ b/test_regress/t/t_mod_dup_bad.v @@ -4,15 +4,15 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module a(); +module a (); endmodule -module test(); - a a(); +module test (); + a a (); endmodule -module a(); +module a (); endmodule -module b(); +module b (); endmodule diff --git a/test_regress/t/t_mod_dup_bad_lib.out b/test_regress/t/t_mod_dup_bad_lib.out index cc0bdb504..2f059f099 100644 --- a/test_regress/t/t_mod_dup_bad_lib.out +++ b/test_regress/t/t_mod_dup_bad_lib.out @@ -1,8 +1,8 @@ %Warning-MODDUP: t/t_mod_dup_bad_lib.v:14:8: Duplicate declaration of module: 'a' - 14 | module a(); + 14 | module a (); | ^ t/t_mod_dup_bad_lib.v:7:8: ... Location of original declaration - 7 | module a(); + 7 | module a (); | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. @@ -11,9 +11,9 @@ ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'test' - 10 | module test(); + 10 | module test (); | ^~~~ : ... Top module 'b' - 17 | module b(); + 17 | module b (); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_dup_bad_lib.v b/test_regress/t/t_mod_dup_bad_lib.v index 55a20802c..af7d3f918 100644 --- a/test_regress/t/t_mod_dup_bad_lib.v +++ b/test_regress/t/t_mod_dup_bad_lib.v @@ -4,15 +4,15 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module a(); +module a (); endmodule -module test(); - a a(); +module test (); + a a (); endmodule -module a(); +module a (); endmodule -module b(); +module b (); endmodule diff --git a/test_regress/t/t_mod_dup_ign.v b/test_regress/t/t_mod_dup_ign.v index 7e08dee11..3f8375ce4 100644 --- a/test_regress/t/t_mod_dup_ign.v +++ b/test_regress/t/t_mod_dup_ign.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub sub (); + sub sub (); endmodule module sub; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule // verilator lint_off MODDUP module sub; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_mod_interface_array0.v b/test_regress/t/t_mod_interface_array0.v index 98c6459f0..33a3b2897 100644 --- a/test_regress/t/t_mod_interface_array0.v +++ b/test_regress/t/t_mod_interface_array0.v @@ -6,60 +6,65 @@ parameter N = 4; -interface a_if #(parameter PARAM = 0) (); - logic long_name; - modport source (output long_name); - modport sink (input long_name); +interface a_if #( + parameter PARAM = 0 +) (); + logic long_name; + modport source(output long_name); + modport sink(input long_name); endinterface -module intf_source - ( - input logic [N-1:0] intf_input, - a_if.source i_intf_source[N-1:0] - ); - generate - for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; - end - endgenerate +module intf_source ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] +); + generate + for (genvar i = 0; i < N; i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate endmodule -module intf_sink - ( - output [N-1:0] a_out, - a_if.sink i_intf_sink[N-1:0] - ); - generate - for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; - end - endgenerate +module intf_sink ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] +); + generate + for (genvar i = 0; i < N; i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate endmodule -module t - ( - clk - ); - input clk; - logic [N-1:0] a_in; - logic [N-1:0] a_out; - logic [N-1:0] ack_out; - a_if #(.PARAM(1)) tl_intf [N-1:0] (); - intf_source source(a_in, tl_intf); - intf_sink sink(a_out, tl_intf); +module t ( + clk +); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + a_if #(.PARAM(1)) tl_intf[N-1:0] (); + intf_source source ( + a_in, + tl_intf + ); + intf_sink sink ( + a_out, + tl_intf + ); - initial a_in = '0; - initial ack_out = '0; - always @(posedge clk) begin - a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; - ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; - if (ack_out != a_out) begin - $stop; - end + initial a_in = '0; + initial ack_out = '0; + always @(posedge clk) begin + a_in <= a_in + {{N - 1{1'b0}}, 1'b1}; + ack_out <= ack_out + {{N - 1{1'b0}}, 1'b1}; + if (ack_out != a_out) begin + $stop; + end - if (& a_in) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (&a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mod_interface_array1.v b/test_regress/t/t_mod_interface_array1.v index b07ff0e99..c35c7fcbb 100644 --- a/test_regress/t/t_mod_interface_array1.v +++ b/test_regress/t/t_mod_interface_array1.v @@ -6,62 +6,67 @@ parameter N = 4; -interface a_if #(parameter PARAM = 0) (); - logic long_name; - modport source (output long_name); - modport sink (input long_name); +interface a_if #( + parameter PARAM = 0 +) (); + logic long_name; + modport source(output long_name); + modport sink(input long_name); endinterface -module intf_source - ( - input logic [N-1:0] intf_input, - a_if.source i_intf_source[N-1:0] - ); - generate - for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; - end - endgenerate +module intf_source ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] +); + generate + for (genvar i = 0; i < N; i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate endmodule -module intf_sink - ( - output [N-1:0] a_out, - a_if.sink i_intf_sink[N-1:0] - ); - generate - for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; - end - endgenerate +module intf_sink ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] +); + generate + for (genvar i = 0; i < N; i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate endmodule -module t - ( - clk - ); - input clk; - logic [N-1:0] a_in; - logic [N-1:0] a_out; - logic [N-1:0] ack_out; - // verilator lint_off ASCRANGE - a_if #(.PARAM(1)) tl_intf [N] (); - // verilator lint_on ASCRANGE - intf_source source(a_in, tl_intf); - intf_sink sink(a_out, tl_intf); +module t ( + clk +); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + // verilator lint_off ASCRANGE + a_if #(.PARAM(1)) tl_intf[N] (); + // verilator lint_on ASCRANGE + intf_source source ( + a_in, + tl_intf + ); + intf_sink sink ( + a_out, + tl_intf + ); - initial a_in = '0; - initial ack_out = '0; - always @(posedge clk) begin - a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; - ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; - if (ack_out != a_out) begin - $stop; - end + initial a_in = '0; + initial ack_out = '0; + always @(posedge clk) begin + a_in <= a_in + {{N - 1{1'b0}}, 1'b1}; + ack_out <= ack_out + {{N - 1{1'b0}}, 1'b1}; + if (ack_out != a_out) begin + $stop; + end - if (& a_in) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (&a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mod_interface_array2.v b/test_regress/t/t_mod_interface_array2.v index 9d2e7af66..75f9b5fc0 100644 --- a/test_regress/t/t_mod_interface_array2.v +++ b/test_regress/t/t_mod_interface_array2.v @@ -7,60 +7,65 @@ parameter N = 4; // verilator lint_off ASCRANGE -interface a_if #(parameter PARAM = 0) (); - logic long_name; - modport source (output long_name); - modport sink (input long_name); +interface a_if #( + parameter PARAM = 0 +) (); + logic long_name; + modport source(output long_name); + modport sink(input long_name); endinterface -module intf_source - ( - input logic [0:N-1] intf_input, - a_if.source i_intf_source[0:N-1] - ); - generate - for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; - end - endgenerate +module intf_source ( + input logic [0:N-1] intf_input, + a_if.source i_intf_source[0:N-1] +); + generate + for (genvar i = 0; i < N; i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate endmodule -module intf_sink - ( - output [0:N-1] a_out, - a_if.sink i_intf_sink[0:N-1] - ); - generate - for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; - end - endgenerate +module intf_sink ( + output [0:N-1] a_out, + a_if.sink i_intf_sink[0:N-1] +); + generate + for (genvar i = 0; i < N; i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate endmodule -module t - ( - clk - ); - input clk; - logic [0:N-1] a_in; - logic [0:N-1] a_out; - logic [0:N-1] ack_out; - a_if #(.PARAM(1)) tl_intf [0:N-1] (); - intf_source source(a_in, tl_intf); - intf_sink sink(a_out, tl_intf); +module t ( + clk +); + input clk; + logic [0:N-1] a_in; + logic [0:N-1] a_out; + logic [0:N-1] ack_out; + a_if #(.PARAM(1)) tl_intf[0:N-1] (); + intf_source source ( + a_in, + tl_intf + ); + intf_sink sink ( + a_out, + tl_intf + ); - initial a_in = '0; - initial ack_out = '0; - always @(posedge clk) begin - a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; - ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; - if (ack_out != a_out) begin - $stop; - end + initial a_in = '0; + initial ack_out = '0; + always @(posedge clk) begin + a_in <= a_in + {{N - 1{1'b0}}, 1'b1}; + ack_out <= ack_out + {{N - 1{1'b0}}, 1'b1}; + if (ack_out != a_out) begin + $stop; + end - if (& a_in) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (&a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mod_interface_array3.out b/test_regress/t/t_mod_interface_array3.out index a2b8ecba7..f1246e764 100644 --- a/test_regress/t/t_mod_interface_array3.out +++ b/test_regress/t/t_mod_interface_array3.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_mod_interface_array3.v:22:20: Unsupported: Multidimensional instances/interfaces. - 22 | a_if iface [2:0][1:0] (); - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_mod_interface_array3.v:24:18: Unsupported: Multidimensional instances/interfaces. - 24 | sub i_sub[2:0][1:0] (.s(str)); +%Error-UNSUPPORTED: t/t_mod_interface_array3.v:26:18: Unsupported: Multidimensional instances/interfaces. + 26 | a_if iface[2:0][1:0] (); | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_mod_interface_array3.v:28:17: Unsupported: Multidimensional instances/interfaces. + 28 | sub i_sub[2:0][1:0] (.s(str)); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_interface_array3.v b/test_regress/t/t_mod_interface_array3.v index 8a4b536be..f6cffd138 100644 --- a/test_regress/t/t_mod_interface_array3.v +++ b/test_regress/t/t_mod_interface_array3.v @@ -4,39 +4,43 @@ // SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface a_if (); - string s; + string s; endinterface -module sub (output string s); - initial s = $sformatf("%m"); +module sub ( + output string s +); + initial s = $sformatf("%m"); endmodule module t; - string str [2:0][1:0]; + string str[2:0][1:0]; - a_if iface [2:0][1:0] (); + a_if iface[2:0][1:0] (); - sub i_sub[2:0][1:0] (.s(str)); + sub i_sub[2:0][1:0] (.s(str)); - initial begin - // TODO make self checking - $display(iface[0][0]); - $display(iface[0][1]); - $display(iface[1][0]); - $display(iface[1][1]); - $display(iface[2][0]); - $display(iface[2][1]); + initial begin + // TODO make self checking + $display(iface[0][0]); + $display(iface[0][1]); + $display(iface[1][0]); + $display(iface[1][1]); + $display(iface[2][0]); + $display(iface[2][1]); - $display(str[0][0]); - $display(str[0][1]); - $display(str[1][0]); - $display(str[1][1]); - $display(str[2][0]); - $display(str[2][1]); - end + $display(str[0][0]); + $display(str[0][1]); + $display(str[1][0]); + $display(str[1][1]); + $display(str[2][0]); + $display(str[2][1]); + end endmodule diff --git a/test_regress/t/t_mod_interface_array4.v b/test_regress/t/t_mod_interface_array4.v index 7ce5e0eda..321d9b4bf 100644 --- a/test_regress/t/t_mod_interface_array4.v +++ b/test_regress/t/t_mod_interface_array4.v @@ -4,75 +4,74 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on interface intf (); - integer index; + integer index; endinterface -module t - ( - clk - ); - input clk; +module t ( + clk +); + input clk; - intf ifa1_intf[2:1](); - intf ifa2_intf[2:1](); - intf ifb1_intf[1:2](); - intf ifb2_intf[1:2](); + intf ifa1_intf[2:1] (); + intf ifa2_intf[2:1] (); + intf ifb1_intf[1:2] (); + intf ifb2_intf[1:2] (); - int cyc; + int cyc; - sub sub - ( - .clk, - .cyc, - .alh(ifa1_intf), - .ahl(ifa2_intf), - .blh(ifb1_intf), - .bhl(ifb2_intf) - ); + sub sub ( + .clk, + .cyc, + .alh(ifa1_intf), + .ahl(ifa2_intf), + .blh(ifb1_intf), + .bhl(ifb2_intf) + ); - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - ifa1_intf[1].index = 'h101; - ifa1_intf[2].index = 'h102; - ifa2_intf[1].index = 'h201; - ifa2_intf[2].index = 'h202; - ifb1_intf[1].index = 'h301; - ifb1_intf[2].index = 'h302; - ifb2_intf[1].index = 'h401; - ifb2_intf[2].index = 'h402; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ifa1_intf[1].index = 'h101; + ifa1_intf[2].index = 'h102; + ifa2_intf[1].index = 'h201; + ifa2_intf[2].index = 'h202; + ifb1_intf[1].index = 'h301; + ifb1_intf[2].index = 'h302; + ifb2_intf[1].index = 'h401; + ifb2_intf[2].index = 'h402; + end + end endmodule -module sub - ( - input logic clk, - input int cyc, - intf alh[1:2], - intf ahl[2:1], - intf blh[1:2], - intf bhl[2:1] - ); +module sub ( + input logic clk, + input int cyc, + intf alh[1:2], + intf ahl[2:1], + intf blh[1:2], + intf bhl[2:1] +); - always @(posedge clk) begin - if (cyc == 5) begin - `checkh(alh[1].index, 'h102); - `checkh(alh[2].index, 'h101); - `checkh(ahl[1].index, 'h201); - `checkh(ahl[2].index, 'h202); - `checkh(blh[1].index, 'h301); - `checkh(blh[2].index, 'h302); - `checkh(bhl[1].index, 'h402); - `checkh(bhl[2].index, 'h401); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 5) begin + `checkh(alh[1].index, 'h102); + `checkh(alh[2].index, 'h101); + `checkh(ahl[1].index, 'h201); + `checkh(ahl[2].index, 'h202); + `checkh(blh[1].index, 'h301); + `checkh(blh[2].index, 'h302); + `checkh(bhl[1].index, 'h402); + `checkh(bhl[2].index, 'h401); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mod_interface_array5.v b/test_regress/t/t_mod_interface_array5.v index 29e0c44a0..6498ec784 100644 --- a/test_regress/t/t_mod_interface_array5.v +++ b/test_regress/t/t_mod_interface_array5.v @@ -4,109 +4,115 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on interface intf (); - integer value; + integer value; endinterface -module fanout - #(parameter int N = 1) - ( +module fanout #( + parameter int N = 1 +) ( intf upstream, intf downstream[N-1:0] - ); +); - genvar i; - for (i = 0; i < N; i = i + 1) - assign downstream[i].value = upstream.value; + genvar i; + for (i = 0; i < N; i = i + 1) assign downstream[i].value = upstream.value; endmodule -module xbar - ( - input logic clk, - input int cyc, - intf Masters[1:0] - ); +module xbar ( + input logic clk, + input int cyc, + intf Masters[1:0] +); - localparam NUM_DEMUX_OUT = 2 * 4; - localparam NUM_MUX_IN = 2 * 4; - intf demuxOut[NUM_DEMUX_OUT-1:0](); - intf muxIn[NUM_MUX_IN-1:0](); + localparam NUM_DEMUX_OUT = 2 * 4; + localparam NUM_MUX_IN = 2 * 4; + intf demuxOut[NUM_DEMUX_OUT-1:0] (); + intf muxIn[NUM_MUX_IN-1:0] (); - //fan out master connections to the crossbar matrix - fanout #(.N(4)) fanout_inst0 - (.upstream(Masters[0]), - .downstream(demuxOut[3:0])); + //fan out master connections to the crossbar matrix + fanout #( + .N(4) + ) fanout_inst0 ( + .upstream(Masters[0]), + .downstream(demuxOut[3:0]) + ); - fanout #(.N(4)) fanout_inst1 - (.upstream(Masters[1]), - .downstream(demuxOut[7:4])); + fanout #( + .N(4) + ) fanout_inst1 ( + .upstream(Masters[1]), + .downstream(demuxOut[7:4]) + ); - //the crossbar matrix assignments, done as 1D arrays because verilator doesn't currently support >1D arrays of interfaces - genvar slv, mst; - for (slv = 0; slv < 4; slv = slv + 1) begin - for (mst = 0; mst < 2; mst = mst + 1) begin - localparam int muxIdx = (slv*2)+mst; - localparam int demuxIdx = slv+(mst*4); - assign muxIn[muxIdx].value = demuxOut[demuxIdx].value; - end - end + //the crossbar matrix assignments, done as 1D arrays because verilator doesn't currently support >1D arrays of interfaces + genvar slv, mst; + for (slv = 0; slv < 4; slv = slv + 1) begin + for (mst = 0; mst < 2; mst = mst + 1) begin + localparam int muxIdx = (slv * 2) + mst; + localparam int demuxIdx = slv + (mst * 4); + assign muxIn[muxIdx].value = demuxOut[demuxIdx].value; + end + end - always @(posedge clk) begin - if (cyc == 5) begin - `checkh(Masters[0].value, 2); - `checkh(Masters[1].value, 1); - // The first 4 demuxOut values should have the value of the first Master - `checkh(demuxOut[0].value, Masters[0].value); - `checkh(demuxOut[1].value, Masters[0].value); - `checkh(demuxOut[2].value, Masters[0].value); - `checkh(demuxOut[3].value, Masters[0].value); - // The next 4 demuxOut values should have the value of the second Master - `checkh(demuxOut[4].value, Masters[1].value); - `checkh(demuxOut[5].value, Masters[1].value); - `checkh(demuxOut[6].value, Masters[1].value); - `checkh(demuxOut[7].value, Masters[1].value); - // Each 2 mux inputs should have one input from each master, in order from low to high - `checkh(muxIn[0].value, Masters[0].value); - `checkh(muxIn[1].value, Masters[1].value); - `checkh(muxIn[2].value, Masters[0].value); - `checkh(muxIn[3].value, Masters[1].value); - `checkh(muxIn[4].value, Masters[0].value); - `checkh(muxIn[5].value, Masters[1].value); - `checkh(muxIn[6].value, Masters[0].value); - `checkh(muxIn[7].value, Masters[1].value); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 5) begin + `checkh(Masters[0].value, 2); + `checkh(Masters[1].value, 1); + // The first 4 demuxOut values should have the value of the first Master + `checkh(demuxOut[0].value, Masters[0].value); + `checkh(demuxOut[1].value, Masters[0].value); + `checkh(demuxOut[2].value, Masters[0].value); + `checkh(demuxOut[3].value, Masters[0].value); + // The next 4 demuxOut values should have the value of the second Master + `checkh(demuxOut[4].value, Masters[1].value); + `checkh(demuxOut[5].value, Masters[1].value); + `checkh(demuxOut[6].value, Masters[1].value); + `checkh(demuxOut[7].value, Masters[1].value); + // Each 2 mux inputs should have one input from each master, in order from low to high + `checkh(muxIn[0].value, Masters[0].value); + `checkh(muxIn[1].value, Masters[1].value); + `checkh(muxIn[2].value, Masters[0].value); + `checkh(muxIn[3].value, Masters[1].value); + `checkh(muxIn[4].value, Masters[0].value); + `checkh(muxIn[5].value, Masters[1].value); + `checkh(muxIn[6].value, Masters[0].value); + `checkh(muxIn[7].value, Masters[1].value); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module t - ( - clk - ); - input clk; +module t ( + clk +); + input clk; - intf masters[1:0](); + intf masters[1:0] (); - int cyc; + int cyc; - xbar sub - (.clk, + xbar sub ( + .clk, .cyc, - .Masters(masters)); + .Masters(masters) + ); - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - masters[0].value <= 2; - masters[1].value <= 1; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + masters[0].value <= 2; + masters[1].value <= 1; + end + end endmodule diff --git a/test_regress/t/t_mod_interface_array6.v b/test_regress/t/t_mod_interface_array6.v index d0b412573..b54cf97ab 100644 --- a/test_regress/t/t_mod_interface_array6.v +++ b/test_regress/t/t_mod_interface_array6.v @@ -4,155 +4,151 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on interface intf (); - integer index; + integer index; endinterface -module t - ( - clk - ); - input clk; +module t ( + clk +); + input clk; - intf ifa1_intf[4:1](); - intf ifa2_intf[4:1](); - intf ifb1_intf[1:4](); - intf ifb2_intf[1:4](); + intf ifa1_intf[4:1] (); + intf ifa2_intf[4:1] (); + intf ifb1_intf[1:4] (); + intf ifb2_intf[1:4] (); - int cyc; + int cyc; - sub sub0 - ( - .n(0), - .clk, - .cyc, - .alh(ifa1_intf[2:1]), - .ahl(ifa2_intf[2:1]), - .blh(ifb1_intf[1:2]), - .bhl(ifb2_intf[1:2]) - ); + sub sub0 ( + .n(0), + .clk, + .cyc, + .alh(ifa1_intf[2:1]), + .ahl(ifa2_intf[2:1]), + .blh(ifb1_intf[1:2]), + .bhl(ifb2_intf[1:2]) + ); - sub sub1 - ( - .n(1), - .clk, - .cyc, - .alh(ifa1_intf[4:3]), - .ahl(ifa2_intf[4:3]), - .blh(ifb1_intf[3:4]), - .bhl(ifb2_intf[3:4]) - ); + sub sub1 ( + .n(1), + .clk, + .cyc, + .alh(ifa1_intf[4:3]), + .ahl(ifa2_intf[4:3]), + .blh(ifb1_intf[3:4]), + .bhl(ifb2_intf[3:4]) + ); -`ifndef verilator // Backwards slicing not supported - sub sub2 - ( - .n(2), - .clk, - .cyc, - .alh(ifa1_intf[1:2]), // backwards vs decl - .ahl(ifa2_intf[1:2]), // backwards vs decl - .blh(ifb1_intf[2:1]), // backwards vs decl - .bhl(ifb2_intf[2:1]) // backwards vs decl - ); +`ifndef verilator // Backwards slicing not supported + sub sub2 ( + .n(2), + .clk, + .cyc, + .alh(ifa1_intf[1:2]), // backwards vs decl + .ahl(ifa2_intf[1:2]), // backwards vs decl + .blh(ifb1_intf[2:1]), // backwards vs decl + .bhl(ifb2_intf[2:1]) // backwards vs decl + ); - sub sub3 - ( - .n(3), - .clk, - .cyc, - .alh(ifa1_intf[3:4]), // backwards vs decl - .ahl(ifa2_intf[3:4]), // backwards vs decl - .blh(ifb1_intf[4:3]), // backwards vs decl - .bhl(ifb2_intf[4:3]) // backwards vs decl - ); + sub sub3 ( + .n(3), + .clk, + .cyc, + .alh(ifa1_intf[3:4]), // backwards vs decl + .ahl(ifa2_intf[3:4]), // backwards vs decl + .blh(ifb1_intf[4:3]), // backwards vs decl + .bhl(ifb2_intf[4:3]) // backwards vs decl + ); `endif - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - ifa1_intf[1].index = 'h101; - ifa1_intf[2].index = 'h102; - ifa1_intf[3].index = 'h103; - ifa1_intf[4].index = 'h104; - ifa2_intf[1].index = 'h201; - ifa2_intf[2].index = 'h202; - ifa2_intf[3].index = 'h203; - ifa2_intf[4].index = 'h204; - ifb1_intf[1].index = 'h301; - ifb1_intf[2].index = 'h302; - ifb1_intf[3].index = 'h303; - ifb1_intf[4].index = 'h304; - ifb2_intf[1].index = 'h401; - ifb2_intf[2].index = 'h402; - ifb2_intf[3].index = 'h403; - ifb2_intf[4].index = 'h404; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ifa1_intf[1].index = 'h101; + ifa1_intf[2].index = 'h102; + ifa1_intf[3].index = 'h103; + ifa1_intf[4].index = 'h104; + ifa2_intf[1].index = 'h201; + ifa2_intf[2].index = 'h202; + ifa2_intf[3].index = 'h203; + ifa2_intf[4].index = 'h204; + ifb1_intf[1].index = 'h301; + ifb1_intf[2].index = 'h302; + ifb1_intf[3].index = 'h303; + ifb1_intf[4].index = 'h304; + ifb2_intf[1].index = 'h401; + ifb2_intf[2].index = 'h402; + ifb2_intf[3].index = 'h403; + ifb2_intf[4].index = 'h404; + end + end endmodule -module sub - ( - input logic clk, - input int cyc, - input int n, - intf alh[1:2], - intf ahl[2:1], - intf blh[1:2], - intf bhl[2:1] - ); +module sub ( + input logic clk, + input int cyc, + input int n, + intf alh[1:2], + intf ahl[2:1], + intf blh[1:2], + intf bhl[2:1] +); - always @(posedge clk) begin + always @(posedge clk) begin - if (cyc == 5) begin - if (n == 0) begin - `checkh(alh[1].index, 'h102); - `checkh(alh[2].index, 'h101); - `checkh(ahl[1].index, 'h201); - `checkh(ahl[2].index, 'h202); - `checkh(blh[1].index, 'h301); - `checkh(blh[2].index, 'h302); - `checkh(bhl[1].index, 'h402); - `checkh(bhl[2].index, 'h401); - end - else if (n == 1) begin - `checkh(alh[1].index, 'h104); - `checkh(alh[2].index, 'h103); - `checkh(ahl[1].index, 'h203); - `checkh(ahl[2].index, 'h204); - `checkh(blh[1].index, 'h303); - `checkh(blh[2].index, 'h304); - `checkh(bhl[1].index, 'h404); - `checkh(bhl[2].index, 'h403); - end - else if (n == 2) begin - `checkh(alh[1].index, 'h101); - `checkh(alh[2].index, 'h102); - `checkh(ahl[1].index, 'h202); - `checkh(ahl[2].index, 'h201); - `checkh(blh[1].index, 'h302); - `checkh(blh[2].index, 'h301); - `checkh(bhl[1].index, 'h401); - `checkh(bhl[2].index, 'h402); - end - else if (n == 3) begin - `checkh(alh[1].index, 'h103); - `checkh(alh[2].index, 'h104); - `checkh(ahl[1].index, 'h204); - `checkh(ahl[2].index, 'h203); - `checkh(blh[1].index, 'h304); - `checkh(blh[2].index, 'h303); - `checkh(bhl[1].index, 'h403); - `checkh(bhl[2].index, 'h404); - end + if (cyc == 5) begin + if (n == 0) begin + `checkh(alh[1].index, 'h102); + `checkh(alh[2].index, 'h101); + `checkh(ahl[1].index, 'h201); + `checkh(ahl[2].index, 'h202); + `checkh(blh[1].index, 'h301); + `checkh(blh[2].index, 'h302); + `checkh(bhl[1].index, 'h402); + `checkh(bhl[2].index, 'h401); end - if (cyc == 9 && n == 0) begin - $write("*-* All Finished *-*\n"); - $finish; + else if (n == 1) begin + `checkh(alh[1].index, 'h104); + `checkh(alh[2].index, 'h103); + `checkh(ahl[1].index, 'h203); + `checkh(ahl[2].index, 'h204); + `checkh(blh[1].index, 'h303); + `checkh(blh[2].index, 'h304); + `checkh(bhl[1].index, 'h404); + `checkh(bhl[2].index, 'h403); end - end + else if (n == 2) begin + `checkh(alh[1].index, 'h101); + `checkh(alh[2].index, 'h102); + `checkh(ahl[1].index, 'h202); + `checkh(ahl[2].index, 'h201); + `checkh(blh[1].index, 'h302); + `checkh(blh[2].index, 'h301); + `checkh(bhl[1].index, 'h401); + `checkh(bhl[2].index, 'h402); + end + else if (n == 3) begin + `checkh(alh[1].index, 'h103); + `checkh(alh[2].index, 'h104); + `checkh(ahl[1].index, 'h204); + `checkh(ahl[2].index, 'h203); + `checkh(blh[1].index, 'h304); + `checkh(blh[2].index, 'h303); + `checkh(bhl[1].index, 'h403); + `checkh(bhl[2].index, 'h404); + end + end + if (cyc == 9 && n == 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_mod_longname.v b/test_regress/t/t_mod_longname.v index 7d6d0d0da..eb7c35b99 100644 --- a/test_regress/t/t_mod_longname.v +++ b/test_regress/t/t_mod_longname.v @@ -12,20 +12,20 @@ module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end - logic `LONG_NAME_VAR; + logic `LONG_NAME_VAR; - `LONG_NAME_MOD - `LONG_NAME_SUB - (); + `LONG_NAME_MOD + `LONG_NAME_SUB + (); endmodule module `LONG_NAME_MOD (); - // Force Verilator to make a new class - logic a1 /* verilator public */; + // Force Verilator to make a new class + logic a1 /* verilator public */; endmodule diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v index 0e7b8d9ba..ca72c29de 100644 --- a/test_regress/t/t_mod_recurse.v +++ b/test_regress/t/t_mod_recurse.v @@ -4,108 +4,121 @@ // SPDX-FileCopyrightText: 2013 Sean Moore // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] tripline = crc[7:0]; + // Take CRC data and apply to testblock inputs + wire [7:0] tripline = crc[7:0]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - wire valid; - wire [3-1:0] value; + wire valid; + wire [3-1:0] value; - PriorityChoice #(.OCODEWIDTH(3)) - pe (.out(valid), .outN(value[2:0]), .tripline(tripline)); + PriorityChoice #( + .OCODEWIDTH(3) + ) pe ( + .out(valid), + .outN(value[2:0]), + .tripline(tripline) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, valid, value}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, valid, value}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hc5fc632f816568fb - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hc5fc632f816568fb + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module PriorityChoice (out, outN, tripline); - parameter OCODEWIDTH = 1; - localparam CODEWIDTH=OCODEWIDTH-1; - localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH; +module PriorityChoice ( + out, + outN, + tripline +); + parameter OCODEWIDTH = 1; + localparam CODEWIDTH = OCODEWIDTH - 1; + localparam SCODEWIDTH = (CODEWIDTH < 1) ? 1 : CODEWIDTH; - output reg out; - output reg [OCODEWIDTH-1:0] outN; - input wire [(1< 1) begin - for (int i=0; i 1) begin + for (int i = 0; i < SIZE; i++) `checkh(array1[i], cyc - 1 + i); + end + #1; + for (int i = 0; i < SIZE; i++) `checkh(array1[i], cyc + i); + end - // Case 2: Array NBA to array also assigned in suspendable - int array2 [SIZE]; - always @ (posedge clk) begin - for (int i=0; i 0) cyc <= cyc + 1; - if (cyc == 15) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if ($time > 0) cyc <= cyc + 1; + if (cyc == 15) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge clk) #1 begin + always @(posedge clk) + #1 begin `ifdef TEST_VERBOSE - $display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d", - $time, cyc, val1, val2, val3, val4, val5, val6); + $display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d", $time, cyc, + val1, val2, val3, val4, val5, val6); `endif if (cyc >= 3) begin - `checkh(val1, cyc - 1); - `checkh(val2, cyc - 2); - `checkh(val3, 0); - `checkh(val4, 0); - `checkh(val5, cyc); - `checkh(val6, cyc - 1); - end + `checkh(val1, cyc - 1); + `checkh(val2, cyc - 2); + `checkh(val3, 0); + `checkh(val4, 0); + `checkh(val5, cyc); + `checkh(val6, cyc - 1); + end end endmodule diff --git a/test_regress/t/t_nettype.out b/test_regress/t/t_nettype.out index f7581cc3f..30b0bcb7b 100644 --- a/test_regress/t/t_nettype.out +++ b/test_regress/t/t_nettype.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_nettype.v:25:4: Unsupported: nettype with - 25 | nettype real real1_n with Pkg::resolver; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_nettype.v:25:3: Unsupported: nettype with + 25 | nettype real real1_n with Pkg::resolver; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_nettype.v:29:4: Unsupported: nettype with - 29 | nettype real real2_n with local_resolver; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_nettype.v:34:4: Unsupported: nettype - 34 | nettype real2_n real3_n; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_nettype.v:38:4: Unsupported: nettype with - 38 | nettype Pkg::real_t real4_n with Pkg::resolver; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_nettype.v:29:3: Unsupported: nettype with + 29 | nettype real real2_n with local_resolver; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_nettype.v:34:3: Unsupported: nettype + 34 | nettype real2_n real3_n; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_nettype.v:38:3: Unsupported: nettype with + 38 | nettype Pkg::real_t real4_n with Pkg::resolver; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_nettype.v b/test_regress/t/t_nettype.v index 9dd3ce0b4..deb879b2f 100644 --- a/test_regress/t/t_nettype.v +++ b/test_regress/t/t_nettype.v @@ -5,51 +5,51 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef real real_t; - real last_resolve; + typedef real real_t; + real last_resolve; - function automatic real resolver(input real drivers[]); - resolver = 0.0; - foreach (drivers[i]) resolver += drivers[i]; - last_resolve = resolver; - endfunction + function automatic real resolver(input real drivers[]); + resolver = 0.0; + foreach (drivers[i]) resolver += drivers[i]; + last_resolve = resolver; + endfunction endpackage module t; - function automatic real local_resolver(input real drivers[]); - local_resolver = 0.0; - foreach (drivers[i]) local_resolver += drivers[i]; - endfunction + function automatic real local_resolver(input real drivers[]); + local_resolver = 0.0; + foreach (drivers[i]) local_resolver += drivers[i]; + endfunction - nettype real real1_n with Pkg::resolver; - real1_n real1; - assign real1 = 1.23; + nettype real real1_n with Pkg::resolver; + real1_n real1; + assign real1 = 1.23; - nettype real real2_n with local_resolver; - real2_n real2; - assign real2 = 1.23; + nettype real real2_n with local_resolver; + real2_n real2; + assign real2 = 1.23; - // Create alias using new name - nettype real2_n real3_n; - real3_n real3; - assign real3 = 1.23; + // Create alias using new name + nettype real2_n real3_n; + real3_n real3; + assign real3 = 1.23; - nettype Pkg::real_t real4_n with Pkg::resolver; - real4_n real4; - assign real4 = 1.23; + nettype Pkg::real_t real4_n with Pkg::resolver; + real4_n real4; + assign real4 = 1.23; - // TODO when implement net types need to check multiple driver cases, across - // submodules + // TODO when implement net types need to check multiple driver cases, across + // submodules - initial begin - #10; - if (real1 != 1.23) $stop; - if (real2 != 1.23) $stop; - if (real3 != 1.23) $stop; - if (Pkg::last_resolve != 1.23) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + if (real1 != 1.23) $stop; + if (real2 != 1.23) $stop; + if (real3 != 1.23) $stop; + if (Pkg::last_resolve != 1.23) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.v b/test_regress/t/t_no_sel_assign_merge_in_cpp.v index cd729985d..126fca776 100644 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.v +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t_no_sel_assign_merge_in_cpp ( - input wire [(8*39)-1:0] d_i, - output wire [(8*32)-1:0] d_o + input wire [(8*39)-1:0] d_i, + output wire [(8*32)-1:0] d_o ); for (genvar i = 0; i < 8; i = i + 1) begin - assign d_o[i*32 +: 32] = d_i[i*39 +: 32]; + assign d_o[i*32+:32] = d_i[i*39+:32]; end endmodule diff --git a/test_regress/t/t_no_std_bad.out b/test_regress/t/t_no_std_bad.out index 987f67523..5a7271393 100644 --- a/test_regress/t/t_no_std_bad.out +++ b/test_regress/t/t_no_std_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_no_std_bad.v:9:11: Import package not found: 'std' - 9 | import std::*; - | ^~~ +%Error: t/t_no_std_bad.v:9:10: Import package not found: 'std' + 9 | import std::*; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_no_std_bad.v b/test_regress/t/t_no_std_bad.v index 7e5457019..ad594f1ce 100644 --- a/test_regress/t/t_no_std_bad.v +++ b/test_regress/t/t_no_std_bad.v @@ -6,5 +6,5 @@ // verilator lint_off DECLFILENAME module t; - import std::*; + import std::*; endmodule diff --git a/test_regress/t/t_notiming.out b/test_regress/t/t_notiming.out index 26ff81c86..ce479d6fd 100644 --- a/test_regress/t/t_notiming.out +++ b/test_regress/t/t_notiming.out @@ -1,50 +1,50 @@ -%Warning-STMTDLY: t/t_notiming.v:12:8: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_notiming.v:12:6: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 12 | #1 - | ^ + 12 | #1 + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Error-NOTIMING: t/t_notiming.v:13:8: Fork statements require --timing +%Error-NOTIMING: t/t_notiming.v:13:6: Fork statements require --timing : ... note: In instance 't' - 13 | fork @e; @e; join; - | ^~~~ + 13 | fork @e; @e; join; + | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Error-NOTIMING: t/t_notiming.v:14:8: Event control statement in this location requires --timing +%Error-NOTIMING: t/t_notiming.v:14:6: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 14 | @e - | ^ -%Error-NOTIMING: t/t_notiming.v:15:8: Wait statements require --timing + 14 | @e + | ^ +%Error-NOTIMING: t/t_notiming.v:15:6: Wait statements require --timing : ... note: In instance 't' - 15 | wait(x == 4) + 15 | wait(x == 4) + | ^~~~ +%Error-NOTIMING: t/t_notiming.v:19:6: Event control statement in this location requires --timing + : ... note: In instance 't' + : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure + 19 | @e + | ^ +%Warning-STMTDLY: t/t_notiming.v:26:11: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 26 | initial #1 ->e; + | ^ +%Warning-STMTDLY: t/t_notiming.v:27:11: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 27 | initial #2 $stop; + | ^ +%Error-NOTIMING: t/t_notiming.v:33:8: mailbox::put() requires --timing + : ... note: In instance 't' + 33 | m.put(i); + | ^~~ +%Error-NOTIMING: t/t_notiming.v:34:8: mailbox::get() requires --timing + : ... note: In instance 't' + 34 | m.get(i); + | ^~~ +%Error-NOTIMING: t/t_notiming.v:35:8: mailbox::peek() requires --timing + : ... note: In instance 't' + 35 | m.peek(i); | ^~~~ -%Error-NOTIMING: t/t_notiming.v:19:8: Event control statement in this location requires --timing +%Error-NOTIMING: t/t_notiming.v:36:8: semaphore::get() requires --timing : ... note: In instance 't' - : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 19 | @e - | ^ -%Warning-STMTDLY: t/t_notiming.v:26:12: Ignoring delay on this statement due to --no-timing - : ... note: In instance 't' - 26 | initial #1 ->e; - | ^ -%Warning-STMTDLY: t/t_notiming.v:27:12: Ignoring delay on this statement due to --no-timing - : ... note: In instance 't' - 27 | initial #2 $stop; - | ^ -%Error-NOTIMING: t/t_notiming.v:33:10: mailbox::put() requires --timing - : ... note: In instance 't' - 33 | m.put(i); - | ^~~ -%Error-NOTIMING: t/t_notiming.v:34:10: mailbox::get() requires --timing - : ... note: In instance 't' - 34 | m.get(i); - | ^~~ -%Error-NOTIMING: t/t_notiming.v:35:10: mailbox::peek() requires --timing - : ... note: In instance 't' - 35 | m.peek(i); - | ^~~~ -%Error-NOTIMING: t/t_notiming.v:36:10: semaphore::get() requires --timing - : ... note: In instance 't' - 36 | s.get(); - | ^~~ + 36 | s.get(); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_notiming.v b/test_regress/t/t_notiming.v index 5777f8c66..5e9e2591f 100644 --- a/test_regress/t/t_notiming.v +++ b/test_regress/t/t_notiming.v @@ -5,36 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event e; + event e; - initial begin - int x; - #1 - fork @e; @e; join; - @e - wait(x == 4) - x = #1 8; - if (x != 8) $stop; - if ($time != 0) $stop; - @e - if (!e.triggered) $stop; - if ($time != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int x; + #1 + fork @e; @e; join; + @e + wait(x == 4) + x = #1 8; + if (x != 8) $stop; + if ($time != 0) $stop; + @e + if (!e.triggered) $stop; + if ($time != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - initial #1 ->e; - initial #2 $stop; // timeout + initial #1 ->e; + initial #2 $stop; // timeout - mailbox#(int) m = new; - semaphore s = new; - initial begin - int i; - m.put(i); - m.get(i); - m.peek(i); - s.get(); - end + mailbox#(int) m = new; + semaphore s = new; + initial begin + int i; + m.put(i); + m.get(i); + m.peek(i); + s.get(); + end endmodule `ifdef VERILATOR_TIMING diff --git a/test_regress/t/t_notiming_off.out b/test_regress/t/t_notiming_off.out index 18d1084ab..62fba9f7c 100644 --- a/test_regress/t/t_notiming_off.out +++ b/test_regress/t/t_notiming_off.out @@ -1,30 +1,30 @@ -%Error-NOTIMING: t/t_timing_off.v:25:8: Event control statement in this location requires --timing +%Error-NOTIMING: t/t_timing_off.v:27:5: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 25 | @e1; - | ^ + 27 | @e1; + | ^ ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Warning-STMTDLY: t/t_timing_off.v:33:12: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_timing_off.v:34:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 33 | initial #2 ->e1; - | ^ + 34 | initial #2->e1; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Warning-STMTDLY: t/t_timing_off.v:37:12: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_timing_off.v:38:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 37 | initial #3 $stop; - | ^ -%Warning-STMTDLY: t/t_timing_off.v:38:12: Ignoring delay on this statement due to --no-timing + 38 | initial #3 $stop; + | ^ +%Warning-STMTDLY: t/t_timing_off.v:39:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ -%Error-NOTIMING: t/t_timing_off.v:38:15: Event control statement in this location requires --timing + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ +%Error-NOTIMING: t/t_timing_off.v:39:14: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ -%Warning-STMTDLY: t/t_timing_off.v:38:25: Ignoring delay on this statement due to --no-timing + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ +%Warning-STMTDLY: t/t_timing_off.v:39:24: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_opt_assemble_cellarray.v b/test_regress/t/t_opt_assemble_cellarray.v index 45dd03a99..a4884e2c2 100644 --- a/test_regress/t/t_opt_assemble_cellarray.v +++ b/test_regress/t/t_opt_assemble_cellarray.v @@ -10,90 +10,106 @@ `define REP_COUNT2 `DATA_WIDTH/2 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg [3:0] count4 = 0; - reg [1:0] count2 = 0; +module t ( + input clk +); - reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; - reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; - reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; - reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; - reg [`DATA_WIDTH-1:0] res1; - reg [`DATA_WIDTH-1:0] res2; - reg [`DATA_WIDTH-1:0] res3; - reg [`DATA_WIDTH-1:0] res4; + reg [3:0] count4 = 0; + reg [1:0] count2 = 0; - drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1)); - drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2)); - drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3)); - drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4)); + reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; + reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] res1; + reg [`DATA_WIDTH-1:0] res2; + reg [`DATA_WIDTH-1:0] res3; + reg [`DATA_WIDTH-1:0] res4; - always@(posedge clk) - begin - count2 <= count2 + 1; - count4 <= count4 + 1; - a <= {`REP_COUNT4{count4}}; - b <= {`REP_COUNT4{count4}}; - c <= {`REP_COUNT2{count2}}; - d <= {`REP_COUNT2{count2}}; + drv1 t_drv1[`DATA_WIDTH-1:0] ( + .colSelA(a), + .datao(res1) + ); + drv2 t_drv2[`DATA_WIDTH-1:0] ( + .colSelA(a), + .colSelB(b), + .datao(res2) + ); + drv3 t_drv3[`DATA_WIDTH-1:0] ( + .colSelA(a), + .colSelB(b), + .colSelC(c), + .datao(res3) + ); + drv4 t_drv4[`DATA_WIDTH-1:0] ( + .colSelA(a), + .colSelB(b), + .colSelC(c), + .colSelD(d), + .datao(res4) + ); - if (res1 != (a)) begin - $stop; - end - if (res2 != (a&b)) begin - $stop; - end - if (res3 != (a&b&c)) begin - $stop; - end - if (res4 != (a&b&c&d)) begin - $stop; - end + always @(posedge clk) begin + count2 <= count2 + 1; + count4 <= count4 + 1; + a <= {`REP_COUNT4{count4}}; + b <= {`REP_COUNT4{count4}}; + c <= {`REP_COUNT2{count2}}; + d <= {`REP_COUNT2{count2}}; - if (count4 > 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (res1 != (a)) begin + $stop; + end + if (res2 != (a & b)) begin + $stop; + end + if (res3 != (a & b & c)) begin + $stop; + end + if (res4 != (a & b & c & d)) begin + $stop; + end + + if (count4 > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module drv1 - (input colSelA, - output datao - ); - assign datao = colSelA; +module drv1 ( + input colSelA, + output datao +); + assign datao = colSelA; endmodule -module drv2 - (input colSelA, - input colSelB, - output datao - ); - assign datao = colSelB & colSelA; +module drv2 ( + input colSelA, + input colSelB, + output datao +); + assign datao = colSelB & colSelA; endmodule -module drv3 - (input colSelA, - input colSelB, - input colSelC, - output datao - ); - assign datao = colSelB & colSelA & colSelC; +module drv3 ( + input colSelA, + input colSelB, + input colSelC, + output datao +); + assign datao = colSelB & colSelA & colSelC; endmodule -module drv4 - (input colSelA, - input colSelB, - input colSelC, - input colSelD, - output datao - ); - assign datao = colSelB & colSelA & colSelC & colSelD; +module drv4 ( + input colSelA, + input colSelB, + input colSelC, + input colSelD, + output datao +); + assign datao = colSelB & colSelA & colSelC & colSelD; endmodule diff --git a/test_regress/t/t_opt_const.v b/test_regress/t/t_opt_const.v index b2eae6d59..171ccde2d 100644 --- a/test_regress/t/t_opt_const.v +++ b/test_regress/t/t_opt_const.v @@ -10,176 +10,176 @@ import "DPI-C" context function int c_fake_dependency(); module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic o; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic o; // From test of Test.v + // End of automatics - wire [31:0] i = crc[31:0]; + wire [31:0] i = crc[31:0]; - Test test(/*AUTOINST*/ - // Outputs - .o (o), - // Inputs - .clk (clk), - .i (i[31:0])); + Test test(/*AUTOINST*/ + // Outputs + .o (o), + // Inputs + .clk (clk), + .i (i[31:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'b0, o}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'b0, o}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); - $display("o %b", o); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $display("o %b", o); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 99) begin - end - else begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 99) begin + end + else begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4c5aa8d19cd13750 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - o, - // Inputs - clk, i - ); + // Outputs + o, + // Inputs + clk, i + ); - input clk; - input [31:0] i; - logic [31:0] d; - logic d0, d1, d2, d3, d4, d5, d6, d7; - logic bug3182_out; - logic bug3197_out; - logic bug3445_out; - logic bug3470_out; - logic bug3509_out; - wire bug3399_out0; - wire bug3399_out1; - logic bug3786_out; - logic bug3824_out; - logic bug4059_out; - logic bug4832_out; - logic bug4837_out; - logic bug4857_out; - logic bug4864_out; - logic bug5186_out; + input clk; + input [31:0] i; + logic [31:0] d; + logic d0, d1, d2, d3, d4, d5, d6, d7; + logic bug3182_out; + logic bug3197_out; + logic bug3445_out; + logic bug3470_out; + logic bug3509_out; + wire bug3399_out0; + wire bug3399_out1; + logic bug3786_out; + logic bug3824_out; + logic bug4059_out; + logic bug4832_out; + logic bug4837_out; + logic bug4857_out; + logic bug4864_out; + logic bug5186_out; - output logic o; + output logic o; - logic [19:0] tmp; - assign o = ^tmp; + logic [19:0] tmp; + assign o = ^tmp; - always_ff @(posedge clk) begin - d <= i; - d0 <= i[0]; - d1 <= i[1]; - d2 <= i[2]; - d3 <= i[3]; - d4 <= i[4]; - d5 <= i[5]; - d6 <= i[6]; - d7 <= i[7]; - end - always_ff @(posedge clk) begin - // Cover more lines in V3Const.cpp - tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot() - tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift - tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr() - tmp[3] <= d0 <-> d1; // replaceLogEq() - tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes - tmp[5] <= bug3182_out; - tmp[6] <= bug3197_out; - tmp[7] <= bug3445_out; - tmp[8] <= bug3470_out; - tmp[9] <= bug3509_out; - tmp[10]<= bug3399_out0; - tmp[11]<= bug3399_out1; - tmp[12]<= bug3786_out; - tmp[13]<= bug3824_out; - tmp[14]<= bug4059_out; - tmp[15]<= bug4832_out; - tmp[16]<= bug4837_out; - tmp[17]<= bug4857_out; - tmp[18]<= bug4864_out; - tmp[19]<= bug5186_out; - end + always_ff @(posedge clk) begin + d <= i; + d0 <= i[0]; + d1 <= i[1]; + d2 <= i[2]; + d3 <= i[3]; + d4 <= i[4]; + d5 <= i[5]; + d6 <= i[6]; + d7 <= i[7]; + end + always_ff @(posedge clk) begin + // Cover more lines in V3Const.cpp + tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot() + tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift + tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr() + tmp[3] <= d0 <-> d1; // replaceLogEq() + tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes + tmp[5] <= bug3182_out; + tmp[6] <= bug3197_out; + tmp[7] <= bug3445_out; + tmp[8] <= bug3470_out; + tmp[9] <= bug3509_out; + tmp[10]<= bug3399_out0; + tmp[11]<= bug3399_out1; + tmp[12]<= bug3786_out; + tmp[13]<= bug3824_out; + tmp[14]<= bug4059_out; + tmp[15]<= bug4832_out; + tmp[16]<= bug4837_out; + tmp[17]<= bug4857_out; + tmp[18]<= bug4864_out; + tmp[19]<= bug5186_out; + end - bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out)); - bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out)); - bug3445 i_bug3445(.clk(clk), .in(d), .out(bug3445_out)); - bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out)); - bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out)); - bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1)); - bug3786 i_bug3786(.clk(clk), .in(d), .out(bug3786_out)); - bug3824 i_bug3824(.clk(clk), .in(d), .out(bug3824_out)); - bug4059 i_bug4059(.clk(clk), .in(d), .out(bug4059_out)); - bug4832 i_bug4832(.clk(clk), .in(d), .out(bug4832_out)); - bug4837 i_bug4837(.clk(clk), .in(d), .out(bug4837_out)); - bug4857 i_bug4857(.clk(clk), .in(d), .out(bug4857_out)); - bug4864 i_bug4864(.clk(clk), .in(d), .out(bug4864_out)); - bug5186 i_bug5186(.clk(clk), .in(d), .out(bug5186_out)); - bug5993 i_bug5993(.clk(clk), .in(d[10])); - bug6016 i_bug6016(.clk(clk), .in(d[10])); + bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out)); + bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out)); + bug3445 i_bug3445(.clk(clk), .in(d), .out(bug3445_out)); + bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out)); + bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out)); + bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1)); + bug3786 i_bug3786(.clk(clk), .in(d), .out(bug3786_out)); + bug3824 i_bug3824(.clk(clk), .in(d), .out(bug3824_out)); + bug4059 i_bug4059(.clk(clk), .in(d), .out(bug4059_out)); + bug4832 i_bug4832(.clk(clk), .in(d), .out(bug4832_out)); + bug4837 i_bug4837(.clk(clk), .in(d), .out(bug4837_out)); + bug4857 i_bug4857(.clk(clk), .in(d), .out(bug4857_out)); + bug4864 i_bug4864(.clk(clk), .in(d), .out(bug4864_out)); + bug5186 i_bug5186(.clk(clk), .in(d), .out(bug5186_out)); + bug5993 i_bug5993(.clk(clk), .in(d[10])); + bug6016 i_bug6016(.clk(clk), .in(d[10])); endmodule module bug3182(in, out); - input wire [4:0] in; - output wire out; + input wire [4:0] in; + output wire out; - logic [4:0] bit_source; + logic [4:0] bit_source; - /* verilator lint_off WIDTH */ - always @(in) - bit_source = c_fake_dependency() | in; + /* verilator lint_off WIDTH */ + always @(in) + bit_source = c_fake_dependency() | in; - wire [5:0] tmp = bit_source; // V3Gate should inline this - assign out = ~(tmp >> 5) & (bit_source == 5'd10); - /* verilator lint_on WIDTH */ + wire [5:0] tmp = bit_source; // V3Gate should inline this + assign out = ~(tmp >> 5) & (bit_source == 5'd10); + /* verilator lint_on WIDTH */ endmodule module bug3197(input wire clk, input wire [31:0] in, output out); - logic [63:0] d; - always_ff @(posedge clk) - d <= {d[31:0], in[0] ? in : 32'b0}; + logic [63:0] d; + always_ff @(posedge clk) + d <= {d[31:0], in[0] ? in : 32'b0}; - wire tmp0 = (|d[38:0]); - assign out = (d[39] | tmp0); + wire tmp0 = (|d[38:0]); + assign out = (d[39] | tmp0); endmodule @@ -197,48 +197,48 @@ endmodule // 3. Insert AstNot if polarity of the frozen node is false (resutl3 in the // test) module bug3445(input wire clk, input wire [31:0] in, output wire out); - logic [127:0] d; - always_ff @(posedge clk) - d <= {d[95:0], in}; + logic [127:0] d; + always_ff @(posedge clk) + d <= {d[95:0], in}; - typedef struct packed { - logic a; - logic [ 2:0] b; - logic [ 2:0] c; - logic [ 1:0] d; - logic [ 7:0] e; - logic [31:0] f; - logic [ 3:0] g; - logic [31:0] h; - logic i; - logic [41:0] j; - } packed_struct; - packed_struct st[4]; + typedef struct packed { + logic a; + logic [ 2:0] b; + logic [ 2:0] c; + logic [ 1:0] d; + logic [ 7:0] e; + logic [31:0] f; + logic [ 3:0] g; + logic [31:0] h; + logic i; + logic [41:0] j; + } packed_struct; + packed_struct st[4]; - // This is always 1'b0, but Verilator cannot notice it. - // This signal helps to reveal wrong optimization of result2 and result3. - logic zero; - always_ff @(posedge clk) begin - st[0] <= d; - st[1] <= st[0]; - st[2] <= st[1]; - st[3] <= st[2]; - zero <= c_fake_dependency() > 0; - end + // This is always 1'b0, but Verilator cannot notice it. + // This signal helps to reveal wrong optimization of result2 and result3. + logic zero; + always_ff @(posedge clk) begin + st[0] <= d; + st[1] <= st[0]; + st[2] <= st[1]; + st[3] <= st[2]; + zero <= c_fake_dependency() > 0; + end - logic result0, result1, result2, result3; - always_ff @(posedge clk) begin - // Cannot optimize further. - result0 <= (st[0].g[0] & st[0].h[0]) & (in[0] == 1'b0); - // There are redundant !in[0] terms. They should be simplified. - result1 <= (!in[0] & (st[1].g[0] & st[1].h[0])) & ((in[0] == 1'b0) & !in[0]); - // Cannot optimize further. - result2 <= !(st[2].g[0] & st[2].h[0]) & (zero == 1'b0); - // There are redundant zero terms. They should be simplified. - result3 <= (!zero & !(st[3].g[0] & st[3].h[0])) & ((zero == 1'b0) & !zero); - end + logic result0, result1, result2, result3; + always_ff @(posedge clk) begin + // Cannot optimize further. + result0 <= (st[0].g[0] & st[0].h[0]) & (in[0] == 1'b0); + // There are redundant !in[0] terms. They should be simplified. + result1 <= (!in[0] & (st[1].g[0] & st[1].h[0])) & ((in[0] == 1'b0) & !in[0]); + // Cannot optimize further. + result2 <= !(st[2].g[0] & st[2].h[0]) & (zero == 1'b0); + // There are redundant zero terms. They should be simplified. + result3 <= (!zero & !(st[3].g[0] & st[3].h[0])) & ((zero == 1'b0) & !zero); + end - assign out = result0 ^ result1 ^ (result2 | result3); + assign out = result0 ^ result1 ^ (result2 | result3); endmodule // Bug3470 @@ -254,24 +254,24 @@ endmodule // -> ^d[31:0] // Of course the correct result is ^d[38:0] = ^d module bug3470(input wire clk, input wire [31:0] in, output wire out); - logic [38:0] d; - initial d = 0; - initial tmp = 0; - initial expected = 0; + logic [38:0] d; + initial d = 0; + initial tmp = 0; + initial expected = 0; - always_ff @(posedge clk) - d <= {d[6:0], in}; + always_ff @(posedge clk) + d <= {d[6:0], in}; - logic tmp, expected; - always_ff @(posedge clk) begin - tmp <= ^(d >> 32) ^ (^d[31:0]); - expected <= ^d; - end + logic tmp, expected; + always_ff @(posedge clk) begin + tmp <= ^(d >> 32) ^ (^d[31:0]); + expected <= ^d; + end - always @(posedge clk) - if (tmp != expected) $stop; + always @(posedge clk) + if (tmp != expected) $stop; - assign out = tmp; + assign out = tmp; endmodule // Bug3509 @@ -286,43 +286,43 @@ endmodule // If "comp" has '1' in upper bit range than "var", // the result is constant after optimization. module bug3509(input wire clk, input wire [31:0] in, output reg out); - reg [2:0] r0; - always_ff @(posedge clk) - r0 <= in[2:0]; + reg [2:0] r0; + always_ff @(posedge clk) + r0 <= in[2:0]; - wire [3:0] w1_0 = {1'b0, in[2:0]}; - wire [3:0] w1_1 = {1'b0, r0}; + wire [3:0] w1_0 = {1'b0, in[2:0]}; + wire [3:0] w1_1 = {1'b0, r0}; - wire tmp[4]; + wire tmp[4]; - // tmp[0:1] is always 0 because w1[3] == 1'b0 - // tmp[2:3] is always 1 because w1[3] == 1'b0 - assign tmp[0] = w1_0[3:2] == 2'h2 && w1_0[1:0] != 2'd3; - assign tmp[1] = w1_1[3:2] == 2'h2 && w1_1[1:0] != 2'd3; - assign tmp[2] = w1_0[3:2] != 2'h2 || w1_0[1:0] == 2'd3; - assign tmp[3] = w1_1[3:2] != 2'h2 || w1_1[1:0] == 2'd3; - always_ff @(posedge clk) begin - out <= tmp[0] | tmp[1] | !tmp[2] | !tmp[3]; - end + // tmp[0:1] is always 0 because w1[3] == 1'b0 + // tmp[2:3] is always 1 because w1[3] == 1'b0 + assign tmp[0] = w1_0[3:2] == 2'h2 && w1_0[1:0] != 2'd3; + assign tmp[1] = w1_1[3:2] == 2'h2 && w1_1[1:0] != 2'd3; + assign tmp[2] = w1_0[3:2] != 2'h2 || w1_0[1:0] == 2'd3; + assign tmp[3] = w1_1[3:2] != 2'h2 || w1_1[1:0] == 2'd3; + always_ff @(posedge clk) begin + out <= tmp[0] | tmp[1] | !tmp[2] | !tmp[3]; + end - always @(posedge clk) begin - if(tmp[0]) begin - $display("tmp[0] != 0"); - $stop; - end - if(tmp[1]) begin - $display("tmp[1] != 0"); - $stop; - end - if(!tmp[2]) begin - $display("tmp[2] != 1"); - $stop; - end - if(!tmp[3]) begin - $display("tmp[3] != 1"); - $stop; - end - end + always @(posedge clk) begin + if(tmp[0]) begin + $display("tmp[0] != 0"); + $stop; + end + if(tmp[1]) begin + $display("tmp[1] != 0"); + $stop; + end + if(!tmp[2]) begin + $display("tmp[2] != 1"); + $stop; + end + if(!tmp[3]) begin + $display("tmp[3] != 1"); + $stop; + end + end endmodule // Bug3399 @@ -335,56 +335,56 @@ endmodule // optimized the tree even though the graph needs more width. // Remember that the target of bit op tree optimization is 1 bit width. module bug3399(input wire clk, input wire [31:0] in, inout wire out0, inout wire out1); - logic [1:0] driver = '0; - logic [1:0] d; - always_ff @(posedge clk) begin - driver <= 2'b11; - d <= in[1:0]; - end + logic [1:0] driver = '0; + logic [1:0] d; + always_ff @(posedge clk) begin + driver <= 2'b11; + d <= in[1:0]; + end - assign out0 = driver[0] ? d[0] : 1'bz; - assign out1 = driver[1] ? d[1] : 1'bz; + assign out0 = driver[0] ? d[0] : 1'bz; + assign out1 = driver[1] ? d[1] : 1'bz; endmodule // Bug3786 // When V3Expand is skipped, wide number is not split by WORDSEL. // Bit op tree opt. expects that bit width is 64 bit at most. module bug3786(input wire clk, input wire [31:0] in, inout wire out); - logic [127:0] d0, d1; - always_ff @(posedge clk) begin - d0 <= {d0[127:32], in}; - d1 <= d1; - end + logic [127:0] d0, d1; + always_ff @(posedge clk) begin + d0 <= {d0[127:32], in}; + d1 <= d1; + end - assign out = ^{d1, d0}; + assign out = ^{d1, d0}; endmodule // Bug3824 // When a variable is shift-out, the term becomes 0. // Such behavior was not considered in Or-tree. module bug3824(input wire clk, input wire [31:0] in, output wire out); - logic [5:0] a; - always_ff @(posedge clk) a <= in[5:0]; - logic [6:0] b; - assign b = {1'b0, a}; + logic [5:0] a; + always_ff @(posedge clk) a <= in[5:0]; + logic [6:0] b; + assign b = {1'b0, a}; - logic c_and; - assign c_and = (b[6]); // c_and is always 1'b0 - always_comb if (c_and != 1'b0) $stop; - logic d_and; - always_ff @(posedge clk) d_and <= (&a) & c_and; + logic c_and; + assign c_and = (b[6]); // c_and is always 1'b0 + always_comb if (c_and != 1'b0) $stop; + logic d_and; + always_ff @(posedge clk) d_and <= (&a) & c_and; - logic c_or; - assign c_or = ~(b[6]); // c_or is always 1'b1 as b[6] is 1'b0 - always_comb if (c_or != 1'b1) $stop; - logic d_or; - always_ff @(posedge clk) d_or <= (|a) | c_or; + logic c_or; + assign c_or = ~(b[6]); // c_or is always 1'b1 as b[6] is 1'b0 + always_comb if (c_or != 1'b1) $stop; + logic d_or; + always_ff @(posedge clk) d_or <= (|a) | c_or; - logic c_xor; - assign c_xor = ^(b[6]); // c_xor is always 1'b0 - always_comb if (c_xor != 1'b0) $stop; - logic d_xor; - always_ff @(posedge clk) d_xor <= (^a) ^ c_xor; + logic c_xor; + assign c_xor = ^(b[6]); // c_xor is always 1'b0 + always_comb if (c_xor != 1'b0) $stop; + logic d_xor; + always_ff @(posedge clk) d_xor <= (^a) ^ c_xor; assign out = d_and ^ d_or ^ d_xor; endmodule @@ -394,27 +394,27 @@ endmodule // In an XOR tree, the entire result is flipped if necessary according to // total polarity. This bug was introduced when fixing issue #3445. module bug4059(input wire clk, input wire [31:0] in, output wire out); - wire [127:0] words_i; - for (genvar i = 0; i < $bits(in); ++i) begin - always_ff @(posedge clk) - words_i[4 * i +: 4] <= {4{in[i]}}; - end + wire [127:0] words_i; + for (genvar i = 0; i < $bits(in); ++i) begin + always_ff @(posedge clk) + words_i[4 * i +: 4] <= {4{in[i]}}; + end - wire _000_ = ~(words_i[104] ^ words_i[96]); - wire _001_ = ~(words_i[88] ^ words_i[80]); - wire _002_ = ~(_000_ ^ _001_); - wire _003_ = words_i[72] ^ words_i[64]; - wire _004_ = words_i[120] ^ words_i[112]; - wire _005_ = ~(_003_ ^ _004_); - wire _006_ = ~(_002_ ^ _005_); - wire _007_ = words_i[40] ^ words_i[32]; - wire _008_ = ~(words_i[24] ^ words_i[16]); - wire _009_ = ~(_007_ ^ _008_); - wire _010_ = words_i[8] ^ words_i[0]; - wire _011_ = words_i[56] ^ words_i[48]; - wire _012_ = ~(_010_ ^ _011_); - wire _013_ = ~(_009_ ^ _012_); - assign out = ~(_006_ ^ _013_); + wire _000_ = ~(words_i[104] ^ words_i[96]); + wire _001_ = ~(words_i[88] ^ words_i[80]); + wire _002_ = ~(_000_ ^ _001_); + wire _003_ = words_i[72] ^ words_i[64]; + wire _004_ = words_i[120] ^ words_i[112]; + wire _005_ = ~(_003_ ^ _004_); + wire _006_ = ~(_002_ ^ _005_); + wire _007_ = words_i[40] ^ words_i[32]; + wire _008_ = ~(words_i[24] ^ words_i[16]); + wire _009_ = ~(_007_ ^ _008_); + wire _010_ = words_i[8] ^ words_i[0]; + wire _011_ = words_i[56] ^ words_i[48]; + wire _012_ = ~(_010_ ^ _011_); + wire _013_ = ~(_009_ ^ _012_); + assign out = ~(_006_ ^ _013_); endmodule /// See issue #4832 @@ -424,21 +424,21 @@ endmodule // A subtree under NOT should be untouched, but was not. // Testing OR subtree too. module bug4832(input wire clk, input wire [31:0] in, output out); - logic [95:0] d; - always_ff @(posedge clk) - d <= {d[63:0], in}; + logic [95:0] d; + always_ff @(posedge clk) + d <= {d[63:0], in}; - logic [31:0] tmp_and; - logic [31:0] tmp_or; - logic result_and; - logic result_or; - assign tmp_and = (d[63:32] & in) >> 3; - assign tmp_or = (d[63:32] | in) >> 8; - always_ff @(posedge clk) begin - result_and <= !tmp_and[0] & d[32 + 22]; - result_or <= !tmp_or[0] | d[32 + 21]; - end - assign out = result_and ^ result_or; + logic [31:0] tmp_and; + logic [31:0] tmp_or; + logic result_and; + logic result_or; + assign tmp_and = (d[63:32] & in) >> 3; + assign tmp_or = (d[63:32] | in) >> 8; + always_ff @(posedge clk) begin + result_and <= !tmp_and[0] & d[32 + 22]; + result_or <= !tmp_or[0] | d[32 + 21]; + end + assign out = result_and ^ result_or; endmodule /// See issue #4837 and $4841 @@ -450,20 +450,20 @@ endmodule // e.g. SHIFTL(AND(a, b), 1) => AND(SHIFTL(a, 1), SHIFTL(b, 1)) // AND in the result must have 1 bit larger widthMin than the original AND module bug4837(input wire clk, input wire [31:0] in, output out); - logic [95:0] d; - always_ff @(posedge clk) - d <= {d[63:0], in}; + logic [95:0] d; + always_ff @(posedge clk) + d <= {d[63:0], in}; - wire celloutsig_0z; - wire [1:0] celloutsig_1z; - wire celloutsig_2z; - wire [95:0] out_data; - assign celloutsig_0z = d[83] < d[74]; - assign celloutsig_1z = { d[54], celloutsig_0z } & { d[42], celloutsig_0z }; - assign celloutsig_2z = d[65:64] < d[83:82]; - assign { out_data[33:32], out_data[0] } = { celloutsig_1z, celloutsig_2z }; + wire celloutsig_0z; + wire [1:0] celloutsig_1z; + wire celloutsig_2z; + wire [95:0] out_data; + assign celloutsig_0z = d[83] < d[74]; + assign celloutsig_1z = { d[54], celloutsig_0z } & { d[42], celloutsig_0z }; + assign celloutsig_2z = d[65:64] < d[83:82]; + assign { out_data[33:32], out_data[0] } = { celloutsig_1z, celloutsig_2z }; - assign out = out_data[33] ^ out_data[32] ^ out_data[0]; + assign out = out_data[33] ^ out_data[32] ^ out_data[0]; endmodule // See issue #4857 @@ -471,35 +471,35 @@ endmodule // (a | b) & 1'b1 // polarity was not considered when traversing NEQ under AND/OR tree module bug4857(input wire clk, input wire [31:0] in, output out); - logic [95:0] d; - always_ff @(posedge clk) - d <= {d[63:0], in}; + logic [95:0] d; + always_ff @(posedge clk) + d <= {d[63:0], in}; - wire celloutsig_12z; - wire celloutsig_15z; - wire celloutsig_17z; - wire celloutsig_4z; - wire celloutsig_67z; - wire celloutsig_9z; - logic [95:0] in_data; - logic result; + wire celloutsig_12z; + wire celloutsig_15z; + wire celloutsig_17z; + wire celloutsig_4z; + wire celloutsig_67z; + wire celloutsig_9z; + logic [95:0] in_data; + logic result; - // verilator lint_off UNDRIVEN - wire [95:0] out_data; - // verilator lint_on UNDRIVEN + // verilator lint_off UNDRIVEN + wire [95:0] out_data; + // verilator lint_on UNDRIVEN - assign celloutsig_4z = ~(in_data[72] & in_data[43]); // 1 - assign celloutsig_67z = | { in_data[64], celloutsig_12z }; // 0 - assign celloutsig_15z = in_data[43] & ~(celloutsig_4z); // 0 - assign celloutsig_9z = celloutsig_17z & ~(in_data[43]); // 00000000 - assign celloutsig_17z = celloutsig_15z & ~(in_data[43]);// 0 - assign celloutsig_12z = celloutsig_4z != celloutsig_9z; // 1 - assign out_data[32] = celloutsig_67z; // 1 + assign celloutsig_4z = ~(in_data[72] & in_data[43]); // 1 + assign celloutsig_67z = | { in_data[64], celloutsig_12z }; // 0 + assign celloutsig_15z = in_data[43] & ~(celloutsig_4z); // 0 + assign celloutsig_9z = celloutsig_17z & ~(in_data[43]); // 00000000 + assign celloutsig_17z = celloutsig_15z & ~(in_data[43]);// 0 + assign celloutsig_12z = celloutsig_4z != celloutsig_9z; // 1 + assign out_data[32] = celloutsig_67z; // 1 - assign in_data = d; - always_ff @ (posedge clk) - result <= out_data[32]; - assign out = result; + assign in_data = d; + always_ff @ (posedge clk) + result <= out_data[32]; + assign out = result; endmodule @@ -510,47 +510,47 @@ endmodule // The result of EQ/NE is just 1 bit width, so EQ/NE under SHFITR cannot be treated as a multi-bit term // such as AND/OR. module bug4864(input wire clk, input wire [31:0] in, output wire out); - logic [159:0] clkin_data = '0; - logic [95:0] in_data = '0; - int cycle = 0; - always @(posedge clk) begin - if (in[0]) begin - cycle <= cycle + 1; - if (cycle == 0) begin - clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_00000000; - end else if (cycle == 1) begin - in_data <= 96'h00000000_FFFFFFFF_00000000; - end else begin - clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_FFFFFFFF; - end + logic [159:0] clkin_data = '0; + logic [95:0] in_data = '0; + int cycle = 0; + always @(posedge clk) begin + if (in[0]) begin + cycle <= cycle + 1; + if (cycle == 0) begin + clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_00000000; + end else if (cycle == 1) begin + in_data <= 96'h00000000_FFFFFFFF_00000000; + end else begin + clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_FFFFFFFF; end - end + end + end - wire moveme; - wire sig_a; - reg [8:0] sig_b; - wire sig_c; - wire [20:0] sig_d; - reg sig_e; + wire moveme; + wire sig_a; + reg [8:0] sig_b; + wire sig_c; + wire [20:0] sig_d; + reg sig_e; - logic myfirst, mysecond; - assign myfirst = 1'b0; - assign mysecond = 1'b0; + logic myfirst, mysecond; + assign myfirst = 1'b0; + assign mysecond = 1'b0; - always_ff @(posedge clkin_data[0], posedge myfirst, posedge mysecond) - if (myfirst) sig_e <= 1'b0; - else if (mysecond) sig_e <= 1'b1; - else if (clkin_data[128]) sig_e <= sig_d[7]; + always_ff @(posedge clkin_data[0], posedge myfirst, posedge mysecond) + if (myfirst) sig_e <= 1'b0; + else if (mysecond) sig_e <= 1'b1; + else if (clkin_data[128]) sig_e <= sig_d[7]; - always_ff @(posedge clkin_data[128]) - sig_b <= '0; + always_ff @(posedge clkin_data[128]) + sig_b <= '0; - assign sig_a = in_data[89]; // 1'b0; - assign sig_c = | { in_data[61:60], sig_b, sig_a }; - assign sig_d = ~ { moveme, 6'b0, sig_b, 1'b0, sig_c, 3'b0 }; - assign moveme = 1'b1; + assign sig_a = in_data[89]; // 1'b0; + assign sig_c = | { in_data[61:60], sig_b, sig_a }; + assign sig_d = ~ { moveme, 6'b0, sig_b, 1'b0, sig_c, 3'b0 }; + assign moveme = 1'b1; - assign out = sig_e; + assign out = sig_e; endmodule @@ -560,17 +560,17 @@ endmodule // matchMaskedShift() thinks the cleaning AND is redundant because the mask // value is 32 bit width. module bug5186(input wire clk, input wire [31:0] in, output out); - logic [63:0] d; - always_ff @(posedge clk) - d <= {d[31:0], in}; + logic [63:0] d; + always_ff @(posedge clk) + d <= {d[31:0], in}; - wire bad; - assign bad = {d[38:32], d[38] ^ d[31] ^ d[38]} != d[38:31]; + wire bad; + assign bad = {d[38:32], d[38] ^ d[31] ^ d[38]} != d[38:31]; - logic result; - always_ff @ (posedge clk) - result <= bad; - assign out = result; + logic result; + always_ff @ (posedge clk) + result <= bad; + assign out = result; endmodule @@ -579,51 +579,51 @@ endmodule // BitOpTree ignored implicit "& 1". It caused the bug" module bug5993(input wire clk, input wire in); - reg in3; - reg [23:16] in4; + reg in3; + reg [23:16] in4; - task automatic checkd(logic gotv, logic expv); - if ((gotv) !== (expv)) begin - $write("%%Error: got=%0d exp=%0d\n", gotv, expv); - $stop; - end - endtask + task automatic checkd(logic gotv, logic expv); + if ((gotv) !== (expv)) begin + $write("%%Error: got=%0d exp=%0d\n", gotv, expv); + $stop; + end + endtask - // verilator lint_off WIDTH - wire wire_2 = in3 ? {4{14'b010111101}} : (in4[18] >> 8'b1); - // verilator lint_on WIDTH + // verilator lint_off WIDTH + wire wire_2 = in3 ? {4{14'b010111101}} : (in4[18] >> 8'b1); + // verilator lint_on WIDTH - always @(posedge clk) begin - in3 <= '0; - in4 <= in ? 8'b00111__0__10 : 8'b00111__1__10; - checkd(wire_2, 1'b0); - end - endmodule + always @(posedge clk) begin + in3 <= '0; + in4 <= in ? 8'b00111__0__10 : 8'b00111__1__10; + checkd(wire_2, 1'b0); + end + endmodule // See issue #6016 // When traversing a tree, a signal may be shifted out. // Then the polarity has to be cleared, but was not. // "(!in[18]) > 1" should be 0, but was not. module bug6016(input wire clk, input wire in); - reg in0; - reg signed [7:0] in4; - wire [1:0] wire_0; - wire out20; + reg in0; + reg signed [7:0] in4; + wire [1:0] wire_0; + wire out20; - // verilator lint_off WIDTH - assign wire_0 = in4[0:0] ? ({{7{in4[3:1]}}, 12'd201} & 2'h2) : (!(in0) >> 9'b1111); - // verilator lint_on WIDTH - assign out20 = wire_0[0:0]; + // verilator lint_off WIDTH + assign wire_0 = in4[0:0] ? ({{7{in4[3:1]}}, 12'd201} & 2'h2) : (!(in0) >> 9'b1111); + // verilator lint_on WIDTH + assign out20 = wire_0[0:0]; - logic in_s1 = 1'b0; - always @(posedge clk) begin - in_s1 <= in; - if (in) begin - in4 <= 8'b1111_1110; - in0 <= 1'b0; - end - if (in_s1) begin - if (out20 != 1'b0) $stop; - end - end + logic in_s1 = 1'b0; + always @(posedge clk) begin + in_s1 <= in; + if (in) begin + in4 <= 8'b1111_1110; + in0 <= 1'b0; + end + if (in_s1) begin + if (out20 != 1'b0) $stop; + end + end endmodule diff --git a/test_regress/t/t_opt_const_cov.v b/test_regress/t/t_opt_const_cov.v index 5d2793197..499db873e 100644 --- a/test_regress/t/t_opt_const_cov.v +++ b/test_regress/t/t_opt_const_cov.v @@ -4,76 +4,74 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [32:0] in = crc[32:0]; + // Take CRC data and apply to testblock inputs + wire [32:0] in = crc[32:0]; - logic bank_rd_vec_m3; - always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33]; + logic bank_rd_vec_m3; + always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33]; - logic [3:0][31:0] data_i; - wire [3:0] out; - for (genvar i = 0; i < 4; ++i) begin - always_ff @(posedge clk) data_i[i] <= crc[63:32]; - ecc_check_pipe u_bank_data_ecc_check( - .clk (clk), - .bank_rd_m3 (bank_rd_vec_m3), - .data_i ({1'b0, data_i[i]}), - .ecc_err_o (out[i]) - ); - end + logic [3:0][31:0] data_i; + wire [3:0] out; + for (genvar i = 0; i < 4; ++i) begin + always_ff @(posedge clk) data_i[i] <= crc[63:32]; + ecc_check_pipe u_bank_data_ecc_check ( + .clk(clk), + .bank_rd_m3(bank_rd_vec_m3), + .data_i({1'b0, data_i[i]}), + .ecc_err_o(out[i]) + ); + end - // Aggregate outputs into a single result vector - wire [63:0] result = {60'b0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'b0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'ha2601675a6ae4972 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'ha2601675a6ae4972 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module ecc_check_pipe ( - input logic clk, - input logic bank_rd_m3, - input logic [32:0] data_i, - output logic ecc_err_o - ); - logic [3:0] check_group_6_0; - logic check_group_6_0_q; +module ecc_check_pipe ( + input logic clk, + input logic bank_rd_m3, + input logic [32:0] data_i, + output logic ecc_err_o +); + logic [3:0] check_group_6_0; + logic check_group_6_0_q; - always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] }; - always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0; - assign ecc_err_o = check_group_6_0_q; + always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7]}; + always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <= ^check_group_6_0; + assign ecc_err_o = check_group_6_0_q; endmodule diff --git a/test_regress/t/t_opt_const_or.v b/test_regress/t/t_opt_const_or.v index 2cd09ec64..6aa173a9b 100644 --- a/test_regress/t/t_opt_const_or.v +++ b/test_regress/t/t_opt_const_or.v @@ -4,108 +4,112 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] rd0; // From test of Test.v - wire [31:0] rd1; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] rd0; // From test of Test.v + wire [31:0] rd1; // From test of Test.v + // End of automatics - wire rden0 = crc[0]; - wire rden1 = crc[1]; - wire [4:0] raddr0 = crc[20:16]; - wire [4:0] raddr1 = crc[28:24]; + wire rden0 = crc[0]; + wire rden1 = crc[1]; + wire [4:0] raddr0 = crc[20:16]; + wire [4:0] raddr1 = crc[28:24]; - Test test(/*AUTOINST*/ - // Outputs - .rd0 (rd0[31:0]), - .rd1 (rd1[31:0]), - // Inputs - .clk (clk), - .raddr0 (raddr0[4:0]), - .raddr1 (raddr1[4:0]), - .rden0 (rden0), - .rden1 (rden1)); + Test test ( /*AUTOINST*/ + // Outputs + .rd0(rd0[31:0]), + .rd1(rd1[31:0]), + // Inputs + .clk(clk), + .raddr0(raddr0[4:0]), + .raddr1(raddr1[4:0]), + .rden0(rden0), + .rden1(rden1) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {rd1, rd0}; + // Aggregate outputs into a single result vector + wire [63:0] result = {rd1, rd0}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hdc97b141ac5d6d7d - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hdc97b141ac5d6d7d + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(/*AUTOARG*/ - // Outputs - rd0, rd1, - // Inputs - clk, raddr0, raddr1, rden0, rden1 - ); +module Test ( /*AUTOARG*/ + // Outputs + rd0, + rd1, + // Inputs + clk, + raddr0, + raddr1, + rden0, + rden1 +); - input clk; - input [4:0] raddr0; - input [4:0] raddr1; - input rden0; - input rden1; + input clk; + input [4:0] raddr0; + input [4:0] raddr1; + input rden0; + input rden1; - output reg [31:0] rd0; - output reg [31:0] rd1; + output reg [31:0] rd0; + output reg [31:0] rd1; - reg [31:0] gpr [31:1]; + reg [31:0] gpr[31:1]; - initial begin - for (int j=1; j<32; j++ ) begin - gpr[j] = {8'(j), 8'(j), 8'(j), 8'(j)}; - end - end + initial begin + for (int j = 1; j < 32; j++) begin + gpr[j] = {8'(j), 8'(j), 8'(j), 8'(j)}; + end + end - always_comb begin - rd0[31:0] = 32'b0; - rd1[31:0] = 32'b0; - // Future optimization: - // Multiple assignments to same variable with OR between them - // ASSIGN(a, OR(a, aq)), ASSIGN(a, OR(a, bq)) -> ASSIGN(a, OR(a, OR(aq, bq)) - // Skip if we're not const'ing an entire module (IE doing only one assign, etc) - for (int j=1; j<32; j++ ) begin - rd0[31:0] |= ({32{rden0 & (raddr0[4:0]== 5'(j))}} & gpr[j][31:0]); - rd1[31:0] |= ({32{rden1 & (raddr1[4:0]== 5'(j))}} & gpr[j][31:0]); - end - end + always_comb begin + rd0[31:0] = 32'b0; + rd1[31:0] = 32'b0; + // Future optimization: + // Multiple assignments to same variable with OR between them + // ASSIGN(a, OR(a, aq)), ASSIGN(a, OR(a, bq)) -> ASSIGN(a, OR(a, OR(aq, bq)) + // Skip if we're not const'ing an entire module (IE doing only one assign, etc) + for (int j = 1; j < 32; j++) begin + rd0[31:0] |= ({32{rden0 & (raddr0[4:0] == 5'(j))}} & gpr[j][31:0]); + rd1[31:0] |= ({32{rden1 & (raddr1[4:0] == 5'(j))}} & gpr[j][31:0]); + end + end endmodule diff --git a/test_regress/t/t_opt_const_red.v b/test_regress/t/t_opt_const_red.v index 589f3b351..ff700354f 100644 --- a/test_regress/t/t_opt_const_red.v +++ b/test_regress/t/t_opt_const_red.v @@ -5,303 +5,303 @@ // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic a1; // From test of Test.v - logic a10; // From test of Test.v - logic a11; // From test of Test.v - logic a2; // From test of Test.v - logic a3; // From test of Test.v - logic a4; // From test of Test.v - logic a5; // From test of Test.v - logic a6; // From test of Test.v - logic a7; // From test of Test.v - logic a8; // From test of Test.v - logic a9; // From test of Test.v - logic o1; // From test of Test.v - logic o10; // From test of Test.v - logic o11; // From test of Test.v - logic o2; // From test of Test.v - logic o3; // From test of Test.v - logic o4; // From test of Test.v - logic o5; // From test of Test.v - logic o6; // From test of Test.v - logic o7; // From test of Test.v - logic o8; // From test of Test.v - logic o9; // From test of Test.v - logic x1; // From test of Test.v - logic x2; // From test of Test.v - logic x3; // From test of Test.v - logic x4; // From test of Test.v - logic x5; // From test of Test.v - logic x6; // From test of Test.v - logic x7; // From test of Test.v - logic x8; // From test of Test.v - logic x9; // From test of Test.v - logic z1; // From test of Test.v - logic z2; // From test of Test.v - logic z3; // From test of Test.v - logic z4; // From test of Test.v - logic z5; // From test of Test.v - logic z6; // From test of Test.v - logic z7; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic a1; // From test of Test.v + logic a10; // From test of Test.v + logic a11; // From test of Test.v + logic a2; // From test of Test.v + logic a3; // From test of Test.v + logic a4; // From test of Test.v + logic a5; // From test of Test.v + logic a6; // From test of Test.v + logic a7; // From test of Test.v + logic a8; // From test of Test.v + logic a9; // From test of Test.v + logic o1; // From test of Test.v + logic o10; // From test of Test.v + logic o11; // From test of Test.v + logic o2; // From test of Test.v + logic o3; // From test of Test.v + logic o4; // From test of Test.v + logic o5; // From test of Test.v + logic o6; // From test of Test.v + logic o7; // From test of Test.v + logic o8; // From test of Test.v + logic o9; // From test of Test.v + logic x1; // From test of Test.v + logic x2; // From test of Test.v + logic x3; // From test of Test.v + logic x4; // From test of Test.v + logic x5; // From test of Test.v + logic x6; // From test of Test.v + logic x7; // From test of Test.v + logic x8; // From test of Test.v + logic x9; // From test of Test.v + logic z1; // From test of Test.v + logic z2; // From test of Test.v + logic z3; // From test of Test.v + logic z4; // From test of Test.v + logic z5; // From test of Test.v + logic z6; // From test of Test.v + logic z7; // From test of Test.v + // End of automatics - wire [15:0] vec_i = crc[15:0]; - wire [31:0] i = crc[31:0]; - logic b8_i; - logic b12_i; - logic match1_o; - logic match2_o; + wire [15:0] vec_i = crc[15:0]; + wire [31:0] i = crc[31:0]; + logic b8_i; + logic b12_i; + logic match1_o; + logic match2_o; - Test test(/*AUTOINST*/ - // Outputs - .a1 (a1), - .a2 (a2), - .a3 (a3), - .a4 (a4), - .a5 (a5), - .a6 (a6), - .a7 (a7), - .a8 (a8), - .a9 (a9), - .a10 (a10), - .a11 (a11), - .o1 (o1), - .o2 (o2), - .o3 (o3), - .o4 (o4), - .o5 (o5), - .o6 (o6), - .o7 (o7), - .o8 (o8), - .o9 (o9), - .o10 (o10), - .o11 (o11), - .x1 (x1), - .x2 (x2), - .x3 (x3), - .x4 (x4), - .x5 (x5), - .x6 (x6), - .x7 (x7), - .x8 (x8), - .x9 (x9), - .z1 (z1), - .z2 (z2), - .z3 (z3), - .z4 (z4), - .z5 (z5), - .z6 (z6), - .z7 (z7), - // Inputs - .clk (clk), - .i (i[31:0])); + Test test(/*AUTOINST*/ + // Outputs + .a1 (a1), + .a2 (a2), + .a3 (a3), + .a4 (a4), + .a5 (a5), + .a6 (a6), + .a7 (a7), + .a8 (a8), + .a9 (a9), + .a10 (a10), + .a11 (a11), + .o1 (o1), + .o2 (o2), + .o3 (o3), + .o4 (o4), + .o5 (o5), + .o6 (o6), + .o7 (o7), + .o8 (o8), + .o9 (o9), + .o10 (o10), + .o11 (o11), + .x1 (x1), + .x2 (x2), + .x3 (x3), + .x4 (x4), + .x5 (x5), + .x6 (x6), + .x7 (x7), + .x8 (x8), + .x9 (x9), + .z1 (z1), + .z2 (z2), + .z3 (z3), + .z4 (z4), + .z5 (z5), + .z6 (z6), + .z7 (z7), + // Inputs + .clk (clk), + .i (i[31:0])); - match i_match( - .vec_i ( i[15:0] ), - .b8_i ( b8_i ), - .b12_i ( b12_i ), - .match1_o ( match1_o ), - .match2_o ( match2_o ) - ); + match i_match( + .vec_i ( i[15:0] ), + .b8_i ( b8_i ), + .b12_i ( b12_i ), + .match1_o ( match1_o ), + .match2_o ( match2_o ) + ); - // Aggregate outputs into a single result vector - // verilator lint_off WIDTH - wire [63:0] result = {a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11, - o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11, - x1,x2,x3,x4,x5,x6,x7,x8,x9}; - // verilator lint_on WIDTH + // Aggregate outputs into a single result vector + // verilator lint_off WIDTH + wire [63:0] result = {a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11, + o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11, + x1,x2,x3,x4,x5,x6,x7,x8,x9}; + // verilator lint_on WIDTH - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); - $display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11); - $display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11); - $display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11); + $display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11); + $display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - b8_i <= 1'b0; - b12_i <= 1'b0; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + b8_i <= 1'b0; + b12_i <= 1'b0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 99) begin + if (a1 != a2) $stop; + if (a1 != a3) $stop; + if (a1 != a4) $stop; + if (a1 != a5) $stop; + if (a6 != a7) $stop; + if (a8 != a9) $stop; + if (o1 != o2) $stop; + if (o1 != o3) $stop; + if (o1 != o4) $stop; + if (o1 != o5) $stop; + if (o6 != o7) $stop; + if (o8 != o9) $stop; + if (x1 != x2) $stop; + if (x1 != x3) $stop; + if (x1 != x4) $stop; + if (x1 != x5) $stop; + if (x1 != x6) $stop; + if (x1 != x7) $stop; + if (z1 != '0) $stop; + if (z2 != '1) $stop; + if (z3 != '0) $stop; + if (z4 != '0) $stop; + if (z5 != '1) $stop; + if (z6 != '1) $stop; + if (z7 != '0) $stop; + if (match1_o != match2_o) begin + $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o); + $stop; end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 99) begin - if (a1 != a2) $stop; - if (a1 != a3) $stop; - if (a1 != a4) $stop; - if (a1 != a5) $stop; - if (a6 != a7) $stop; - if (a8 != a9) $stop; - if (o1 != o2) $stop; - if (o1 != o3) $stop; - if (o1 != o4) $stop; - if (o1 != o5) $stop; - if (o6 != o7) $stop; - if (o8 != o9) $stop; - if (x1 != x2) $stop; - if (x1 != x3) $stop; - if (x1 != x4) $stop; - if (x1 != x5) $stop; - if (x1 != x6) $stop; - if (x1 != x7) $stop; - if (z1 != '0) $stop; - if (z2 != '1) $stop; - if (z3 != '0) $stop; - if (z4 != '0) $stop; - if (z5 != '1) $stop; - if (z6 != '1) $stop; - if (z7 != '0) $stop; - if (match1_o != match2_o) begin - $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o); - $stop; - end - end - else begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + end + else begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h727fb78d09c1981e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, o1, o2, o3, o4, o5, - o6, o7, o8, o9, o10, o11, x1, x2, x3, x4, x5, x6, x7, x8, x9, z1, - z2, z3, z4, z5, z6, z7, - // Inputs - clk, i - ); + // Outputs + a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, o1, o2, o3, o4, o5, + o6, o7, o8, o9, o10, o11, x1, x2, x3, x4, x5, x6, x7, x8, x9, z1, + z2, z3, z4, z5, z6, z7, + // Inputs + clk, i + ); - input clk; - input [31:0] i; + input clk; + input [31:0] i; - output logic a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11; - output logic o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11; - output logic x1, x2, x3, x4, x5, x6, x7, x8, x9; - output logic z1, z2, z3, z4, z5, z6, z7; + output logic a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11; + output logic o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11; + output logic x1, x2, x3, x4, x5, x6, x7, x8, x9; + output logic z1, z2, z3, z4, z5, z6, z7; - logic [127:0] d; - logic [17:0] e; - always_ff @(posedge clk) d <= {i, ~i, ~i, i}; - always_ff @(posedge clk) e <= i[17:00]; + logic [127:0] d; + logic [17:0] e; + always_ff @(posedge clk) d <= {i, ~i, ~i, i}; + always_ff @(posedge clk) e <= i[17:00]; - always_ff @(posedge clk) begin - a1 <= (i[5] & ~i[3] & i[1]); - a2 <= (i[5]==1 & i[3]==0 & i[1]==1); - a3 <= &{i[5], ~i[3], i[1]}; - a4 <= ((i & 32'b101010) == 32'b100010); - a5 <= ((i & 32'b001010) == 32'b000010) & i[5]; - a6 <= &i[5:3]; - a7 <= i[5] & i[4] & i[3] & i[5] & i[4]; - a8 <= &(~i[5:3]); - a9 <= ~i[5] & !i[4] & !i[3] && ~i[5] && !i[4]; - a10 <= ~(i[5] & ~d[3]) & (!i[5] & d[1]); // cannot be optimized - a11 <= d[0] & d[33] & d[66] & d[99] & !d[31] & !d[62] & !d[93] & !d[124] & e[0] & !e[1] & e[2]; - // - o1 <= (~i[5] | i[3] | ~i[1]); - o2 <= (i[5]!=1 | i[3]!=0 | i[1]!=1); - o3 <= |{~i[5], i[3], ~i[1]}; - o4 <= ((i & 32'b101010) != 32'b100010); - o5 <= ((i & 32'b001010) != 32'b000010) | !i[5]; - o6 <= |i[5:3]; - o7 <= i[5] | i[4] | i[3] | i[5] | i[4]; - o8 <= |(~i[5:3]); - o9 <= ~i[5] | !i[4] | ~i[3] || !i[5] || ~i[4]; - o10 <= ~(~i[5] | d[3]) | (i[5] | ~d[1]); // cannot be optimized - o11 <= d[0] | d[33] | d[66] | d[99] | !d[31] | !d[62] | !d[93] | !d[124] | e[0] | !e[1] | e[2]; - // - x1 <= (i[5] ^ ~i[3] ^ i[1]); - x2 <= (i[5]==1 ^ i[3]==0 ^ i[1]==1); - x3 <= ^{i[5], ~i[3], i[1]}; - x4 <= ^((i & 32'b101010) ^ 32'b001000); - x5 <= ^((i & 32'b001010) ^ 32'b001000) ^ i[5]; - x6 <= i[5] ^ ~i[3] ^ i[1] ^ i[3] ^ !i[1] ^ i[3] ^ ~i[1]; - x7 <= i[5] ^ (^((i & 32'b001010) ^ 32'b001000)); - x8 <= ~(~i[5] ^ d[3]) ^ (i[5] ^ ~d[1]); - x9 <= d[0] ^ d[33] ^ d[66] ^ d[99] ^ !d[31] ^ !d[62] ^ !d[93] ^ !d[124] ^ e[0] ^ !e[1] ^ e[2]; - // - // All zero/all one cases - z1 <= (i[5] & ~i[3] & ~i[5]); - z2 <= (~i[5] | i[3] | i[5]); - z3 <= (i[5] ^ ~i[3] ^ ~i[5] ^ i[3]); - z4 <= &(i[0] && !i[0]); - z5 <= |(i[1] || !i[1]); - z6 <= ^(i[2] ^ !i[2]); - z7 <= ^(i[2] ^ i[2]); - end + always_ff @(posedge clk) begin + a1 <= (i[5] & ~i[3] & i[1]); + a2 <= (i[5]==1 & i[3]==0 & i[1]==1); + a3 <= &{i[5], ~i[3], i[1]}; + a4 <= ((i & 32'b101010) == 32'b100010); + a5 <= ((i & 32'b001010) == 32'b000010) & i[5]; + a6 <= &i[5:3]; + a7 <= i[5] & i[4] & i[3] & i[5] & i[4]; + a8 <= &(~i[5:3]); + a9 <= ~i[5] & !i[4] & !i[3] && ~i[5] && !i[4]; + a10 <= ~(i[5] & ~d[3]) & (!i[5] & d[1]); // cannot be optimized + a11 <= d[0] & d[33] & d[66] & d[99] & !d[31] & !d[62] & !d[93] & !d[124] & e[0] & !e[1] & e[2]; + // + o1 <= (~i[5] | i[3] | ~i[1]); + o2 <= (i[5]!=1 | i[3]!=0 | i[1]!=1); + o3 <= |{~i[5], i[3], ~i[1]}; + o4 <= ((i & 32'b101010) != 32'b100010); + o5 <= ((i & 32'b001010) != 32'b000010) | !i[5]; + o6 <= |i[5:3]; + o7 <= i[5] | i[4] | i[3] | i[5] | i[4]; + o8 <= |(~i[5:3]); + o9 <= ~i[5] | !i[4] | ~i[3] || !i[5] || ~i[4]; + o10 <= ~(~i[5] | d[3]) | (i[5] | ~d[1]); // cannot be optimized + o11 <= d[0] | d[33] | d[66] | d[99] | !d[31] | !d[62] | !d[93] | !d[124] | e[0] | !e[1] | e[2]; + // + x1 <= (i[5] ^ ~i[3] ^ i[1]); + x2 <= (i[5]==1 ^ i[3]==0 ^ i[1]==1); + x3 <= ^{i[5], ~i[3], i[1]}; + x4 <= ^((i & 32'b101010) ^ 32'b001000); + x5 <= ^((i & 32'b001010) ^ 32'b001000) ^ i[5]; + x6 <= i[5] ^ ~i[3] ^ i[1] ^ i[3] ^ !i[1] ^ i[3] ^ ~i[1]; + x7 <= i[5] ^ (^((i & 32'b001010) ^ 32'b001000)); + x8 <= ~(~i[5] ^ d[3]) ^ (i[5] ^ ~d[1]); + x9 <= d[0] ^ d[33] ^ d[66] ^ d[99] ^ !d[31] ^ !d[62] ^ !d[93] ^ !d[124] ^ e[0] ^ !e[1] ^ e[2]; + // + // All zero/all one cases + z1 <= (i[5] & ~i[3] & ~i[5]); + z2 <= (~i[5] | i[3] | i[5]); + z3 <= (i[5] ^ ~i[3] ^ ~i[5] ^ i[3]); + z4 <= &(i[0] && !i[0]); + z5 <= |(i[1] || !i[1]); + z6 <= ^(i[2] ^ !i[2]); + z7 <= ^(i[2] ^ i[2]); + end endmodule module match ( - input logic [15:0] vec_i, - input logic b8_i, - input logic b12_i, - output logic match1_o, - output logic match2_o - ); + input logic [15:0] vec_i, + input logic b8_i, + input logic b12_i, + output logic match1_o, + output logic match2_o + ); - always_comb - begin - match1_o = 1'b0; - if ( - (vec_i[1:0] == 2'b0) - && - (vec_i[4] == 1'b0) - && - (vec_i[8] == b8_i) - && - (vec_i[12] == b12_i) - ) - begin - match1_o = 1'b1; - end - end + always_comb + begin + match1_o = 1'b0; + if ( + (vec_i[1:0] == 2'b0) + && + (vec_i[4] == 1'b0) + && + (vec_i[8] == b8_i) + && + (vec_i[12] == b12_i) + ) + begin + match1_o = 1'b1; + end + end - always_comb - begin - match2_o = 1'b0; - if ( - (vec_i[1:0] == 2'b0) - && - (vec_i[8] == b8_i) - && - (vec_i[12] == b12_i) - && - (vec_i[4] == 1'b0) - ) - begin - match2_o = 1'b1; - end - end + always_comb + begin + match2_o = 1'b0; + if ( + (vec_i[1:0] == 2'b0) + && + (vec_i[8] == b8_i) + && + (vec_i[12] == b12_i) + && + (vec_i[4] == 1'b0) + ) + begin + match2_o = 1'b1; + end + end endmodule diff --git a/test_regress/t/t_opt_const_shortcut.v b/test_regress/t/t_opt_const_shortcut.v index 42a7d4c9a..bedfd9f36 100644 --- a/test_regress/t/t_opt_const_shortcut.v +++ b/test_regress/t/t_opt_const_shortcut.v @@ -10,84 +10,84 @@ import "DPI-C" context function int import_func2(); import "DPI-C" context function int import_func3(); import "DPI-C" context function int import_func4(); -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - wire [31:0] i = crc[31:0]; - wire out; + wire [31:0] i = crc[31:0]; + wire out; - Test test( - // Outputs - .out (out), - // Inputs - .clk (clk), - .i (i[31:0])); + Test test ( + // Outputs + .out(out), + // Inputs + .clk(clk), + .i(i[31:0]) + ); - wire [63:0] result = {63'b0, out}; + wire [63:0] result = {63'b0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (import_func1() != 1) $stop; // this must be the first call - if (import_func3() != 1) $stop; // this must be the first call - if (import_func4() < 95) $stop; // expected to return around 100 - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h162c58b1635b8d6e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (import_func1() != 1) $stop; // this must be the first call + if (import_func3() != 1) $stop; // this must be the first call + if (import_func4() < 95) $stop; // expected to return around 100 + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h162c58b1635b8d6e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, i - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + i +); - input clk; - input [31:0] i; + input clk; + input [31:0] i; - output wire out; + output wire out; - logic [2:0] tmp; - assign out = ^tmp; + logic [2:0] tmp; + assign out = ^tmp; - always_ff @(posedge clk) begin - // Note that import_func?() always returns positive integer, - // so '|(import_func?())' is always 1'b1 - tmp[0] <= |(import_func0()) || |(import_func1()); // import_fnc1 must not be called - tmp[1] <= !(|(import_func2())) && |(import_func3()); // import_fnc3 must not be called - tmp[2] <= ^(0 * import_func4()); // import_func1 has side effect, so must be executed anyway. - end + always_ff @(posedge clk) begin + // Note that import_func?() always returns positive integer, + // so '|(import_func?())' is always 1'b1 + tmp[0] <= |(import_func0()) || |(import_func1()); // import_fnc1 must not be called + tmp[1] <= !(|(import_func2())) && |(import_func3()); // import_fnc3 must not be called + tmp[2] <= ^(0 * import_func4()); // import_func1 has side effect, so must be executed anyway. + end endmodule diff --git a/test_regress/t/t_opt_dead.v b/test_regress/t/t_opt_dead.v index 09c0a8c08..906e37d6e 100644 --- a/test_regress/t/t_opt_dead.v +++ b/test_regress/t/t_opt_dead.v @@ -8,23 +8,23 @@ class EmptyClass_Dead; endclass module Mod_Dead; -class ModClass_Dead; - int memberb_dead; -endclass + class ModClass_Dead; + int memberb_dead; + endclass endmodule //TODO dead check with class extends module t; - generate - if (0) begin - Mod_Dead cell_dead(); - end - endgenerate + generate + if (0) begin + Mod_Dead cell_dead (); + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_dead_enumpkg.v b/test_regress/t/t_opt_dead_enumpkg.v index 11bae4aed..1aa5c0570 100644 --- a/test_regress/t/t_opt_dead_enumpkg.v +++ b/test_regress/t/t_opt_dead_enumpkg.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef enum logic [2:0] { - TWO = 2, - THREE = 3 - } enum_t; + typedef enum logic [2:0] { + TWO = 2, + THREE = 3 + } enum_t; endpackage module t; - localparam L_TWO = pkg::TWO; - initial begin - if (L_TWO != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + localparam L_TWO = pkg::TWO; + initial begin + if (L_TWO != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_dead_noassigns.v b/test_regress/t/t_opt_dead_noassigns.v index e302db4ab..ba6de0172 100644 --- a/test_regress/t/t_opt_dead_noassigns.v +++ b/test_regress/t/t_opt_dead_noassigns.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - in - ); - input int in; + // Inputs + in + ); + input int in; - int ass_keptdead; + int ass_keptdead; - initial begin - if (in != 0) begin - ass_keptdead = 1 | in; - $display("Avoid gate removing"); - ass_keptdead = 2 | in; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (in != 0) begin + ass_keptdead = 1 | in; + $display("Avoid gate removing"); + ass_keptdead = 2 | in; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_dead_nocells.v b/test_regress/t/t_opt_dead_nocells.v index 4db59694e..db32a34e1 100644 --- a/test_regress/t/t_opt_dead_nocells.v +++ b/test_regress/t/t_opt_dead_nocells.v @@ -9,10 +9,10 @@ endmodule module t; - Mod_Dead cell_keptdead(); + Mod_Dead cell_keptdead (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_expand_keep_widths.v b/test_regress/t/t_opt_expand_keep_widths.v index 61f6ca22c..41b12f826 100644 --- a/test_regress/t/t_opt_expand_keep_widths.v +++ b/test_regress/t/t_opt_expand_keep_widths.v @@ -4,58 +4,64 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module gymhnulbvj (in5, clock_10, clock_12, out18); +module gymhnulbvj ( + in5, + clock_10, + clock_12, + out18 +); - input wire [23:22] in5; - wire [29:1] wire_4; - reg reg_35; - output wire out18; - input wire clock_10; - input wire clock_12; + input wire [23:22] in5; + wire [29:1] wire_4; + reg reg_35; + output wire out18; + input wire clock_10; + input wire clock_12; - // verilator lint_off WIDTH - assign wire_4 = ~ in5[22]; - assign out18 = reg_35 ? 0 : !(!(~(wire_4[6:5] | 8'hc6))); - // verilator lint_on WIDTH + // verilator lint_off WIDTH + assign wire_4 = ~in5[22]; + assign out18 = reg_35 ? 0 : !(!(~(wire_4[6:5] | 8'hc6))); + // verilator lint_on WIDTH - always @(posedge clock_10 or posedge clock_12) begin - if (clock_12) begin - reg_35 <= 0; - end - else begin - // verilator lint_off WIDTH - reg_35 <= wire_4; - // verilator lint_on WIDTH - end - end + always @(posedge clock_10 or posedge clock_12) begin + if (clock_12) begin + reg_35 <= 0; + end + else begin + // verilator lint_off WIDTH + reg_35 <= wire_4; + // verilator lint_on WIDTH + end + end endmodule module t; - reg [23:22] in5; - reg clock_10 = 0; - reg clock_12 = 0; - wire out18; + reg [23:22] in5; + reg clock_10 = 0; + reg clock_12 = 0; + wire out18; - gymhnulbvj uut ( - .in5(in5), - .clock_10(clock_10), - .clock_12(clock_12), - .out18(out18) - ); + gymhnulbvj uut ( + .in5(in5), + .clock_10(clock_10), + .clock_12(clock_12), + .out18(out18) + ); - initial begin - $monitor("[%0t] in5=%d clock_10=%d clock_12=%d out18=%d", $time, in5, clock_10, clock_12, out18); + initial begin + $monitor("[%0t] in5=%d clock_10=%d clock_12=%d out18=%d", $time, in5, clock_10, clock_12, + out18); - in5 = 2'b00; - #5 clock_12 = 1; - #5 clock_12 = 0; + in5 = 2'b00; + #5 clock_12 = 1; + #5 clock_12 = 0; - #5 clock_10 = 1; - #5 clock_10 = 0; + #5 clock_10 = 1; + #5 clock_10 = 0; - #10; - $write("*-* All Finished *-*\n"); - $finish; - end + #10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_if_array.v b/test_regress/t/t_opt_if_array.v index 9bb49b2fe..1baffaa37 100644 --- a/test_regress/t/t_opt_if_array.v +++ b/test_regress/t/t_opt_if_array.v @@ -4,49 +4,50 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - dinitout, - // Inputs - clk, rstn - ); +module t ( /*AUTOARG*/ + // Outputs + dinitout, + // Inputs + clk, + rstn +); - input clk; - input rstn; - output [31:0] dinitout; + input clk; + input rstn; + output [31:0] dinitout; - wire zero; - assign zero = 1'd0; + wire zero; + assign zero = 1'd0; - reg [31:0] dinit [0:1]; - wire [31:0] dinitout = dinit[0] | dinit[1]; + reg [31:0] dinit[0:1]; + wire [31:0] dinitout = dinit[0] | dinit[1]; - reg rstn_r; // .py file checks that this signal gets optimized away - always @(posedge clk) begin - rstn_r <= rstn; - end + reg rstn_r; // .py file checks that this signal gets optimized away + always @(posedge clk) begin + rstn_r <= rstn; + end - always @(posedge clk) begin - if ((rstn_r == 0)) begin // Will optimize away - dinit[0] <= '0; - end - else begin - dinit[0] <= {31'd0, zero}; - end - end + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[0] <= '0; + end + else begin + dinit[0] <= {31'd0, zero}; + end + end - always @(posedge clk) begin - if ((rstn_r == 0)) begin // Will optimize away - dinit[1] <= 1234; - end - else begin - dinit[1] <= 1234; - end - end + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[1] <= 1234; + end + else begin + dinit[1] <= 1234; + end + end - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_ifjumpgo.v b/test_regress/t/t_opt_ifjumpgo.v index 69ff06d76..6c31cfe16 100644 --- a/test_regress/t/t_opt_ifjumpgo.v +++ b/test_regress/t/t_opt_ifjumpgo.v @@ -10,27 +10,30 @@ endclass class uvm_callback; endclass -class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback); - bit m_registered = 1; - virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); - if (m_is_for_me(cb) && m_am_i_a(obj)) begin - return m_registered; - end - endfunction +class uvm_callbacks #( + type T = uvm_object, + type CB = uvm_callback +); + bit m_registered = 1; + virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); + if (m_is_for_me(cb) && m_am_i_a(obj)) begin + return m_registered; + end + endfunction - virtual function bit m_is_for_me(uvm_callback cb); - CB this_cb; - // verilator lint_off WIDTHTRUNC - return ($cast(this_cb, cb)); - // verilator lint_on WIDTHTRUNC - endfunction + virtual function bit m_is_for_me(uvm_callback cb); + CB this_cb; + // verilator lint_off WIDTHTRUNC + return ($cast(this_cb, cb)); + // verilator lint_on WIDTHTRUNC + endfunction - virtual function bit m_am_i_a(uvm_object obj); - T this_t; - // verilator lint_off WIDTHTRUNC - return ($cast(this_t, obj)); - // verilator lint_on WIDTHTRUNC - endfunction + virtual function bit m_am_i_a(uvm_object obj); + T this_t; + // verilator lint_off WIDTHTRUNC + return ($cast(this_t, obj)); + // verilator lint_on WIDTHTRUNC + endfunction endclass class my_object extends uvm_object; @@ -44,24 +47,24 @@ endclass module t; - initial begin - my_object obj; - other_object oobj; - my_callback cb; - uvm_callbacks#(my_object, my_callback) ucs; - bit i; + initial begin + my_object obj; + other_object oobj; + my_callback cb; + uvm_callbacks #(my_object, my_callback) ucs; + bit i; - obj = new; - oobj = new; - cb = new; - ucs = new; + obj = new; + oobj = new; + cb = new; + ucs = new; - i = ucs.m_is_registered(obj, cb); - if (i !== 1) $stop; - i = ucs.m_is_registered(oobj, cb); - if (i !== 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + i = ucs.m_is_registered(obj, cb); + if (i !== 1) $stop; + i = ucs.m_is_registered(oobj, cb); + if (i !== 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_inline_funcs.v b/test_regress/t/t_opt_inline_funcs.v index 56bfeeb51..e1aaa6481 100644 --- a/test_regress/t/t_opt_inline_funcs.v +++ b/test_regress/t/t_opt_inline_funcs.v @@ -4,9 +4,10 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 - +// verilog_format: off `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) +// verilog_format: on module t; diff --git a/test_regress/t/t_opt_life.v b/test_regress/t/t_opt_life.v index 7faa743f5..7b96b14dc 100644 --- a/test_regress/t/t_opt_life.v +++ b/test_regress/t/t_opt_life.v @@ -4,112 +4,107 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - // Life analysis checks - reg [15:0] life; + // Life analysis checks + reg [15:0] life; - // Ding case - reg [7:0] din; - reg [15:0] fixin; - always @* begin - fixin = {din[7:0],din[7:0]}; - case (din[1:0]) - 2'b00: begin - fixin = {fixin[14:0], 1'b1}; - if (cyc==101) $display("Prevent ?: optimization a"); - end - 2'b01: begin - fixin = {fixin[13:0], 2'b11}; - if (cyc==101) $display("Prevent ?: optimization b"); - end - 2'b10: begin - fixin = {fixin[12:0], 3'b111}; - if (cyc==101) $display("Prevent ?: optimization c"); - end - 2'b11: begin - fixin = {fixin[11:0], 4'b1111}; - if (cyc==101) $display("Prevent ?: optimization d"); - end - endcase - end - - // Remove CResets - function int f(int in); - automatic int aut; - aut = in; - return aut; - endfunction - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - life = 16'h8000; // Dropped - life = 16'h0010; // Used below - if (life != 16'h0010) $stop; - // - life = 16'h0020; // Used below - if ($time < 10000) - if (life != 16'h0020) $stop; - // - life = 16'h8000; // Dropped - if ($time > 100000) begin - if ($time != 0) $stop; // Prevent conversion to ?: - life = 16'h1030; - end - else - life = 16'h0030; - if (life != 16'h0030) $stop; - // - life = 16'h0040; // Not dropped, no else below - if ($time > 100000) - life = 16'h1040; - if (life != 16'h0040) $stop; - // - life = 16'h8000; // Dropped - if ($time > 100000) begin - life = 16'h1050; - if (life != 0) $stop; // Ignored, as set is first - end - else begin - if ($time > 100010) - life = 16'h1050; - else life = 16'h0050; - end - if (life != 16'h0050) $stop; - end - if (cyc==2) begin - din <= 8'haa; - end - if (cyc==3) begin - din <= 8'hfb; - if (fixin != 16'h5557) $stop; - end - if (cyc==4) begin - din <= 8'h5c; - if (fixin != 16'hbfbf) $stop; - end - if (cyc==5) begin - din <= 8'hed; - if (fixin != 16'hb8b9) $stop; - end - if (cyc==6) begin - if (fixin != 16'hb7b7) $stop; - end - if (cyc==8) begin - if (f(123) != 123) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Ding case + reg [7:0] din; + reg [15:0] fixin; + always @* begin + fixin = {din[7:0], din[7:0]}; + case (din[1:0]) + 2'b00: begin + fixin = {fixin[14:0], 1'b1}; + if (cyc == 101) $display("Prevent ?: optimization a"); end - end + 2'b01: begin + fixin = {fixin[13:0], 2'b11}; + if (cyc == 101) $display("Prevent ?: optimization b"); + end + 2'b10: begin + fixin = {fixin[12:0], 3'b111}; + if (cyc == 101) $display("Prevent ?: optimization c"); + end + 2'b11: begin + fixin = {fixin[11:0], 4'b1111}; + if (cyc == 101) $display("Prevent ?: optimization d"); + end + endcase + end + + // Remove CResets + function int f(int in); + automatic int aut; + aut = in; + return aut; + endfunction + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + life = 16'h8000; // Dropped + life = 16'h0010; // Used below + if (life != 16'h0010) $stop; + // + life = 16'h0020; // Used below + if ($time < 10000) if (life != 16'h0020) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + if ($time != 0) $stop; // Prevent conversion to ?: + life = 16'h1030; + end + else life = 16'h0030; + if (life != 16'h0030) $stop; + // + life = 16'h0040; // Not dropped, no else below + if ($time > 100000) life = 16'h1040; + if (life != 16'h0040) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + life = 16'h1050; + if (life != 0) $stop; // Ignored, as set is first + end + else begin + if ($time > 100010) life = 16'h1050; + else life = 16'h0050; + end + if (life != 16'h0050) $stop; + end + if (cyc == 2) begin + din <= 8'haa; + end + if (cyc == 3) begin + din <= 8'hfb; + if (fixin != 16'h5557) $stop; + end + if (cyc == 4) begin + din <= 8'h5c; + if (fixin != 16'hbfbf) $stop; + end + if (cyc == 5) begin + din <= 8'hed; + if (fixin != 16'hb8b9) $stop; + end + if (cyc == 6) begin + if (fixin != 16'hb7b7) $stop; + end + if (cyc == 8) begin + if (f(123) != 123) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_opt_localize_max_size.v b/test_regress/t/t_opt_localize_max_size.v index ae2d48d67..ca67404de 100644 --- a/test_regress/t/t_opt_localize_max_size.v +++ b/test_regress/t/t_opt_localize_max_size.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int x; - initial begin - x = $c32(1); - $display(x); - x = $c32(2); - $display(x); - $write("*-* All Finished *-*\n"); - $finish; - end + int x; + initial begin + x = $c32(1); + $display(x); + x = $c32(2); + $display(x); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_merge_cond.v b/test_regress/t/t_opt_merge_cond.v index 61aaa624a..edd71c3a6 100644 --- a/test_regress/t/t_opt_merge_cond.v +++ b/test_regress/t/t_opt_merge_cond.v @@ -4,232 +4,242 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc= 64'h5aef0c8d_d70a4497; - reg [63:0] prev_crc; + integer cyc = 0; + reg [63:0] crc = 64'h5aef0c8d_d70a4497; + reg [63:0] prev_crc; - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - prev_crc <= crc; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + prev_crc <= crc; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - wire cond2 = &crc[1:0]; - wire cond3 = &crc[2:0]; + wire cond2 = &crc[1:0]; + wire cond3 = &crc[2:0]; - reg shuf_q [63:0]; + reg shuf_q[63:0]; - always @(posedge clk) begin - reg bits [63:0]; - reg shuf_a [63:0]; - reg shuf_b [63:0]; - reg shuf_c [63:0]; - reg shuf_d [63:0]; - reg shuf_e [63:0]; + always @(posedge clk) begin + reg bits[63:0]; + reg shuf_a[63:0]; + reg shuf_b[63:0]; + reg shuf_c[63:0]; + reg shuf_d[63:0]; + reg shuf_e[63:0]; - // Unpack these to test core algorithm + // Unpack these to test core algorithm + for (int i = 0; i < 64; i = i + 1) begin + bits[i] = crc[i]; + end + + for (int i = 0; i < 64; i = i + 1) begin + shuf_a[i] = cyc[0] ? bits[i] : bits[63-i]; + end + + if (cyc[1]) begin for (int i = 0; i < 64; i = i + 1) begin - bits[i] = crc[i]; + shuf_b[i] = cyc[0] ? bits[i] : bits[63-i]; end - + end + else begin for (int i = 0; i < 64; i = i + 1) begin - shuf_a[i] = cyc[0] ? bits[i] : bits[63-i]; + shuf_b[i] = cyc[0] ? bits[63-i] : bits[i]; + end + end + + // Also test merge under clean/bit extract + for (int i = 0; i < 64; i = i + 1) begin + shuf_c[i] = cyc[0] ? crc[i] : crc[63-i]; + end + + // Merge with 'cond & value', 'value & cond', or 'cond' + shuf_d[0] = cond2 ? bits[0] : bits[63]; + for (int i = 1; i < 32; i = i + 2) begin + shuf_d[i] = cond2 & bits[i]; + end + for (int i = 2; i < 32; i = i + 2) begin + shuf_d[i] = bits[i] & cond2; + end + for (int i = 32; i < 64; i = i + 1) begin + shuf_d[i] = cond2; + end + + // Merge with an '&' also used for masking of LSB. + shuf_e[0] = cond3 ? bits[0] : bits[63]; + for (int i = 1; i < 64; i = i + 1) begin + shuf_e[i] = cond3 & crc[0]; + end + + // Also delayed.. + for (int i = 0; i < 64; i = i + 1) begin + shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i]; + end + + // Check results + + if (cyc[0]) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]); + end + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]); + end + + if (cyc[0] ~^ cyc[1]) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]); + end + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]); + end + + if (cyc[0]) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]); + end + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]); + end + + if (cond2) begin + `check(shuf_d[0], crc[0]); + for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]); + for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1); + end + else begin + `check(shuf_d[0], crc[63]); + for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0); + for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0); + end + + if (cond3) begin + `check(shuf_e[0], crc[0]); + for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]); + end + else begin + `check(shuf_e[0], crc[63]); + for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0); + end + + if (cyc > 0) begin + if (~cyc[0]) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]); + end + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]); end - if (cyc[1]) begin - for (int i = 0; i < 64; i = i + 1) begin - shuf_b[i] = cyc[0] ? bits[i] : bits[63-i]; - end - end else begin - for (int i = 0; i < 64; i = i + 1) begin - shuf_b[i] = cyc[0] ? bits[63-i] : bits[i]; - end + if (((cyc - 1) >> 1) % 2 == 1) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]); end - - // Also test merge under clean/bit extract - for (int i = 0; i < 64; i = i + 1) begin - shuf_c[i] = cyc[0] ? crc[i] : crc[63-i]; + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]); end + end - // Merge with 'cond & value', 'value & cond', or 'cond' - shuf_d[0] = cond2 ? bits[0] : bits[63]; - for (int i = 1; i < 32; i = i + 2) begin - shuf_d[i] = cond2 & bits[i]; - end - for (int i = 2; i < 32; i = i + 2) begin - shuf_d[i] = bits[i] & cond2; - end - for (int i = 32; i < 64; i = i + 1) begin - shuf_d[i] = cond2; - end + if (cyc[2]) begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]); + end + else begin + for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]); + end + end - // Merge with an '&' also used for masking of LSB. - shuf_e[0] = cond3 ? bits[0] : bits[63]; - for (int i = 1; i < 64; i = i + 1) begin - shuf_e[i] = cond3 & crc[0]; - end + // Generated always + reg shuf_g[63:0]; + generate + for (genvar i = 0; i < 64; i = i + 1) + always @(posedge clk) begin + shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i]; + end + endgenerate - // Also delayed.. - for (int i = 0; i < 64; i = i + 1) begin - shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i]; - end + // Generated assign + wire shuf_w[63:0]; + generate + for (genvar i = 0; i < 64; i = i + 1) assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i]; + endgenerate - // Check results + // Things not to merge + always @(posedge clk) begin + reg bits[63:0]; - if (cyc[0]) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]); - end + reg x; + reg y; + reg z; + reg w; - if (cyc[0] ~^ cyc[1]) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]); - end + // Unpack these to test core algorithm + for (int i = 0; i < 64; i = i + 1) begin + bits[i] = crc[i]; + end - if (cyc[0]) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]); - end + // Do not merge if condition appears in an LVALUE + x = bits[0]; + y = x ? bits[2] : bits[1]; + x = x ? bits[3] : bits[4]; + x = x ? bits[5] : bits[6]; - if (cond2) begin - `check(shuf_d[0], crc[0]); - for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]); - for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1); - end else begin - `check(shuf_d[0], crc[63]); - for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0); - for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0); - end + `check(x, (bits[0] ? bits[3] : bits[4]) ? bits[5] : bits[6]); + `check(y, bits[0] ? bits[2] : bits[1]); - if (cond3) begin - `check(shuf_e[0], crc[0]); - for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]); - end else begin - `check(shuf_e[0], crc[63]); - for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0); - end + // However do merge when starting a new list in the same block with the + // previous condition variable, but without the condition being an LVALUE + x = cond2 ? bits[0] : bits[1]; + y = cond2 & bits[2]; + z = cond2 & bits[3]; + w = cond2 & bits[4]; - if (cyc > 0) begin - if (~cyc[0]) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]); - end + `check(x, cond2 ? bits[0] : bits[1]); + `check(y, cond2 & bits[2]); + `check(z, cond2 & bits[3]); + `check(w, cond2 & bits[4]); - if (((cyc - 1) >> 1) % 2 == 1) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]); - end - end + // Do not merge if condition is not a pure expression + $c("int _cnt = 0;"); + x = $c("_cnt++") ? bits[0] : bits[1]; + y = $c("_cnt++") ? bits[2] : bits[3]; + z = $c("_cnt++") ? bits[4] : bits[5]; + w = $c("_cnt++") ? bits[6] : bits[7]; + $c("if (_cnt != 4) abort();"); - if (cyc[2]) begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]); - end else begin - for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]); - end - end + `check(x, bits[1]); + `check(y, bits[2]); + `check(z, bits[4]); + `check(w, bits[6]); - // Generated always - reg shuf_g [63:0]; - generate for (genvar i = 0 ; i < 64; i = i + 1) - always @(posedge clk) begin - shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i]; - end - endgenerate + // Do not merge with assignment under other statement + x = cond2 ? bits[0] : bits[1]; + if (bits[1]) begin + y = cond2 ? bits[2] : bits[3]; + end - // Generated assign - wire shuf_w [63:0]; - generate for (genvar i = 0 ; i < 64; i = i + 1) - assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i]; - endgenerate + `check(x, cond2 ? bits[0] : bits[1]); + if (bits[1]) begin + `check(y, cond2 ? bits[2] : bits[3]); + end - // Things not to merge - always @(posedge clk) begin - reg bits [63:0]; - - reg x; - reg y; - reg z; - reg w; - - // Unpack these to test core algorithm - for (int i = 0; i < 64; i = i + 1) begin - bits[i] = crc[i]; - end - - // Do not merge if condition appears in an LVALUE - x = bits[0]; - y = x ? bits[2] : bits[1]; - x = x ? bits[3] : bits[4]; - x = x ? bits[5] : bits[6]; - - `check(x, (bits[0] ? bits[3] : bits[4]) ? bits[5] : bits[6]); - `check(y, bits[0] ? bits[2] : bits[1]); - - // However do merge when starting a new list in the same block with the - // previous condition variable, but without the condition being an LVALUE - x = cond2 ? bits[0] : bits[1]; + // Do not merge with assignment under other statement + x = cond2 ? bits[0] : bits[1]; + if (bits[1]) begin y = cond2 & bits[2]; - z = cond2 & bits[3]; - w = cond2 & bits[4]; + end - `check(x, cond2 ? bits[0] : bits[1]); + `check(x, cond2 ? bits[0] : bits[1]); + if (bits[1]) begin `check(y, cond2 & bits[2]); - `check(z, cond2 & bits[3]); - `check(w, cond2 & bits[4]); - - // Do not merge if condition is not a pure expression - $c("int _cnt = 0;"); - x = $c("_cnt++") ? bits[0] : bits[1]; - y = $c("_cnt++") ? bits[2] : bits[3]; - z = $c("_cnt++") ? bits[4] : bits[5]; - w = $c("_cnt++") ? bits[6] : bits[7]; - $c("if (_cnt != 4) abort();"); - - `check(x, bits[1]); - `check(y, bits[2]); - `check(z, bits[4]); - `check(w, bits[6]); - - // Do not merge with assignment under other statement - x = cond2 ? bits[0] : bits[1]; - if (bits[1]) begin - y = cond2 ? bits[2] : bits[3]; - end - - `check(x, cond2 ? bits[0] : bits[1]); - if (bits[1]) begin - `check(y, cond2 ? bits[2] : bits[3]); - end - - // Do not merge with assignment under other statement - x = cond2 ? bits[0] : bits[1]; - if (bits[1]) begin - y = cond2 & bits[2]; - end - - `check(x, cond2 ? bits[0] : bits[1]); - if (bits[1]) begin - `check(y, cond2 & bits[2]); - end - end + end + end endmodule diff --git a/test_regress/t/t_opt_merge_cond_blowup.v b/test_regress/t/t_opt_merge_cond_blowup.v index 57927db99..9ecc42ee2 100644 --- a/test_regress/t/t_opt_merge_cond_blowup.v +++ b/test_regress/t/t_opt_merge_cond_blowup.v @@ -4,52 +4,51 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - localparam int N = 4096; + localparam int N = 4096; - integer cyc = 0; - reg [63:0] crc= 64'h5aef0c8d_d70a4497; + integer cyc = 0; + reg [63:0] crc = 64'h5aef0c8d_d70a4497; - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - reg a [N-1:0]; - reg b [N-1:0]; + reg a[N-1:0]; + reg b[N-1:0]; - // This yields pathological complexity for the current conditional merging - // algorithm. Note in practice, other parts of the compiler blow up on this - // code far earlier than the conditional merging, but here we go anyway. - generate - genvar i; - for (i = 0 ; i < N ; i = i + 1) begin - always @(posedge clk) a[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; - end - for (i = 0 ; i < N ; i = i + 1) begin - always @(posedge clk) b[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; - end - endgenerate + // This yields pathological complexity for the current conditional merging + // algorithm. Note in practice, other parts of the compiler blow up on this + // code far earlier than the conditional merging, but here we go anyway. + generate + genvar i; + for (i = 0; i < N; i = i + 1) begin + always @(posedge clk) a[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; + end + for (i = 0; i < N; i = i + 1) begin + always @(posedge clk) b[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; + end + endgenerate - always @(posedge clk) begin - if (cyc >= 2) begin - for (int i = 0 ; i < N ; i = i + 1) begin - if (a[i] !== b[i]) begin - $write("%%Error: %s:%0d: cyc=%0d i=%0d a[i]='h%x b[i]='h%x\n", `__FILE__,`__LINE__, cyc, i, a[i], b[i]); - $stop; - end + always @(posedge clk) begin + if (cyc >= 2) begin + for (int i = 0; i < N; i = i + 1) begin + if (a[i] !== b[i]) begin + $write("%%Error: %s:%0d: cyc=%0d i=%0d a[i]='h%x b[i]='h%x\n", `__FILE__, `__LINE__, cyc, + i, a[i], b[i]); + $stop; end end - end + end + end endmodule diff --git a/test_regress/t/t_opt_merge_cond_bug_3409.v b/test_regress/t/t_opt_merge_cond_bug_3409.v index f8713e16b..8f9527593 100644 --- a/test_regress/t/t_opt_merge_cond_bug_3409.v +++ b/test_regress/t/t_opt_merge_cond_bug_3409.v @@ -4,90 +4,90 @@ // SPDX-FileCopyrightText: 2022 Raynard Qiao // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] din = crc[3:0]; + // Take CRC data and apply to testblock inputs + wire [3:0] din = crc[3:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire row_found; // From test of Test.v - wire [1:0] row_idx; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire row_found; // From test of Test.v + wire [1:0] row_idx; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .row_idx (row_idx[1:0]), - .row_found (row_found), - // Inputs - .din (din)); + Test test ( /*AUTOINST*/ + // Outputs + .row_idx(row_idx[1:0]), + .row_found(row_found), + // Inputs + .din(din) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {48'b0, din, 7'b0, row_found, 2'b0, row_idx}; + // Aggregate outputs into a single result vector + wire [63:0] result = {48'b0, din, 7'b0, row_found, 2'b0, row_idx}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h8b61595b704e511f - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h8b61595b704e511f + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(/*AUTOARG*/ - // Outputs - row_idx, row_found, - // Inputs - din - ); +module Test ( /*AUTOARG*/ + // Outputs + row_idx, + row_found, + // Inputs + din +); - input din; - output [1:0] row_idx; - output row_found; + input din; + output [1:0] row_idx; + output row_found; - reg [3:0] din; - reg [3:0] wide_din; - reg row_found; - reg [1:0] row_idx; + reg [3:0] din; + reg [3:0] wide_din; + reg row_found; + reg [1:0] row_idx; - always_comb begin - integer x; - row_idx = {2{1'b0}}; - row_found = 1'b0; - // Issue #3409: After unrolling, these conditionals should not be merged - // as row_found is assigned. - for (x = 0; $unsigned(x) < 4; x = x + 1) begin - row_idx = !row_found ? x[1:0] : row_idx; - row_found = !row_found ? din[x] : row_found; - end - end + always_comb begin + integer x; + row_idx = {2{1'b0}}; + row_found = 1'b0; + // Issue #3409: After unrolling, these conditionals should not be merged + // as row_found is assigned. + for (x = 0; $unsigned(x) < 4; x = x + 1) begin + row_idx = !row_found ? x[1:0] : row_idx; + row_found = !row_found ? din[x] : row_found; + end + end endmodule diff --git a/test_regress/t/t_opt_merge_cond_motion_branch.v b/test_regress/t/t_opt_merge_cond_motion_branch.v index 990b4ec07..ea2b34ca1 100644 --- a/test_regress/t/t_opt_merge_cond_motion_branch.v +++ b/test_regress/t/t_opt_merge_cond_motion_branch.v @@ -6,18 +6,18 @@ // Based on ivtest's pr540.v by Steve Williams. module t; - bit fail = 0; - bit abort = 0; + bit fail = 0; + bit abort = 0; - initial begin - abort = 1; // Set here so it's non-constant, otherwise ifs gets folded - begin: block - if (abort) disable block; - fail = 1; // Don't try to move this in order to merge the 2 ifs - if (abort) $display("unreachable"); - end - if (fail) $error("block disable FAILED"); - $write("*-* All Finished *-*\n"); - $finish(0); - end + initial begin + abort = 1; // Set here so it's non-constant, otherwise ifs gets folded + begin : block + if (abort) disable block; + fail = 1; // Don't try to move this in order to merge the 2 ifs + if (abort) $display("unreachable"); + end + if (fail) $error("block disable FAILED"); + $write("*-* All Finished *-*\n"); + $finish(0); + end endmodule diff --git a/test_regress/t/t_opt_merge_cond_no_extend.v b/test_regress/t/t_opt_merge_cond_no_extend.v index bcff66546..2781cba1f 100644 --- a/test_regress/t/t_opt_merge_cond_no_extend.v +++ b/test_regress/t/t_opt_merge_cond_no_extend.v @@ -11,12 +11,12 @@ module t ( output reg [7:0] o ); - reg cond = 0; + reg cond = 0; - always @(posedge clk) begin - if (cond) o = i; - cond = a; - if (cond) o = ~i; - end + always @(posedge clk) begin + if (cond) o = i; + cond = a; + if (cond) o = ~i; + end endmodule diff --git a/test_regress/t/t_opt_redor.v b/test_regress/t/t_opt_redor.v index c42c90824..fb608b9d7 100644 --- a/test_regress/t/t_opt_redor.v +++ b/test_regress/t/t_opt_redor.v @@ -4,81 +4,80 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [15:0] in = crc[15:0]; + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out), - // Inputs - .in (in[15:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out), + // Inputs + .in(in[15:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h162c58b1635b8d6e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h162c58b1635b8d6e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); - input [15:0] in; - output reg out; + input [15:0] in; + output reg out; - // TODO this should flatten into a reduction OR - always_comb begin - out = 0; - for (int i=0; i<16; i=i+1) begin - if (in[i]) begin - out = 1; - end + // TODO this should flatten into a reduction OR + always_comb begin + out = 0; + for (int i = 0; i < 16; i = i + 1) begin + if (in[i]) begin + out = 1; end - end + end + end endmodule diff --git a/test_regress/t/t_opt_slice.v b/test_regress/t/t_opt_slice.v index 4a6c095e0..029175aac 100644 --- a/test_regress/t/t_opt_slice.v +++ b/test_regress/t/t_opt_slice.v @@ -4,20 +4,20 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - o1a2, - // Inputs - i1a2 - ); +module t ( /*AUTOARG*/ + // Outputs + o1a2, + // Inputs + i1a2 +); - input i1a2 [1:0]; - output logic o1a2 [1:0]; + input i1a2[1:0]; + output logic o1a2[1:0]; - always o1a2 = i1a2; + always o1a2 = i1a2; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_slice_element_limit.v b/test_regress/t/t_opt_slice_element_limit.v index b69a3eff3..dc845a07b 100644 --- a/test_regress/t/t_opt_slice_element_limit.v +++ b/test_regress/t/t_opt_slice_element_limit.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input logic [7:0] i1 [8], - input logic [7:0] i2 [16], - input logic [7:0] i3 [512], - output logic [7:0] o1 [8], - output logic [7:0] o2 [16], - output logic [7:0] o3 [256] - ); + input logic [7:0] i1[8], + input logic [7:0] i2[16], + input logic [7:0] i3[512], + output logic [7:0] o1[8], + output logic [7:0] o2[16], + output logic [7:0] o3[256] +); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_opt_table_display.v b/test_regress/t/t_opt_table_display.v index 6c859ca45..e34c3ed12 100644 --- a/test_regress/t/t_opt_table_display.v +++ b/test_regress/t/t_opt_table_display.v @@ -4,41 +4,41 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - test, - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Outputs + test, + // Inputs + clk +); + input clk; - output reg [5:0] test; - parameter STATE1 = 6'b000001; - parameter STATE2 = 6'b000010; - parameter STATE3 = 6'b000100; - parameter STATE4 = 6'b001000; - parameter STATE5 = 6'b010000; - parameter STATE6 = 6'b100000; + output reg [5:0] test; + parameter STATE1 = 6'b000001; + parameter STATE2 = 6'b000010; + parameter STATE3 = 6'b000100; + parameter STATE4 = 6'b001000; + parameter STATE5 = 6'b010000; + parameter STATE6 = 6'b100000; - always @(posedge clk) begin - $display("Clocked"); - case (test) - STATE1: test <= STATE2; - STATE2: test <= STATE3; - STATE3: test <= STATE4; - STATE4: test <= STATE5; - STATE5: test <= STATE6; - default: test <= STATE1; - endcase - end + always @(posedge clk) begin + $display("Clocked"); + case (test) + STATE1: test <= STATE2; + STATE2: test <= STATE3; + STATE3: test <= STATE4; + STATE4: test <= STATE5; + STATE5: test <= STATE6; + default: test <= STATE1; + endcase + end - int cyc; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cyc; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_enum.v b/test_regress/t/t_opt_table_enum.v index 7b31a3331..e1a93f3db 100644 --- a/test_regress/t/t_opt_table_enum.v +++ b/test_regress/t/t_opt_table_enum.v @@ -4,42 +4,42 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - enum { - CASE_0 = 0, - CASE_1 = 1, - CASE_2 = 2, - CASE_4 = 4, - CASE_5 = 5, - DEFAULT = 99 - } e; + enum { + CASE_0 = 0, + CASE_1 = 1, + CASE_2 = 2, + CASE_4 = 4, + CASE_5 = 5, + DEFAULT = 99 + } e; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: e = CASE_0; - 3'b001: e = CASE_1; - 3'b010: e = CASE_2; - 3'b100: e = CASE_4; - 3'b101: e = CASE_5; - default: e = DEFAULT; - endcase - end + always @* begin + case (cyc) + 3'b000: e = CASE_0; + 3'b001: e = CASE_1; + 3'b010: e = CASE_2; + 3'b100: e = CASE_4; + 3'b101: e = CASE_5; + default: e = DEFAULT; + endcase + end - always @(posedge clk) begin - $display("cyle %d = %d", cyc, e); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = %d", cyc, e); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_fsm.v b/test_regress/t/t_opt_table_fsm.v index bd9e3d66e..0a1ec7954 100644 --- a/test_regress/t/t_opt_table_fsm.v +++ b/test_regress/t/t_opt_table_fsm.v @@ -3,158 +3,147 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - reg reset; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire myevent; // From test of Test.v - wire myevent_pending; // From test of Test.v - wire [1:0] state; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire myevent; // From test of Test.v + wire myevent_pending; // From test of Test.v + wire [1:0] state; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .state (state[1:0]), - .myevent (myevent), - .myevent_pending (myevent_pending), - // Inputs - .clk (clk), - .reset (reset)); + Test test ( /*AUTOINST*/ + // Outputs + .state(state[1:0]), + .myevent(myevent), + .myevent_pending(myevent_pending), + // Inputs + .clk(clk), + .reset(reset) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, myevent_pending,myevent,state}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, myevent_pending, myevent, state}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent, myevent_pending); + $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent, + myevent_pending); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - reset <= (cyc<2); - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4e93a74bd97b25ef - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + reset <= (cyc < 2); + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h4e93a74bd97b25ef + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - state, myevent, myevent_pending, - // Inputs - clk, reset - ); - input clk; - input reset; - output [1:0] state; - output myevent; - output myevent_pending; +module Test ( /*AUTOARG*/ + // Outputs + state, + myevent, + myevent_pending, + // Inputs + clk, + reset +); + input clk; + input reset; + output [1:0] state; + output myevent; + output myevent_pending; - reg [5:0] count = 0; - always @ (posedge clk) - if (reset) count <= 0; - else count <= count + 1; + reg [5:0] count = 0; + always @(posedge clk) + if (reset) count <= 0; + else count <= count + 1; - reg myevent = 1'b0; - always @ (posedge clk) - myevent <= (count == 6'd27); + reg myevent = 1'b0; + always @(posedge clk) myevent <= (count == 6'd27); - reg myevent_done; - reg hickup_ready; - reg hickup_done; + reg myevent_done; + reg hickup_ready; + reg hickup_done; - localparam STATE_ZERO = 0; - localparam STATE_ONE = 1; - localparam STATE_TWO = 2; + localparam STATE_ZERO = 0; + localparam STATE_ONE = 1; + localparam STATE_TWO = 2; - reg [1:0] state = STATE_ZERO; - reg state_start_myevent = 1'b0; - reg state_start_hickup = 1'b0; - reg myevent_pending = 1'b0; - always @ (posedge clk) begin - state <= state; - myevent_pending <= myevent_pending || myevent; - state_start_myevent <= 1'b0; - state_start_hickup <= 1'b0; - case (state) - STATE_ZERO: - if (myevent_pending) begin - state <= STATE_ONE; - myevent_pending <= 1'b0; - state_start_myevent <= 1'b1; - end else if (hickup_ready) begin - state <= STATE_TWO; - state_start_hickup <= 1'b1; - end + reg [1:0] state = STATE_ZERO; + reg state_start_myevent = 1'b0; + reg state_start_hickup = 1'b0; + reg myevent_pending = 1'b0; + always @(posedge clk) begin + state <= state; + myevent_pending <= myevent_pending || myevent; + state_start_myevent <= 1'b0; + state_start_hickup <= 1'b0; + case (state) + STATE_ZERO: + if (myevent_pending) begin + state <= STATE_ONE; + myevent_pending <= 1'b0; + state_start_myevent <= 1'b1; + end + else if (hickup_ready) begin + state <= STATE_TWO; + state_start_hickup <= 1'b1; + end - STATE_ONE: - if (myevent_done) - state <= STATE_ZERO; + STATE_ONE: if (myevent_done) state <= STATE_ZERO; - STATE_TWO: - if (hickup_done) - state <= STATE_ZERO; + STATE_TWO: if (hickup_done) state <= STATE_ZERO; - default: - ; /* do nothing */ - endcase - end + default: ; /* do nothing */ + endcase + end - reg [3:0] myevent_count = 0; - always @ (posedge clk) - if (state_start_myevent) - myevent_count <= 9; - else if (myevent_count > 0) - myevent_count <= myevent_count - 1; + reg [3:0] myevent_count = 0; + always @(posedge clk) + if (state_start_myevent) myevent_count <= 9; + else if (myevent_count > 0) myevent_count <= myevent_count - 1; - initial myevent_done = 1'b0; - always @ (posedge clk) - myevent_done <= (myevent_count == 0); + initial myevent_done = 1'b0; + always @(posedge clk) myevent_done <= (myevent_count == 0); - reg [4:0] hickup_backlog = 2; - always @ (posedge clk) - if (state_start_myevent) - hickup_backlog <= hickup_backlog - 1; - else if (state_start_hickup) - hickup_backlog <= hickup_backlog + 1; + reg [4:0] hickup_backlog = 2; + always @(posedge clk) + if (state_start_myevent) hickup_backlog <= hickup_backlog - 1; + else if (state_start_hickup) hickup_backlog <= hickup_backlog + 1; - initial hickup_ready = 1'b1; - always @ (posedge clk) - hickup_ready <= (hickup_backlog < 3); + initial hickup_ready = 1'b1; + always @(posedge clk) hickup_ready <= (hickup_backlog < 3); - reg [3:0] hickup_count = 0; - always @ (posedge clk) - if (state_start_hickup) - hickup_count <= 10; - else if (hickup_count > 0) - hickup_count <= hickup_count - 1; + reg [3:0] hickup_count = 0; + always @(posedge clk) + if (state_start_hickup) hickup_count <= 10; + else if (hickup_count > 0) hickup_count <= hickup_count - 1; - initial hickup_done = 1'b0; - always @ (posedge clk) - hickup_done <= (hickup_count == 1); + initial hickup_done = 1'b0; + always @(posedge clk) hickup_done <= (hickup_count == 1); endmodule diff --git a/test_regress/t/t_opt_table_packed_array.v b/test_regress/t/t_opt_table_packed_array.v index b06fb0d32..70c9c9191 100644 --- a/test_regress/t/t_opt_table_packed_array.v +++ b/test_regress/t/t_opt_table_packed_array.v @@ -4,35 +4,33 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic [3:0][3:0] a; + logic [3:0][3:0] a; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: a = {4'd0, 4'd1, 4'd2, 4'd3}; - 3'b001: a = {4'd1, 4'd2, 4'd3, 4'd4}; - 3'b010: a = {4'd4, 4'd3, 4'd4, 4'd5}; - 3'b100: a = {4'd4, 4'd5, 4'd6, 4'd7}; - 3'b101: a = {4'd5, 4'd6, 4'd7, 4'd8}; - default: a = {4{4'hf}}; - endcase - end + always @* begin + case (cyc) + 3'b000: a = {4'd0, 4'd1, 4'd2, 4'd3}; + 3'b001: a = {4'd1, 4'd2, 4'd3, 4'd4}; + 3'b010: a = {4'd4, 4'd3, 4'd4, 4'd5}; + 3'b100: a = {4'd4, 4'd5, 4'd6, 4'd7}; + 3'b101: a = {4'd5, 4'd6, 4'd7, 4'd8}; + default: a = {4{4'hf}}; + endcase + end - always @(posedge clk) begin - $display("cyle %d = { %d, %d, %d, %d }", cyc, a[0], a[1], a[2], a[3]); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = { %d, %d, %d, %d }", cyc, a[0], a[1], a[2], a[3]); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_same.v b/test_regress/t/t_opt_table_same.v index 1695187bc..65d476f9c 100644 --- a/test_regress/t/t_opt_table_same.v +++ b/test_regress/t/t_opt_table_same.v @@ -4,48 +4,46 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int i; - int j; + int i; + int j; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: i = 0; - 3'b001: i = 1; - 3'b010: i = 2; - 3'b100: i = 4; - 3'b101: i = 5; - default: i = 99; - endcase - end + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = 1; + 3'b010: i = 2; + 3'b100: i = 4; + 3'b101: i = 5; + default: i = 99; + endcase + end - // Equivalent to above - always @* begin - case (cyc) - 3'b101: j = 5; - 3'b100: j = 4; - 3'b010: j = 2; - 3'b001: j = 1; - 3'b000: j = 0; - default: j = 99; - endcase - end + // Equivalent to above + always @* begin + case (cyc) + 3'b101: j = 5; + 3'b100: j = 4; + 3'b010: j = 2; + 3'b001: j = 1; + 3'b000: j = 0; + default: j = 99; + endcase + end - always @(posedge clk) begin - $display("cyle %d = %d %d", cyc, i, j); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = %d %d", cyc, i, j); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_signed.v b/test_regress/t/t_opt_table_signed.v index 95108bdd1..9578f2c5a 100644 --- a/test_regress/t/t_opt_table_signed.v +++ b/test_regress/t/t_opt_table_signed.v @@ -4,35 +4,33 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int i; + int i; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: i = 0; - 3'b001: i = -1; - 3'b010: i = 2; - 3'b100: i = -4; - 3'b101: i = 5; - default: i = -1 << 31; - endcase - end + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = -1; + 3'b010: i = 2; + 3'b100: i = -4; + 3'b101: i = 5; + default: i = -1 << 31; + endcase + end - always @(posedge clk) begin - $display("cyle %d = %d", cyc, i); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = %d", cyc, i); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_sparse.v b/test_regress/t/t_opt_table_sparse.v index e9647baec..6ea1f4218 100644 --- a/test_regress/t/t_opt_table_sparse.v +++ b/test_regress/t/t_opt_table_sparse.v @@ -4,37 +4,35 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int i; + int i; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - /* verilator lint_off LATCH */ - always @* begin - case (cyc) - 3'b000: i = 0; - 3'b001: i = 1; - 3'b010: ; // unset - 3'b100: i = 4; - 3'b101: i = 5; - default: i = 99; - endcase - end - /* verilator lint_on LATCH */ + /* verilator lint_off LATCH */ + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = 1; + 3'b010: ; // unset + 3'b100: i = 4; + 3'b101: i = 5; + default: i = 99; + endcase + end + /* verilator lint_on LATCH */ - always @(posedge clk) begin - $display("cyle %d = %d", cyc, i); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = %d", cyc, i); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_string.v b/test_regress/t/t_opt_table_string.v index 1b91b0c77..ab0842b87 100644 --- a/test_regress/t/t_opt_table_string.v +++ b/test_regress/t/t_opt_table_string.v @@ -4,34 +4,32 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - string s; - reg [2:0] cyc; + string s; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: s = "case-0"; - 3'b001: s = "case-1"; - 3'b010: s = "case-2"; - 3'b100: s = "case-4"; - 3'b101: s = "case-5"; - default: s = "default"; - endcase - end + always @* begin + case (cyc) + 3'b000: s = "case-0"; + 3'b001: s = "case-1"; + 3'b010: s = "case-2"; + 3'b100: s = "case-4"; + 3'b101: s = "case-5"; + default: s = "default"; + endcase + end - always @(posedge clk) begin - $display("cyle %d = %s", cyc, s); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = %s", cyc, s); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_opt_table_struct.v b/test_regress/t/t_opt_table_struct.v index 25e1f6072..00085b282 100644 --- a/test_regress/t/t_opt_table_struct.v +++ b/test_regress/t/t_opt_table_struct.v @@ -4,39 +4,37 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - struct packed { - bit [31:0] a; - bit [15:0] b; - bit [ 7:0] c; - } s; + struct packed { + bit [31:0] a; + bit [15:0] b; + bit [7:0] c; + } s; - reg [2:0] cyc; + reg [2:0] cyc; - initial cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - always @* begin - case (cyc) - 3'b000: s = {32'd0, 16'd1, 8'd2}; - 3'b001: s = {32'd1, 16'd2, 8'd3}; - 3'b010: s = {32'd2, 16'd3, 8'd4}; - 3'b100: s = {32'd4, 16'd5, 8'd6}; - 3'b101: s = {32'd5, 16'd6, 8'd7}; - default: s = '0; - endcase - end + always @* begin + case (cyc) + 3'b000: s = {32'd0, 16'd1, 8'd2}; + 3'b001: s = {32'd1, 16'd2, 8'd3}; + 3'b010: s = {32'd2, 16'd3, 8'd4}; + 3'b100: s = {32'd4, 16'd5, 8'd6}; + 3'b101: s = {32'd5, 16'd6, 8'd7}; + default: s = '0; + endcase + end - always @(posedge clk) begin - $display("cyle %d = { %d, %d, %d }", cyc, s.a, s.b, s.c); - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("cyle %d = { %d, %d, %d }", cyc, s.a, s.b, s.c); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v index 04359f5d0..72e181938 100644 --- a/test_regress/t/t_order.v +++ b/test_regress/t/t_order.v @@ -4,103 +4,101 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - // surefire lint_off ASWEBB - // surefire lint_off ASWEMB - // surefire lint_off STMINI - // surefire lint_off CSEBEQ + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + // surefire lint_off STMINI + // surefire lint_off CSEBEQ - input clk; + reg [7:0] a_to_clk_levm3; + reg [7:0] b_to_clk_levm1; + reg [7:0] c_com_levs10; + reg [7:0] d_to_clk_levm2; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v + wire [7:0] n_from_clk_lev2; // From a of t_order_a.v + wire [7:0] o_from_com_levs11; // From a of t_order_a.v + wire [7:0] o_from_comandclk_levs12; // From a of t_order_a.v + wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v + // End of automatics - reg [7:0] a_to_clk_levm3; - reg [7:0] b_to_clk_levm1; - reg [7:0] c_com_levs10; - reg [7:0] d_to_clk_levm2; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v - wire [7:0] n_from_clk_lev2; // From a of t_order_a.v - wire [7:0] o_from_com_levs11; // From a of t_order_a.v - wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v - wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v - // End of automatics + reg [7:0] cyc; + initial cyc = 0; - reg [7:0] cyc; initial cyc = 0; + t_order_a a ( + .one(8'h1), + /*AUTOINST*/ + // Outputs + .m_from_clk_lev1_r(m_from_clk_lev1_r[7:0]), + .n_from_clk_lev2(n_from_clk_lev2[7:0]), + .o_from_com_levs11(o_from_com_levs11[7:0]), + .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), + // Inputs + .clk(clk), + .a_to_clk_levm3(a_to_clk_levm3[7:0]), + .b_to_clk_levm1(b_to_clk_levm1[7:0]), + .c_com_levs10(c_com_levs10[7:0]), + .d_to_clk_levm2(d_to_clk_levm2[7:0]) + ); - t_order_a a ( - .one (8'h1), - /*AUTOINST*/ - // Outputs - .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), - .n_from_clk_lev2 (n_from_clk_lev2[7:0]), - .o_from_com_levs11 (o_from_com_levs11[7:0]), - .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), - // Inputs - .clk (clk), - .a_to_clk_levm3 (a_to_clk_levm3[7:0]), - .b_to_clk_levm1 (b_to_clk_levm1[7:0]), - .c_com_levs10 (c_com_levs10[7:0]), - .d_to_clk_levm2 (d_to_clk_levm2[7:0])); + t_order_b b ( + /*AUTOINST*/ + // Outputs + .o_subfrom_clk_lev2(o_subfrom_clk_lev2[7:0]), + // Inputs + .m_from_clk_lev1_r(m_from_clk_lev1_r[7:0]) + ); - t_order_b b ( - /*AUTOINST*/ - // Outputs - .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), - // Inputs - .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); + reg [7:0] o_from_com_levs12; + reg [7:0] o_from_com_levs13; + always @( /*AS*/ o_from_com_levs11) begin + o_from_com_levs12 = o_from_com_levs11 + 8'h1; + o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize + o_from_com_levs13 = o_from_com_levs12; + end - reg [7:0] o_from_com_levs12; - reg [7:0] o_from_com_levs13; - always @ (/*AS*/o_from_com_levs11) begin - o_from_com_levs12 = o_from_com_levs11 + 8'h1; - o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize - o_from_com_levs13 = o_from_com_levs12; - end + reg sepassign_in; + wire [3:0] sepassign; - reg sepassign_in; - wire [3:0] sepassign; + // verilator lint_off UNOPT + assign #0.1 sepassign[0] = 0, + sepassign[1] = sepassign[2], + sepassign[2] = sepassign[3], + sepassign[3] = sepassign_in; + wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; + // verilator lint_on UNOPT - // verilator lint_off UNOPT - assign #0.1 sepassign[0] = 0, - sepassign[1] = sepassign[2], - sepassign[2] = sepassign[3], - sepassign[3] = sepassign_in; - wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; - // verilator lint_on UNOPT + always @(posedge clk) begin + cyc <= cyc + 8'd1; + sepassign_in <= 0; + if (cyc == 8'd1) begin + a_to_clk_levm3 <= 0; + d_to_clk_levm2 <= 1; + b_to_clk_levm1 <= 1; + c_com_levs10 <= 2; + sepassign_in <= 1; + end + if (cyc == 8'd2) begin + if (sepassign !== 4'b1110) $stop; + end + if (cyc == 8'd3) begin - always @ (posedge clk) begin - cyc <= cyc+8'd1; - sepassign_in <= 0; - if (cyc == 8'd1) begin - a_to_clk_levm3 <= 0; - d_to_clk_levm2 <= 1; - b_to_clk_levm1 <= 1; - c_com_levs10 <= 2; - sepassign_in <= 1; - end - if (cyc == 8'd2) begin - if (sepassign !== 4'b1110) $stop; - end - if (cyc == 8'd3) begin + $display("%d %d %d %d", m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, + o_from_comandclk_levs12); - $display("%d %d %d %d", m_from_clk_lev1_r, - n_from_clk_lev2, - o_from_com_levs11, - o_from_comandclk_levs12); - - if (m_from_clk_lev1_r !== 8'h2) $stop; - if (o_subfrom_clk_lev3 !== 8'h2) $stop; - if (n_from_clk_lev2 !== 8'h2) $stop; - if (o_from_com_levs11 !== 8'h3) $stop; - if (o_from_com_levs13 !== 8'h5) $stop; - if (o_from_comandclk_levs12 !== 8'h5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (m_from_clk_lev1_r !== 8'h2) $stop; + if (o_subfrom_clk_lev3 !== 8'h2) $stop; + if (n_from_clk_lev2 !== 8'h2) $stop; + if (o_from_com_levs11 !== 8'h3) $stop; + if (o_from_com_levs13 !== 8'h5) $stop; + if (o_from_comandclk_levs12 !== 8'h5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_order_2d.v b/test_regress/t/t_order_2d.v index 773de764b..080f277fb 100644 --- a/test_regress/t/t_order_2d.v +++ b/test_regress/t/t_order_2d.v @@ -4,77 +4,76 @@ // SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire input_signal = crc[0]; + // Take CRC data and apply to testblock inputs + wire input_signal = crc[0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire output_signal; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire output_signal; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .output_signal (output_signal), - // Inputs - .input_signal (input_signal)); + Test test ( /*AUTOINST*/ + // Outputs + .output_signal(output_signal), + // Inputs + .input_signal(input_signal) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'h0, output_signal}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, output_signal}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h765b2e12b25ec97b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h765b2e12b25ec97b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( input input_signal, output output_signal - ); +); - // bug872 + // bug872 - // verilator lint_off UNOPTFLAT - wire some_signal[1:0][1:0]; - assign some_signal[0][0] = input_signal; - assign some_signal[0][1] = some_signal[0][0]; - assign some_signal[1][0] = some_signal[0][1]; - assign some_signal[1][1] = some_signal[1][0]; - assign output_signal = some_signal[1][1]; + // verilator lint_off UNOPTFLAT + wire some_signal[1:0][1:0]; + assign some_signal[0][0] = input_signal; + assign some_signal[0][1] = some_signal[0][0]; + assign some_signal[1][0] = some_signal[0][1]; + assign some_signal[1][1] = some_signal[1][0]; + assign output_signal = some_signal[1][1]; endmodule diff --git a/test_regress/t/t_order_a.v b/test_regress/t/t_order_a.v index 839c3ace7..09d8a9a64 100644 --- a/test_regress/t/t_order_a.v +++ b/test_regress/t/t_order_a.v @@ -4,51 +4,52 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_order_a (/*AUTOARG*/ - // Outputs - m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, - o_from_comandclk_levs12, - // Inputs - clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one - ); +module t_order_a ( /*AUTOARG*/ + // Outputs + m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, + o_from_comandclk_levs12, + // Inputs + clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one + ); - input clk; - input [7:0] a_to_clk_levm3; - input [7:0] b_to_clk_levm1; - input [7:0] c_com_levs10; - input [7:0] d_to_clk_levm2; - input [7:0] one; - output [7:0] m_from_clk_lev1_r; - output [7:0] n_from_clk_lev2; - output [7:0] o_from_com_levs11; - output [7:0] o_from_comandclk_levs12; + input clk; + input [7:0] a_to_clk_levm3; + input [7:0] b_to_clk_levm1; + input [7:0] c_com_levs10; + input [7:0] d_to_clk_levm2; + input [7:0] one; + output [7:0] m_from_clk_lev1_r; + output [7:0] n_from_clk_lev2; + output [7:0] o_from_com_levs11; + output [7:0] o_from_comandclk_levs12; - /*AUTOREG*/ - // Beginning of automatic regs (for this module's undeclared outputs) - reg [7:0] m_from_clk_lev1_r; - // End of automatics + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [7:0] m_from_clk_lev1_r; + // End of automatics - // surefire lint_off ASWEBB - // surefire lint_off ASWEMB + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB - wire [7:0] a_to_clk_levm1; - wire [7:0] a_to_clk_levm2; - wire [7:0] c_com_levs11; - reg [7:0] o_from_comandclk_levs12; - wire [7:0] n_from_clk_lev2; - wire [7:0] n_from_clk_lev3; + wire [7:0] a_to_clk_levm1; + wire [7:0] a_to_clk_levm2; + wire [7:0] c_com_levs11; + reg [7:0] o_from_comandclk_levs12; + wire [7:0] n_from_clk_lev2; + wire [7:0] n_from_clk_lev3; - assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; - assign a_to_clk_levm2 = a_to_clk_levm3 + 0; + assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; + assign a_to_clk_levm2 = a_to_clk_levm3 + 0; - always @ (posedge clk) begin - m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; - end + always @(posedge clk) begin + m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; + end - assign c_com_levs11 = c_com_levs10 + one; - always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; - assign n_from_clk_lev2 = m_from_clk_lev1_r; - assign n_from_clk_lev3 = n_from_clk_lev2; - wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; + assign c_com_levs11 = c_com_levs10 + one; + always @( /*AS*/c_com_levs11 or n_from_clk_lev3) + o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; + assign n_from_clk_lev2 = m_from_clk_lev1_r; + assign n_from_clk_lev3 = n_from_clk_lev2; + wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; endmodule diff --git a/test_regress/t/t_order_b.v b/test_regress/t/t_order_b.v index 1229ad2a9..e87e5bef2 100644 --- a/test_regress/t/t_order_b.v +++ b/test_regress/t/t_order_b.v @@ -4,16 +4,16 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_order_b (/*AUTOARG*/ - // Outputs - o_subfrom_clk_lev2, - // Inputs - m_from_clk_lev1_r - ); +module t_order_b ( /*AUTOARG*/ + // Outputs + o_subfrom_clk_lev2, + // Inputs + m_from_clk_lev1_r +); - input [7:0] m_from_clk_lev1_r; - output [7:0] o_subfrom_clk_lev2; + input [7:0] m_from_clk_lev1_r; + output [7:0] o_subfrom_clk_lev2; - wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; + wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; endmodule diff --git a/test_regress/t/t_order_blkandnblk_bad.out b/test_regress/t/t_order_blkandnblk_bad.out index 64452a103..f11e87488 100644 --- a/test_regress/t/t_order_blkandnblk_bad.out +++ b/test_regress/t/t_order_blkandnblk_bad.out @@ -1,30 +1,30 @@ -%Warning-MULTIDRIVEN: t/t_order_blkandnblk_bad.v:33:6: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'unpacked' - : ... note: In instance 't' - t/t_order_blkandnblk_bad.v:33:6: - 33 | unpacked.b <= unpacked.a; - | ^~~~~~~~ - t/t_order_blkandnblk_bad.v:30:16: ... Location of always_comb write - 30 | always_comb unpacked.a = i; - | ^~~~~~~~ +%Warning-MULTIDRIVEN: t/t_order_blkandnblk_bad.v:33:25: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'unpacked' + : ... note: In instance 't' + t/t_order_blkandnblk_bad.v:33:25: + 33 | always @(posedge clk) unpacked.b <= unpacked.a; + | ^~~~~~~~ + t/t_order_blkandnblk_bad.v:31:15: ... Location of always_comb write + 31 | always_comb unpacked.a = i; + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:18:21: Unsupported: Blocking and non-blocking assignments to potentially overlapping bits of same packed variable: 't.array' - 18 | logic [1:0][3:0] array; - | ^~~~~ - t/t_order_blkandnblk_bad.v:20:25: ... Location of blocking assignment (bits [3:0]) - 20 | always_comb array[0] = i; - | ^ - t/t_order_blkandnblk_bad.v:23:6: ... Location of nonblocking assignment (bits [3:0]) - 23 | array[0] <= array[0]; - | ^~~~~ +%Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:20:20: Unsupported: Blocking and non-blocking assignments to potentially overlapping bits of same packed variable: 't.array' + 20 | logic [1:0][3:0] array; + | ^~~~~ + t/t_order_blkandnblk_bad.v:22:24: ... Location of blocking assignment (bits [3:0]) + 22 | always_comb array[0] = i; + | ^ + t/t_order_blkandnblk_bad.v:24:25: ... Location of nonblocking assignment (bits [3:0]) + 24 | always @(posedge clk) array[0] <= array[0]; + | ^~~~~ ... For error description see https://verilator.org/warn/BLKANDNBLK?v=latest -%Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:28:6: Unsupported: Blocking and non-blocking assignments to same non-packed variable: 't.unpacked' - 28 | } unpacked; - | ^~~~~~~~ - t/t_order_blkandnblk_bad.v:30:16: ... Location of blocking assignment - 30 | always_comb unpacked.a = i; - | ^~~~~~~~ - t/t_order_blkandnblk_bad.v:33:6: ... Location of nonblocking assignment - 33 | unpacked.b <= unpacked.a; - | ^~~~~~~~ +%Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:29:5: Unsupported: Blocking and non-blocking assignments to same non-packed variable: 't.unpacked' + 29 | } unpacked; + | ^~~~~~~~ + t/t_order_blkandnblk_bad.v:31:15: ... Location of blocking assignment + 31 | always_comb unpacked.a = i; + | ^~~~~~~~ + t/t_order_blkandnblk_bad.v:33:25: ... Location of nonblocking assignment + 33 | always @(posedge clk) unpacked.b <= unpacked.a; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_order_blkandnblk_bad.v b/test_regress/t/t_order_blkandnblk_bad.v index b7f19e3bc..91544eac8 100644 --- a/test_regress/t/t_order_blkandnblk_bad.v +++ b/test_regress/t/t_order_blkandnblk_bad.v @@ -4,34 +4,34 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - o, - // Inputs - clk, i, idx - ); - input clk; - input [3:0] i; - input idx; - output [3:0] o; +module t ( /*AUTOARG*/ + // Outputs + o, + // Inputs + clk, + i, + idx +); + input clk; + input [3:0] i; + input idx; + output [3:0] o; - logic [1:0][3:0] array; + logic [1:0][3:0] array; - always_comb array[0] = i; + always_comb array[0] = i; - always @ (posedge clk) - array[0] <= array[0]; + always @(posedge clk) array[0] <= array[0]; - struct { - logic [3:0] a; - logic [3:0] b; - } unpacked; + struct { + logic [3:0] a; + logic [3:0] b; + } unpacked; - always_comb unpacked.a = i; + always_comb unpacked.a = i; - always @ (posedge clk) - unpacked.b <= unpacked.a; + always @(posedge clk) unpacked.b <= unpacked.a; - assign o = array[idx] + unpacked.a; + assign o = array[idx] + unpacked.a; endmodule diff --git a/test_regress/t/t_order_blkloopinit_bad.out b/test_regress/t/t_order_blkloopinit_bad.out index bff530c62..51bee947a 100644 --- a/test_regress/t/t_order_blkloopinit_bad.out +++ b/test_regress/t/t_order_blkloopinit_bad.out @@ -1,6 +1,6 @@ -%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:26:20: Unsupported: Non-blocking assignment to array with compound element type inside loop +%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:26:17: Unsupported: Non-blocking assignment to array with compound element type inside loop : ... note: In instance 't' - 26 | array2[i] <= null; - | ^~ + 26 | array2[i] <= null; + | ^~ ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_order_blkloopinit_bad.v b/test_regress/t/t_order_blkloopinit_bad.v index 671a78a60..1db649a12 100644 --- a/test_regress/t/t_order_blkloopinit_bad.v +++ b/test_regress/t/t_order_blkloopinit_bad.v @@ -7,24 +7,24 @@ // verilator lint_off MULTIDRIVEN module t (/*AUTOARG*/ - // Outputs - o, - // Inputs - clk - ); - input clk; - output int o; + // Outputs + o, + // Inputs + clk + ); + input clk; + output int o; - localparam SIZE = 65536; + localparam SIZE = 65536; - // Unsupported case 1: Array NBA to compund type - class C; endclass - C array2[SIZE]; - always @ (negedge clk) begin - o <= int'(array2[1] == null); - for (int i=0; i 0) begin - count = count + 1; - runner = runnerm1; - $write ("%m count=%d runner =%x\n",count, runnerm1); + reg [7:0] cyc; + initial cyc = 0; + always @(posedge clk) begin + //$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + c1_start <= 1'b0; end - end - -endmodule - -module seq_loop (/*AUTOARG*/ - // Outputs - count, - // Inputs - start - ); - input start; - output reg [31:0] count; initial count = 0; - - reg [31:0] runnerm1, runner; initial runner = 0; - - always @ (posedge start) begin - count = 0; - runner <= 3; - end - - always @ (/*AS*/runner) begin - runnerm1 = runner - 32'd1; - end - - always @ (/*AS*/runnerm1) begin - if (runner > 0) begin - count = count + 1; - runner <= runnerm1; - $write ("%m count=%d runner<=%x\n",count, runnerm1); + 8'd01: begin + c1_start <= 1'b1; end - end + default: ; + endcase + case (cyc) + 8'd02: begin + // On Verilator, we expect these comparisons to match exactly, + // confirming that our settle loop repeated the exact number of + // iterations we expect. No '$stop' should be called here, and we + // should reach the normal '$finish' below on the next cycle. + if (c1_count != 32'h3) $stop; + if (s2_count != 32'h3) $stop; + if (c3_count != 32'h3) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule + +module comb_loop ( /*AUTOARG*/ + // Outputs + count, + // Inputs + start +); + input start; + output reg [31:0] count = 0; + + reg [31:0] runnerm1, runner; + initial runner = 0; + + always @(posedge start) begin + count = 0; + runner = 3; + end + + always @( /*AS*/ runner) begin + runnerm1 = runner - 32'd1; + end + + always @( /*AS*/ runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner = runnerm1; + $write("%m count=%d runner =%x\n", count, runnerm1); + end + end + +endmodule + +module seq_loop ( /*AUTOARG*/ + // Outputs + count, + // Inputs + start +); + input start; + output reg [31:0] count; + initial count = 0; + + reg [31:0] runnerm1, runner; + initial runner = 0; + + always @(posedge start) begin + count = 0; + runner <= 3; + end + + always @( /*AS*/ runner) begin + runnerm1 = runner - 32'd1; + end + + always @( /*AS*/ runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner <= runnerm1; + $write("%m count=%d runner<=%x\n", count, runnerm1); + end + end endmodule diff --git a/test_regress/t/t_order_comboclkloop.v b/test_regress/t/t_order_comboclkloop.v index e99f19af3..d0c5392c1 100644 --- a/test_regress/t/t_order_comboclkloop.v +++ b/test_regress/t/t_order_comboclkloop.v @@ -4,66 +4,69 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // verilator lint_off COMBDLY - // verilator lint_off LATCH - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - // verilator lint_off MULTIDRIVEN + // verilator lint_off COMBDLY + // verilator lint_off LATCH + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN - reg [31:0] runnerm1, runner; initial runner = 0; - reg [31:0] runcount; initial runcount = 0; - reg [31:0] clkrun; initial clkrun = 0; - reg [31:0] clkcount; initial clkcount = 0; - always @ (/*AS*/runner) begin - runnerm1 = runner - 32'd1; - end - reg run0; - always @ (/*AS*/runnerm1) begin - if ((runner & 32'hf)!=0) begin - runcount = runcount + 1; - runner = runnerm1; - $write(" seq runcount=%0d runner =%0x\n", runcount, runnerm1); + reg [31:0] runnerm1, runner; + initial runner = 0; + reg [31:0] runcount; + initial runcount = 0; + reg [31:0] clkrun; + initial clkrun = 0; + reg [31:0] clkcount; + initial clkcount = 0; + always @( /*AS*/ runner) begin + runnerm1 = runner - 32'd1; + end + reg run0; + always @( /*AS*/ runnerm1) begin + if ((runner & 32'hf) != 0) begin + runcount = runcount + 1; + runner = runnerm1; + $write(" seq runcount=%0d runner =%0x\n", runcount, runnerm1); + end + run0 = (runner[8:4] != 0 && runner[3:0] == 0); + end + + always @(posedge run0) begin + // Do something that forces another combo run + clkcount <= clkcount + 1; + runner[8:4] <= runner[8:4] - 1; + runner[3:0] <= 3; + $write("[%0t] posedge runner=%0x\n", $time, runner); + end + + reg [7:0] cyc; + initial cyc = 0; + always @(posedge clk) begin + $write("[%0t] %x counts %0x %0x\n", $time, cyc, runcount, clkcount); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + runner <= 0; end - run0 = (runner[8:4]!=0 && runner[3:0]==0); - end - - always @ (posedge run0) begin - // Do something that forces another combo run - clkcount <= clkcount + 1; - runner[8:4] <= runner[8:4] - 1; - runner[3:0] <= 3; - $write ("[%0t] posedge runner=%0x\n", $time, runner); - end - - reg [7:0] cyc; initial cyc = 0; - always @ (posedge clk) begin - $write("[%0t] %x counts %0x %0x\n", $time, cyc, runcount, clkcount); - cyc <= cyc + 8'd1; - case (cyc) - 8'd00: begin - runner <= 0; - end - 8'd01: begin - runner <= 32'h35; - end - default: ; - endcase - case (cyc) - 8'd02: begin - if (runcount!=32'he) $stop; - if (clkcount!=32'h3) $stop; - end - 8'd03: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - end + 8'd01: begin + runner <= 32'h35; + end + default: ; + endcase + case (cyc) + 8'd02: begin + if (runcount != 32'he) $stop; + if (clkcount != 32'h3) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end endmodule diff --git a/test_regress/t/t_order_comboloop.v b/test_regress/t/t_order_comboloop.v index f9ce7bca8..6ea9099d5 100644 --- a/test_regress/t/t_order_comboloop.v +++ b/test_regress/t/t_order_comboloop.v @@ -4,54 +4,55 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc; initial cyc=1; +module t ( + input clk +); - // verilator lint_off LATCH - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - reg [31:0] runner; initial runner = 5; - reg [31:0] runnerm1; - reg [59:0] runnerq; - reg [89:0] runnerw; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin + integer cyc; + initial cyc = 1; + + // verilator lint_off LATCH + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + reg [31:0] runner; + initial runner = 5; + reg [31:0] runnerm1; + reg [59:0] runnerq; + reg [89:0] runnerw; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin `ifdef verilator - if (runner != 0) $stop; // Initial settlement failed + if (runner != 0) $stop; // Initial settlement failed `endif - end - if (cyc==2) begin - runner = 20; - runnerq = 60'h0; - runnerw = 90'h0; - end - if (cyc==3) begin - if (runner != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end end - end - - // This forms a "loop" where we keep going through the always till runner=0 - // This isn't "regular" beh code, but ensures our change detection is working properly - always @ (/*AS*/runner) begin - runnerm1 = runner - 32'd1; - end - - always @ (/*AS*/runnerm1) begin - if (runner > 0) begin - runner = runnerm1; - runnerq = runnerq - 60'd1; - runnerw = runnerw - 90'd1; - $write ("[%0t] runner=%d\n", $time, runner); + if (cyc == 2) begin + runner = 20; + runnerq = 60'h0; + runnerw = 90'h0; end - end + if (cyc == 3) begin + if (runner != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + // This forms a "loop" where we keep going through the always till runner=0 + // This isn't "regular" beh code, but ensures our change detection is working properly + always @( /*AS*/ runner) begin + runnerm1 = runner - 32'd1; + end + + always @( /*AS*/ runnerm1) begin + if (runner > 0) begin + runner = runnerm1; + runnerq = runnerq - 60'd1; + runnerw = runnerw - 90'd1; + $write("[%0t] runner=%d\n", $time, runner); + end + end endmodule diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v index bbd008556..7aeb2beac 100644 --- a/test_regress/t/t_order_doubleloop.v +++ b/test_regress/t/t_order_doubleloop.v @@ -4,98 +4,103 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc; initial cyc=1; +module t ( + input clk +); - // verilator lint_off LATCH - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - // verilator lint_off MULTIDRIVEN - // verilator lint_off BLKANDNBLK + integer cyc; + initial cyc = 1; - reg [31:0] comcnt; - reg [31:0] dlycnt; initial dlycnt=0; - reg [31:0] lastdlycnt; initial lastdlycnt = 0; + // verilator lint_off LATCH + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN + // verilator lint_off BLKANDNBLK - reg [31:0] comrun; initial comrun = 0; - reg [31:0] comrunm1; - reg [31:0] dlyrun; initial dlyrun = 0; - reg [31:0] dlyrunm1; - always @ (posedge clk) begin - $write("[%0t] cyc %d\n", $time,cyc); - cyc <= cyc + 1; - if (cyc==2) begin - // Test # of iters - lastdlycnt = 0; - comcnt = 0; - dlycnt <= 0; - end - if (cyc==3) begin - dlyrun <= 5; - dlycnt <= 0; - end - if (cyc==4) begin - comrun = 4; - end - end - always @ (negedge clk) begin - if (cyc==5) begin - $display("%d %d\n", dlycnt, comcnt); - if (dlycnt != 32'd5) $stop; - if (comcnt != 32'd19) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + reg [31:0] comcnt; + reg [31:0] dlycnt; + initial dlycnt = 0; + reg [31:0] lastdlycnt; + initial lastdlycnt = 0; - // This forms a "loop" where we keep going through the always till comrun=0 - reg runclk; initial runclk = 1'b0; - always @ (/*AS*/comrunm1 or dlycnt) begin - if (lastdlycnt != dlycnt) begin - comrun = 3; - $write ("[%0t] comrun=%0d start\n", $time, comrun); - end - else if (comrun > 0) begin - comrun = comrunm1; - if (comrunm1==1) begin - runclk = 1; - $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); - end - else $write ("[%0t] comrun=%0d\n", $time, comrun); - end - lastdlycnt = dlycnt; - end + reg [31:0] comrun; + initial comrun = 0; + reg [31:0] comrunm1; + reg [31:0] dlyrun; + initial dlyrun = 0; + reg [31:0] dlyrunm1; + always @(posedge clk) begin + $write("[%0t] cyc %d\n", $time, cyc); + cyc <= cyc + 1; + if (cyc == 2) begin + // Test # of iters + lastdlycnt = 0; + comcnt = 0; + dlycnt <= 0; + end + if (cyc == 3) begin + dlyrun <= 5; + dlycnt <= 0; + end + if (cyc == 4) begin + comrun = 4; + end + end + always @(negedge clk) begin + if (cyc == 5) begin + $display("%d %d\n", dlycnt, comcnt); + if (dlycnt != 32'd5) $stop; + if (comcnt != 32'd19) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @ (/*AS*/comrun) begin - if (comrun!=0) begin - comrunm1 = comrun - 32'd1; - comcnt = comcnt + 32'd1; - $write("[%0t] comcnt=%0d\n", $time,comcnt); + // This forms a "loop" where we keep going through the always till comrun=0 + reg runclk; + initial runclk = 1'b0; + always @( /*AS*/ comrunm1 or dlycnt) begin + if (lastdlycnt != dlycnt) begin + comrun = 3; + $write("[%0t] comrun=%0d start\n", $time, comrun); + end + else if (comrun > 0) begin + comrun = comrunm1; + if (comrunm1 == 1) begin + runclk = 1; + $write("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); end - end + else $write("[%0t] comrun=%0d\n", $time, comrun); + end + lastdlycnt = dlycnt; + end - // This forms a "loop" where we keep going through the always till dlyrun=0 - reg runclkrst; - always @ (posedge runclk) begin - runclkrst <= 1; - $write ("[%0t] runclk\n", $time); - if (dlyrun > 0) begin - dlyrun <= dlyrun - 32'd1; - dlycnt <= dlycnt + 32'd1; - $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); - end - end + always @( /*AS*/ comrun) begin + if (comrun != 0) begin + comrunm1 = comrun - 32'd1; + comcnt = comcnt + 32'd1; + $write("[%0t] comcnt=%0d\n", $time, comcnt); + end + end - always @* begin - if (runclkrst) begin - $write ("[%0t] runclk reset\n", $time); - runclkrst = 0; - runclk = 0; - end - end + // This forms a "loop" where we keep going through the always till dlyrun=0 + reg runclkrst; + always @(posedge runclk) begin + runclkrst <= 1; + $write("[%0t] runclk\n", $time); + if (dlyrun > 0) begin + dlyrun <= dlyrun - 32'd1; + dlycnt <= dlycnt + 32'd1; + $write("[%0t] dlyrun<=%0d\n", $time, dlyrun - 32'd1); + end + end + + always @* begin + if (runclkrst) begin + $write("[%0t] runclk reset\n", $time); + runclkrst = 0; + runclk = 0; + end + end endmodule diff --git a/test_regress/t/t_order_dpi_export_1.v b/test_regress/t/t_order_dpi_export_1.v index 85edfea8b..5f8c840c0 100644 --- a/test_regress/t/t_order_dpi_export_1.v +++ b/test_regress/t/t_order_dpi_export_1.v @@ -8,28 +8,28 @@ module testbench; - logic clk; + logic clk; - export "DPI-C" function set_clk; - function void set_clk(bit val); - clk = val; - endfunction; + export "DPI-C" function set_clk; + function void set_clk(bit val); + clk = val; + endfunction - // Downstream signal dependent on clk demonstrates scheduling issue. - // The '$c("1") &' ensures that dependent_clk does not get - // replaced with clk early and hence hiding the issue - wire dependent_clk = $c1("1") & clk; + // Downstream signal dependent on clk demonstrates scheduling issue. + // The '$c("1") &' ensures that dependent_clk does not get + // replaced with clk early and hence hiding the issue + wire dependent_clk = $c1("1") & clk; - int n = 0; + int n = 0; - always @(posedge dependent_clk) begin - $display("t=%t n=%d", $time, n); - if ($time != (2*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(posedge dependent_clk) begin + $display("t=%t n=%d", $time, n); + if ($time != (2 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_2.v b/test_regress/t/t_order_dpi_export_2.v index 4f2efe691..0949b5f27 100644 --- a/test_regress/t/t_order_dpi_export_2.v +++ b/test_regress/t/t_order_dpi_export_2.v @@ -6,37 +6,35 @@ // SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; // Top level input clock - bit other_clk; // Dependent clock set via DPI + bit other_clk; // Dependent clock set via DPI - export "DPI-C" function set_other_clk; - function void set_other_clk(bit val); - other_clk = val; - endfunction; + export "DPI-C" function set_other_clk; + function void set_other_clk(bit val); + other_clk = val; + endfunction + ; - bit even_other = 1; - import "DPI-C" context function void toggle_other_clk(bit val); - always @(posedge clk) begin - even_other <= ~even_other; - toggle_other_clk(even_other); - end + bit even_other = 1; + import "DPI-C" context function void toggle_other_clk(bit val); + always @(posedge clk) begin + even_other <= ~even_other; + toggle_other_clk(even_other); + end - int n = 0; + int n = 0; - always @(posedge other_clk) begin - $display("[%0t] n=%0d", $time, n); - if ($time != (4*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(posedge other_clk) begin + $display("[%0t] n=%0d", $time, n); + if ($time != (4 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_3.v b/test_regress/t/t_order_dpi_export_3.v index f326e690f..15daf2a17 100644 --- a/test_regress/t/t_order_dpi_export_3.v +++ b/test_regress/t/t_order_dpi_export_3.v @@ -6,50 +6,49 @@ // SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; // Top level input clock - bit other_clk; // Dependent clock set via DPI - bit third_clk; // Additional dependent clock set via DPI + bit other_clk; // Dependent clock set via DPI + bit third_clk; // Additional dependent clock set via DPI - export "DPI-C" function set_other_clk; - function void set_other_clk(bit val); - other_clk = val; - endfunction; + export "DPI-C" function set_other_clk; + function void set_other_clk(bit val); + other_clk = val; + endfunction + ; - export "DPI-C" function set_third_clk; - function void set_third_clk(bit val); - third_clk = val; - endfunction; + export "DPI-C" function set_third_clk; + function void set_third_clk(bit val); + third_clk = val; + endfunction + ; - bit even_other = 1; - import "DPI-C" context function void toggle_other_clk(bit val); - always @(posedge clk) begin - even_other <= ~even_other; - toggle_other_clk(even_other); - end + bit even_other = 1; + import "DPI-C" context function void toggle_other_clk(bit val); + always @(posedge clk) begin + even_other <= ~even_other; + toggle_other_clk(even_other); + end - bit even_third = 1; - import "DPI-C" context function void toggle_third_clk(bit val); - always @(posedge other_clk) begin - even_third <= ~even_third; - toggle_third_clk(even_third); - end + bit even_third = 1; + import "DPI-C" context function void toggle_third_clk(bit val); + always @(posedge other_clk) begin + even_third <= ~even_third; + toggle_third_clk(even_third); + end - int n = 0; + int n = 0; - always @(posedge third_clk) begin - $display("[%0t] n=%0d", $time, n); - if ($time != (8*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(posedge third_clk) begin + $display("[%0t] n=%0d", $time, n); + if ($time != (8 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_4.v b/test_regress/t/t_order_dpi_export_4.v index 808066a7d..b21ab24da 100644 --- a/test_regress/t/t_order_dpi_export_4.v +++ b/test_regress/t/t_order_dpi_export_4.v @@ -6,52 +6,49 @@ // SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; // Top level input clock - bit other_clk; // Dependent clock set via DPI - bit third_clk; // Additional dependent clock set via DPI + bit other_clk; // Dependent clock set via DPI + bit third_clk; // Additional dependent clock set via DPI - export "DPI-C" function set_other_clk; - function void set_other_clk(bit val); - other_clk = val; - endfunction; + export "DPI-C" function set_other_clk; + function void set_other_clk(bit val); + other_clk = val; + endfunction - export "DPI-C" function set_third_clk; - function void set_third_clk(bit val); - third_clk = val; - endfunction; + export "DPI-C" function set_third_clk; + function void set_third_clk(bit val); + third_clk = val; + endfunction - bit even_other = 1; - import "DPI-C" context function void toggle_other_clk(bit val); - always @(posedge clk) begin - even_other <= ~even_other; - toggle_other_clk(even_other); - end + bit even_other = 1; + import "DPI-C" context function void toggle_other_clk(bit val); + always @(posedge clk) begin + even_other <= ~even_other; + toggle_other_clk(even_other); + end - bit even_third = 1; - import "DPI-C" context function void toggle_third_clk(bit val); - always @(posedge other_clk) begin - even_third <= ~even_third; - toggle_third_clk(even_third); - end + bit even_third = 1; + import "DPI-C" context function void toggle_third_clk(bit val); + always @(posedge other_clk) begin + even_third <= ~even_third; + toggle_third_clk(even_third); + end - int n = 0; + int n = 0; - wire final_clk = $c1("1") & third_clk; + wire final_clk = $c1("1") & third_clk; - always @(posedge final_clk) begin - $display("[%0t] n=%0d", $time, n); - if ($time != (8*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(posedge final_clk) begin + $display("[%0t] n=%0d", $time, n); + if ($time != (8 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_5.v b/test_regress/t/t_order_dpi_export_5.v index f498708ab..e03319312 100644 --- a/test_regress/t/t_order_dpi_export_5.v +++ b/test_regress/t/t_order_dpi_export_5.v @@ -6,40 +6,37 @@ // SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; + int cnt = 0; + export "DPI-C" function set_cnt; + function void set_cnt(int val); + cnt = val; + endfunction - int cnt = 0; - export "DPI-C" function set_cnt; - function void set_cnt(int val); - cnt = val; - endfunction; - export "DPI-C" function get_cnt; - function int get_cnt(); - return cnt; - endfunction; + export "DPI-C" function get_cnt; + function int get_cnt(); + return cnt; + endfunction - always @(posedge clk) cnt += 1; + always @(posedge clk) cnt += 1; - // Downstream combinational signal dependent on both input clock and - // DPI export. - wire dependent_clk = cnt == 2; + // Downstream combinational signal dependent on both input clock and + // DPI export. + wire dependent_clk = cnt == 2; - int n = 0; + int n = 0; - always @(posedge dependent_clk) begin - $display("t=%t n=%d", $time, n); - if ($time != (8*n+3) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(posedge dependent_clk) begin + $display("t=%t n=%d", $time, n); + if ($time != (8 * n + 3) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_6.v b/test_regress/t/t_order_dpi_export_6.v index b9fa2a6fa..60e361575 100644 --- a/test_regress/t/t_order_dpi_export_6.v +++ b/test_regress/t/t_order_dpi_export_6.v @@ -6,43 +6,41 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; // Top level input clock - bit other_clk; // Dependent clock set via DPI + bit other_clk; // Dependent clock set via DPI - export "DPI-C" function set_other_clk; - function void set_other_clk(bit val); - other_clk = val; - endfunction; + export "DPI-C" function set_other_clk; + function void set_other_clk(bit val); + other_clk = val; + endfunction + ; - bit even_other = 1; - bit current_even_other = 1; - import "DPI-C" context function void toggle_other_clk(bit val); - always @(posedge clk) begin - even_other <= ~even_other; - current_even_other = even_other; - toggle_other_clk(even_other); - end + bit even_other = 1; + bit current_even_other = 1; + import "DPI-C" context function void toggle_other_clk(bit val); + always @(posedge clk) begin + even_other <= ~even_other; + current_even_other = even_other; + toggle_other_clk(even_other); + end - int n = 0; + int n = 0; - always @(edge other_clk) begin - // This always block needs to evaluate before the NBA to even_other - // above is committed, as setting clocks via the set_other_clk uses - // blocking assignment. - if (even_other !== current_even_other) $stop; - $display("[%0t] n=%0d", $time, n); - if ($time != (2*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(edge other_clk) begin + // This always block needs to evaluate before the NBA to even_other + // above is committed, as setting clocks via the set_other_clk uses + // blocking assignment. + if (even_other !== current_even_other) $stop; + $display("[%0t] n=%0d", $time, n); + if ($time != (2 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_7.v b/test_regress/t/t_order_dpi_export_7.v index bc6b5edcf..cfccc03ef 100644 --- a/test_regress/t/t_order_dpi_export_7.v +++ b/test_regress/t/t_order_dpi_export_7.v @@ -8,32 +8,33 @@ module testbench; - logic clk; - logic data; + logic clk; + logic data; - export "DPI-C" function set_inputs; - function void set_inputs(bit val); - clk = val; - data = val; - endfunction; + export "DPI-C" function set_inputs; + function void set_inputs(bit val); + clk = val; + data = val; + endfunction + ; - // This needs to be in the 'ico' region. Written with $c1 to prevent - // gate optimization. - wire invdata = $c1(1) ^ data; + // This needs to be in the 'ico' region. Written with $c1 to prevent + // gate optimization. + wire invdata = $c1(1) ^ data; - int n = 0; + int n = 0; - always @(edge clk) begin - // The combinational update needs to have take effect (in the 'ico' - // region), before this always block is executed - if (invdata != ~data) $stop; - $display("t=%t n=%d", $time, n); - if ($time != (1*n+1) * 500) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(edge clk) begin + // The combinational update needs to have take effect (in the 'ico' + // region), before this always block is executed + if (invdata != ~data) $stop; + $display("t=%t n=%d", $time, n); + if ($time != (1 * n + 1) * 500) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_dpi_export_8.v b/test_regress/t/t_order_dpi_export_8.v index b9493c710..c049ae0ca 100644 --- a/test_regress/t/t_order_dpi_export_8.v +++ b/test_regress/t/t_order_dpi_export_8.v @@ -6,43 +6,40 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module testbench( - /*AUTOARG*/ - // Inputs - clk - ); +module testbench ( + input clk +); - input clk; // Top level input clock + bit x = 0; - bit x = 0; + wire y = x & $c(1); - wire y = x & $c(1); + export "DPI-C" function set_x; + function void set_x(bit val); + x = val; + endfunction + ; - export "DPI-C" function set_x; - function void set_x(bit val); - x = val; - endfunction; + import "DPI-C" context function void call_set_x(bit val); - import "DPI-C" context function void call_set_x(bit val); + bit q = 0; + always @(posedge clk) q <= ~q; - bit q = 0; - always @(posedge clk) q <= ~q; + always @(edge q) call_set_x(q); - always @(edge q) call_set_x(q); + int n = 0; - int n = 0; - - always @(edge clk) begin - // This always block needs to evaluate before the NBA to even_other - // above is committed, as setting clocks via the set_other_clk uses - // blocking assignment. - $display("t=%t q=%d x=%d y=%d", $time, q, x, y); - if (y !== q) $stop; - if (n == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - n += 1; - end + always @(edge clk) begin + // This always block needs to evaluate before the NBA to even_other + // above is committed, as setting clocks via the set_other_clk uses + // blocking assignment. + $display("t=%t q=%d x=%d y=%d", $time, q, x, y); + if (y !== q) $stop; + if (n == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + n += 1; + end endmodule diff --git a/test_regress/t/t_order_first.v b/test_regress/t/t_order_first.v index 970a9c1dc..38b014af0 100644 --- a/test_regress/t/t_order_first.v +++ b/test_regress/t/t_order_first.v @@ -4,56 +4,57 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - fastclk - ); - input fastclk; +module t ( + input fastclk +); - t_netlist tnetlist - (.also_fastclk (fastclk), + t_netlist tnetlist ( + .also_fastclk(fastclk), /*AUTOINST*/ // Inputs - .fastclk (fastclk)); + .fastclk(fastclk) + ); endmodule -module t_netlist (/*AUTOARG*/ - // Inputs - fastclk, also_fastclk - ); +module t_netlist ( /*AUTOARG*/ + // Inputs + fastclk, + also_fastclk +); - // surefire lint_off ASWEMB + // surefire lint_off ASWEMB - input fastclk; - input also_fastclk; - integer _mode; initial _mode = 0; + input fastclk; + input also_fastclk; + integer _mode; + initial _mode = 0; - // This entire module should optimize to nearly nothing... + // This entire module should optimize to nearly nothing... - reg [4:0] a,a2,b,c,d,e; + reg [4:0] a, a2, b, c, d, e; - initial a=5'd1; + initial a = 5'd1; - always @ (posedge fastclk) begin - b <= a+5'd1; - c <= b+5'd1; // Better for ordering if this moves before previous statement - end + always @(posedge fastclk) begin + b <= a + 5'd1; + c <= b + 5'd1; // Better for ordering if this moves before previous statement + end - always @ (d or /*AS*/a or c) begin - e = d+5'd1; - a2 = a+5'd1; // This can be pulled out of the middle of the always - d = c+5'd1; // Better for ordering if this moves before previous statement - end + always @(d or /*AS*/ a or c) begin + e = d + 5'd1; + a2 = a + 5'd1; // This can be pulled out of the middle of the always + d = c + 5'd1; // Better for ordering if this moves before previous statement + end - always @ (posedge also_fastclk) begin - if (_mode==5) begin - if (a2 != 5'd2) $stop; - if (e != 5'd5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - _mode <= _mode + 1; - end + always @(posedge also_fastclk) begin + if (_mode == 5) begin + if (a2 != 5'd2) $stop; + if (e != 5'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + _mode <= _mode + 1; + end endmodule diff --git a/test_regress/t/t_order_loop_bad.v b/test_regress/t/t_order_loop_bad.v index 45749302d..ef7b559db 100644 --- a/test_regress/t/t_order_loop_bad.v +++ b/test_regress/t/t_order_loop_bad.v @@ -10,33 +10,31 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg ready; + reg ready; - initial begin - ready = 1'b0; - end + initial begin + ready = 1'b0; + end - always @(posedge ready) begin - if ((ready === 1'b1)) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge ready) begin + if ((ready === 1'b1)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge ready) begin - if ((ready === 1'b0)) begin - ready = 1'b1 ; - end - end - - always @(posedge clk) begin + always @(posedge ready) begin + if ((ready === 1'b0)) begin ready = 1'b1; - end + end + end + + always @(posedge clk) begin + ready = 1'b1; + end endmodule diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 3686c1504..40b2f4fa8 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -4,57 +4,55 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [31:0] in_a; + reg [31:0] in_b; - reg [31:0] in_a; - reg [31:0] in_b; + reg [31:0] e, f, g, h; - reg [31:0] e,f,g,h; + always @( /*AS*/ in_a) begin + e = in_a; + f = {e[15:0], e[31:16]}; + g = {f[15:0], f[31:16]}; + h = {g[15:0], g[31:16]}; + end - always @ (/*AS*/in_a) begin - e = in_a; - f = {e[15:0], e[31:16]}; - g = {f[15:0], f[31:16]}; - h = {g[15:0], g[31:16]}; - end + reg [31:0] e2, f2, g2, h2; + always @( /*AS*/ f2, g2) begin + h2 = {g2[15:0], g2[31:16]}; + g2 = {f2[15:0], f2[31:16]}; + end + always @( /*AS*/ in_a, e2) begin + f2 = {e2[15:0], e2[31:16]}; + e2 = in_a; + end - reg [31:0] e2,f2,g2,h2; - always @ (/*AS*/f2, g2) begin - h2 = {g2[15:0], g2[31:16]}; - g2 = {f2[15:0], f2[31:16]}; - end - always @ (/*AS*/in_a, e2) begin - f2 = {e2[15:0], e2[31:16]}; - e2 = in_a; - end - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x\n", cyc, h, h2); - if (h != h2) $stop; - if (cyc==1) begin - in_a <= 32'h89a14fab; - in_b <= 32'h7ab512fa; - end - if (cyc==2) begin - in_a <= 32'hf4c11a42; - in_b <= 32'h359967c6; - if (h != 32'h4fab89a1) $stop; - end - if (cyc==3) begin - if (h != 32'h1a42f4c1) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d %x %x\n", cyc, h, h2); + if (h != h2) $stop; + if (cyc == 1) begin + in_a <= 32'h89a14fab; + in_b <= 32'h7ab512fa; end - end + if (cyc == 2) begin + in_a <= 32'hf4c11a42; + in_b <= 32'h359967c6; + if (h != 32'h4fab89a1) $stop; + end + if (cyc == 3) begin + if (h != 32'h1a42f4c1) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v index e26c5d14e..e58ba9755 100644 --- a/test_regress/t/t_order_multidriven.v +++ b/test_regress/t/t_order_multidriven.v @@ -10,184 +10,173 @@ //bug634 module t ( - input i_clk_wr, - input i_clk_rd - ); + input i_clk_wr, + input i_clk_rd +); - wire wr$wen; - wire [7:0] wr$addr; - wire [7:0] wr$wdata; - wire [7:0] wr$rdata; + wire wr$wen; + wire [7:0] wr$addr; + wire [7:0] wr$wdata; + wire [7:0] wr$rdata; - wire rd$wen; - wire [7:0] rd$addr; - wire [7:0] rd$wdata; - wire [7:0] rd$rdata; + wire rd$wen; + wire [7:0] rd$addr; + wire [7:0] rd$wdata; + wire [7:0] rd$rdata; - wire clk_wr; - wire clk_rd; + wire clk_wr; + wire clk_rd; - `ifdef MULTI_CLK - assign clk_wr = i_clk_wr; - assign clk_rd = i_clk_rd; - `else - assign clk_wr = i_clk_wr; - assign clk_rd = i_clk_wr; - `endif +`ifdef MULTI_CLK + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_rd; +`else + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_wr; +`endif - FooWr u_wr ( - .i_clk ( clk_wr ), + FooWr u_wr ( + .i_clk(clk_wr), - .o_wen ( wr$wen ), - .o_addr ( wr$addr ), - .o_wdata ( wr$wdata ), - .i_rdata ( wr$rdata ) - ); + .o_wen(wr$wen), + .o_addr(wr$addr), + .o_wdata(wr$wdata), + .i_rdata(wr$rdata) + ); - FooRd u_rd ( - .i_clk ( clk_rd ), + FooRd u_rd ( + .i_clk(clk_rd), - .o_wen ( rd$wen ), - .o_addr ( rd$addr ), - .o_wdata ( rd$wdata ), - .i_rdata ( rd$rdata ) - ); + .o_wen(rd$wen), + .o_addr(rd$addr), + .o_wdata(rd$wdata), + .i_rdata(rd$rdata) + ); - FooMem u_mem ( - .iv_clk ( {clk_wr, clk_rd } ), - .iv_wen ( {wr$wen, rd$wen } ), - .iv_addr ( {wr$addr, rd$addr } ), - .iv_wdata ( {wr$wdata,rd$wdata} ), - .ov_rdata ( {wr$rdata,rd$rdata} ) - ); + FooMem u_mem ( + .iv_clk({clk_wr, clk_rd}), + .iv_wen({wr$wen, rd$wen}), + .iv_addr({wr$addr, rd$addr}), + .iv_wdata({wr$wdata, rd$wdata}), + .ov_rdata({wr$rdata, rd$rdata}) + ); endmodule // Memory Writer -module FooWr( - input i_clk, +module FooWr ( + input i_clk, - output o_wen, - output [7:0] o_addr, - output [7:0] o_wdata, - input [7:0] i_rdata - ); + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata +); - reg [7:0] cnt = 0; + reg [7:0] cnt = 0; - // Count [0,200] - always @( posedge i_clk ) - if ( cnt < 8'd50 ) - cnt <= cnt + 8'd1; + // Count [0,200] + always @(posedge i_clk) if (cnt < 8'd50) cnt <= cnt + 8'd1; - // Write addr in (10,30) if even - assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 ); - assign o_addr = cnt; - assign o_wdata = cnt; + // Write addr in (10,30) if even + assign o_wen = (cnt > 8'd10) && (cnt < 8'd30) && (cnt[0] == 1'b0); + assign o_addr = cnt; + assign o_wdata = cnt; endmodule // Memory Reader -module FooRd( - input i_clk, +module FooRd ( + input i_clk, - output o_wen, - output [7:0] o_addr, - output [7:0] o_wdata, - input [7:0] i_rdata - ); + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata +); - reg [7:0] cnt = 0; - reg [7:0] addr_r; - reg en_r; + reg [7:0] cnt = 0; + reg [7:0] addr_r; + reg en_r; - // Count [0,200] - always @( posedge i_clk ) - if ( cnt < 8'd200 ) - cnt <= cnt + 8'd1; + // Count [0,200] + always @(posedge i_clk) if (cnt < 8'd200) cnt <= cnt + 8'd1; - // Read data - assign o_wen = 0; - assign o_addr = cnt - 8'd100; + // Read data + assign o_wen = 0; + assign o_addr = cnt - 8'd100; - // Track issued read - always @( posedge i_clk ) - begin - addr_r <= o_addr; - en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 ); - end + // Track issued read + always @(posedge i_clk) begin + addr_r <= o_addr; + en_r <= (cnt > 8'd110) && (cnt < 8'd130) && (cnt[0] == 1'b0); + end - // Display to console 100 cycles after writer - always @( negedge i_clk ) - if ( en_r ) begin + // Display to console 100 cycles after writer + always @(negedge i_clk) + if (en_r) begin `ifdef TEST_VERBOSE - $display( "MEM[%x] == %x", addr_r, i_rdata ); + $display("MEM[%x] == %x", addr_r, i_rdata); `endif - if (addr_r != i_rdata) $stop; - end + if (addr_r != i_rdata) $stop; + end endmodule // Multi-port memory abstraction -module FooMem( - input [2 -1:0] iv_clk, - input [2 -1:0] iv_wen, - input [2*8-1:0] iv_addr, - input [2*8-1:0] iv_wdata, - output [2*8-1:0] ov_rdata - ); +module FooMem ( + input [2 -1:0] iv_clk, + input [2 -1:0] iv_wen, + input [2*8-1:0] iv_addr, + input [2*8-1:0] iv_wdata, + output [2*8-1:0] ov_rdata +); - FooMemImpl u_impl ( - .a_clk ( iv_clk [0*1+:1] ), - .a_wen ( iv_wen [0*1+:1] ), - .a_addr ( iv_addr [0*8+:8] ), - .a_wdata ( iv_wdata[0*8+:8] ), - .a_rdata ( ov_rdata[0*8+:8] ), + FooMemImpl u_impl ( + .a_clk(iv_clk[0*1+:1]), + .a_wen(iv_wen[0*1+:1]), + .a_addr(iv_addr[0*8+:8]), + .a_wdata(iv_wdata[0*8+:8]), + .a_rdata(ov_rdata[0*8+:8]), - .b_clk ( iv_clk [1*1+:1] ), - .b_wen ( iv_wen [1*1+:1] ), - .b_addr ( iv_addr [1*8+:8] ), - .b_wdata ( iv_wdata[1*8+:8] ), - .b_rdata ( ov_rdata[1*8+:8] ) - ); + .b_clk(iv_clk[1*1+:1]), + .b_wen(iv_wen[1*1+:1]), + .b_addr(iv_addr[1*8+:8]), + .b_wdata(iv_wdata[1*8+:8]), + .b_rdata(ov_rdata[1*8+:8]) + ); endmodule // Dual-Port L1 Memory Implementation -module FooMemImpl( - input a_clk, - input a_wen, - input [7:0] a_addr, - input [7:0] a_wdata, - output reg [7:0] a_rdata, +module FooMemImpl ( + input a_clk, + input a_wen, + input [7:0] a_addr, + input [7:0] a_wdata, + output reg [7:0] a_rdata, - input b_clk, - input b_wen, - input [7:0] b_addr, - input [7:0] b_wdata, - output reg [7:0] b_rdata - ); + input b_clk, + input b_wen, + input [7:0] b_addr, + input [7:0] b_wdata, + output reg [7:0] b_rdata +); - /* verilator lint_off MULTIDRIVEN */ - reg [7:0] mem[0:255]; - /* verilator lint_on MULTIDRIVEN */ + /* verilator lint_off MULTIDRIVEN */ + reg [7:0] mem[0:255]; + /* verilator lint_on MULTIDRIVEN */ - always @( posedge a_clk ) - if ( a_wen ) - mem[a_addr] <= a_wdata; + always @(posedge a_clk) if (a_wen) mem[a_addr] <= a_wdata; - always @( posedge b_clk ) - if ( b_wen ) - mem[b_addr] <= b_wdata; + always @(posedge b_clk) if (b_wen) mem[b_addr] <= b_wdata; - always @( posedge a_clk ) - a_rdata <= mem[a_addr]; + always @(posedge a_clk) a_rdata <= mem[a_addr]; - always @( posedge b_clk ) - b_rdata <= mem[b_addr]; + always @(posedge b_clk) b_rdata <= mem[b_addr]; endmodule diff --git a/test_regress/t/t_order_quad.v b/test_regress/t/t_order_quad.v index 1d23f39ba..b73003410 100644 --- a/test_regress/t/t_order_quad.v +++ b/test_regress/t/t_order_quad.v @@ -5,13 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 // See issue #762 -module t(a0, y); - input [3:0] a0; - // verilator lint_off UNOPTFLAT - output [44:0] y; +module t ( + a0, + y +); + input [3:0] a0; + // verilator lint_off UNOPTFLAT + output [44:0] y; - assign y[40] = 0; - assign y[30] = 0; - assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 }; + assign y[40] = 0; + assign y[30] = 0; + assign {y[44:41], y[39:31], y[29:0]} = { + 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 + }; endmodule diff --git a/test_regress/t/t_order_wireloop.v b/test_regress/t/t_order_wireloop.v index 2749a4033..bc33c0015 100644 --- a/test_regress/t/t_order_wireloop.v +++ b/test_regress/t/t_order_wireloop.v @@ -4,16 +4,16 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - bar - ); +module t ( /*AUTOARG*/ + // Outputs + bar +); - wire foo; - output bar; + wire foo; + output bar; - // Oh dear. - assign foo = bar; - assign bar = foo; + // Oh dear. + assign foo = bar; + assign bar = foo; endmodule diff --git a/test_regress/t/t_package.v b/test_regress/t/t_package.v index 99d559c4e..a8b5eb1b9 100644 --- a/test_regress/t/t_package.v +++ b/test_regress/t/t_package.v @@ -7,68 +7,67 @@ typedef int unit_type_t; function [3:0] unit_plusone(input [3:0] i); - unit_plusone = i+1; + unit_plusone = i + 1; endfunction package p; - typedef int package_type_t; - integer pi = 123; - function [3:0] plusone(input [3:0] i); - plusone = i+1; - endfunction + typedef int package_type_t; + integer pi = 123; + function [3:0] plusone(input [3:0] i); + plusone = i + 1; + endfunction endpackage package p2; - typedef int package2_type_t; - function [3:0] plustwo(input [3:0] i); - plustwo = i+2; - endfunction + typedef int package2_type_t; + function [3:0] plustwo(input [3:0] i); + plustwo = i + 2; + endfunction - function automatic bit realCompare(real r); - logic [63:0] b = $realtobits(r); - return b > 0; - endfunction + function automatic bit realCompare(real r); + logic [63:0] b = $realtobits(r); + return b > 0; + endfunction endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - unit_type_t vu; - $unit::unit_type_t vdu; - p::package_type_t vp; +module t ( + input clk +); - t2 t2 (); + unit_type_t vu; + $unit::unit_type_t vdu; + p::package_type_t vp; - initial begin - if (unit_plusone(1) !== 2) $stop; - if ($unit::unit_plusone(1) !== 2) $stop; - if (p::plusone(1) !== 2) $stop; - p::pi = 124; - if (p::pi !== 124) $stop; + t2 t2 (); - $write("*-* All Finished *-*\n"); - $finish; - end - always @ (posedge clk) begin - p::pi += 1; - if (p::pi < 124) $stop; - end + initial begin + if (unit_plusone(1) !== 2) $stop; + if ($unit::unit_plusone(1) !== 2) $stop; + if (p::plusone(1) !== 2) $stop; + p::pi = 124; + if (p::pi !== 124) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + always @(posedge clk) begin + p::pi += 1; + if (p::pi < 124) $stop; + end endmodule module t2; - import p::*; - import p2::plustwo; - import p2::realCompare; - import p2::package2_type_t; - package_type_t vp; - package2_type_t vp2; - initial begin - automatic bit x = realCompare(1.0); - if (plusone(1) !== 2) $stop; - if (plustwo(1) !== 3) $stop; - if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value - end + import p::*; + import p2::plustwo; + import p2::realCompare; + import p2::package2_type_t; + package_type_t vp; + package2_type_t vp2; + initial begin + automatic bit x = realCompare(1.0); + if (plusone(1) !== 2) $stop; + if (plustwo(1) !== 3) $stop; + if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value + end endmodule diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index a265e1861..0d49da467 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -7,27 +7,27 @@ // see bug491 package functions; - function real abs (real num); - abs = (num <0) ? -num : num; - endfunction - function real neg (real num); - return -abs(num); // Check package funcs can call package funcs - endfunction + function real abs(real num); + abs = (num < 0) ? -num : num; + endfunction + function real neg(real num); + return -abs(num); // Check package funcs can call package funcs + endfunction endpackage module t; - import functions::*; - localparam P = 1; - generate - if (P == 1) begin - initial begin - if (abs(-2.1) != 2.1) $stop; - if (abs(2.2) != 2.2) $stop; - if (neg(-2.1) != -2.1) $stop; - if (neg(2.2) != -2.2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + import functions::*; + localparam P = 1; + generate + if (P == 1) begin + initial begin + if (abs(-2.1) != 2.1) $stop; + if (abs(2.2) != 2.2) $stop; + if (neg(-2.1) != -2.1) $stop; + if (neg(2.2) != -2.2) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v index ad24d2901..b05acf0b5 100644 --- a/test_regress/t/t_package_ddecl.v +++ b/test_regress/t/t_package_ddecl.v @@ -6,26 +6,26 @@ // See issue #474 package functions; - localparam LP_PACK = 512; - localparam LP_PACK_AND_MOD = 19; - task check_param; - $display("In %m\n"); // "In functions::check_param" - if (LP_PACK_AND_MOD != 19) $stop; - endtask + localparam LP_PACK = 512; + localparam LP_PACK_AND_MOD = 19; + task check_param; + $display("In %m\n"); // "In functions::check_param" + if (LP_PACK_AND_MOD != 19) $stop; + endtask endpackage module t; - // synthesis translate off - import functions::*; - // synthesis translate on - localparam LP_PACK_AND_MOD = 20; - initial begin - // verilator lint_off STMTDLY - #10; - // verilator lint_on STMTDLY - if (LP_PACK_AND_MOD != 20) $stop; - check_param(); - $write("*-* All Finished *-*\n"); - $finish; - end + // synthesis translate off + import functions::*; + // synthesis translate on + localparam LP_PACK_AND_MOD = 20; + initial begin + // verilator lint_off STMTDLY + #10; + // verilator lint_on STMTDLY + if (LP_PACK_AND_MOD != 20) $stop; + check_param(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_dimport.v b/test_regress/t/t_package_dimport.v index 0e3cc60b7..080880798 100644 --- a/test_regress/t/t_package_dimport.v +++ b/test_regress/t/t_package_dimport.v @@ -5,60 +5,56 @@ // SPDX-License-Identifier: CC0-1.0 package defs; - function automatic integer max; - input integer a; - input integer b; - max = (a > b) ? a : b; - endfunction + function automatic integer max; + input integer a; + input integer b; + max = (a > b) ? a : b; + endfunction - function automatic integer log2; - input integer value; - value = value >> 1; - for (log2 = 0; value > 0; log2 = log2 + 1) - value = value >> 1; - endfunction + function automatic integer log2; + input integer value; + value = value >> 1; + for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1; + endfunction - function automatic integer ceil_log2; - input integer value; - value = value - 1; - for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) - value = value >> 1; - endfunction + function automatic integer ceil_log2; + input integer value; + value = value - 1; + for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) value = value >> 1; + endfunction endpackage -module sub(); +module sub (); - import defs::*; + import defs::*; - parameter RAND_NUM_MAX = ""; + parameter RAND_NUM_MAX = ""; - localparam DATA_RANGE = RAND_NUM_MAX + 1; - localparam DATA_WIDTH = ceil_log2(DATA_RANGE); - localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); + localparam DATA_RANGE = RAND_NUM_MAX + 1; + localparam DATA_WIDTH = ceil_log2(DATA_RANGE); + localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); endmodule module t; - import defs::*; + import defs::*; - parameter WHICH = 0; - parameter MAX_COUNT = 10; + parameter WHICH = 0; + parameter MAX_COUNT = 10; - localparam MAX_EXPONENT = log2(MAX_COUNT); - localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); + localparam MAX_EXPONENT = log2(MAX_COUNT); + localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); - generate - if (WHICH == 1) - begin : which_true - sub sub_true(); - defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; - end - else - begin : which_false - sub sub_false(); - defparam sub_false.RAND_NUM_MAX = MAX_COUNT; - end - endgenerate + generate + if (WHICH == 1) begin : which_true + sub sub_true (); + defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; + end + else begin : which_false + sub sub_false (); + defparam sub_false.RAND_NUM_MAX = MAX_COUNT; + end + endgenerate endmodule diff --git a/test_regress/t/t_package_dot.v b/test_regress/t/t_package_dot.v index 61338d899..f478e776f 100644 --- a/test_regress/t/t_package_dot.v +++ b/test_regress/t/t_package_dot.v @@ -5,21 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef struct packed { - logic [3:0] msk; - logic [3:0] dat; - } STR_t; -endpackage; + typedef struct packed { + logic [3:0] msk; + logic [3:0] dat; + } STR_t; +endpackage +; package csr_pkg; - typedef pkg::STR_t reg_t; - localparam reg_t REG_RST = 8'h34; + typedef pkg::STR_t reg_t; + localparam reg_t REG_RST = 8'h34; endpackage module t; - initial begin - if (csr_pkg::REG_RST.msk != 4'h3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (csr_pkg::REG_RST.msk != 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_dup_bad.out b/test_regress/t/t_package_dup_bad.out index 916b8bf19..5b7e0f6ef 100644 --- a/test_regress/t/t_package_dup_bad.out +++ b/test_regress/t/t_package_dup_bad.out @@ -6,14 +6,14 @@ | ^~~ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. -%Warning-MODDUP: t/t_package_dup_bad.v:19:9: Duplicate declaration of package: 'pkg' - 19 | package pkg; +%Warning-MODDUP: t/t_package_dup_bad.v:21:9: Duplicate declaration of package: 'pkg' + 21 | package pkg; | ^~~ t/t_package_dup_bad.v:7:9: ... Location of original declaration 7 | package pkg; | ^~~ -%Warning-MODDUP: t/t_package_dup_bad.v:22:9: Duplicate declaration of package: 'pkg' - 22 | package pkg; +%Warning-MODDUP: t/t_package_dup_bad.v:24:9: Duplicate declaration of package: 'pkg' + 24 | package pkg; | ^~~ t/t_package_dup_bad.v:7:9: ... Location of original declaration 7 | package pkg; diff --git a/test_regress/t/t_package_dup_bad.v b/test_regress/t/t_package_dup_bad.v index aef6858be..6c93244d3 100644 --- a/test_regress/t/t_package_dup_bad.v +++ b/test_regress/t/t_package_dup_bad.v @@ -5,15 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - localparam PARAM = 10; + localparam PARAM = 10; endpackage package pkg; - localparam PARAM = 10; + localparam PARAM = 10; endpackage -module sub import pkg::*; - #( ) (); +module sub + import pkg::*; +#( +) (); endmodule package pkg; @@ -23,9 +25,9 @@ package pkg; endpackage module t; - sub sub (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + sub sub (); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_enum.v b/test_regress/t/t_package_enum.v index 1e89369e1..5dcd501f1 100644 --- a/test_regress/t/t_package_enum.v +++ b/test_regress/t/t_package_enum.v @@ -5,33 +5,32 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef enum bit [1:0] - { - E__NOT = 2'b00, - E__VAL = 2'b11 - } E_t; + typedef enum bit [1:0] { + E__NOT = 2'b00, + E__VAL = 2'b11 + } E_t; endpackage module t; - reg [1:0] ttype; - reg m; + reg [1:0] ttype; + reg m; - enum bit [1:0] { LOCAL } l; + enum bit [1:0] {LOCAL} l; - always @ (m or 1'b0 or LOCAL) begin - // Don't complain about constants in sensitivity lists - end + always @(m or 1'b0 or LOCAL) begin + // Don't complain about constants in sensitivity lists + end - initial begin - ttype = pkg::E__NOT; - m = (ttype == pkg::E__VAL); - if (m != 1'b0) $stop; + initial begin + ttype = pkg::E__NOT; + m = (ttype == pkg::E__VAL); + if (m != 1'b0) $stop; - ttype = pkg::E__VAL; - m = (ttype == pkg::E__VAL); - if (m != 1'b1) $stop; + ttype = pkg::E__VAL; + m = (ttype == pkg::E__VAL); + if (m != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_export.v b/test_regress/t/t_package_export.v index 99c79f289..8e6c305c9 100644 --- a/test_regress/t/t_package_export.v +++ b/test_regress/t/t_package_export.v @@ -7,65 +7,64 @@ // See issue #591 package pkg1; - parameter PARAM2 = 16; - parameter PARAM3 = 16; + parameter PARAM2 = 16; + parameter PARAM3 = 16; endpackage : pkg1 package pkg10; - import pkg1::*; - import pkg1::*; // Ignore if already + import pkg1::*; + import pkg1::*; // Ignore if already `ifdef T_PACKAGE_EXPORT - export *::*; // Not supported on all simulators + export * ::*; // Not supported on all simulators `endif - parameter PARAM1 = 8; + parameter PARAM1 = 8; endpackage package pkg11; - import pkg10::*; + import pkg10::*; endpackage package pkg20; - import pkg1::*; + import pkg1::*; `ifdef T_PACKAGE_EXPORT - export pkg1::*; + export pkg1::*; `endif - parameter PARAM1 = 8; + parameter PARAM1 = 8; endpackage package pkg21; - import pkg20::*; + import pkg20::*; endpackage package pkg30; - import pkg1::*; + import pkg1::*; `ifdef T_PACKAGE_EXPORT - export pkg1::PARAM2; - export pkg1::PARAM3; + export pkg1::PARAM2; export pkg1::PARAM3; `endif `ifdef T_PACKAGE_EXPORT_BAD - export pkg1::BAD_DOES_NOT_EXIST; + export pkg1::BAD_DOES_NOT_EXIST; `endif - parameter PARAM1 = 8; + parameter PARAM1 = 8; endpackage package pkg31; - import pkg30::*; + import pkg30::*; endpackage module t; - reg [pkg11::PARAM1 : 0] bus11; - reg [pkg11::PARAM2 : 0] bus12; - reg [pkg11::PARAM3 : 0] bus13; + reg [pkg11::PARAM1 : 0] bus11; + reg [pkg11::PARAM2 : 0] bus12; + reg [pkg11::PARAM3 : 0] bus13; - reg [pkg21::PARAM1 : 0] bus21; - reg [pkg21::PARAM2 : 0] bus22; - reg [pkg21::PARAM3 : 0] bus23; + reg [pkg21::PARAM1 : 0] bus21; + reg [pkg21::PARAM2 : 0] bus22; + reg [pkg21::PARAM3 : 0] bus23; - reg [pkg31::PARAM1 : 0] bus31; - reg [pkg31::PARAM2 : 0] bus32; - reg [pkg31::PARAM3 : 0] bus33; + reg [pkg31::PARAM1 : 0] bus31; + reg [pkg31::PARAM2 : 0] bus32; + reg [pkg31::PARAM3 : 0] bus33; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_export_bad.out b/test_regress/t/t_package_export_bad.out index 7cfde4f39..86bd27d80 100644 --- a/test_regress/t/t_package_export_bad.out +++ b/test_regress/t/t_package_export_bad.out @@ -1,29 +1,29 @@ -%Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST' - 45 | export pkg1::BAD_DOES_NOT_EXIST; - | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_package_export.v:44:16: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST' + 44 | export pkg1::BAD_DOES_NOT_EXIST; + | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_package_export.v:56:16: Can't find definition of scope/variable/func: 'PARAM2' +%Error: t/t_package_export.v:55:15: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' - 56 | reg [pkg11::PARAM2 : 0] bus12; - | ^~~~~~ -%Error: t/t_package_export.v:57:16: Can't find definition of scope/variable/func: 'PARAM3' + 55 | reg [pkg11::PARAM2 : 0] bus12; + | ^~~~~~ +%Error: t/t_package_export.v:56:15: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' - 57 | reg [pkg11::PARAM3 : 0] bus13; - | ^~~~~~ -%Error: t/t_package_export.v:60:16: Can't find definition of scope/variable/func: 'PARAM2' + 56 | reg [pkg11::PARAM3 : 0] bus13; + | ^~~~~~ +%Error: t/t_package_export.v:59:15: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' - 60 | reg [pkg21::PARAM2 : 0] bus22; - | ^~~~~~ -%Error: t/t_package_export.v:61:16: Can't find definition of scope/variable/func: 'PARAM3' + 59 | reg [pkg21::PARAM2 : 0] bus22; + | ^~~~~~ +%Error: t/t_package_export.v:60:15: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' - 61 | reg [pkg21::PARAM3 : 0] bus23; - | ^~~~~~ -%Error: t/t_package_export.v:64:16: Can't find definition of scope/variable/func: 'PARAM2' + 60 | reg [pkg21::PARAM3 : 0] bus23; + | ^~~~~~ +%Error: t/t_package_export.v:63:15: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' - 64 | reg [pkg31::PARAM2 : 0] bus32; - | ^~~~~~ -%Error: t/t_package_export.v:65:16: Can't find definition of scope/variable/func: 'PARAM3' + 63 | reg [pkg31::PARAM2 : 0] bus32; + | ^~~~~~ +%Error: t/t_package_export.v:64:15: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' - 65 | reg [pkg31::PARAM3 : 0] bus33; - | ^~~~~~ + 64 | reg [pkg31::PARAM3 : 0] bus33; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad2.out b/test_regress/t/t_package_export_bad2.out index 6ff1b4848..5260d9f6e 100644 --- a/test_regress/t/t_package_export_bad2.out +++ b/test_regress/t/t_package_export_bad2.out @@ -1,5 +1,5 @@ -%Error: t/t_package_export_bad2.v:12:18: Export package not found: 'Pkg1b' - 12 | export Pkg1b::*; - | ^ +%Error: t/t_package_export_bad2.v:12:17: Export package not found: 'Pkg1b' + 12 | export Pkg1b::*; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad2.v b/test_regress/t/t_package_export_bad2.v index 7c7a305ea..9346ea5f9 100644 --- a/test_regress/t/t_package_export_bad2.v +++ b/test_regress/t/t_package_export_bad2.v @@ -8,8 +8,8 @@ package Pkg1; endpackage package Pkg10; - // verilator lint_off PKGNODECL - export Pkg1b::*; // BAD - typo in package name + // verilator lint_off PKGNODECL + export Pkg1b::*; // BAD - typo in package name endpackage module t; diff --git a/test_regress/t/t_package_identifier_bad.out b/test_regress/t/t_package_identifier_bad.out index a19e9a417..a11abddca 100644 --- a/test_regress/t/t_package_identifier_bad.out +++ b/test_regress/t/t_package_identifier_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_package_identifier_bad.v:15:20: Package/class for ':: reference' not found: 'Bar' - 15 | int baz = Foo::Bar::baz; - | ^~~ +%Error: t/t_package_identifier_bad.v:15:18: Package/class for ':: reference' not found: 'Bar' + 15 | int baz = Foo::Bar::baz; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_package_identifier_bad.v b/test_regress/t/t_package_identifier_bad.v index d3e1605f3..d1d174d7b 100644 --- a/test_regress/t/t_package_identifier_bad.v +++ b/test_regress/t/t_package_identifier_bad.v @@ -8,9 +8,9 @@ package Foo; endpackage package Bar; - static int baz; + static int baz; endpackage module t; - int baz = Foo::Bar::baz; + int baz = Foo::Bar::baz; endmodule diff --git a/test_regress/t/t_package_import_bad2.out b/test_regress/t/t_package_import_bad2.out index 584c7d98e..42e7a0ef3 100644 --- a/test_regress/t/t_package_import_bad2.out +++ b/test_regress/t/t_package_import_bad2.out @@ -1,5 +1,5 @@ -%Error: t/t_package_import_bad2.v:12:11: Import package not found: 'Pkg1b' - 12 | import Pkg1b::*; - | ^~~~~ +%Error: t/t_package_import_bad2.v:12:10: Import package not found: 'Pkg1b' + 12 | import Pkg1b::*; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_package_import_bad2.v b/test_regress/t/t_package_import_bad2.v index e080d0c29..bbd01e4b5 100644 --- a/test_regress/t/t_package_import_bad2.v +++ b/test_regress/t/t_package_import_bad2.v @@ -8,8 +8,8 @@ package Pkg1; endpackage package Pkg10; - // verilator lint_off PKGNODECL - import Pkg1b::*; // BAD - typo in package name + // verilator lint_off PKGNODECL + import Pkg1b::*; // BAD - typo in package name endpackage module t; diff --git a/test_regress/t/t_package_local_bad.out b/test_regress/t/t_package_local_bad.out index 755ad04bc..9a06c1916 100644 --- a/test_regress/t/t_package_local_bad.out +++ b/test_regress/t/t_package_local_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_package_local_bad.v:9:16: Illegal 'local::' outside 'randomize() with' (IEEE 1800-2023 18.7.1) - 9 | $display(local::x); - | ^~~~~ +%Error: t/t_package_local_bad.v:9:14: Illegal 'local::' outside 'randomize() with' (IEEE 1800-2023 18.7.1) + 9 | $display(local:: x); + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_package_local_bad.v b/test_regress/t/t_package_local_bad.v index 24a574858..a7efc0c9b 100644 --- a/test_regress/t/t_package_local_bad.v +++ b/test_regress/t/t_package_local_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $display(local::x); - $finish; - end + initial begin + $display(local:: x); + $finish; + end endmodule diff --git a/test_regress/t/t_package_param.v b/test_regress/t/t_package_param.v index 736f58142..3be6c3a2a 100644 --- a/test_regress/t/t_package_param.v +++ b/test_regress/t/t_package_param.v @@ -9,31 +9,29 @@ // SPDX-License-Identifier: CC0-1.0 package defs; - parameter NUMBER = 8; - localparam NUM = NUMBER; + parameter NUMBER = 8; + localparam NUM = NUMBER; endpackage -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - import defs::*; + import defs::*; - // This also fails if we use localparam - parameter NUM = 32; + // This also fails if we use localparam + parameter NUM = 32; - // Check we have the right definition - always @(posedge clk) begin - if (NUM == 32) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end + // Check we have the right definition + always @(posedge clk) begin + if (NUM == 32) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v index 8218dd4bc..8c559bfbc 100644 --- a/test_regress/t/t_package_twodeep.v +++ b/test_regress/t/t_package_twodeep.v @@ -7,22 +7,22 @@ // See issue #591 package pkg2; - parameter PARAM2 = 16; -endpackage // pkg2 + parameter PARAM2 = 16; +endpackage // pkg2 package pkg1; - import pkg2::*; - parameter PARAM1 = 8; -endpackage // pkg1 + import pkg2::*; + parameter PARAM1 = 8; +endpackage // pkg1 module t - import pkg1::*; // Test SV 2012 import format + import pkg1::*; // Test SV 2012 import format ; - reg [PARAM1:0] bus1; + reg [PARAM1:0] bus1; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_package_using_dollar_unit.v b/test_regress/t/t_package_using_dollar_unit.v index f7f987aa0..9bd42cbdf 100644 --- a/test_regress/t/t_package_using_dollar_unit.v +++ b/test_regress/t/t_package_using_dollar_unit.v @@ -4,61 +4,60 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on typedef int my_type; class my_class; - static int a = 1; + static int a = 1; endclass function int get_val; - return 2; + return 2; endfunction package my_pkg; - int my_type_size = $bits(my_type); - int my_class_a = my_class::a; - int get_val_result = get_val(); + int my_type_size = $bits(my_type); + int my_class_a = my_class::a; + int get_val_result = get_val(); endpackage package overwriting_pkg; - typedef logic [9:0] my_type; + typedef logic [9:0] my_type; - class my_class; - static int a = 2; - endclass + class my_class; + static int a = 2; + endclass - function int get_val; - return 3; - endfunction + function int get_val; + return 3; + endfunction - int my_type_size = $bits(my_type); - int my_class_a = my_class::a; - int get_val_result = get_val(); + int my_type_size = $bits(my_type); + int my_class_a = my_class::a; + int get_val_result = get_val(); endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; - int cyc; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 2) begin - `checkh(my_pkg::my_type_size, 32); - `checkh(my_pkg::my_class_a, 1); - `checkh(my_pkg::get_val_result, 2); - `checkh(overwriting_pkg::my_type_size, 10); - `checkh(overwriting_pkg::my_class_a, 2); - `checkh(overwriting_pkg::get_val_result, 3); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + `checkh(my_pkg::my_type_size, 32); + `checkh(my_pkg::my_class_a, 1); + `checkh(my_pkg::get_val_result, 2); + `checkh(overwriting_pkg::my_type_size, 10); + `checkh(overwriting_pkg::my_class_a, 2); + `checkh(overwriting_pkg::get_val_result, 3); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_package_verb.v b/test_regress/t/t_package_verb.v index 63ad0c36b..2c449c253 100644 --- a/test_regress/t/t_package_verb.v +++ b/test_regress/t/t_package_verb.v @@ -6,18 +6,20 @@ // bug474 package verb_pkg; - typedef enum int {VERB_I, - VERB_W} Verb_t; - Verb_t verb = VERB_I; - string message = " "; + typedef enum int { + VERB_I, + VERB_W + } Verb_t; + Verb_t verb = VERB_I; + string message = " "; endpackage module t; - import verb_pkg::*; + import verb_pkg::*; - string message = "*x*"; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + string message = "*x*"; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_packed_concat.v b/test_regress/t/t_packed_concat.v index 036be30c1..ddcdbd04f 100644 --- a/test_regress/t/t_packed_concat.v +++ b/test_regress/t/t_packed_concat.v @@ -6,19 +6,19 @@ module t; - typedef logic [15:0] count_t; - typedef bit [31:0] bit_int_t; + typedef logic [15:0] count_t; + typedef bit [31:0] bit_int_t; - // bug1627 - localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; - localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + // bug1627 + localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - initial begin - if (count_bits[0] != 16) $stop; - if (count_bits[1] != 16) $stop; - if (count_bitsc[0] != 16) $stop; - if (count_bitsc[1] != 16) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (count_bits[0] != 16) $stop; + if (count_bits[1] != 16) $stop; + if (count_bitsc[0] != 16) $stop; + if (count_bitsc[1] != 16) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_packed_concat_bad.out b/test_regress/t/t_packed_concat_bad.out index bb7829997..6c1cb72df 100644 --- a/test_regress/t/t_packed_concat_bad.out +++ b/test_regress/t/t_packed_concat_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:12:47: Unsized numbers/parameters not allowed in replications. +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:12:46: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 12 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; - | ^~~~~ + 12 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:46: Unsized numbers/parameters not allowed in concatenations. +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:45: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' - 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - | ^~~~~ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:60: Unsized numbers/parameters not allowed in replications. + 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + | ^~~~~ +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:59: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - | ^ + 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_packed_concat_bad.v b/test_regress/t/t_packed_concat_bad.v index 80e04362b..7b8273398 100644 --- a/test_regress/t/t_packed_concat_bad.v +++ b/test_regress/t/t_packed_concat_bad.v @@ -6,18 +6,18 @@ module t; - typedef logic [15:0] count_t; - typedef bit [31:0] bit_int_t; + typedef logic [15:0] count_t; + typedef bit [31:0] bit_int_t; - localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; - localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - initial begin - if (count_bits[0] != 16) $stop; - if (count_bits[1] != 16) $stop; - if (count_bitsc[0] != 16) $stop; - if (count_bitsc[1] != 16) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (count_bits[0] != 16) $stop; + if (count_bits[1] != 16) $stop; + if (count_bitsc[0] != 16) $stop; + if (count_bitsc[1] != 16) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index 0bb9354b1..b1708d07f 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -4,82 +4,83 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - parameter PAR = 3; +module t ( + input clk +); - m1 #(PAR) m1(); - m3 #(PAR) m3(); - mnooverride #(10) mno(); - mreal #1.2 mr(); + parameter PAR = 3; - input clk; - integer cyc=1; - reg [4:0] bitsel; + m1 #(PAR) m1 (); + m3 #(PAR) m3 (); + mnooverride #(10) mno (); + mreal #1.2 mr (); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - bitsel = 0; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 1; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 2; - if (PAR[bitsel]!==1'b0) $stop; - end - if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + integer cyc = 1; + reg [4:0] bitsel; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + bitsel = 0; + if (PAR[bitsel] !== 1'b1) $stop; + bitsel = 1; + if (PAR[bitsel] !== 1'b1) $stop; + bitsel = 2; + if (PAR[bitsel] !== 1'b0) $stop; + end + if (cyc == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module m1; - localparam PAR1MINUS1 = PAR1DUP-2-1; - localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly - parameter PAR1 = 0; - m2 #(PAR1MINUS1) m2 (); + localparam PAR1MINUS1 = PAR1DUP - 2 - 1; + localparam PAR1DUP = PAR1 + 2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #(PAR1MINUS1) m2 (); - // Packed arrays - localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 }; - initial if (PACKED_PARAM != 8'h36) $stop; + // Packed arrays + localparam [1:0][3:0] PACKED_PARAM = {4'h3, 4'h6}; + initial if (PACKED_PARAM != 8'h36) $stop; endmodule // See issue #810 -module m2 #(/*parameter*/ integer PAR2 = 10); - initial begin - $display("%x",PAR2); - if (PAR2 !== 2) $stop; - end +module m2 #( /*parameter*/ + integer PAR2 = 10 +); + initial begin + $display("%x", PAR2); + if (PAR2 !== 2) $stop; + end endmodule module m3; - localparam LOC = 13; - parameter PAR = 10; - initial begin - $display("%x %x",LOC,PAR); - if (LOC !== 13) $stop; - if (PAR !== 3) $stop; - end + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x", LOC, PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end endmodule module mnooverride; - localparam LOC = 13; - parameter PAR = 10; - initial begin - $display("%x %x",LOC,PAR); - if (LOC !== 13) $stop; - if (PAR !== 10) $stop; - end + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x", LOC, PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end endmodule module mreal; - parameter real REAL = 99.99; - initial begin - $display("%f", REAL); - if (REAL !== 1.2) $stop; - end + parameter real REAL = 99.99; + initial begin + $display("%f", REAL); + if (REAL !== 1.2) $stop; + end endmodule diff --git a/test_regress/t/t_param_array.v b/test_regress/t/t_param_array.v index e321928d0..826a9f080 100644 --- a/test_regress/t/t_param_array.v +++ b/test_regress/t/t_param_array.v @@ -6,82 +6,83 @@ module t; - typedef enum int { - PADTYPE_DEFAULT = 32'd0, - PADTYPE_GPIO, - PADTYPE_VDD, - PADTYPE_GND - } t_padtype; + typedef enum int { + PADTYPE_DEFAULT = 32'd0, + PADTYPE_GPIO, + PADTYPE_VDD, + PADTYPE_GND + } t_padtype; - localparam int STR_PINID [0:15] - = '{ + // verilog_format: off + localparam int STR_PINID [0:15] = '{ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" }; + // verilog_format: on - typedef struct packed { - t_padtype padtype; - int aux; - } t_pin_descriptor; + typedef struct packed { + t_padtype padtype; + int aux; + } t_pin_descriptor; - localparam t_pin_descriptor - PINOUT[ 1: 6] - = '{ - '{default:0, padtype:PADTYPE_GPIO, aux:1}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_VDD}, - '{default:0, padtype:PADTYPE_GND} - }; + localparam t_pin_descriptor PINOUT[1:6] = '{ + '{default: 0, padtype: PADTYPE_GPIO, aux: 1}, + '{default: 0, padtype: PADTYPE_GPIO}, + '{default: 0, padtype: PADTYPE_GPIO}, + '{default: 0, padtype: PADTYPE_GPIO}, + '{default: 0, padtype: PADTYPE_VDD}, + '{default: 0, padtype: PADTYPE_GND} + }; - localparam int PINOUT_SIZE = 6; - localparam int PINOUT_WA[1:PINOUT_SIZE][3] - = '{ - '{0, PADTYPE_GPIO, 0}, - '{1, PADTYPE_GPIO, 0}, - '{2, PADTYPE_GPIO, 0}, - '{5, PADTYPE_GPIO, 0}, - '{6, PADTYPE_VDD, 0}, - '{8, PADTYPE_GND , 0} - }; + localparam int PINOUT_SIZE = 6; + localparam int PINOUT_WA[1:PINOUT_SIZE][3] = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND, 0} + }; - const int pinout_static_const[1:PINOUT_SIZE][3] - = '{ - '{0, PADTYPE_GPIO, 0}, - '{1, PADTYPE_GPIO, 0}, - '{2, PADTYPE_GPIO, 0}, - '{5, PADTYPE_GPIO, 0}, - '{6, PADTYPE_VDD, 0}, - '{8, PADTYPE_GND , 0} - }; + const + int + pinout_static_const[1:PINOUT_SIZE][3] = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND, 0} + }; - // Make sure consants propagate - checkstr #(.PINID(STR_PINID[1]), - .EXP("ERR")) - substr1 (); - checkstr #(.PINID(STR_PINID[8]), - .EXP("PA0")) - substr8 (); + // Make sure consants propagate + checkstr #( + .PINID(STR_PINID[1]), + .EXP("ERR") + ) substr1 (); + checkstr #( + .PINID(STR_PINID[8]), + .EXP("PA0") + ) substr8 (); - initial begin - $display("PINID1 %s", STR_PINID[1]); - $display("PINID8 %s", STR_PINID[8]); - if (STR_PINID[1] != "ERR") $stop; - if (STR_PINID[8] != "PA0") $stop; - if (pinout_static_const[1][0] != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("PINID1 %s", STR_PINID[1]); + $display("PINID8 %s", STR_PINID[8]); + if (STR_PINID[1] != "ERR") $stop; + if (STR_PINID[8] != "PA0") $stop; + if (pinout_static_const[1][0] != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module checkstr; - parameter int PINID = " "; - parameter int EXP = " "; - initial begin - $display("PID %s EXP %s", PINID, EXP); - if (EXP != "ERR" && EXP != "PA0") $stop; - if (PINID != EXP) $stop; - end + parameter int PINID = " "; + parameter int EXP = " "; + initial begin + $display("PID %s EXP %s", PINID, EXP); + if (EXP != "ERR" && EXP != "PA0") $stop; + if (PINID != EXP) $stop; + end endmodule diff --git a/test_regress/t/t_param_array2.v b/test_regress/t/t_param_array2.v index 6d5fd05bc..ac57b5711 100644 --- a/test_regress/t/t_param_array2.v +++ b/test_regress/t/t_param_array2.v @@ -5,18 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam int C[4] = '{5, 6, 7, 8}; - a #(.P(C)) i_a (); + localparam int C[4] = '{5, 6, 7, 8}; + a #(.P(C)) i_a (); endmodule -module a - #( parameter int P[4] = '{1, 2, 3, 4} ); - initial begin - if (P[0] != 5) $stop; - if (P[1] != 6) $stop; - if (P[2] != 7) $stop; - if (P[3] != 8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end +module a #( + parameter int P[4] = '{1, 2, 3, 4} +); + initial begin + if (P[0] != 5) $stop; + if (P[1] != 6) $stop; + if (P[2] != 7) $stop; + if (P[3] != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_array3.v b/test_regress/t/t_param_array3.v index 0071cc5b9..40e2c57cb 100644 --- a/test_regress/t/t_param_array3.v +++ b/test_regress/t/t_param_array3.v @@ -5,33 +5,33 @@ // SPDX-License-Identifier: CC0-1.0 module t; - parameter int SIZES [3:0] = '{1,2,3,4}; - typedef int calc_sums_t [3:0]; + parameter int SIZES[3:0] = '{1, 2, 3, 4}; + typedef int calc_sums_t[3:0]; - function static calc_sums_t calc_sums; - int sum = 0; - for (int i=0; i<4; i++) begin - sum = sum + SIZES[i]; - calc_sums[i] = sum; - //TODO: calc_sums[i][31:0] = sum; - end - endfunction + function static calc_sums_t calc_sums; + int sum = 0; + for (int i = 0; i < 4; i++) begin + sum = sum + SIZES[i]; + calc_sums[i] = sum; + //TODO: calc_sums[i][31:0] = sum; + end + endfunction - parameter int SUMS[3:0] = calc_sums(); - parameter int SUMS1[3:0] = calc_sums(); + parameter int SUMS[3:0] = calc_sums(); + parameter int SUMS1[3:0] = calc_sums(); - initial begin - if (SUMS[0] != 4) $stop; - if (SUMS[1] != 4+3) $stop; - if (SUMS[2] != 4+3+2) $stop; - if (SUMS[3] != 4+3+2+1) $stop; - // According to IEEE 1800-2023 13.4.3 - // execution at elaboration has no effect on the initial values - // of the variables used either at simulation time or among - // multiple invocations of a function at elaboration time - if (SUMS1 != SUMS) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (SUMS[0] != 4) $stop; + if (SUMS[1] != 4 + 3) $stop; + if (SUMS[2] != 4 + 3 + 2) $stop; + if (SUMS[3] != 4 + 3 + 2 + 1) $stop; + // According to IEEE 1800-2023 13.4.3 + // execution at elaboration has no effect on the initial values + // of the variables used either at simulation time or among + // multiple invocations of a function at elaboration time + if (SUMS1 != SUMS) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_array4.v b/test_regress/t/t_param_array4.v index 062ca3927..a4114b356 100644 --- a/test_regress/t/t_param_array4.v +++ b/test_regress/t/t_param_array4.v @@ -5,38 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 module t; - parameter int SIZES [3:1] = '{10,20,30}; - parameter int SUMS3 = SIZES[3]; - parameter int SUMS2 = SIZES[2]; - parameter int SUMS1 = SIZES[1]; + parameter int SIZES[3:1] = '{10, 20, 30}; + parameter int SUMS3 = SIZES[3]; + parameter int SUMS2 = SIZES[2]; + parameter int SUMS1 = SIZES[1]; - parameter int LE_SIZES [1:3] = '{10,20,30}; - parameter int LE_SUMS3 = LE_SIZES[3]; - parameter int LE_SUMS2 = LE_SIZES[2]; - parameter int LE_SUMS1 = LE_SIZES[1]; + parameter int LE_SIZES[1:3] = '{10, 20, 30}; + parameter int LE_SUMS3 = LE_SIZES[3]; + parameter int LE_SUMS2 = LE_SIZES[2]; + parameter int LE_SUMS1 = LE_SIZES[1]; - function int from_array(int index); - if (index != 0); return SIZES[index]; - endfunction - function int from_array_le(int index); - if (index != 0); return LE_SIZES[index]; - endfunction + function int from_array(int index); + if (index != 0); + return SIZES[index]; + endfunction + function int from_array_le(int index); + if (index != 0); + return LE_SIZES[index]; + endfunction - initial begin - if (SUMS1 != 30) $stop; - if (SUMS2 != 20) $stop; - if (SUMS3 != 10) $stop; - if (LE_SUMS1 != 10) $stop; - if (LE_SUMS2 != 20) $stop; - if (LE_SUMS3 != 30) $stop; - if (from_array(1) != 30) $stop; - if (from_array(2) != 20) $stop; - if (from_array(3) != 10) $stop; - if (from_array_le(1) != 10) $stop; - if (from_array_le(2) != 20) $stop; - if (from_array_le(3) != 30) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (SUMS1 != 30) $stop; + if (SUMS2 != 20) $stop; + if (SUMS3 != 10) $stop; + if (LE_SUMS1 != 10) $stop; + if (LE_SUMS2 != 20) $stop; + if (LE_SUMS3 != 30) $stop; + if (from_array(1) != 30) $stop; + if (from_array(2) != 20) $stop; + if (from_array(3) != 10) $stop; + if (from_array_le(1) != 10) $stop; + if (from_array_le(2) != 20) $stop; + if (from_array_le(3) != 30) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_array5.v b/test_regress/t/t_param_array5.v index 4c4f9f354..5026004fb 100644 --- a/test_regress/t/t_param_array5.v +++ b/test_regress/t/t_param_array5.v @@ -6,34 +6,34 @@ //bug1578 module t; - parameter N = 4; + parameter N = 4; - typedef logic array_t[N]; + typedef logic array_t[N]; - parameter array_t MASK = mask_array(); - //TODO bug1578: parameter MASK = mask_array(); + parameter array_t MASK = mask_array(); + //TODO bug1578: parameter MASK = mask_array(); - function array_t mask_array(); - for(int i = 0; i < N; i++) begin - mask_array[i] = i[0]; - end - endfunction + function array_t mask_array(); + for (int i = 0; i < N; i++) begin + mask_array[i] = i[0]; + end + endfunction - array_t norm; + array_t norm; - initial begin - if (N != 4) $stop; - norm = mask_array(); - if (norm[0] != 1'b0) $stop; - if (norm[1] != 1'b1) $stop; - if (norm[2] != 1'b0) $stop; - if (norm[3] != 1'b1) $stop; - if (MASK[0] != 1'b0) $stop; - if (MASK[1] != 1'b1) $stop; - if (MASK[2] != 1'b0) $stop; - if (MASK[3] != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (N != 4) $stop; + norm = mask_array(); + if (norm[0] != 1'b0) $stop; + if (norm[1] != 1'b1) $stop; + if (norm[2] != 1'b0) $stop; + if (norm[3] != 1'b1) $stop; + if (MASK[0] != 1'b0) $stop; + if (MASK[1] != 1'b1) $stop; + if (MASK[2] != 1'b0) $stop; + if (MASK[3] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_array6.v b/test_regress/t/t_param_array6.v index a2d24a8bf..2d7451b73 100644 --- a/test_regress/t/t_param_array6.v +++ b/test_regress/t/t_param_array6.v @@ -5,57 +5,60 @@ // SPDX-License-Identifier: CC0-1.0 package test_pkg; - localparam [31:0] test_arr [4][4:0] - = '{ - '{'h0000, 'h1000, 'h2000, 'h3000, 'h4000}, - '{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF}, - '{ 'd0, 'd0, 'd0, 'd0, 'd0}, - '{ 'd0, 'd1, 'd2, 'd3, 'd4} - }; + localparam [31:0] test_arr[4][4:0] = '{ + '{'h0000, 'h1000, 'h2000, 'h3000, 'h4000}, + '{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF}, + '{'d0, 'd0, 'd0, 'd0, 'd0}, + '{'d0, 'd1, 'd2, 'd3, 'd4} + }; - typedef struct packed{ - logic [7:0] val_1; - logic [7:0] val_2; - } test_ret_t; + typedef struct packed { + logic [7:0] val_1; + logic [7:0] val_2; + } test_ret_t; endpackage -module t import test_pkg::*; (clk); - input clk; +module t + import test_pkg::*; +( + clk +); + input clk; - function automatic test_ret_t test_f(logic [31:0] val); - test_ret_t temp; + function automatic test_ret_t test_f(logic [31:0] val); + test_ret_t temp; - temp = test_ret_t'(0); - for (int i=0; i<5; i++) begin - if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin - temp.val_1 = test_arr[2][i][7:0]; - temp.val_2 = test_arr[3][i][7:0]; - end + temp = test_ret_t'(0); + for (int i = 0; i < 5; i++) begin + if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin + temp.val_1 = test_arr[2][i][7:0]; + temp.val_2 = test_arr[3][i][7:0]; end - return temp; - endfunction + end + return temp; + endfunction - test_ret_t temp; - logic [31:0] random; + test_ret_t temp; + logic [31:0] random; - int cyc; - bit [63:0] sum; + int cyc; + bit [63:0] sum; - always @ (posedge clk) begin - cyc <= cyc + 1; - random <= {17'b0, cyc[3:0], 11'b0}; - temp <= test_f(random); + always @(posedge clk) begin + cyc <= cyc + 1; + random <= {17'b0, cyc[3:0], 11'b0}; + temp <= test_f(random); `ifdef TEST_VERBOSE - $display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2); + $display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2); `endif - if (cyc > 10 && cyc < 90) begin - sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - end - else if (cyc == 99) begin - $displayh(sum); - if (sum != 64'h74d34ea7a775f994) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc > 10 && cyc < 90) begin + sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + end + else if (cyc == 99) begin + $displayh(sum); + if (sum != 64'h74d34ea7a775f994) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_param_array7.v b/test_regress/t/t_param_array7.v index be093cbca..362f1a824 100644 --- a/test_regress/t/t_param_array7.v +++ b/test_regress/t/t_param_array7.v @@ -5,56 +5,54 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - longint a; - longint b; - longint c; + longint a; + longint b; + longint c; } s_t; module t; - localparam int C0 [4] = '{5, 6, 7, 8}; - localparam bit [255:0] C1 [4] = '{9, 10, 11, 12}; - localparam string C2 [2] = '{"baz", "quux"}; - localparam s_t C3 [2] = '{'{a: 100, b: 200, c: 300}, - '{a: 1000, b: 2000, c: 3000}}; + localparam int C0[4] = '{5, 6, 7, 8}; + localparam bit [255:0] C1[4] = '{9, 10, 11, 12}; + localparam string C2[2] = '{"baz", "quux"}; + localparam s_t C3[2] = '{'{a: 100, b: 200, c: 300}, '{a: 1000, b: 2000, c: 3000}}; - a #( - .P0(C0), - .P1(C1), - .P2(C2), - .P3(C3) - ) i_a (); + a #( + .P0(C0), + .P1(C1), + .P2(C2), + .P3(C3) + ) i_a (); endmodule -module a - #( - parameter int P0 [4] = '{1, 2, 3, 4}, - parameter bit [255:0] P1 [4] = '{1, 2, 3, 4}, - parameter string P2 [2] = '{"foo", "bar"}, - parameter s_t P3 [2] = '{'{a: 1, b: 2, c: 3}, - '{a: 1, b: 2, c: 3}} - ); +module a #( + parameter int P0[4] = '{1, 2, 3, 4}, + parameter bit [255:0] P1[4] = '{1, 2, 3, 4}, + parameter string P2[2] = '{"foo", "bar"}, + parameter s_t P3[2] = '{'{a: 1, b: 2, c: 3}, '{a: 1, b: 2, c: 3}} +); - int i; + int i; - initial begin - // Go via $c to ensure parameters are emitted - i = $c("0"); if (P0[i] != 5) $stop; - i = $c("1"); if (P0[i] != 6) $stop; - i = $c("2"); if (P0[i] != 7) $stop; - i = $c("3"); if (P0[i] != 8) $stop; - i = $c("0"); if (P1[i] != 9) $stop; - i = $c("1"); if (P1[i] != 10) $stop; - i = $c("2"); if (P1[i] != 11) $stop; - i = $c("3"); if (P1[i] != 12) $stop; - i = $c("0"); if (P2[i] != "baz") $stop; - i = $c("1"); if (P2[i] != "quux") $stop; - i = $c("0"); if (P3[i].a != 100) $stop; - i = $c("0"); if (P3[i].b != 200) $stop; - i = $c("0"); if (P3[i].c != 300) $stop; - i = $c("1"); if (P3[i].a != 1000) $stop; - i = $c("1"); if (P3[i].b != 2000) $stop; - i = $c("1"); if (P3[i].c != 3000) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Go via $c to ensure parameters are emitted + // verilog_format: off + i = $c("0"); if (P0[i] != 5) $stop; + i = $c("1"); if (P0[i] != 6) $stop; + i = $c("2"); if (P0[i] != 7) $stop; + i = $c("3"); if (P0[i] != 8) $stop; + i = $c("0"); if (P1[i] != 9) $stop; + i = $c("1"); if (P1[i] != 10) $stop; + i = $c("2"); if (P1[i] != 11) $stop; + i = $c("3"); if (P1[i] != 12) $stop; + i = $c("0"); if (P2[i] != "baz") $stop; + i = $c("1"); if (P2[i] != "quux") $stop; + i = $c("0"); if (P3[i].a != 100) $stop; + i = $c("0"); if (P3[i].b != 200) $stop; + i = $c("0"); if (P3[i].c != 300) $stop; + i = $c("1"); if (P3[i].a != 1000) $stop; + i = $c("1"); if (P3[i].b != 2000) $stop; + i = $c("1"); if (P3[i].c != 3000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_array8.v b/test_regress/t/t_param_array8.v index 4e91b9d29..edf4d1539 100644 --- a/test_regress/t/t_param_array8.v +++ b/test_regress/t/t_param_array8.v @@ -4,23 +4,21 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module sub - #( - parameter int unsigned VAL[2] = '{1, 2} - ) - (); +module sub #( + parameter int unsigned VAL[2] = '{1, 2} +) (); endmodule module t; - sub sub12 (); - sub #(.VAL ( '{3, 4} )) sub34 (); + sub sub12 (); + sub #(.VAL('{3, 4})) sub34 (); - initial begin - if (sub12.VAL[0] != 1) $stop; - if (sub12.VAL[1] != 2) $stop; - if (sub34.VAL[0] != 3) $stop; - if (sub34.VAL[1] != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (sub12.VAL[0] != 1) $stop; + if (sub12.VAL[1] != 2) $stop; + if (sub34.VAL[0] != 3) $stop; + if (sub34.VAL[1] != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_avec.v b/test_regress/t/t_param_avec.v index 6b00894d4..b6519ce0a 100644 --- a/test_regress/t/t_param_avec.v +++ b/test_regress/t/t_param_avec.v @@ -4,37 +4,48 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - sub #(.IDX(0), .CHK(10)) i0(); - sub #(.IDX(2), .CHK(12)) i2(); - sub #(.IDX(7), .CHK(17)) i7(); - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; + sub #( + .IDX(0), + .CHK(10) + ) i0 (); + sub #( + .IDX(2), + .CHK(12) + ) i2 (); + sub #( + .IDX(7), + .CHK(17) + ) i7 (); + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub (); - function integer get_element; - input integer index; - input integer array_arg[7:0]; - get_element = array_arg[index]; - endfunction + function integer get_element; + input integer index; + input integer array_arg[7:0]; + get_element = array_arg[index]; + endfunction - parameter integer IDX = 5; - parameter integer CHK = 5; - localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; - localparam element1 = array[IDX]; - localparam elementf = get_element(IDX, array); - initial begin - `checkh (element1, CHK); - `checkh (elementf, CHK); - end + parameter integer IDX = 5; + parameter integer CHK = 5; + localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; + localparam element1 = array[IDX]; + localparam elementf = get_element(IDX, array); + initial begin + `checkh(element1, CHK); + `checkh(elementf, CHK); + end endmodule diff --git a/test_regress/t/t_param_bit_sel.v b/test_regress/t/t_param_bit_sel.v index fb27ce534..3c76ad31a 100644 --- a/test_regress/t/t_param_bit_sel.v +++ b/test_regress/t/t_param_bit_sel.v @@ -9,25 +9,23 @@ // SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // At this point it is ambiguous whether a is scalar or vector - parameter A = 1'b0; - wire b = A[0]; - // Note however b[0] is illegal. + // At this point it is ambiguous whether a is scalar or vector + parameter A = 1'b0; + wire b = A[0]; + // Note however b[0] is illegal. - always @(posedge clk) begin - if (b == 1'b0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end + always @(posedge clk) begin + if (b == 1'b0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_param_bracket.v b/test_regress/t/t_param_bracket.v index 1c39515f3..e53df5fad 100644 --- a/test_regress/t/t_param_bracket.v +++ b/test_regress/t/t_param_bracket.v @@ -4,15 +4,15 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder; // SPDX-License-Identifier: CC0-1.0 -module t - #(parameter WIDTH = 8) - (/*AUTOARG*/ - // Outputs - o - ); - output [WIDTH-1:0] o; - localparam DEPTH = $clog2(5); - // Note single bracket below - reg [WIDTH-1:0] arid [1< y ) ? x : y; - endfunction + function integer max2; + input integer x; + input integer y; + begin + begin : blk + automatic int temp; + temp = x; + end + end + max2 = (x > y) ? x : y; + endfunction - function integer max4; - input integer x; - input integer y; - input integer z; - input integer w; - // MAX2 is used multiple times - max4 = max2( max2( x, y ), max2( z, w ) ); - endfunction + function integer max4; + input integer x; + input integer y; + input integer z; + input integer w; + // MAX2 is used multiple times + max4 = max2(max2(x, y), max2(z, w)); + endfunction - localparam MAX4 = max4( 1, 1, 0, 0 ); + localparam MAX4 = max4(1, 1, 0, 0); - initial begin - if (MAX4 != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (MAX4 != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_circ_bad.out b/test_regress/t/t_param_circ_bad.out index 844a260ba..4c57c1f12 100644 --- a/test_regress/t/t_param_circ_bad.out +++ b/test_regress/t/t_param_circ_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_param_circ_bad.v:11:43: Variable's initial value is circular: 'X' +%Error: t/t_param_circ_bad.v:13:15: Variable's initial value is circular: 'X' : ... note: In instance 't.sub' - 11 | module sub #(parameter WIDTH=X, parameter X=WIDTH) - | ^ + 13 | parameter X = WIDTH + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_circ_bad.v b/test_regress/t/t_param_circ_bad.v index 86fdcfd71..d710332e2 100644 --- a/test_regress/t/t_param_circ_bad.v +++ b/test_regress/t/t_param_circ_bad.v @@ -5,9 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub sub (); + sub sub (); endmodule -module sub #(parameter WIDTH=X, parameter X=WIDTH) - (); +module sub #( + parameter WIDTH = X, + parameter X = WIDTH +) (); endmodule diff --git a/test_regress/t/t_param_concat.v b/test_regress/t/t_param_concat.v index 20a660fd8..619e344e2 100644 --- a/test_regress/t/t_param_concat.v +++ b/test_regress/t/t_param_concat.v @@ -4,25 +4,23 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - parameter UNSIZED = 10; + parameter UNSIZED = 10; - integer cyc=1; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; - if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + integer cyc = 1; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + if ({UNSIZED, UNSIZED + 1} != {32'd10, 32'd11}) $stop; + if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_param_concat_bad.out b/test_regress/t/t_param_concat_bad.out index 87b78c550..d493f049b 100644 --- a/test_regress/t/t_param_concat_bad.out +++ b/test_regress/t/t_param_concat_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTHCONCAT: t/t_param_concat.v:19:15: Unsized numbers/parameters not allowed in concatenations. +%Warning-WIDTHCONCAT: t/t_param_concat.v:17:12: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' - 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; - | ^~~~~~~ + 17 | if ({UNSIZED, UNSIZED + 1} != {32'd10, 32'd11}) $stop; + | ^~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. +%Warning-WIDTHCONCAT: t/t_param_concat.v:17:19: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; - | ^ -%Warning-WIDTHCONCAT: t/t_param_concat.v:20:17: Unsized numbers/parameters not allowed in replications. + 17 | if ({UNSIZED, UNSIZED + 1} != {32'd10, 32'd11}) $stop; + | ^ +%Warning-WIDTHCONCAT: t/t_param_concat.v:18:14: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' - 20 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; - | ^~~~~~~ + 18 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_const_part.v b/test_regress/t/t_param_const_part.v index e66373059..aa4ad5284 100644 --- a/test_regress/t/t_param_const_part.v +++ b/test_regress/t/t_param_const_part.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t; - function integer bottom_4bits; - input [7:0] i; - bottom_4bits = 0; - bottom_4bits[3:0] = i[3:0]; - endfunction + function integer bottom_4bits; + input [7:0] i; + bottom_4bits = 0; + bottom_4bits[3:0] = i[3:0]; + endfunction - function integer bottom_2_unknown; - input [7:0] i; - // bottom_4bits = 0; 'x - bottom_2_unknown[1:0] = i[1:0]; - endfunction + function integer bottom_2_unknown; + input [7:0] i; + // bottom_4bits = 0; 'x + bottom_2_unknown[1:0] = i[1:0]; + endfunction - localparam P = bottom_4bits(8'h13); - localparam BU = bottom_2_unknown(8'h13); + localparam P = bottom_4bits(8'h13); + localparam BU = bottom_2_unknown(8'h13); - initial begin - if (P != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (P != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_ddeep_width.v b/test_regress/t/t_param_ddeep_width.v index 625650558..87a6fc5ee 100644 --- a/test_regress/t/t_param_ddeep_width.v +++ b/test_regress/t/t_param_ddeep_width.v @@ -5,27 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 // bug541 +// verilog_format: off module t(clk,odata); - input clk; - output [7:0] odata; - paramtest_DFFRE #(1) dffre0(clk,odata[7]); - paramtest_WRAP #(7) dffe0(clk,odata[6:0]); + input clk; + output [7:0] odata; + paramtest_DFFRE #(1) dffre0(clk,odata[7]); + paramtest_WRAP #(7) dffe0(clk,odata[6:0]); endmodule module paramtest_WRAP(clk,q); - parameter W=1; - input clk; - output [W-1:0] q; - paramtest_DFFRE #(W) dffre0(clk,q); + parameter W=1; + input clk; + output [W-1:0] q; + paramtest_DFFRE #(W) dffre0(clk,q); endmodule module paramtest_DFFRE(clk,q); - parameter W=1; - parameter [W-1:0] INIT={W{1'b0}}; - input clk; - output [W-1:0] q; - reg [W-1:0] q; - always @(posedge clk) begin - q <= INIT; - end + parameter W=1; + parameter [W-1:0] INIT={W{1'b0}}; + input clk; + output [W-1:0] q; + reg [W-1:0] q; + always @(posedge clk) begin + q <= INIT; + end endmodule diff --git a/test_regress/t/t_param_default.v b/test_regress/t/t_param_default.v index 2f664fd38..27e66bcb5 100644 --- a/test_regress/t/t_param_default.v +++ b/test_regress/t/t_param_default.v @@ -4,17 +4,19 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module m #(parameter int Foo); +module m #( + parameter int Foo +); endmodule module t; - m #(10) foo(); + m #(10) foo (); - initial begin + initial begin if (foo.Foo != 10) $stop; $write("*-* All Finished *-*\n"); $finish; - end + end endmodule diff --git a/test_regress/t/t_param_default_2.v b/test_regress/t/t_param_default_2.v index d6e89cdfe..40f53cb92 100644 --- a/test_regress/t/t_param_default_2.v +++ b/test_regress/t/t_param_default_2.v @@ -5,34 +5,44 @@ // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; -class uvm_queue #(type T=int); -endclass -class m_uvm_waiter; -endclass -class uvm_config_db#(type T=int); - static local uvm_queue#(m_uvm_waiter) m_waiters[string]; - static function void set(int a, string b, string c, int d); - endfunction -endclass + class uvm_queue #( + type T = int + ); + endclass + class m_uvm_waiter; + endclass + class uvm_config_db #( + type T = int + ); + static local uvm_queue #(m_uvm_waiter) m_waiters[string]; + static function void set(int a, string b, string c, int d); + endfunction + endclass endpackage package sfr_agent_pkg; -class sfr_monitor_abstract; -endclass -endpackage: sfr_agent_pkg -module sfr_monitor_bfm #(ADDR_WIDTH = 8, - DATA_WIDTH = 8) - ( - input [ADDR_WIDTH-1:0] address); + class sfr_monitor_abstract; + endclass +endpackage : sfr_agent_pkg +module sfr_monitor_bfm #( + ADDR_WIDTH = 8, + DATA_WIDTH = 8 +) ( + input [ADDR_WIDTH-1:0] address +); import uvm_pkg::*; - import sfr_agent_pkg::*; int SFR_MONITOR; -initial begin - uvm_config_db #(sfr_monitor_abstract)::set(null, "uvm_test_top", "SFR_MONITOR", SFR_MONITOR); -end -endmodule: sfr_monitor_bfm + import sfr_agent_pkg::*; + int SFR_MONITOR; + initial begin + uvm_config_db#(sfr_monitor_abstract)::set(null, "uvm_test_top", "SFR_MONITOR", SFR_MONITOR); + end +endmodule : sfr_monitor_bfm module hdl_top; -parameter DATA_WIDTH = 32; -parameter ADDR_WIDTH = 32; -sfr_monitor_bfm #(.ADDR_WIDTH(ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH)) SFR_MONITOR( - .address(42)); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 32; + sfr_monitor_bfm #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH) + ) SFR_MONITOR ( + .address(42) + ); endmodule diff --git a/test_regress/t/t_param_default_bad.out b/test_regress/t/t_param_default_bad.out index 5c8b28d6c..16396240d 100644 --- a/test_regress/t/t_param_default_bad.out +++ b/test_regress/t/t_param_default_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_param_default_bad.v:7:26: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' +%Error: t/t_param_default_bad.v:8:19: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' : ... note: In instance 't.foo' - 7 | module m #(parameter int Foo); - | ^~~ + 8 | parameter int Foo + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_default_bad.v b/test_regress/t/t_param_default_bad.v index 8c49a0d9c..fc16ee490 100644 --- a/test_regress/t/t_param_default_bad.v +++ b/test_regress/t/t_param_default_bad.v @@ -4,11 +4,13 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module m #(parameter int Foo); +module m #( + parameter int Foo +); endmodule module t; - m foo(); + m foo (); endmodule diff --git a/test_regress/t/t_param_default_override.v b/test_regress/t/t_param_default_override.v index c70582101..43b1b3378 100644 --- a/test_regress/t/t_param_default_override.v +++ b/test_regress/t/t_param_default_override.v @@ -5,54 +5,54 @@ // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH - +// verilog_format: off module m2 #(parameter int N = 4) - (input [N-1:0] i0, i1, - input s, - output [N-1:0] y); + (input [N-1:0] i0, i1, + input s, + output [N-1:0] y); - assign y = s ? i1 : i0; + assign y = s ? i1 : i0; endmodule module m4 #(parameter int N = 4) - (input [N-1:0] i0, i1, i2, i3, - input [1:0] S, - output [N-1:0] y); + (input [N-1:0] i0, i1, i2, i3, + input [1:0] S, + output [N-1:0] y); - wire [N-1:0] o_low, o_high; + wire [N-1:0] o_low, o_high; - // See issue #4920 - use of m4 without parameter overrides - // caused the other use of m4(#(6)) to irop the #(N) below - m2 #(N) lowm( .i0(i0), .i1(i1), .s(S[0]), .y(o_low)); - m2 #(N) highm( .i0(i2), .i1(i3), .s(S[0]), .y(o_high)); - m2 #(N) finalm( .i0(o_low), .i1(o_high), .s(S[1]), .y(y)); + // See issue #4920 - use of m4 without parameter overrides + // caused the other use of m4(#(6)) to irop the #(N) below + m2 #(N) lowm( .i0(i0), .i1(i1), .s(S[0]), .y(o_low)); + m2 #(N) highm( .i0(i2), .i1(i3), .s(S[0]), .y(o_high)); + m2 #(N) finalm( .i0(o_low), .i1(o_high), .s(S[1]), .y(y)); endmodule module m8 #(parameter int N = 4) (input [N-1:0] i0, i1, i2, i3, i4, i5, i6, i7, - input [2:0] S, - output [N-1:0] y); + input [2:0] S, + output [N-1:0] y); - wire [N-1:0] o_low, o_high; + wire [N-1:0] o_low, o_high; - m4 #(N) lowm(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S[1:0]), .y(o_low)); - m4 #(N) highm(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .S(S[1:0]), .y(o_high)); - m2 #(N) finalm(.i0(o_low), .i1(o_high), .s(S[2]), .y(y)); + m4 #(N) lowm(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S[1:0]), .y(o_low)); + m4 #(N) highm(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .S(S[1:0]), .y(o_high)); + m2 #(N) finalm(.i0(o_low), .i1(o_high), .s(S[2]), .y(y)); endmodule module t; - reg [5:0] i0, i1, i2, i3; - reg [1:0] S; - wire [5:0] Y; + reg [5:0] i0, i1, i2, i3; + reg [1:0] S; + wire [5:0] Y; - m4 #(6) iut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S), .y(Y)); + m4 #(6) iut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S), .y(Y)); - initial begin - i0 = 6'b000000; i1 = 6'b000001; i2 = 6'b000010; i3 = 6'b000100; - S = 2'b00; #10; - S = 2'b01; #10; - $write("*-* All Finished *-*\n"); - end + initial begin + i0 = 6'b000000; i1 = 6'b000001; i2 = 6'b000010; i3 = 6'b000100; + S = 2'b00; #10; + S = 2'b01; #10; + $write("*-* All Finished *-*\n"); + end endmodule diff --git a/test_regress/t/t_param_default_presv_bad.out b/test_regress/t/t_param_default_presv_bad.out index 828ef91a0..ce33df41c 100644 --- a/test_regress/t/t_param_default_presv_bad.out +++ b/test_regress/t/t_param_default_presv_bad.out @@ -1,11 +1,11 @@ -%Warning-NEWERSTD: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later. - 7 | module m #(parameter int Foo); - | ^~~ +%Warning-NEWERSTD: t/t_param_default_bad.v:8:19: Parameter requires default value, or use IEEE 1800-2009 or later. + 8 | parameter int Foo + | ^~~ ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. -%Error: t/t_param_default_bad.v:7:26: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' +%Error: t/t_param_default_bad.v:8:19: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' : ... note: In instance 't.foo' - 7 | module m #(parameter int Foo); - | ^~~ + 8 | parameter int Foo + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_first.v b/test_regress/t/t_param_first.v index 083531dc6..eea84e2c3 100644 --- a/test_regress/t/t_param_first.v +++ b/test_regress/t/t_param_first.v @@ -4,144 +4,148 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg _ranit; + reg _ranit; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [4:0] par1; // From a1 of t_param_first_a.v - wire [4:0] par2; // From a2 of t_param_first_a.v - wire [4:0] par3; // From a3 of t_param_first_a.v - wire [4:0] par4; // From a4 of t_param_first_a.v - wire [1:0] varwidth1; // From a1 of t_param_first_a.v - wire [2:0] varwidth2; // From a2 of t_param_first_a.v - wire [3:0] varwidth3; // From a3 of t_param_first_a.v - wire [3:0] varwidth4; // From a4 of t_param_first_a.v - // End of automatics - /*t_param_first_a AUTO_TEMPLATE ( + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [4:0] par1; // From a1 of t_param_first_a.v + wire [4:0] par2; // From a2 of t_param_first_a.v + wire [4:0] par3; // From a3 of t_param_first_a.v + wire [4:0] par4; // From a4 of t_param_first_a.v + wire [1:0] varwidth1; // From a1 of t_param_first_a.v + wire [2:0] varwidth2; // From a2 of t_param_first_a.v + wire [3:0] varwidth3; // From a3 of t_param_first_a.v + wire [3:0] varwidth4; // From a4 of t_param_first_a.v + // End of automatics + /*t_param_first_a AUTO_TEMPLATE ( .par (par@[])); .varwidth (varwidth@[])); */ - parameter XX = 2'bXX; + parameter XX = 2'bXX; - parameter THREE = 3; + parameter THREE = 3; - t_param_first_a #(1,5) a1 - ( + t_param_first_a #(1, 5) a1 ( // Outputs - .varwidth (varwidth1[1:0]), + .varwidth(varwidth1[1:0]), /*AUTOINST*/ // Outputs - .par (par1[4:0])); // Templated - t_param_first_a #(2,5) a2 - ( + .par(par1[4:0]) + ); // Templated + t_param_first_a #(2, 5) a2 ( // Outputs - .varwidth (varwidth2[2:0]), + .varwidth(varwidth2[2:0]), /*AUTOINST*/ // Outputs - .par (par2[4:0])); // Templated - t_param_first_a #(THREE,5) a3 - ( + .par(par2[4:0]) + ); // Templated + t_param_first_a #(THREE, 5) a3 ( // Outputs - .varwidth (varwidth3[3:0]), + .varwidth(varwidth3[3:0]), /*AUTOINST*/ // Outputs - .par (par3[4:0])); // Templated - t_param_first_a #(THREE,5) a4 - ( + .par(par3[4:0]) + ); // Templated + t_param_first_a #(THREE, 5) a4 ( // Outputs - .varwidth (varwidth4[3:0]), + .varwidth(varwidth4[3:0]), /*AUTOINST*/ // Outputs - .par (par4[4:0])); // Templated + .par(par4[4:0]) + ); // Templated - parameter THREE_BITS_WIDE = 3'b011; - parameter THREE_2WIDE = 2'b11; - parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; - parameter THREEPP_32_WIDE = 2*8*2+3; - parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide + parameter THREE_BITS_WIDE = 3'b011; + parameter THREE_2WIDE = 2'b11; + parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; + parameter THREEPP_32_WIDE = 2 * 8 * 2 + 3; + parameter THREEPP_3_WIDE = 3'd4 * 3'd4 * 3'd2 + 3'd3; // Yes folks VCS says 3 bits wide - // Width propagation doesn't care about LHS vs RHS - // But the width of a RHS/LHS on a upper node does affect lower nodes; - // Thus must double-descend in width analysis. - // VCS 7.0.1 is broken on this test! - parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; - parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; + // Width propagation doesn't care about LHS vs RHS + // But the width of a RHS/LHS on a upper node does affect lower nodes; + // Thus must double-descend in width analysis. + // VCS 7.0.1 is broken on this test! + parameter T10 = (3'h7 + 3'h7) + 4'h0; //initial if (T10!==4'd14) $stop; + parameter T11 = 4'h0 + (3'h7 + 3'h7); //initial if (T11!==4'd14) $stop; - // Parameters assign LHS is affectively width zero. - parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; - parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; + // Parameters assign LHS is affectively width zero. + parameter T12 = THREE_2WIDE + THREE_2WIDE; + initial if (T12 !== 2'd2) $stop; + parameter T13 = THREE_2WIDE + 3; + initial if (T13 !== 32'd6) $stop; - // Must be careful about LSB's with extracts - parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop; + // Must be careful about LSB's with extracts + parameter [39:8] T14 = 32'h00_1234_56; + initial if (T14[24:16] !== 9'h34) $stop; - // - parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3; - parameter THREE_32_WIDE = 3%32; - parameter THIRTYTWO = 2; // Param is 32 bits - parameter [40:0] WIDEPARAM = 41'h12_3456789a; - parameter [40:0] WIDEPARAM2 = WIDEPARAM; + // + parameter THREEPP_32P_WIDE = 3'd4 * 3'd4 * 2 + 3'd3; + parameter THREE_32_WIDE = 3 % 32; + parameter THIRTYTWO = 2; // Param is 32 bits + parameter [40:0] WIDEPARAM = 41'h12_3456789a; + parameter [40:0] WIDEPARAM2 = WIDEPARAM; - reg [7:0] eightb; - reg [3:0] fourb; - wire [7:0] eight = 8'b00010000; - wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; - wire [2:0] threebits = ALSO_THREE_WIDE; + reg [7:0] eightb; + reg [3:0] fourb; + wire [7:0] eight = 8'b00010000; + wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; + wire [2:0] threebits = ALSO_THREE_WIDE; - // surefire lint_off CWCCXX + // surefire lint_off CWCCXX - initial _ranit = 0; + initial _ranit = 0; - always @ (posedge clk) begin - if (!_ranit) begin - _ranit <= 1; - $write("[%0t] t_param: Running\n", $time); - // - $write(" %d %d %d\n", par1,par2,par3); - if (par1!==5'd1) $stop; - if (par2!==5'd2) $stop; - if (par3!==5'd3) $stop; - if (par4!==5'd3) $stop; - if (varwidth1!==2'd2) $stop; - if (varwidth2!==3'd2) $stop; - if (varwidth3!==4'd2) $stop; - if (varwidth4!==4'd2) $stop; - if (threebits !== 3'b011) $stop; - if (eight !== 8'b00010000) $stop; - if (eight2two !== 2'b10) $stop; - $write(" Params = %b %b\n %b %b\n", - THREEPP_32_WIDE,THREEPP_3_WIDE, - THIRTYTWO, THREEPP_32P_WIDE); - if (THREEPP_32_WIDE !== 32'h23) $stop; - if (THREEPP_3_WIDE !== 3'h3) $stop; - if (THREEPP_32P_WIDE !== 32'h23) $stop; - if (THIRTYTWO[1:0] !== 2'h2) $stop; - if (THIRTYTWO !== 32'h2) $stop; - if (THIRTYTWO !== 2) $stop; - if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; - if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; - if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 - // - // Example of assignment LHS affecting expression widths. - // verilator lint_off WIDTH - // surefire lint_off ASWCMB - // surefire lint_off ASWCBB - eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; - fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; - fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; - // verilator lint_on WIDTH - // surefire lint_on ASWCMB - // surefire lint_on ASWCBB - // - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + $write("[%0t] t_param: Running\n", $time); + // + $write(" %d %d %d\n", par1, par2, par3); + if (par1 !== 5'd1) $stop; + if (par2 !== 5'd2) $stop; + if (par3 !== 5'd3) $stop; + if (par4 !== 5'd3) $stop; + if (varwidth1 !== 2'd2) $stop; + if (varwidth2 !== 3'd2) $stop; + if (varwidth3 !== 4'd2) $stop; + if (varwidth4 !== 4'd2) $stop; + if (threebits !== 3'b011) $stop; + if (eight !== 8'b00010000) $stop; + if (eight2two !== 2'b10) $stop; + $write(" Params = %b %b\n %b %b\n", THREEPP_32_WIDE, THREEPP_3_WIDE, THIRTYTWO, + THREEPP_32P_WIDE); + if (THREEPP_32_WIDE !== 32'h23) $stop; + if (THREEPP_3_WIDE !== 3'h3) $stop; + if (THREEPP_32P_WIDE !== 32'h23) $stop; + if (THIRTYTWO[1:0] !== 2'h2) $stop; + if (THIRTYTWO !== 32'h2) $stop; + if (THIRTYTWO !== 2) $stop; + if ((THIRTYTWO[1:0] + 2'b00) !== 2'b10) $stop; + if ({1'b1, {THIRTYTWO[1:0] + 2'b00}} !== 3'b110) $stop; + if (XX === 0 || XX === 1 || XX === 2 || XX === 3) + $stop; // Paradoxical but right, since 1'bx!=0 && !=1 + // + // Example of assignment LHS affecting expression widths. + // verilator lint_off WIDTH + // surefire lint_off ASWCMB + // surefire lint_off ASWCBB + eightb = (4'd8 + 4'd8) / 4'd4; + if (eightb !== 8'd4) $stop; + fourb = (4'd8 + 4'd8) / 4'd4; + if (fourb !== 4'd0) $stop; + fourb = (4'd8 + 8) / 4'd4; + if (fourb !== 4'd4) $stop; + // verilator lint_on WIDTH + // surefire lint_on ASWCMB + // surefire lint_on ASWCBB + // + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_param_first_a.v b/test_regress/t/t_param_first_a.v index 4898e07c3..a92910538 100644 --- a/test_regress/t/t_param_first_a.v +++ b/test_regress/t/t_param_first_a.v @@ -4,25 +4,26 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_param_first_a (/*AUTOARG*/ - // Outputs - varwidth, par - ); +module t_param_first_a ( /*AUTOARG*/ + // Outputs + varwidth, + par +); - parameter X = 1; - parameter FIVE = 0; // Overridden - parameter TWO = 2; + parameter X = 1; + parameter FIVE = 0; // Overridden + parameter TWO = 2; - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [4:0] par; // From b of t_param_first_b.v - output [X:0] varwidth; // From b of t_param_first_b.v - // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [4:0] par; // From b of t_param_first_b.v + output [X:0] varwidth; // From b of t_param_first_b.v + // End of automatics - t_param_first_b #(X,FIVE,TWO) b - (/*AUTOINST*/ + t_param_first_b #(X, FIVE, TWO) b ( /*AUTOINST*/ // Outputs - .par (par[4:0]), - .varwidth (varwidth[X:0])); + .par(par[4:0]), + .varwidth(varwidth[X:0]) + ); endmodule diff --git a/test_regress/t/t_param_first_b.v b/test_regress/t/t_param_first_b.v index 29a865180..002bde6c5 100644 --- a/test_regress/t/t_param_first_b.v +++ b/test_regress/t/t_param_first_b.v @@ -4,19 +4,20 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_param_first_b (/*AUTOARG*/ - // Outputs - par, varwidth - ); +module t_param_first_b ( /*AUTOARG*/ + // Outputs + par, + varwidth +); - parameter X = 1; - parameter FIVE = 0; // Overridden - parameter TWO = 2; + parameter X = 1; + parameter FIVE = 0; // Overridden + parameter TWO = 2; - output [4:0] par; - output [X:0] varwidth; + output [4:0] par; + output [X:0] varwidth; - wire [4:0] par = X; - wire [X:0] varwidth = (FIVE==5)?TWO:0; + wire [4:0] par = X; + wire [X:0] varwidth = (FIVE == 5) ? TWO : 0; endmodule diff --git a/test_regress/t/t_param_func.v b/test_regress/t/t_param_func.v index 89c5dea51..5ddee42e0 100644 --- a/test_regress/t/t_param_func.v +++ b/test_regress/t/t_param_func.v @@ -7,28 +7,28 @@ // SPDX-FileCopyrightText: 2015 Roland Kruse and Jie Xu // SPDX-License-Identifier: CC0-1.0 -module test#( +module test #( parameter SIZE = 4, - parameter P = sum({32'h1,32'h2,32'h3,32'h4}, SIZE)) + parameter P = sum({32'h1, 32'h2, 32'h3, 32'h4}, SIZE) +) ( + input clk, + input logic sel, + output [P:0] res +); - (input clk, - input logic sel, - output [P:0] res); + logic [P:0] cc = 'h45; - logic [P:0] cc = 'h45; + assign res = sel ? cc : {(P + 1) {1'b1}}; - assign res = sel ? cc : {(P+1){1'b1}}; + function integer sum; + input [3:0][31:0] values; + input int size; - function integer sum; - input [3:0][31:0] values; - input int size; + sum = 0; - sum = 0; - - begin - for (int i = 0; i < size; i ++) - sum += values[i]; - end - endfunction + begin + for (int i = 0; i < size; i++) sum += values[i]; + end + endfunction endmodule diff --git a/test_regress/t/t_param_func2.v b/test_regress/t/t_param_func2.v index 6893bb9d2..7f74efa46 100644 --- a/test_regress/t/t_param_func2.v +++ b/test_regress/t/t_param_func2.v @@ -5,48 +5,48 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub #(.WIDTH(4)) sub4(); - sub #(.WIDTH(8)) sub8(); + sub #(.WIDTH(4)) sub4 (); + sub #(.WIDTH(8)) sub8 (); - logic [3:0] out4; - logic [7:0] out8; + logic [3:0] out4; + logic [7:0] out8; - initial begin - out4 = sub4.orer(4'b1000); - out8 = sub8.orer(8'b10000000); - if (out4 != 4'b1011) $stop; - if (out8 != 8'b10111111) $stop; - out4 = sub4.orer2(4'b1000); - out8 = sub8.orer2(8'b10000000); - if (out4 != 4'b1001) $stop; - if (out8 != 8'b10011111) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + out4 = sub4.orer(4'b1000); + out8 = sub8.orer(8'b10000000); + if (out4 != 4'b1011) $stop; + if (out8 != 8'b10111111) $stop; + out4 = sub4.orer2(4'b1000); + out8 = sub8.orer2(8'b10000000); + if (out4 != 4'b1001) $stop; + if (out8 != 8'b10011111) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub; - parameter WIDTH = 1; + parameter WIDTH = 1; - function automatic [WIDTH-1:0] orer; - input [WIDTH-1:0] in; - // IEEE provices no way to override this parameter, basically it's a localparam - parameter MASK_W = WIDTH - 2; - localparam [MASK_W-1:0] MASK = '1; - // verilator lint_off WIDTH - return in | MASK; - // verilator lint_on WIDTH - endfunction + function automatic [WIDTH-1:0] orer; + input [WIDTH-1:0] in; + // IEEE provices no way to override this parameter, basically it's a localparam + parameter MASK_W = WIDTH - 2; + localparam [MASK_W-1:0] MASK = '1; + // verilator lint_off WIDTH + return in | MASK; + // verilator lint_on WIDTH + endfunction - function automatic [WIDTH-1:0] orer2; - input [WIDTH-1:0] in; - // Same param names as other function to check we disambiguate - // IEEE provices no way to override this parameter, basically it's a localparam - parameter MASK_W = WIDTH - 3; - localparam [MASK_W-1:0] MASK = '1; - // verilator lint_off WIDTH - return in | MASK; - // verilator lint_on WIDTH - endfunction + function automatic [WIDTH-1:0] orer2; + input [WIDTH-1:0] in; + // Same param names as other function to check we disambiguate + // IEEE provices no way to override this parameter, basically it's a localparam + parameter MASK_W = WIDTH - 3; + localparam [MASK_W-1:0] MASK = '1; + // verilator lint_off WIDTH + return in | MASK; + // verilator lint_on WIDTH + endfunction endmodule diff --git a/test_regress/t/t_param_if_blk.v b/test_regress/t/t_param_if_blk.v index 58e9a1d4c..ec8118234 100644 --- a/test_regress/t/t_param_if_blk.v +++ b/test_regress/t/t_param_if_blk.v @@ -6,134 +6,127 @@ // bug648 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] datai = crc[7:0]; - wire enable = crc[8]; + // Take CRC data and apply to testblock inputs + wire [7:0] datai = crc[7:0]; + wire enable = crc[8]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [7:0] datao; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [7:0] datao; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .datao (datao[7:0]), - // Inputs - .clk (clk), - .datai (datai[7:0]), - .enable (enable)); + Test test ( /*AUTOINST*/ + // Outputs + .datao(datao[7:0]), + // Inputs + .clk(clk), + .datai(datai[7:0]), + .enable(enable) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {56'h0, datao}; + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, datao}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h9d550d82d38926fa - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h9d550d82d38926fa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule `define FAIL 1 -module Nested - ( - input logic clk, - input logic x, - output logic y - ); - logic t; - always_comb t = x ^ 1'b1; +module Nested ( + input logic clk, + input logic x, + output logic y +); + logic t; + always_comb t = x ^ 1'b1; - always_ff @(posedge clk) begin - if (clk) - y <= t; - end + always_ff @(posedge clk) begin + if (clk) y <= t; + end endmodule -module Test - ( - input logic clk, - input logic [7:0] datai, - input logic enable, - output logic [7:0] datao - ); +module Test ( + input logic clk, + input logic [7:0] datai, + input logic enable, + output logic [7:0] datao +); - logic [7:0] datat; + logic [7:0] datat; - for (genvar i = 0; i < 8; i++) begin - if (i%4 != 3) begin + for (genvar i = 0; i < 8; i++) begin + if (i % 4 != 3) begin `ifndef FAIL - logic t; - always_comb begin - t = datai[i] ^ 1'b1; - end - always_ff @(posedge clk) begin - if (clk) - datat[i] <= t; - end + logic t; + always_comb begin + t = datai[i] ^ 1'b1; + end + always_ff @(posedge clk) begin + if (clk) datat[i] <= t; + end `else - Nested nested_i - ( - .clk(clk), - .x(datai[i]), - .y(datat[i]) //<== via Vcellout wire - ); + Nested nested_i ( + .clk(clk), + .x(datai[i]), + .y(datat[i]) //<== via Vcellout wire + ); `endif - always_comb begin - casez (enable) - 1'b1: datao[i] = datat[i]; - 1'b0: datao[i] = '0; - default: datao[i] = 'x; - endcase - end + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i]; + 1'b0: datao[i] = '0; + default: datao[i] = 'x; + endcase end - else begin - always_ff @(posedge clk) begin - if (clk) - datat[i] <= 0; //<== assign delayed - end - always_comb begin - casez (enable) - 1'b1: datao[i] = datat[i] ^ 1'b1; - 1'b0: datao[i] = '1; - default: datao[i] = 'x; - endcase - end + end + else begin + always_ff @(posedge clk) begin + if (clk) datat[i] <= 0; //<== assign delayed end - end + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i] ^ 1'b1; + 1'b0: datao[i] = '1; + default: datao[i] = 'x; + endcase + end + end + end endmodule diff --git a/test_regress/t/t_param_implicit_local_bad.out b/test_regress/t/t_param_implicit_local_bad.out index 947d67592..198dcc768 100644 --- a/test_regress/t/t_param_implicit_local_bad.out +++ b/test_regress/t/t_param_implicit_local_bad.out @@ -1,40 +1,40 @@ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:15:20: Parameter not found: '__paramNumber2' - 15 | NestedCls #(1, 2) cls; - | ^ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:15:18: Parameter not found: '__paramNumber2' + 15 | NestedCls #(1, 2) cls; + | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:17:21: Parameter not found: '__paramNumber3' - 17 | mod1 # ( 3, 4, 5 ) i_mod1 (); - | ^ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:17:19: Parameter not found: '__paramNumber3' + 17 | mod1 # ( 3, 4, 5 ) i_mod1 (); + | ^ : ... Location of instance's module declaration 26 | module mod1 # ( | ^~~~ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:15: Parameter not found: '__paramNumber1' - 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); - | ^ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:13: Parameter not found: '__paramNumber1' + 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); + | ^ : ... Location of instance's module declaration 38 | module mod3 #() (); | ^~~~ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:18: Parameter not found: '__paramNumber2' - 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); - | ^~ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:16: Parameter not found: '__paramNumber2' + 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); + | ^~ : ... Location of instance's module declaration 38 | module mod3 #() (); | ^~~~ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:22: Parameter not found: '__paramNumber3' - 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); - | ^~ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:20: Parameter not found: '__paramNumber3' + 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); + | ^~ : ... Location of instance's module declaration 38 | module mod3 #() (); | ^~~~ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:20:22: Parameter not found: '__paramNumber3' - 20 | intf1 # ( 8, 15, 17 ) i_intf1 (); - | ^~ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:20:20: Parameter not found: '__paramNumber3' + 20 | intf1 # ( 8, 15, 17 ) i_intf1 (); + | ^~ : ... Location of instance's interface declaration 43 | interface intf1 # ( | ^~~~~ -%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:21:22: Parameter not found: '__paramNumber3' - 21 | prgm1 # ( 9, 40, 41 ) i_prgm1 (); - | ^~ +%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:21:20: Parameter not found: '__paramNumber3' + 21 | prgm1 # ( 9, 40, 41 ) i_prgm1 (); + | ^~ : ... Location of instance's program declaration 50 | program prgm1 # ( | ^~~~~ diff --git a/test_regress/t/t_param_implicit_local_bad.v b/test_regress/t/t_param_implicit_local_bad.v index da3387e63..40a14a041 100644 --- a/test_regress/t/t_param_implicit_local_bad.v +++ b/test_regress/t/t_param_implicit_local_bad.v @@ -6,50 +6,50 @@ module t; - class NestedCls #( - parameter A = 0 - ); - parameter B = 0; - endclass + class NestedCls #( + parameter A = 0 + ); + parameter B = 0; + endclass - NestedCls #(1, 2) cls; + NestedCls #(1, 2) cls; - mod1 # ( 3, 4, 5 ) i_mod1 (); - mod2 # ( 5, 12, 13 ) i_mod2 (); - mod3 # ( 7, 24, 25 ) i_mod3 (); - intf1 # ( 8, 15, 17 ) i_intf1 (); - prgm1 # ( 9, 40, 41 ) i_prgm1 (); + mod1 # ( 3, 4, 5 ) i_mod1 (); + mod2 # ( 5, 12, 13 ) i_mod2 (); + mod3 # ( 7, 24, 25 ) i_mod3 (); + intf1 # ( 8, 15, 17 ) i_intf1 (); + prgm1 # ( 9, 40, 41 ) i_prgm1 (); endmodule `define CHECK_PARAMS if (A**2 + B**2 != C**2) $error("A**2 + B**2 != C**2") module mod1 # ( - parameter A = 1, B = 1 + parameter A = 1, B = 1 ); - parameter C = 1; - `CHECK_PARAMS; + parameter C = 1; + `CHECK_PARAMS; endmodule module mod2 (); - parameter A = 1, B = 1, C = 1; - `CHECK_PARAMS; + parameter A = 1, B = 1, C = 1; + `CHECK_PARAMS; endmodule module mod3 #() (); - parameter A = 1, B = 1, C = 1; - `CHECK_PARAMS; + parameter A = 1, B = 1, C = 1; + `CHECK_PARAMS; endmodule interface intf1 # ( - parameter A = 1, B = 1 + parameter A = 1, B = 1 ); - parameter C = 1; - `CHECK_PARAMS; + parameter C = 1; + `CHECK_PARAMS; endinterface program prgm1 # ( - parameter A = 1, B = 1 + parameter A = 1, B = 1 ); - parameter C = 1; - `CHECK_PARAMS; + parameter C = 1; + `CHECK_PARAMS; endprogram diff --git a/test_regress/t/t_param_in_func.v b/test_regress/t/t_param_in_func.v index 5f992e680..8202a7af7 100644 --- a/test_regress/t/t_param_in_func.v +++ b/test_regress/t/t_param_in_func.v @@ -5,125 +5,120 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - if (getUnpacked($c("0")) != "0") $stop; - if (getUnpacked($c("1")) != "1") $stop; - if (getUnpacked($c("2")) != "2") $stop; - if (getUnpacked($c("3")) != "3") $stop; - if (getUnpacked($c("4")) != "4") $stop; - if (getUnpacked($c("5")) != "5") $stop; - if (getUnpacked($c("6")) != "6") $stop; - if (getUnpacked($c("7")) != "7") $stop; - if (getUnpacked($c("8")) != "8") $stop; - if (getUnpacked($c("9")) != "9") $stop; + initial begin + if (getUnpacked($c("0")) != "0") $stop; + if (getUnpacked($c("1")) != "1") $stop; + if (getUnpacked($c("2")) != "2") $stop; + if (getUnpacked($c("3")) != "3") $stop; + if (getUnpacked($c("4")) != "4") $stop; + if (getUnpacked($c("5")) != "5") $stop; + if (getUnpacked($c("6")) != "6") $stop; + if (getUnpacked($c("7")) != "7") $stop; + if (getUnpacked($c("8")) != "8") $stop; + if (getUnpacked($c("9")) != "9") $stop; - if (getPacked($c("0")) != "0") $stop; - if (getPacked($c("1")) != "1") $stop; - if (getPacked($c("2")) != "2") $stop; - if (getPacked($c("3")) != "3") $stop; - if (getPacked($c("4")) != "4") $stop; - if (getPacked($c("5")) != "5") $stop; - if (getPacked($c("6")) != "6") $stop; - if (getPacked($c("7")) != "7") $stop; - if (getPacked($c("8")) != "8") $stop; - if (getPacked($c("9")) != "9") $stop; + if (getPacked($c("0")) != "0") $stop; + if (getPacked($c("1")) != "1") $stop; + if (getPacked($c("2")) != "2") $stop; + if (getPacked($c("3")) != "3") $stop; + if (getPacked($c("4")) != "4") $stop; + if (getPacked($c("5")) != "5") $stop; + if (getPacked($c("6")) != "6") $stop; + if (getPacked($c("7")) != "7") $stop; + if (getPacked($c("8")) != "8") $stop; + if (getPacked($c("9")) != "9") $stop; - if (getString($c("0")) != "0") $stop; - if (getString($c("1")) != "1") $stop; - if (getString($c("2")) != "2") $stop; - if (getString($c("3")) != "3") $stop; - if (getString($c("4")) != "4") $stop; - if (getString($c("5")) != "5") $stop; - if (getString($c("6")) != "6") $stop; - if (getString($c("7")) != "7") $stop; - if (getString($c("8")) != "8") $stop; - if (getString($c("9")) != "9") $stop; + if (getString($c("0")) != "0") $stop; + if (getString($c("1")) != "1") $stop; + if (getString($c("2")) != "2") $stop; + if (getString($c("3")) != "3") $stop; + if (getString($c("4")) != "4") $stop; + if (getString($c("5")) != "5") $stop; + if (getString($c("6")) != "6") $stop; + if (getString($c("7")) != "7") $stop; + if (getString($c("8")) != "8") $stop; + if (getString($c("9")) != "9") $stop; - if (getStruct($c("0")) != "0") $stop; - if (getStruct($c("1")) != "1") $stop; - if (getStruct($c("2")) != "2") $stop; - if (getStruct($c("3")) != "3") $stop; - if (getStruct($c("4")) != "4") $stop; - if (getStruct($c("5")) != "5") $stop; - if (getStruct($c("6")) != "6") $stop; - if (getStruct($c("7")) != "7") $stop; - if (getStruct($c("8")) != "8") $stop; - if (getStruct($c("9")) != "9") $stop; + if (getStruct($c("0")) != "0") $stop; + if (getStruct($c("1")) != "1") $stop; + if (getStruct($c("2")) != "2") $stop; + if (getStruct($c("3")) != "3") $stop; + if (getStruct($c("4")) != "4") $stop; + if (getStruct($c("5")) != "5") $stop; + if (getStruct($c("6")) != "6") $stop; + if (getStruct($c("7")) != "7") $stop; + if (getStruct($c("8")) != "8") $stop; + if (getStruct($c("9")) != "9") $stop; - if (getType($c("0")) != "0") $stop; - if (getType($c("1")) != "1") $stop; - if (getType($c("2")) != "2") $stop; - if (getType($c("3")) != "3") $stop; - if (getType($c("4")) != "4") $stop; - if (getType($c("5")) != "5") $stop; - if (getType($c("6")) != "6") $stop; - if (getType($c("7")) != "7") $stop; - if (getType($c("8")) != "8") $stop; - if (getType($c("9")) != "9") $stop; + if (getType($c("0")) != "0") $stop; + if (getType($c("1")) != "1") $stop; + if (getType($c("2")) != "2") $stop; + if (getType($c("3")) != "3") $stop; + if (getType($c("4")) != "4") $stop; + if (getType($c("5")) != "5") $stop; + if (getType($c("6")) != "6") $stop; + if (getType($c("7")) != "7") $stop; + if (getType($c("8")) != "8") $stop; + if (getType($c("9")) != "9") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -function automatic logic [7:0] getUnpacked(logic[3:0] d); +function automatic logic [7:0] getUnpacked(logic [3:0] d); `ifdef NO_INLINE - /* verilator no_inline_task */ + /* verilator no_inline_task */ `endif - localparam logic [7:0] DIGITS [10] = - '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; - return DIGITS[d]; + localparam logic [7:0] DIGITS[10] = '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; + return DIGITS[d]; endfunction -function automatic logic [7:0] getPacked(logic[3:0] d); +function automatic logic [7:0] getPacked(logic [3:0] d); `ifdef NO_INLINE - /* verilator no_inline_task */ + /* verilator no_inline_task */ `endif - localparam logic [9:0][7:0] DIGITS = - {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; - return DIGITS[d]; + localparam logic [9:0][7:0] DIGITS = {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; + return DIGITS[d]; endfunction -function automatic string getString(logic[3:0] d); +function automatic string getString(logic [3:0] d); `ifdef NO_INLINE - /* verilator no_inline_task */ + /* verilator no_inline_task */ `endif - localparam string DIGITS [10] = - '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; - return DIGITS[d]; + localparam string DIGITS[10] = '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; + return DIGITS[d]; endfunction -function automatic logic [7:0] getStruct(logic[3:0] d); +function automatic logic [7:0] getStruct(logic [3:0] d); `ifdef NO_INLINE - /* verilator no_inline_task */ + /* verilator no_inline_task */ `endif - // Silly indirect lookup table because we want to use a struct - typedef struct packed { - logic [7:0] result; - longint index; - } lut_t; - localparam lut_t DIGITS [10] = - '{ - '{result: "1", index: 9}, - '{result: "2", index: 0}, - '{result: "3", index: 1}, - '{result: "4", index: 2}, - '{result: "5", index: 3}, - '{result: "6", index: 4}, - '{result: "7", index: 5}, - '{result: "8", index: 6}, - '{result: "9", index: 7}, - '{result: "0", index: 8} - }; - return DIGITS[4'(DIGITS[d].index)].result; + // Silly indirect lookup table because we want to use a struct + typedef struct packed { + logic [7:0] result; + longint index; + } lut_t; + localparam lut_t DIGITS[10] = '{ + '{result: "1", index: 9}, + '{result: "2", index: 0}, + '{result: "3", index: 1}, + '{result: "4", index: 2}, + '{result: "5", index: 3}, + '{result: "6", index: 4}, + '{result: "7", index: 5}, + '{result: "8", index: 6}, + '{result: "9", index: 7}, + '{result: "0", index: 8} + }; + return DIGITS[4'(DIGITS[d].index)].result; endfunction -function automatic logic [7:0] getType(logic[3:0] d); +function automatic logic [7:0] getType(logic [3:0] d); `ifdef NO_INLINE - /* verilator no_inline_task */ + /* verilator no_inline_task */ `endif - localparam type octet_t = logic [7:0]; - localparam octet_t [9:0] DIGITS = - {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; - return DIGITS[d]; + localparam type octet_t = logic [7:0]; + localparam octet_t [9:0] DIGITS = {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; + return DIGITS[d]; endfunction diff --git a/test_regress/t/t_param_local.v b/test_regress/t/t_param_local.v index 374533079..15ee18985 100644 --- a/test_regress/t/t_param_local.v +++ b/test_regress/t/t_param_local.v @@ -4,26 +4,28 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - a, y - ); +module t ( /*AUTOARG*/ + // Inputs + a, + y +); - input [1:0] a; - output [3:0] y; + input [1:0] a; + output [3:0] y; - Test #(.C(2)) - test (.*); + Test #(.C(2)) test (.*); endmodule -module Test - #(C = 3, - localparam O = 1 << C) - (input [C-1:0] a, - output reg [O-1:0] y); - initial begin - if (O != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end +module Test #( + C = 3, + localparam O = 1 << C +) ( + input [C-1:0] a, + output reg [O-1:0] y +); + initial begin + if (O != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_long.v b/test_regress/t/t_param_long.v index 706da0509..a6901c221 100644 --- a/test_regress/t/t_param_long.v +++ b/test_regress/t/t_param_long.v @@ -5,171 +5,171 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - parameter PAR = 3; - input clk; + // Inputs + clk + ); + parameter PAR = 3; + input clk; - defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; - defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG"; - defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG"; - defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG"; - i i (.clk(clk)); + i i (.clk(clk)); - integer cyc=1; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module i - (/*AUTOARG*/ - // Inputs - clk - ); + (/*AUTOARG*/ + // Inputs + clk + ); - // verilator public_module + // verilator public_module - input clk; + input clk; - parameter [255:0] L00 = 256'h0; - parameter [255:0] L01 = 256'h0; - parameter [255:0] L02 = 256'h0; - parameter [255:0] L03 = 256'h0; - parameter [255:0] L04 = 256'h0; - parameter [255:0] L05 = 256'h0; - parameter [255:0] L06 = 256'h0; - parameter [255:0] L07 = 256'h0; - parameter [255:0] L08 = 256'h0; - parameter [255:0] L09 = 256'h0; - parameter [255:0] L0A = 256'h0; - parameter [255:0] L0B = 256'h0; - parameter [255:0] L0C = 256'h0; - parameter [255:0] L0D = 256'h0; - parameter [255:0] L0E = 256'h0; - parameter [255:0] L0F = 256'h0; - parameter [255:0] L10 = 256'h0; - parameter [255:0] L11 = 256'h0; - parameter [255:0] L12 = 256'h0; - parameter [255:0] L13 = 256'h0; - parameter [255:0] L14 = 256'h0; - parameter [255:0] L15 = 256'h0; - parameter [255:0] L16 = 256'h0; - parameter [255:0] L17 = 256'h0; - parameter [255:0] L18 = 256'h0; - parameter [255:0] L19 = 256'h0; - parameter [255:0] L1A = 256'h0; - parameter [255:0] L1B = 256'h0; - parameter [255:0] L1C = 256'h0; - parameter [255:0] L1D = 256'h0; - parameter [255:0] L1E = 256'h0; - parameter [255:0] L1F = 256'h0; - parameter [255:0] L20 = 256'h0; - parameter [255:0] L21 = 256'h0; - parameter [255:0] L22 = 256'h0; - parameter [255:0] L23 = 256'h0; - parameter [255:0] L24 = 256'h0; - parameter [255:0] L25 = 256'h0; - parameter [255:0] L26 = 256'h0; - parameter [255:0] L27 = 256'h0; - parameter [255:0] L28 = 256'h0; - parameter [255:0] L29 = 256'h0; - parameter [255:0] L2A = 256'h0; - parameter [255:0] L2B = 256'h0; - parameter [255:0] L2C = 256'h0; - parameter [255:0] L2D = 256'h0; - parameter [255:0] L2E = 256'h0; - parameter [255:0] L2F = 256'h0; - parameter [255:0] L30 = 256'h0; - parameter [255:0] L31 = 256'h0; - parameter [255:0] L32 = 256'h0; - parameter [255:0] L33 = 256'h0; - parameter [255:0] L34 = 256'h0; - parameter [255:0] L35 = 256'h0; - parameter [255:0] L36 = 256'h0; - parameter [255:0] L37 = 256'h0; - parameter [255:0] L38 = 256'h0; - parameter [255:0] L39 = 256'h0; - parameter [255:0] L3A = 256'h0; - parameter [255:0] L3B = 256'h0; - parameter [255:0] L3C = 256'h0; - parameter [255:0] L3D = 256'h0; - parameter [255:0] L3E = 256'h0; - parameter [255:0] L3F = 256'h0; - parameter [255:0] A0 = 256'h0; - parameter [255:0] A1 = 256'h0; - parameter [255:0] A2 = 256'h0; + parameter [255:0] L00 = 256'h0; + parameter [255:0] L01 = 256'h0; + parameter [255:0] L02 = 256'h0; + parameter [255:0] L03 = 256'h0; + parameter [255:0] L04 = 256'h0; + parameter [255:0] L05 = 256'h0; + parameter [255:0] L06 = 256'h0; + parameter [255:0] L07 = 256'h0; + parameter [255:0] L08 = 256'h0; + parameter [255:0] L09 = 256'h0; + parameter [255:0] L0A = 256'h0; + parameter [255:0] L0B = 256'h0; + parameter [255:0] L0C = 256'h0; + parameter [255:0] L0D = 256'h0; + parameter [255:0] L0E = 256'h0; + parameter [255:0] L0F = 256'h0; + parameter [255:0] L10 = 256'h0; + parameter [255:0] L11 = 256'h0; + parameter [255:0] L12 = 256'h0; + parameter [255:0] L13 = 256'h0; + parameter [255:0] L14 = 256'h0; + parameter [255:0] L15 = 256'h0; + parameter [255:0] L16 = 256'h0; + parameter [255:0] L17 = 256'h0; + parameter [255:0] L18 = 256'h0; + parameter [255:0] L19 = 256'h0; + parameter [255:0] L1A = 256'h0; + parameter [255:0] L1B = 256'h0; + parameter [255:0] L1C = 256'h0; + parameter [255:0] L1D = 256'h0; + parameter [255:0] L1E = 256'h0; + parameter [255:0] L1F = 256'h0; + parameter [255:0] L20 = 256'h0; + parameter [255:0] L21 = 256'h0; + parameter [255:0] L22 = 256'h0; + parameter [255:0] L23 = 256'h0; + parameter [255:0] L24 = 256'h0; + parameter [255:0] L25 = 256'h0; + parameter [255:0] L26 = 256'h0; + parameter [255:0] L27 = 256'h0; + parameter [255:0] L28 = 256'h0; + parameter [255:0] L29 = 256'h0; + parameter [255:0] L2A = 256'h0; + parameter [255:0] L2B = 256'h0; + parameter [255:0] L2C = 256'h0; + parameter [255:0] L2D = 256'h0; + parameter [255:0] L2E = 256'h0; + parameter [255:0] L2F = 256'h0; + parameter [255:0] L30 = 256'h0; + parameter [255:0] L31 = 256'h0; + parameter [255:0] L32 = 256'h0; + parameter [255:0] L33 = 256'h0; + parameter [255:0] L34 = 256'h0; + parameter [255:0] L35 = 256'h0; + parameter [255:0] L36 = 256'h0; + parameter [255:0] L37 = 256'h0; + parameter [255:0] L38 = 256'h0; + parameter [255:0] L39 = 256'h0; + parameter [255:0] L3A = 256'h0; + parameter [255:0] L3B = 256'h0; + parameter [255:0] L3C = 256'h0; + parameter [255:0] L3D = 256'h0; + parameter [255:0] L3E = 256'h0; + parameter [255:0] L3F = 256'h0; + parameter [255:0] A0 = 256'h0; + parameter [255:0] A1 = 256'h0; + parameter [255:0] A2 = 256'h0; - always @ (posedge clk) begin - end + always @ (posedge clk) begin + end endmodule diff --git a/test_regress/t/t_param_mem_attr.v b/test_regress/t/t_param_mem_attr.v index 3ffa00f87..2cf67f21b 100644 --- a/test_regress/t/t_param_mem_attr.v +++ b/test_regress/t/t_param_mem_attr.v @@ -16,27 +16,28 @@ // SPDX-FileCopyrightText: 2012 Jie Xu // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - wire [71:0] ctrl; - wire [7:0] cl; // this line is added +module t ( + input clk +); - memory #(.WORDS(72)) i_memory (.clk (clk)); + wire [71:0] ctrl; + wire [7:0] cl; // this line is added - assign ctrl = i_memory.mem[0]; - assign cl = i_memory.mem[0][7:0]; // and this line + memory #(.WORDS(72)) i_memory (.clk(clk)); + + assign ctrl = i_memory.mem[0]; + assign cl = i_memory.mem[0][7:0]; // and this line endmodule // memory module, which is used with parameter -module memory (clk); - input clk; +module memory ( + clk +); + input clk; - parameter WORDS = 16384, BITS = 72; + parameter WORDS = 16384, BITS = 72; - reg [BITS-1 :0] mem[WORDS-1 : 0]; + reg [BITS-1 : 0] mem[WORDS-1 : 0]; endmodule diff --git a/test_regress/t/t_param_mintypmax.v b/test_regress/t/t_param_mintypmax.v index 3e1dec67a..8c5d78a44 100644 --- a/test_regress/t/t_param_mintypmax.v +++ b/test_regress/t/t_param_mintypmax.v @@ -6,25 +6,27 @@ module t; - parameter MTM = (1:2:3); + parameter MTM = (1: 2: 3); - sub sub (); - //UNSUP sub #(.MTM(10:20:30)) sub20name (); - //UNSUP sub #(.MTM(100:200)) sub200name (); - //UNSUP sub #(10:20:30) sub20pos (); - //UNSUP sub #(100:200) sub200pos (); + sub sub (); + //UNSUP sub #(.MTM(10:20:30)) sub20name (); + //UNSUP sub #(.MTM(100:200)) sub200name (); + //UNSUP sub #(10:20:30) sub20pos (); + //UNSUP sub #(100:200) sub200pos (); - initial begin - if (MTM != 2) $stop; - //UNSUP if (sub20pos.MTM != 20) $stop; - //UNSUP if (sub200pos.MTM != 200) $stop; - //UNSUP if (sub20name.MTM != 20) $stop; - //UNSUP if (sub200name.MTM != 200) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (MTM != 2) $stop; + //UNSUP if (sub20pos.MTM != 20) $stop; + //UNSUP if (sub200pos.MTM != 200) $stop; + //UNSUP if (sub20name.MTM != 20) $stop; + //UNSUP if (sub200name.MTM != 200) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub #(parameter MTM = (1:2:3)) (); +module sub #( + parameter MTM = (1: 2: 3) +) (); endmodule diff --git a/test_regress/t/t_param_module.v b/test_regress/t/t_param_module.v index cb329a82d..8ef384407 100644 --- a/test_regress/t/t_param_module.v +++ b/test_regress/t/t_param_module.v @@ -16,41 +16,41 @@ // bug606 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - localparam logic[4:0] WID = 16; + localparam logic [4:0] WID = 16; //localparam WID = 16; // No problem if defined like this wire [15:0] b33; - test #(WID) i_test_33(.clk (clk), - .b (b33)); + test #(WID) i_test_33 ( + .clk(clk), + .b(b33) + ); endmodule -module test (/*AUTOARG*/ - //Inputs - clk, - // Outputs - b - ); - parameter WIDTH = 10; - localparam MSB = WIDTH - 1; +module test ( /*AUTOARG*/ + //Inputs + clk, + // Outputs + b +); + parameter WIDTH = 10; + localparam MSB = WIDTH - 1; - input clk; - output wire [MSB:0] b; + input clk; + output wire [MSB:0] b; - wire [MSB:0] a; - assign b = {~a[MSB-1:0], clk}; + wire [MSB:0] a; + assign b = {~a[MSB-1:0], clk}; - initial begin - if ($bits(WIDTH)!=5) $stop; // Comes from the parent! - if ($bits(MSB)!=32) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if ($bits(WIDTH) != 5) $stop; // Comes from the parent! + if ($bits(MSB) != 32) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_named.v b/test_regress/t/t_param_named.v index f702bc05e..95c502522 100644 --- a/test_regress/t/t_param_named.v +++ b/test_regress/t/t_param_named.v @@ -4,53 +4,52 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - parameter PAR = 3; - input clk; +module t ( + input clk +); - defparam m3.FROMDEFP = 19; + parameter PAR = 3; - m3 #(.P3(PAR), - .P2(2)) - m3(.clk(clk)); + defparam m3.FROMDEFP = 19; - integer cyc=1; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + m3 #( + .P3(PAR), + .P2(2) + ) m3 ( + .clk(clk) + ); + + integer cyc = 1; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module m3 - #( - parameter UNCH = 99, - parameter P1 = 10, - parameter P2 = 20, - P3 = 30, - parameter FROMDEFP = 11 - ) - (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - localparam LOC = 13; +module m3 #( + parameter UNCH = 99, + parameter P1 = 10, + parameter P2 = 20, + P3 = 30, + parameter FROMDEFP = 11 +) ( + input clk +); - initial begin - $display("%x %x %x",P1,P2,P3); - end - always @ (posedge clk) begin - if (UNCH !== 99) $stop; - if (P1 !== 10) $stop; - if (P2 !== 2) $stop; - if (P3 !== 3) $stop; - if (FROMDEFP !== 19) $stop; - end + localparam LOC = 13; + + initial begin + $display("%x %x %x", P1, P2, P3); + end + always @(posedge clk) begin + if (UNCH !== 99) $stop; + if (P1 !== 10) $stop; + if (P2 !== 2) $stop; + if (P3 !== 3) $stop; + if (FROMDEFP !== 19) $stop; + end endmodule diff --git a/test_regress/t/t_param_named_2.v b/test_regress/t/t_param_named_2.v index 603a3eefc..a9f1b95a4 100644 --- a/test_regress/t/t_param_named_2.v +++ b/test_regress/t/t_param_named_2.v @@ -4,53 +4,49 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - parameter PAR = 3; - input clk; +module t ( + input clk +); - m3 m3_inst (.clk(clk)); - defparam m3_inst.FROMDEFP = 19; - defparam m3_inst.P2 = 2; - //defparam m3_inst.P3 = PAR; - defparam m3_inst.P3 = 3; + parameter PAR = 3; - integer cyc=1; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + m3 m3_inst (.clk(clk)); + defparam m3_inst.FROMDEFP = 19; defparam m3_inst.P2 = 2; + //defparam m3_inst.P3 = PAR; + defparam m3_inst.P3 = 3; + + integer cyc = 1; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module m3 - (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - localparam LOC = 13; +module m3 ( + input clk +); - parameter UNCH = 99; - parameter P1 = 10; - parameter P2 = 20; - parameter P3 = 30; + localparam LOC = 13; - parameter FROMDEFP = 11; + parameter UNCH = 99; + parameter P1 = 10; + parameter P2 = 20; + parameter P3 = 30; - initial begin - $display("%x %x %x",P1,P2,P3); - end - always @ (posedge clk) begin - if (UNCH !== 99) $stop; - if (P1 !== 10) $stop; - if (P2 !== 2) $stop; - if (P3 !== 3) $stop; - if (FROMDEFP !== 19) $stop; - end + parameter FROMDEFP = 11; + + initial begin + $display("%x %x %x", P1, P2, P3); + end + always @(posedge clk) begin + if (UNCH !== 99) $stop; + if (P1 !== 10) $stop; + if (P2 !== 2) $stop; + if (P3 !== 3) $stop; + if (FROMDEFP !== 19) $stop; + end endmodule diff --git a/test_regress/t/t_param_no_parentheses.v b/test_regress/t/t_param_no_parentheses.v index 66c3fb904..3a24d5471 100644 --- a/test_regress/t/t_param_no_parentheses.v +++ b/test_regress/t/t_param_no_parentheses.v @@ -8,68 +8,68 @@ // removed. module t (/*AUTOARG*/ - // Inputs - clk - ); - parameter PAR = 3; + // Inputs + clk + ); + parameter PAR = 3; - m1 #PAR m1(); - m3 #PAR m3(); - mnooverride #10 mno(); + m1 #PAR m1(); + m3 #PAR m3(); + mnooverride #10 mno(); - input clk; - integer cyc=1; - reg [4:0] bitsel; + input clk; + integer cyc=1; + reg [4:0] bitsel; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - bitsel = 0; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 1; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 2; - if (PAR[bitsel]!==1'b0) $stop; - end - if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; + end + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module m1; - localparam PAR1MINUS1 = PAR1DUP-2-1; - localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly - parameter PAR1 = 0; - m2 #PAR1MINUS1 m2 (); + localparam PAR1MINUS1 = PAR1DUP-2-1; + localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #PAR1MINUS1 m2 (); endmodule module m2; - parameter PAR2 = 10; - initial begin - $display("%x",PAR2); - if (PAR2 !== 2) $stop; - end + parameter PAR2 = 10; + initial begin + $display("%x",PAR2); + if (PAR2 !== 2) $stop; + end endmodule module m3; - localparam LOC = 13; - parameter PAR = 10; - initial begin - $display("%x %x",LOC,PAR); - if (LOC !== 13) $stop; - if (PAR !== 3) $stop; - end + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end endmodule module mnooverride; - localparam LOC = 13; - parameter PAR = 10; - initial begin - $display("%x %x",LOC,PAR); - if (LOC !== 13) $stop; - if (PAR !== 10) $stop; - end + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end endmodule diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out index a27d9aed2..b5348fcf4 100644 --- a/test_regress/t/t_param_noval_bad.out +++ b/test_regress/t/t_param_noval_bad.out @@ -7,27 +7,27 @@ : ... note: In instance 't' 7 | module t #(parameter P, parameter type T); | ^ -%Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. +%Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:5: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. : ... note: In instance 't' - 10 | for (j=0; P; j++) - | ^~~ + 10 | for (j=0; P; j++) + | ^~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' +%Error: t/t_param_noval_bad.v:10:5: Non-genvar used in generate for: 'j' : ... note: In instance 't' - 10 | for (j=0; P; j++) - | ^~~ -%Error: t/t_param_noval_bad.v:10:7: Loop unrolling failed. + 10 | for (j=0; P; j++) + | ^~~ +%Error: t/t_param_noval_bad.v:10:5: Loop unrolling failed. : ... note: In instance 't' - 10 | for (j=0; P; j++) - | ^~~ -%Error-UNSUPPORTED: t/t_param_noval_bad.v:10:7: Unsupported: Can't unroll generate for; Unable to unroll loop + 10 | for (j=0; P; j++) + | ^~~ +%Error-UNSUPPORTED: t/t_param_noval_bad.v:10:5: Unsupported: Can't unroll generate for; Unable to unroll loop : ... note: In instance 't' - 10 | for (j=0; P; j++) - | ^~~ + 10 | for (j=0; P; j++) + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_param_noval_bad.v:10:7: For loop doesn't have genvar index, or is malformed +%Error: t/t_param_noval_bad.v:10:5: For loop doesn't have genvar index, or is malformed : ... note: In instance 't' - 10 | for (j=0; P; j++) - | ^~~ + 10 | for (j=0; P; j++) + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_noval_bad.v b/test_regress/t/t_param_noval_bad.v index 1a78f3561..4f96d0e50 100644 --- a/test_regress/t/t_param_noval_bad.v +++ b/test_regress/t/t_param_noval_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t #(parameter P, parameter type T); - generate - var j; - for (j=0; P; j++) - initial begin end - endgenerate + generate + var j; + for (j=0; P; j++) + initial begin end + endgenerate endmodule diff --git a/test_regress/t/t_param_package.v b/test_regress/t/t_param_package.v index 9931091cc..221c9c0b7 100644 --- a/test_regress/t/t_param_package.v +++ b/test_regress/t/t_param_package.v @@ -4,23 +4,27 @@ // SPDX-License-Identifier: CC0-1.0 module t; - Test0 t0 (.val0('0)); - Test1 t1 (.val1('0)); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + Test0 t0 (.val0('0)); + Test1 t1 (.val1('0)); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule package params; - parameter P = 7; + parameter P = 7; endpackage -module Test0 (val0); - parameter Z = 1; - input [Z : 0] val0; +module Test0 ( + val0 +); + parameter Z = 1; + input [Z : 0] val0; endmodule -module Test1 (val1); - input logic [params::P : 0] val1; // Fully qualified parameter +module Test1 ( + val1 +); + input logic [params::P : 0] val1; // Fully qualified parameter endmodule diff --git a/test_regress/t/t_param_passed_to_port.v b/test_regress/t/t_param_passed_to_port.v index ff971ed03..bc9de4a2f 100644 --- a/test_regress/t/t_param_passed_to_port.v +++ b/test_regress/t/t_param_passed_to_port.v @@ -7,19 +7,19 @@ parameter int HwDataAttr[1] = '{1}; module flash_mp_data_region_sel ( - input int region_attrs_i[1] + input int region_attrs_i[1] ); - initial begin - automatic int o = 0; - for (int i = 0; i < 1; i++) begin - o = region_attrs_i[i]; - end - if (o != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic int o = 0; + for (int i = 0; i < 1; i++) begin + o = region_attrs_i[i]; + end + if (o != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module t; - flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr)); + flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr)); endmodule diff --git a/test_regress/t/t_param_pattern.v b/test_regress/t/t_param_pattern.v index 7eca40b3f..eb0470be9 100644 --- a/test_regress/t/t_param_pattern.v +++ b/test_regress/t/t_param_pattern.v @@ -4,43 +4,43 @@ // SPDX-FileCopyrightText: 2021 Krzysztof Bieganski // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package config_pkg; - typedef struct packed { - int UPPER0; - int UPPER2; - int USE_QUAD0; - int USE_QUAD1; - int USE_QUAD2; - } config_struct_t; + typedef struct packed { + int UPPER0; + int UPPER2; + int USE_QUAD0; + int USE_QUAD1; + int USE_QUAD2; + } config_struct_t; endpackage module t; - import config_pkg::*; + import config_pkg::*; - struct_submodule #(.MY_CONFIG('{ - UPPER0: 10, - UPPER2: 20, - USE_QUAD0: 4, - USE_QUAD1: 5, - USE_QUAD2: 6 - })) a_submodule_I (); + struct_submodule #( + .MY_CONFIG('{UPPER0: 10, UPPER2: 20, USE_QUAD0: 4, USE_QUAD1: 5, USE_QUAD2: 6}) + ) a_submodule_I (); endmodule module struct_submodule import config_pkg::*; - #(parameter config_struct_t MY_CONFIG = '0); +#( + parameter config_struct_t MY_CONFIG = '0 +); - initial begin - `checkd(MY_CONFIG.UPPER0, 10); - `checkd(MY_CONFIG.USE_QUAD0, 4); - `checkd(MY_CONFIG.USE_QUAD1, 5); - `checkd(MY_CONFIG.USE_QUAD2, 6); - `checkd(MY_CONFIG.UPPER2, 20); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `checkd(MY_CONFIG.UPPER0, 10); + `checkd(MY_CONFIG.USE_QUAD0, 4); + `checkd(MY_CONFIG.USE_QUAD1, 5); + `checkd(MY_CONFIG.USE_QUAD2, 6); + `checkd(MY_CONFIG.UPPER2, 20); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v index 1245de47c..60642b079 100644 --- a/test_regress/t/t_param_pattern2.v +++ b/test_regress/t/t_param_pattern2.v @@ -4,19 +4,21 @@ // SPDX-FileCopyrightText: 2021 Ryszard Rozak // SPDX-License-Identifier: CC0-1.0 -module dut - #(parameter int P [5]) - (output int x); - assign x = P[2]; +module dut #( + parameter int P[5] +) ( + output int x +); + assign x = P[2]; endmodule module t; - int o; - dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o)); + int o; + dut #(.P('{1, 2, 3, 4, 5})) u_dut (.x(o)); - initial begin - if (o !== 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (o !== 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_pattern_init.v b/test_regress/t/t_param_pattern_init.v index 2a40a4134..2b0fd91d1 100644 --- a/test_regress/t/t_param_pattern_init.v +++ b/test_regress/t/t_param_pattern_init.v @@ -4,102 +4,88 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package some_pkg; - localparam FOO = 5; - localparam BAR = 6; + localparam FOO = 5; + localparam BAR = 6; - typedef enum int { - QUX = 7 - } pkg_enum_t; + typedef enum int {QUX = 7} pkg_enum_t; endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; + int cyc = 0; - localparam int unsigned SPI_INDEX = 0; - localparam int unsigned I2C_INDEX = 1; - localparam int unsigned TMR_INDEX = 4; + localparam int unsigned SPI_INDEX = 0; + localparam int unsigned I2C_INDEX = 1; + localparam int unsigned TMR_INDEX = 4; - localparam logic [31:0] AHB_ADDR[6] = '{ + localparam logic [31:0] AHB_ADDR[6] = '{ SPI_INDEX: 32'h80001000, I2C_INDEX: 32'h80002000, TMR_INDEX: 32'h80003000, - default: '0}; + default: '0 + }; - initial begin - `checkh(AHB_ADDR[0], 32'h80001000); - `checkh(AHB_ADDR[1], 32'h80002000); - `checkh(AHB_ADDR[2], 32'h0); - `checkh(AHB_ADDR[3], 32'h0); - `checkh(AHB_ADDR[4], 32'h80003000); - `checkh(AHB_ADDR[5], 32'h0); - end + initial begin + `checkh(AHB_ADDR[0], 32'h80001000); + `checkh(AHB_ADDR[1], 32'h80002000); + `checkh(AHB_ADDR[2], 32'h0); + `checkh(AHB_ADDR[3], 32'h0); + `checkh(AHB_ADDR[4], 32'h80003000); + `checkh(AHB_ADDR[5], 32'h0); + end - genvar genvar_i; - for (genvar_i = 0; genvar_i < 2; genvar_i++) begin: the_gen - logic [31:0] gen_array [10]; + genvar genvar_i; + for (genvar_i = 0; genvar_i < 2; genvar_i++) begin : the_gen + logic [31:0] gen_array[10]; - always_comb gen_array = '{ - genvar_i: 32'habcd, - default: 0 - }; - - always_ff @(posedge clk) begin - `checkh(gen_array[genvar_i], 32'habcd); - end - end - - typedef enum int { - ENUM_A = 0, - ENUM_B, - ENUM_C - } enum_t; - - logic [31:0] enum_array [11]; - - always_comb enum_array = '{ - ENUM_A: 32'h1234, - ENUM_B: 32'h7777, - ENUM_C: 32'ha5a5, - default: 0 - }; + always_comb gen_array = '{genvar_i: 32'habcd, default: 0}; always_ff @(posedge clk) begin - `checkh(enum_array[0], 32'h1234); - `checkh(enum_array[1], 32'h7777); - `checkh(enum_array[2], 32'ha5a5); + `checkh(gen_array[genvar_i], 32'habcd); end + end - logic [31:0] package_array [8]; + typedef enum int { + ENUM_A = 0, + ENUM_B, + ENUM_C + } enum_t; - import some_pkg::*; - always_comb package_array = '{ - FOO: 32'h9876, - BAR: 32'h1212, - QUX: 32'h5432, - default: 0 - }; + logic [31:0] enum_array[11]; - always_ff @(posedge clk) begin - `checkh(package_array[5], 32'h9876); - `checkh(package_array[6], 32'h1212); - `checkh(package_array[7], 32'h5432); + always_comb enum_array = '{ENUM_A: 32'h1234, ENUM_B: 32'h7777, ENUM_C: 32'ha5a5, default: 0}; + + always_ff @(posedge clk) begin + `checkh(enum_array[0], 32'h1234); + `checkh(enum_array[1], 32'h7777); + `checkh(enum_array[2], 32'ha5a5); + end + + logic [31:0] package_array[8]; + + import some_pkg::*; + always_comb package_array = '{FOO: 32'h9876, BAR: 32'h1212, QUX: 32'h5432, default: 0}; + + always_ff @(posedge clk) begin + `checkh(package_array[5], 32'h9876); + `checkh(package_array[6], 32'h1212); + `checkh(package_array[7], 32'h5432); + end + + always_ff @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + $write("*-* All Finished *-*\n"); + $finish; end - - always_ff @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end endmodule diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v index e8d3a8198..e53caae71 100644 --- a/test_regress/t/t_param_public.v +++ b/test_regress/t/t_param_public.v @@ -8,35 +8,35 @@ module t; - parameter TOP_PARAM /*verilator public*/ = 20; + parameter TOP_PARAM /*verilator public*/ = 20; - a #(1) a1 (); - b #(2) b2 (); + a #(1) a1 (); + b #(2) b2 (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module a; - parameter ONE /*verilator public*/ = 22; - initial if (ONE != 1) $stop; + parameter ONE /*verilator public*/ = 22; + initial if (ONE != 1) $stop; `ifdef VERILATOR - initial if ($c32("this->ONE") != 1) $stop; + initial if ($c32("this->ONE") != 1) $stop; `endif endmodule module b #( - parameter TWO /*verilator public*/ = 22 - ); - initial if (TWO != 2) $stop; + parameter TWO /*verilator public*/ = 22 +); + initial if (TWO != 2) $stop; `ifdef VERILATOR - initial if ($c32("this->TWO") != 2) $stop; + initial if ($c32("this->TWO") != 2) $stop; `endif endmodule //bug804 package p; - localparam INPACK /*verilator public*/ = 6; + localparam INPACK /*verilator public*/ = 6; endpackage diff --git a/test_regress/t/t_param_real.v b/test_regress/t/t_param_real.v index 543e317d7..94b8a2111 100644 --- a/test_regress/t/t_param_real.v +++ b/test_regress/t/t_param_real.v @@ -7,21 +7,21 @@ module mod #( parameter real HZ = 0 ); - //verilator no_inline_module - initial begin - if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; - if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; - end + //verilator no_inline_module + initial begin + if ((HZ - $floor(HZ)) - 0.45 > 0.01) $stop; + if ((HZ - $floor(HZ)) - 0.45 < -0.01) $stop; + end endmodule module t; - mod #(.HZ(123.45)) mod1(); - mod #(.HZ(24.45)) mod2(); + mod #(.HZ(123.45)) mod1 (); + mod #(.HZ(24.45)) mod2 (); - initial begin - if (mod1.HZ != 123.45) $stop; - if (mod2.HZ != 24.45) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (mod1.HZ != 123.45) $stop; + if (mod2.HZ != 24.45) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_real2.v b/test_regress/t/t_param_real2.v index 03f225549..ba646661d 100644 --- a/test_regress/t/t_param_real2.v +++ b/test_regress/t/t_param_real2.v @@ -3,35 +3,34 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module foo -#( parameter real BAR = 2.0) -(); +module foo #( + parameter real BAR = 2.0 +) (); endmodule module t; - genvar m, r; - generate - for (m = 10; m <= 20; m+=10) begin : gen_m - for (r = 0; r <= 1; r++) begin : gen_r - localparam real LPARAM = m + (r + 0.5); - initial begin - if (LPARAM != foo_inst.BAR) begin - $display("%m: LPARAM != foo_inst.BAR (%f, %f)", - LPARAM, foo_inst.BAR); - $stop(); - end - end + genvar m, r; + generate + for (m = 10; m <= 20; m += 10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real LPARAM = m + (r + 0.5); + initial begin + if (LPARAM != foo_inst.BAR) begin + $display("%m: LPARAM != foo_inst.BAR (%f, %f)", LPARAM, foo_inst.BAR); + $stop(); + end + end - foo #(.BAR (LPARAM)) foo_inst (); - end + foo #(.BAR(LPARAM)) foo_inst (); end - endgenerate + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 7743ecfd1..24671ef1a 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -4,48 +4,44 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - parameter [31:0] TWENTY4 = 24; - parameter [31:0] PA = TWENTY4/8; - parameter [1:0] VALUE = 2'b10; - parameter [5:0] REPL = {PA{VALUE}}; - parameter [7:0] CONC = {REPL,VALUE}; + parameter [31:0] TWENTY4 = 24; + parameter [31:0] PA = TWENTY4 / 8; + parameter [1:0] VALUE = 2'b10; + parameter [5:0] REPL = {PA{VALUE}}; + parameter [7:0] CONC = {REPL, VALUE}; - parameter DBITS = 32; - parameter INIT_BYTE = 8'h1F; - parameter DWORDS_LOG2 = 7; - parameter DWORDS = (1<> M; - endfunction + function [M:0] gen_matrix; + gen_matrix[0] = 1 >> M; + endfunction - reg [95: 0] lfsr = 0; - always @(posedge clk) begin - lfsr <= (1 >> P); - end + reg [95:0] lfsr = 0; + always @(posedge clk) begin + lfsr <= (1 >> P); + end - wire [95: 0] lfsr_w = 1 >> P; + wire [95:0] lfsr_w = 1 >> P; - localparam [95: 0] LFSR_P = 1 >> P; + localparam [95:0] LFSR_P = 1 >> P; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_store_bad.out b/test_regress/t/t_param_store_bad.out index a77a55464..21edec1db 100644 --- a/test_regress/t/t_param_store_bad.out +++ b/test_regress/t/t_param_store_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_store_bad.v:12:31: Storing to parameter variable 'S' in a context that is determined only at runtime - 12 | $value$plusargs("S=%s", S); - | ^ +%Error: t/t_param_store_bad.v:12:29: Storing to parameter variable 'S' in a context that is determined only at runtime + 12 | $value$plusargs("S=%s", S); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_store_bad.v b/test_regress/t/t_param_store_bad.v index 4dff59398..4f387c4d1 100644 --- a/test_regress/t/t_param_store_bad.v +++ b/test_regress/t/t_param_store_bad.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t #( - string S = "" - ); + string S = "" +); - initial begin - $value$plusargs("S=%s", S); // BAD assignment to S - #1; // Original bug got compile time error only with this line - $display("S=%s", S); - $finish; - end + initial begin + $value$plusargs("S=%s", S); // BAD assignment to S + #1; // Original bug got compile time error only with this line + $display("S=%s", S); + $finish; + end endmodule diff --git a/test_regress/t/t_param_type.v b/test_regress/t/t_param_type.v index 088f387ed..faee6c646 100644 --- a/test_regress/t/t_param_type.v +++ b/test_regress/t/t_param_type.v @@ -4,90 +4,88 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // counters + int cnt; + int cnt_bit; + int cnt_byte; + int cnt_int; + int cnt_ar1d; + int cnt_ar2d; - // counters - int cnt; - int cnt_bit ; - int cnt_byte; - int cnt_int ; - int cnt_ar1d; - int cnt_ar2d; + // sizes + int siz_bit; + int siz_byte; + int siz_int; + int siz_ar1d; + int siz_ar2d; - // sizes - int siz_bit ; - int siz_byte; - int siz_int ; - int siz_ar1d; - int siz_ar2d; + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; - // add all counters - assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; - - // finish report - always @ (posedge clk) - if (cnt == 5) begin - if (siz_bit != 1) $stop(); - if (siz_byte != 8) $stop(); - if (siz_int != 32) $stop(); - if (siz_ar1d != 24) $stop(); - if (siz_ar2d != 16) $stop(); - end else if (cnt > 5) begin + // finish report + always @(posedge clk) + if (cnt == 5) begin + if (siz_bit != 1) $stop(); + if (siz_byte != 8) $stop(); + if (siz_int != 32) $stop(); + if (siz_ar1d != 24) $stop(); + if (siz_ar2d != 16) $stop(); + end + else if (cnt > 5) begin $write("*-* All Finished *-*\n"); $finish; - end + end - // instances with various types - mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); - mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); - mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); - mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); - mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + // instances with various types + // verilog_format: off + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); - // double types - mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3(); - mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5(); + // double types + mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3(); + mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5(); + // verilog_format: on endmodule : t module mod_typ #( - parameter type TYP = byte -)( - input logic clk, - output TYP cnt, - output int siz + parameter type TYP = byte +) ( + input logic clk, + output TYP cnt, + output int siz ); - initial cnt = 0; + initial cnt = 0; - always @ (posedge clk) - cnt <= cnt + 1; + always @(posedge clk) cnt <= cnt + 1; - assign siz = $bits (cnt); + assign siz = $bits(cnt); endmodule -module mod_typ2 - #( +module mod_typ2 #( parameter int WIDTH1 = 0, parameter int WIDTH2 = WIDTH1, parameter type TYP1 = byte, // Below we need to imply that TYP2 is a type TYP2 = TYP1 - )(); +) (); - TYP1 t1; - TYP2 t2; + TYP1 t1; + TYP2 t2; - initial begin - if ($bits(t1) != WIDTH1) $stop; - if ($bits(t2) != WIDTH2) $stop; - end + initial begin + if ($bits(t1) != WIDTH1) $stop; + if ($bits(t2) != WIDTH2) $stop; + end endmodule diff --git a/test_regress/t/t_param_type2.v b/test_regress/t/t_param_type2.v index 498e3b9d1..21385b83f 100644 --- a/test_regress/t/t_param_type2.v +++ b/test_regress/t/t_param_type2.v @@ -5,37 +5,43 @@ // SPDX-License-Identifier: CC0-1.0 package tt_pkg; - typedef enum logic [1:0] {L0, L1, L2, L3} test_t; + typedef enum logic [1:0] { + L0, + L1, + L2, + L3 + } test_t; endpackage -module t (/*AUTOARG*/ - // Outputs - ob - ); +module t ( /*AUTOARG*/ + // Outputs + ob +); - output [1:0] ob; + output [1:0] ob; - import tt_pkg::*; + import tt_pkg::*; - test_t a; - test_t b; + test_t a; + test_t b; - assign a = L0; - assign ob = b; + assign a = L0; + assign ob = b; - tt_buf #(.T_t(test_t)) - u_test - (.i(a), .o(b)); + tt_buf #( + .T_t(test_t) + ) u_test ( + .i(a), + .o(b) + ); endmodule -module tt_buf - #( +module tt_buf #( parameter type T_t = logic [0:0] - ) - ( - input T_t i, +) ( + input T_t i, output T_t o - ); - assign o = i; +); + assign o = i; endmodule diff --git a/test_regress/t/t_param_type3.v b/test_regress/t/t_param_type3.v index 1399798fb..f34a90e00 100644 --- a/test_regress/t/t_param_type3.v +++ b/test_regress/t/t_param_type3.v @@ -6,52 +6,59 @@ typedef logic T_t; -module t (/*AUTOARG*/ - // Outputs - o, ob, o2, o2b, - // Inputs - i - ); +module t ( /*AUTOARG*/ + // Outputs + o, + ob, + o2, + o2b, + // Inputs + i +); - input T_t i; - output T_t o, ob, o2, o2b; + input T_t i; + output T_t o, ob, o2, o2b; - sub1 #(.T_t(T_t), .CHECK(1)) - sub1 (.i, .o(o)); + // verilog_format: off + sub1 #(.T_t(T_t), .CHECK(1)) + sub1 (.i, .o(o)); - sub2 #(.T_t(T_t), .CHECK(2)) - sub2 (.i, .o(o2)); + sub2 #(.T_t(T_t), .CHECK(2)) + sub2 (.i, .o(o2)); - sub1 #(T_t, 1) - sub1b (i, ob); + sub1 #(T_t, 1) + sub1b (i, ob); + + sub2 #(T_t, 2) + sub2b (i, o2b); + // verilog_format: on - sub2 #(T_t, 2) - sub2b (i, o2b); endmodule -module sub1 (i,o); - parameter type T_t = real; - localparam type T2_t = T_t; - parameter int CHECK = 0; - input T_t i; - output T2_t o; - assign o = i; - if (CHECK != 1) $error; +module sub1 ( + i, + o +); + parameter type T_t = real; + localparam type T2_t = T_t; + parameter int CHECK = 0; + input T_t i; + output T2_t o; + assign o = i; + if (CHECK != 1) $error; endmodule -module sub2 - #( +module sub2 #( parameter type T_t = real, localparam type T2_t = T_t, parameter int CHECK = 0 - ) - ( - input T_t i, +) ( + input T_t i, output T_t o - ); - assign o = i; - if (CHECK != 2) $error; +); + assign o = i; + if (CHECK != 2) $error; endmodule // Local Variables: diff --git a/test_regress/t/t_param_type4.v b/test_regress/t/t_param_type4.v index 61c515c45..0ef9ed5b3 100644 --- a/test_regress/t/t_param_type4.v +++ b/test_regress/t/t_param_type4.v @@ -4,62 +4,64 @@ // SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire o0, o1; + wire o0, o1; - sub #(1) a(.i(1'b0), .o(o0)); - sub #(2) b(.i(1'b0), .o(o1)); + sub #(1) a ( + .i(1'b0), + .o(o0) + ); + sub #(2) b ( + .i(1'b0), + .o(o1) + ); - always @(posedge clk) begin - if (o0 != 1'b0) begin - $write("Bad o0\n"); - $stop; - end - if (o1 != 1'b1) begin - $write("Bad o1\n"); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (o0 != 1'b0) begin + $write("Bad o0\n"); + $stop; + end + if (o1 != 1'b1) begin + $write("Bad o1\n"); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub - #( +module sub #( parameter int W - ) - ( - input wire i, +) ( + input wire i, output wire o - ); +); - typedef struct packed { - logic [W-1:0] a; - } s; + typedef struct packed {logic [W-1:0] a;} s; - sub2 #(s) c(.i(i), .o(o)); + sub2 #(s) c ( + .i(i), + .o(o) + ); endmodule -module sub2 - # ( - parameter type T = logic - ) - ( - input wire i, +module sub2 #( + parameter type T = logic +) ( + input wire i, output wire o - ); +); - if ($bits(T) % 2 == 1) begin - assign o = i; - end else begin - assign o = ~i; - end + if ($bits(T) % 2 == 1) begin + assign o = i; + end + else begin + assign o = ~i; + end endmodule diff --git a/test_regress/t/t_param_type5.v b/test_regress/t/t_param_type5.v index d5abe3ea9..49c81a535 100644 --- a/test_regress/t/t_param_type5.v +++ b/test_regress/t/t_param_type5.v @@ -4,35 +4,38 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class ParamClass #(string P = "ABC", R = "GDF"); +class ParamClass #( + string P = "ABC", + R = "GDF" +); endclass module t #( - parameter int A = 0, B = 1, C = 2, type D = int, E = string, F = - struct packed { - struct packed { - logic a; - } b; - } + parameter int A = 0, + B = 1, + C = 2, + type D = int, + E = string, + F = struct packed {struct packed {logic a;} b;} ); - parameter bit G = 1'b0, H = 1'b1; - parameter type I = int, J = string; - E str1 = "abc"; - J str2 = ""; + parameter bit G = 1'b0, H = 1'b1; + parameter type I = int, J = string; + E str1 = "abc"; + J str2 = ""; - F struct1; - assign struct1.b.a = 1'b1; + F struct1; + assign struct1.b.a = 1'b1; - initial begin - automatic ParamClass param_class = new; - if ($typename(B) != "int") $stop; - if ($typename(C) != "int") $stop; - if (str1.len() != 3) $stop; - if ($typename(H) != "bit") $stop; - if (str2.len() != 0) $stop; - if ($typename(param_class.R) != "string") $stop; - if ($typename(struct1.b.a) != "MEMBERDTYPE 'a'") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic ParamClass param_class = new; + if ($typename(B) != "int") $stop; + if ($typename(C) != "int") $stop; + if (str1.len() != 3) $stop; + if ($typename(H) != "bit") $stop; + if (str2.len() != 0) $stop; + if ($typename(param_class.R) != "string") $stop; + if ($typename(struct1.b.a) != "MEMBERDTYPE 'a'") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_type6.v b/test_regress/t/t_param_type6.v index 7557e7cb9..fae9d082b 100644 --- a/test_regress/t/t_param_type6.v +++ b/test_regress/t/t_param_type6.v @@ -7,46 +7,45 @@ interface intf #( parameter type the_type = bit ); - the_type foo; + the_type foo; endinterface interface no_param_intf; - logic [13:0] bar; + logic [13:0] bar; endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + intf #(.the_type(logic [7:0])) intf_eight (); + no_param_intf the_no_param_intf (); + sub #( + .TYPE_BITS(8) + ) sub_eight ( + .intf_pin(intf_eight), + .no_param_intf_pin(the_no_param_intf) + ); - intf #(.the_type (logic [7:0])) intf_eight(); - no_param_intf the_no_param_intf(); - sub #(.TYPE_BITS (8)) sub_eight ( - .intf_pin (intf_eight), - .no_param_intf_pin (the_no_param_intf) - ); - - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub #( parameter int TYPE_BITS -)( +) ( intf intf_pin, no_param_intf no_param_intf_pin ); - localparam type intf_type = type(intf_pin.foo); - localparam type no_param_intf_type = type(no_param_intf_pin.bar); - initial begin - if ($bits(intf_type) != TYPE_BITS) $stop(); - if ($bits(no_param_intf_type) != 14) $stop(); - end + localparam type intf_type = type (intf_pin.foo); + localparam type no_param_intf_type = type (no_param_intf_pin.bar); + initial begin + if ($bits(intf_type) != TYPE_BITS) $stop(); + if ($bits(no_param_intf_type) != 14) $stop(); + end endmodule diff --git a/test_regress/t/t_param_type_bad.out b/test_regress/t/t_param_type_bad.out index 68b6bf22f..fe7834e26 100644 --- a/test_regress/t/t_param_type_bad.out +++ b/test_regress/t/t_param_type_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_type_bad.v:9:27: Expecting a data type, not a constant: 2 - 9 | localparam type bad2 = 2; - | ^ +%Error: t/t_param_type_bad.v:9:26: Expecting a data type, not a constant: 2 + 9 | localparam type bad2 = 2; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad.v b/test_regress/t/t_param_type_bad.v index b70983e4e..946053474 100644 --- a/test_regress/t/t_param_type_bad.v +++ b/test_regress/t/t_param_type_bad.v @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam type t = logic; // Fine - localparam type bad2 = 2; // Bad + localparam type t = logic; // Fine + localparam type bad2 = 2; // Bad endmodule diff --git a/test_regress/t/t_param_type_bad2.out b/test_regress/t/t_param_type_bad2.out index 61334d445..b7f870c21 100644 --- a/test_regress/t/t_param_type_bad2.out +++ b/test_regress/t/t_param_type_bad2.out @@ -1,10 +1,10 @@ -%Error: t/t_param_type_bad2.v:8:19: Operator VAR 't' expected non-datatype Initial value but 'logic' is a datatype. +%Error: t/t_param_type_bad2.v:8:18: Operator VAR 't' expected non-datatype Initial value but 'logic' is a datatype. : ... note: In instance 't' - 8 | localparam t = logic; - | ^~~~~ + 8 | localparam t = logic; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_param_type_bad2.v:9:20: Operator VAR 't2' expected non-datatype Initial value but 'real' is a datatype. +%Error: t/t_param_type_bad2.v:9:19: Operator VAR 't2' expected non-datatype Initial value but 'real' is a datatype. : ... note: In instance 't' - 9 | localparam t2 = realtime; - | ^~~~~~~~ + 9 | localparam t2 = realtime; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad2.v b/test_regress/t/t_param_type_bad2.v index 8a78237e9..c805512c5 100644 --- a/test_regress/t/t_param_type_bad2.v +++ b/test_regress/t/t_param_type_bad2.v @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam t = logic; // Bad - localparam t2 = realtime; // Bad + localparam t = logic; // Bad + localparam t2 = realtime; // Bad endmodule diff --git a/test_regress/t/t_param_type_bad3.out b/test_regress/t/t_param_type_bad3.out index 0350e5cb2..2fd91fa1c 100644 --- a/test_regress/t/t_param_type_bad3.out +++ b/test_regress/t/t_param_type_bad3.out @@ -1,5 +1,5 @@ -%Error: t/t_param_type_bad3.v:9:26: Expecting a data type, not VARREF: 'PI' - 9 | localparam type P_T = PI; - | ^~ +%Error: t/t_param_type_bad3.v:9:25: Expecting a data type, not VARREF: 'PI' + 9 | localparam type P_T = PI; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad3.v b/test_regress/t/t_param_type_bad3.v index 98b91ab2d..9b8b8f81a 100644 --- a/test_regress/t/t_param_type_bad3.v +++ b/test_regress/t/t_param_type_bad3.v @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam int PI = 6; - localparam type P_T = PI; // Bad + localparam int PI = 6; + localparam type P_T = PI; // Bad endmodule diff --git a/test_regress/t/t_param_type_bit.v b/test_regress/t/t_param_type_bit.v index b5bd12f51..276333f72 100644 --- a/test_regress/t/t_param_type_bit.v +++ b/test_regress/t/t_param_type_bit.v @@ -8,18 +8,18 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub sub(); + sub sub(); endmodule module sub #(parameter type T = type(bit[9:0]) ) - (); + (); - type(bit[9:0]) tvar; + type(bit[9:0]) tvar; - initial begin - if ($bits(T) != 10) $stop; - if ($bits(tvar) != 10) $stop; - $finish; - end + initial begin + if ($bits(T) != 10) $stop; + if ($bits(tvar) != 10) $stop; + $finish; + end endmodule diff --git a/test_regress/t/t_param_type_cmp.v b/test_regress/t/t_param_type_cmp.v index 99ce7ad7b..b4b59aea5 100644 --- a/test_regress/t/t_param_type_cmp.v +++ b/test_regress/t/t_param_type_cmp.v @@ -6,44 +6,54 @@ module t; - logic [2:0] a; - logic [2:0] b; + logic [2:0] a; + logic [2:0] b; - logic signed_out; - logic unsigned_out; + logic signed_out; + logic unsigned_out; - cmp #(.element_type(logic signed [2:0])) signed_cmp (.a(a), .b(b), .c(signed_out)); - cmp #(.element_type(logic [2:0])) unsigned_cmp (.a(a), .b(b), .c(unsigned_out)); + cmp #( + .element_type(logic signed [2:0]) + ) signed_cmp ( + .a(a), + .b(b), + .c(signed_out) + ); + cmp #( + .element_type(logic [2:0]) + ) unsigned_cmp ( + .a(a), + .b(b), + .c(unsigned_out) + ); - initial a = 3'b001; - initial b = 3'b111; + initial a = 3'b001; + initial b = 3'b111; - initial begin - #1; - if (signed_out !== 1'b0) begin - $display("%%Error: bad signed comparison %b < %b: got=%d exp=%d", a, b, signed_out, 1'b0); - $stop; - end - if (unsigned_out !== 1'b1) begin - $display("%%Error: bad unsigned comparison %b < %b: got=%d exp=%d", a, b, unsigned_out, 1'b1); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #1; + if (signed_out !== 1'b0) begin + $display("%%Error: bad signed comparison %b < %b: got=%d exp=%d", a, b, signed_out, 1'b0); + $stop; + end + if (unsigned_out !== 1'b1) begin + $display("%%Error: bad unsigned comparison %b < %b: got=%d exp=%d", a, b, unsigned_out, 1'b1); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module cmp -#( +module cmp #( parameter type element_type = logic -) -( - input element_type a, - input element_type b, - output logic c +) ( + input element_type a, + input element_type b, + output logic c ); - assign c = a < b; + assign c = a < b; endmodule diff --git a/test_regress/t/t_param_type_fwd.v b/test_regress/t/t_param_type_fwd.v index 4fdab946f..f41da9e51 100644 --- a/test_regress/t/t_param_type_fwd.v +++ b/test_regress/t/t_param_type_fwd.v @@ -17,24 +17,24 @@ interface class ic_t; endclass module sub; - parameter type enum E_t; - parameter type struct S_t; - parameter type union U_t; - parameter type class C_t; - parameter type interface class IC_t; + parameter type enum E_t; + parameter type struct S_t; + parameter type union U_t; + parameter type class C_t; + parameter type interface class IC_t; endmodule class Cls #(parameter type enum E_t, - parameter type struct S_t, - parameter type union U_t, - parameter type class C_t, - parameter type interface class IC_t); + parameter type struct S_t, + parameter type union U_t, + parameter type class C_t, + parameter type interface class IC_t); endclass module t; - sub #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) sub(); - Cls #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) c; - initial begin - c = new; - end + sub #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) sub(); + Cls #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) c; + initial begin + c = new; + end endmodule diff --git a/test_regress/t/t_param_type_fwd_bad.out b/test_regress/t/t_param_type_fwd_bad.out index 42da02e1f..4241604eb 100644 --- a/test_regress/t/t_param_type_fwd_bad.out +++ b/test_regress/t/t_param_type_fwd_bad.out @@ -1,42 +1,42 @@ -%Error: t/t_param_type_fwd_bad.v:25:11: Parameter type expression type 'int' violates parameter's forwarding type 'enum' +%Error: t/t_param_type_fwd_bad.v:25:10: Parameter type expression type 'int' violates parameter's forwarding type 'enum' : ... note: In instance 't' - 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - | ^~~ + 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_param_type_fwd_bad.v:25:24: Parameter type expression type 'int' violates parameter's forwarding type 'struct' +%Error: t/t_param_type_fwd_bad.v:25:23: Parameter type expression type 'int' violates parameter's forwarding type 'struct' : ... note: In instance 't' - 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - | ^~~ -%Error: t/t_param_type_fwd_bad.v:25:37: Parameter type expression type 'int' violates parameter's forwarding type 'union' + 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + | ^~~ +%Error: t/t_param_type_fwd_bad.v:25:36: Parameter type expression type 'int' violates parameter's forwarding type 'union' : ... note: In instance 't' - 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - | ^~~ -%Error: t/t_param_type_fwd_bad.v:25:50: Parameter type expression type 'int' violates parameter's forwarding type 'class' + 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + | ^~~ +%Error: t/t_param_type_fwd_bad.v:25:49: Parameter type expression type 'int' violates parameter's forwarding type 'class' : ... note: In instance 't' - 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - | ^~~ -%Error: t/t_param_type_fwd_bad.v:25:63: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' + 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + | ^~~ +%Error: t/t_param_type_fwd_bad.v:25:62: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' : ... note: In instance 't' - 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - | ^~~~ -%Error: t/t_param_type_fwd_bad.v:26:11: Parameter type expression type 'int' violates parameter's forwarding type 'enum' + 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + | ^~~~ +%Error: t/t_param_type_fwd_bad.v:26:10: Parameter type expression type 'int' violates parameter's forwarding type 'enum' : ... note: In instance 't' - 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - | ^~~ -%Error: t/t_param_type_fwd_bad.v:26:24: Parameter type expression type 'int' violates parameter's forwarding type 'struct' + 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + | ^~~ +%Error: t/t_param_type_fwd_bad.v:26:23: Parameter type expression type 'int' violates parameter's forwarding type 'struct' : ... note: In instance 't' - 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - | ^~~ -%Error: t/t_param_type_fwd_bad.v:26:37: Parameter type expression type 'int' violates parameter's forwarding type 'union' + 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + | ^~~ +%Error: t/t_param_type_fwd_bad.v:26:36: Parameter type expression type 'int' violates parameter's forwarding type 'union' : ... note: In instance 't' - 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - | ^~~ -%Error: t/t_param_type_fwd_bad.v:26:50: Parameter type expression type 'int' violates parameter's forwarding type 'class' + 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + | ^~~ +%Error: t/t_param_type_fwd_bad.v:26:49: Parameter type expression type 'int' violates parameter's forwarding type 'class' : ... note: In instance 't' - 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - | ^~~ -%Error: t/t_param_type_fwd_bad.v:26:63: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' + 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + | ^~~ +%Error: t/t_param_type_fwd_bad.v:26:62: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' : ... note: In instance 't' - 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - | ^~~~ + 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_fwd_bad.v b/test_regress/t/t_param_type_fwd_bad.v index f5333afe9..ef054a9fb 100644 --- a/test_regress/t/t_param_type_fwd_bad.v +++ b/test_regress/t/t_param_type_fwd_bad.v @@ -7,24 +7,24 @@ typedef int int_t; module sub; - parameter type enum E_t; - parameter type struct S_t; - parameter type union U_t; - parameter type class C_t; - parameter type interface class IC_t; + parameter type enum E_t; + parameter type struct S_t; + parameter type union U_t; + parameter type class C_t; + parameter type interface class IC_t; endmodule class Cls #(parameter type enum E_t, - parameter type struct S_t, - parameter type union U_t, - parameter type class C_t, - parameter type interface class IC_t); + parameter type struct S_t, + parameter type union U_t, + parameter type class C_t, + parameter type interface class IC_t); endclass module t; - sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); - Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; - initial begin - c = new; - end + sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); + Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; + initial begin + c = new; + end endmodule diff --git a/test_regress/t/t_param_typedef.v b/test_regress/t/t_param_typedef.v index 796d3b9c1..cf5d7510e 100644 --- a/test_regress/t/t_param_typedef.v +++ b/test_regress/t/t_param_typedef.v @@ -10,45 +10,44 @@ module fifo_v3 #( parameter int unsigned DATA_WIDTH = 32, parameter int unsigned DEPTH = 8, parameter type dtype_t = logic [DATA_WIDTH-1:0] -)( +) ( input int data_i, output int data_o ); - if (DEPTH == 0) begin : gen_pass_through - end + if (DEPTH == 0) begin : gen_pass_through + end endmodule module axi_lite_mux #( - parameter int unsigned NoSlvPorts = 32'd32, - parameter int unsigned MaxTrans = 32'd0 + parameter int unsigned NoSlvPorts = 32'd32, + parameter int unsigned MaxTrans = 32'd0 ) ( - input logic clk_i, - input logic rst_ni + input logic clk_i, + input logic rst_ni ); - wire [31:0] ar_select; - wire [31:0] r_select; + wire [31:0] ar_select; + wire [31:0] r_select; - if (NoSlvPorts == 32'h1) begin : gen_no_mux - end - else begin : gen_mux - typedef logic [$clog2(NoSlvPorts)-1:0] select_t; - fifo_v3 #( - .DEPTH ( MaxTrans ), - .dtype_t ( select_t ) - ) - i_r_fifo ( - .data_i ( ar_select ), - .data_o ( r_select ) - ); - end + if (NoSlvPorts == 32'h1) begin : gen_no_mux + end + else begin : gen_mux + typedef logic [$clog2(NoSlvPorts)-1:0] select_t; + fifo_v3 #( + .DEPTH(MaxTrans), + .dtype_t(select_t) + ) i_r_fifo ( + .data_i(ar_select), + .data_o(r_select) + ); + end endmodule -module t - ( - input logic clk_i, - input logic rst_ni - ); - axi_lite_mux i_axi_mux ( - .clk_i, - .rst_ni); +module t ( + input logic clk_i, + input logic rst_ni +); + axi_lite_mux i_axi_mux ( + .clk_i, + .rst_ni + ); endmodule diff --git a/test_regress/t/t_param_unreachable.v b/test_regress/t/t_param_unreachable.v index 67756cce3..d4c0eec5e 100644 --- a/test_regress/t/t_param_unreachable.v +++ b/test_regress/t/t_param_unreachable.v @@ -3,32 +3,34 @@ // SPDX-FileCopyrightText: 2020 Pierre-Henri Horrein // SPDX-License-Identifier: CC0-1.0 -module t (input clk); +module t ( + input clk +); - parameter DEPTH = 1; - reg [DEPTH-1:0] shiftreg_gen; - reg [DEPTH-1:0] shiftreg; - reg my_sr_input = '1; + parameter DEPTH = 1; + reg [DEPTH-1:0] shiftreg_gen; + reg [DEPTH-1:0] shiftreg; + reg my_sr_input = '1; - // shiftreg_gen is generated: it should not raise any warning or error - always_ff @(posedge clk) begin - shiftreg_gen[0] <= my_sr_input; - end - if (DEPTH > 1) begin - always_ff @(posedge clk) begin - shiftreg_gen[DEPTH-1:1] <= shiftreg_gen[DEPTH-2:0]; - end - end - // shiftreg is not generated: it can raise a warning - always_ff @(posedge clk) begin - shiftreg[0] <= my_sr_input; - /* verilator lint_off SELRANGE */ - if (DEPTH > 1) shiftreg[DEPTH-1:1] <= shiftreg[DEPTH-2:0]; - /* verilator lint_on SELRANGE */ - end + // shiftreg_gen is generated: it should not raise any warning or error + always_ff @(posedge clk) begin + shiftreg_gen[0] <= my_sr_input; + end + if (DEPTH > 1) begin + always_ff @(posedge clk) begin + shiftreg_gen[DEPTH-1:1] <= shiftreg_gen[DEPTH-2:0]; + end + end + // shiftreg is not generated: it can raise a warning + always_ff @(posedge clk) begin + shiftreg[0] <= my_sr_input; + /* verilator lint_off SELRANGE */ + if (DEPTH > 1) shiftreg[DEPTH-1:1] <= shiftreg[DEPTH-2:0]; + /* verilator lint_on SELRANGE */ + end - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_up_bad.out b/test_regress/t/t_param_up_bad.out index f8dcf3408..bdbd9349e 100644 --- a/test_regress/t/t_param_up_bad.out +++ b/test_regress/t/t_param_up_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_up_bad.v:16:19: Can't find definition of scope/variable: 'bar' - 16 | assign a_bad = bar.foo; - | ^~~ +%Error: t/t_param_up_bad.v:14:18: Can't find definition of scope/variable: 'bar' + 14 | assign a_bad = bar.foo; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_up_bad.v b/test_regress/t/t_param_up_bad.v index 92bf6d5e9..80351f001 100644 --- a/test_regress/t/t_param_up_bad.v +++ b/test_regress/t/t_param_up_bad.v @@ -6,27 +6,22 @@ //bug1099 -typedef struct packed { - logic foo; -} some_struct_t; +typedef struct packed {logic foo;} some_struct_t; module child (); - logic a_bad; - // bar is in the parent module, but illegal to reference without module name - assign a_bad = bar.foo; + logic a_bad; + // bar is in the parent module, but illegal to reference without module name + assign a_bad = bar.foo; endmodule -module parent - #( +module parent #( parameter PARAM = 0 - ) - ( - ); - some_struct_t bar; - child c (); +) (); + some_struct_t bar; + child c (); endmodule module t; - // The parameter must be anything other than the default - parent #( 1 ) p (); + // The parameter must be anything other than the default + parent #(1) p (); endmodule diff --git a/test_regress/t/t_param_value.v b/test_regress/t/t_param_value.v index cfedb195c..46c2f701b 100644 --- a/test_regress/t/t_param_value.v +++ b/test_regress/t/t_param_value.v @@ -8,57 +8,57 @@ module t; -`define ASSERT(x) initial if (!(x)) $stop - // See IEEE 6.20.2 on value parameters + `define ASSERT(x) initial if (!(x)) $stop + // See IEEE 6.20.2 on value parameters - localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef; - localparam signed [63:0] SIGNED =64'sh99934567_89abcdef; - localparam real REAL=1.234; - `ASSERT(UNSIGNED > 0); - `ASSERT(SIGNED < 0); + localparam unsigned [63:0] UNSIGNED = 64'h99934567_89abcdef; + localparam signed [63:0] SIGNED = 64'sh99934567_89abcdef; + localparam real REAL = 1.234; + `ASSERT(UNSIGNED > 0); + `ASSERT(SIGNED < 0); - // bullet 1 - localparam A1_WIDE = UNSIGNED; - `ASSERT($bits(A1_WIDE)==64); + // bullet 1 + localparam A1_WIDE = UNSIGNED; + `ASSERT($bits(A1_WIDE) == 64); - localparam A2_REAL = REAL; - `ASSERT(A2_REAL == 1.234); + localparam A2_REAL = REAL; + `ASSERT(A2_REAL == 1.234); - localparam A3_SIGNED = SIGNED; - `ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0); + localparam A3_SIGNED = SIGNED; + `ASSERT($bits(A3_SIGNED) == 64 && A3_SIGNED < 0); - localparam A4_EXPR = (2'b01 + 2'b10); - `ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11); + localparam A4_EXPR = (2'b01 + 2'b10); + `ASSERT($bits(A4_EXPR) == 2 && A4_EXPR == 2'b11); - // bullet 2 - localparam [63:0] B_UNSIGNED = SIGNED; - `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0); + // bullet 2 + localparam [63:0] B_UNSIGNED = SIGNED; + `ASSERT($bits(B_UNSIGNED) == 64 && B_UNSIGNED > 0); - // bullet 3 - localparam signed C_SIGNED = UNSIGNED; - `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0); + // bullet 3 + localparam signed C_SIGNED = UNSIGNED; + `ASSERT($bits(C_SIGNED) == 64 && C_SIGNED < 0); - localparam unsigned C_UNSIGNED = SIGNED; - `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); + localparam unsigned C_UNSIGNED = SIGNED; + `ASSERT($bits(C_UNSIGNED) == 64 && C_UNSIGNED > 0); - // bullet 4 - // verilator lint_off WIDTH - localparam signed [59:0] D_SIGNED = UNSIGNED; - `ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0); - // verilator lint_on WIDTH + // bullet 4 + // verilator lint_off WIDTH + localparam signed [59:0] D_SIGNED = UNSIGNED; + `ASSERT($bits(D_SIGNED) == 60 && D_SIGNED < 0); + // verilator lint_on WIDTH - // verilator lint_off WIDTH - localparam unsigned [59:0] D_UNSIGNED = SIGNED; - `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); - // verilator lint_on WIDTH + // verilator lint_off WIDTH + localparam unsigned [59:0] D_UNSIGNED = SIGNED; + `ASSERT($bits(D_UNSIGNED) == 60 && D_UNSIGNED > 0); + // verilator lint_on WIDTH - // bullet 6 - localparam UNSIZED = 23; - `ASSERT($bits(UNSIZED)>=32); + // bullet 6 + localparam UNSIZED = 23; + `ASSERT($bits(UNSIZED) >= 32); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_while.v b/test_regress/t/t_param_while.v index 8e4bc172c..435b52865 100644 --- a/test_regress/t/t_param_while.v +++ b/test_regress/t/t_param_while.v @@ -8,23 +8,22 @@ module t; - parameter WIDTH = 33; - localparam MAX_WIDTH = 11; - localparam NUM_OUT = num_out(WIDTH); + parameter WIDTH = 33; + localparam MAX_WIDTH = 11; + localparam NUM_OUT = num_out(WIDTH); - wire [NUM_OUT-1:0] z; + wire [NUM_OUT-1:0] z; - function integer num_out; - input integer width; - num_out = 1; - while ((width + num_out - 1) / num_out > MAX_WIDTH) - num_out = num_out * 2; - endfunction + function integer num_out; + input integer width; + num_out = 1; + while ((width + num_out - 1) / num_out > MAX_WIDTH) num_out = num_out * 2; + endfunction - initial begin - if (NUM_OUT != 4) $stop; - if ($bits(z) != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (NUM_OUT != 4) $stop; + if ($bits(z) != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_wide_io.v b/test_regress/t/t_param_wide_io.v index efb140c18..907fc9b39 100644 --- a/test_regress/t/t_param_wide_io.v +++ b/test_regress/t/t_param_wide_io.v @@ -6,15 +6,13 @@ // See issue #1991 -module t - #( - parameter[96:0] P = 97'h12344321_12344321_12344327 - ) - ( - input [P&7 - 1:0] in, - output [P&7 - 1:0] out - ); +module t #( + parameter [96:0] P = 97'h12344321_12344321_12344327 +) ( + input [P&7 - 1:0] in, + output [P&7 - 1:0] out +); - assign out = in; + assign out = in; endmodule diff --git a/test_regress/t/t_param_width.v b/test_regress/t/t_param_width.v index 106fd7727..6b5528b7c 100644 --- a/test_regress/t/t_param_width.v +++ b/test_regress/t/t_param_width.v @@ -6,33 +6,32 @@ // See issue #1991 -module t - (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - socket #(3'b000) s0(); - socket #(3'b010) s1(); - socket #(2'b10) s2(); - socket #(2'b11) s3(); +module t ( + input clk +); - always_ff @ (posedge clk) begin - if (s0.ADDR != 0) $stop; - if (s1.ADDR != 2) $stop; - if (s2.ADDR != 2) $stop; - if (s3.ADDR != 3) $stop; - if ($bits(s0.ADDR) != 3) $stop; - if ($bits(s1.ADDR) != 3) $stop; - if ($bits(s2.ADDR) != 2) $stop; - if ($bits(s3.ADDR) != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + socket #(3'b000) s0 (); + socket #(3'b010) s1 (); + socket #(2'b10) s2 (); + socket #(2'b11) s3 (); + + always_ff @(posedge clk) begin + if (s0.ADDR != 0) $stop; + if (s1.ADDR != 2) $stop; + if (s2.ADDR != 2) $stop; + if (s3.ADDR != 3) $stop; + if ($bits(s0.ADDR) != 3) $stop; + if ($bits(s1.ADDR) != 3) $stop; + if ($bits(s2.ADDR) != 2) $stop; + if ($bits(s3.ADDR) != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module socket #(ADDR)(); - initial - $display("bits %0d, addr %b", $bits(ADDR), ADDR); +module socket #( + ADDR +) (); + initial $display("bits %0d, addr %b", $bits(ADDR), ADDR); endmodule diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out index df2ace02d..36795729c 100644 --- a/test_regress/t/t_param_width_loc_bad.out +++ b/test_regress/t/t_param_width_loc_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'PARAM' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. +%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:19:21: Operator VAR 'PARAM' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. : ... note: In instance 't.test_i' - 20 | parameter logic PARAM = 1'b0 + 19 | parameter logic PARAM = 1'b0 | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v index 4b30df634..9ea9a5b99 100644 --- a/test_regress/t/t_param_width_loc_bad.v +++ b/test_regress/t/t_param_width_loc_bad.v @@ -6,17 +6,16 @@ module t; - // bug1624 - test #(.PARAM(32'd0)) test_i(); + // bug1624 + test #(.PARAM(32'd0)) test_i (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module test - #( +module test #( parameter logic PARAM = 1'b0 - ) (); +) (); endmodule diff --git a/test_regress/t/t_param_x_unique.v b/test_regress/t/t_param_x_unique.v index 02162f3a7..0147daf7f 100644 --- a/test_regress/t/t_param_x_unique.v +++ b/test_regress/t/t_param_x_unique.v @@ -4,13 +4,15 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module sub #(parameter P = 1'bx); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end +module sub #( + parameter P = 1'bx +); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module t; - sub sub(); + sub sub (); endmodule diff --git a/test_regress/t/t_paramgraph_minimal_sibling.v b/test_regress/t/t_paramgraph_minimal_sibling.v index 87df13b20..5c96fd767 100644 --- a/test_regress/t/t_paramgraph_minimal_sibling.v +++ b/test_regress/t/t_paramgraph_minimal_sibling.v @@ -11,9 +11,10 @@ // - A module that accesses typedefs from BOTH siblings // +// verilog_format: off `define stop $stop -`define checkd(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on // Parameterized interface with a typedef that depends on the parameter interface a_if #( diff --git a/test_regress/t/t_parse_delay.v b/test_regress/t/t_parse_delay.v index f78f630b2..c91b068df 100644 --- a/test_regress/t/t_parse_delay.v +++ b/test_regress/t/t_parse_delay.v @@ -6,16 +6,17 @@ module t; - // verilator lint_off WIDTH - reg [6:0] myreg1; + // verilator lint_off WIDTH + reg [6:0] myreg1; - initial begin - myreg1 = # 100 7'd0; - myreg1 = # 100 'b0; // [#] [100] ['b0] - myreg1 = #100'b0; // [#] [100] ['b0] - myreg1 = 100'b0; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // verilog_format: off + myreg1 = # 100 7'd0; + myreg1 = # 100 'b0; // [#] [100] ['b0] + myreg1 = #100'b0; // [#] [100] ['b0] + myreg1 = 100'b0; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_parse_sync_bad.out b/test_regress/t/t_parse_sync_bad.out index d3d33ca66..9aeda1e4d 100644 --- a/test_regress/t/t_parse_sync_bad.out +++ b/test_regress/t/t_parse_sync_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_parse_sync_bad.v:19:22: syntax error, unexpected IDENTIFIER, expecting "'{" - 19 | pkg::cls::defi invalid; - | ^~~~~~~ +%Error: t/t_parse_sync_bad.v:19:20: syntax error, unexpected IDENTIFIER, expecting "'{" + 19 | pkg::cls::defi invalid; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_parse_sync_bad.v:25:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' - 25 | logic clk /*verilator clocker*/; - | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_parse_sync_bad.v:25:13: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' + 25 | logic clk /*verilator clocker*/; + | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_parse_sync_bad.v:29:1: syntax error, unexpected endmodule 29 | endmodule | ^~~~~~~~~ diff --git a/test_regress/t/t_parse_sync_bad.v b/test_regress/t/t_parse_sync_bad.v index 892850503..808a4978e 100644 --- a/test_regress/t/t_parse_sync_bad.v +++ b/test_regress/t/t_parse_sync_bad.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - class cls; - typedef unknown defu; - typedef int defi; - endclass + class cls; + typedef unknown defu; + typedef int defi; + endclass endpackage module t; - task tsk; - begin - valid1 = 5; // valid statement + task tsk; + begin + valid1 = 5; // valid statement - pkg::cls::defi invalid; // invalid statement - end - endtask + pkg::cls::defi invalid; // invalid statement + end + endtask endmodule typedef struct packed { - logic clk /*verilator clocker*/; - logic data; + logic clk /*verilator clocker*/; + logic data; } ss_s; endmodule diff --git a/test_regress/t/t_parse_sync_bad2.out b/test_regress/t/t_parse_sync_bad2.out index 5fa429099..1352669f2 100644 --- a/test_regress/t/t_parse_sync_bad2.out +++ b/test_regress/t/t_parse_sync_bad2.out @@ -1,6 +1,6 @@ -%Error: t/t_parse_sync_bad2.v:9:15: Can't find typedef/interface: 'unknown' - 9 | typedef unknown defu; - | ^~~~~~~ +%Error: t/t_parse_sync_bad2.v:9:13: Can't find typedef/interface: 'unknown' + 9 | typedef unknown defu; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_parse_sync_bad2.v:17:7: Can't find typedef/interface: 'Invalid1' 17 | Invalid1 invalid1; diff --git a/test_regress/t/t_parse_sync_bad2.v b/test_regress/t/t_parse_sync_bad2.v index 39d53599f..5e85f67b2 100644 --- a/test_regress/t/t_parse_sync_bad2.v +++ b/test_regress/t/t_parse_sync_bad2.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - class cls; - typedef unknown defu; - typedef int defi; - endclass + class cls; + typedef unknown defu; + typedef int defi; + endclass endpackage module t; - task tsk; - begin + task tsk; + begin Invalid1 invalid1; // invalid declaration pkg::cls::defi valid1; // valid declaration pkg::cls::defu valid2; // valid declaration Invalid2 invalid2; // invalid declaration - end - endtask + end + endtask endmodule diff --git a/test_regress/t/t_past.v b/test_regress/t/t_past.v index 510fe87f5..e5244d59c 100644 --- a/test_regress/t/t_past.v +++ b/test_regress/t/t_past.v @@ -4,121 +4,124 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) + ); - Test2 test2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); + Test2 test2 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) + ); - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - reg [31:0] dly0; - reg [31:0] dly1; - reg [31:0] dly2; - reg [31:0] dly3; - reg [31:0] dly0Inc; - reg [31:0] dly1Inc; - reg [31:0] dly2Inc; - reg [31:0] dly3Inc; + reg [31:0] dly0; + reg [31:0] dly1; + reg [31:0] dly2; + reg [31:0] dly3; + reg [31:0] dly0Inc; + reg [31:0] dly1Inc; + reg [31:0] dly2Inc; + reg [31:0] dly3Inc; - // If called in an assertion, sequence, or property, the appropriate clocking event. - // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. - // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. - // Otherwise, if called in a procedure, the inferred clock - // Otherwise, default clocking + // If called in an assertion, sequence, or property, the appropriate clocking event. + // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. + // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. + // Otherwise, if called in a procedure, the inferred clock + // Otherwise, default clocking - always @(posedge clk) begin - dly0 <= in; - dly1 <= dly0; - dly2 <= dly1; - dly3 <= dly2; - dly0Inc <= in + 1; - dly1Inc <= dly0Inc; - dly2Inc <= dly1Inc; - dly3Inc <= dly2Inc; - if ($time > 40) begin - // $past(expression, ticks, expression, clocking) - // In clock expression - if (dly0 != $past(in)) $stop; - if (dly0 != $past(in,)) $stop; - if (dly1 != $past(in, 2)) $stop; - if (dly1 != $past(in, 2, )) $stop; - if (dly1 != $past(in, 2, , )) $stop; - if (dly0Inc != $past(in + 1)) $stop; - if (dly0Inc != $past(in + 1,)) $stop; - if (dly1Inc != $past(in + 1, 2)) $stop; - if (dly1Inc != $past(in + 1, 2, )) $stop; - if (dly1Inc != $past(in + 1, 2, , )) $stop; - // $sampled(expression) -> expression - if (in != $sampled(in)) $stop; - end - end + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + dly2 <= dly1; + dly3 <= dly2; + dly0Inc <= in + 1; + dly1Inc <= dly0Inc; + dly2Inc <= dly1Inc; + dly3Inc <= dly2Inc; + if ($time > 40) begin + // $past(expression, ticks, expression, clocking) + // In clock expression + if (dly0 != $past(in)) $stop; + if (dly0 != $past(in,)) $stop; + if (dly1 != $past(in, 2)) $stop; + if (dly1 != $past(in, 2,)) $stop; + if (dly1 != $past(in, 2,,)) $stop; + if (dly0Inc != $past(in + 1)) $stop; + if (dly0Inc != $past(in + 1,)) $stop; + if (dly1Inc != $past(in + 1, 2)) $stop; + if (dly1Inc != $past(in + 1, 2,)) $stop; + if (dly1Inc != $past(in + 1, 2,,)) $stop; + // $sampled(expression) -> expression + if (in != $sampled(in)) $stop; + end + end - assert property (@(posedge clk) $time < 40 || dly0 == $past(in)); - assert property (@(posedge clk) $time < 40 || dly0Inc == $past(in + 1)); + assert property (@(posedge clk) $time < 40 || dly0 == $past(in)); + assert property (@(posedge clk) $time < 40 || dly0Inc == $past(in + 1)); endmodule -module Test2 (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test2 ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - reg [31:0] dly0; - reg [31:0] dly1; + reg [31:0] dly0; + reg [31:0] dly1; - always @(posedge clk) begin - dly0 <= in; - dly1 <= dly0; - end + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + end - default clocking @(posedge clk); endclocking - assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2)); + default clocking @(posedge clk); + endclocking + assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2)); endmodule diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index d525a72ca..9fe6ddcaa 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -1,20 +1,20 @@ -%Error: t/t_past_bad.v:16:20: Expecting expression to be constant, but variable isn't const: 'num' +%Error: t/t_past_bad.v:16:18: Expecting expression to be constant, but variable isn't const: 'num' : ... note: In instance 't' - 16 | if ($past(d, num)) $stop; - | ^~~ + 16 | if ($past(d, num)) $stop; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_past_bad.v:16:11: $past tick value must be constant (IEEE 1800-2023 16.9.3) +%Error: t/t_past_bad.v:16:9: $past tick value must be constant (IEEE 1800-2023 16.9.3) + : ... note: In instance 't' + 16 | if ($past(d, num)) $stop; + | ^~~~~ +%Error: t/t_past_bad.v:17:18: $past tick value must be >= 1 (IEEE 1800-2023 16.9.3) : ... note: In instance 't' - 16 | if ($past(d, num)) $stop; - | ^~~~~ -%Error: t/t_past_bad.v:17:20: $past tick value must be >= 1 (IEEE 1800-2023 16.9.3) - : ... note: In instance 't' - 17 | if ($past(d, 0)) $stop; - | ^ -%Warning-TICKCOUNT: t/t_past_bad.v:18:20: $past tick value of 10000 may have a large performance cost + 17 | if ($past(d, 0)) $stop; + | ^ +%Warning-TICKCOUNT: t/t_past_bad.v:18:18: $past tick value of 10000 may have a large performance cost : ... note: In instance 't' - 18 | if ($past(d, 10000)) $stop; - | ^~~~~ + 18 | if ($past(d, 10000)) $stop; + | ^~~~~ ... For warning description see https://verilator.org/warn/TICKCOUNT?v=latest ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.v b/test_regress/t/t_past_bad.v index 70a21e12c..20fd3eda8 100644 --- a/test_regress/t/t_past_bad.v +++ b/test_regress/t/t_past_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - d, clk, num - ); - input d; - input clk; - input int num; + // Inputs + d, clk, num + ); + input d; + input clk; + input int num; - always @ (posedge clk) begin - if ($past(d, num)) $stop; // IEEE 16.9.3 must be const - if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >= 0 - if ($past(d, 10000)) $stop; // TICKCOUNT - end + always @ (posedge clk) begin + if ($past(d, num)) $stop; // IEEE 16.9.3 must be const + if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >= 0 + if ($past(d, 10000)) $stop; // TICKCOUNT + end endmodule diff --git a/test_regress/t/t_past_funcs.v b/test_regress/t/t_past_funcs.v index 79bd9e558..45497d49a 100644 --- a/test_regress/t/t_past_funcs.v +++ b/test_regress/t/t_past_funcs.v @@ -4,140 +4,148 @@ // SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ - // Inputs - clk +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + wire [31:0] in = cyc; + + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) ); - input clk; - integer cyc; initial cyc=1; - wire [31:0] in = cyc; + Test2 test2 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) + ); - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); + Test3 test3 ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) + ); - Test2 test2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - Test3 test3 (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - bit [31:0] dly0 = 0; - bit [31:0] dly1 = 0; - bit [31:0] dly2 = 0; + bit [31:0] dly0 = 0; + bit [31:0] dly1 = 0; + bit [31:0] dly2 = 0; - // If called in an assertion, sequence, or property, the appropriate clocking event. - // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. - // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. - // Otherwise, if called in a procedure, the inferred clock - // Otherwise, default clocking + // If called in an assertion, sequence, or property, the appropriate clocking event. + // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. + // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. + // Otherwise, if called in a procedure, the inferred clock + // Otherwise, default clocking - always @(posedge clk) begin - dly0 <= in; - dly1 <= dly0; - dly2 <= dly1; - // In clock expression - $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); - if ($rose(dly0[4])) $stop; - if ($fell(dly0[4])) $stop; - if (!$stable(dly0[4])) $stop; - if ($changed(dly0[4])) $stop; - end + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + dly2 <= dly1; + // In clock expression + $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); + if ($rose(dly0[4])) $stop; + if ($fell(dly0[4])) $stop; + if (!$stable(dly0[4])) $stop; + if ($changed(dly0[4])) $stop; + end - assert property (@(posedge clk) $rose(dly0) || dly0%2==0 || dly2 < 3); - assert property (@(posedge clk) $fell(dly1) || dly1%2==1 || dly2 < 3); - assert property (@(posedge clk) !$stable(dly2) || dly2 < 3); - assert property (@(posedge clk) $changed(dly2) || dly2 < 3); + assert property (@(posedge clk) $rose(dly0) || dly0 % 2 == 0 || dly2 < 3); + assert property (@(posedge clk) $fell(dly1) || dly1 % 2 == 1 || dly2 < 3); + assert property (@(posedge clk) !$stable(dly2) || dly2 < 3); + assert property (@(posedge clk) $changed(dly2) || dly2 < 3); - global clocking @(posedge clk); endclocking - always @ ($global_clock) $display("gc in=%0d", in); - // - assert property (@(posedge clk) $rose(dly0, $global_clock) || dly0%2==0 || dly2 < 3); - assert property (@(posedge clk) $fell(dly1, $global_clock) || dly1%2==1 || dly2 < 3); - assert property (@(posedge clk) !$stable(dly2, $global_clock) || dly2 < 3); - assert property (@(posedge clk) $changed(dly2, $global_clock) || dly2 < 3); - // - assert property (@(posedge clk) $rose_gclk(dly0) || dly0%2==0 || dly2 < 3); - assert property (@(posedge clk) $fell_gclk(dly1) || dly1%2==1 || dly2 < 3); - assert property (@(posedge clk) $past_gclk(dly1) == dly2 || dly2 < 3); - assert property (@(posedge clk) !$stable_gclk(dly2) || dly2 < 3); - assert property (@(posedge clk) $changed_gclk(dly2) || dly2 < 3); + global clocking @(posedge clk); + endclocking + always @($global_clock) $display("gc in=%0d", in); + // + assert property (@(posedge clk) $rose(dly0, $global_clock) || dly0 % 2 == 0 || dly2 < 3); + assert property (@(posedge clk) $fell(dly1, $global_clock) || dly1 % 2 == 1 || dly2 < 3); + assert property (@(posedge clk) !$stable(dly2, $global_clock) || dly2 < 3); + assert property (@(posedge clk) $changed(dly2, $global_clock) || dly2 < 3); + // + assert property (@(posedge clk) $rose_gclk(dly0) || dly0 % 2 == 0 || dly2 < 3); + assert property (@(posedge clk) $fell_gclk(dly1) || dly1 % 2 == 1 || dly2 < 3); + assert property (@(posedge clk) $past_gclk(dly1) == dly2 || dly2 < 3); + assert property (@(posedge clk) !$stable_gclk(dly2) || dly2 < 3); + assert property (@(posedge clk) $changed_gclk(dly2) || dly2 < 3); - // global_clocking_future_functions are not supported yet: - // $changing_gclk global_clocking_future_function - // $falling_gclk global_clocking_future_function - // $future_gclk global_clocking_future_function - // $rising_gclk global_clocking_future_function - // $steady_gclk global_clocking_future_function + // global_clocking_future_functions are not supported yet: + // $changing_gclk global_clocking_future_function + // $falling_gclk global_clocking_future_function + // $future_gclk global_clocking_future_function + // $rising_gclk global_clocking_future_function + // $steady_gclk global_clocking_future_function endmodule -module Test2 (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test2 ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - bit [31:0] dly0 = 0; - bit [31:0] dly1 = 0; - bit [31:0] dly2 = 0; + bit [31:0] dly0 = 0; + bit [31:0] dly1 = 0; + bit [31:0] dly2 = 0; - always @(posedge clk) begin - dly0 <= in; - dly1 <= dly0; - dly2 <= dly1; - if ($rose(dly0[31:4])) $stop; - if ($fell(dly1[31:4])) $stop; - if (!$stable(dly2[31:4])) $stop; - if ($changed(dly2[31:4])) $stop; - end + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + dly2 <= dly1; + if ($rose(dly0[31:4])) $stop; + if ($fell(dly1[31:4])) $stop; + if (!$stable(dly2[31:4])) $stop; + if ($changed(dly2[31:4])) $stop; + end - default clocking @(posedge clk); endclocking + default clocking @(posedge clk); + endclocking - assert property ($rose(dly0[0]) || dly0%2==0 || dly2 < 3); - assert property ($fell(dly1[0]) || dly1%2==1 || dly2 < 3); - assert property ($stable(dly2[31:4]) || dly2 < 3); - assert property (!$changed(dly2[31:4]) || dly2 < 3); + assert property ($rose(dly0[0]) || dly0 % 2 == 0 || dly2 < 3); + assert property ($fell(dly1[0]) || dly1 % 2 == 1 || dly2 < 3); + assert property ($stable(dly2[31:4]) || dly2 < 3); + assert property (!$changed(dly2[31:4]) || dly2 < 3); endmodule -module Test3 (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test3 ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - // Check the named form of global clocking - global clocking gck @(posedge clk); endclocking + // Check the named form of global clocking + global clocking gck @(posedge clk); + endclocking endmodule diff --git a/test_regress/t/t_past_strobe.v b/test_regress/t/t_past_strobe.v index 8d154cf34..57855d48c 100644 --- a/test_regress/t/t_past_strobe.v +++ b/test_regress/t/t_past_strobe.v @@ -4,41 +4,45 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [3:0] a, b; + reg [3:0] a, b; - Test1 t1(clk, a, b); + Test1 t1 ( + clk, + a, + b + ); - initial begin - a = 0; - b = 0; - end + initial begin + a = 0; + b = 0; + end - always @(posedge clk) begin - a <= a + 1; - b = b + 1; + always @(posedge clk) begin + a <= a + 1; + b = b + 1; - if (b >= 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (b >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test1( - clk, a, b - ); +module Test1 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - always @(posedge clk) begin - if (a < 9) $strobe("%0d == %0d, %0d == %0d", a, b, $past(a), $past(b)); - end + always @(posedge clk) begin + if (a < 9) $strobe("%0d == %0d, %0d == %0d", a, b, $past(a), $past(b)); + end endmodule diff --git a/test_regress/t/t_past_unsup.out b/test_regress/t/t_past_unsup.out index 888dec662..32e1d9c21 100644 --- a/test_regress/t/t_past_unsup.out +++ b/test_regress/t/t_past_unsup.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_past_unsup.v:16:11: Unsupported: $past expr2 and/or clock arguments - 16 | if ($past(d, 1, 1)) $stop; - | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup.v:16:9: Unsupported: $past expr2 and/or clock arguments + 16 | if ($past(d, 1, 1)) $stop; + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_past_unsup.v:17:11: Unsupported: $past expr2 and/or clock arguments - 17 | if ($past(d, 1, 1, )) $stop; - | ^~~~~ -%Error-UNSUPPORTED: t/t_past_unsup.v:18:11: Unsupported: $past expr2 and/or clock arguments - 18 | if ($past(d, 1, 1, @(posedge clk))) $stop; - | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup.v:17:9: Unsupported: $past expr2 and/or clock arguments + 17 | if ($past(d, 1, 1, )) $stop; + | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup.v:18:9: Unsupported: $past expr2 and/or clock arguments + 18 | if ($past(d, 1, 1, @(posedge clk))) $stop; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup.v b/test_regress/t/t_past_unsup.v index ffdac94dd..5f7397684 100644 --- a/test_regress/t/t_past_unsup.v +++ b/test_regress/t/t_past_unsup.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - d, clk, num - ); - input d; - input clk; - input int num; + // Inputs + d, clk, num + ); + input d; + input clk; + input int num; - always @ (posedge clk) begin - if ($past(d, 1, 1)) $stop; // Unsup - if ($past(d, 1, 1, )) $stop; // Unsup - if ($past(d, 1, 1, @(posedge clk))) $stop; // Unsup - end + always @ (posedge clk) begin + if ($past(d, 1, 1)) $stop; // Unsup + if ($past(d, 1, 1, )) $stop; // Unsup + if ($past(d, 1, 1, @(posedge clk))) $stop; // Unsup + end endmodule diff --git a/test_regress/t/t_pgo_profoutofdate_bad.v b/test_regress/t/t_pgo_profoutofdate_bad.v index 652557f31..5145fd53b 100644 --- a/test_regress/t/t_pgo_profoutofdate_bad.v +++ b/test_regress/t/t_pgo_profoutofdate_bad.v @@ -5,21 +5,21 @@ // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; + integer cyc = 0; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_pli_bad.out b/test_regress/t/t_pli_bad.out index 0525303d8..d30e20128 100644 --- a/test_regress/t/t_pli_bad.out +++ b/test_regress/t/t_pli_bad.out @@ -1,22 +1,22 @@ -%Error: t/t_pli_bad.v:10:7: Unsupported or unknown PLI call: '$unknown_pli_task' - 10 | $unknown_pli_task; - | ^~~~~~~~~~~~~~~~~ +%Error: t/t_pli_bad.v:10:5: Unsupported or unknown PLI call: '$unknown_pli_task' + 10 | $unknown_pli_task; + | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_pli_bad.v:11:7: Unsupported or unknown PLI call: '$unknown_pli_task' - 11 | $unknown_pli_task("arg", i); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_pli_bad.v:12:11: Unsupported or unknown PLI call: '$unknown_pli_function' - 12 | i = $unknown_pli_function; - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_pli_bad.v:13:11: Unsupported or unknown PLI call: '$unknown_pli_function' - 13 | i = $unknown_pli_function("arg", i); - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_pli_bad.v:15:7: Unsupported or unknown PLI call: '$sformatff' +%Error: t/t_pli_bad.v:11:5: Unsupported or unknown PLI call: '$unknown_pli_task' + 11 | $unknown_pli_task("arg", i); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_pli_bad.v:12:9: Unsupported or unknown PLI call: '$unknown_pli_function' + 12 | i = $unknown_pli_function; + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_pli_bad.v:13:9: Unsupported or unknown PLI call: '$unknown_pli_function' + 13 | i = $unknown_pli_function("arg", i); + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_pli_bad.v:15:5: Unsupported or unknown PLI call: '$sformatff' : ... Suggested alternative: '$sformatf' - 15 | $sformatff(); - | ^~~~~~~~~~ -%Error: t/t_pli_bad.v:16:11: Unsupported or unknown PLI call: '$sformatff' - : ... Suggested alternative: '$sformatf' - 16 | i = $sformatff(); - | ^~~~~~~~~~ + 15 | $sformatff(); + | ^~~~~~~~~~ +%Error: t/t_pli_bad.v:16:9: Unsupported or unknown PLI call: '$sformatff' + : ... Suggested alternative: '$sformatf' + 16 | i = $sformatff(); + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pli_bad.v b/test_regress/t/t_pli_bad.v index 35e198f64..8f68f1dc4 100644 --- a/test_regress/t/t_pli_bad.v +++ b/test_regress/t/t_pli_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer i; - initial begin - $unknown_pli_task; - $unknown_pli_task("arg", i); - i = $unknown_pli_function; - i = $unknown_pli_function("arg", i); + integer i; + initial begin + $unknown_pli_task; + $unknown_pli_task("arg", i); + i = $unknown_pli_function; + i = $unknown_pli_function("arg", i); - $sformatff(); // Typo - i = $sformatff(); // Typo + $sformatff(); // Typo + i = $sformatff(); // Typo - $stop; - end + $stop; + end endmodule diff --git a/test_regress/t/t_pp_display.v b/test_regress/t/t_pp_display.v index 28fe82569..7bfa83df5 100644 --- a/test_regress/t/t_pp_display.v +++ b/test_regress/t/t_pp_display.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire d1 = 1'b1; - wire d2 = 1'b1; - wire d3 = 1'b1; - wire o1,o2,o3; - add1 add1 (d1,o1); - add2 add2 (d2,o2); + wire d1 = 1'b1; + wire d2 = 1'b1; + wire d3 = 1'b1; + wire o1,o2,o3; + add1 add1 (d1,o1); + add2 add2 (d2,o2); `define ls left_side `define rs right_side @@ -19,40 +19,40 @@ module t; `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" `define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string - initial begin - //$display(`msg( \`, \`)); // Illegal - $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); - $display(`msg(left side,right side)); - $display(`msg( left side , right side )); - $display(`msg( `ls , `rs )); - $display(`msg( `noarg , `rs )); - $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); - $display(`msg(`noarg,`noarg`noarg)); - $display(`msg( `thruthru , `thruthru )); // Results vary between simulators - $display(`left(`msg( left side , right side ), left_replaced)); - //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error + initial begin + //$display(`msg( \`, \`)); // Illegal + $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); + $display(`msg(left side,right side)); + $display(`msg( left side , right side )); + $display(`msg( `ls , `rs )); + $display(`msg( `noarg , `rs )); + $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); + $display(`msg(`noarg,`noarg`noarg)); + $display(`msg( `thruthru , `thruthru )); // Results vary between simulators + $display(`left(`msg( left side , right side ), left_replaced)); + //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error `ifndef VCS // Sim bug - wrong number of arguments, but we're right - $display(`msg(`thru(),)); // Empty + $display(`msg(`thru(),)); // Empty `endif - $display(`msg(`thru(left side),`thru(right side))); - $display(`msg( `thru( left side ) , `thru( right side ) )); + $display(`msg(`thru(left side),`thru(right side))); + $display(`msg( `thru( left side ) , `thru( right side ) )); `ifndef NC - $display(`"standalone`"); + $display(`"standalone`"); `endif `ifdef VERILATOR - // Illegal on some simulators, as the "..." crosses two lines + // Illegal on some simulators, as the "..." crosses two lines `define twoline first \ second - $display(`msg(twoline, `twoline)); + $display(`msg(twoline, `twoline)); `endif - $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); + $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); - //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. - $write("*-* All Finished *-*\n"); - $finish; - end + //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. + $write("*-* All Finished *-*\n"); + $finish; + end endmodule `define ADD_UP(a,c) \ diff --git a/test_regress/t/t_pp_dupdef.v b/test_regress/t/t_pp_dupdef.v index 3e1e71b9e..02483d435 100644 --- a/test_regress/t/t_pp_dupdef.v +++ b/test_regress/t/t_pp_dupdef.v @@ -12,6 +12,6 @@ module t; `define DUPP paramed(x) (x) `define DUPP paramed(x,z) (x*z) - initial $stop; // Should have failed + initial $stop; // Should have failed endmodule diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index c21188b58..11253e752 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -6,6 +6,6 @@ `include "t_pp_lib_inc.vh" module t; - wire [`WIDTH-1:0] a; - library_cell n1(a); + wire [`WIDTH-1:0] a; + library_cell n1(a); endmodule diff --git a/test_regress/t/t_pp_lib_library.v b/test_regress/t/t_pp_lib_library.v index 431f73f48..7a8dd620a 100644 --- a/test_regress/t/t_pp_lib_library.v +++ b/test_regress/t/t_pp_lib_library.v @@ -4,10 +4,12 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module library_cell(a); - input [`WIDTH-1:0] a; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end +module library_cell ( + a +); + input [`WIDTH-1:0] a; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_pp_misdef_bad.out b/test_regress/t/t_pp_misdef_bad.out index ba5e0b2c0..b3f2f0c9c 100644 --- a/test_regress/t/t_pp_misdef_bad.out +++ b/test_regress/t/t_pp_misdef_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_pp_misdef_bad.v:11:4: Define or directive not defined: '`NDEFINED' +%Error: t/t_pp_misdef_bad.v:12:4: Define or directive not defined: '`NDEFINED' : ... Suggested alternative: '`DEFINED' - 11 | `NDEFINED + 12 | `NDEFINED | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_pp_misdef_bad.v:14:6: Define or directive not defined: '`imescale' +%Error: t/t_pp_misdef_bad.v:15:6: Define or directive not defined: '`imescale' : ... Suggested alternative: '`timescale' - 14 | `imescale + 15 | `imescale | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_misdef_bad.v b/test_regress/t/t_pp_misdef_bad.v index bc5c56b8f..99e6a5a5a 100644 --- a/test_regress/t/t_pp_misdef_bad.v +++ b/test_regress/t/t_pp_misdef_bad.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; `define DEFINED diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v index 3b994574a..5ff2d93e2 100644 --- a/test_regress/t/t_pp_pragmas.v +++ b/test_regress/t/t_pp_pragmas.v @@ -54,8 +54,8 @@ // unsupported: `uselib dir=../lib.dir libext=.v module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_pp_recursedef_bad.out b/test_regress/t/t_pp_recursedef_bad.out index 741d039d6..d37b640cb 100644 --- a/test_regress/t/t_pp_recursedef_bad.out +++ b/test_regress/t/t_pp_recursedef_bad.out @@ -1,3 +1,3 @@ -%Error: t/t_pp_recursedef_bad.v:9:8012: Recursive `define substitution: `RECURSE +%Error: t/t_pp_recursedef_bad.v:10:8011: Recursive `define substitution: `RECURSE ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_pp_recursedef_bad.v b/test_regress/t/t_pp_recursedef_bad.v index 57287cfe8..477aaa5f4 100644 --- a/test_regress/t/t_pp_recursedef_bad.v +++ b/test_regress/t/t_pp_recursedef_bad.v @@ -4,10 +4,11 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; -`define RECURSE `RECURSE - `RECURSE + `define RECURSE `RECURSE + `RECURSE - initial $stop; // Should have failed + initial $stop; // Should have failed endmodule diff --git a/test_regress/t/t_pp_underline_bad.out b/test_regress/t/t_pp_underline_bad.out index 977a7a361..2623fa4c7 100644 --- a/test_regress/t/t_pp_underline_bad.out +++ b/test_regress/t/t_pp_underline_bad.out @@ -1,8 +1,8 @@ -%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ - 8 | // verilator_no_inline_module - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:3: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ + 8 | // verilator_no_inline_module + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest -%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:10:19: Extra underscore in meta-comment, ignoring comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ - 10 | case (1'b1) // synopsys_full_case - | ^~~~~~~~~~~~~~~~~~~~~ +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:10:18: Extra underscore in meta-comment, ignoring comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ + 10 | case (1'b1) // synopsys_full_case + | ^~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v index 56a87c969..d7c88621b 100644 --- a/test_regress/t/t_pp_underline_bad.v +++ b/test_regress/t/t_pp_underline_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - // verilator_no_inline_module - initial begin - case (1'b1) // synopsys_full_case - 1'b0: $stop; - 1'b1: $finish; - endcase - $stop; // Should have failed - end + // verilator_no_inline_module + initial begin + case (1'b1) // synopsys_full_case + 1'b0: $stop; + 1'b1: $finish; + endcase + $stop; // Should have failed + end endmodule diff --git a/test_regress/t/t_pp_underline_bad_vlt.out b/test_regress/t/t_pp_underline_bad_vlt.out index 89ac5c94b..91c53519c 100644 --- a/test_regress/t/t_pp_underline_bad_vlt.out +++ b/test_regress/t/t_pp_underline_bad_vlt.out @@ -1,5 +1,5 @@ -%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ - 8 | // verilator_no_inline_module - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:3: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ + 8 | // verilator_no_inline_module + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_premit_rw.v b/test_regress/t/t_premit_rw.v index f9bb52cc9..ef9aadbb7 100644 --- a/test_regress/t/t_premit_rw.v +++ b/test_regress/t/t_premit_rw.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - logic car_enable; - logic [3-1:0] car_rpv; - logic [2-1:0] car_sn; + logic car_enable; + logic [3-1:0] car_rpv; + logic [2-1:0] car_sn; } car_s; -module t (/*AUTOARG*/ - // Outputs - action, - // Inputs - rsp - ); - input rsp; - output action; - car_s rsp; - car_s action; - always @(*) begin - action = rsp; - if (rsp.car_enable == 1'b1) begin - action.car_rpv[ action.car_sn] = 1'b0; // causing problem - // OK - //action.car_rpv[ rsp.car_sn] = 1'b0; - end - end +module t ( /*AUTOARG*/ + // Outputs + action, + // Inputs + rsp +); + input rsp; + output action; + car_s rsp; + car_s action; + always @(*) begin + action = rsp; + if (rsp.car_enable == 1'b1) begin + action.car_rpv[action.car_sn] = 1'b0; // causing problem + // OK + //action.car_rpv[ rsp.car_sn] = 1'b0; + end + end endmodule diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index ef17bae5a..f3b0a1737 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -6,9 +6,9 @@ // verilog_format: off module t; - integer num; - initial begin - num = 0; + integer num; + initial begin + num = 0; `define EMPTY_TRUE `ifndef EMPTY_TRUE @@ -33,13 +33,13 @@ module t; `elsif C $stop; `else $stop; `endif - if (num == 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("%%Error: Bad count: %d\n", num); - $stop; - end - end + if (num == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("%%Error: Bad count: %d\n", num); + $stop; + end + end endmodule diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index 6108e5f4e..5bbf404d8 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -6,21 +6,21 @@ // verilog_format: off module t; - v95 v95 (); - v01nc v01nc (); - v01c v01c (); - v05 v05 (); - s05 s05 (); - s09 s09 (); - s12 s12 (); - s17 s17 (); - s23 s23 (); + v95 v95 (); + v01nc v01nc (); + v01c v01c (); + v05 v05 (); + s05 s05 (); + s09 s09 (); + s12 s12 (); + s17 s17 (); + s23 s23 (); - a23 a23 (); + a23 a23 (); - initial begin - $finish; - end + initial begin + $finish; + end endmodule `begin_keywords "1364-1995" diff --git a/test_regress/t/t_probdist.v b/test_regress/t/t_probdist.v index 340455f92..e22f16bb0 100644 --- a/test_regress/t/t_probdist.v +++ b/test_regress/t/t_probdist.v @@ -4,108 +4,110 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - integer seed; - integer r; - integer sum; + integer seed; + integer r; + integer sum; - initial begin - //======= - seed = 1234; - r = $dist_chi_square(seed, 5); - `checkd(seed, 923940542); - `checkd(r, 8); - sum = 1; - repeat(20) sum += $dist_chi_square(seed, 5); - `checkd(sum, 130); - sum = 1; - repeat(20) sum += $dist_chi_square(seed, -5); - `checkd(sum, 1); - sum = 1; - repeat(20) sum += $dist_chi_square(seed, 2); - `checkd(sum, 30); + initial begin + //======= + seed = 1234; + r = $dist_chi_square(seed, 5); + `checkd(seed, 923940542); + `checkd(r, 8); + sum = 1; + repeat (20) sum += $dist_chi_square(seed, 5); + `checkd(sum, 130); + sum = 1; + repeat (20) sum += $dist_chi_square(seed, -5); + `checkd(sum, 1); + sum = 1; + repeat (20) sum += $dist_chi_square(seed, 2); + `checkd(sum, 30); - //======= - seed = 1234; - r = $dist_erlang(seed, 5, 10); - `checkd(seed, 1025211431); - `checkd(r, 19); - sum = 1; - repeat(20) sum += $dist_erlang(seed, 5, 10); - `checkd(sum, 173); - sum = 1; - repeat(20) sum += $dist_erlang(seed, 5, -10); - `checkd(sum, -241); + //======= + seed = 1234; + r = $dist_erlang(seed, 5, 10); + `checkd(seed, 1025211431); + `checkd(r, 19); + sum = 1; + repeat (20) sum += $dist_erlang(seed, 5, 10); + `checkd(sum, 173); + sum = 1; + repeat (20) sum += $dist_erlang(seed, 5, -10); + `checkd(sum, -241); - //======= - seed = 1234; - r = $dist_exponential(seed, 5); - `checkd(seed, 85231147); - `checkd(r, 20); - sum = 1; - repeat(20) sum += $dist_exponential(seed, 5); - `checkd(sum, 104); + //======= + seed = 1234; + r = $dist_exponential(seed, 5); + `checkd(seed, 85231147); + `checkd(r, 20); + sum = 1; + repeat (20) sum += $dist_exponential(seed, 5); + `checkd(sum, 104); - //======= - seed = 1234; - r = $dist_normal(seed, 5, 10); - `checkd(seed, -1570070672); - `checkd(r, 4); - sum = 1; - repeat(20) sum += $dist_normal(seed, 5, 10); - `checkd(sum, 114); + //======= + seed = 1234; + r = $dist_normal(seed, 5, 10); + `checkd(seed, -1570070672); + `checkd(r, 4); + sum = 1; + repeat (20) sum += $dist_normal(seed, 5, 10); + `checkd(sum, 114); - //======= - seed = 1234; - r = $dist_poisson(seed, 5); - `checkd(seed, 418012337); - `checkd(r, 2); - sum = 1; - repeat(20) sum += $dist_poisson(seed, 5); - `checkd(sum, 111); + //======= + seed = 1234; + r = $dist_poisson(seed, 5); + `checkd(seed, 418012337); + `checkd(r, 2); + sum = 1; + repeat (20) sum += $dist_poisson(seed, 5); + `checkd(sum, 111); - //======= - seed = 1234; - r = $dist_t(seed, 5); - `checkd(seed, -797481412); - `checkd(r, 0); - sum = 1; - repeat(20) sum += $dist_t(seed, 5); - `checkd(sum, -2); + //======= + seed = 1234; + r = $dist_t(seed, 5); + `checkd(seed, -797481412); + `checkd(r, 0); + sum = 1; + repeat (20) sum += $dist_t(seed, 5); + `checkd(sum, -2); - //======= - seed = 1234; - r = $dist_uniform(seed, 5, 10); - `checkd(seed, 85231147); - `checkd(r, 5); - sum = 1; - repeat(20) sum += $dist_uniform(seed, 5, 10); - `checkd(sum, 147); + //======= + seed = 1234; + r = $dist_uniform(seed, 5, 10); + `checkd(seed, 85231147); + `checkd(r, 5); + sum = 1; + repeat (20) sum += $dist_uniform(seed, 5, 10); + `checkd(sum, 147); - seed = 1234; - r = $dist_uniform(seed, 10, 5); - `checkd(r, 10); - sum = 1; - repeat(20) sum += $dist_uniform(seed, -2147483648, -20); - `checkd(sum, 1768955681); - sum = 1; - repeat(20) sum += $dist_uniform(seed, 20, 2147483647); - `checkd(sum, 1534326415); - sum = 1; - repeat(20) sum += $dist_uniform(seed, -2147483648, 2147483647); - `checkd(sum, 1394525852); - seed = 0; - sum = 1; - repeat(20) sum += $dist_uniform(seed, -10, 100); - `checkd(seed, 1003647461); - `checkd(sum, 896); + seed = 1234; + r = $dist_uniform(seed, 10, 5); + `checkd(r, 10); + sum = 1; + repeat (20) sum += $dist_uniform(seed, -2147483648, -20); + `checkd(sum, 1768955681); + sum = 1; + repeat (20) sum += $dist_uniform(seed, 20, 2147483647); + `checkd(sum, 1534326415); + sum = 1; + repeat (20) sum += $dist_uniform(seed, -2147483648, 2147483647); + `checkd(sum, 1394525852); + seed = 0; + sum = 1; + repeat (20) sum += $dist_uniform(seed, -10, 100); + `checkd(seed, 1003647461); + `checkd(sum, 896); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_probdist_bad.v b/test_regress/t/t_probdist_bad.v index 672412e16..dd262a660 100644 --- a/test_regress/t/t_probdist_bad.v +++ b/test_regress/t/t_probdist_bad.v @@ -4,32 +4,34 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - integer seed; - integer r; + integer seed; + integer r; - initial begin - // Illegal values - r = $dist_chi_square(seed, 0); - if (r != 0 && !$isunknown(r)) $stop; - r = $dist_erlang(seed, 0, 0); - if (r != 0 && !$isunknown(r)) $stop; - r = $dist_exponential(seed, 0); - if (r != 0 && !$isunknown(r)) $stop; - // r =$dist_exponential(seed, mean); // Always valid - r = $dist_poisson(seed, 0); - if (r != 0 && !$isunknown(r)) $stop; - r = $dist_t(seed, 0); - if (r != 0 && !$isunknown(r)) $stop; - r = $dist_uniform(seed, 10, 0); - if (r != 10 && !$isunknown(r)) $stop; + initial begin + // Illegal values + r = $dist_chi_square(seed, 0); + if (r != 0 && !$isunknown(r)) $stop; + r = $dist_erlang(seed, 0, 0); + if (r != 0 && !$isunknown(r)) $stop; + r = $dist_exponential(seed, 0); + if (r != 0 && !$isunknown(r)) $stop; + // r =$dist_exponential(seed, mean); // Always valid + r = $dist_poisson(seed, 0); + if (r != 0 && !$isunknown(r)) $stop; + r = $dist_t(seed, 0); + if (r != 0 && !$isunknown(r)) $stop; + r = $dist_uniform(seed, 10, 0); + if (r != 10 && !$isunknown(r)) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process.v b/test_regress/t/t_process.v index e800d6707..186432eda 100644 --- a/test_regress/t/t_process.v +++ b/test_regress/t/t_process.v @@ -19,28 +19,28 @@ // endclass module t; - process p; + process p; - initial begin - if (p != null) $stop; - p = process::self(); - if (p.status() != process::RUNNING) $stop; - if (p.status() == process::WAITING) $stop; - if (p.status() == process::SUSPENDED) $stop; - if (p.status() == process::KILLED) $stop; - if (p.status() == process::FINISHED) $stop; + initial begin + if (p != null) $stop; + p = process::self(); + if (p.status() != process::RUNNING) $stop; + if (p.status() == process::WAITING) $stop; + if (p.status() == process::SUSPENDED) $stop; + if (p.status() == process::KILLED) $stop; + if (p.status() == process::FINISHED) $stop; - if (0) p.kill(); - if (0) p.await(); - if (0) p.suspend(); - if (0) p.resume(); - // See also t_urandom.py - p.srandom(0); - p.set_randstate(p.get_randstate()); + if (0) p.kill(); + if (0) p.await(); + if (0) p.suspend(); + if (0) p.resume(); + // See also t_urandom.py + p.srandom(0); + p.set_randstate(p.get_randstate()); - $display("%p", p); + $display("%p", p); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_bad.out b/test_regress/t/t_process_bad.out index f58892526..d4ec32048 100644 --- a/test_regress/t/t_process_bad.out +++ b/test_regress/t/t_process_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_process_bad.v:13:13: Class method 'bad_method' not found in class 'process' +%Error: t/t_process_bad.v:13:11: Class method 'bad_method' not found in class 'process' : ... note: In instance 't' - 13 | if (p.bad_method() != 0) $stop; - | ^~~~~~~~~~ + 13 | if (p.bad_method() != 0) $stop; + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_process_bad.v:15:9: Class method 'bad_method_2' not found in class 'process' +%Error: t/t_process_bad.v:15:7: Class method 'bad_method_2' not found in class 'process' : ... note: In instance 't' - 15 | p.bad_method_2(); - | ^~~~~~~~~~~~ + 15 | p.bad_method_2(); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_process_bad.v b/test_regress/t/t_process_bad.v index 665c7c1d7..b31cd6791 100644 --- a/test_regress/t/t_process_bad.v +++ b/test_regress/t/t_process_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - process p; + process p; - initial begin - if (p != null) $stop; - p = process::self(); - if (p.bad_method() != 0) $stop; + initial begin + if (p != null) $stop; + p = process::self(); + if (p.bad_method() != 0) $stop; - p.bad_method_2(); + p.bad_method_2(); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_compare.v b/test_regress/t/t_process_compare.v index 02f7dcc2e..d8f10baa1 100644 --- a/test_regress/t/t_process_compare.v +++ b/test_regress/t/t_process_compare.v @@ -5,36 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 class A; - local process proc2; - task run; - process proc1; - proc1 = process::self(); + local process proc2; + task run; + process proc1; + proc1 = process::self(); - if (proc2 == null) begin - proc2 = proc1; - end - else if (proc1 == proc2) begin - $display("process is equal %p %p", proc1, proc2); - end - else begin - $display("process is not equal (using ! ==) %p %p", proc1, proc2); - $stop; - end + if (proc2 == null) begin + proc2 = proc1; + end + else if (proc1 == proc2) begin + $display("process is equal %p %p", proc1, proc2); + end + else begin + $display("process is not equal (using ! ==) %p %p", proc1, proc2); + $stop; + end - if (proc2 != null && proc1 != proc2) begin - $display("process is not equal (using !=) %p %p", proc1, proc2); - $stop; - end - endtask + if (proc2 != null && proc1 != proc2) begin + $display("process is not equal (using !=) %p %p", proc1, proc2); + $stop; + end + endtask endclass module t; - initial begin - A a; - a = new(); - a.run(); - a.run(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + A a; + a = new(); + a.run(); + a.run(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_copy_constr.v b/test_regress/t/t_process_copy_constr.v index fa335548a..bd5765f20 100644 --- a/test_regress/t/t_process_copy_constr.v +++ b/test_regress/t/t_process_copy_constr.v @@ -5,21 +5,21 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int x = 1; - function new(); - process p = process::self(); - endfunction + int x = 1; + function new(); + process p = process::self(); + endfunction endclass -module t (/*AUTOARG*/ - ); - initial begin - Cls c, d; - c = new; - c.x = 2; - d = new c; - if (d.x != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end +module t ( /*AUTOARG*/ +); + initial begin + Cls c, d; + c = new; + c.x = 2; + d = new c; + if (d.x != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_finished.v b/test_regress/t/t_process_finished.v index 109acb469..e274050c7 100644 --- a/test_regress/t/t_process_finished.v +++ b/test_regress/t/t_process_finished.v @@ -4,21 +4,19 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - process p; +module t ( + input clk +); - initial begin - p = process::self(); - end + process p; - always @(posedge clk) begin - if (p.status() != process::FINISHED) - $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + p = process::self(); + end + + always @(posedge clk) begin + if (p.status() != process::FINISHED) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_fork.v b/test_regress/t/t_process_fork.v index 854c050ea..0620f0cab 100644 --- a/test_regress/t/t_process_fork.v +++ b/test_regress/t/t_process_fork.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 module t; - process job[] = new [8]; + process job[] = new[8]; - initial begin - foreach (job[j]) begin - fork - begin - $write("job started\n"); - job[j] = process::self(); - end - join_none - #0; - end - foreach (job[j]) begin - wait (job[j]); - end - $write("all jobs started\n"); - foreach (job[j]) begin - job[j].await(); - end - $write("all jobs finished\n"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + foreach (job[j]) begin + fork + begin + $write("job started\n"); + job[j] = process::self(); + end + join_none + #0; + end + foreach (job[j]) begin + wait (job[j]); + end + $write("all jobs started\n"); + foreach (job[j]) begin + job[j].await(); + end + $write("all jobs finished\n"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_kill.v b/test_regress/t/t_process_kill.v index f5ed09ea1..9317f3556 100644 --- a/test_regress/t/t_process_kill.v +++ b/test_regress/t/t_process_kill.v @@ -4,26 +4,26 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - process p; +module t ( + input clk +); - initial begin - wait (p); - p.kill(); - p.await(); - $write("*-* All Finished *-*\n"); - $finish; - end + process p; - always @(posedge clk) begin - if (!p) begin - p = process::self(); - end else begin - $stop; - end - end + initial begin + wait (p); + p.kill(); + p.await(); + $write("*-* All Finished *-*\n"); + $finish; + end + + always @(posedge clk) begin + if (!p) begin + p = process::self(); + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_process_notiming.out b/test_regress/t/t_process_notiming.out index 4a663d81f..556686086 100644 --- a/test_regress/t/t_process_notiming.out +++ b/test_regress/t/t_process_notiming.out @@ -1,54 +1,54 @@ -%Error-NOTIMING: t/t_process.v:26:20: process::self() requires --timing +%Error-NOTIMING: t/t_process.v:26:18: process::self() requires --timing : ... note: In instance 't' - 26 | p = process::self(); - | ^~~~ + 26 | p = process::self(); + | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Error-NOTIMING: t/t_process.v:27:13: process::status() requires --timing +%Error-NOTIMING: t/t_process.v:27:11: process::status() requires --timing : ... note: In instance 't' - 27 | if (p.status() != process::RUNNING) $stop; - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:28:13: process::status() requires --timing + 27 | if (p.status() != process::RUNNING) $stop; + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:28:11: process::status() requires --timing : ... note: In instance 't' - 28 | if (p.status() == process::WAITING) $stop; - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:29:13: process::status() requires --timing + 28 | if (p.status() == process::WAITING) $stop; + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:29:11: process::status() requires --timing : ... note: In instance 't' - 29 | if (p.status() == process::SUSPENDED) $stop; - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:30:13: process::status() requires --timing + 29 | if (p.status() == process::SUSPENDED) $stop; + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:30:11: process::status() requires --timing : ... note: In instance 't' - 30 | if (p.status() == process::KILLED) $stop; - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:31:13: process::status() requires --timing + 30 | if (p.status() == process::KILLED) $stop; + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:31:11: process::status() requires --timing : ... note: In instance 't' - 31 | if (p.status() == process::FINISHED) $stop; - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:33:16: process::kill() requires --timing + 31 | if (p.status() == process::FINISHED) $stop; + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:33:14: process::kill() requires --timing : ... note: In instance 't' - 33 | if (0) p.kill(); - | ^~~~ -%Error-NOTIMING: t/t_process.v:34:16: process::await() requires --timing + 33 | if (0) p.kill(); + | ^~~~ +%Error-NOTIMING: t/t_process.v:34:14: process::await() requires --timing : ... note: In instance 't' - 34 | if (0) p.await(); - | ^~~~~ -%Error-NOTIMING: t/t_process.v:35:16: process::suspend() requires --timing + 34 | if (0) p.await(); + | ^~~~~ +%Error-NOTIMING: t/t_process.v:35:14: process::suspend() requires --timing : ... note: In instance 't' - 35 | if (0) p.suspend(); - | ^~~~~~~ -%Error-NOTIMING: t/t_process.v:36:16: process::resume() requires --timing + 35 | if (0) p.suspend(); + | ^~~~~~~ +%Error-NOTIMING: t/t_process.v:36:14: process::resume() requires --timing : ... note: In instance 't' - 36 | if (0) p.resume(); - | ^~~~~~ -%Error-NOTIMING: t/t_process.v:38:9: process::srandom() requires --timing + 36 | if (0) p.resume(); + | ^~~~~~ +%Error-NOTIMING: t/t_process.v:38:7: process::srandom() requires --timing : ... note: In instance 't' - 38 | p.srandom(0); - | ^~~~~~~ -%Error-NOTIMING: t/t_process.v:39:9: process::set_randstate() requires --timing + 38 | p.srandom(0); + | ^~~~~~~ +%Error-NOTIMING: t/t_process.v:39:7: process::set_randstate() requires --timing : ... note: In instance 't' - 39 | p.set_randstate(p.get_randstate()); - | ^~~~~~~~~~~~~ -%Error-NOTIMING: t/t_process.v:39:25: process::get_randstate() requires --timing + 39 | p.set_randstate(p.get_randstate()); + | ^~~~~~~~~~~~~ +%Error-NOTIMING: t/t_process.v:39:23: process::get_randstate() requires --timing : ... note: In instance 't' - 39 | p.set_randstate(p.get_randstate()); - | ^~~~~~~~~~~~~ + 39 | p.set_randstate(p.get_randstate()); + | ^~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_process_rand.v b/test_regress/t/t_process_rand.v index 2607e4dd3..151570c2d 100644 --- a/test_regress/t/t_process_rand.v +++ b/test_regress/t/t_process_rand.v @@ -5,48 +5,46 @@ // SPDX-License-Identifier: CC0-1.0 module t; - process p; + process p; - integer seed; - string state; - int a; - int b; + integer seed; + string state; + int a; + int b; - initial begin - p = process::self(); + initial begin + p = process::self(); - // Test setting RNG state with state string - state = p.get_randstate(); - p.set_randstate(state); - a = $random; - p.set_randstate(state); - b = $random; - $display("a=%d, b=%d", a, b); - if (a != b) $stop; + // Test setting RNG state with state string + state = p.get_randstate(); + p.set_randstate(state); + a = $random; + p.set_randstate(state); + b = $random; + $display("a=%d, b=%d", a, b); + if (a != b) $stop; - // Test the same with $urandom - state = p.get_randstate(); - p.set_randstate(state); - a = $urandom; - p.set_randstate(state); - b = $urandom; - $display("a=%d, b=%d", a, b); - if (a != b) $stop; + // Test the same with $urandom + state = p.get_randstate(); + p.set_randstate(state); + a = $urandom; + p.set_randstate(state); + b = $urandom; + $display("a=%d, b=%d", a, b); + if (a != b) $stop; - // Test if the results repeat after the state is reset - state = p.get_randstate(); - for (int i = 0; i < 10; i++) - $random; - a = $random; - // Now reset the state and take 11th result again - p.set_randstate(state); - for (int i = 0; i < 10; i++) - $random; - b = $random; - $display("a=%d, b=%d", a, b); - if (a != b) $stop; + // Test if the results repeat after the state is reset + state = p.get_randstate(); + for (int i = 0; i < 10; i++) $random; + a = $random; + // Now reset the state and take 11th result again + p.set_randstate(state); + for (int i = 0; i < 10; i++) $random; + b = $random; + $display("a=%d, b=%d", a, b); + if (a != b) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_redecl.v b/test_regress/t/t_process_redecl.v index 78b46f537..5720ffd86 100644 --- a/test_regress/t/t_process_redecl.v +++ b/test_regress/t/t_process_redecl.v @@ -4,20 +4,19 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t ( - ); +module t; - // Overrides standard class - class process; - endclass - class mailbox; - endclass - class semaphore; - endclass + // Overrides standard class + class process; + endclass + class mailbox; + endclass + class semaphore; + endclass - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_task.v b/test_regress/t/t_process_task.v index 1ba02cf41..161f5583c 100644 --- a/test_regress/t/t_process_task.v +++ b/test_regress/t/t_process_task.v @@ -5,29 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 module t; - std::process proc; - logic clk = 0; - logic b = 0; + std::process proc; + logic clk = 0; + logic b = 0; - always #1 clk = ~clk; + always #1 clk = ~clk; - task kill_me_after_1ns(); - fork - #1 proc.kill(); - #3 begin - $write("*-* All Finished *-*\n"); - $finish; - end - join_none - endtask - - always @(posedge clk) begin - if (!b) begin - proc = std::process::self(); - kill_me_after_1ns(); - b = 1; - end else begin - $stop; + task kill_me_after_1ns(); + fork + #1 proc.kill(); + #3 begin + $write("*-* All Finished *-*\n"); + $finish; end - end + join_none + endtask + + always @(posedge clk) begin + if (!b) begin + proc = std::process::self(); + kill_me_after_1ns(); + b = 1; + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_prof.v b/test_regress/t/t_prof.v index 9bce13891..fbd1dddfe 100644 --- a/test_regress/t/t_prof.v +++ b/test_regress/t/t_prof.v @@ -6,74 +6,74 @@ module t( `ifdef T_PROF - clk + clk `endif - ); + ); `ifdef T_PROF - input clk; + input clk; `else - bit clk; - initial forever begin #5; clk = !clk; end + bit clk; + initial forever begin #5; clk = !clk; end `endif - integer cyc = 0; - wire [63:0] result; + integer cyc = 0; + wire [63:0] result; - Test test(/*AUTOINST*/ - // Outputs - .result (result[63:0]), - // Inputs - .clk (clk), - .cyc (cyc)); + Test test(/*AUTOINST*/ + // Outputs + .result (result[63:0]), + // Inputs + .clk (clk), + .cyc (cyc)); - reg [63:0] sum; + reg [63:0] sum; - always @ (posedge clk) begin + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d result=%x\n", $time, cyc, result); + $write("[%0t] cyc==%0d result=%x\n", $time, cyc, result); `endif - cyc <= cyc + 1; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hfefad16f06ba6b1f - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - result, - // Inputs - clk, cyc - ); + // Outputs + result, + // Inputs + clk, cyc + ); - input clk; - input int cyc; - output reg [63:0] result; + input clk; + input int cyc; + output reg [63:0] result; - logic [63:0] adder; + logic [63:0] adder; - always @(posedge clk) begin - adder = 0; - for (int i = 0; i < 1000; ++i) - adder += {32'h0, (cyc+i)} ** 3; + always @(posedge clk) begin + adder = 0; + for (int i = 0; i < 1000; ++i) + adder += {32'h0, (cyc+i)} ** 3; - result <= adder; - end + result <= adder; + end endmodule diff --git a/test_regress/t/t_property.v b/test_regress/t/t_property.v index b7b196b1f..2e5a06007 100644 --- a/test_regress/t/t_property.v +++ b/test_regress/t/t_property.v @@ -4,55 +4,54 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .cyc (cyc[31:0])); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .cyc(cyc[31:0]) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test - ( - input clk, - input [31:0] cyc - ); +module Test ( + input clk, + input [31:0] cyc +); `ifdef FAIL_ASSERT_1 - assert property (@(posedge clk) cyc==3) - else $display("cyc != 3, cyc == %0d", cyc); - assume property (@(posedge clk) cyc==3) - else $display("cyc != 3, cyc == %0d", cyc); + assert property (@(posedge clk) cyc == 3) + else $display("cyc != 3, cyc == %0d", cyc); + assume property (@(posedge clk) cyc == 3) + else $display("cyc != 3, cyc == %0d", cyc); `endif `ifdef FAIL_ASSERT_2 - assert property (@(posedge clk) cyc!=3); - assume property (@(posedge clk) cyc!=3); + assert property (@(posedge clk) cyc != 3); + assume property (@(posedge clk) cyc != 3); `endif - assert property (@(posedge clk) cyc < 100); - assume property (@(posedge clk) cyc < 100); + assert property (@(posedge clk) cyc < 100); + assume property (@(posedge clk) cyc < 100); - restrict property (@(posedge clk) cyc==1); // Ignored in simulators + restrict property (@(posedge clk) cyc == 1); // Ignored in simulators -// Unclocked is not supported: -// assert property (cyc != 6); + // Unclocked is not supported: + // assert property (cyc != 6); endmodule diff --git a/test_regress/t/t_property_named.v b/test_regress/t/t_property_named.v index 85d707eae..cf855e5c0 100644 --- a/test_regress/t/t_property_named.v +++ b/test_regress/t/t_property_named.v @@ -5,79 +5,79 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - clk - ); + clk + ); - input clk; - int cyc = 0; - logic val = 0; + input clk; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int cyc_mod_2, logic expected); - @(posedge clk) - cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(int cyc_mod_2, logic expected); + @(posedge clk) + cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - // Also checks parsing 'var datatype' - property check_if_1(var int cyc_mod_2); - check(cyc_mod_2, 1); - endproperty + // Also checks parsing 'var datatype' + property check_if_1(var int cyc_mod_2); + check(cyc_mod_2, 1); + endproperty - // Also checks parsing 'signing range' - property check_if_gt_5(signed [31:0] cyc); - @(posedge clk) - cyc > 5; - endproperty + // Also checks parsing 'signing range' + property check_if_gt_5(signed [31:0] cyc); + @(posedge clk) + cyc > 5; + endproperty - property pass_assertion(int cyc); - disable iff (cyc <= 10) - cyc > 10; - endproperty + property pass_assertion(int cyc); + disable iff (cyc <= 10) + cyc > 10; + endproperty - int expected_fails = 0; + int expected_fails = 0; - assert property(check(0, 1)) - else begin - // Assertion should pass - $display("[%0t] Assert failed, but shouldn't", $time); - $stop; - end - assert property(check(1, 1)) - else begin - // Assertion should fail - expected_fails += 1; - end - assert property(check_if_1(1)) - else begin - // Assertion should fail - expected_fails += 1; - end + assert property(check(0, 1)) + else begin + // Assertion should pass + $display("[%0t] Assert failed, but shouldn't", $time); + $stop; + end + assert property(check(1, 1)) + else begin + // Assertion should fail + expected_fails += 1; + end + assert property(check_if_1(1)) + else begin + // Assertion should fail + expected_fails += 1; + end - logic out = 1; + logic out = 1; - property prop_a; - @(posedge clk) disable iff (cyc <= 1) out; - endproperty : prop_a + property prop_a; + @(posedge clk) disable iff (cyc <= 1) out; + endproperty : prop_a - property prop_b(); - @(posedge clk) disable iff (cyc <= 1) out; - endproperty : prop_b + property prop_b(); + @(posedge clk) disable iff (cyc <= 1) out; + endproperty : prop_b - assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1)); - assert property(@(posedge clk) pass_assertion(cyc)); - assert property (prop_a) else $error($sformatf("property check failed :assert: (False)")); - assert property (prop_a()) else $error($sformatf("property check failed :assert: (False)")); - assert property (prop_b) else $error($sformatf("property check failed :assert: (False)")); - assert property (prop_b()) else $error($sformatf("property check failed :assert: (False)")); + assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1)); + assert property(@(posedge clk) pass_assertion(cyc)); + assert property (prop_a) else $error($sformatf("property check failed :assert: (False)")); + assert property (prop_a()) else $error($sformatf("property check failed :assert: (False)")); + assert property (prop_b) else $error($sformatf("property check failed :assert: (False)")); + assert property (prop_b()) else $error($sformatf("property check failed :assert: (False)")); - always @(posedge clk) begin - if (expected_fails == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (expected_fails == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_property_negated.v b/test_regress/t/t_property_negated.v index 72f4772a0..142c8875c 100644 --- a/test_regress/t/t_property_negated.v +++ b/test_regress/t/t_property_negated.v @@ -7,44 +7,44 @@ `define MAX 10 module t (/*AUTOARG*/ - clk - ); + clk + ); - input clk; - int cyc = 0; - logic [`MAX:0] val = {`MAX+1{1'b0}}; + input clk; + int cyc = 0; + logic [`MAX:0] val = {`MAX+1{1'b0}}; - initial val[0] = 1; + initial val[0] = 1; - Test1 t1(clk, cyc, val); + Test1 t1(clk, cyc, val); - always @(posedge clk) begin - cyc <= cyc + 1; + always @(posedge clk) begin + cyc <= cyc + 1; - $display("val = %20b", val); + $display("val = %20b", val); - if (cyc < `MAX) begin - val[cyc] <= 0; - val[cyc+1] <= 1; - end else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc < `MAX) begin + val[cyc] <= 0; + val[cyc+1] <= 1; + end else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test1 ( - clk, - cyc, - val - ); + clk, + cyc, + val + ); - input clk; - input [`MAX:0] val; - input integer cyc; + input clk; + input [`MAX:0] val; + input integer cyc; - assert property(@(posedge clk) not (&val)); + assert property(@(posedge clk) not (&val)); - assert property(@(posedge clk) (not ~|val)); + assert property(@(posedge clk) (not ~|val)); endmodule diff --git a/test_regress/t/t_property_pexpr_unsup.out b/test_regress/t/t_property_pexpr_unsup.out index fb003c30c..72bf6e6d1 100644 --- a/test_regress/t/t_property_pexpr_unsup.out +++ b/test_regress/t/t_property_pexpr_unsup.out @@ -1,101 +1,101 @@ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:25:13: Unsupported: strong (in property expression) - 25 | strong(a); - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:29:11: Unsupported: weak (in property expression) - 29 | weak(a); +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:23:11: Unsupported: strong (in property expression) + 23 | strong(a); | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:33:9: Unsupported: until (in property expression) - 33 | a until b; - | ^~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:37:9: Unsupported: s_until (in property expression) - 37 | a s_until b; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:41:9: Unsupported: until_with (in property expression) - 41 | a until_with b; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:45:9: Unsupported: s_until_with (in property expression) - 45 | a s_until_with b; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:49:9: Unsupported: #-# (in property expression) - 49 | a #-# b; - | ^~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:53:9: Unsupported: #=# (in property expression) - 53 | a #=# b; - | ^~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:57:7: Unsupported: nexttime (in property expression) - 57 | nexttime a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:61:7: Unsupported: nexttime[] (in property expression) - 61 | nexttime [2] a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:65:7: Unsupported: s_nexttime (in property expression) - 65 | s_nexttime a; + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:27:9: Unsupported: weak (in property expression) + 27 | weak(a); + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:31:7: Unsupported: until (in property expression) + 31 | a until b; + | ^~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:35:7: Unsupported: s_until (in property expression) + 35 | a s_until b; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:39:7: Unsupported: until_with (in property expression) + 39 | a until_with b; | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:69:7: Unsupported: s_nexttime[] (in property expression) - 69 | s_nexttime [2] a; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:73:16: Unsupported: always (in property expression) - 73 | nexttime always a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:73:7: Unsupported: nexttime (in property expression) - 73 | nexttime always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:77:20: Unsupported: always (in property expression) - 77 | nexttime [2] always a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:77:7: Unsupported: nexttime[] (in property expression) - 77 | nexttime [2] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:81:20: Unsupported: always (in property expression) - 81 | nexttime [2] always a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:81:7: Unsupported: nexttime[] (in property expression) - 81 | nexttime [2] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:85:16: Unsupported: s_eventually (in property expression) - 85 | nexttime s_eventually a; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:85:7: Unsupported: nexttime (in property expression) - 85 | nexttime s_eventually a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:35: Unsupported: always (in property expression) - 89 | nexttime s_eventually [2:$] always a; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:16: Unsupported: s_eventually[] (in property expression) - 89 | nexttime s_eventually [2:$] always a; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:7: Unsupported: nexttime (in property expression) - 89 | nexttime s_eventually [2:$] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:93:17: Unsupported: accept_on (in property expression) - 93 | accept_on (a) b; - | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:97:22: Unsupported: sync_accept_on (in property expression) - 97 | sync_accept_on (a) b; - | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:101:17: Unsupported: reject_on (in property expression) - 101 | reject_on (a) b; - | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:105:22: Unsupported: sync_reject_on (in property expression) - 105 | sync_reject_on (a) b; - | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:108:27: Unsupported: property argument data type - 108 | property p_arg_propery(property inprop); - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:111:27: Unsupported: sequence argument data type - 111 | property p_arg_seqence(sequence inseq); - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:116:7: Unsupported: property case expression - 116 | case (a) endcase - | ^~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:119:7: Unsupported: property case expression - 119 | case (a) default: b; endcase - | ^~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:122:7: Unsupported: property case expression - 122 | if (a) b - | ^~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:125:7: Unsupported: property case expression - 125 | if (a) b else c - | ^~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:43:7: Unsupported: s_until_with (in property expression) + 43 | a s_until_with b; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:47:7: Unsupported: #-# (in property expression) + 47 | a #-# b; + | ^~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:51:7: Unsupported: #=# (in property expression) + 51 | a #=# b; + | ^~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:55:5: Unsupported: nexttime (in property expression) + 55 | nexttime a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:59:5: Unsupported: nexttime[] (in property expression) + 59 | nexttime [2] a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:63:5: Unsupported: s_nexttime (in property expression) + 63 | s_nexttime a; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:67:5: Unsupported: s_nexttime[] (in property expression) + 67 | s_nexttime [2] a; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:71:14: Unsupported: always (in property expression) + 71 | nexttime always a; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:71:5: Unsupported: nexttime (in property expression) + 71 | nexttime always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:75:18: Unsupported: always (in property expression) + 75 | nexttime [2] always a; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:75:5: Unsupported: nexttime[] (in property expression) + 75 | nexttime [2] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:79:18: Unsupported: always (in property expression) + 79 | nexttime [2] always a; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:79:5: Unsupported: nexttime[] (in property expression) + 79 | nexttime [2] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:83:14: Unsupported: s_eventually (in property expression) + 83 | nexttime s_eventually a; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:83:5: Unsupported: nexttime (in property expression) + 83 | nexttime s_eventually a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:87:33: Unsupported: always (in property expression) + 87 | nexttime s_eventually [2:$] always a; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:87:14: Unsupported: s_eventually[] (in property expression) + 87 | nexttime s_eventually [2:$] always a; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:87:5: Unsupported: nexttime (in property expression) + 87 | nexttime s_eventually [2:$] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:91:15: Unsupported: accept_on (in property expression) + 91 | accept_on (a) b; + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:95:20: Unsupported: sync_accept_on (in property expression) + 95 | sync_accept_on (a) b; + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:99:15: Unsupported: reject_on (in property expression) + 99 | reject_on (a) b; + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:103:20: Unsupported: sync_reject_on (in property expression) + 103 | sync_reject_on (a) b; + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:106:26: Unsupported: property argument data type + 106 | property p_arg_propery(property inprop); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:109:26: Unsupported: sequence argument data type + 109 | property p_arg_seqence(sequence inseq); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:114:5: Unsupported: property case expression + 114 | case (a) endcase + | ^~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:117:5: Unsupported: property case expression + 117 | case (a) default: b; endcase + | ^~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:120:5: Unsupported: property case expression + 120 | if (a) b + | ^~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:123:5: Unsupported: property case expression + 123 | if (a) b else c + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_property_pexpr_unsup.v b/test_regress/t/t_property_pexpr_unsup.v index 464ca558b..2acbb3b40 100644 --- a/test_regress/t/t_property_pexpr_unsup.v +++ b/test_regress/t/t_property_pexpr_unsup.v @@ -4,131 +4,129 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; - int a; - int b; - int c; - int cyc = 0; + int a; + int b; + int c; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end - // NOTE this grammar hasn't been checked with other simulators, - // is here just to avoid uncovered code lines in the grammar. - property p_strong; - strong(a); - endproperty + // NOTE this grammar hasn't been checked with other simulators, + // is here just to avoid uncovered code lines in the grammar. + property p_strong; + strong(a); + endproperty - property p_weak; - weak(a); - endproperty + property p_weak; + weak(a); + endproperty - property p_until; - a until b; - endproperty + property p_until; + a until b; + endproperty - property p_suntil; - a s_until b; - endproperty + property p_suntil; + a s_until b; + endproperty - property p_untilwith; - a until_with b; - endproperty + property p_untilwith; + a until_with b; + endproperty - property p_suntilwith; - a s_until_with b; - endproperty + property p_suntilwith; + a s_until_with b; + endproperty - property p_poundminuspound1; - a #-# b; - endproperty + property p_poundminuspound1; + a #-# b; + endproperty - property p_poundeqpound; - a #=# b; - endproperty + property p_poundeqpound; + a #=# b; + endproperty - property p_nexttime; - nexttime a; - endproperty + property p_nexttime; + nexttime a; + endproperty - property p_nexttime2; - nexttime [2] a; - endproperty + property p_nexttime2; + nexttime [2] a; + endproperty - property p_snexttime; - s_nexttime a; - endproperty + property p_snexttime; + s_nexttime a; + endproperty - property p_snexttime2; - s_nexttime [2] a; - endproperty + property p_snexttime2; + s_nexttime [2] a; + endproperty - property p_nexttime_always; - nexttime always a; - endproperty + property p_nexttime_always; + nexttime always a; + endproperty - property p_nexttime_always2; - nexttime [2] always a; - endproperty + property p_nexttime_always2; + nexttime [2] always a; + endproperty - property p_nexttime_eventually2; - nexttime [2] always a; - endproperty + property p_nexttime_eventually2; + nexttime [2] always a; + endproperty - property p_nexttime_seventually; - nexttime s_eventually a; - endproperty + property p_nexttime_seventually; + nexttime s_eventually a; + endproperty - property p_nexttime_seventually2; - nexttime s_eventually [2:$] always a; - endproperty + property p_nexttime_seventually2; + nexttime s_eventually [2:$] always a; + endproperty - property p_accepton; - accept_on (a) b; - endproperty + property p_accepton; + accept_on (a) b; + endproperty - property p_syncaccepton; - sync_accept_on (a) b; - endproperty + property p_syncaccepton; + sync_accept_on (a) b; + endproperty - property p_rejecton; - reject_on (a) b; - endproperty + property p_rejecton; + reject_on (a) b; + endproperty - property p_syncrejecton; - sync_reject_on (a) b; - endproperty + property p_syncrejecton; + sync_reject_on (a) b; + endproperty - property p_arg_propery(property inprop); - inprop; - endproperty - property p_arg_seqence(sequence inseq); - inseq; - endproperty + property p_arg_propery(property inprop); + inprop; + endproperty + property p_arg_seqence(sequence inseq); + inseq; + endproperty - property p_case_1; - case (a) endcase - endproperty - property p_case_2; - case (a) default: b; endcase - endproperty - property p_if; - if (a) b - endproperty - property p_ifelse; - if (a) b else c - endproperty + property p_case_1; + case (a) endcase + endproperty + property p_case_2; + case (a) default: b; endcase + endproperty + property p_if; + if (a) b + endproperty + property p_ifelse; + if (a) b else c + endproperty - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_property_recursive_unsup.out b/test_regress/t/t_property_recursive_unsup.out index a55a38ac1..d35dd7c53 100644 --- a/test_regress/t/t_property_recursive_unsup.out +++ b/test_regress/t/t_property_recursive_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_property_recursive_unsup.v:20:13: Unsupported: Recursive property call: 'check' +%Error-UNSUPPORTED: t/t_property_recursive_unsup.v:19:12: Unsupported: Recursive property call: 'check' : ... note: In instance 't' - 20 | property check(int n); - | ^~~~~ + 19 | property check(int n); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_property_recursive_unsup.v b/test_regress/t/t_property_recursive_unsup.v index 9acff81ba..175d1e6df 100644 --- a/test_regress/t/t_property_recursive_unsup.v +++ b/test_regress/t/t_property_recursive_unsup.v @@ -4,33 +4,33 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int n); - disable iff (n == 0) - check(n - 1); - endproperty + property check(int n); + disable iff (n == 0) check( + n - 1 + ); + endproperty - assert property(@(posedge clk) check(1)) - else begin - // Assertion should pass - $write("*-* Assertion failed *-*\n"); - $stop; - end + assert property (@(posedge clk) check(1)) + else begin + // Assertion should pass + $write("*-* Assertion failed *-*\n"); + $stop; + end - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_property_sexpr_disable.v b/test_regress/t/t_property_sexpr_disable.v index b2df8471f..f934a166c 100644 --- a/test_regress/t/t_property_sexpr_disable.v +++ b/test_regress/t/t_property_sexpr_disable.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; - typedef struct { int fails; int passs; diff --git a/test_regress/t/t_property_sexpr_disable_sampled_unsup.out b/test_regress/t/t_property_sexpr_disable_sampled_unsup.out index 9c988bb01..cafbb5d6a 100644 --- a/test_regress/t/t_property_sexpr_disable_sampled_unsup.out +++ b/test_regress/t/t_property_sexpr_disable_sampled_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_property_sexpr_disable_sampled_unsup.v:23:48: Unsupported: $sampled inside disabled condition of a sequence +%Error-UNSUPPORTED: t/t_property_sexpr_disable_sampled_unsup.v:21:48: Unsupported: $sampled inside disabled condition of a sequence : ... note: In instance 't' - 23 | assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) 1 ##1 cyc % 3 == 0) passes++; + 21 | assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) 1 ##1 cyc % 3 == 0) passes++; | ^~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_property_sexpr_disable_sampled_unsup.v b/test_regress/t/t_property_sexpr_disable_sampled_unsup.v index 1172b73c1..3375f3af5 100644 --- a/test_regress/t/t_property_sexpr_disable_sampled_unsup.v +++ b/test_regress/t/t_property_sexpr_disable_sampled_unsup.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; - localparam MAX = 10; int cyc = 0; int passes = 0; diff --git a/test_regress/t/t_property_untyped.v b/test_regress/t/t_property_untyped.v index e13764522..b74f88cb4 100644 --- a/test_regress/t/t_property_untyped.v +++ b/test_regress/t/t_property_untyped.v @@ -4,35 +4,33 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic [4:0] val = 0; + int cyc = 0; + logic [4:0] val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(cyc_mod_2, untyped expected); - @(posedge clk) - cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(cyc_mod_2, untyped expected); + @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - assert property(check(0, 5'b11111)) - else begin - // Assertion should pass - $display("[%0t] Assert failed, but shouldn't", $time); - $stop; - end + assert property (check(0, 5'b11111)) + else begin + // Assertion should pass + $display("[%0t] Assert failed, but shouldn't", $time); + $stop; + end - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_property_untyped_unsup.out b/test_regress/t/t_property_untyped_unsup.out index 5b663f222..1d693ab3f 100644 --- a/test_regress/t/t_property_untyped_unsup.out +++ b/test_regress/t/t_property_untyped_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_property_untyped_unsup.v:20:52: Untyped property port following a typed port - 20 | property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); - | ^~~~ +%Error-UNSUPPORTED: t/t_property_untyped_unsup.v:19:51: Untyped property port following a typed port + 19 | property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); + | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_property_untyped_unsup.v b/test_regress/t/t_property_untyped_unsup.v index 9bdb57374..f850ee8e3 100644 --- a/test_regress/t/t_property_untyped_unsup.v +++ b/test_regress/t/t_property_untyped_unsup.v @@ -4,30 +4,28 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic [4:0] val = 0; + int cyc = 0; + logic [4:0] val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); - @(posedge clk) - cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); + @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - assert property(check(0, 5'b11111, 100, 25, 17)); + assert property (check(0, 5'b11111, 100, 25, 17)); - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_property_var_unsup.out b/test_regress/t/t_property_var_unsup.out index 443e262b2..5fffe4942 100644 --- a/test_regress/t/t_property_var_unsup.out +++ b/test_regress/t/t_property_var_unsup.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_property_var_unsup.v:18:13: Unsupported: sequence match items - 18 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); - | ^ +%Error-UNSUPPORTED: t/t_property_var_unsup.v:16:11: Unsupported: sequence match items + 16 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_var_unsup.v:17:11: Unsupported: property variable declaration - 17 | int prevcyc; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_var_unsup.v:24:31: Unsupported: property variable default value - 24 | property with_def(int nine = 9); - | ^ +%Error-UNSUPPORTED: t/t_property_var_unsup.v:15:9: Unsupported: property variable declaration + 15 | int prevcyc; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_property_var_unsup.v:23:30: Unsupported: property variable default value + 23 | property with_def(int nine = 9); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_property_var_unsup.v b/test_regress/t/t_property_var_unsup.v index 30091f240..b58e61148 100644 --- a/test_regress/t/t_property_var_unsup.v +++ b/test_regress/t/t_property_var_unsup.v @@ -4,35 +4,34 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc; - bit valid; + int cyc; + bit valid; - property prop; - int prevcyc; - (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); - endproperty + property prop; + int prevcyc; + (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); + endproperty - default clocking @(posedge clk); endclocking - assert property(prop); + default clocking @(posedge clk); + endclocking + assert property (prop); - property with_def(int nine = 9); - cyc == 9 |-> cyc == nine; - endproperty + property with_def(int nine = 9); + cyc == 9 |-> cyc == nine; + endproperty - assert property(with_def); + assert property (with_def); - always @(posedge clk) begin - cyc <= cyc + 1; - valid <= cyc == 5; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + valid <= cyc == 5; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_protect_ids.v b/test_regress/t/t_protect_ids.v index 9f2bf7e9f..5527a15cc 100644 --- a/test_regress/t/t_protect_ids.v +++ b/test_regress/t/t_protect_ids.v @@ -4,74 +4,79 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface secret_intf(); - logic secret_a; - integer secret_b; +interface secret_intf (); + logic secret_a; + integer secret_b; endinterface -module t (/*AUTOARG*/ - // Inputs - clk +module t ( + input clk +); + + secret_sub secret_inst (.*); + secret_other secret_inst2 (.*); +endmodule + +module secret_sub ( + input clk +); + + // verilator no_inline_module + + typedef struct { + integer secret_field; + integer secret_field_r; + } secret_st; + + int secret_cyc; + real secret_cyc_r; + integer secret_o; + real secret_r; + secret_st secret_pair; + + export "DPI-C" task dpix_a_task; + task dpix_a_task(input int i, output int o); + o = i + 1; + endtask + import "DPI-C" context task dpii_a_task( + input int i, + output int o ); - input clk; - secret_sub secret_inst (.*); - secret_other secret_inst2 (.*); -endmodule + export "DPI-C" function dpix_a_func; + function int dpix_a_func(input int i); + return i + 2; + endfunction + import "DPI-C" context function int dpii_a_func(input int i); -module secret_sub - ( - input clk); - - // verilator no_inline_module - - typedef struct { - integer secret_field; - integer secret_field_r; - } secret_st; - - int secret_cyc; - real secret_cyc_r; - integer secret_o; - real secret_r; - secret_st secret_pair; - - export "DPI-C" task dpix_a_task; - task dpix_a_task(input int i, output int o); o = i + 1; endtask - import "DPI-C" context task dpii_a_task(input int i, output int o); - - export "DPI-C" function dpix_a_func; - function int dpix_a_func(input int i); return i + 2; endfunction - import "DPI-C" context function int dpii_a_func(input int i); - - // Test loop - always @ (posedge clk) begin - secret_pair.secret_field += 1; - secret_pair.secret_field_r += 2; - secret_cyc_r = $itor(secret_cyc)/10.0 - 5.0; - secret_cyc <= dpii_a_func(secret_cyc); - secret_r += 1.0 + $cos(secret_cyc_r); - dpix_a_task(secret_cyc, secret_o); - if (secret_cyc==90) begin - $write("*-* All Finished *-*\n"); - end - end + // Test loop + always @(posedge clk) begin + secret_pair.secret_field += 1; + secret_pair.secret_field_r += 2; + secret_cyc_r = $itor(secret_cyc) / 10.0 - 5.0; + secret_cyc <= dpii_a_func(secret_cyc); + secret_r += 1.0 + $cos(secret_cyc_r); + dpix_a_task(secret_cyc, secret_o); + if (secret_cyc == 90) begin + $write("*-* All Finished *-*\n"); + end + end endmodule -module secret_other - ( - input clk); +module secret_other ( + input clk +); - int secret_cyc; + int secret_cyc; - always @ (posedge clk) begin - secret_cyc <= secret_cyc + 1; - if (secret_cyc==99) begin - $finish; - end - end + always @(posedge clk) begin + secret_cyc <= secret_cyc + 1; + if (secret_cyc == 99) begin + $finish; + end + end - secret_intf secret_interface(); + secret_intf secret_interface (); endmodule diff --git a/test_regress/t/t_public_clk.v b/test_regress/t/t_public_clk.v index cd40d635f..5f8ae4068 100644 --- a/test_regress/t/t_public_clk.v +++ b/test_regress/t/t_public_clk.v @@ -14,15 +14,15 @@ module t; - logic clk /* verilator public_flat_rw */; - int count; - wire other_clk = `IMPURE_ONE & clk; + logic clk /* verilator public_flat_rw */; + int count; + wire other_clk = `IMPURE_ONE & clk; - always_ff @(posedge other_clk) begin - count <= count + 1; - if (count == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always_ff @(posedge other_clk) begin + count <= count + 1; + if (count == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_public_seq.v b/test_regress/t/t_public_seq.v index ce55d349a..8bafb689c 100644 --- a/test_regress/t/t_public_seq.v +++ b/test_regress/t/t_public_seq.v @@ -13,32 +13,32 @@ `endif module t ( - input clk, - input dummy_clk // Never toggled from C++ + input clk, + input dummy_clk // Never toggled from C++ ); - int count; + int count; - logic [7:0] pub_byte /* verilator public_flat_rw */ = 123; - logic [7:0] comb_byte; + logic [7:0] pub_byte /* verilator public_flat_rw */ = 123; + logic [7:0] comb_byte; - always_comb comb_byte = `IMPURE_ONE ? pub_byte : '0; + always_comb comb_byte = `IMPURE_ONE ? pub_byte : '0; - always_ff @(posedge clk) begin - count <= count + 1; - if (comb_byte != pub_byte) begin - $display("%%Error: comb_byte (%0d) != pub_byte (%0d)", comb_byte, pub_byte); - $stop; - end - if (count == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always_ff @(posedge clk) begin + count <= count + 1; + if (comb_byte != pub_byte) begin + $display("%%Error: comb_byte (%0d) != pub_byte (%0d)", comb_byte, pub_byte); + $stop; + end + if (count == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_ff @(posedge dummy_clk) begin - // verilator lint_off MULTIDRIVEN - comb_byte = ~pub_byte; - // verilator lint_on MULTIDRIVEN - end + always_ff @(posedge dummy_clk) begin + // verilator lint_off MULTIDRIVEN + comb_byte = ~pub_byte; + // verilator lint_on MULTIDRIVEN + end endmodule diff --git a/test_regress/t/t_public_unpacked_port.v b/test_regress/t/t_public_unpacked_port.v index 2384f3a4f..cb5c4c1d8 100644 --- a/test_regress/t/t_public_unpacked_port.v +++ b/test_regress/t/t_public_unpacked_port.v @@ -4,52 +4,51 @@ // SPDX-License-Identifier: CC0-1.0 module sub ( - output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */, - input logic sub_clk, - input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */ - ); + output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */, + input logic sub_clk, + input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */ +); - // Evaluate clock edges - always @(posedge sub_clk) begin - sub_s1up_out <= sub_s1up_in; - end + // Evaluate clock edges + always @(posedge sub_clk) begin + sub_s1up_out <= sub_s1up_in; + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - logic [31:0] s1up_in[1]; - logic [31:0] s1up_out[1]; + integer cyc = 0; + logic [31:0] s1up_in[1]; + logic [31:0] s1up_out[1]; - sub the_sub ( - .sub_s1up_in (s1up_in), - .sub_s1up_out (s1up_out), - .sub_clk (clk)); + sub the_sub ( + .sub_s1up_in(s1up_in), + .sub_s1up_out(s1up_out), + .sub_clk(clk) + ); - always_comb s1up_in[0] = cyc; + always_comb s1up_in[0] = cyc; - always @(posedge clk) begin - cyc <= cyc + 1; + always @(posedge clk) begin + cyc <= cyc + 1; - if (cyc == 10) begin - if (s1up_out[0] != 9) begin - $display("%%Error: got %0d instead of 9", s1up_out); - $stop; - end - if (the_sub.sub_s1up_in[0] != 10) begin - $display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]); - $stop; - end - $display("final cycle = %0d", cyc); - $write("*-* All Finished *-*\n"); - $finish; + if (cyc == 10) begin + if (s1up_out[0] != 9) begin + $display("%%Error: got %0d instead of 9", s1up_out); + $stop; end - end + if (the_sub.sub_s1up_in[0] != 10) begin + $display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]); + $stop; + end + $display("final cycle = %0d", cyc); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_randc.v b/test_regress/t/t_randc.v index 409a30a95..7947daad1 100644 --- a/test_regress/t/t_randc.v +++ b/test_regress/t/t_randc.v @@ -4,131 +4,135 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class ClsNarrow #(parameter int WIDTH); - randc bit [WIDTH-1:0] m_var; +class ClsNarrow #( + parameter int WIDTH +); + randc bit [WIDTH-1:0] m_var; - function void test; - automatic int i; - automatic int count[2**WIDTH]; - automatic int maxcount; - automatic bit bad; - automatic int randomize_result; - $display("Test %m"); - for (int trial = 0; trial < 10; ++trial) begin - for (i = 0; i < (2 ** WIDTH); ++i) begin - randomize_result = randomize(); - if (randomize_result !== 1) $stop; -`ifdef TEST_VERBOSE - $display("w%0d i=%0d m_var=%x", WIDTH, i, m_var); -`endif - ++count[m_var]; - end - end - maxcount = count[0]; - bad = '0; -`ifndef TEST_IGNORE_RANDC + function void test; + automatic int i; + automatic int count[2**WIDTH]; + automatic int maxcount; + automatic bit bad; + automatic int randomize_result; + $display("Test %m"); + for (int trial = 0; trial < 10; ++trial) begin for (i = 0; i < (2 ** WIDTH); ++i) begin - if (maxcount != count[i]) bad = '1; - end + randomize_result = randomize(); + if (randomize_result !== 1) $stop; +`ifdef TEST_VERBOSE + $display("w%0d i=%0d m_var=%x", WIDTH, i, m_var); `endif - if (bad) begin - $display("%%Error: count mismatch"); - for (i = 0; i < (2 ** WIDTH); ++i) begin - $display("w%0d entry[%0d]=%0d", WIDTH, i, count[i]); - end - $stop; + ++count[m_var]; end - endfunction + end + maxcount = count[0]; + bad = '0; +`ifndef TEST_IGNORE_RANDC + for (i = 0; i < (2 ** WIDTH); ++i) begin + if (maxcount != count[i]) bad = '1; + end +`endif + if (bad) begin + $display("%%Error: count mismatch"); + for (i = 0; i < (2 ** WIDTH); ++i) begin + $display("w%0d entry[%0d]=%0d", WIDTH, i, count[i]); + end + $stop; + end + endfunction endclass -class ClsWide #(parameter int WIDTH); - randc bit [WIDTH-1:0] m_var; +class ClsWide #( + parameter int WIDTH +); + randc bit [WIDTH-1:0] m_var; - function void test; - automatic bit [WIDTH-1:0] last; - automatic int randomize_result; - $display("Test %m"); - for (int i = 0; i < 100; ++i) begin - randomize_result = randomize(); - if (randomize_result !== 1) $stop; + function void test; + automatic bit [WIDTH-1:0] last; + automatic int randomize_result; + $display("Test %m"); + for (int i = 0; i < 100; ++i) begin + randomize_result = randomize(); + if (randomize_result !== 1) $stop; `ifdef TEST_VERBOSE - $display("ww%0d i=%0d m_var=%x", WIDTH, i, m_var); + $display("ww%0d i=%0d m_var=%x", WIDTH, i, m_var); `endif - if (i != 0) begin + if (i != 0) begin `ifndef TEST_IGNORE_RANDC - if (m_var == last) $stop; + if (m_var == last) $stop; `endif - end - last = m_var; end - endfunction + last = m_var; + end + endfunction endclass class ClsEnum; - typedef enum bit [3:0] { - TWO = 2, - FIVE = 5, - SIX = 6 - } enum_t; + typedef enum bit [3:0] { + TWO = 2, + FIVE = 5, + SIX = 6 + } enum_t; - randc enum_t m_var; + randc enum_t m_var; - function void test; - automatic enum_t last; - automatic int randomize_result; - $display("Test %m"); - for (int trial = 0; trial < 10; ++trial) begin - for (int i = 0; i < 3; ++i) begin - randomize_result = randomize(); - if (randomize_result !== 1) $stop; + function void test; + automatic enum_t last; + automatic int randomize_result; + $display("Test %m"); + for (int trial = 0; trial < 10; ++trial) begin + for (int i = 0; i < 3; ++i) begin + randomize_result = randomize(); + if (randomize_result !== 1) $stop; `ifdef TEST_VERBOSE - $display("we i=%0d m_var=%x", i, m_var); + $display("we i=%0d m_var=%x", i, m_var); `endif - if (m_var != TWO && m_var != FIVE && m_var != SIX) $stop; - if (i != 0) begin + if (m_var != TWO && m_var != FIVE && m_var != SIX) $stop; + if (i != 0) begin `ifndef TEST_IGNORE_RANDC - if (m_var == last) $stop; + if (m_var == last) $stop; `endif - end - last = m_var; - end + end + last = m_var; end - endfunction + end + endfunction endclass module t; - ClsNarrow #(1) c1; // Degenerate case - ClsNarrow #(2) c2; - ClsNarrow #(3) c3; - ClsNarrow #(3) c3b; // Need to have two of same size to cover dtype dedup code - ClsNarrow #(9) c9; - ClsWide #(31) c31; - ClsWide #(32) c32; - ClsEnum ce; + ClsNarrow #(1) c1; // Degenerate case + ClsNarrow #(2) c2; + ClsNarrow #(3) c3; + ClsNarrow #(3) c3b; // Need to have two of same size to cover dtype dedup code + ClsNarrow #(9) c9; + ClsWide #(31) c31; + ClsWide #(32) c32; + ClsEnum ce; - initial begin - c1 = new; - c1.test(); - c2 = new; - c2.test(); - c3 = new; - c3.test(); - c3b = new; - c3b.test(); - c9 = new; - c9.test(); - c31 = new; - c31.test(); - c32 = new; - c32.test(); - ce = new; - ce.test(); - $write("*-* All Finished *-*\n"); - $finish(); - end + initial begin + c1 = new; + c1.test(); + c2 = new; + c2.test(); + c3 = new; + c3.test(); + c3b = new; + c3b.test(); + c9 = new; + c9.test(); + c31 = new; + c31.test(); + c32 = new; + c32.test(); + ce = new; + ce.test(); + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_randc_oversize_bad.out b/test_regress/t/t_randc_oversize_bad.out index 0ca28a1a6..10e11df1d 100644 --- a/test_regress/t/t_randc_oversize_bad.out +++ b/test_regress/t/t_randc_oversize_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_randc_oversize_bad.v:8:21: Maximum implemented width for randc is 32 bits, 'i' is 38 bits +%Error: t/t_randc_oversize_bad.v:8:20: Maximum implemented width for randc is 32 bits, 'i' is 38 bits : ... note: In instance 't' - 8 | randc bit [37:0] i; - | ^ + 8 | randc bit [37:0] i; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_randc_oversize_bad.v b/test_regress/t/t_randc_oversize_bad.v index 63c8049f6..124513cd9 100644 --- a/test_regress/t/t_randc_oversize_bad.v +++ b/test_regress/t/t_randc_oversize_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - randc bit [37:0] i; + randc bit [37:0] i; endclass module t; - Cls c; - initial begin - c = new; - c.randomize; - end + Cls c; + initial begin + c = new; + c.randomize; + end endmodule diff --git a/test_regress/t/t_randcase.v b/test_regress/t/t_randcase.v index 583827916..a8becefc4 100644 --- a/test_regress/t/t_randcase.v +++ b/test_regress/t/t_randcase.v @@ -4,85 +4,87 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100) +// verilog_format: on module t; - localparam int COUNT = 1000; + localparam int COUNT = 1000; - int v; - int counts[8]; + int v; + int counts[8]; - function int randfunc(); - int i; + function int randfunc(); + int i; + randcase + 0: i = 50; // Never + 1: i = 100; + endcase + return i; + endfunction + + initial begin + if (randfunc() != 100) $stop; + + // + for (int i = 0; i < 8; ++i) counts[i] = 0; + for (int i = 0; i < COUNT; ++i) begin randcase - 0 : i = 50; // Never - 1 : i = 100; + 0: ; // Never + 0: counts[0]++; // Never + 1: counts[1]++; endcase - return i; - endfunction + end + `check_range(counts[0], 0, 0); + `check_range(counts[1], COUNT, COUNT); - initial begin - if (randfunc() != 100) $stop; + // + for (int i = 0; i < 8; ++i) counts[i] = 0; + for (int i = 0; i < COUNT; ++i) begin + randcase + i - i: counts[0]++; // Never + i + i + 1: counts[1]++; + endcase + end + `check_range(counts[0], 0, 0); + `check_range(counts[1], COUNT, COUNT); - // - for (int i = 0; i < 8; ++i) counts[i] = 0; - for (int i = 0; i < COUNT; ++i) begin - randcase - 0 : ; // Never - 0 : counts[0]++; // Never - 1 : counts[1]++; - endcase - end - `check_range(counts[0], 0, 0); - `check_range(counts[1], COUNT, COUNT); + // + for (int i = 0; i < 8; ++i) counts[i] = 0; + for (int i = 0; i < COUNT; ++i) begin + randcase + 1: counts[0]++; // Never + 4: counts[1]++; + endcase + end + `check_within_30_percent(counts[0], (COUNT * 1 / 5)); + `check_within_30_percent(counts[1], (COUNT * 4 / 5)); - // - for (int i = 0; i < 8; ++i) counts[i] = 0; - for (int i = 0; i < COUNT; ++i) begin - randcase - i - i : counts[0]++; // Never - i + i + 1: counts[1]++; - endcase - end - `check_range(counts[0], 0, 0); - `check_range(counts[1], COUNT, COUNT); + // + for (int i = 0; i < 8; ++i) counts[i] = 0; + for (int i = 0; i < COUNT; ++i) begin + randcase + 2: counts[0]++; // Never + 2: counts[1]++; // Never + 1: counts[2]++; // Never + 1: counts[3]++; // Never + 1: counts[4]++; // Never + 1: counts[5]++; // Never + 1: counts[6]++; // Never + 1: counts[7]++; // Never + endcase + end + `check_within_30_percent(counts[0], (COUNT * 2 / 10)); + `check_within_30_percent(counts[1], (COUNT * 2 / 10)); + `check_within_30_percent(counts[2], (COUNT * 1 / 10)); + `check_within_30_percent(counts[7], (COUNT * 1 / 10)); - // - for (int i = 0; i < 8; ++i) counts[i] = 0; - for (int i = 0; i < COUNT; ++i) begin - randcase - 1 : counts[0]++; // Never - 4 : counts[1]++; - endcase - end - `check_within_30_percent(counts[0], (COUNT * 1 / 5)); - `check_within_30_percent(counts[1], (COUNT * 4 / 5)); - - // - for (int i = 0; i < 8; ++i) counts[i] = 0; - for (int i = 0; i < COUNT; ++i) begin - randcase - 2 : counts[0]++; // Never - 2 : counts[1]++; // Never - 1 : counts[2]++; // Never - 1 : counts[3]++; // Never - 1 : counts[4]++; // Never - 1 : counts[5]++; // Never - 1 : counts[6]++; // Never - 1 : counts[7]++; // Never - endcase - end - `check_within_30_percent(counts[0], (COUNT * 2 / 10)); - `check_within_30_percent(counts[1], (COUNT * 2 / 10)); - `check_within_30_percent(counts[2], (COUNT * 1 / 10)); - `check_within_30_percent(counts[7], (COUNT * 1 / 10)); - - // - $write("*-* All Finished *-*\n"); - $finish; - end + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randcase_bad.v b/test_regress/t/t_randcase_bad.v index 110b4d9eb..15deeaf91 100644 --- a/test_regress/t/t_randcase_bad.v +++ b/test_regress/t/t_randcase_bad.v @@ -8,12 +8,12 @@ module t; - initial begin - randcase // Bad all zero weights - 0 : $stop; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + randcase // Bad all zero weights + 0: $stop; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize.v b/test_regress/t/t_randomize.v index 0a0231de6..54e5786c7 100644 --- a/test_regress/t/t_randomize.v +++ b/test_regress/t/t_randomize.v @@ -5,73 +5,73 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int header; // 0..7 - rand int length; // 0..15 - rand int sublength; // 0..15 - rand bit if_4; - rand bit iff_5_6; + rand int header; // 0..7 + rand int length; // 0..15 + rand int sublength; // 0..15 + rand bit if_4; + rand bit iff_5_6; - rand int array[2]; // 2,4,6 + rand int array[2]; // 2,4,6 - constraint empty {} + constraint empty {} - constraint size { - header > 0 && header <= 7; - length <= 15; - length >= header; - length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; - } + constraint size { + header > 0 && header <= 7; + length <= 15; + length >= header; + length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; + } - constraint ifs { - if (header > 4) { - if_4 == '1; - } - if (header == 5 || header == 6) { - iff_5_6 == '1; - } else { - iff_5_6 == '0; - } - } + constraint ifs { + if (header > 4) { + if_4 == '1; + } + if (header == 5 || header == 6) { + iff_5_6 == '1; + } else { + iff_5_6 == '0; + } + } - constraint arr_uniq { - foreach (array[i]) { - array[i] inside {2, 4, 6}; - } - unique { array[0], array[1] }; - } + constraint arr_uniq { + foreach (array[i]) { + array[i] inside {2, 4, 6}; + } + unique { array[0], array[1] }; + } - constraint order { solve length before header; } + constraint order { solve length before header; } - constraint dis { - soft sublength; - disable soft sublength; - sublength <= length; - } + constraint dis { + soft sublength; + disable soft sublength; + sublength <= length; + } endclass module t; - Packet p; + Packet p; - initial begin + initial begin - automatic int v; - automatic bit if_4 = '0; - p = new; - v = p.randomize(); - if (v != 1) $stop; - v = p.randomize() with {}; - if (v != 1) $stop; - v = p.randomize() with { if_4 == local::if_4; header == 2; }; - if (v != 1) $stop; - // verilator lint_off WIDTH - assert(p.randomize && p.randomize); // No parens, math - // verilator lint_on WIDTH + automatic int v; + automatic bit if_4 = '0; + p = new; + v = p.randomize(); + if (v != 1) $stop; + v = p.randomize() with {}; + if (v != 1) $stop; + v = p.randomize() with { if_4 == local::if_4; header == 2; }; + if (v != 1) $stop; + // verilator lint_off WIDTH + assert(p.randomize && p.randomize); // No parens, math + // verilator lint_on WIDTH - // TODO not testing other randomize forms as unused in UVM + // TODO not testing other randomize forms as unused in UVM - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.out b/test_regress/t/t_randomize_inline_var_ctl_bad.out index 35fb0186c..0b8dc2c1a 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.out +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.out @@ -1,26 +1,26 @@ -%Error: t/t_randomize_inline_var_ctl_bad.v:12:23: 'randomize()' argument must be a variable contained in 'Foo' +%Error: t/t_randomize_inline_var_ctl_bad.v:12:21: 'randomize()' argument must be a variable contained in 'Foo' : ... note: In instance 't' - 12 | void'(randomize(y)); - | ^ + 12 | void'(randomize(y)); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_randomize_inline_var_ctl_bad.v:26:46: 'randomize()' argument must be a variable contained in 'foo' +%Error: t/t_randomize_inline_var_ctl_bad.v:26:44: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' - 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - | ^ -%Error: t/t_randomize_inline_var_ctl_bad.v:26:53: 'randomize()' argument must be a variable contained in 'foo' + 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + | ^ +%Error: t/t_randomize_inline_var_ctl_bad.v:26:51: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' - 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - | ^ -%Error: t/t_randomize_inline_var_ctl_bad.v:26:59: 'randomize()' argument must be a variable contained in 'foo' + 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + | ^ +%Error: t/t_randomize_inline_var_ctl_bad.v:26:57: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' - 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - | ^ -%Error: t/t_randomize_inline_var_ctl_bad.v:26:66: 'randomize()' argument must be a variable contained in 'foo' + 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + | ^ +%Error: t/t_randomize_inline_var_ctl_bad.v:26:64: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' - 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - | ^~ -%Error: t/t_randomize_inline_var_ctl_bad.v:26:37: Cannot pass more arguments to 'randomize(null)' + 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + | ^~ +%Error: t/t_randomize_inline_var_ctl_bad.v:26:35: Cannot pass more arguments to 'randomize(null)' : ... note: In instance 't' - 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - | ^~~~ + 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.v b/test_regress/t/t_randomize_inline_var_ctl_bad.v index 6b806e823..00bee755b 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.v +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - int x; + int x; - function void test; - int y; - void'(randomize(y)); - endfunction + function void test; + int y; + void'(randomize(y)); + endfunction endclass class Bar; - int y; + int y; endclass module t; - initial begin - automatic Foo foo = new; - automatic Foo qux = new; - automatic Bar bar = new; - automatic int x; - void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); - end + initial begin + automatic Foo foo = new; + automatic Foo qux = new; + automatic Bar bar = new; + automatic int x; + void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); + end endmodule diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.out b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.out index 55527bd65..1da1b0d5a 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.out +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:20:37: Unsupported: Non-variable expression as 'randomize()' argument +%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:20:35: Unsupported: Non-variable expression as 'randomize()' argument : ... note: In instance 't' - 20 | void'(foo.randomize(Foo::get().x)); - | ^ + 20 | void'(foo.randomize(Foo::get().x)); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:21:34: Unsupported: Non-variable expression as 'randomize()' argument +%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:21:32: Unsupported: Non-variable expression as 'randomize()' argument : ... note: In instance 't' - 21 | void'(foo.randomize(foos[0].x)); - | ^ -%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:22:27: Unsupported: 'randomize(null)' + 21 | void'(foo.randomize(foos[0].x)); + | ^ +%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:22:25: Unsupported: 'randomize(null)' : ... note: In instance 't' - 22 | void'(foo.randomize(null)); - | ^~~~ + 22 | void'(foo.randomize(null)); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v index 96224aac2..c358a769d 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - int x; + int x; - static function Foo get; - Foo foo = new; - return foo; - endfunction + static function Foo get; + Foo foo = new; + return foo; + endfunction endclass module t; - initial begin - automatic Foo foo = Foo::get(); - automatic Foo foos[] = new[1]; - void'(foo.randomize(Foo::get().x)); - void'(foo.randomize(foos[0].x)); - void'(foo.randomize(null)); - end + initial begin + automatic Foo foo = Foo::get(); + automatic Foo foos[] = new[1]; + void'(foo.randomize(Foo::get().x)); + void'(foo.randomize(foos[0].x)); + void'(foo.randomize(null)); + end endmodule diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out index 9e62f0b8b..9f494f463 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out @@ -1,9 +1,9 @@ -%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_2.v:17:29: Unsupported: Inline random variable control with 'randomize()' called on complex expressions - 17 | initial void'(Foo::get().randomize(x)); - | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_2.v:17:28: Unsupported: Inline random variable control with 'randomize()' called on complex expressions + 17 | initial void'(Foo::get().randomize(x)); + | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_randomize_inline_var_ctl_unsup_2.v:17:39: Can't find definition of variable: 'x' - 17 | initial void'(Foo::get().randomize(x)); - | ^ +%Error: t/t_randomize_inline_var_ctl_unsup_2.v:17:38: Can't find definition of variable: 'x' + 17 | initial void'(Foo::get().randomize(x)); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v index c8f44779a..bca32c189 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - int x; + int x; - static function Foo get; - Foo foo = new; - return foo; - endfunction + static function Foo get; + Foo foo = new; + return foo; + endfunction endclass module t; - initial void'(Foo::get().randomize(x)); + initial void'(Foo::get().randomize(x)); endmodule diff --git a/test_regress/t/t_randomize_method.v b/test_regress/t/t_randomize_method.v index d5fa914c0..eed69f2ed 100644 --- a/test_regress/t/t_randomize_method.v +++ b/test_regress/t/t_randomize_method.v @@ -20,206 +20,206 @@ begin \ if (ok != 1) $stop; \ end -typedef enum bit[15:0] { - ONE = 3, - TWO = 5, - THREE = 8, - FOUR = 13 +typedef enum bit [15:0] { + ONE = 3, + TWO = 5, + THREE = 8, + FOUR = 13 } Enum; typedef struct packed { - int a; - bit b; - Enum c; + int a; + bit b; + Enum c; } StructInner; typedef struct packed { - bit x; - StructInner s; - Enum y; - longint z; + bit x; + StructInner s; + Enum y; + longint z; } StructOuter; typedef struct { - int i; - StructOuter j; - Enum k; - longint z; + int i; + StructOuter j; + Enum k; + longint z; } StructUnpacked; class BaseCls1; endclass class Inner; - rand logic[7:0] a; - rand logic[15:0] b; - rand logic[3:0] c; - rand logic[11:0] d; - int e; + rand logic [7:0] a; + rand logic [15:0] b; + rand logic [3:0] c; + rand logic [11:0] d; + int e; - function new; - a = 0; - b = 0; - c = 0; - d = 0; - e = 0; - endfunction + function new; + a = 0; + b = 0; + c = 0; + d = 0; + e = 0; + endfunction endclass class DerivedCls1 extends BaseCls1; - rand Inner i; - rand int j; - int k; - rand Enum l; + rand Inner i; + rand int j; + int k; + rand Enum l; - function new; - i = new; - j = 0; - k = 0; - l = ONE; - endfunction + function new; + i = new; + j = 0; + k = 0; + l = ONE; + endfunction endclass class BaseCls2; - rand int i; + rand int i; - function new; - i = 0; - endfunction + function new; + i = 0; + endfunction endclass class DerivedCls2 extends BaseCls2; - rand int j; + rand int j; - function new; - super.new; - j = 0; - endfunction + function new; + super.new; + j = 0; + endfunction endclass class OtherCls; - logic[63:0] v; - rand logic[63:0] w; - rand logic[47:0] x; - rand logic[31:0] y; - rand logic[23:0] z; - rand StructUnpacked str; + logic [63:0] v; + rand logic [63:0] w; + rand logic [47:0] x; + rand logic [31:0] y; + rand logic [23:0] z; + rand StructUnpacked str; - function new; - v = 0; - w = 0; - x = 0; - y = 0; - z = 0; - str.i = 0; - str.j = '{x: 1'b0, y: ONE, z: 64'd0, s: '{a: 32'd0, b: 1'b0, c: ONE}}; - str.k = ONE; - endfunction + function new; + v = 0; + w = 0; + x = 0; + y = 0; + z = 0; + str.i = 0; + str.j = '{x: 1'b0, y: ONE, z: 64'd0, s: '{a: 32'd0, b: 1'b0, c: ONE}}; + str.k = ONE; + endfunction endclass class ContainsNull; - rand BaseCls1 b; + rand BaseCls1 b; endclass class ClsWithInt; - rand int a; - int b; + rand int a; + int b; endclass class DeriveClsWithInt extends ClsWithInt; endclass class DeriveAndContainClsWithInt extends ClsWithInt; - rand ClsWithInt cls1; - ClsWithInt cls2; - function new; - cls1 = new; - cls2 = new; - endfunction + rand ClsWithInt cls1; + ClsWithInt cls2; + function new; + cls1 = new; + cls2 = new; + endfunction endclass class ClsUsedOnlyHere; - rand int a; + rand int a; endclass typedef ClsUsedOnlyHere cls_used_only_here_t; class ClsContainUsedOnlyHere; - rand cls_used_only_here_t c; - function new; - c = new; - endfunction + rand cls_used_only_here_t c; + function new; + c = new; + endfunction endclass module t; - DerivedCls1 derived1; - DerivedCls2 derived2; - OtherCls other; - BaseCls1 base; - ContainsNull cont; - DeriveClsWithInt der_int; - DeriveAndContainClsWithInt der_contain; - ClsContainUsedOnlyHere cls_cont_used; + DerivedCls1 derived1; + DerivedCls2 derived2; + OtherCls other; + BaseCls1 base; + ContainsNull cont; + DeriveClsWithInt der_int; + DeriveAndContainClsWithInt der_contain; + ClsContainUsedOnlyHere cls_cont_used; - initial begin - derived1 = new; - derived2 = new; - other = new; - cont = new; - der_int = new; - der_contain = new; - base = derived1; - cls_cont_used = new; - for (int i = 0; i < 10; i++) begin - void'(base.randomize()); - void'(derived2.randomize()); - void'(other.randomize()); - void'(cont.randomize()); - void'(der_int.randomize()); - void'(der_contain.randomize()); - if (!(derived1.l inside {ONE, TWO, THREE, FOUR})) $stop; - if (!(other.str.j.s.c inside {ONE, TWO, THREE, FOUR})) $stop; - if (!(other.str.j.y inside {ONE, TWO, THREE, FOUR})) $stop; - if (!(other.str.k inside {ONE, TWO, THREE, FOUR})) $stop; - if (derived1.i.e != 0) $stop; - if (derived1.k != 0) $stop; - if (other.v != 0) $stop; - if (cont.b != null) $stop; - if (der_int.b != 0) $stop; - if (der_contain.cls2.a != 0) $stop; - if (der_contain.cls1.b != 0) $stop; - if (der_contain.b != 0) $stop; - end - `check_rand(derived1, derived1.i.a); - `check_rand(derived1, derived1.i.b); - `check_rand(derived1, derived1.i.c); - `check_rand(derived1, derived1.j); - `check_rand(derived1, derived1.l); - `check_rand(derived2, derived2.i); - `check_rand(derived2, derived2.j); - `check_rand(other, other.w); - `check_rand(other, other.x); - `check_rand(other, other.y); - `check_rand(other, other.z); - `check_rand(other, other.str.i); - `check_rand(other, other.str.j.x); - `check_rand(other, other.str.j.y); - `check_rand(other, other.str.j.z); - `check_rand(other, other.str.j.s.a); - `check_rand(other, other.str.j.s.b); - `check_rand(other, other.str.j.s.c); - `check_rand(other, other.str.k); - `check_rand(der_int, der_int.a); - `check_rand(der_contain, der_contain.cls1.a); - `check_rand(der_contain, der_contain.a); - `check_rand(cls_cont_used, cls_cont_used.c.a); + initial begin + derived1 = new; + derived2 = new; + other = new; + cont = new; + der_int = new; + der_contain = new; + base = derived1; + cls_cont_used = new; + for (int i = 0; i < 10; i++) begin + void'(base.randomize()); + void'(derived2.randomize()); + void'(other.randomize()); + void'(cont.randomize()); + void'(der_int.randomize()); + void'(der_contain.randomize()); + if (!(derived1.l inside {ONE, TWO, THREE, FOUR})) $stop; + if (!(other.str.j.s.c inside {ONE, TWO, THREE, FOUR})) $stop; + if (!(other.str.j.y inside {ONE, TWO, THREE, FOUR})) $stop; + if (!(other.str.k inside {ONE, TWO, THREE, FOUR})) $stop; + if (derived1.i.e != 0) $stop; + if (derived1.k != 0) $stop; + if (other.v != 0) $stop; + if (cont.b != null) $stop; + if (der_int.b != 0) $stop; + if (der_contain.cls2.a != 0) $stop; + if (der_contain.cls1.b != 0) $stop; + if (der_contain.b != 0) $stop; + end + `check_rand(derived1, derived1.i.a); + `check_rand(derived1, derived1.i.b); + `check_rand(derived1, derived1.i.c); + `check_rand(derived1, derived1.j); + `check_rand(derived1, derived1.l); + `check_rand(derived2, derived2.i); + `check_rand(derived2, derived2.j); + `check_rand(other, other.w); + `check_rand(other, other.x); + `check_rand(other, other.y); + `check_rand(other, other.z); + `check_rand(other, other.str.i); + `check_rand(other, other.str.j.x); + `check_rand(other, other.str.j.y); + `check_rand(other, other.str.j.z); + `check_rand(other, other.str.j.s.a); + `check_rand(other, other.str.j.s.b); + `check_rand(other, other.str.j.s.c); + `check_rand(other, other.str.k); + `check_rand(der_int, der_int.a); + `check_rand(der_contain, der_contain.cls1.a); + `check_rand(der_contain, der_contain.a); + `check_rand(cls_cont_used, cls_cont_used.c.a); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_method_bad.out b/test_regress/t/t_randomize_method_bad.out index f54740a9b..35fbb87f3 100644 --- a/test_regress/t/t_randomize_method_bad.out +++ b/test_regress/t/t_randomize_method_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_randomize_method_bad.v:8:17: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) - 8 | function int randomize; - | ^~~~~~~~~ +%Error: t/t_randomize_method_bad.v:8:16: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) + 8 | function int randomize; + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_randomize_method_bad.v:14:18: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) - 14 | function void randomize(int x); - | ^~~~~~~~~ -%Error: t/t_randomize_method_bad.v:16:18: 'srandom' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) - 16 | function void srandom(int seed); - | ^~~~~~~ +%Error: t/t_randomize_method_bad.v:14:17: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) + 14 | function void randomize(int x); + | ^~~~~~~~~ +%Error: t/t_randomize_method_bad.v:16:17: 'srandom' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) + 16 | function void srandom(int seed); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_bad.v b/test_regress/t/t_randomize_method_bad.v index 45c3bb29e..9282a7324 100644 --- a/test_regress/t/t_randomize_method_bad.v +++ b/test_regress/t/t_randomize_method_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - function int randomize; - return 1; - endfunction + function int randomize; + return 1; + endfunction endclass class Cls2; - function void randomize(int x); - endfunction - function void srandom(int seed); - endfunction + function void randomize(int x); + endfunction + function void srandom(int seed); + endfunction endclass module t; diff --git a/test_regress/t/t_randomize_method_complex_bad.out b/test_regress/t/t_randomize_method_complex_bad.out index 01851ca9c..de46e0a97 100644 --- a/test_regress/t/t_randomize_method_complex_bad.out +++ b/test_regress/t/t_randomize_method_complex_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_randomize_method_complex_bad.v:17:9: 'randomize() with' on a non-class-instance 'int' - 17 | i.randomize() with { v < 5; }); - | ^~~~~~~~~ +%Error: t/t_randomize_method_complex_bad.v:18:7: 'randomize() with' on a non-class-instance 'int' + 18 | i.randomize() with { v < 5; }); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_randomize_method_complex_bad.v:17:28: Can't find definition of variable: 'v' - 17 | i.randomize() with { v < 5; }); - | ^ +%Error: t/t_randomize_method_complex_bad.v:18:26: Can't find definition of variable: 'v' + 18 | i.randomize() with { v < 5; }); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_complex_bad.v b/test_regress/t/t_randomize_method_complex_bad.v index 9af38bbd1..32105de45 100644 --- a/test_regress/t/t_randomize_method_complex_bad.v +++ b/test_regress/t/t_randomize_method_complex_bad.v @@ -5,14 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - Cls f; - rand int r; + Cls f; + rand int r; endclass module t; - Cls x = new; - int i; - initial $display( - x.f.randomize(), - x.f.randomize() with { r < 5; }, - i.randomize() with { v < 5; }); + Cls x = new; + int i; + // verilog_format: off + initial $display( + x.f.randomize(), + x.f.randomize() with { r < 5; }, + i.randomize() with { v < 5; }); endmodule diff --git a/test_regress/t/t_randomize_method_constraints.v b/test_regress/t/t_randomize_method_constraints.v index f61d009a1..594874d36 100644 --- a/test_regress/t/t_randomize_method_constraints.v +++ b/test_regress/t/t_randomize_method_constraints.v @@ -5,72 +5,72 @@ // SPDX-License-Identifier: CC0-1.0 typedef enum bit[15:0] { - ONE = 3, - TWO = 5, - THREE = 8, - FOUR = 13 + ONE = 3, + TWO = 5, + THREE = 8, + FOUR = 13 } Enum; class Cls; - constraint A { v inside {ONE, THREE}; } - constraint B { w == 5; x inside {1,2} || x inside {4,5}; } - constraint C { z < 3 * 7; z > 5 + 8; u > 0; } - constraint D { - |redor == 1'b1; - redor[31:1] == 31'b0; - } + constraint A { v inside {ONE, THREE}; } + constraint B { w == 5; x inside {1,2} || x inside {4,5}; } + constraint C { z < 3 * 7; z > 5 + 8; u > 0; } + constraint D { + |redor == 1'b1; + redor[31:1] == 31'b0; + } - rand logic[79:0] u; - rand Enum v; - rand logic[63:0] w; - rand logic[47:0] x; - rand logic[31:0] y; - rand logic[22:0] z; - rand logic[31:0] redor; + rand logic[79:0] u; + rand Enum v; + rand logic[63:0] w; + rand logic[47:0] x; + rand logic[31:0] y; + rand logic[22:0] z; + rand logic[31:0] redor; - function new; - u = 0; - v = ONE; - w = 0; - x = 0; - y = 0; - z = 0; - endfunction + function new; + u = 0; + v = ONE; + w = 0; + x = 0; + y = 0; + z = 0; + endfunction endclass module t; - Cls obj; + Cls obj; - initial begin - int rand_result; - longint prev_checksum; - $display("===================\nSatisfiable constraints:"); - for (int i = 0; i < 25; i++) begin - obj = new; - rand_result = obj.randomize(); - $display("obj.u == %0d", obj.u); - $display("obj.v == %0d", obj.v); - $display("obj.w == %0d", obj.w); - $display("obj.x == %0d", obj.x); - $display("obj.y == %0d", obj.y); - $display("obj.z == %0d", obj.z); - $display("obj.redor == %0d", obj.redor); - $display("rand_result == %0d", rand_result); - $display("-------------------"); - if (!(obj.v inside {ONE, THREE})) $stop; - if (obj.w != 5) $stop; - if (!(obj.x inside {1,2,4,5})) $stop; - if (obj.z <= 13 || obj.z >= 21) $stop; - if (obj.redor != 1) $stop; - end - //$display("===================\nUnsatisfiable constraints for obj.y:"); - //rand_result = obj.randomize() with { 256 < y && y < 256; }; - //$display("obj.y == %0d", obj.y); - //$display("rand_result == %0d", rand_result); - //if (rand_result != 0) $stop; - //rand_result = obj.randomize() with { 16 <= z && z <= 32; }; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int rand_result; + longint prev_checksum; + $display("===================\nSatisfiable constraints:"); + for (int i = 0; i < 25; i++) begin + obj = new; + rand_result = obj.randomize(); + $display("obj.u == %0d", obj.u); + $display("obj.v == %0d", obj.v); + $display("obj.w == %0d", obj.w); + $display("obj.x == %0d", obj.x); + $display("obj.y == %0d", obj.y); + $display("obj.z == %0d", obj.z); + $display("obj.redor == %0d", obj.redor); + $display("rand_result == %0d", rand_result); + $display("-------------------"); + if (!(obj.v inside {ONE, THREE})) $stop; + if (obj.w != 5) $stop; + if (!(obj.x inside {1,2,4,5})) $stop; + if (obj.z <= 13 || obj.z >= 21) $stop; + if (obj.redor != 1) $stop; + end + //$display("===================\nUnsatisfiable constraints for obj.y:"); + //rand_result = obj.randomize() with { 256 < y && y < 256; }; + //$display("obj.y == %0d", obj.y); + //$display("rand_result == %0d", rand_result); + //if (rand_result != 0) $stop; + //rand_result = obj.randomize() with { 16 <= z && z <= 32; }; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_method_nclass_bad.out b/test_regress/t/t_randomize_method_nclass_bad.out index f337aca10..5fa87507d 100644 --- a/test_regress/t/t_randomize_method_nclass_bad.out +++ b/test_regress/t/t_randomize_method_nclass_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_randomize_method_nclass_bad.v:10:7: Calling implicit class method 'srandom' without being under class - 10 | srandom(1); - | ^~~~~~~ +%Error: t/t_randomize_method_nclass_bad.v:10:5: Calling implicit class method 'srandom' without being under class + 10 | srandom(1); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_nclass_bad.v b/test_regress/t/t_randomize_method_nclass_bad.v index f7026f717..fc77aaf84 100644 --- a/test_regress/t/t_randomize_method_nclass_bad.v +++ b/test_regress/t/t_randomize_method_nclass_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - randomize(1); - srandom(1); - end + initial begin + randomize(1); + srandom(1); + end endmodule diff --git a/test_regress/t/t_randomize_method_std.v b/test_regress/t/t_randomize_method_std.v index 6c1d2cbe1..7eeb262e5 100644 --- a/test_regress/t/t_randomize_method_std.v +++ b/test_regress/t/t_randomize_method_std.v @@ -7,16 +7,16 @@ process p; // force importing std into top-level namespace class C; - function new; - if (randomize() != 1) $stop; - endfunction + function new; + if (randomize() != 1) $stop; + endfunction endclass module t; - initial begin - automatic C c = new; + initial begin + automatic C c = new; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_method_types_unsup.out b/test_regress/t/t_randomize_method_types_unsup.out index 2b19d4450..f9c72d91f 100644 --- a/test_regress/t/t_randomize_method_types_unsup.out +++ b/test_regress/t/t_randomize_method_types_unsup.out @@ -1,18 +1,18 @@ -%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:23:17: Unsupported: randomizing this expression, treating as state - 23 | dynarr[1].size < 10; - | ^~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:23:15: Unsupported: randomizing this expression, treating as state + 23 | dynarr[1].size < 10; + | ^~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:27:9: Size constraint combined with element constraint may not work correctly +%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:27:7: Size constraint combined with element constraint may not work correctly : ... note: In instance 't' - 27 | q.size < 5; - | ^~~~ -%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:13: Unsupported: random member variable with the type of the containing class + 27 | q.size < 5; + | ^~~~ +%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:12: Unsupported: random member variable with the type of the containing class : ... note: In instance 't' - 15 | rand Cls cls; - | ^~~ + 15 | rand Cls cls; + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:43:43: Unsupported: randomizing this expression, treating as state - 43 | res = obj.randomize() with { dynarr.size > 2; }; - | ^~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:43:41: Unsupported: randomizing this expression, treating as state + 43 | res = obj.randomize() with { dynarr.size > 2; }; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_types_unsup.v b/test_regress/t/t_randomize_method_types_unsup.v index cc1955a9e..5494bbeae 100644 --- a/test_regress/t/t_randomize_method_types_unsup.v +++ b/test_regress/t/t_randomize_method_types_unsup.v @@ -5,41 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - rand int x; + rand int x; endclass class Cls; - rand int assocarr[string]; - rand int dynarr[][]; - rand int q[$]; - rand Cls cls; - rand int i; - rand Foo foo; - rand int y; - int st; - constraint dynsize { - dynarr.size < 20; - dynarr.size > 0; - dynarr[1].size < 10; - } - constraint statedep { i < st + 2; } - constraint q_size_elem { - q.size < 5; - q[i] < 10; - } - constraint global_constraint { - foo.x < y; + rand int assocarr[string]; + rand int dynarr[][]; + rand int q[$]; + rand Cls cls; + rand int i; + rand Foo foo; + rand int y; + int st; + constraint dynsize { + dynarr.size < 20; + dynarr.size > 0; + dynarr[1].size < 10; + } + constraint statedep { i < st + 2; } + constraint q_size_elem { + q.size < 5; + q[i] < 10; + } + constraint global_constraint { + foo.x < y; } endclass module t; - Cls obj; - int res; + Cls obj; + int res; - initial begin - obj = new; - obj.foo = new; - res = obj.randomize(); - res = obj.randomize() with { dynarr.size > 2; }; - end + initial begin + obj = new; + obj.foo = new; + res = obj.randomize(); + res = obj.randomize() with { dynarr.size > 2; }; + end endmodule diff --git a/test_regress/t/t_randomize_method_with_scoping.v b/test_regress/t/t_randomize_method_with_scoping.v index 803a24281..aca12a4e7 100644 --- a/test_regress/t/t_randomize_method_with_scoping.v +++ b/test_regress/t/t_randomize_method_with_scoping.v @@ -5,111 +5,111 @@ // SPDX-License-Identifier: CC0-1.0 class c1; - rand int c1_f; + rand int c1_f; endclass class c2; - rand int c2_f; + rand int c2_f; endclass localparam int PARAM = 42; class Cls; - rand int x; - int q[$] = {0}; - rand enum { - ONE_Y, - TWO_Y - } y; - virtual function int get_x(); - return x; - endfunction + rand int x; + int q[$] = {0}; + rand enum { + ONE_Y, + TWO_Y + } y; + virtual function int get_x(); + return x; + endfunction endclass class SubA extends Cls; - c1 e = new; - rand enum { - AMBIG, - ONE_A, - TWO_A - } en; - function c1 get_c(); - return e; - endfunction - function int op(int v); - return v + 1; - endfunction + c1 e = new; + rand enum { + AMBIG, + ONE_A, + TWO_A + } en; + function c1 get_c(); + return e; + endfunction + function int op(int v); + return v + 1; + endfunction endclass class SubB extends Cls; - int z; + int z; endclass class SubC extends SubB; - c2 e = new; - rand enum { - AMBIG, - ONE_B, - TWO_B - } en; - SubA f = new; - function c2 get_c(); - return e; - endfunction - function int op(int v); - return v - 1; - endfunction - function int doit; - // access ambiguous names so width complains if we miss something - doit = 1; + c2 e = new; + rand enum { + AMBIG, + ONE_B, + TWO_B + } en; + SubA f = new; + function c2 get_c(); + return e; + endfunction + function int op(int v); + return v - 1; + endfunction + function int doit; + // access ambiguous names so width complains if we miss something + doit = 1; - f.x = 4; - x = 5; - doit = f.randomize() with { x == local::x; }; - if (f.x != x) $stop; + f.x = 4; + x = 5; + doit = f.randomize() with { x == local::x; }; + if (f.x != x) $stop; - z = 6; - doit &= f.randomize() with { x == z; }; - if (f.x != z) $stop; + z = 6; + doit &= f.randomize() with { x == z; }; + if (f.x != z) $stop; - doit &= f.randomize() with { e.c1_f == local::e.c2_f; }; - doit &= f.randomize() with { get_x() == local::get_x(); }; - doit &= f.randomize() with { get_c().c1_f == local::get_c().c2_f; }; - doit &= f.randomize() with { (get_c).c1_f == (local::get_c).c2_f; }; + doit &= f.randomize() with { e.c1_f == local::e.c2_f; }; + doit &= f.randomize() with { get_x() == local::get_x(); }; + doit &= f.randomize() with { get_c().c1_f == local::get_c().c2_f; }; + doit &= f.randomize() with { (get_c).c1_f == (local::get_c).c2_f; }; - f.y = ONE_Y; - y = TWO_Y; - doit &= f.randomize() with { y == local::y; }; - if (f.y != y) $stop; + f.y = ONE_Y; + y = TWO_Y; + doit &= f.randomize() with { y == local::y; }; + if (f.y != y) $stop; - f.en = SubA::ONE_A; - doit &= f.randomize() with { en == AMBIG; }; - if (doit != 1) $stop; - if (f.en != SubA::AMBIG) $stop; + f.en = SubA::ONE_A; + doit &= f.randomize() with { en == AMBIG; }; + if (doit != 1) $stop; + if (f.en != SubA::AMBIG) $stop; - doit &= f.randomize() with { x == PARAM; }; - if (doit != 1) $stop; - if (f.x != PARAM) $stop; + doit &= f.randomize() with { x == PARAM; }; + if (doit != 1) $stop; + if (f.x != PARAM) $stop; - f.en = SubA::ONE_A; - doit &= f.randomize() with { en == ONE_A; }; - doit &= f.randomize() with { local::en == local::AMBIG; }; - en = ONE_B; - doit &= f.randomize() with { local::en == ONE_B; }; + f.en = SubA::ONE_A; + doit &= f.randomize() with { en == ONE_A; }; + doit &= f.randomize() with { local::en == local::AMBIG; }; + en = ONE_B; + doit &= f.randomize() with { local::en == ONE_B; }; - doit &= f.randomize() with { x == local::op(op(0)); }; - if (f.x != 0) $stop; - doit &= f.randomize() with { x == op(local::op(1)); }; - if (f.x != 1) $stop; - doit &= f.randomize() with { x == local::op(op(local::op(op(0)))); }; - if (f.x != 0) $stop; - doit &= f.randomize() with { x == op(local::op(op(local::op(1)))); }; - if (f.x != 1) $stop; - doit &= f.randomize() with { foreach (q[i]) x == i; }; - if (f.x != 0) $stop; - endfunction + doit &= f.randomize() with { x == local::op(op(0)); }; + if (f.x != 0) $stop; + doit &= f.randomize() with { x == op(local::op(1)); }; + if (f.x != 1) $stop; + doit &= f.randomize() with { x == local::op(op(local::op(op(0)))); }; + if (f.x != 0) $stop; + doit &= f.randomize() with { x == op(local::op(op(local::op(1)))); }; + if (f.x != 1) $stop; + doit &= f.randomize() with { foreach (q[i]) x == i; }; + if (f.x != 0) $stop; + endfunction endclass module t; - SubC obj = new; + SubC obj = new; - initial begin - if (obj.doit != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (obj.doit != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_param_with.v b/test_regress/t/t_randomize_param_with.v index 89dcede46..e47dc870c 100644 --- a/test_regress/t/t_randomize_param_with.v +++ b/test_regress/t/t_randomize_param_with.v @@ -6,43 +6,43 @@ `define check_rand(cl, field, constr, cond) \ begin \ - automatic longint prev_result; \ - automatic int ok; \ - if (!bit'(cl.randomize() with { constr; })) $stop; \ - prev_result = longint'(field); \ - if (!(cond)) $stop; \ - repeat(9) begin \ - longint result; \ - if (!bit'(cl.randomize() with { constr; })) $stop; \ - result = longint'(field); \ - if (!(cond)) $stop; \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize() with { constr; })) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize() with { constr; })) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end class Cls #(int LIMIT = 3); - rand int x; - int y = -100; - constraint x_limit { x <= LIMIT; }; + rand int x; + int y = -100; + constraint x_limit { x <= LIMIT; }; endclass module t; - initial begin - automatic Cls#() cd = new; - automatic Cls#(5) c5 = new; + initial begin + automatic Cls#() cd = new; + automatic Cls#(5) c5 = new; - `check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3); - `check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3); - if (cd.randomize() with {x > 3;} == 1) $stop; + `check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3); + `check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3); + if (cd.randomize() with {x > 3;} == 1) $stop; - `check_rand(c5, c5.x, x > 0, c5.x > 0 && c5.x <= 5); - `check_rand(c5, c5.x, x > y, c5.x > -100 && c5.x <= 5); - if (c5.randomize() with {x >= 5;} == 0) $stop; - if (c5.x != 5) $stop; + `check_rand(c5, c5.x, x > 0, c5.x > 0 && c5.x <= 5); + `check_rand(c5, c5.x, x > y, c5.x > -100 && c5.x <= 5); + if (c5.randomize() with {x >= 5;} == 0) $stop; + if (c5.x != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_prepost.v b/test_regress/t/t_randomize_prepost.v index e0540f34c..f4427fedd 100644 --- a/test_regress/t/t_randomize_prepost.v +++ b/test_regress/t/t_randomize_prepost.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on typedef enum int { RANDOMIZED = 20 diff --git a/test_regress/t/t_randomize_queue_size.v b/test_regress/t/t_randomize_queue_size.v index 2fbc550a6..9ea76c5c8 100644 --- a/test_regress/t/t_randomize_queue_size.v +++ b/test_regress/t/t_randomize_queue_size.v @@ -6,80 +6,80 @@ `define check_rand(cl, field, cond) \ begin \ - automatic longint prev_result; \ - automatic int ok; \ - if (!bit'(cl.randomize())) $stop; \ - prev_result = longint'(field); \ - if (!(cond)) $stop; \ - repeat(9) begin \ - longint result; \ - if (!bit'(cl.randomize())) $stop; \ - result = longint'(field); \ - if (!(cond)) $stop; \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end class Foo; - rand int q[$]; - rand int q2[$][$]; - int x = 1; - constraint c { - q.size() == 15; - q2.size() == 10; - } + rand int q[$]; + rand int q2[$][$]; + int x = 1; + constraint c { + q.size() == 15; + q2.size() == 10; + } endclass class Bar; - rand int q[$]; - rand int min_size; - rand int q2[$]; - constraint c { - min_size > 2; - q.size() >= min_size; - q.size() < 10; - }; - constraint c2 { - q2.size() < 7; - } + rand int q[$]; + rand int min_size; + rand int q2[$]; + constraint c { + min_size > 2; + q.size() >= min_size; + q.size() < 10; + }; + constraint c2 { + q2.size() < 7; + } endclass class Baz; - rand Foo foo_arr[]; - constraint c_foo { - foo_arr.size == 7; - } + rand Foo foo_arr[]; + constraint c_foo { + foo_arr.size == 7; + } endclass module t; - initial begin - automatic Foo foo = new; - automatic Bar bar = new; - automatic Baz baz = new; + initial begin + automatic Foo foo = new; + automatic Bar bar = new; + automatic Baz baz = new; - void'(foo.randomize()); - if (foo.q.size() != 15) $stop; - if (foo.q2.size() != 10) $stop; + void'(foo.randomize()); + if (foo.q.size() != 15) $stop; + if (foo.q2.size() != 10) $stop; - `check_rand(bar, bar.q.size(), bar.q.size() > 2 && bar.q.size() < 10); - `check_rand(bar, bar.q2.size(), bar.q2.size() < 7); + `check_rand(bar, bar.q.size(), bar.q.size() > 2 && bar.q.size() < 10); + `check_rand(bar, bar.q2.size(), bar.q2.size() < 7); - baz.foo_arr = new[4]; - for (int i = 0; i < 4; i++) baz.foo_arr[i] = new; - baz.foo_arr[2].x = 2; - void'(baz.randomize()); + baz.foo_arr = new[4]; + for (int i = 0; i < 4; i++) baz.foo_arr[i] = new; + baz.foo_arr[2].x = 2; + void'(baz.randomize()); - if (baz.foo_arr.size() != 7) $stop; - for (int i = 0; i < 4; i++) - if (baz.foo_arr[i] == null) $stop; - for (int i = 4; i < 7; i++) - if (baz.foo_arr[i] != null) $stop; - if (baz.foo_arr[2].x != 2) $stop; - `check_rand(baz, baz.foo_arr[1].q[5], 1'b1); + if (baz.foo_arr.size() != 7) $stop; + for (int i = 0; i < 4; i++) + if (baz.foo_arr[i] == null) $stop; + for (int i = 4; i < 7; i++) + if (baz.foo_arr[i] != null) $stop; + if (baz.foo_arr[2].x != 2) $stop; + `check_rand(baz, baz.foo_arr[1].q[5], 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_rand_mode.v b/test_regress/t/t_randomize_rand_mode.v index afc3192b9..8214427a9 100644 --- a/test_regress/t/t_randomize_rand_mode.v +++ b/test_regress/t/t_randomize_rand_mode.v @@ -4,118 +4,120 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Base; - rand int m_one; + rand int m_one; - task test1; - m_one.rand_mode(0); - `checkh(m_one.rand_mode(), 0); - verify(0); + task test1; + m_one.rand_mode(0); + `checkh(m_one.rand_mode(), 0); + verify(0); - m_one.rand_mode(1); - `checkh(m_one.rand_mode(), 1); - verify(1); - endtask + m_one.rand_mode(1); + `checkh(m_one.rand_mode(), 1); + verify(1); + endtask - task verify(int mode_one); - bit one_ne10 = '0; - int v; - if (m_one.rand_mode() != mode_one) $stop; - for (int i = 0; i < 20; ++i) begin - m_one = 10; - v = randomize(); - if (m_one != 10) one_ne10 = 1'b1; + task verify(int mode_one); + bit one_ne10 = '0; + int v; + if (m_one.rand_mode() != mode_one) $stop; + for (int i = 0; i < 20; ++i) begin + m_one = 10; + v = randomize(); + if (m_one != 10) one_ne10 = 1'b1; `ifdef TEST_VERBOSE - $display("one=%0d(rand_mode=%0d)", m_one, mode_one); + $display("one=%0d(rand_mode=%0d)", m_one, mode_one); `endif - end - if (mode_one != 0 && !one_ne10) $stop; - if (mode_one == 0 && one_ne10) $stop; - endtask + end + if (mode_one != 0 && !one_ne10) $stop; + if (mode_one == 0 && one_ne10) $stop; + endtask endclass class Packet extends Base; - rand int m_two; + rand int m_two; - task test2; - rand_mode(0); - `checkh(m_one.rand_mode(), 0); - `checkh(m_two.rand_mode(), 0); - verify(0, 0); + task test2; + rand_mode(0); + `checkh(m_one.rand_mode(), 0); + `checkh(m_two.rand_mode(), 0); + verify(0, 0); - m_one.rand_mode(0); - `checkh(m_one.rand_mode(), 0); - m_two.rand_mode(1); - `checkh(m_two.rand_mode(), 1); - verify(0, 1); - endtask + m_one.rand_mode(0); + `checkh(m_one.rand_mode(), 0); + m_two.rand_mode(1); + `checkh(m_two.rand_mode(), 1); + verify(0, 1); + endtask - task verify(int mode_one, int mode_two); - bit one_ne10 = '0; - bit two_ne10 = '0; - int v; - if (m_one.rand_mode() != mode_one) $stop; - if (m_two.rand_mode() != mode_two) $stop; - for (int i = 0; i < 20; ++i) begin - m_one = 10; - m_two = 10; - v = randomize(); - if (m_one != 10) one_ne10 = 1'b1; - if (m_two != 10) two_ne10 = 1'b1; + task verify(int mode_one, int mode_two); + bit one_ne10 = '0; + bit two_ne10 = '0; + int v; + if (m_one.rand_mode() != mode_one) $stop; + if (m_two.rand_mode() != mode_two) $stop; + for (int i = 0; i < 20; ++i) begin + m_one = 10; + m_two = 10; + v = randomize(); + if (m_one != 10) one_ne10 = 1'b1; + if (m_two != 10) two_ne10 = 1'b1; `ifdef TEST_VERBOSE - $display("one=%0d(rand_mode=%0d) two=%0d(rand_mode=%0d)", - m_one, mode_one, m_two, mode_two); + $display("one=%0d(rand_mode=%0d) two=%0d(rand_mode=%0d)", + m_one, mode_one, m_two, mode_two); `endif - end - if (mode_one != 0 && !one_ne10) $stop; - if (mode_two != 0 && !two_ne10) $stop; - if (mode_one == 0 && one_ne10) $stop; - if (mode_two == 0 && two_ne10) $stop; - endtask + end + if (mode_one != 0 && !one_ne10) $stop; + if (mode_two != 0 && !two_ne10) $stop; + if (mode_one == 0 && one_ne10) $stop; + if (mode_two == 0 && two_ne10) $stop; + endtask endclass module t; - Packet p; + Packet p; - int v; + int v; - initial begin - p = new; + initial begin + p = new; - p.test1(); - p.test2(); + p.test1(); + p.test2(); - // IEEE: function void object[.random_variable].rand_mode(bit on_off); - // IEEE: function int object.random_variable.rand_mode(); - // Not legal to get current rand() value on a class-only call + // IEEE: function void object[.random_variable].rand_mode(bit on_off); + // IEEE: function int object.random_variable.rand_mode(); + // Not legal to get current rand() value on a class-only call - // We call rand_mode here too becuase the parsing is different from that - // called from the class itself - p.m_one.rand_mode(0); - `checkh(p.m_one.rand_mode(), 0); - p.m_two.rand_mode(0); - `checkh(p.m_two.rand_mode(), 0); - p.verify(0, 0); + // We call rand_mode here too becuase the parsing is different from that + // called from the class itself + p.m_one.rand_mode(0); + `checkh(p.m_one.rand_mode(), 0); + p.m_two.rand_mode(0); + `checkh(p.m_two.rand_mode(), 0); + p.verify(0, 0); - p.m_one.rand_mode(0); - `checkh(p.m_one.rand_mode(), 0); - p.m_two.rand_mode(1); - `checkh(p.m_two.rand_mode(), 1); - p.verify(0, 1); + p.m_one.rand_mode(0); + `checkh(p.m_one.rand_mode(), 0); + p.m_two.rand_mode(1); + `checkh(p.m_two.rand_mode(), 1); + p.verify(0, 1); - p.rand_mode(1); - p.verify(1, 1); + p.rand_mode(1); + p.verify(1, 1); - p.rand_mode(0); - p.verify(0, 0); + p.rand_mode(0); + p.verify(0, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_rand_mode_bad.out b/test_regress/t/t_randomize_rand_mode_bad.out index 41521e4a5..2492f6eae 100644 --- a/test_regress/t/t_randomize_rand_mode_bad.out +++ b/test_regress/t/t_randomize_rand_mode_bad.out @@ -1,28 +1,28 @@ -%Error: t/t_randomize_rand_mode_bad.v:22:15: Cannot call 'rand_mode()' on non-random, non-class variable +%Error: t/t_randomize_rand_mode_bad.v:22:13: Cannot call 'rand_mode()' on non-random, non-class variable : ... note: In instance 't' - 22 | p.m_val.rand_mode(0); - | ^~~~~~~~~ + 22 | p.m_val.rand_mode(0); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_randomize_rand_mode_bad.v:23:19: Cannot call 'rand_mode()' on packed array element +%Error: t/t_randomize_rand_mode_bad.v:23:17: Cannot call 'rand_mode()' on packed array element : ... note: In instance 't' - 23 | p.m_pack[0].rand_mode(0); - | ^~~~~~~~~ -%Error: t/t_randomize_rand_mode_bad.v:24:39: Cannot call 'rand_mode()' as a function on non-random variable + 23 | p.m_pack[0].rand_mode(0); + | ^~~~~~~~~ +%Error: t/t_randomize_rand_mode_bad.v:24:37: Cannot call 'rand_mode()' as a function on non-random variable : ... note: In instance 't' - 24 | $display("p.rand_mode()=%0d", p.rand_mode()); - | ^~~~~~~~~ -%Error: t/t_randomize_rand_mode_bad.v:25:18: 'rand_mode()' with arguments cannot be called as a function + 24 | $display("p.rand_mode()=%0d", p.rand_mode()); + | ^~~~~~~~~ +%Error: t/t_randomize_rand_mode_bad.v:25:16: 'rand_mode()' with arguments cannot be called as a function : ... note: In instance 't' - 25 | $display(p.rand_mode(0)); - | ^~~~~~~~~ -%Warning-IGNOREDRETURN: t/t_randomize_rand_mode_bad.v:26:21: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 25 | $display(p.rand_mode(0)); + | ^~~~~~~~~ +%Warning-IGNOREDRETURN: t/t_randomize_rand_mode_bad.v:26:19: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) : ... note: In instance 't' - 26 | p.m_other_val.rand_mode(); - | ^~~~~~~~~ + 26 | p.m_other_val.rand_mode(); + | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. -%Error: t/t_randomize_rand_mode_bad.v:13:14: Cannot call 'rand_mode()' as a function on non-random variable +%Error: t/t_randomize_rand_mode_bad.v:13:12: Cannot call 'rand_mode()' as a function on non-random variable : ... note: In instance 't' - 13 | return rand_mode(); - | ^~~~~~~~~ + 13 | return rand_mode(); + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_rand_mode_bad.v b/test_regress/t/t_randomize_rand_mode_bad.v index 0d3ba5236..b35b4661e 100644 --- a/test_regress/t/t_randomize_rand_mode_bad.v +++ b/test_regress/t/t_randomize_rand_mode_bad.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - int m_val; - rand int m_other_val; - rand logic [7:0] m_pack; + int m_val; + rand int m_other_val; + rand logic [7:0] m_pack; - function int get_rand_mode; - return rand_mode(); - endfunction + function int get_rand_mode; + return rand_mode(); + endfunction endclass module t; - Packet p; + Packet p; - initial begin - p = new; - p.m_val.rand_mode(0); - p.m_pack[0].rand_mode(0); - $display("p.rand_mode()=%0d", p.rand_mode()); - $display(p.rand_mode(0)); - p.m_other_val.rand_mode(); - end + initial begin + p = new; + p.m_val.rand_mode(0); + p.m_pack[0].rand_mode(0); + $display("p.rand_mode()=%0d", p.rand_mode()); + $display(p.rand_mode(0)); + p.m_other_val.rand_mode(); + end endmodule diff --git a/test_regress/t/t_randomize_rand_mode_unsup.out b/test_regress/t/t_randomize_rand_mode_unsup.out index 7c5186142..e894388b8 100644 --- a/test_regress/t/t_randomize_rand_mode_unsup.out +++ b/test_regress/t/t_randomize_rand_mode_unsup.out @@ -1,26 +1,26 @@ -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:17:22: Unsupported: 'rand_mode()' on dynamic array element +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:17:20: Unsupported: 'rand_mode()' on dynamic array element : ... note: In instance 't' - 17 | p.m_dyn_arr[0].rand_mode(0); - | ^~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:18:22: Unsupported: 'rand_mode()' on unpacked array element - : ... note: In instance 't' - 18 | p.m_unp_arr[0].rand_mode(0); - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:19:20: Unsupported: 'rand_mode()' on unpacked struct element - : ... note: In instance 't' - 19 | p.m_struct.y.rand_mode(0); + 17 | p.m_dyn_arr[0].rand_mode(0); | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:20:18: Unsupported: 'rand_mode()' on static variable + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:18:20: Unsupported: 'rand_mode()' on unpacked array element : ... note: In instance 't' - 20 | p.m_static.rand_mode(0); + 18 | p.m_unp_arr[0].rand_mode(0); + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:19:18: Unsupported: 'rand_mode()' on unpacked struct element + : ... note: In instance 't' + 19 | p.m_struct.y.rand_mode(0); | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:21:57: Unsupported: 'rand_mode()' on static variable +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:20:16: Unsupported: 'rand_mode()' on static variable : ... note: In instance 't' - 21 | $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:22:9: Unsupported: 'rand_mode()' on static variable: 'm_static' + 20 | p.m_static.rand_mode(0); + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:21:55: Unsupported: 'rand_mode()' on static variable + : ... note: In instance 't' + 21 | $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:22:7: Unsupported: 'rand_mode()' on static variable: 'm_static' : ... note: In instance 't' - 22 | p.rand_mode(0); - | ^~~~~~~~~ + 22 | p.rand_mode(0); + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_rand_mode_unsup.v b/test_regress/t/t_randomize_rand_mode_unsup.v index 98fcdd99a..0e66b1c98 100644 --- a/test_regress/t/t_randomize_rand_mode_unsup.v +++ b/test_regress/t/t_randomize_rand_mode_unsup.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int m_dyn_arr[]; - rand int m_unp_arr[10]; - rand struct { int y; } m_struct; - static rand int m_static; + rand int m_dyn_arr[]; + rand int m_unp_arr[10]; + rand struct {int y;} m_struct; + static rand int m_static; endclass module t; - initial begin - automatic Packet p = new; - p.m_dyn_arr[0].rand_mode(0); - p.m_unp_arr[0].rand_mode(0); - p.m_struct.y.rand_mode(0); - p.m_static.rand_mode(0); - $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); - p.rand_mode(0); - end + initial begin + automatic Packet p = new; + p.m_dyn_arr[0].rand_mode(0); + p.m_unp_arr[0].rand_mode(0); + p.m_struct.y.rand_mode(0); + p.m_static.rand_mode(0); + $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); + p.rand_mode(0); + end endmodule diff --git a/test_regress/t/t_randomize_srandom.v b/test_regress/t/t_randomize_srandom.v index 172f7df38..f1a06d9ec 100644 --- a/test_regress/t/t_randomize_srandom.v +++ b/test_regress/t/t_randomize_srandom.v @@ -4,151 +4,153 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkeq(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkne(gotv,expv) do if ((gotv) === (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on class Cls; - bit [63:0] m_sum; - rand int m_r; - function void hash_init(); - m_sum = 64'h5aef0c8d_d70a4497; - endfunction - function void hash(int res); - $display(" res %x", res); - m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; - endfunction + bit [63:0] m_sum; + rand int m_r; + function void hash_init(); + m_sum = 64'h5aef0c8d_d70a4497; + endfunction + function void hash(int res); + $display(" res %x", res); + m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; + endfunction - function bit [63:0] test1(); - Cls o; - // Affected by srandom - $display(" init for randomize"); - hash_init; - // TODO: Support this.randomize() - o = this; - void'(o.randomize()); - hash(m_r); - void'(o.randomize()); - hash(m_r); - return m_sum; - endfunction + function bit [63:0] test1(); + Cls o; + // Affected by srandom + $display(" init for randomize"); + hash_init; + // TODO: Support this.randomize() + o = this; + void'(o.randomize()); + hash(m_r); + void'(o.randomize()); + hash(m_r); + return m_sum; + endfunction - function bit [63:0] test2(int seed); - $display(" init for seeded randomize"); - hash_init; - this.srandom(seed); - void'(this.randomize()); - hash(m_r); - return m_sum; - endfunction + function bit [63:0] test2(int seed); + $display(" init for seeded randomize"); + hash_init; + this.srandom(seed); + void'(this.randomize()); + hash(m_r); + return m_sum; + endfunction - function bit [63:0] test3(int seed); - $display(" init for seeded randomize"); - hash_init; - srandom(seed); - void'(randomize()); - hash(m_r); - return m_sum; - endfunction + function bit [63:0] test3(int seed); + $display(" init for seeded randomize"); + hash_init; + srandom(seed); + void'(randomize()); + hash(m_r); + return m_sum; + endfunction endclass class Foo; endclass class Bar extends Foo; - bit [63:0] m_sum; - rand int m_r; - function void hash_init(); - m_sum = 64'h5aef0c8d_d70a4497; - endfunction - function void hash(int res); - $display(" res %x", res); - m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; - endfunction + bit [63:0] m_sum; + rand int m_r; + function void hash_init(); + m_sum = 64'h5aef0c8d_d70a4497; + endfunction + function void hash(int res); + $display(" res %x", res); + m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; + endfunction - function void this_srandom(int seed); - this.srandom(seed); - endfunction + function void this_srandom(int seed); + this.srandom(seed); + endfunction - function bit [63:0] test2; - $display(" init for seeded randomize"); - hash_init; - $display("%d", m_r); - hash(m_r); - return m_sum; - endfunction + function bit [63:0] test2; + $display(" init for seeded randomize"); + hash_init; + $display("%d", m_r); + hash(m_r); + return m_sum; + endfunction endclass module t; - Cls ca; - Cls cb; - Bar b1; - Bar b2; + Cls ca; + Cls cb; + Bar b1; + Bar b2; - bit [63:0] sa; - bit [63:0] sb; + bit [63:0] sa; + bit [63:0] sb; - initial begin - // Each class gets different seed from same thread, - // so the randomization should be different - $display("New"); - ca = new; - cb = new; - b1 = new; - b2 = new; + initial begin + // Each class gets different seed from same thread, + // so the randomization should be different + $display("New"); + ca = new; + cb = new; + b1 = new; + b2 = new; - sa = ca.test1(); - sb = cb.test1(); - `checkne(sa, sb); // Could false-fail 2^-32 + sa = ca.test1(); + sb = cb.test1(); + `checkne(sa, sb); // Could false-fail 2^-32 - // Seed the classes to be synced - $display("Seed"); - ca.srandom(123); - cb.srandom(123); + // Seed the classes to be synced + $display("Seed"); + ca.srandom(123); + cb.srandom(123); - sa = ca.test1(); - sb = cb.test1(); - `checkeq(sa, sb); + sa = ca.test1(); + sb = cb.test1(); + `checkeq(sa, sb); - // Check using this - $display("this.srandom"); - sa = ca.test2(1); - sb = cb.test2(2); - `checkne(sa, sb); + // Check using this + $display("this.srandom"); + sa = ca.test2(1); + sb = cb.test2(2); + `checkne(sa, sb); - sa = ca.test2(3); - sb = cb.test2(3); - `checkeq(sa, sb); + sa = ca.test2(3); + sb = cb.test2(3); + `checkeq(sa, sb); - $display("this.srandom - Bar class"); - b1.this_srandom(1); - b2.this_srandom(2); - void'(b1.randomize()); - void'(b2.randomize()); - sa = b1.test2; - sb = b2.test2; - `checkne(sa, sb); + $display("this.srandom - Bar class"); + b1.this_srandom(1); + b2.this_srandom(2); + void'(b1.randomize()); + void'(b2.randomize()); + sa = b1.test2; + sb = b2.test2; + `checkne(sa, sb); - b1.this_srandom(3); - b2.this_srandom(3); - void'(b1.randomize()); - void'(b2.randomize()); - sa = b1.test2; - sb = b2.test2; - `checkeq(sa, sb); + b1.this_srandom(3); + b2.this_srandom(3); + void'(b1.randomize()); + void'(b2.randomize()); + sa = b1.test2; + sb = b2.test2; + `checkeq(sa, sb); - // Check using direct call - $display("srandom"); - sa = ca.test3(1); - sb = cb.test3(2); - `checkne(sa, sb); + // Check using direct call + $display("srandom"); + sa = ca.test3(1); + sb = cb.test3(2); + `checkne(sa, sb); - sa = ca.test3(3); - sb = cb.test3(3); - `checkeq(sa, sb); + sa = ca.test3(3); + sb = cb.test3(3); + `checkeq(sa, sb); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_this.v b/test_regress/t/t_randomize_this.v index 6120581d6..ced05d0b5 100644 --- a/test_regress/t/t_randomize_this.v +++ b/test_regress/t/t_randomize_this.v @@ -5,43 +5,43 @@ // SPDX-License-Identifier: CC0-1.0 class Member; - rand int m_val; + rand int m_val; endclass class Cls; - rand int m_val; - rand Member m_member; + rand int m_val; + rand Member m_member; - function void test; - automatic int rand_result; - logic ok1 = 0, ok2 = 0; + function void test; + automatic int rand_result; + logic ok1 = 0, ok2 = 0; - m_val = 256; - m_member.m_val = 65535; - for (int i = 0; i < 20; i++) begin - rand_result = randomize(); - if (rand_result != 1) $stop; - if (m_val != 256) ok1 = 1; - if (m_member.m_val != 65535) ok2 = 1; - end - if (!ok1) $stop; - if (!ok2) $stop; - endfunction + m_val = 256; + m_member.m_val = 65535; + for (int i = 0; i < 20; i++) begin + rand_result = randomize(); + if (rand_result != 1) $stop; + if (m_val != 256) ok1 = 1; + if (m_member.m_val != 65535) ok2 = 1; + end + if (!ok1) $stop; + if (!ok2) $stop; + endfunction - function new; - m_member = new; - endfunction + function new; + m_member = new; + endfunction endclass module t; - initial begin - Cls c; - c = new; + initial begin + Cls c; + c = new; - c.test; + c.test; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_union.v b/test_regress/t/t_randomize_union.v index 4fbdcdf80..3952f4676 100644 --- a/test_regress/t/t_randomize_union.v +++ b/test_regress/t/t_randomize_union.v @@ -5,164 +5,175 @@ // SPDX-License-Identifier: CC0-1.0 typedef union packed { - int int_value; - bit [31:0] bits; + int int_value; + bit [31:0] bits; } SimpleUnion; typedef struct packed { - rand bit [3:0] field_a; - rand bit [7:0] field_b; + rand bit [3:0] field_a; + rand bit [7:0] field_b; } PackedStruct; typedef union packed { - PackedStruct struct_fields; - bit [11:0] inner_bits; + PackedStruct struct_fields; + bit [11:0] inner_bits; } StructInUnion; typedef union packed { - StructInUnion inner_union; - bit [11:0] outer_bits; + StructInUnion inner_union; + bit [11:0] outer_bits; } UnionInUnion; // SimpleUnion Constrained Test Class class SimpleUnionConstrainedTest; - rand SimpleUnion union_instance; + rand SimpleUnion union_instance; - function new(); - union_instance.bits = 32'b0; - endfunction + function new(); + union_instance.bits = 32'b0; + endfunction - constraint union_constraint { - union_instance.bits[11:0] inside {[0:4095]}; - } + constraint union_constraint {union_instance.bits[11:0] inside {[0 : 4095]};} endclass // SimpleUnion Unconstrained Test Class class SimpleUnionUnconstrainedTest; - rand SimpleUnion union_instance; + rand SimpleUnion union_instance; - function new(); - union_instance.bits = 32'b0; - endfunction + function new(); + union_instance.bits = 32'b0; + endfunction endclass // StructInUnion Constrained Test Class class StructInUnionConstrainedTest; - rand StructInUnion union_instance; + rand StructInUnion union_instance; - function new(); - union_instance.inner_bits = 12'b0; - endfunction + function new(); + union_instance.inner_bits = 12'b0; + endfunction - constraint union_constraint { - union_instance.inner_bits inside {[0:4095]}; - } + constraint union_constraint {union_instance.inner_bits inside {[0 : 4095]};} endclass // StructInUnion Unconstrained Test Class class StructInUnionUnconstrainedTest; - rand StructInUnion union_instance; + rand StructInUnion union_instance; - function new(); - union_instance.inner_bits = 12'b0; - endfunction + function new(); + union_instance.inner_bits = 12'b0; + endfunction endclass // UnionInUnion Constrained Test Class class UnionInUnionConstrainedTest; - rand UnionInUnion union_instance; + rand UnionInUnion union_instance; - function new(); - union_instance.outer_bits = 12'b0; - endfunction + function new(); + union_instance.outer_bits = 12'b0; + endfunction - constraint union_constraint { - union_instance.outer_bits inside {[0:4095]}; - } + constraint union_constraint {union_instance.outer_bits inside {[0 : 4095]};} endclass // UnionInUnion Unconstrained Test Class class UnionInUnionUnconstrainedTest; - rand UnionInUnion union_instance; + rand UnionInUnion union_instance; - function new(); - union_instance.outer_bits = 12'b0; - endfunction + function new(); + union_instance.outer_bits = 12'b0; + endfunction endclass // Top-Level Test Module module t_randomize_union; - // Instances of each test class - SimpleUnionConstrainedTest test_simple_union_constrained; - SimpleUnionUnconstrainedTest test_simple_union_unconstrained; - StructInUnionConstrainedTest test_struct_in_union_constrained; - StructInUnionUnconstrainedTest test_struct_in_union_unconstrained; - UnionInUnionConstrainedTest test_union_in_union_constrained; - UnionInUnionUnconstrainedTest test_union_in_union_unconstrained; + // Instances of each test class + SimpleUnionConstrainedTest test_simple_union_constrained; + SimpleUnionUnconstrainedTest test_simple_union_unconstrained; + StructInUnionConstrainedTest test_struct_in_union_constrained; + StructInUnionUnconstrainedTest test_struct_in_union_unconstrained; + UnionInUnionConstrainedTest test_union_in_union_constrained; + UnionInUnionUnconstrainedTest test_union_in_union_unconstrained; - initial begin - // Test 1: SimpleUnion Constrained Test - test_simple_union_constrained = new(); - $display("\n--- Test 1: SimpleUnion Constrained Test ---"); - repeat(10) begin - int success; - success = test_simple_union_constrained.randomize(); - if (success != 1) $stop; - $display("SimpleUnion (Constrained): int_value: %b, bits: %b", test_simple_union_constrained.union_instance.int_value, test_simple_union_constrained.union_instance.bits); - end - - // Test 2: SimpleUnion Unconstrained Test - test_simple_union_unconstrained = new(); - $display("\n--- Test 2: SimpleUnion Unconstrained Test ---"); - repeat(10) begin - int success; - success = test_simple_union_unconstrained.randomize(); - if (success != 1) $stop; - $display("SimpleUnion (Unconstrained): int_value: %b, bits: %b", test_simple_union_unconstrained.union_instance.int_value, test_simple_union_unconstrained.union_instance.bits); - end - - // Test 3: StructInUnion Constrained Test - test_struct_in_union_constrained = new(); - $display("\n--- Test 3: StructInUnion Constrained Test ---"); - repeat(10) begin - int success; - success = test_struct_in_union_constrained.randomize(); - if (success != 1) $stop; - $display("StructInUnion (Constrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_constrained.union_instance.struct_fields.field_a, test_struct_in_union_constrained.union_instance.struct_fields.field_b, test_struct_in_union_constrained.union_instance.inner_bits); - end - - // Test 4: StructInUnion Unconstrained Test - test_struct_in_union_unconstrained = new(); - $display("\n--- Test 4: StructInUnion Unconstrained Test ---"); - repeat(10) begin - int success; - success = test_struct_in_union_unconstrained.randomize(); - if (success != 1) $stop; - $display("StructInUnion (Unconstrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_unconstrained.union_instance.struct_fields.field_a, test_struct_in_union_unconstrained.union_instance.struct_fields.field_b, test_struct_in_union_unconstrained.union_instance.inner_bits); - end - - // Test 5: UnionInUnion Constrained Test - test_union_in_union_constrained = new(); - $display("\n--- Test 5: UnionInUnion Constrained Test ---"); - repeat(10) begin - int success; - success = test_union_in_union_constrained.randomize(); - if (success != 1) $stop; - $display("UnionInUnion (Constrained): outer_bits: %b, inner_union.struct: %b, b: %b", test_union_in_union_constrained.union_instance.outer_bits, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_a, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_b); - end - - // Test 6: UnionInUnion Unconstrained Test - test_union_in_union_unconstrained = new(); - $display("\n--- Test 6: UnionInUnion Unconstrained Test ---"); - repeat(10) begin - int success; - success = test_union_in_union_unconstrained.randomize(); - if (success != 1) $stop; - $display("UnionInUnion (Unconstrained): outer_bits: %b, inner_union.struct: %b, inner_union.inner_bits: %b", test_union_in_union_unconstrained.union_instance.outer_bits, test_union_in_union_unconstrained.union_instance.inner_union.struct_fields, test_union_in_union_unconstrained.union_instance.inner_union.inner_bits); - end - $write("*-* All Finished *-*\n"); - $finish; + initial begin + // Test 1: SimpleUnion Constrained Test + test_simple_union_constrained = new(); + $display("\n--- Test 1: SimpleUnion Constrained Test ---"); + repeat (10) begin + int success; + success = test_simple_union_constrained.randomize(); + if (success != 1) $stop; + $display("SimpleUnion (Constrained): int_value: %b, bits: %b", + test_simple_union_constrained.union_instance.int_value, + test_simple_union_constrained.union_instance.bits); end + // Test 2: SimpleUnion Unconstrained Test + test_simple_union_unconstrained = new(); + $display("\n--- Test 2: SimpleUnion Unconstrained Test ---"); + repeat (10) begin + int success; + success = test_simple_union_unconstrained.randomize(); + if (success != 1) $stop; + $display("SimpleUnion (Unconstrained): int_value: %b, bits: %b", + test_simple_union_unconstrained.union_instance.int_value, + test_simple_union_unconstrained.union_instance.bits); + end + + // Test 3: StructInUnion Constrained Test + test_struct_in_union_constrained = new(); + $display("\n--- Test 3: StructInUnion Constrained Test ---"); + repeat (10) begin + int success; + success = test_struct_in_union_constrained.randomize(); + if (success != 1) $stop; + $display("StructInUnion (Constrained): struct.a: %b, struct.b: %b, inner_bits: %b", + test_struct_in_union_constrained.union_instance.struct_fields.field_a, + test_struct_in_union_constrained.union_instance.struct_fields.field_b, + test_struct_in_union_constrained.union_instance.inner_bits); + end + + // Test 4: StructInUnion Unconstrained Test + test_struct_in_union_unconstrained = new(); + $display("\n--- Test 4: StructInUnion Unconstrained Test ---"); + repeat (10) begin + int success; + success = test_struct_in_union_unconstrained.randomize(); + if (success != 1) $stop; + $display("StructInUnion (Unconstrained): struct.a: %b, struct.b: %b, inner_bits: %b", + test_struct_in_union_unconstrained.union_instance.struct_fields.field_a, + test_struct_in_union_unconstrained.union_instance.struct_fields.field_b, + test_struct_in_union_unconstrained.union_instance.inner_bits); + end + + // Test 5: UnionInUnion Constrained Test + test_union_in_union_constrained = new(); + $display("\n--- Test 5: UnionInUnion Constrained Test ---"); + repeat (10) begin + int success; + success = test_union_in_union_constrained.randomize(); + if (success != 1) $stop; + $display("UnionInUnion (Constrained): outer_bits: %b, inner_union.struct: %b, b: %b", + test_union_in_union_constrained.union_instance.outer_bits, + test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_a, + test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_b); + end + + // Test 6: UnionInUnion Unconstrained Test + test_union_in_union_unconstrained = new(); + $display("\n--- Test 6: UnionInUnion Unconstrained Test ---"); + repeat (10) begin + int success; + success = test_union_in_union_unconstrained.randomize(); + if (success != 1) $stop; + $display( + "UnionInUnion (Unconstrained): outer_bits: %b, inner_union.struct: %b, inner_union.inner_bits: %b", + test_union_in_union_unconstrained.union_instance.outer_bits, + test_union_in_union_unconstrained.union_instance.inner_union.struct_fields, + test_union_in_union_unconstrained.union_instance.inner_union.inner_bits); + end + $write("*-* All Finished *-*\n"); + $finish; + end + endmodule diff --git a/test_regress/t/t_randomize_union_bad.v b/test_regress/t/t_randomize_union_bad.v index 08c00e22d..e1092ee0e 100644 --- a/test_regress/t/t_randomize_union_bad.v +++ b/test_regress/t/t_randomize_union_bad.v @@ -5,32 +5,34 @@ // SPDX-License-Identifier: CC0-1.0 typedef union { - int int_value; - bit [31:0] bits; + int int_value; + bit [31:0] bits; } UnpackedUnion; class UnpackedUnionErrorTest; - rand UnpackedUnion union_instance; + rand UnpackedUnion union_instance; - function new(); - union_instance.bits = 32'b0; - endfunction + function new(); + union_instance.bits = 32'b0; + endfunction endclass module t_randomize_union_bad; - UnpackedUnionErrorTest test_unpacked_union; + UnpackedUnionErrorTest test_unpacked_union; - initial begin - test_unpacked_union = new(); - repeat(10) begin - int success; - success = test_unpacked_union.randomize(); - if (success != 1) $stop; - $display("UnpackedUnion: int_value: %b, bits: %b", test_unpacked_union.union_instance.int_value, test_unpacked_union.union_instance.bits); - end - $write("*-* All Finished *-*\n"); - $finish; + initial begin + test_unpacked_union = new(); + repeat (10) begin + int success; + success = test_unpacked_union.randomize(); + if (success != 1) $stop; + $display("UnpackedUnion: int_value: %b, bits: %b", + test_unpacked_union.union_instance.int_value, + test_unpacked_union.union_instance.bits); end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randstate_func.v b/test_regress/t/t_randstate_func.v index 663309356..8db25cbc4 100644 --- a/test_regress/t/t_randstate_func.v +++ b/test_regress/t/t_randstate_func.v @@ -5,41 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - rand int length; + rand int length; - function void test; - automatic int rand_result, v1, v2; - automatic string s; + function void test; + automatic int rand_result, v1, v2; + automatic string s; - // UVM 2023 does a print, so check is ascii - $display("get_randstate = '%s'", get_randstate()); + // UVM 2023 does a print, so check is ascii + $display("get_randstate = '%s'", get_randstate()); - s = get_randstate(); + s = get_randstate(); - rand_result = randomize(); - if (rand_result != 1) $stop; - v1 = length; + rand_result = randomize(); + if (rand_result != 1) $stop; + v1 = length; - set_randstate(s); + set_randstate(s); - rand_result = randomize(); - if (rand_result != 1) $stop; - v2 = length; + rand_result = randomize(); + if (rand_result != 1) $stop; + v2 = length; `ifdef VERILATOR // About half of the other simulators fail at this - if (v1 != v2) $stop; + if (v1 != v2) $stop; `endif - endfunction + endfunction endclass module t; - initial begin - Cls c; - c = new; - c.test; + initial begin + Cls c; + c = new; + c.test; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randstate_seed_bad.v b/test_regress/t/t_randstate_seed_bad.v index c454710a9..3011f4c28 100644 --- a/test_regress/t/t_randstate_seed_bad.v +++ b/test_regress/t/t_randstate_seed_bad.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - function void test; - automatic string s; + function void test; + automatic string s; - s = get_randstate(); - // Vlt only result check - if (s[0] !== "R") $fatal(2, $sformatf("Bad get_randstate = '%s'", s)); + s = get_randstate(); + // Vlt only result check + if (s[0] !== "R") $fatal(2, $sformatf("Bad get_randstate = '%s'", s)); - set_randstate("000bad"); // Bad - set_randstate("Zdlffjfmkmhodjcnddlffjfmkmhodjcnd"); // Bad - endfunction + set_randstate("000bad"); // Bad + set_randstate("Zdlffjfmkmhodjcnddlffjfmkmhodjcnd"); // Bad + endfunction endclass module t; - initial begin - Cls c; - c = new; - c.test; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c = new; + c.test; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_real_cast.v b/test_regress/t/t_real_cast.v index 4a5b3e187..a0104c967 100644 --- a/test_regress/t/t_real_cast.v +++ b/test_regress/t/t_real_cast.v @@ -4,36 +4,33 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + typedef logic [85:0] big_t; + localparam big_t foo = big_t'(8.531630271583128e+16); - typedef logic [85:0] big_t; - localparam big_t foo = big_t'(8.531630271583128e+16); + big_t bar; + int cyc; + real some_real; - big_t bar; - int cyc; - real some_real; + initial begin + cyc = 0; + some_real = 5.123; + end - initial begin - cyc = 0; - some_real = 5.123; - end - - always_comb bar = big_t'(some_real); - - always @(posedge clk) begin - cyc <= cyc + 1; - some_real <= some_real * 1.234e4; - if (cyc == 6) begin - if (foo != 86'd85316302715831280) $stop(); - if (bar != 86'd18089031459271914704338944) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + always_comb bar = big_t'(some_real); + + always @(posedge clk) begin + cyc <= cyc + 1; + some_real <= some_real * 1.234e4; + if (cyc == 6) begin + if (foo != 86'd85316302715831280) $stop(); + if (bar != 86'd18089031459271914704338944) $stop(); + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule diff --git a/test_regress/t/t_real_param.v b/test_regress/t/t_real_param.v index 0f86b3b3b..9647fb16c 100644 --- a/test_regress/t/t_real_param.v +++ b/test_regress/t/t_real_param.v @@ -4,33 +4,32 @@ // SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module foo - #( parameter real BAR = 2.0) - (); +module foo #( + parameter real BAR = 2.0 +) (); endmodule module t; - genvar m, r; - generate - for (m = 10; m <= 20; m+=10) begin : gen_m - for (r = 0; r <= 1; r++) begin : gen_r - localparam real LPARAM = m + (r + 0.5); - initial begin - if (LPARAM != foo_inst.BAR) begin - $display("%m: LPARAM != foo_inst.BAR (%f, %f)", - LPARAM, foo_inst.BAR); - $stop(); - end - end + genvar m, r; + generate + for (m = 10; m <= 20; m += 10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real LPARAM = m + (r + 0.5); + initial begin + if (LPARAM != foo_inst.BAR) begin + $display("%m: LPARAM != foo_inst.BAR (%f, %f)", LPARAM, foo_inst.BAR); + $stop(); + end + end - foo #(.BAR (LPARAM)) foo_inst (); - end + foo #(.BAR(LPARAM)) foo_inst (); end - endgenerate + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_recursive_method.v b/test_regress/t/t_recursive_method.v index 1209221af..e0e00b64e 100644 --- a/test_regress/t/t_recursive_method.v +++ b/test_regress/t/t_recursive_method.v @@ -5,66 +5,60 @@ // SPDX-License-Identifier: CC0-1.0 class Fib; - function int get_fib(int n); - if (n == 0 || n == 1) - return n; - else - return get_fib(n - 1) + get_fib(n - 2); - endfunction + function int get_fib(int n); + if (n == 0 || n == 1) return n; + else return get_fib(n - 1) + get_fib(n - 2); + endfunction endclass class FibStatic; - static function int get_fib(int n); - if (n == 0 || n == 1) - return n; - else - return get_fib(n - 1) + get_fib(n - 2); - endfunction + static function int get_fib(int n); + if (n == 0 || n == 1) return n; + else return get_fib(n - 1) + get_fib(n - 2); + endfunction endclass class Factorial; - static function int factorial(int n); - return fact(n, 1); - endfunction - static function int fact(int n, int acc); - if (n < 2) - fact = acc; - else - fact = fact(n - 1, acc * n); - endfunction + static function int factorial(int n); + return fact(n, 1); + endfunction + static function int fact(int n, int acc); + if (n < 2) fact = acc; + else fact = fact(n - 1, acc * n); + endfunction endclass -class Getter3 #(int T=5); - static function int get_3(); - if (T == 3) - return 3; - else - return Getter3#(3)::get_3(); - endfunction +class Getter3 #( + int T = 5 +); + static function int get_3(); + if (T == 3) return 3; + else return Getter3#(3)::get_3(); + endfunction endclass module t; - initial begin - automatic Fib fib = new; - automatic Getter3 getter3 = new; + initial begin + automatic Fib fib = new; + automatic Getter3 getter3 = new; - if (fib.get_fib(0) != 0) $stop; - if (fib.get_fib(1) != 1) $stop; - if (fib.get_fib(8) != 21) $stop; + if (fib.get_fib(0) != 0) $stop; + if (fib.get_fib(1) != 1) $stop; + if (fib.get_fib(8) != 21) $stop; - if (FibStatic::get_fib(0) != 0) $stop; - if (FibStatic::get_fib(1) != 1) $stop; - if (FibStatic::get_fib(8) != 21) $stop; + if (FibStatic::get_fib(0) != 0) $stop; + if (FibStatic::get_fib(1) != 1) $stop; + if (FibStatic::get_fib(8) != 21) $stop; - if (Factorial::factorial(0) != 1) $stop; - if (Factorial::factorial(1) != 1) $stop; - if (Factorial::factorial(6) != 720) $stop; + if (Factorial::factorial(0) != 1) $stop; + if (Factorial::factorial(1) != 1) $stop; + if (Factorial::factorial(6) != 720) $stop; - if (getter3.get_3() != 3) $stop; - if (Getter3#(3)::get_3() != 3) $stop; + if (getter3.get_3() != 3) $stop; + if (Getter3#(3)::get_3() != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_recursive_module_bug.v b/test_regress/t/t_recursive_module_bug.v index 118d1460c..191046c9f 100644 --- a/test_regress/t/t_recursive_module_bug.v +++ b/test_regress/t/t_recursive_module_bug.v @@ -11,36 +11,69 @@ // then caused V3Inline to blow up as it assumes that. module top #( - parameter N=8 + parameter N = 8 ) ( - input wire [N-1:0] i, - output wire [N-1:0] o, - output wire [N-1:0] a + input wire [N-1:0] i, + output wire [N-1:0] o, + output wire [N-1:0] a ); -sub #(.N(N)) inst(.i(i), .o(a)); + sub #( + .N(N) + ) inst ( + .i(i), + .o(a) + ); -generate if (N > 1) begin: recursive - top #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2]), .a()); - top #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0]), .a()); -end else begin: base - assign o = i; -end endgenerate + generate + if (N > 1) begin : recursive + top #( + .N(N / 2) + ) hi ( + .i(i[N-1:N/2]), + .o(o[N-1:N/2]), + .a() + ); + top #( + .N(N / 2) + ) lo ( + .i(i[N/2-1:0]), + .o(o[N/2-1:0]), + .a() + ); + end + else begin : base + assign o = i; + end + endgenerate endmodule module sub #( parameter N = 8 ) ( - input wire [N-1:0] i, - output wire [N-1:0] o + input wire [N-1:0] i, + output wire [N-1:0] o ); -generate if (N > 1) begin: recursive - sub #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2])); - sub #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0])); -end else begin: base - assign o = i; -end endgenerate + generate + if (N > 1) begin : recursive + sub #( + .N(N / 2) + ) hi ( + .i(i[N-1:N/2]), + .o(o[N-1:N/2]) + ); + sub #( + .N(N / 2) + ) lo ( + .i(i[N/2-1:0]), + .o(o[N/2-1:0]) + ); + end + else begin : base + assign o = i; + end + endgenerate endmodule diff --git a/test_regress/t/t_recursive_module_bug_2.v b/test_regress/t/t_recursive_module_bug_2.v index 658442cd8..b2d501899 100644 --- a/test_regress/t/t_recursive_module_bug_2.v +++ b/test_regress/t/t_recursive_module_bug_2.v @@ -6,17 +6,20 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module a #(parameter N) (); - generate if (N > 1) begin +module a #( + parameter N +) (); + generate + if (N > 1) begin // With N == 5, this will first expand N == 2, then expand N == 3, // which instantiates N == 2. This requires fixing up topological order // in V3Param. - a #(.N( N/2)) sub_lo(); - a #(.N(N-N/2)) sub_hi(); - end - endgenerate + a #(.N(N / 2)) sub_lo (); + a #(.N(N - N / 2)) sub_hi (); + end + endgenerate endmodule -module top(); - a #(.N(5)) root (); +module top (); + a #(.N(5)) root (); endmodule diff --git a/test_regress/t/t_reloop_cam.v b/test_regress/t/t_reloop_cam.v index 6f347345b..ee493e691 100644 --- a/test_regress/t/t_reloop_cam.v +++ b/test_regress/t/t_reloop_cam.v @@ -4,174 +4,172 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - reg rst; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + reg rst; - // Two phases, random so nothing optimizes away, and focused so get hits - logic inval; - wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); - wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); - wire wdat_val = 1'b1; - wire camen = crc[32]; - wire ren = crc[33]; - wire wen = crc[34]; - wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); + // Two phases, random so nothing optimizes away, and focused so get hits + logic inval; + wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); + wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); + wire wdat_val = 1'b1; + wire camen = crc[32]; + wire ren = crc[33]; + wire wen = crc[34]; + wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic hit_d2r; // From cam of cam.v - logic [7:0] hitidx_d1r; // From cam of cam.v - logic [255:0] hitvec_d1r; // From cam of cam.v - logic [30:0] rdat_d2r; // From cam of cam.v - logic rdat_val_d2r; // From cam of cam.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic hit_d2r; // From cam of cam.v + logic [7:0] hitidx_d1r; // From cam of cam.v + logic [255:0] hitvec_d1r; // From cam of cam.v + logic [30:0] rdat_d2r; // From cam of cam.v + logic rdat_val_d2r; // From cam of cam.v + // End of automatics - cam cam (/*AUTOINST*/ - // Outputs - .hitvec_d1r (hitvec_d1r[255:0]), - .hitidx_d1r (hitidx_d1r[7:0]), - .hit_d2r (hit_d2r), - .rdat_d2r (rdat_d2r[30:0]), - .rdat_val_d2r (rdat_val_d2r), - // Inputs - .clk (clk), - .rst (rst), - .camen (camen), - .inval (inval), - .cdat (cdat[30:0]), - .ren (ren), - .wen (wen), - .wdat (wdat[30:0]), - .wdat_val (wdat_val), - .rwidx (rwidx[7:0])); + cam cam ( /*AUTOINST*/ + // Outputs + .hitvec_d1r(hitvec_d1r[255:0]), + .hitidx_d1r(hitidx_d1r[7:0]), + .hit_d2r(hit_d2r), + .rdat_d2r(rdat_d2r[30:0]), + .rdat_val_d2r(rdat_val_d2r), + // Inputs + .clk(clk), + .rst(rst), + .camen(camen), + .inval(inval), + .cdat(cdat[30:0]), + .ren(ren), + .wen(wen), + .wdat(wdat[30:0]), + .wdat_val(wdat_val), + .rwidx(rwidx[7:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; + // Aggregate outputs into a single result vector + wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - rst <= 1'b1; - end - else if (cyc<10) begin - sum <= '0; - rst <= 1'b0; - end - else if (cyc==70) begin - inval <= 1'b1; - end - else if (cyc==71) begin - inval <= 1'b0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h5182640870b07199 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + rst <= 1'b1; + end + else if (cyc < 10) begin + sum <= '0; + rst <= 1'b0; + end + else if (cyc == 70) begin + inval <= 1'b1; + end + else if (cyc == 71) begin + inval <= 1'b0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h5182640870b07199 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module cam - ( - input clk, - input rst, +module cam ( + input clk, + input rst, - input camen, - input inval, - input [30:0] cdat, - output logic [255:0] hitvec_d1r, - output logic [7:0] hitidx_d1r, - output logic hit_d2r, + input camen, + input inval, + input [30:0] cdat, + output logic [255:0] hitvec_d1r, + output logic [7:0] hitidx_d1r, + output logic hit_d2r, - input ren, - input wen, - input [30:0] wdat, - input wdat_val, - input [7:0] rwidx, - output logic [30:0] rdat_d2r, - output logic rdat_val_d2r - ); + input ren, + input wen, + input [30:0] wdat, + input wdat_val, + input [7:0] rwidx, + output logic [30:0] rdat_d2r, + output logic rdat_val_d2r +); - logic camen_d1r; - logic inval_d1r; - logic ren_d1r; - logic wen_d1r; - logic [7:0] rwidx_d1r; - logic [30:0] cdat_d1r; - logic [30:0] wdat_d1r; - logic wdat_val_d1r; + logic camen_d1r; + logic inval_d1r; + logic ren_d1r; + logic wen_d1r; + logic [7:0] rwidx_d1r; + logic [30:0] cdat_d1r; + logic [30:0] wdat_d1r; + logic wdat_val_d1r; - always_ff @(posedge clk) begin - camen_d1r <= camen; - inval_d1r <= inval; - ren_d1r <= ren; - wen_d1r <= wen; + always_ff @(posedge clk) begin + camen_d1r <= camen; + inval_d1r <= inval; + ren_d1r <= ren; + wen_d1r <= wen; - cdat_d1r <= cdat; - rwidx_d1r <= rwidx; - wdat_d1r <= wdat; - wdat_val_d1r <= wdat_val; - end + cdat_d1r <= cdat; + rwidx_d1r <= rwidx; + wdat_d1r <= wdat; + wdat_val_d1r <= wdat_val; + end - typedef struct packed { - logic [30:0] data; - logic valid; - } entry_t; - entry_t [255:0] entries; + typedef struct packed { + logic [30:0] data; + logic valid; + } entry_t; + entry_t [255:0] entries; - always_ff @(posedge clk) begin - if (camen_d1r) begin - for (int i = 0; i < 256; i = i + 1) begin - hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); - end + always_ff @(posedge clk) begin + if (camen_d1r) begin + for (int i = 0; i < 256; i = i + 1) begin + hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); end - end - always_ff @(posedge clk) begin - hit_d2r <= | hitvec_d1r; - end + end + end + always_ff @(posedge clk) begin + hit_d2r <= |hitvec_d1r; + end - always_ff @(posedge clk) begin - if (rst) begin - for (int i = 0; i < 256; i = i + 1) begin - entries[i] <= '0; - end + always_ff @(posedge clk) begin + if (rst) begin + for (int i = 0; i < 256; i = i + 1) begin + entries[i] <= '0; end - else if (wen_d1r) begin - entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r}; + end + else if (wen_d1r) begin + entries[rwidx_d1r] <= '{valid: wdat_val_d1r, data: wdat_d1r}; + end + else if (inval_d1r) begin + for (int i = 0; i < 256; i = i + 1) begin + entries[i] <= '{valid: '0, data: entries[i].data}; end - else if (inval_d1r) begin - for (int i = 0; i < 256; i = i + 1) begin - entries[i] <= '{valid:'0, data:entries[i].data}; - end - end - end + end + end - always_ff @(posedge clk) begin - if (ren_d1r) begin - rdat_d2r <= entries[rwidx_d1r].data; - rdat_val_d2r <= entries[rwidx_d1r].valid; - end - end + always_ff @(posedge clk) begin + if (ren_d1r) begin + rdat_d2r <= entries[rwidx_d1r].data; + rdat_val_d2r <= entries[rwidx_d1r].valid; + end + end endmodule diff --git a/test_regress/t/t_reloop_local.v b/test_regress/t/t_reloop_local.v index 9a9dce57c..7a0c7f409 100644 --- a/test_regress/t/t_reloop_local.v +++ b/test_regress/t/t_reloop_local.v @@ -7,82 +7,86 @@ typedef logic [7:0] Word; typedef logic [255:0] BigItem; -module shuffler - ( +module shuffler ( input logic clk, input logic reset_l, output logic odd, output logic [255:0][7:0] shuffle - ); +); - Word ctr; - assign odd = ctr[0]; + Word ctr; + assign odd = ctr[0]; - always_ff @(posedge clk) begin - if (!reset_l) begin - ctr <= 0; - end - else begin - ctr <= ctr + 1; - end - end + always_ff @(posedge clk) begin + if (!reset_l) begin + ctr <= 0; + end + else begin + ctr <= ctr + 1; + end + end - for (genvar i = 0; i < 256; i++) always_comb begin - shuffle[i] = Word'(i) - ctr; - end + for (genvar i = 0; i < 256; i++) + always_comb begin + shuffle[i] = Word'(i) - ctr; + end - for (genvar i = 0; i < 256; i++) begin - assert property (@(posedge clk) shuffle[ctr + Word'(i)] == i); - end + for (genvar i = 0; i < 256; i++) begin + assert property (@(posedge clk) shuffle[ctr+Word'(i)] == i); + end endmodule -interface big_port(); - BigItem big; +interface big_port (); + BigItem big; - function automatic BigItem get_big(); - return big; - endfunction + function automatic BigItem get_big(); + return big; + endfunction - modport reader(import get_big); + modport reader(import get_big); endinterface module foo ( - input clk, - input reset_l, - big_port.reader big); + input clk, + input reset_l, + big_port.reader big +); - logic odd; - Word[255 : 0] shuffle; - shuffler fifo ( - .clk, - .reset_l, - .odd, - .shuffle - ); + logic odd; + Word [255 : 0] shuffle; + shuffler fifo ( + .clk, + .reset_l, + .odd, + .shuffle + ); - BigItem bigs[256]; - for (genvar i = 0; i < 256; i++) always_comb begin - bigs[i] = odd ? big.get_big() : 0; - end + BigItem bigs[256]; + for (genvar i = 0; i < 256; i++) + always_comb begin + bigs[i] = odd ? big.get_big() : 0; + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk, reset_l - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + reset_l +); - input clk; - input reset_l; + input clk; + input reset_l; - big_port big(); + big_port big (); - foo foo ( - .clk, - .reset_l, - .big); + foo foo ( + .clk, + .reset_l, + .big + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_reloop_offset.v b/test_regress/t/t_reloop_offset.v index c043f44c8..c8947dac3 100644 --- a/test_regress/t/t_reloop_offset.v +++ b/test_regress/t/t_reloop_offset.v @@ -8,43 +8,43 @@ module t; - int iarray [63:0]; - int oarray [63:0]; + int iarray[63:0]; + int oarray[63:0]; - initial begin - for (int i = 0; i < 64 ; i = i + 1) begin - iarray[i] = i; - oarray[i] = 0; - end + initial begin + for (int i = 0; i < 64; i = i + 1) begin + iarray[i] = i; + oarray[i] = 0; + end - for (int i = 0; i < 63; i = i + 1) begin - oarray[i] = iarray[i + 1]; - end + for (int i = 0; i < 63; i = i + 1) begin + oarray[i] = iarray[i+1]; + end - $display("shift down 1"); - `show(63); - `show(62); - `show(61); - `show(32); - `show(2); - `show(1); - `show(0); + $display("shift down 1"); + `show(63); + `show(62); + `show(61); + `show(32); + `show(2); + `show(1); + `show(0); - for (int i = 63; i >= 2 ; i = i - 1) begin - oarray[i] = iarray[i - 2]; - end + for (int i = 63; i >= 2; i = i - 1) begin + oarray[i] = iarray[i-2]; + end - $display("shift up 2"); - `show(63); - `show(62); - `show(61); - `show(32); - `show(2); - `show(1); - `show(0); + $display("shift up 2"); + `show(63); + `show(62); + `show(61); + `show(32); + `show(2); + `show(1); + `show(0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_repeat.v b/test_regress/t/t_repeat.v index 38445c644..621b2ed3b 100644 --- a/test_regress/t/t_repeat.v +++ b/test_regress/t/t_repeat.v @@ -6,28 +6,28 @@ module t; - reg signed [2:0] negcnt; - integer times; - initial begin - times = 0; - repeat (1) begin - repeat (0) $stop; - repeat (-1) $stop; - negcnt = 'sb111; - // Not all commercial simulators agree on the below stopping or not - // verilator lint_off WIDTH - repeat (negcnt) $stop; - // verilator lint_on WIDTH - repeat (5) begin - repeat (2) begin - times = times + 1; - end - end + reg signed [2:0] negcnt; + integer times; + initial begin + times = 0; + repeat (1) begin + repeat (0) $stop; + repeat (-1) $stop; + negcnt = 'sb111; + // Not all commercial simulators agree on the below stopping or not + // verilator lint_off WIDTH + repeat (negcnt) $stop; + // verilator lint_on WIDTH + repeat (5) begin + repeat (2) begin + times = times + 1; + end end - if (times != 10) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (times != 10) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_rnd.v b/test_regress/t/t_rnd.v index 09feede25..35a5cf17f 100644 --- a/test_regress/t/t_rnd.v +++ b/test_regress/t/t_rnd.v @@ -4,46 +4,45 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg _ranit; + reg _ranit; - reg [2:0] a; - reg [33:0] wide; - reg unused_r; + reg [2:0] a; + reg [33:0] wide; + reg unused_r; - initial _ranit = 0; + initial _ranit = 0; - always @ (posedge clk) begin : blockName - begin // Verify begin/begin is legal - unused_r <= 1'b1; - end - begin end // Verify empty is legal - end + always @(posedge clk) begin : blockName + begin // Verify begin/begin is legal + unused_r <= 1'b1; + end + begin + end // Verify empty is legal + end - wire one = 1'b1; - wire [7:0] rand_bits = 8'b01xx_xx10; + wire one = 1'b1; + wire [7:0] rand_bits = 8'b01xx_xx10; - always @ (posedge clk) begin - if (!_ranit) begin - _ranit <= 1; - // - a = 3'b1xx; - wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; - if (one !== 1'b1) $stop; - if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + // + a = 3'b1xx; + wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; + if (one !== 1'b1) $stop; + if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end - // verilator lint_off UNUSED - wire _unused_ok = |{1'b1, wide}; - // verilator lint_on UNUSED + // verilator lint_off UNUSED + wire _unused_ok = |{1'b1, wide}; + // verilator lint_on UNUSED endmodule diff --git a/test_regress/t/t_runflag.v b/test_regress/t/t_runflag.v index 115ceeccc..0c46052c0 100644 --- a/test_regress/t/t_runflag.v +++ b/test_regress/t/t_runflag.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_bad.v b/test_regress/t/t_runflag_bad.v index 52ef42d60..b1eae5642 100644 --- a/test_regress/t/t_runflag_bad.v +++ b/test_regress/t/t_runflag_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_errorlimit_bad.v b/test_regress/t/t_runflag_errorlimit_bad.v index 3019a10d6..24ccecb9b 100644 --- a/test_regress/t/t_runflag_errorlimit_bad.v +++ b/test_regress/t/t_runflag_errorlimit_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $error("One"); - $error("Two"); - $error("Three"); - $error("Four"); - $error("Five"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $error("One"); + $error("Two"); + $error("Three"); + $error("Four"); + $error("Five"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.v b/test_regress/t/t_runflag_errorlimit_fatal_bad.v index 3570c7f62..88906bedd 100644 --- a/test_regress/t/t_runflag_errorlimit_fatal_bad.v +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $error("One"); - $fatal; - $error("Two"); - $error("Three"); - $error("Four"); - $error("Five"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $error("One"); + $fatal; + $error("Two"); + $error("Three"); + $error("Four"); + $error("Five"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_quiet.v b/test_regress/t/t_runflag_quiet.v index f968cd295..81446b89e 100644 --- a/test_regress/t/t_runflag_quiet.v +++ b/test_regress/t/t_runflag_quiet.v @@ -4,13 +4,12 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -timeunit 1us; -timeprecision 1ns; +timeunit 1us; timeprecision 1ns; module t; - initial begin - #10; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_seed.v b/test_regress/t/t_runflag_seed.v index 5e52bf1ec..564b1d776 100644 --- a/test_regress/t/t_runflag_seed.v +++ b/test_regress/t/t_runflag_seed.v @@ -4,16 +4,18 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - initial begin - automatic integer r = $random; - integer ex; - if ($value$plusargs("SEED=%x", ex) !== 1) $stop; - `checkh(r, ex); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic integer r = $random; + integer ex; + if ($value$plusargs("SEED=%x", ex) !== 1) $stop; + `checkh(r, ex); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_runflag_uninit_bad.v b/test_regress/t/t_runflag_uninit_bad.v index fc082ba27..92afebbf6 100644 --- a/test_regress/t/t_runflag_uninit_bad.v +++ b/test_regress/t/t_runflag_uninit_bad.v @@ -7,5 +7,5 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - initial $display($test$plusargs("MYFLAG")); + initial $display($test$plusargs("MYFLAG")); endmodule diff --git a/test_regress/t/t_sampled_expr.v b/test_regress/t/t_sampled_expr.v index cab5cf066..c29be0d62 100644 --- a/test_regress/t/t_sampled_expr.v +++ b/test_regress/t/t_sampled_expr.v @@ -4,65 +4,64 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +// verilog_format: off +module t ( + input clk + ); - reg [3:0] a, b; + reg [3:0] a, b; - Test1 t1(clk, a, b); - Test2 t2(clk, a, b); - Test3 t3(clk); + Test1 t1(clk, a, b); + Test2 t2(clk, a, b); + Test3 t3(clk); - initial begin - a = 0; - b = 0; - end + initial begin + a = 0; + b = 0; + end - always @(posedge clk) begin - a <= a + 1; - b = b + 1; + always @(posedge clk) begin + a <= a + 1; + b = b + 1; - $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); + $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); - if (b >= 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (b >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test1( - clk, a, b - ); + clk, a, b + ); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) $sampled(a == b) == ($sampled(a) == $sampled(b))); + assert property (@(posedge clk) $sampled(a == b) == ($sampled(a) == $sampled(b))); endmodule module Test2( - clk, a, b - ); + clk, a, b + ); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) eq(a, b)); + assert property (@(posedge clk) eq(a, b)); - function [0:0] eq([3:0] x, y); - return x == y; - endfunction + function [0:0] eq([3:0] x, y); + return x == y; + endfunction endmodule module Test3( - clk - ); + clk + ); - input clk; + input clk; - assert property (@(posedge clk) $sampled($time) == $time); + assert property (@(posedge clk) $sampled($time) == $time); endmodule diff --git a/test_regress/t/t_sampled_expr_unsup.out b/test_regress/t/t_sampled_expr_unsup.out index f6b05c074..d673c1322 100644 --- a/test_regress/t/t_sampled_expr_unsup.out +++ b/test_regress/t/t_sampled_expr_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_sampled_expr_unsup.v:20:38: Unsupported: Write to variable in sampled expression +%Error-UNSUPPORTED: t/t_sampled_expr_unsup.v:18:37: Unsupported: Write to variable in sampled expression : ... note: In instance 't' - 20 | assert property (@(posedge clk) f(a) >= 0); - | ^ + 18 | assert property (@(posedge clk) f(a) >= 0); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_sampled_expr_unsup.v b/test_regress/t/t_sampled_expr_unsup.v index b9941b3ae..5c5486575 100644 --- a/test_regress/t/t_sampled_expr_unsup.v +++ b/test_regress/t/t_sampled_expr_unsup.v @@ -4,18 +4,16 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int a = 0; + int a = 0; - function int f(output int a); - a = 1; - return a; - endfunction + function int f(output int a); + a = 1; + return a; + endfunction - assert property (@(posedge clk) f(a) >= 0); + assert property (@(posedge clk) f(a) >= 0); endmodule diff --git a/test_regress/t/t_sampled_sensitivity.out b/test_regress/t/t_sampled_sensitivity.out index e35a70b97..ca109fe35 100644 --- a/test_regress/t/t_sampled_sensitivity.out +++ b/test_regress/t/t_sampled_sensitivity.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_sampled_sensitivity.v:14:20: Unsupported: $sampled inside sensitivity list +%Error-UNSUPPORTED: t/t_sampled_sensitivity.v:11:20: Unsupported: $sampled inside sensitivity list : ... note: In instance 't' - 14 | always @(posedge $sampled(clk)) begin + 11 | always @(posedge $sampled(clk)) begin | ^~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_sampled_sensitivity.v b/test_regress/t/t_sampled_sensitivity.v index bff4af5a4..5b921e3be 100644 --- a/test_regress/t/t_sampled_sensitivity.v +++ b/test_regress/t/t_sampled_sensitivity.v @@ -4,13 +4,10 @@ // SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; - always @(posedge $sampled(clk)) begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v index 2aca73c43..0be1a9f3f 100644 --- a/test_regress/t/t_savable.v +++ b/test_regress/t/t_savable.v @@ -4,103 +4,103 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, model - ); - /*verilator no_inline_module*/ // So we'll get hiearachy we can test - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk, + model +); + /*verilator no_inline_module*/ // So we'll get hiearachy we can test + input clk; - // Parameter so we can test for different model error - parameter MODEL_WIDTH = 10; - input [MODEL_WIDTH-1:0] model; + // Parameter so we can test for different model error + parameter MODEL_WIDTH = 10; + input [MODEL_WIDTH-1:0] model; - initial $write("Model width = %0d\n", MODEL_WIDTH); + initial $write("Model width = %0d\n", MODEL_WIDTH); - sub sub (/*AUTOINST*/ - // Inputs - .clk (clk)); + sub sub ( /*AUTOINST*/ + // Inputs + .clk(clk) + ); endmodule -module sub (/*AUTOARG*/ - // Inputs - clk - ); +module sub ( + input clk +); - input clk; - /*verilator no_inline_module*/ // So we'll get hiearachy we can test + /*verilator no_inline_module*/ // So we'll get hiearachy we can test - integer cyc = 0; + integer cyc = 0; - reg [127:0] save128; - reg [47:0] save48; - reg [1:0] save2; - bit [255:0] cycdone; // Make sure each cycle executes exactly once - reg [31:0] vec[2:1][2:1]; - reg [2:1][2:1][31:0] pvec; - real r; - string s,s2; - string sarr[2:1]; - string assoc[string]; + reg [127:0] save128; + reg [47:0] save48; + reg [1:0] save2; + bit [255:0] cycdone; // Make sure each cycle executes exactly once + reg [31:0] vec[2:1][2:1]; + reg [2:1][2:1][31:0] pvec; + real r; + string s, s2; + string sarr[2:1]; + string assoc[string]; - string si; + string si; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - si = "siimmed"; - cyc <= cyc + 1; - if (cycdone[cyc[7:0]]) $stop; - cycdone[cyc[7:0]] <= '1; - if (cyc==0) begin - // Setup - save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; - save48 <= 48'h4afe43fb79d7; - save2 <= 2'b10; - vec[1][1] <= 32'h0101; - vec[1][2] <= 32'h0102; - vec[2][1] <= 32'h0201; - vec[2][2] <= 32'h0202; - pvec[1][1] <= 32'h10101; - pvec[1][2] <= 32'h10102; - pvec[2][1] <= 32'h10201; - pvec[2][2] <= 32'h10202; - r <= 1.234; - s <= "hello"; - // Blocking to avoid delayed to dynamic var - sarr[1] = "sarr[1]"; - sarr[2] = "sarr[2]"; - assoc["mapped"] = "Is mapped"; + si = "siimmed"; + cyc <= cyc + 1; + if (cycdone[cyc[7:0]]) $stop; + cycdone[cyc[7:0]] <= '1; + if (cyc == 0) begin + // Setup + save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; + save48 <= 48'h4afe43fb79d7; + save2 <= 2'b10; + vec[1][1] <= 32'h0101; + vec[1][2] <= 32'h0102; + vec[2][1] <= 32'h0201; + vec[2][2] <= 32'h0202; + pvec[1][1] <= 32'h10101; + pvec[1][2] <= 32'h10102; + pvec[2][1] <= 32'h10201; + pvec[2][2] <= 32'h10202; + r <= 1.234; + s <= "hello"; + // Blocking to avoid delayed to dynamic var + sarr[1] = "sarr[1]"; + sarr[2] = "sarr[2]"; + assoc["mapped"] = "Is mapped"; + end + if (cyc == 1) begin + if ($test$plusargs("save_restore") != 0) begin + // Don't allow the restored model to run from time 0, it must run from a restore + $write("%%Error: didn't really restore\n"); + $stop; end - if (cyc==1) begin - if ($test$plusargs("save_restore") != 0) begin - // Don't allow the restored model to run from time 0, it must run from a restore - $write("%%Error: didn't really restore\n"); - $stop; - end - end - else if (cyc==99) begin - if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; - if (save48 !== 48'h4afe43fb79d7) $stop; - if (save2 !== 2'b10) $stop; - if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; - if (vec[1][1] !== 32'h0101) $stop; - if (vec[1][2] !== 32'h0102) $stop; - if (vec[2][1] !== 32'h0201) $stop; - if (vec[2][2] !== 32'h0202) $stop; - if (pvec[1][1] !== 32'h10101) $stop; - if (pvec[1][2] !== 32'h10102) $stop; - if (pvec[2][1] !== 32'h10201) $stop; - if (pvec[2][2] !== 32'h10202) $stop; - if (r != 1.234) $stop; - $display("%s",s); - $display("%s",sarr[1]); - $display("%s",sarr[2]); - if (assoc["mapped"] != "Is mapped") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 99) begin + if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; + if (save48 !== 48'h4afe43fb79d7) $stop; + if (save2 !== 2'b10) $stop; + if (cycdone !== {{(256 - 99) {1'b0}}, {99{1'b1}}}) $stop; + if (vec[1][1] !== 32'h0101) $stop; + if (vec[1][2] !== 32'h0102) $stop; + if (vec[2][1] !== 32'h0201) $stop; + if (vec[2][2] !== 32'h0202) $stop; + if (pvec[1][1] !== 32'h10101) $stop; + if (pvec[1][2] !== 32'h10102) $stop; + if (pvec[2][1] !== 32'h10201) $stop; + if (pvec[2][2] !== 32'h10202) $stop; + if (r != 1.234) $stop; + $display("%s", s); + $display("%s", sarr[1]); + $display("%s", sarr[2]); + if (assoc["mapped"] != "Is mapped") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_savable_class_bad.v b/test_regress/t/t_savable_class_bad.v index 49b5f52f3..549b17000 100644 --- a/test_regress/t/t_savable_class_bad.v +++ b/test_regress/t/t_savable_class_bad.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int imembera; + int imembera; endclass : Cls module t; - initial begin - Cls c; - if (c != null) $stop; - c = new; - c.imembera = 10; - if (c.imembera != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + if (c != null) $stop; + c = new; + c.imembera = 10; + if (c.imembera != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sc_names.v b/test_regress/t/t_sc_names.v index 67372319d..c266cc7c2 100644 --- a/test_regress/t/t_sc_names.v +++ b/test_regress/t/t_sc_names.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - clk - ); - input clk; + clk +); + input clk; endmodule diff --git a/test_regress/t/t_sc_vl_assign_sbw.v b/test_regress/t/t_sc_vl_assign_sbw.v index 7803f8697..0a5805a87 100644 --- a/test_regress/t/t_sc_vl_assign_sbw.v +++ b/test_regress/t/t_sc_vl_assign_sbw.v @@ -6,24 +6,24 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t( - input [255:0] in, - output [255:0] out - ); +module t ( + input [255:0] in, + output [255:0] out +); - // do not optimize assignment - logic tmp = $c(0); - typedef logic[255:0] biguint; - assign out = in + biguint'(tmp); + // do not optimize assignment + logic tmp = $c(0); + typedef logic [255:0] biguint; + assign out = in + biguint'(tmp); - always @(out) begin - if (in !== 1) begin - $write("'in' mismatch: (1 !== %d)\n", logic'(in)); - $stop; - end - else if (out !== 1) begin - $write("'out' mismatch: (1 !== %d)\n", logic'(out)); - $stop; - end - end + always @(out) begin + if (in !== 1) begin + $write("'in' mismatch: (1 !== %d)\n", logic'(in)); + $stop; + end + else if (out !== 1) begin + $write("'out' mismatch: (1 !== %d)\n", logic'(out)); + $stop; + end + end endmodule diff --git a/test_regress/t/t_scheduling_5.v b/test_regress/t/t_scheduling_5.v index 690ce25dd..3dac62629 100644 --- a/test_regress/t/t_scheduling_5.v +++ b/test_regress/t/t_scheduling_5.v @@ -4,41 +4,40 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg start = 0; - reg [31:0] count; - reg [31:0] runner = 0; + reg start = 0; + reg [31:0] count; + reg [31:0] runner = 0; - always @ (posedge start) count = 0; - always @ (posedge start) runner = 3; + always @(posedge start) count = 0; + always @(posedge start) runner = 3; - always @ (runner) begin - if (runner > 0) begin - $display("count=%d runner=%d",count, runner); - count = count + 1; - runner = runner - 1;; + always @(runner) begin + if (runner > 0) begin + $display("count=%d runner=%d", count, runner); + count = count + 1; + runner = runner - 1; + ; + end + end + + reg [7:0] cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: start <= 1'b0; + 8'd01: start <= 1'b1; + 8'd02: begin + $display("Final count=%d", count); + if (count != 32'h3) $stop; end - end - - reg [7:0] cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 8'd1; - case (cyc) - 8'd00: start <= 1'b0; - 8'd01: start <= 1'b1; - 8'd02: begin - $display("Final count=%d", count); - if (count!=32'h3) $stop; - end - default: begin - $write("*-* All Finished *-*\n"); - $finish; - end - endcase - end + default: begin + $write("*-* All Finished *-*\n"); + $finish; + end + endcase + end endmodule diff --git a/test_regress/t/t_scheduling_6.v b/test_regress/t/t_scheduling_6.v index 242241c85..169c560f7 100644 --- a/test_regress/t/t_scheduling_6.v +++ b/test_regress/t/t_scheduling_6.v @@ -6,12 +6,10 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - clk +module top ( + input clk ); - input clk; - reg clk_half = 0; reg [31:0] cyc = 0; @@ -33,7 +31,7 @@ module top( end always @(posedge clk) a = cyc + $c(1); - always @(a) b = a + $c(1); - assign c = a + $c(1); + always @(a) b = a + $c(1); + assign c = a + $c(1); endmodule diff --git a/test_regress/t/t_scheduling_many_clocks.v b/test_regress/t/t_scheduling_many_clocks.v index fef5142c1..9cd72e790 100644 --- a/test_regress/t/t_scheduling_many_clocks.v +++ b/test_regress/t/t_scheduling_many_clocks.v @@ -27,21 +27,22 @@ module t ( int cyc = 0; bit par = 0; always @(posedge clk) begin - if (~|gclk) begin - gclk[0] = 1'b1; - end else begin - gclk = {gclk[N-2:0], gclk[N-1]}; - end + if (~|gclk) begin + gclk[0] = 1'b1; + end + else begin + gclk = {gclk[N-2:0], gclk[N-1]}; + end - // This make the always block requires a 'pre' trigger (and makes it non splitable) - par <= ^gclk; + // This make the always block requires a 'pre' trigger (and makes it non splitable) + par <= ^gclk; - cyc <= cyc + 32'd1; - if (cyc == ITERATIONS*N - 1) begin - $display("final cycle: %0d, par: %0d", cyc, par); - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 32'd1; + if (cyc == ITERATIONS * N - 1) begin + $display("final cycle: %0d, par: %0d", cyc, par); + $write("*-* All Finished *-*\n"); + $finish; + end end for (genvar n = 0; n < N; n++) begin : gen diff --git a/test_regress/t/t_scope_map.v b/test_regress/t/t_scope_map.v index 0080e5a33..99608c144 100644 --- a/test_regress/t/t_scope_map.v +++ b/test_regress/t/t_scope_map.v @@ -5,63 +5,56 @@ // SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module t - ( - input wire CLK - ); +module t ( + input wire CLK +); - foo #(.WIDTH (1)) foo1 (.*); - foo #(.WIDTH (7)) foo7 (.*); - foo #(.WIDTH (8)) foo8 (.*); - foo #(.WIDTH (32)) foo32 (.*); - foo #(.WIDTH (33)) foo33 (.*); - foo #(.WIDTH (40)) foo40 (.*); - foo #(.WIDTH (41)) foo41 (.*); - foo #(.WIDTH (64)) foo64 (.*); - foo #(.WIDTH (65)) foo65 (.*); - foo #(.WIDTH (96)) foo96 (.*); - foo #(.WIDTH (97)) foo97 (.*); - foo #(.WIDTH (128)) foo128 (.*); - foo #(.WIDTH (256)) foo256 (.*); - foo #(.WIDTH (1024)) foo1024 (.*); - bar #(.WIDTH (1024)) bar1024 (.*); + foo #(.WIDTH(1)) foo1 (.*); + foo #(.WIDTH(7)) foo7 (.*); + foo #(.WIDTH(8)) foo8 (.*); + foo #(.WIDTH(32)) foo32 (.*); + foo #(.WIDTH(33)) foo33 (.*); + foo #(.WIDTH(40)) foo40 (.*); + foo #(.WIDTH(41)) foo41 (.*); + foo #(.WIDTH(64)) foo64 (.*); + foo #(.WIDTH(65)) foo65 (.*); + foo #(.WIDTH(96)) foo96 (.*); + foo #(.WIDTH(97)) foo97 (.*); + foo #(.WIDTH(128)) foo128 (.*); + foo #(.WIDTH(256)) foo256 (.*); + foo #(.WIDTH(1024)) foo1024 (.*); + bar #(.WIDTH(1024)) bar1024 (.*); endmodule -module foo - #( +module foo #( parameter WIDTH = 32 - ) - ( +) ( input CLK - ); +); - logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value; - logic [ WIDTH - 1 : 0 ] value_q /* verilator public */; - integer i; + logic [( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0] initial_value; + logic [WIDTH - 1 : 0] value_q /* verilator public */; + integer i; - initial begin - initial_value = '1; + initial begin + initial_value = '1; - for (i = 0; i < WIDTH / 8; i++) - initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ]; + for (i = 0; i < WIDTH / 8; i++) initial_value[i*8+:8] = i[7 : 0]; - value_q = initial_value[ WIDTH - 1 : 0 ]; - end + value_q = initial_value[WIDTH-1 : 0]; + end - always @(posedge CLK) - value_q <= ~value_q; + always @(posedge CLK) value_q <= ~value_q; endmodule -module bar - #( +module bar #( parameter WIDTH = 32 - ) - ( +) ( input CLK - ); +); - foo #(.WIDTH (WIDTH)) foo (.*); + foo #(.WIDTH(WIDTH)) foo (.*); endmodule diff --git a/test_regress/t/t_select_2d.v b/test_regress/t/t_select_2d.v index d57b66623..4f02abce2 100644 --- a/test_regress/t/t_select_2d.v +++ b/test_regress/t/t_select_2d.v @@ -4,75 +4,74 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0; + // Take CRC data and apply to testblock inputs + wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [63:0] out_o; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [63:0] out_o; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .out_o (out_o[63:0]), - // Inputs - .cnt_i (cnt_i[4:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out_o(out_o[63:0]), + // Inputs + .cnt_i(cnt_i[4:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = out_o; + // Aggregate outputs into a single result vector + wire [63:0] result = out_o; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h1f324087bbba0bfa - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h1f324087bbba0bfa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test - (input logic [4:0] cnt_i, - output logic [63:0] out_o); +module Test ( + input logic [4:0] cnt_i, + output logic [63:0] out_o +); - logic [17:0][63:0] data; - initial begin - for (int a = 0; a < 18; ++a) - data[a] = {8{a[7:0]}}; - end + logic [17:0][63:0] data; + initial begin + for (int a = 0; a < 18; ++a) data[a] = {8{a[7:0]}}; + end - // verilator lint_off WIDTH - assign out_o = data[5'd17 - cnt_i]; + // verilator lint_off WIDTH + assign out_o = data[5'd17-cnt_i]; endmodule diff --git a/test_regress/t/t_select_ascending.v b/test_regress/t/t_select_ascending.v index a933a8187..eeef10f33 100644 --- a/test_regress/t/t_select_ascending.v +++ b/test_regress/t/t_select_ascending.v @@ -4,72 +4,71 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // verilator lint_off ASCRANGE - wire [10:41] sel2 = crc[31:0]; - wire [10:100] sel3 = {crc[26:0],crc}; + // verilator lint_off ASCRANGE + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0], crc}; - wire out20 = sel2[{1'b0,crc[3:0]} + 11]; - wire [3:0] out21 = sel2[13 : 16]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + wire out20 = sel2[{1'b0, crc[3:0]}+11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0, crc[3:0]}+20+:4]; + wire [3:0] out23 = sel2[{1'b0, crc[3:0]}+20-:4]; - wire out30 = sel3[{2'b0,crc[3:0]} + 11]; - wire [3:0] out31 = sel3[13 : 16]; - wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + wire out30 = sel3[{2'b0, crc[3:0]}+11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0]+20+:4]; + wire [3:0] out33 = sel3[crc[5:0]+20-:4]; - // Aggregate outputs into a single result vector - wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + // Aggregate outputs into a single result vector + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; - reg [19:50] sel1; - initial begin - // Path clearing - // 122333445 - // 826048260 - sel1 = 32'h12345678; - if (sel1 != 32'h12345678) $stop; - if (sel1[47 : 50] != 4'h8) $stop; - if (sel1[31 : 34] != 4'h4) $stop; - if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] - if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] - end + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[47 : 50] != 4'h8) $stop; + if (sel1[31 : 34] != 4'h4) $stop; + if (sel1[27+:4] != 4'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26-:4] != 4'h2) $stop; //==[23:26], in memory as [27:24] + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20, out21, out22, out23, out30, out31, + out32, out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h28bf65439eb12c00 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h28bf65439eb12c00 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index 30cfd0055..cd5566c49 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -1,13 +1,13 @@ -%Warning-ASCRANGE: t/t_select_bad_msb.v:12:8: Ascending bit range vector: left < right of bit range: [0:22] +%Warning-ASCRANGE: t/t_select_bad_msb.v:13:7: Ascending bit range vector: left < right of bit range: [0:22] : ... note: In instance 't' - 12 | reg [0:22] backwd; - | ^ + 13 | reg [0:22] backwd; + | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Slice range has ascending bit ordering, perhaps you wanted [4:1] +%Warning-SELRANGE: t/t_select_bad_msb.v:17:14: [1:4] Slice range has ascending bit ordering, perhaps you wanted [4:1] : ... note: In instance 't' - 16 | sel2 = mi[1:4]; - | ^ + 17 | sel2 = mi[1:4]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_msb.v b/test_regress/t/t_select_bad_msb.v index 33fffbe54..e42803aea 100644 --- a/test_regress/t/t_select_bad_msb.v +++ b/test_regress/t/t_select_bad_msb.v @@ -4,16 +4,17 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - reg [43:0] mi; - reg [3:0] sel2; - reg [0:22] backwd; + reg [43:0] mi; + reg [3:0] sel2; + reg [0:22] backwd; - always @ (posedge clk) begin - mi = 44'h123; - sel2 = mi[1:4]; - $write ("Bad select %x\n", sel2); - end + always @(posedge clk) begin + mi = 44'h123; + sel2 = mi[1:4]; + $write("Bad select %x\n", sel2); + end endmodule diff --git a/test_regress/t/t_select_bad_range.out b/test_regress/t/t_select_bad_range.out index 19205ca10..88cfdb873 100644 --- a/test_regress/t/t_select_bad_range.out +++ b/test_regress/t/t_select_bad_range.out @@ -1,11 +1,11 @@ -%Warning-SELRANGE: t/t_select_bad_range.v:16:15: Selection index out of range: 44:44 outside 43:0 +%Warning-SELRANGE: t/t_select_bad_range.v:17:13: Selection index out of range: 44:44 outside 43:0 : ... note: In instance 't' - 16 | sel = mi[44]; - | ^ + 17 | sel = mi[44]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 +%Warning-SELRANGE: t/t_select_bad_range.v:18:14: Selection index out of range: 44:41 outside 43:0 : ... note: In instance 't' - 17 | sel2 = mi[44:41]; - | ^ + 18 | sel2 = mi[44:41]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range.v b/test_regress/t/t_select_bad_range.v index f862e5a64..256adbc31 100644 --- a/test_regress/t/t_select_bad_range.v +++ b/test_regress/t/t_select_bad_range.v @@ -4,17 +4,18 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - reg [43:0] mi; - reg sel; - reg [3:0] sel2; + reg [43:0] mi; + reg sel; + reg [3:0] sel2; - always @ (posedge clk) begin - mi = 44'h123; - sel = mi[44]; - sel2 = mi[44:41]; - $write ("Bad select %x %x\n", sel, sel2); - end + always @(posedge clk) begin + mi = 44'h123; + sel = mi[44]; + sel2 = mi[44:41]; + $write("Bad select %x %x\n", sel, sel2); + end endmodule diff --git a/test_regress/t/t_select_bad_range2.out b/test_regress/t/t_select_bad_range2.out index 428fc9aed..1da61403d 100644 --- a/test_regress/t/t_select_bad_range2.out +++ b/test_regress/t/t_select_bad_range2.out @@ -1,7 +1,7 @@ -%Warning-SELRANGE: t/t_select_bad_range2.v:51:21: Selection index out of range: 3:2 outside 1:0 +%Warning-SELRANGE: t/t_select_bad_range2.v:51:20: Selection index out of range: 3:2 outside 1:0 : ... note: In instance 't.test' - 51 | assign out32 = in[3:2]; - | ^ + 51 | assign out32 = in[3:2]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range2.v b/test_regress/t/t_select_bad_range2.v index 455988cdf..a7226b15f 100644 --- a/test_regress/t/t_select_bad_range2.v +++ b/test_regress/t/t_select_bad_range2.v @@ -4,50 +4,50 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [1:0] in; + reg [1:0] in; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] out10; // From test of Test.v - wire [1:0] out32; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] out10; // From test of Test.v + wire [1:0] out32; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out32 (out32[1:0]), - .out10 (out10[1:0]), - // Inputs - .in (in[1:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out32(out32[1:0]), + .out10(out10[1:0]), + // Inputs + .in(in[1:0]) + ); - // Test loop - always @ (posedge clk) begin - in <= in + 1; + // Test loop + always @(posedge clk) begin + in <= in + 1; `ifdef TEST_VERBOSE - $write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10); + $write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10); `endif - if (in==3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (in == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out32, out10, - // Inputs - in - ); - input [1:0] in; - output [1:0] out32; - output [1:0] out10; +module Test ( /*AUTOARG*/ + // Outputs + out32, + out10, + // Inputs + in +); + input [1:0] in; + output [1:0] out32; + output [1:0] out10; - assign out32 = in[3:2]; - assign out10 = in[1:0]; + assign out32 = in[3:2]; + assign out10 = in[1:0]; endmodule diff --git a/test_regress/t/t_select_bad_range3.out b/test_regress/t/t_select_bad_range3.out index 612b981a8..ec2ea7914 100644 --- a/test_regress/t/t_select_bad_range3.out +++ b/test_regress/t/t_select_bad_range3.out @@ -1,7 +1,7 @@ -%Warning-SELRANGE: t/t_select_bad_range3.v:19:33: Selection index out of range: 13 outside 12:10 +%Warning-SELRANGE: t/t_select_bad_range3.v:19:32: Selection index out of range: 13 outside 12:10 : ... note: In instance 't' - 19 | assign outwires[12] = inwires[13]; - | ^ + 19 | assign outwires[12] = inwires[13]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range3.v b/test_regress/t/t_select_bad_range3.v index 0933370d4..426fa4e07 100644 --- a/test_regress/t/t_select_bad_range3.v +++ b/test_regress/t/t_select_bad_range3.v @@ -4,18 +4,18 @@ // SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - outwires, - // Inputs - inwires - ); +module t ( /*AUTOARG*/ + // Outputs + outwires, + // Inputs + inwires +); - input [7:0] inwires [12:10]; - output wire [7:0] outwires [12:10]; + input [7:0] inwires[12:10]; + output wire [7:0] outwires[12:10]; - assign outwires[10] = inwires[11]; - assign outwires[11] = inwires[12]; - assign outwires[12] = inwires[13]; // must be an error here + assign outwires[10] = inwires[11]; + assign outwires[11] = inwires[12]; + assign outwires[12] = inwires[13]; // must be an error here endmodule diff --git a/test_regress/t/t_select_bad_range4.out b/test_regress/t/t_select_bad_range4.out index 81703b9f2..db1b0a86e 100644 --- a/test_regress/t/t_select_bad_range4.out +++ b/test_regress/t/t_select_bad_range4.out @@ -1,88 +1,88 @@ -%Error: t/t_select_bad_range4.v:17:8: Width of bit range is huge; vector of over 1 billion bits: 0x20000001 +%Error: t/t_select_bad_range4.v:20:7: Width of bit range is huge; vector of over 1 billion bits: 0x20000001 : ... note: In instance 't' - 17 | reg [1<<29 : 0] hugerange; - | ^ + 20 | reg [1<<29 : 0] hugerange; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_select_bad_range4.v:20:16: Width of :+ or :- is < 0: 32'hffffffff +%Error: t/t_select_bad_range4.v:23:14: Width of :+ or :- is < 0: 32'hffffffff : ... note: In instance 't' - 20 | sel2 = mi[44 +: -1]; - | ^ -%Error: t/t_select_bad_range4.v:20:16: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) + 23 | sel2 = mi[44+:-1]; + | ^ +%Error: t/t_select_bad_range4.v:23:14: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' - 20 | sel2 = mi[44 +: -1]; - | ^ -%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + 23 | sel2 = mi[44+:-1]; + | ^ +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 20 | sel2 = mi[44 +: -1]; - | ^ + 23 | sel2 = mi[44+:-1]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000 +%Error: t/t_select_bad_range4.v:24:14: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000 : ... note: In instance 't' - 21 | sel2 = mi[44 +: 1<<29]; - | ^ -%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Extracting 536870912 bits from only 6 bit number + 24 | sel2 = mi[44+:1<<29]; + | ^ +%Warning-SELRANGE: t/t_select_bad_range4.v:24:14: Extracting 536870912 bits from only 6 bit number : ... note: In instance 't' - 21 | sel2 = mi[44 +: 1<<29]; - | ^ + 24 | sel2 = mi[44+:1<<29]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Selection index out of range: 536870915:4 outside 45:40 +%Warning-SELRANGE: t/t_select_bad_range4.v:24:14: Selection index out of range: 536870915:4 outside 45:40 : ... note: In instance 't' - 21 | sel2 = mi[44 +: 1<<29]; - | ^ -%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870912 bits. + 24 | sel2 = mi[44+:1<<29]; + | ^ +%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:24:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870912 bits. : ... note: In instance 't' - 21 | sel2 = mi[44 +: 1<<29]; - | ^ + 24 | sel2 = mi[44+:1<<29]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst' +%Error: t/t_select_bad_range4.v:25:19: Expecting expression to be constant, but variable isn't const: 'nonconst' : ... note: In instance 't' - 22 | sel2 = mi[44 +: nonconst]; - | ^~~~~~~~ -%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit slice range isn't a constant + 25 | sel2 = mi[44+:nonconst]; + | ^~~~~~~~ +%Error: t/t_select_bad_range4.v:25:19: Width of :+ or :- bit slice range isn't a constant : ... note: In instance 't' - 22 | sel2 = mi[44 +: nonconst]; - | ^~~~~~~~ -%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + 25 | sel2 = mi[44+:nonconst]; + | ^~~~~~~~ +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:25:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 22 | sel2 = mi[44 +: nonconst]; - | ^ -%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:17: Operator SUB expects 32 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits. + 25 | sel2 = mi[44+:nonconst]; + | ^ +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:26:15: Operator SUB expects 32 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits. : ... note: In instance 't' - 23 | sel2 = mi[nonconst]; - | ^~~~~~~~ -%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + 26 | sel2 = mi[nonconst]; + | ^~~~~~~~ +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:26:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 23 | sel2 = mi[nonconst]; - | ^ -%Error: t/t_select_bad_range4.v:24:17: First value of [a:b] isn't a constant, maybe you want +: or -: + 26 | sel2 = mi[nonconst]; + | ^ +%Error: t/t_select_bad_range4.v:27:15: First value of [a:b] isn't a constant, maybe you want +: or -: : ... note: In instance 't' - 24 | sel2 = mi[nonconst : nonconst]; - | ^~~~~~~~ -%Error: t/t_select_bad_range4.v:24:28: Second value of [a:b] isn't a constant, maybe you want +: or -: + 27 | sel2 = mi[nonconst : nonconst]; + | ^~~~~~~~ +%Error: t/t_select_bad_range4.v:27:26: Second value of [a:b] isn't a constant, maybe you want +: or -: : ... note: In instance 't' - 24 | sel2 = mi[nonconst : nonconst]; - | ^~~~~~~~ -%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + 27 | sel2 = mi[nonconst : nonconst]; + | ^~~~~~~~ +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:27:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 24 | sel2 = mi[nonconst : nonconst]; - | ^ -%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 536870913 bits from only 6 bit number + 27 | sel2 = mi[nonconst : nonconst]; + | ^ +%Warning-SELRANGE: t/t_select_bad_range4.v:28:14: Extracting 536870913 bits from only 6 bit number : ... note: In instance 't' - 25 | sel2 = mi[1<<29 : 0]; - | ^ -%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Selection index out of range: 536870872:-40 outside 45:40 + 28 | sel2 = mi[1<<29 : 0]; + | ^ +%Warning-SELRANGE: t/t_select_bad_range4.v:28:14: Selection index out of range: 536870872:-40 outside 45:40 : ... note: In instance 't' - 25 | sel2 = mi[1<<29 : 0]; - | ^ -%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 536870913 bits from only 536870873 bit number + 28 | sel2 = mi[1<<29 : 0]; + | ^ +%Warning-SELRANGE: t/t_select_bad_range4.v:28:14: Extracting 536870913 bits from only 536870873 bit number : ... note: In instance 't' - 25 | sel2 = mi[1<<29 : 0]; - | ^ -%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870913 bits. + 28 | sel2 = mi[1<<29 : 0]; + | ^ +%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:28:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870913 bits. : ... note: In instance 't' - 25 | sel2 = mi[1<<29 : 0]; - | ^ + 28 | sel2 = mi[1<<29 : 0]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range4.v b/test_regress/t/t_select_bad_range4.v index 6429fc802..0101b0f62 100644 --- a/test_regress/t/t_select_bad_range4.v +++ b/test_regress/t/t_select_bad_range4.v @@ -4,24 +4,27 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, unk, nonconst, mi - ); - input clk; - input unk; - input nonconst; +module t ( /*AUTOARG*/ + // Inputs + clk, + unk, + nonconst, + mi +); + input clk; + input unk; + input nonconst; - input [45:40] mi; - reg [3:0] sel2; - reg [1<<29 : 0] hugerange; + input [45:40] mi; + reg [3:0] sel2; + reg [1<<29 : 0] hugerange; - always @ (posedge clk) begin - sel2 = mi[44 +: -1]; - sel2 = mi[44 +: 1<<29]; - sel2 = mi[44 +: nonconst]; - sel2 = mi[nonconst]; - sel2 = mi[nonconst : nonconst]; - sel2 = mi[1<<29 : 0]; - end + always @(posedge clk) begin + sel2 = mi[44+:-1]; + sel2 = mi[44+:1<<29]; + sel2 = mi[44+:nonconst]; + sel2 = mi[nonconst]; + sel2 = mi[nonconst : nonconst]; + sel2 = mi[1<<29 : 0]; + end endmodule diff --git a/test_regress/t/t_select_bad_range5.out b/test_regress/t/t_select_bad_range5.out index cd9f439eb..6a6d8c075 100644 --- a/test_regress/t/t_select_bad_range5.out +++ b/test_regress/t/t_select_bad_range5.out @@ -1,28 +1,28 @@ -%Error: t/t_select_bad_range5.v:16:19: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' +%Error: t/t_select_bad_range5.v:18:18: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 16 | assign mi = unk[3:2]; - | ^ + 18 | assign mi = unk[3:2]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Extracting 2 bits from only 1 bit number +%Warning-SELRANGE: t/t_select_bad_range5.v:18:18: Extracting 2 bits from only 1 bit number : ... note: In instance 't' - 16 | assign mi = unk[3:2]; - | ^ + 18 | assign mi = unk[3:2]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Selection index out of range: 3:2 outside 1:0 +%Warning-SELRANGE: t/t_select_bad_range5.v:18:18: Selection index out of range: 3:2 outside 1:0 : ... note: In instance 't' - 16 | assign mi = unk[3:2]; - | ^ -%Warning-WIDTHEXPAND: t/t_select_bad_range5.v:16:19: Bit extraction of var[3:0] requires 2 bit index, not 1 bits. + 18 | assign mi = unk[3:2]; + | ^ +%Warning-WIDTHEXPAND: t/t_select_bad_range5.v:18:18: Bit extraction of var[3:0] requires 2 bit index, not 1 bits. : ... note: In instance 't' - 16 | assign mi = unk[3:2]; - | ^ + 18 | assign mi = unk[3:2]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. +%Warning-WIDTHTRUNC: t/t_select_bad_range5.v:18:13: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. : ... note: In instance 't' - 16 | assign mi = unk[3:2]; - | ^ + 18 | assign mi = unk[3:2]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range5.v b/test_regress/t/t_select_bad_range5.v index 1ea46eb6e..c5778ba40 100644 --- a/test_regress/t/t_select_bad_range5.v +++ b/test_regress/t/t_select_bad_range5.v @@ -4,14 +4,16 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, unk, mi - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + unk, + mi +); - input clk; - input unk; - output mi; + input clk; + input unk; + output mi; - assign mi = unk[3:2]; + assign mi = unk[3:2]; endmodule diff --git a/test_regress/t/t_select_bad_range6.out b/test_regress/t/t_select_bad_range6.out index 0787be816..cb435a2ac 100644 --- a/test_regress/t/t_select_bad_range6.out +++ b/test_regress/t/t_select_bad_range6.out @@ -1,11 +1,11 @@ -%Warning-SELRANGE: t/t_select_bad_range6.v:13:16: Extracting 31 bits from only 12 bit number +%Warning-SELRANGE: t/t_select_bad_range6.v:14:15: Extracting 31 bits from only 12 bit number : ... note: In instance 't' - 13 | assign o = i[31:1]; - | ^ + 14 | assign o = i[31:1]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_range6.v:13:16: Selection index out of range: 31:1 outside 11:0 +%Warning-SELRANGE: t/t_select_bad_range6.v:14:15: Selection index out of range: 31:1 outside 11:0 : ... note: In instance 't' - 13 | assign o = i[31:1]; - | ^ + 14 | assign o = i[31:1]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range6.v b/test_regress/t/t_select_bad_range6.v index 3ddf50644..d4f2c8ed8 100644 --- a/test_regress/t/t_select_bad_range6.v +++ b/test_regress/t/t_select_bad_range6.v @@ -4,18 +4,19 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - logic [11:0] i; - logic [30:0] o; + logic [11:0] i; + logic [30:0] o; - assign o = i[31:1]; + assign o = i[31:1]; - always @(posedge clk) begin - i = 12'h123; - end - always @(negedge clk) begin - $write ("Bad select %x\n", o); - end + always @(posedge clk) begin + i = 12'h123; + end + always @(negedge clk) begin + $write("Bad select %x\n", o); + end endmodule diff --git a/test_regress/t/t_select_bad_tri.out b/test_regress/t/t_select_bad_tri.out index 856b72df0..c8921a845 100644 --- a/test_regress/t/t_select_bad_tri.out +++ b/test_regress/t/t_select_bad_tri.out @@ -1,9 +1,9 @@ -%Error: t/t_select_bad_tri.v:11:24: Selection index is constantly unknown or tristated: 1'bx - 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; - | ^ +%Error: t/t_select_bad_tri.v:11:18: Selection index is constantly unknown or tristated: 1'bx + 11 | if (in[((1'h0/1'b0))+:71] != 71'h0) $stop; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: Internal Error: t/t_select_bad_tri.v:11:24: ../V3Number.cpp:#: toUInt with 4-state 1'bx +%Error: Internal Error: t/t_select_bad_tri.v:11:18: ../V3Number.cpp:#: toUInt with 4-state 1'bx : ... note: In instance 't' - 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; - | ^ + 11 | if (in[((1'h0/1'b0))+:71] != 71'h0) $stop; + | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_select_bad_tri.v b/test_regress/t/t_select_bad_tri.v index 4ef3c2873..cdf2ba307 100644 --- a/test_regress/t/t_select_bad_tri.v +++ b/test_regress/t/t_select_bad_tri.v @@ -6,9 +6,9 @@ module t; - reg [72:1] in; - initial begin - if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; - end + reg [72:1] in; + initial begin + if (in[((1'h0/1'b0))+:71] != 71'h0) $stop; + end endmodule diff --git a/test_regress/t/t_select_bad_width0.out b/test_regress/t/t_select_bad_width0.out index bb6fd52bb..ce65d8e73 100644 --- a/test_regress/t/t_select_bad_width0.out +++ b/test_regress/t/t_select_bad_width0.out @@ -1,20 +1,20 @@ -%Error: t/t_select_bad_width0.v:15:31: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) +%Error: t/t_select_bad_width0.v:15:29: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' - 15 | automatic int part = val[left +: ZERO]; - | ^ + 15 | automatic int part = val[left+:ZERO]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. +%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:29: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 15 | automatic int part = val[left +: ZERO]; - | ^ + 15 | automatic int part = val[left+:ZERO]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Error: t/t_select_bad_width0.v:17:17: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) +%Error: t/t_select_bad_width0.v:17:15: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' - 17 | part = val[left -: ZERO]; - | ^ -%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:17:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + 17 | part = val[left-:ZERO]; + | ^ +%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:17:10: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 17 | part = val[left -: ZERO]; - | ^ + 17 | part = val[left-:ZERO]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_width0.v b/test_regress/t/t_select_bad_width0.v index ec96804a7..0db91a8c7 100644 --- a/test_regress/t/t_select_bad_width0.v +++ b/test_regress/t/t_select_bad_width0.v @@ -6,19 +6,19 @@ module t; - parameter int ZERO = 0; + parameter int ZERO = 0; - initial begin - automatic bit [31:0] val = '1; - automatic int left = 4; + initial begin + automatic bit [31:0] val = '1; + automatic int left = 4; - automatic int part = val[left +: ZERO]; - $display(part); - part = val[left -: ZERO]; - $display(part); + automatic int part = val[left+:ZERO]; + $display(part); + part = val[left-:ZERO]; + $display(part); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v index a47791fc5..732649f96 100644 --- a/test_regress/t/t_select_bound1.v +++ b/test_regress/t/t_select_bound1.v @@ -5,90 +5,91 @@ // SPDX-License-Identifier: CC0-1.0 // bug823 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [2:0] in = crc[2:0]; + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] mask; // From test of Test.v - wire [3:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - .mask (mask[3:0]), - // Inputs - .clk (clk), - .in (in[2:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[3:0]), + .mask(mask[3:0]), + // Inputs + .clk(clk), + .in(in[2:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, out & mask}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'ha9d3a7a69d2bea75 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'ha9d3a7a69d2bea75 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, mask, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + mask, + // Inputs + clk, + in +); - input clk; - input [2:0] in; - output reg [3:0] out; - output reg [3:0] mask; - localparam [15:5] P = 11'h1ac; + input clk; + input [2:0] in; + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] P = 11'h1ac; - always @(posedge clk) begin - // verilator lint_off WIDTH - out <= P[15 + in -: 5]; - // verilator lint_on WIDTH - end - always @(posedge clk) begin - mask[3] <= ((15 + in - 5) < 12); - mask[2] <= ((15 + in - 5) < 13); - mask[1] <= ((15 + in - 5) < 14); - mask[0] <= ((15 + in - 5) < 15); - end + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= P[15+in-:5]; + // verilator lint_on WIDTH + end + always @(posedge clk) begin + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end endmodule diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v index 15ceed670..13aa95809 100644 --- a/test_regress/t/t_select_bound2.v +++ b/test_regress/t/t_select_bound2.v @@ -5,88 +5,89 @@ // SPDX-License-Identifier: CC0-1.0 // bug823 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [6:0] in = crc[6:0]; + // Take CRC data and apply to testblock inputs + wire [6:0] in = crc[6:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] mask; // From test of Test.v - wire [3:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - .mask (mask[3:0]), - // Inputs - .clk (clk), - .in (in[6:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[3:0]), + .mask(mask[3:0]), + // Inputs + .clk(clk), + .in(in[6:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, out & mask}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4e9d3a74e9d3f656 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h4e9d3a74e9d3f656 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, mask, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + mask, + // Inputs + clk, + in +); - input clk; - input [6:0] in; // Note much wider than any index - output reg [3:0] out; - output reg [3:0] mask; - localparam [15:5] P = 11'h1ac; + input clk; + input [6:0] in; // Note much wider than any index + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] P = 11'h1ac; - always @(posedge clk) begin - // verilator lint_off WIDTH - out <= P[15 + in -: 5]; - // verilator lint_on WIDTH - mask[3] <= ((15 + in - 5) < 12); - mask[2] <= ((15 + in - 5) < 13); - mask[1] <= ((15 + in - 5) < 14); - mask[0] <= ((15 + in - 5) < 15); - end + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= P[15+in-:5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end endmodule diff --git a/test_regress/t/t_select_bound3.v b/test_regress/t/t_select_bound3.v index 8793aaa29..9852cae7b 100644 --- a/test_regress/t/t_select_bound3.v +++ b/test_regress/t/t_select_bound3.v @@ -7,22 +7,22 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class cls; - int m_field; + int m_field; endclass module t; - cls inst[2]; + cls inst[2]; - initial begin - // Loop (even just 1 iteration) is needed to reproduce the error - for (int i = 0; i < 2; ++i) begin - inst[i] = new(); - inst[i].m_field = i; - end - for (int i = 0; i < 2; ++i) begin - if (inst[i].m_field != i) $stop; - end - $write("*-* All Finished *-*\n"); - $finish; + initial begin + // Loop (even just 1 iteration) is needed to reproduce the error + for (int i = 0; i < 2; ++i) begin + inst[i] = new(); + inst[i].m_field = i; end + for (int i = 0; i < 2; ++i) begin + if (inst[i].m_field != i) $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_select_c.v b/test_regress/t/t_select_c.v index 225a2c980..997eef870 100644 --- a/test_regress/t/t_select_c.v +++ b/test_regress/t/t_select_c.v @@ -5,23 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 module t; - // verilator lint_off WIDTH - // verilator lint_off IMPLICIT - wire [22:0] w274; - wire w412; - wire w413; - wire w509; + // verilator lint_off WIDTH + // verilator lint_off IMPLICIT + wire [22:0] w274; + wire w412; + wire w413; + wire w509; - assign w104 = ! w509; - assign w201 = w258 > 12'hab7; - assign w204 = 7'h7f <= w104; - wire [11:0] w258 = 3'h3 || w274; - assign w538 = w412 ? out21 : w201; - wire [16:0] w539 = w413 ? w538 : 17'h00570; - wire [21:5] out21 = w204; - assign out51 = w539[0]; + assign w104 = !w509; + assign w201 = w258 > 12'hab7; + assign w204 = 7'h7f <= w104; + wire [11:0] w258 = 3'h3 || w274; + assign w538 = w412 ? out21 : w201; + wire [16:0] w539 = w413 ? w538 : 17'h00570; + wire [21:5] out21 = w204; + assign out51 = w539[0]; - initial begin - $display("%0d", out51); - end + initial begin + $display("%0d", out51); + end endmodule diff --git a/test_regress/t/t_select_crazy.v b/test_regress/t/t_select_crazy.v index 3206c006a..219ea7e6f 100644 --- a/test_regress/t/t_select_crazy.v +++ b/test_regress/t/t_select_crazy.v @@ -6,38 +6,38 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - logic a; + logic a; endinterface -function integer the_other_func (input integer val); - return val; +function integer the_other_func(input integer val); + return val; endfunction module t; - genvar the_genvar; - generate - for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop - foo foo_inst(); - end - endgenerate + genvar the_genvar; + generate + for (the_genvar = 0; the_genvar < 4; the_genvar++) begin : foo_loop + foo foo_inst (); + end + endgenerate - bar bar_inst(); + bar bar_inst (); - logic x; - assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; - //localparam N = 2; - //assign x = foo_loop[N].foo_inst.y; + logic x; + assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; + //localparam N = 2; + //assign x = foo_loop[N].foo_inst.y; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module foo(); - logic y; +module foo (); + logic y; endmodule -module bar(); - localparam THE_LP = 2; +module bar (); + localparam THE_LP = 2; endmodule diff --git a/test_regress/t/t_select_index.v b/test_regress/t/t_select_index.v index 02ea629ed..9648229e9 100644 --- a/test_regress/t/t_select_index.v +++ b/test_regress/t/t_select_index.v @@ -4,46 +4,44 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - // surefire lint_off NBAJAM + // surefire lint_off NBAJAM - input clk; - reg [7:0] _ranit; + reg [7:0] _ranit; - reg [2:0] a; - reg [7:0] vvector; - reg [7:0] vvector_flip; + reg [2:0] a; + reg [7:0] vvector; + reg [7:0] vvector_flip; - // surefire lint_off STMINI - initial _ranit = 0; + // surefire lint_off STMINI + initial _ranit = 0; - always @ (posedge clk) begin - a <= a + 3'd1; - vvector[a] <= 1'b1; // This should use "old" value for a - vvector_flip[~a] <= 1'b1; // This should use "old" value for a + always @(posedge clk) begin + a <= a + 3'd1; + vvector[a] <= 1'b1; // This should use "old" value for a + vvector_flip[~a] <= 1'b1; // This should use "old" value for a + // + //======== + if (_ranit == 8'd0) begin + _ranit <= 8'd1; + $write("[%0t] t_select_index: Running\n", $time); + vvector <= 0; + vvector_flip <= 0; + a <= 3'b1; + end + else _ranit <= _ranit + 8'd1; + // + if (_ranit == 8'd3) begin + $write("%x %x\n", vvector, vvector_flip); + if (vvector !== 8'b0000110) $stop; + if (vvector_flip !== 8'b0110_0000) $stop; // - //======== - if (_ranit==8'd0) begin - _ranit <= 8'd1; - $write("[%0t] t_select_index: Running\n", $time); - vvector <= 0; - vvector_flip <= 0; - a <= 3'b1; - end - else _ranit <= _ranit + 8'd1; - // - if (_ranit==8'd3) begin - $write("%x %x\n",vvector,vvector_flip); - if (vvector !== 8'b0000110) $stop; - if (vvector_flip !== 8'b0110_0000) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v index 16c297444..d901b86f3 100644 --- a/test_regress/t/t_select_index2.v +++ b/test_regress/t/t_select_index2.v @@ -6,28 +6,27 @@ module t; - reg [7:0] x; - wire [3:0] en; - wire sel; - wire a; + reg [7:0] x; + wire [3:0] en; + wire sel; + wire a; - // bug675 - generate - genvar g_k; - for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) - begin: g_index - always @* begin - // Note this isn't a genif, but normal if - // verilator lint_off SELRANGE - if(g_k<4) begin - x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; - end - else begin - x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; - end - // verilator lint_on SELRANGE - end + // bug675 + generate + genvar g_k; + for (g_k = 0; g_k < 8; g_k = g_k + 1) begin : g_index + always @* begin + // Note this isn't a genif, but normal if + // verilator lint_off SELRANGE + if (g_k < 4) begin + x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; end - endgenerate + else begin + x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; + end + // verilator lint_on SELRANGE + end + end + endgenerate endmodule diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v index 6dbdde4dd..3cd17521d 100644 --- a/test_regress/t/t_select_lhs_oob.v +++ b/test_regress/t/t_select_lhs_oob.v @@ -4,90 +4,89 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - reg [6:0] mem1d; - reg [6:0] mem2d [5:0]; - reg [6:0] mem3d [4:0][5:0]; + integer cyc = 0; - integer i,j,k; + reg [6:0] mem1d; + reg [6:0] mem2d[5:0]; + reg [6:0] mem3d[4:0][5:0]; - // Four different test cases for out of bounds - // = - // <= - // Continuous assigns - // Output pin interconnect (also covers cont assigns) - // Each with both bit selects and array selects + integer i, j, k; - initial begin - mem1d[0] = 1'b0; - i=7; - mem1d[i] = 1'b1; - if (mem1d[0] !== 1'b0) $stop; - // - for (i=0; i<8; i=i+1) begin - for (j=0; j<8; j=j+1) begin - for (k=0; k<8; k=k+1) begin - mem1d[k] = k[0]; - mem2d[j][k] = j[0]+k[0]; - mem3d[i][j][k] = i[0]+j[0]+k[0]; - end - end + // Four different test cases for out of bounds + // = + // <= + // Continuous assigns + // Output pin interconnect (also covers cont assigns) + // Each with both bit selects and array selects + + initial begin + mem1d[0] = 1'b0; + i = 7; + mem1d[i] = 1'b1; + if (mem1d[0] !== 1'b0) $stop; + // + for (i = 0; i < 8; i = i + 1) begin + for (j = 0; j < 8; j = j + 1) begin + for (k = 0; k < 8; k = k + 1) begin + mem1d[k] = k[0]; + mem2d[j][k] = j[0] + k[0]; + mem3d[i][j][k] = i[0] + j[0] + k[0]; + end end - for (i=0; i<5; i=i+1) begin - for (j=0; j<6; j=j+1) begin - for (k=0; k<7; k=k+1) begin - if (mem1d[k] !== k[0]) $stop; - if (mem2d[j][k] !== j[0]+k[0]) $stop; - if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; - end - end + end + for (i = 0; i < 5; i = i + 1) begin + for (j = 0; j < 6; j = j + 1) begin + for (k = 0; k < 7; k = k + 1) begin + if (mem1d[k] !== k[0]) $stop; + if (mem2d[j][k] !== j[0] + k[0]) $stop; + if (mem3d[i][j][k] !== i[0] + j[0] + k[0]) $stop; + end end - end + end + end - integer wi; - wire [31:0] wd = cyc; - reg [31:0] reg2d[6:0]; - always @ (posedge clk) reg2d[wi[2:0]] <= wd; + integer wi; + wire [31:0] wd = cyc; + reg [31:0] reg2d[6:0]; + always @(posedge clk) reg2d[wi[2:0]] <= wd; - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n", $time, cyc, wi[2:0], reg2d[wi[2:0]], wd); + $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n", $time, cyc, wi[2:0], reg2d[wi[2:0]], wd); `endif - cyc <= cyc + 1; - if (cyc<10) begin - wi <= 0; - end - else if (cyc==10) begin - wi <= 1; - end - else if (cyc==11) begin - if (reg2d[0] !== 10) $stop; - wi <= 6; - end - else if (cyc==12) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - wi <= 7; // Will be ignored - end - else if (cyc==13) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - if (reg2d[6] !== 12) $stop; - end - else if (cyc==14) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - if (reg2d[6] !== 12) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc < 10) begin + wi <= 0; + end + else if (cyc == 10) begin + wi <= 1; + end + else if (cyc == 11) begin + if (reg2d[0] !== 10) $stop; + wi <= 6; + end + else if (cyc == 12) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + wi <= 7; // Will be ignored + end + else if (cyc == 13) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc == 14) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_lhs_oob2.v b/test_regress/t/t_select_lhs_oob2.v index 2fc2f1093..aeb866c04 100644 --- a/test_regress/t/t_select_lhs_oob2.v +++ b/test_regress/t/t_select_lhs_oob2.v @@ -4,139 +4,142 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] out; // From test of Test.v + // End of automatics - wire reset_l = ~(cyc<15); - wire [63:0] d = crc[63:0]; - wire [8:0] t_wa = crc[8:0]; - wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; + wire reset_l = ~(cyc < 15); + wire [63:0] d = crc[63:0]; + wire [8:0] t_wa = crc[8:0]; + wire [8:0] t_addr = {crc[18:17], 3'b0, crc[13:10]}; - Test test (/*AUTOINST*/ - // Outputs - .out (out[63:0]), - // Inputs - .clk (clk), - .reset_l (reset_l), - .t_wa (t_wa[8:0]), - .d (d[63:0]), - .t_addr (t_addr[8:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[63:0]), + // Inputs + .clk(clk), + .reset_l(reset_l), + .t_wa(t_wa[8:0]), + .d(d[63:0]), + .t_addr(t_addr[8:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h421a41d1541ea652 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h421a41d1541ea652 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, reset_l, t_wa, d, t_addr - ); - input clk; - input reset_l; +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + reset_l, + t_wa, + d, + t_addr +); + input clk; + input reset_l; - reg [63:0] m_w0 [47:0]; - reg [63:0] m_w1 [23:0]; - reg [63:0] m_w2 [23:0]; - reg [63:0] m_w3 [23:0]; - reg [63:0] m_w4 [23:0]; - reg [63:0] m_w5 [23:0]; + reg [63:0] m_w0[47:0]; + reg [63:0] m_w1[23:0]; + reg [63:0] m_w2[23:0]; + reg [63:0] m_w3[23:0]; + reg [63:0] m_w4[23:0]; + reg [63:0] m_w5[23:0]; - input [8:0] t_wa; - input [63:0] d; + input [8:0] t_wa; + input [63:0] d; - always @ (posedge clk) begin - if (~reset_l) begin : blk - integer i; + always @(posedge clk) begin + if (~reset_l) begin : blk + integer i; - for (i=0; i<48; i=i+1) begin - m_w0[i] <= 64'h0; - end - - for (i=0; i<24; i=i+1) begin - m_w1[i] <= 64'h0; - m_w2[i] <= 64'h0; - m_w3[i] <= 64'h0; - m_w4[i] <= 64'h0; - m_w5[i] <= 64'h0; - end + for (i = 0; i < 48; i = i + 1) begin + m_w0[i] <= 64'h0; end - else begin - casez (t_wa[8:6]) - 3'd0: m_w0[t_wa[5:0]] <= d; - 3'd1: m_w1[t_wa[4:0]] <= d; - 3'd2: m_w2[t_wa[4:0]] <= d; - 3'd3: m_w3[t_wa[4:0]] <= d; - 3'd4: m_w4[t_wa[4:0]] <= d; - default: m_w5[t_wa[4:0]] <= d; - endcase + + for (i = 0; i < 24; i = i + 1) begin + m_w1[i] <= 64'h0; + m_w2[i] <= 64'h0; + m_w3[i] <= 64'h0; + m_w4[i] <= 64'h0; + m_w5[i] <= 64'h0; end - end - - input [8:0] t_addr; - - wire [63:0] t_w0 = m_w0[t_addr[5:0]]; - wire [63:0] t_w1 = m_w1[t_addr[4:0]]; - wire [63:0] t_w2 = m_w2[t_addr[4:0]]; - wire [63:0] t_w3 = m_w3[t_addr[4:0]]; - wire [63:0] t_w4 = m_w4[t_addr[4:0]]; - wire [63:0] t_w5 = m_w5[t_addr[4:0]]; - - output reg [63:0] out; - always @* begin - casez (t_addr[8:6]) - 3'd0: out = t_w0; - 3'd1: out = t_w1; - 3'd2: out = t_w2; - 3'd3: out = t_w3; - 3'd4: out = t_w4; - default: out = t_w5; + end + else begin + casez (t_wa[8:6]) + 3'd0: m_w0[t_wa[5:0]] <= d; + 3'd1: m_w1[t_wa[4:0]] <= d; + 3'd2: m_w2[t_wa[4:0]] <= d; + 3'd3: m_w3[t_wa[4:0]] <= d; + 3'd4: m_w4[t_wa[4:0]] <= d; + default: m_w5[t_wa[4:0]] <= d; endcase - end + end + end + + input [8:0] t_addr; + + wire [63:0] t_w0 = m_w0[t_addr[5:0]]; + wire [63:0] t_w1 = m_w1[t_addr[4:0]]; + wire [63:0] t_w2 = m_w2[t_addr[4:0]]; + wire [63:0] t_w3 = m_w3[t_addr[4:0]]; + wire [63:0] t_w4 = m_w4[t_addr[4:0]]; + wire [63:0] t_w5 = m_w5[t_addr[4:0]]; + + output reg [63:0] out; + always @* begin + casez (t_addr[8:6]) + 3'd0: out = t_w0; + 3'd1: out = t_w1; + 3'd2: out = t_w2; + 3'd3: out = t_w3; + 3'd4: out = t_w4; + default: out = t_w5; + endcase + end endmodule diff --git a/test_regress/t/t_select_little.v b/test_regress/t/t_select_little.v index 993f001a7..107f42940 100644 --- a/test_regress/t/t_select_little.v +++ b/test_regress/t/t_select_little.v @@ -4,72 +4,71 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // verilator lint_off LITENDIAN - wire [10:41] sel2 = crc[31:0]; - wire [10:100] sel3 = {crc[26:0],crc}; + // verilator lint_off LITENDIAN + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0], crc}; - wire out20 = sel2[{1'b0,crc[3:0]} + 11]; - wire [3:0] out21 = sel2[13 : 16]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + wire out20 = sel2[{1'b0, crc[3:0]}+11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0, crc[3:0]}+20+:4]; + wire [3:0] out23 = sel2[{1'b0, crc[3:0]}+20-:4]; - wire out30 = sel3[{2'b0,crc[3:0]} + 11]; - wire [3:0] out31 = sel3[13 : 16]; - wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + wire out30 = sel3[{2'b0, crc[3:0]}+11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0]+20+:4]; + wire [3:0] out33 = sel3[crc[5:0]+20-:4]; - // Aggregate outputs into a single result vector - wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + // Aggregate outputs into a single result vector + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; - reg [19:50] sel1; - initial begin - // Path clearing - // 122333445 - // 826048260 - sel1 = 32'h12345678; - if (sel1 != 32'h12345678) $stop; - if (sel1[47 : 50] != 4'h8) $stop; - if (sel1[31 : 34] != 4'h4) $stop; - if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] - if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] - end + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[47 : 50] != 4'h8) $stop; + if (sel1[31 : 34] != 4'h4) $stop; + if (sel1[27+:4] != 4'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26-:4] != 4'h2) $stop; //==[23:26], in memory as [27:24] + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20, out21, out22, out23, out30, out31, + out32, out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h28bf65439eb12c00 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h28bf65439eb12c00 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_little_pack.v b/test_regress/t/t_select_little_pack.v index 94b876604..ce1a333d2 100644 --- a/test_regress/t/t_select_little_pack.v +++ b/test_regress/t/t_select_little_pack.v @@ -6,20 +6,20 @@ module t; - // No ascending range warning here - reg [7:0] pack [3:0]; + // No ascending range warning here + reg [7:0] pack[3:0]; - initial begin - pack[0] = 8'h78; - pack[1] = 8'h88; - pack[2] = 8'h98; - pack[3] = 8'hA8; - if (pack[0] !== 8'h78) $stop; - if (pack[1] !== 8'h88) $stop; - if (pack[2] !== 8'h98) $stop; - if (pack[3] !== 8'hA8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + pack[0] = 8'h78; + pack[1] = 8'h88; + pack[2] = 8'h98; + pack[3] = 8'hA8; + if (pack[0] !== 8'h78) $stop; + if (pack[1] !== 8'h88) $stop; + if (pack[2] !== 8'h98) $stop; + if (pack[3] !== 8'hA8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_select_loop.v b/test_regress/t/t_select_loop.v index c04dddbf1..144ca770f 100644 --- a/test_regress/t/t_select_loop.v +++ b/test_regress/t/t_select_loop.v @@ -4,52 +4,51 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [255:0] a; - reg [255:0] q; - reg [63:0] qq; + reg [255:0] a; + reg [255:0] q; + reg [63:0] qq; - integer i; - always @* begin - for (i=0; i<256; i=i+1) begin - q[255-i] = a[i]; - end - q[27:16] = 12'hfed; - for (i=0; i<64; i=i+1) begin - qq[63-i] = a[i]; - end - qq[27:16] = 12'hfed; - end + integer i; + always @* begin + for (i = 0; i < 256; i = i + 1) begin + q[255-i] = a[i]; + end + q[27:16] = 12'hfed; + for (i = 0; i < 64; i = i + 1) begin + qq[63-i] = a[i]; + end + qq[27:16] = 12'hfed; + end - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x/%x %x\n", q, qq, a); + $write("%x/%x %x\n", q, qq, a); `endif - if (cyc==1) begin - a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - end - if (cyc==2) begin - a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; - if (qq != 64'h64fe7e285fed892e) $stop; - end - if (cyc==3) begin - if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; - if (qq != 64'h1da9cf939fed1250) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 1) begin + a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end - end + if (cyc == 2) begin + a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; + if (qq != 64'h64fe7e285fed892e) $stop; + end + if (cyc == 3) begin + if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; + if (qq != 64'h1da9cf939fed1250) $stop; + end + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_select_mul_extend.v b/test_regress/t/t_select_mul_extend.v index ebb042404..f7a0e8179 100644 --- a/test_regress/t/t_select_mul_extend.v +++ b/test_regress/t/t_select_mul_extend.v @@ -5,108 +5,108 @@ // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test(/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); - Test2 test2(/*AUTOINST*/ - // Inputs - .clk (clk)); + Test2 test2(/*AUTOINST*/ + // Inputs + .clk (clk)); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); + $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); + // Outputs + out, + // Inputs + clk, in + ); - input clk; - input [31:0] in; - output reg [31:0] out; + input clk; + input [31:0] in; + output reg [31:0] out; - logic [31:0] cnt = 0; - logic [7:0][30:0] q; - logic cond = 0; + logic [31:0] cnt = 0; + logic [7:0][30:0] q; + logic cond = 0; - always_comb begin - for (int i = 0; i < 8; i++) begin - if (i == (cond ? (2-cnt)%8 : 0)) begin - q[i] = 31'(in); - end - else begin - q[i] = '0; - end + always_comb begin + for (int i = 0; i < 8; i++) begin + if (i == (cond ? (2-cnt)%8 : 0)) begin + q[i] = 31'(in); end - end + else begin + q[i] = '0; + end + end + end - always @(posedge clk) begin - cnt <= cnt + 1; - cond <= ~cond; - out <= {in[31], q[cond ? (3'd2 - cnt[2:0]) : 3'd0]}; - end + always @(posedge clk) begin + cnt <= cnt + 1; + cond <= ~cond; + out <= {in[31], q[cond ? (3'd2 - cnt[2:0]) : 3'd0]}; + end endmodule module Test2(input wire clk); - reg [127:1][7:0] arrayu; - reg [6:0] index = 0; - wire logic [7:0] selectedu = arrayu[index]; - always @(posedge clk) begin - index <= index + 1; - if (index == 2) $display(selectedu); - end + reg [127:1][7:0] arrayu; + reg [6:0] index = 0; + wire logic [7:0] selectedu = arrayu[index]; + always @(posedge clk) begin + index <= index + 1; + if (index == 2) $display(selectedu); + end endmodule diff --git a/test_regress/t/t_select_negative.v b/test_regress/t/t_select_negative.v index 3ca4c5617..520ab58dd 100644 --- a/test_regress/t/t_select_negative.v +++ b/test_regress/t/t_select_negative.v @@ -4,67 +4,65 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [15:-16] sel2 = crc[31:0]; - wire [80:-10] sel3 = {crc[26:0],crc}; + wire [15:-16] sel2 = crc[31:0]; + wire [80:-10] sel3 = {crc[26:0], crc}; - wire [3:0] out21 = sel2[-3 : -6]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; + wire [3:0] out21 = sel2[-3 :-6]; + wire [3:0] out22 = sel2[{1'b0, crc[3:0]}-16+:4]; + wire [3:0] out23 = sel2[{1'b0, crc[3:0]}-10-:4]; - wire [3:0] out31 = sel3[-3 : -6]; - wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; + wire [3:0] out31 = sel3[-3 :-6]; + wire [3:0] out32 = sel3[crc[5:0]-6+:4]; + wire [3:0] out33 = sel3[crc[5:0]-6-:4]; - // Aggregate outputs into a single result vector - wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; + // Aggregate outputs into a single result vector + wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; - reg [15:-16] sel1; - initial begin - // Path clearing - sel1 = 32'h12345678; - if (sel1 != 32'h12345678) $stop; - if (sel1[-13 : -16] != 4'h8) $stop; - if (sel1[3:0] != 4'h4) $stop; - if (sel1[4 +: 4] != 4'h3) $stop; - if (sel1[11 -: 4] != 4'h2) $stop; - end + reg [15:-16] sel1; + initial begin + // Path clearing + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[-13 :-16] != 4'h8) $stop; + if (sel1[3:0] != 4'h4) $stop; + if (sel1[4+:4] != 4'h3) $stop; + if (sel1[11-:4] != 4'h2) $stop; + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21,out22,out23, out31,out32,out33); - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21, out22, out23, out31, out32, out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'hba7fe1e7ac128362 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'hba7fe1e7ac128362 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_out_of_range.v b/test_regress/t/t_select_out_of_range.v index 25a7ec6c0..5e3608694 100644 --- a/test_regress/t/t_select_out_of_range.v +++ b/test_regress/t/t_select_out_of_range.v @@ -4,22 +4,24 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module serial_adder( - input cin, - output cout +module serial_adder ( + input cin, + output cout ); - localparam WIDTH = 8; + localparam WIDTH = 8; - wire [WIDTH:0] c; + wire [WIDTH:0] c; - generate for (genvar i = 0; i < WIDTH; i++) - full_adder fa(c[i+1]); - endgenerate + generate + for (genvar i = 0; i < WIDTH; i++) full_adder fa (c[i+1]); + endgenerate - assign c[0] = cin; - assign cout = c[WIDTH+1]; // intentional out-of-range + assign c[0] = cin; + assign cout = c[WIDTH+1]; // intentional out-of-range endmodule -module full_adder (output cout); +module full_adder ( + output cout +); endmodule diff --git a/test_regress/t/t_select_param.v b/test_regress/t/t_select_param.v index b849d1ae7..eb9fa5fa9 100644 --- a/test_regress/t/t_select_param.v +++ b/test_regress/t/t_select_param.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - parameter [ BMSB : BLSB ] B = A[23:20]; // 3 - parameter A = 32'h12345678; - parameter BLSB = A[16+:4]; // 4 - parameter BMSB = A[7:4]; // 7 + parameter [BMSB : BLSB] B = A[23:20]; // 3 + parameter A = 32'h12345678; + parameter BLSB = A[16+:4]; // 4 + parameter BMSB = A[7:4]; // 7 - initial begin - if (B !== 4'h3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (B !== 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index 61c061f0b..f3a6eb474 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -4,89 +4,88 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [83:4] from; + reg [83:4] to; + reg [6:0] bitn; + reg [3:0] nibblep; + reg [3:0] nibblem; - reg [83:4] from; - reg [83:4] to; - reg [6:0] bitn; - reg [3:0] nibblep; - reg [3:0] nibblem; + reg [7:0] cyc; + initial cyc = 0; - reg [7:0] cyc; initial cyc = 0; + always @* begin + nibblep = from[bitn+:4]; + nibblem = from[bitn-:4]; + to = from; + to[bitn+:4] = cyc[3:0]; + to[bitn-:4] = cyc[3:0]; + end - always @* begin - nibblep = from[bitn +: 4]; - nibblem = from[bitn -: 4]; - to = from; - to[bitn +: 4] = cyc[3:0]; - to[bitn -: 4] = cyc[3:0]; - end + // verilog_format: off + always @ (posedge clk) begin + //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end + 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end + 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: + 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end + 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: + 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc + 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc + 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end + 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate + 8'd09: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end + 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end + 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end + 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end + 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + default: $stop; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end + 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end + 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end + 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end + 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 + 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 + 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end + 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end + 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end + default: $stop; + endcase + end - always @ (posedge clk) begin - //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to); - cyc <= cyc + 8'd1; - case (cyc) - 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end - 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end - 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: - 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end - 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: - 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc - 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc - 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end - 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate - 8'd09: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - case (cyc) - 8'd00: ; - 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end - 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end - 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end - 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end - 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end - 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end - 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - default: $stop; - endcase - case (cyc) - 8'd00: ; - 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end - 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end - 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end - 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end - 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 - 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 - 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end - 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end - 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end - default: $stop; - endcase - end + // Additional constant folding check - this used to trigger a bug + reg [23:0] a; + reg [3:0] b; - // Additional constant folding check - this used to trigger a bug - reg [23:0] a; - reg [3:0] b; + initial begin + a = 24'd0; + b = 4'b0111; + a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits + if (a != 24'b11100000_00000000_00000000) $stop; - initial begin - a = 24'd0; - b = 4'b0111; - a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits - if (a != 24'b11100000_00000000_00000000) $stop; - - a = 24'd0; - b = 4'b0110; - a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits - if (a != 24'b00000111_00000000_00000000) $stop; - end + a = 24'd0; + b = 4'b0110; + a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits + if (a != 24'b00000111_00000000_00000000) $stop; + end endmodule diff --git a/test_regress/t/t_select_plus_mul_pow2.v b/test_regress/t/t_select_plus_mul_pow2.v index c04f7303a..397257be9 100644 --- a/test_regress/t/t_select_plus_mul_pow2.v +++ b/test_regress/t/t_select_plus_mul_pow2.v @@ -4,51 +4,50 @@ // SPDX-FileCopyrightText: 2020 Conor McCullough // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [63:0] from = 64'h0706050403020100; + reg [7:0] to; + reg [2:0] bitn; + reg [7:0] cyc; + initial cyc = 0; - reg [63:0] from = 64'h0706050403020100; - reg [7:0] to; - reg [2:0] bitn; - reg [7:0] cyc; initial cyc = 0; + always @* begin + to = from[bitn*8+:8]; + end - always @* begin - to = from[bitn * 8 +: 8]; - end - - always @ (posedge clk) begin - cyc <= cyc + 8'd1; - case (cyc) - 8'd00: begin bitn<=3'd0; end - 8'd01: begin bitn<=3'd1; end - 8'd02: begin bitn<=3'd2; end - 8'd03: begin bitn<=3'd3; end - 8'd04: begin bitn<=3'd4; end - 8'd05: begin bitn<=3'd5; end - 8'd06: begin bitn<=3'd6; end - 8'd07: begin bitn<=3'd7; end - 8'd08: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - case (cyc) - 8'd00: ; - 8'd01: begin if (to !== 8'h00) $stop; end - 8'd02: begin if (to !== 8'h01) $stop; end - 8'd03: begin if (to !== 8'h02) $stop; end - 8'd04: begin if (to !== 8'h03) $stop; end - 8'd05: begin if (to !== 8'h04) $stop; end - 8'd06: begin if (to !== 8'h05) $stop; end - 8'd07: begin if (to !== 8'h06) $stop; end - 8'd08: begin if (to !== 8'h07) $stop; end - default: $stop; - endcase - end + // verilog_format: off + always @ (posedge clk) begin + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin bitn <= 3'd0; end + 8'd01: begin bitn <= 3'd1; end + 8'd02: begin bitn <= 3'd2; end + 8'd03: begin bitn <= 3'd3; end + 8'd04: begin bitn <= 3'd4; end + 8'd05: begin bitn <= 3'd5; end + 8'd06: begin bitn <= 3'd6; end + 8'd07: begin bitn <= 3'd7; end + 8'd08: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if (to !== 8'h00) $stop; end + 8'd02: begin if (to !== 8'h01) $stop; end + 8'd03: begin if (to !== 8'h02) $stop; end + 8'd04: begin if (to !== 8'h03) $stop; end + 8'd05: begin if (to !== 8'h04) $stop; end + 8'd06: begin if (to !== 8'h05) $stop; end + 8'd07: begin if (to !== 8'h06) $stop; end + 8'd08: begin if (to !== 8'h07) $stop; end + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v index 16635a82d..15987a62a 100644 --- a/test_regress/t/t_select_plusloop.v +++ b/test_regress/t/t_select_plusloop.v @@ -4,64 +4,68 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [31:0] narrow; + reg [63:0] quad; + reg [127:0] wide; - reg [31:0] narrow; - reg [63:0] quad; - reg [127:0] wide; + integer cyc; + initial cyc = 0; + reg [7:0] crc; + reg [6:0] index; - integer cyc; initial cyc = 0; - reg [7:0] crc; - reg [6:0] index; - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b n=%x\n", $time, cyc, crc, narrow); - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - narrow <= 32'h0; - quad <= 64'h0; - wide <= 128'h0; - crc <= 8'hed; - index <= 7'h0; - end - else if (cyc<90) begin - index <= index + 7'h2; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - // verilator lint_off WIDTH - if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; - if (index < 9'd60) quad [index +: 3] <= crc[2:0]; - if (index < 9'd120) wide [index +: 3] <= crc[2:0]; - // - narrow[index[3:0]] <= ~narrow[index[3:0]]; - quad [~index[3:0]]<= ~quad [~index[3:0]]; - wide [~index[3:0]] <= ~wide [~index[3:0]]; - // verilator lint_on WIDTH - end - else if (cyc==90) begin - wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; - wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; - wide[82 +: 4] <=4'h6; - end - else if (cyc==91) begin - wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; - wide[41] <=1'b1; quad[41] <=1'b1; - wide[81] <=1'b1; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide); - if (crc != 8'b01111001) $stop; - if (narrow != 32'h001661c7) $stop; - if (quad != 64'h16d49b6f64266039) $stop; - if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b n=%x\n", $time, cyc, crc, narrow); + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + narrow <= 32'h0; + quad <= 64'h0; + wide <= 128'h0; + crc <= 8'hed; + index <= 7'h0; + end + else if (cyc < 90) begin + index <= index + 7'h2; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + // verilator lint_off WIDTH + if (index < 9'd20) narrow[index+:3] <= crc[2:0]; + if (index < 9'd60) quad[index+:3] <= crc[2:0]; + if (index < 9'd120) wide[index+:3] <= crc[2:0]; + // + narrow[index[3:0]] <= ~narrow[index[3:0]]; + quad[~index[3:0]] <= ~quad[~index[3:0]]; + wide[~index[3:0]] <= ~wide[~index[3:0]]; + // verilator lint_on WIDTH + end + else if (cyc == 90) begin + wide[12+:4] <= 4'h6; + quad[12+:4] <= 4'h6; + narrow[12+:4] <= 4'h6; + wide[42+:4] <= 4'h6; + quad[42+:4] <= 4'h6; + wide[82+:4] <= 4'h6; + end + else if (cyc == 91) begin + wide[0] <= 1'b1; + quad[0] <= 1'b1; + narrow[0] <= 1'b1; + wide[41] <= 1'b1; + quad[41] <= 1'b1; + wide[81] <= 1'b1; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide); + if (crc != 8'b01111001) $stop; + if (narrow != 32'h001661c7) $stop; + if (quad != 64'h16d49b6f64266039) $stop; + if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v index 07a7a73a2..c01c0d380 100644 --- a/test_regress/t/t_select_runtime_range.v +++ b/test_regress/t/t_select_runtime_range.v @@ -4,73 +4,75 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - reg [43:0] mi; - reg [5:0] index; - integer indexi; - reg read; + reg [43:0] mi; + reg [5:0] index; + integer indexi; + reg read; - initial begin - // Static - mi = 44'b01010101010101010101010101010101010101010101; - if (mi[0] !== 1'b1) $stop; - if (mi[1 -: 2] !== 2'b01) $stop; + initial begin + // Static + mi = 44'b01010101010101010101010101010101010101010101; + if (mi[0] !== 1'b1) $stop; + if (mi[1-:2] !== 2'b01) $stop; `ifdef VERILATOR - // verilator lint_off SELRANGE - if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; - if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop; - if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop; - // verilator lint_on SELRANGE + // verilator lint_off SELRANGE + if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; + if (mi[0-:2] !== 2'b1x && 1'b0) $stop; + if (mi[-1-:2] !== 2'bxx && 1'b0) $stop; + // verilator lint_on SELRANGE `else - if (mi[-1] !== 1'bx) $stop; - if (mi[0 -: 2] !== 2'b1x) $stop; - if (mi[-1 -: 2] !== 2'bxx) $stop; + if (mi[-1] !== 1'bx) $stop; + if (mi[0-:2] !== 2'b1x) $stop; + if (mi[-1-:2] !== 2'bxx) $stop; `endif - end + end - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - mi = 44'h123; - end - if (cyc==2) begin - index = 6'd43; - indexi = 43; - end - if (cyc==3) begin - read = mi[index]; - if (read!==1'b0) $stop; - read = mi[indexi]; - if (read!==1'b0) $stop; - end - if (cyc==4) begin - index = 6'd44; - indexi = 44; - end - if (cyc==5) begin - read = mi[index]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - read = mi[indexi]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - end - if (cyc==6) begin - indexi = -1; - end - if (cyc==7) begin - read = mi[indexi]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + mi = 44'h123; end - end + if (cyc == 2) begin + index = 6'd43; + indexi = 43; + end + if (cyc == 3) begin + read = mi[index]; + if (read !== 1'b0) $stop; + read = mi[indexi]; + if (read !== 1'b0) $stop; + end + if (cyc == 4) begin + index = 6'd44; + indexi = 44; + end + if (cyc == 5) begin + read = mi[index]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + read = mi[indexi]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc == 6) begin + indexi = -1; + end + if (cyc == 7) begin + read = mi[indexi]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_select_set.v b/test_regress/t/t_select_set.v index 0523790f3..cd3f67aaa 100644 --- a/test_regress/t/t_select_set.v +++ b/test_regress/t/t_select_set.v @@ -4,47 +4,49 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - reg [63:0] inwide; - reg [39:0] addr; + reg [63:0] inwide; + reg [39:0] addr; - integer cyc; initial cyc=1; - always @ (posedge clk) begin + integer cyc; + initial cyc = 1; + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("%x %x\n", cyc, addr); + $write("%x %x\n", cyc, addr); `endif - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - addr <= 40'h12_3456_7890; - end - if (cyc==2) begin - if (addr !== 40'h1234567890) $stop; - addr[31:0] <= 32'habcd_efaa; - end - if (cyc==3) begin - if (addr !== 40'h12abcdefaa) $stop; - addr[39:32] <= 8'h44; - inwide <= 64'hffeeddcc_11334466; - end - if (cyc==4) begin - if (addr !== 40'h44abcdefaa) $stop; - addr[31:0] <= inwide[31:0]; - end - if (cyc==5) begin - if (addr !== 40'h4411334466) $stop; - $display ("Flip [%x]\n", inwide[3:0]); - addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; - end - if (cyc==6) begin - if (addr !== 40'h4411334426) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + addr <= 40'h12_3456_7890; end - end + if (cyc == 2) begin + if (addr !== 40'h1234567890) $stop; + addr[31:0] <= 32'habcd_efaa; + end + if (cyc == 3) begin + if (addr !== 40'h12abcdefaa) $stop; + addr[39:32] <= 8'h44; + inwide <= 64'hffeeddcc_11334466; + end + if (cyc == 4) begin + if (addr !== 40'h44abcdefaa) $stop; + addr[31:0] <= inwide[31:0]; + end + if (cyc == 5) begin + if (addr !== 40'h4411334466) $stop; + $display("Flip [%x]\n", inwide[3:0]); + addr[{2'b0, inwide[3:0]}] <= !addr[{2'b0, inwide[3:0]}]; + end + if (cyc == 6) begin + if (addr !== 40'h4411334426) $stop; + end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_select_width.v b/test_regress/t/t_select_width.v index 8bf086724..6fc9d6ddc 100644 --- a/test_regress/t/t_select_width.v +++ b/test_regress/t/t_select_width.v @@ -4,24 +4,25 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - vlan, - // Inputs - clk, pkt_data - ); +module t ( /*AUTOARG*/ + // Outputs + vlan, + // Inputs + clk, + pkt_data +); - parameter WIDTH = 320; - input clk; - input [2559:0] pkt_data; - output reg [15:0] vlan; + parameter WIDTH = 320; + input clk; + input [2559:0] pkt_data; + output reg [15:0] vlan; - always @(posedge clk) begin - // verilator lint_off WIDTHCONCAT - // verilator lint_off WIDTHTRUNC - vlan <= pkt_data[ { (WIDTH-12), 3'b0 } - 1 -: 16]; - // verilator lint_on WIDTHCONCAT - // verilator lint_on WIDTHTRUNC - end + always @(posedge clk) begin + // verilator lint_off WIDTHCONCAT + // verilator lint_off WIDTHTRUNC + vlan <= pkt_data[{(WIDTH-12), 3'b0}-1-:16]; + // verilator lint_on WIDTHCONCAT + // verilator lint_on WIDTHTRUNC + end endmodule diff --git a/test_regress/t/t_semaphore.v b/test_regress/t/t_semaphore.v index 283b2f7a7..1281d2918 100644 --- a/test_regress/t/t_semaphore.v +++ b/test_regress/t/t_semaphore.v @@ -13,49 +13,49 @@ // endclass `ifndef SEMAPHORE_T - `define SEMAPHORE_T semaphore +`define SEMAPHORE_T semaphore `endif // verilator lint_off DECLFILENAME module t; - // From UVM: - `SEMAPHORE_T s; - `SEMAPHORE_T s2; + // From UVM: + `SEMAPHORE_T s; + `SEMAPHORE_T s2; - initial begin - s = new(1); - if (s.try_get() == 0) $stop; - if (s.try_get() != 0) $stop; + initial begin + s = new(1); + if (s.try_get() == 0) $stop; + if (s.try_get() != 0) $stop; - s = new; - if (s.try_get() != 0) $stop; + s = new; + if (s.try_get() != 0) $stop; - s.put(); - s.get(); + s.put(); + s.get(); - s.put(2); - s.get(2); + s.put(2); + s.get(2); - s.put(2); - if (s.try_get(2) <= 0) $stop; + s.put(2); + if (s.try_get(2) <= 0) $stop; - fork - begin - #10; // So later then get() starts below - s.put(1); - s.put(1); - end - begin - if (s.try_get(1) != 0) $stop; - s.get(); // Blocks until put - s.get(); - end - join + fork + begin + #10; // So later then get() starts below + s.put(1); + s.put(1); + end + begin + if (s.try_get(1) != 0) $stop; + s.get(); // Blocks until put + s.get(); + end + join - s2 = new; - if (s2.try_get() != 0) $stop; + s2 = new; + if (s2.try_get() != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_semaphore_always.v b/test_regress/t/t_semaphore_always.v index 4de6f7079..e2d28e7ef 100644 --- a/test_regress/t/t_semaphore_always.v +++ b/test_regress/t/t_semaphore_always.v @@ -4,20 +4,19 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - semaphore s = new; +module t ( + input clk +); - initial begin - s.put(); - end + semaphore s = new; - always @(posedge clk) begin - s.get(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + s.put(); + end + + always @(posedge clk) begin + s.get(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_semaphore_bad.out b/test_regress/t/t_semaphore_bad.out index 6e0cdae8d..2c467deeb 100644 --- a/test_regress/t/t_semaphore_bad.out +++ b/test_regress/t/t_semaphore_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_semaphore_bad.v:12:13: Class method 'bad_method' not found in class 'semaphore' +%Error: t/t_semaphore_bad.v:12:11: Class method 'bad_method' not found in class 'semaphore' : ... note: In instance 't' - 12 | if (s.bad_method() != 0) $stop; - | ^~~~~~~~~~ + 12 | if (s.bad_method() != 0) $stop; + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_semaphore_bad.v b/test_regress/t/t_semaphore_bad.v index 2e9dc917b..509e814e1 100644 --- a/test_regress/t/t_semaphore_bad.v +++ b/test_regress/t/t_semaphore_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - semaphore s; + semaphore s; - initial begin - s = new(4); - if (s.bad_method() != 0) $stop; + initial begin + s = new(4); + if (s.bad_method() != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_semaphore_concurrent.v b/test_regress/t/t_semaphore_concurrent.v index 56342859c..f9e47b399 100644 --- a/test_regress/t/t_semaphore_concurrent.v +++ b/test_regress/t/t_semaphore_concurrent.v @@ -5,30 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 module t; - semaphore s; + semaphore s; - // Stand-in for a task that should only be run by one thread at a time - task automatic exclusive_task; - $display("%0t", $time); - #1; - endtask + // Stand-in for a task that should only be run by one thread at a time + task automatic exclusive_task; + $display("%0t", $time); + #1; + endtask - task automatic call_exclusive_task; - s.get(1); - exclusive_task(); - s.put(1); - endtask + task automatic call_exclusive_task; + s.get(1); + exclusive_task(); + s.put(1); + endtask - initial begin - s = new(1); - fork - call_exclusive_task(); - call_exclusive_task(); - call_exclusive_task(); - call_exclusive_task(); - join + initial begin + s = new(1); + fork + call_exclusive_task(); + call_exclusive_task(); + call_exclusive_task(); + call_exclusive_task(); + join - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sequence_first_match_unsup.out b/test_regress/t/t_sequence_first_match_unsup.out index 1ccf94aca..a64703292 100644 --- a/test_regress/t/t_sequence_first_match_unsup.out +++ b/test_regress/t/t_sequence_first_match_unsup.out @@ -1,20 +1,20 @@ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:40: Unsupported: or (in sequence expression) - 50 | initial p0: assert property ((##1 1) or (##2 1) |-> x==1); - | ^~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:51:41: Unsupported: or (in sequence expression) + 51 | initial p0 : assert property ((##1 1) or(##2 1) |-> x == 1); + | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:52: Unsupported: or (in sequence expression) - 53 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); - | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:32: Unsupported: first_match (in sequence expression) - 53 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:34: Unsupported: or (in sequence expression) - 56 | initial p2: assert property (1 or ##1 1 |-> x==0); - | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:59:46: Unsupported: or (in sequence expression) - 59 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); - | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:59:32: Unsupported: first_match (in sequence expression) - 59 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); - | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:54:54: Unsupported: or (in sequence expression) + 54 | initial p1 : assert property (first_match ((##1 1) or(##2 1)) |-> x == 1); + | ^~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:54:33: Unsupported: first_match (in sequence expression) + 54 | initial p1 : assert property (first_match ((##1 1) or(##2 1)) |-> x == 1); + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:57:35: Unsupported: or (in sequence expression) + 57 | initial p2 : assert property (1 or ##1 1 |-> x == 0); + | ^~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:60:48: Unsupported: or (in sequence expression) + 60 | initial p3 : assert property (first_match (1 or ##1 1) |-> x == 0); + | ^~ +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:60:33: Unsupported: first_match (in sequence expression) + 60 | initial p3 : assert property (first_match (1 or ##1 1) |-> x == 0); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sequence_first_match_unsup.v b/test_regress/t/t_sequence_first_match_unsup.v index 5658fc05a..5f4d08838 100644 --- a/test_regress/t/t_sequence_first_match_unsup.v +++ b/test_regress/t/t_sequence_first_match_unsup.v @@ -36,26 +36,27 @@ // - homepage : https://www.cprover.org/ebmc/ // - source repository : https://github.com/diffblue/hw-cbmc -module main(input clk); +module main ( + input clk +); reg [31:0] x = 0; - always @(posedge clk) - x<=x+1; + always @(posedge clk) x <= x + 1; // Starting from a particular state, // first_match yields the sequence that _ends_ first. // fails - initial p0: assert property ((##1 1) or (##2 1) |-> x==1); + initial p0 : assert property ((##1 1) or(##2 1) |-> x == 1); // passes - initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); + initial p1 : assert property (first_match ((##1 1) or(##2 1)) |-> x == 1); // fails - initial p2: assert property (1 or ##1 1 |-> x==0); + initial p2 : assert property (1 or ##1 1 |-> x == 0); // passes - initial p3: assert property (first_match(1 or ##1 1) |-> x==0); + initial p3 : assert property (first_match (1 or ##1 1) |-> x == 0); endmodule diff --git a/test_regress/t/t_sequence_sexpr_unsup.out b/test_regress/t/t_sequence_sexpr_unsup.out index a6c63030e..fdd39486f 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.out +++ b/test_regress/t/t_sequence_sexpr_unsup.out @@ -1,184 +1,184 @@ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:13: Unsupported: sequence - 27 | sequence s_a; - | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:25:12: Unsupported: sequence + 25 | sequence s_a; + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:13: Unsupported: sequence - 30 | sequence s_var; - | ^~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:36:9: Unsupported: within (in sequence expression) - 36 | a within(b); - | ^~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:13: Unsupported: sequence - 35 | sequence s_within; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:40:9: Unsupported: and (in sequence expression) - 40 | a and b; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:13: Unsupported: sequence - 39 | sequence s_and; - | ^~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:44:9: Unsupported: or (in sequence expression) - 44 | a or b; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:13: Unsupported: sequence - 43 | sequence s_or; - | ^~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:48:9: Unsupported: throughout (in sequence expression) - 48 | a throughout b; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:13: Unsupported: sequence - 47 | sequence s_throughout; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:52:9: Unsupported: intersect (in sequence expression) - 52 | a intersect b; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:13: Unsupported: sequence - 51 | sequence s_intersect; - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:13: Unsupported: sequence - 55 | sequence s_uni_cycdelay_id; - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:13: Unsupported: sequence - 58 | sequence s_uni_cycdelay_pid; - | ^~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:7: Unsupported: ## range cycle delay range expression - 62 | ## [1:2] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:28:12: Unsupported: sequence + 28 | sequence s_var; + | ^~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:34:7: Unsupported: within (in sequence expression) + 34 | a within(b); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:33:12: Unsupported: sequence + 33 | sequence s_within; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:38:7: Unsupported: and (in sequence expression) + 38 | a and b; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:37:12: Unsupported: sequence + 37 | sequence s_and; + | ^~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:42:7: Unsupported: or (in sequence expression) + 42 | a or b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:13: Unsupported: sequence - 61 | sequence s_uni_cycdelay_range; - | ^~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:65:7: Unsupported: ## [*] cycle delay range expression - 65 | ## [*] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:41:12: Unsupported: sequence + 41 | sequence s_or; + | ^~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:46:7: Unsupported: throughout (in sequence expression) + 46 | a throughout b; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:45:12: Unsupported: sequence + 45 | sequence s_throughout; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:50:7: Unsupported: intersect (in sequence expression) + 50 | a intersect b; + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:49:12: Unsupported: sequence + 49 | sequence s_intersect; + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:53:12: Unsupported: sequence + 53 | sequence s_uni_cycdelay_id; + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:56:12: Unsupported: sequence + 56 | sequence s_uni_cycdelay_pid; + | ^~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:60:5: Unsupported: ## range cycle delay range expression + 60 | ## [1:2] b; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:59:12: Unsupported: sequence + 59 | sequence s_uni_cycdelay_range; + | ^~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:63:5: Unsupported: ## [*] cycle delay range expression + 63 | ## [*] b; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:12: Unsupported: sequence + 62 | sequence s_uni_cycdelay_star; + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:66:5: Unsupported: ## [+] cycle delay range expression + 66 | ## [+] b; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:65:12: Unsupported: sequence + 65 | sequence s_uni_cycdelay_plus; + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:69:12: Unsupported: sequence + 69 | sequence s_cycdelay_id; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:72:12: Unsupported: sequence + 72 | sequence s_cycdelay_pid; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:76:7: Unsupported: ## range cycle delay range expression + 76 | a ## [1:2] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:13: Unsupported: sequence - 64 | sequence s_uni_cycdelay_star; - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:68:7: Unsupported: ## [+] cycle delay range expression - 68 | ## [+] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:75:12: Unsupported: sequence + 75 | sequence s_cycdelay_range; + | ^~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:79:7: Unsupported: ## [*] cycle delay range expression + 79 | a ## [*] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:13: Unsupported: sequence - 67 | sequence s_uni_cycdelay_plus; - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:13: Unsupported: sequence - 71 | sequence s_cycdelay_id; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:13: Unsupported: sequence - 74 | sequence s_cycdelay_pid; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:9: Unsupported: ## range cycle delay range expression - 78 | a ## [1:2] b; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:13: Unsupported: sequence - 77 | sequence s_cycdelay_range; - | ^~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:9: Unsupported: ## [*] cycle delay range expression - 81 | a ## [*] b; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:13: Unsupported: sequence - 80 | sequence s_cycdelay_star; - | ^~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:84:9: Unsupported: ## [+] cycle delay range expression - 84 | a ## [+] b; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:13: Unsupported: sequence - 83 | sequence s_cycdelay_plus; - | ^~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:9: Unsupported: [*] boolean abbrev expression - 88 | a [* 1 ]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:12: Unsupported: boolean abbrev (in sequence expression) - 88 | a [* 1 ]; - | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:13: Unsupported: sequence - 87 | sequence s_booleanabbrev_brastar_int; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: [*] boolean abbrev expression - 91 | a [*]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: boolean abbrev (in sequence expression) - 91 | a [*]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:13: Unsupported: sequence - 90 | sequence s_booleanabbrev_brastar; - | ^~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: [+] boolean abbrev expression - 94 | a [+]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: boolean abbrev (in sequence expression) - 94 | a [+]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:13: Unsupported: sequence - 93 | sequence s_booleanabbrev_plus; - | ^~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: [= boolean abbrev expression - 97 | a [= 1]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:12: Unsupported: boolean abbrev (in sequence expression) - 97 | a [= 1]; - | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:13: Unsupported: sequence - 96 | sequence s_booleanabbrev_eq; - | ^~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [= boolean abbrev expression - 100 | a [= 1:2]; - | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: boolean abbrev (in sequence expression) - 100 | a [= 1:2]; - | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:13: Unsupported: sequence - 99 | sequence s_booleanabbrev_eq_range; - | ^~~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [-> boolean abbrev expression - 103 | a [-> 1]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:13: Unsupported: boolean abbrev (in sequence expression) - 103 | a [-> 1]; - | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:13: Unsupported: sequence - 102 | sequence s_booleanabbrev_minusgt; - | ^~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:9: Unsupported: [-> boolean abbrev expression - 106 | a [-> 1:2]; - | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:13: Unsupported: boolean abbrev (in sequence expression) - 106 | a [-> 1:2]; - | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:13: Unsupported: sequence - 105 | sequence s_booleanabbrev_minusgt_range; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:27: Unsupported: sequence argument data type - 109 | sequence p_arg_seqence(sequence inseq); - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:13: Unsupported: sequence - 109 | sequence p_arg_seqence(sequence inseq); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:7: Unsupported: first_match (in sequence expression) - 114 | first_match (a); - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:113:13: Unsupported: sequence - 113 | sequence s_firstmatch_a; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:117:7: Unsupported: first_match (in sequence expression) - 117 | first_match (a, res0 = 1); - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:13: Unsupported: sequence - 116 | sequence s_firstmatch_ab; - | ^~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:120:7: Unsupported: first_match (in sequence expression) - 120 | first_match (a, res0 = 1, res1 = 2); - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:13: Unsupported: sequence - 119 | sequence s_firstmatch_abc; - | ^~~~~~~~~~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:10: Ignoring unsupported: cover sequence - 123 | cover sequence (s_a) $display(""); - | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:12: Unsupported: sequence + 78 | sequence s_cycdelay_star; + | ^~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:82:7: Unsupported: ## [+] cycle delay range expression + 82 | a ## [+] b; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:12: Unsupported: sequence + 81 | sequence s_cycdelay_plus; + | ^~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:86:7: Unsupported: [*] boolean abbrev expression + 86 | a [* 1 ]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:86:10: Unsupported: boolean abbrev (in sequence expression) + 86 | a [* 1 ]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:85:12: Unsupported: sequence + 85 | sequence s_booleanabbrev_brastar_int; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: [*] boolean abbrev expression + 89 | a [*]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: boolean abbrev (in sequence expression) + 89 | a [*]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:12: Unsupported: sequence + 88 | sequence s_booleanabbrev_brastar; + | ^~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: [+] boolean abbrev expression + 92 | a [+]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: boolean abbrev (in sequence expression) + 92 | a [+]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:12: Unsupported: sequence + 91 | sequence s_booleanabbrev_plus; + | ^~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:7: Unsupported: [= boolean abbrev expression + 95 | a [= 1]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:10: Unsupported: boolean abbrev (in sequence expression) + 95 | a [= 1]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:12: Unsupported: sequence + 94 | sequence s_booleanabbrev_eq; + | ^~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:7: Unsupported: [= boolean abbrev expression + 98 | a [= 1:2]; + | ^~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:10: Unsupported: boolean abbrev (in sequence expression) + 98 | a [= 1:2]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:12: Unsupported: sequence + 97 | sequence s_booleanabbrev_eq_range; + | ^~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:101:7: Unsupported: [-> boolean abbrev expression + 101 | a [-> 1]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:101:11: Unsupported: boolean abbrev (in sequence expression) + 101 | a [-> 1]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: sequence + 100 | sequence s_booleanabbrev_minusgt; + | ^~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:104:7: Unsupported: [-> boolean abbrev expression + 104 | a [-> 1:2]; + | ^~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:104:11: Unsupported: boolean abbrev (in sequence expression) + 104 | a [-> 1:2]; + | ^ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:12: Unsupported: sequence + 103 | sequence s_booleanabbrev_minusgt_range; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:107:26: Unsupported: sequence argument data type + 107 | sequence p_arg_seqence(sequence inseq); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:107:12: Unsupported: sequence + 107 | sequence p_arg_seqence(sequence inseq); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:5: Unsupported: first_match (in sequence expression) + 112 | first_match (a); + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:111:12: Unsupported: sequence + 111 | sequence s_firstmatch_a; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:5: Unsupported: first_match (in sequence expression) + 115 | first_match (a, res0 = 1); + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:12: Unsupported: sequence + 114 | sequence s_firstmatch_ab; + | ^~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:118:5: Unsupported: first_match (in sequence expression) + 118 | first_match (a, res0 = 1, res1 = 2); + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:117:12: Unsupported: sequence + 117 | sequence s_firstmatch_abc; + | ^~~~~~~~~~~~~~~~ +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:121:9: Ignoring unsupported: cover sequence + 121 | cover sequence (s_a) $display(""); + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:124:10: Ignoring unsupported: cover sequence - 124 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); - | ^~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:125:10: Ignoring unsupported: cover sequence - 125 | cover sequence (disable iff (b) s_a) $display(""); - | ^~~~~~~~ +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:122:9: Ignoring unsupported: cover sequence + 122 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); + | ^~~~~~~~ +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:9: Ignoring unsupported: cover sequence + 123 | cover sequence (disable iff (b) s_a) $display(""); + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sequence_sexpr_unsup.v b/test_regress/t/t_sequence_sexpr_unsup.v index 263800142..eac565574 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.v +++ b/test_regress/t/t_sequence_sexpr_unsup.v @@ -4,130 +4,128 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int a; - int b; - int cyc = 0; - int res0, res1; + int a; + int b; + int cyc = 0; + int res0, res1; - localparam DELAY = 1; + localparam DELAY = 1; - always @(posedge clk) begin - cyc <= cyc + 1; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end - // NOTE this grammar hasn't been checked with other simulators, - // is here just to avoid uncovered code lines in the grammar. - // NOTE using 'property weak' here as sequence/endsequence not supported - sequence s_a; - a; - endsequence : s_a - sequence s_var; - logic l1, l2; - a; - endsequence + // NOTE this grammar hasn't been checked with other simulators, + // is here just to avoid uncovered code lines in the grammar. + // NOTE using 'property weak' here as sequence/endsequence not supported + sequence s_a; + a; + endsequence : s_a + sequence s_var; + logic l1, l2; + a; + endsequence - sequence s_within; - a within(b); - endsequence + sequence s_within; + a within(b); + endsequence - sequence s_and; - a and b; - endsequence + sequence s_and; + a and b; + endsequence - sequence s_or; - a or b; - endsequence + sequence s_or; + a or b; + endsequence - sequence s_throughout; - a throughout b; - endsequence + sequence s_throughout; + a throughout b; + endsequence - sequence s_intersect; - a intersect b; - endsequence + sequence s_intersect; + a intersect b; + endsequence - sequence s_uni_cycdelay_id; - ## DELAY b; - endsequence - sequence s_uni_cycdelay_pid; - ## ( DELAY ) b; - endsequence - sequence s_uni_cycdelay_range; - ## [1:2] b; - endsequence - sequence s_uni_cycdelay_star; - ## [*] b; - endsequence - sequence s_uni_cycdelay_plus; - ## [+] b; - endsequence + sequence s_uni_cycdelay_id; + ## DELAY b; + endsequence + sequence s_uni_cycdelay_pid; + ## ( DELAY ) b; + endsequence + sequence s_uni_cycdelay_range; + ## [1:2] b; + endsequence + sequence s_uni_cycdelay_star; + ## [*] b; + endsequence + sequence s_uni_cycdelay_plus; + ## [+] b; + endsequence - sequence s_cycdelay_id; - a ## DELAY b; - endsequence - sequence s_cycdelay_pid; - a ## ( DELAY ) b; - endsequence - sequence s_cycdelay_range; - a ## [1:2] b; - endsequence - sequence s_cycdelay_star; - a ## [*] b; - endsequence - sequence s_cycdelay_plus; - a ## [+] b; - endsequence + sequence s_cycdelay_id; + a ## DELAY b; + endsequence + sequence s_cycdelay_pid; + a ## ( DELAY ) b; + endsequence + sequence s_cycdelay_range; + a ## [1:2] b; + endsequence + sequence s_cycdelay_star; + a ## [*] b; + endsequence + sequence s_cycdelay_plus; + a ## [+] b; + endsequence - sequence s_booleanabbrev_brastar_int; - a [* 1 ]; - endsequence - sequence s_booleanabbrev_brastar; - a [*]; - endsequence - sequence s_booleanabbrev_plus; - a [+]; - endsequence - sequence s_booleanabbrev_eq; - a [= 1]; - endsequence - sequence s_booleanabbrev_eq_range; - a [= 1:2]; - endsequence - sequence s_booleanabbrev_minusgt; - a [-> 1]; - endsequence - sequence s_booleanabbrev_minusgt_range; - a [-> 1:2]; - endsequence + sequence s_booleanabbrev_brastar_int; + a [* 1 ]; + endsequence + sequence s_booleanabbrev_brastar; + a [*]; + endsequence + sequence s_booleanabbrev_plus; + a [+]; + endsequence + sequence s_booleanabbrev_eq; + a [= 1]; + endsequence + sequence s_booleanabbrev_eq_range; + a [= 1:2]; + endsequence + sequence s_booleanabbrev_minusgt; + a [-> 1]; + endsequence + sequence s_booleanabbrev_minusgt_range; + a [-> 1:2]; + endsequence - sequence p_arg_seqence(sequence inseq); - inseq; - endsequence + sequence p_arg_seqence(sequence inseq); + inseq; + endsequence - sequence s_firstmatch_a; - first_match (a); - endsequence - sequence s_firstmatch_ab; - first_match (a, res0 = 1); - endsequence - sequence s_firstmatch_abc; - first_match (a, res0 = 1, res1 = 2); - endsequence + sequence s_firstmatch_a; + first_match (a); + endsequence + sequence s_firstmatch_ab; + first_match (a, res0 = 1); + endsequence + sequence s_firstmatch_abc; + first_match (a, res0 = 1, res1 = 2); + endsequence - cover sequence (s_a) $display(""); - cover sequence (@(posedge a) disable iff (b) s_a) $display(""); - cover sequence (disable iff (b) s_a) $display(""); + cover sequence (s_a) $display(""); + cover sequence (@(posedge a) disable iff (b) s_a) $display(""); + cover sequence (disable iff (b) s_a) $display(""); - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_setuphold.v b/test_regress/t/t_setuphold.v index a7bb81aee..1ffce42ac 100644 --- a/test_regress/t/t_setuphold.v +++ b/test_regress/t/t_setuphold.v @@ -5,80 +5,80 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk, - d, - t_in - ); + // Inputs + clk, + d, + t_in + ); - input clk; - input d; - input t_in; - wire delayed_CLK; - wire delayed_D; - reg notifier; - wire [1:0] BL_X = 2'b11; - wire [5:0] BL_X2; - wire BL_0; - wire [3:0] BL_1 = 4'b1100; - wire fake_CLK; - wire fake_D; + input clk; + input d; + input t_in; + wire delayed_CLK; + wire delayed_D; + reg notifier; + wire [1:0] BL_X = 2'b11; + wire [5:0] BL_X2; + wire BL_0; + wire [3:0] BL_1 = 4'b1100; + wire fake_CLK; + wire fake_D; - logic[3:0] sh1 = 1; - logic[3:0] sh2 = 2; - logic[3:0] sh3 = 3; - logic[3:0] sh4 = 4; - logic[3:0] sh5 = 5; - logic[3:0] sh6 = 6; + logic[3:0] sh1 = 1; + logic[3:0] sh2 = 2; + logic[3:0] sh3 = 3; + logic[3:0] sh4 = 4; + logic[3:0] sh5 = 5; + logic[3:0] sh6 = 6; - int cyc = 0; + int cyc = 0; - specify - $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, delayed_CLK, delayed_D); - $setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4); - $setuphold (posedge sh5, negedge d, 0, 0, notifier,,, sh6); - $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3), (0:0:0)); - $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3)); - $setuphold (posedge clk, negedge d, 0, 0, notifier); - $setuphold (posedge clk, negedge d, 0, 0); - $setuphold (posedge clk, negedge d, 0, 0); - $setuphold (posedge clk, negedge d, (0:0:0), (0:0:0)); - $setuphold (posedge clk, negedge d, 0:0:0, 0:0:0); - $setuphold (posedge clk, negedge d, 0, 0,,,,,); + specify + $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, delayed_CLK, delayed_D); + $setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4); + $setuphold (posedge sh5, negedge d, 0, 0, notifier,,, sh6); + $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3), (0:0:0)); + $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3)); + $setuphold (posedge clk, negedge d, 0, 0, notifier); + $setuphold (posedge clk, negedge d, 0, 0); + $setuphold (posedge clk, negedge d, 0, 0); + $setuphold (posedge clk, negedge d, (0:0:0), (0:0:0)); + $setuphold (posedge clk, negedge d, 0:0:0, 0:0:0); + $setuphold (posedge clk, negedge d, 0, 0,,,,,); - $setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0); - $setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]); + $setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0); + $setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]); - $setuphold (fake_CLK, fake_D &&& sh1, 0, 0); - $setuphold (posedge fake_CLK, posedge fake_D &&& sh1, 0, 0); - $setuphold (negedge fake_CLK, negedge fake_D &&& sh1, 0, 0); - $setuphold (edge fake_CLK, edge fake_D &&& sh1, 0, 0); - $setuphold (edge [0Z, z1, 10] fake_CLK, edge [01, x0, 0X] fake_CLK &&& sh1, 0, 0); + $setuphold (fake_CLK, fake_D &&& sh1, 0, 0); + $setuphold (posedge fake_CLK, posedge fake_D &&& sh1, 0, 0); + $setuphold (negedge fake_CLK, negedge fake_D &&& sh1, 0, 0); + $setuphold (edge fake_CLK, edge fake_D &&& sh1, 0, 0); + $setuphold (edge [0Z, z1, 10] fake_CLK, edge [01, x0, 0X] fake_CLK &&& sh1, 0, 0); - $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, t_in); - endspecify + $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, t_in); + endspecify - initial begin - if (sh1 != sh2 || sh3 != sh4) begin - $stop; - end - if (sh5 != sh6) begin - $stop; - end - if (BL_0 != BL_X[0] || BL_1 != BL_X2[4:1]) begin - $stop; - end - end + initial begin + if (sh1 != sh2 || sh3 != sh4) begin + $stop; + end + if (sh5 != sh6) begin + $stop; + end + if (BL_0 != BL_X[0] || BL_1 != BL_X2[4:1]) begin + $stop; + end + end - always @(posedge clk) begin - cyc <= cyc + 1; - $display("%d %d", clk, delayed_CLK); - if (delayed_CLK != clk || delayed_D != d) begin - $stop; - end - if (cyc == 10) begin - $display("*-* All Finished *-*"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + $display("%d %d", clk, delayed_CLK); + if (delayed_CLK != clk || delayed_D != d) begin + $stop; + end + if (cyc == 10) begin + $display("*-* All Finished *-*"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_slice_cmp.v b/test_regress/t/t_slice_cmp.v index 1f12f0a81..43857e26a 100644 --- a/test_regress/t/t_slice_cmp.v +++ b/test_regress/t/t_slice_cmp.v @@ -6,22 +6,20 @@ module t; - bit a [5:0]; - bit b [5:0]; + bit a[5:0]; + bit b[5:0]; - initial begin - a = '{1, 1, 1, 0, 0, 0}; - b = '{0, 0, 0, 1, 1, 1}; - $display(":assert: ('%b%b%b_%b%b%b' == '111_000')", - a[5], a[4], a[3], a[2], a[1], a[0]); - $display(":assert: ('%b%b%b_%b%b%b' == '000_111')", - b[5], b[4], b[3], b[2], b[1], b[0]); + initial begin + a = '{1, 1, 1, 0, 0, 0}; + b = '{0, 0, 0, 1, 1, 1}; + $display(":assert: ('%b%b%b_%b%b%b' == '111_000')", a[5], a[4], a[3], a[2], a[1], a[0]); + $display(":assert: ('%b%b%b_%b%b%b' == '000_111')", b[5], b[4], b[3], b[2], b[1], b[0]); - if ((a[5:3] == b[2:0]) != 1'b1) $stop; - if ((a[5:3] != b[2:0]) != 1'b0) $stop; + if ((a[5:3] == b[2:0]) != 1'b1) $stop; + if ((a[5:3] != b[2:0]) != 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_slice_cond.v b/test_regress/t/t_slice_cond.v index a94a00732..67068f550 100644 --- a/test_regress/t/t_slice_cond.v +++ b/test_regress/t/t_slice_cond.v @@ -4,36 +4,36 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - dataout, - // Inputs - clk, sel, d0, d1 - ); +module t ( /*AUTOARG*/ + // Outputs + dataout, + // Inputs + clk, + sel, + d0, + d1 +); - input clk; - input sel; + input clk; + input sel; - logic [7:0] data [1:0][3:0]; - input [7:0] d0, d1; + logic [7:0] data[1:0][3:0]; + input [7:0] d0, d1; - output wire [8*2*4-1:0] dataout; + output wire [8*2*4-1:0] dataout; - always_comb begin - for ( integer j = 0; j <= 1; j++ ) begin - if (sel) - data[j] = '{ d0, d1, 8'h00, 8'h00 }; - else - data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; - end - for ( integer j = 0; j <= 1; j++ ) begin - data[j] = sel - ? '{ d0, d1, 8'h00, 8'h00 } - : '{ 8'h00, 8'h00, 8'h00, 8'h00 }; - end - end + always_comb begin + for (integer j = 0; j <= 1; j++) begin + if (sel) data[j] = '{d0, d1, 8'h00, 8'h00}; + else data[j] = '{8'h00, 8'h00, 8'h00, 8'h00}; + end + for (integer j = 0; j <= 1; j++) begin + data[j] = sel ? '{d0, d1, 8'h00, 8'h00} : '{8'h00, 8'h00, 8'h00, 8'h00}; + end + end - assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3], - data[1][0], data[1][1], data[1][2], data[1][3]}; + assign dataout = { + data[0][0], data[0][1], data[0][2], data[0][3], data[1][0], data[1][1], data[1][2], data[1][3] + }; endmodule diff --git a/test_regress/t/t_slice_cond_2d_side_effect.v b/test_regress/t/t_slice_cond_2d_side_effect.v index 56e7b2276..a29407702 100644 --- a/test_regress/t/t_slice_cond_2d_side_effect.v +++ b/test_regress/t/t_slice_cond_2d_side_effect.v @@ -7,30 +7,32 @@ typedef int arr_t[5][3]; class Cls; - int cnt; - int init_depth; - function arr_t get_arr(int depth); - arr_t arr = (depth > 1) ? get_arr(depth - 1) : '{5{'{init_depth, init_depth * 2, init_depth * 3}}}; - cnt++; - return arr; - endfunction + int cnt; + int init_depth; + function arr_t get_arr(int depth); + arr_t arr = (depth > 1) ? get_arr( + depth - 1 + ) : '{5{'{init_depth, init_depth * 2, init_depth * 3}}}; + cnt++; + return arr; + endfunction endclass module t; - Cls c = new; - initial begin - arr_t arr; - c.init_depth = 5; - arr = (c.init_depth > 0) ? c.get_arr(5) : '{5{'{1, 2, 3}}}; + Cls c = new; + initial begin + arr_t arr; + c.init_depth = 5; + arr = (c.init_depth > 0) ? c.get_arr(5) : '{5{'{1, 2, 3}}}; - if (arr[0][0] != 5) $stop; - if (arr[0][1] != 10) $stop; - if (arr[0][2] != 15) $stop; - if (arr[3][2] != 15) $stop; + if (arr[0][0] != 5) $stop; + if (arr[0][1] != 10) $stop; + if (arr[0][2] != 15) $stop; + if (arr[3][2] != 15) $stop; - if (c.cnt != 5) $stop; + if (c.cnt != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_slice_cond_side_effect.v b/test_regress/t/t_slice_cond_side_effect.v index 107ed0997..d68388e0a 100644 --- a/test_regress/t/t_slice_cond_side_effect.v +++ b/test_regress/t/t_slice_cond_side_effect.v @@ -7,29 +7,29 @@ typedef int arr_t[3]; class Cls; - int cnt; - int init_depth; - function arr_t get_arr(int depth); - arr_t arr = (depth > 1) ? get_arr(depth - 1) : '{init_depth, init_depth * 2, init_depth * 3}; - cnt++; - return arr; - endfunction + int cnt; + int init_depth; + function arr_t get_arr(int depth); + arr_t arr = (depth > 1) ? get_arr(depth - 1) : '{init_depth, init_depth * 2, init_depth * 3}; + cnt++; + return arr; + endfunction endclass module t; - Cls c = new; - initial begin - arr_t arr; - c.init_depth = 5; - arr = (c.init_depth > 0) ? c.get_arr(5) : '{1, 2, 3}; + Cls c = new; + initial begin + arr_t arr; + c.init_depth = 5; + arr = (c.init_depth > 0) ? c.get_arr(5) : '{1, 2, 3}; - if (arr[0] != 5) $stop; - if (arr[1] != 10) $stop; - if (arr[2] != 15) $stop; + if (arr[0] != 5) $stop; + if (arr[1] != 10) $stop; + if (arr[2] != 15) $stop; - if (c.cnt != 5) $stop; + if (c.cnt != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_slice_init.v b/test_regress/t/t_slice_init.v index 5e7942f3f..eee5e943b 100644 --- a/test_regress/t/t_slice_init.v +++ b/test_regress/t/t_slice_init.v @@ -4,57 +4,55 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, d0, d1 - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + d0, + d1 +); - input clk; - input [7:0] d0, d1; + input clk; + input [7:0] d0, d1; - logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, - '{ '1, '1, 8'h11, 8'h22 }}; - logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, - '{ '1, '1, 8'h11, 8'h22 }}; + logic [7:0] inia[1:0][3:0] = '{'{'0, '1, 8'hfe, 8'hed}, '{'1, '1, 8'h11, 8'h22}}; + logic [7:0] inil[0:1][0:3] = '{'{'0, '1, 8'hfe, 8'hed}, '{'1, '1, 8'h11, 8'h22}}; - logic [7:0] data [1:0][3:0]; - logic [7:0] datl [0:1][0:3]; + logic [7:0] data[1:0][3:0]; + logic [7:0] datl[0:1][0:3]; - initial begin - data = '{ '{ d0, d1, 8'hfe, 8'hed }, - '{ d1, d1, 8'h11, 8'h22 }}; - data[0] = '{ d0, d1, 8'h19, 8'h39 }; + initial begin + data = '{'{d0, d1, 8'hfe, 8'hed}, '{d1, d1, 8'h11, 8'h22}}; + data[0] = '{d0, d1, 8'h19, 8'h39}; - datl = '{ '{ d0, d1, 8'hfe, 8'hed }, - '{ d1, d1, 8'h11, 8'h22 }}; - datl[0] = '{ d0, d1, 8'h19, 8'h39 }; + datl = '{'{d0, d1, 8'hfe, 8'hed}, '{d1, d1, 8'h11, 8'h22}}; + datl[0] = '{d0, d1, 8'h19, 8'h39}; `ifdef TEST_VERBOSE - $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); - $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); - $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); - $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); + $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); + $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); + $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); + $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); `endif - if (inia[0][0] !== 8'h22) $stop; - if (inia[0][1] !== 8'h11) $stop; - if (inia[1][0] !== 8'hed) $stop; - if (inia[1][1] !== 8'hfe) $stop; + if (inia[0][0] !== 8'h22) $stop; + if (inia[0][1] !== 8'h11) $stop; + if (inia[1][0] !== 8'hed) $stop; + if (inia[1][1] !== 8'hfe) $stop; - if (inil[0][2] !== 8'hfe) $stop; - if (inil[0][3] !== 8'hed) $stop; - if (inil[1][2] !== 8'h11) $stop; - if (inil[1][3] !== 8'h22) $stop; + if (inil[0][2] !== 8'hfe) $stop; + if (inil[0][3] !== 8'hed) $stop; + if (inil[1][2] !== 8'h11) $stop; + if (inil[1][3] !== 8'h22) $stop; - if (data[0][0] !== 8'h39) $stop; - if (data[0][1] !== 8'h19) $stop; - if (data[1][0] !== 8'hed) $stop; - if (data[1][1] !== 8'hfe) $stop; + if (data[0][0] !== 8'h39) $stop; + if (data[0][1] !== 8'h19) $stop; + if (data[1][0] !== 8'hed) $stop; + if (data[1][1] !== 8'hfe) $stop; - if (datl[0][2] !== 8'h19) $stop; - if (datl[0][3] !== 8'h39) $stop; - if (datl[1][2] !== 8'h11) $stop; - if (datl[1][3] !== 8'h22) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (datl[0][2] !== 8'h19) $stop; + if (datl[0][3] !== 8'h39) $stop; + if (datl[1][2] !== 8'h11) $stop; + if (datl[1][3] !== 8'h22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v index dddde330b..d395867c1 100644 --- a/test_regress/t/t_split_var_0.v +++ b/test_regress/t/t_split_var_0.v @@ -7,408 +7,408 @@ // If split_var pragma is removed, UNOPTFLAT appears. module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out /*verilator split_var*/); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out /*verilator split_var*/); - localparam OFFSET = -3; + localparam OFFSET = -3; `ifdef TEST_ATTRIBUTES - logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; + logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; `else - logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; + logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; `endif - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - if (shift[i]) begin - /*verilator lint_off ALWCOMBORDER*/ - tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; - /*verilator lint_on ALWCOMBORDER*/ - end - else begin - tmp[i+1+OFFSET] = tmp[i+OFFSET]; - end - end - endgenerate - assign tmp[0+OFFSET] = in; - assign out[WIDTH-1-:WIDTH-1] = tmp[DEPTH+OFFSET][WIDTH-1:1]; - assign out[0] = tmp[DEPTH+OFFSET][0+:1]; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always_comb + if (shift[i]) begin + /*verilator lint_off ALWCOMBORDER*/ + tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; + /*verilator lint_on ALWCOMBORDER*/ + end + else begin + tmp[i+1+OFFSET] = tmp[i+OFFSET]; + end + end + endgenerate + assign tmp[0+OFFSET] = in; + assign out[WIDTH-1-:WIDTH-1] = tmp[DEPTH+OFFSET][WIDTH-1:1]; + assign out[0] = tmp[DEPTH+OFFSET][0+:1]; endmodule module barshift_1d_unpacked_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = -3; - // almost same as above module, but tmp[smaller:bigger] here. - logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET] /*verilator split_var*/; - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - if (shift[i]) begin - /*verilator lint_off ALWCOMBORDER*/ - tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; - /*verilator lint_on ALWCOMBORDER*/ - end - else begin - tmp[i+1+OFFSET] = tmp[i+OFFSET]; - end - end - endgenerate - assign tmp[0+OFFSET] = in; - assign out = tmp[DEPTH+OFFSET]; + localparam OFFSET = -3; + // almost same as above module, but tmp[smaller:bigger] here. + logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET] /*verilator split_var*/; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always_comb + if (shift[i]) begin + /*verilator lint_off ALWCOMBORDER*/ + tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; + /*verilator lint_on ALWCOMBORDER*/ + end + else begin + tmp[i+1+OFFSET] = tmp[i+OFFSET]; + end + end + endgenerate + assign tmp[0+OFFSET] = in; + assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_unpacked_struct0 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = 1; - typedef struct packed { logic [WIDTH-1:0] data; } data_type; - data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - if (shift[i]) begin - /*verilator lint_off ALWCOMBORDER*/ - tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; - /*verilator lint_on ALWCOMBORDER*/ - end - else begin - tmp[i+1+OFFSET] = tmp[i+OFFSET]; - end - end - endgenerate - assign tmp[0+OFFSET] = in; - assign out = tmp[DEPTH+OFFSET]; + localparam OFFSET = 1; + typedef struct packed { logic [WIDTH-1:0] data; } data_type; + data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always_comb + if (shift[i]) begin + /*verilator lint_off ALWCOMBORDER*/ + tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; + /*verilator lint_on ALWCOMBORDER*/ + end + else begin + tmp[i+1+OFFSET] = tmp[i+OFFSET]; + end + end + endgenerate + assign tmp[0+OFFSET] = in; + assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = 1; - localparam N = 3; - reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; - reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; - reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + localparam OFFSET = 1; + localparam N = 3; + reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; + reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; + reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar, - // UNOPTFLAT appears, but it's fine. - /*verilator lint_off UNOPTFLAT*/ - reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; - /*verilator lint_on UNOPTFLAT*/ - reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar, + // UNOPTFLAT appears, but it's fine. + /*verilator lint_off UNOPTFLAT*/ + reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; + /*verilator lint_on UNOPTFLAT*/ + reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; + reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; - generate - for(genvar i = 0; i < DEPTH; ++i) begin - for(genvar j = OFFSET; j < N + OFFSET; ++j) begin - always_comb - if (shift[i]) begin - /*verilator lint_off ALWCOMBORDER*/ - tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]}; - /*verilator lint_on ALWCOMBORDER*/ - end - else begin - tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j]; - end - end - end + generate + for(genvar i = 0; i < DEPTH; ++i) begin for(genvar j = OFFSET; j < N + OFFSET; ++j) begin - assign tmp0[0 + OFFSET][j] = in; + always_comb + if (shift[i]) begin + /*verilator lint_off ALWCOMBORDER*/ + tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]}; + /*verilator lint_on ALWCOMBORDER*/ + end + else begin + tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j]; + end end - endgenerate - assign tmp1 = tmp0; // split both side - assign tmp2 = tmp1; // split only rhs - assign tmp3 = tmp2; // split only lhs - always_comb tmp4 = tmp3; // split both side - always_comb tmp5 = tmp4; // split only rhs - always_comb tmp6 = tmp5; // split only lhs + end + for(genvar j = OFFSET; j < N + OFFSET; ++j) begin + assign tmp0[0 + OFFSET][j] = in; + end + endgenerate + assign tmp1 = tmp0; // split both side + assign tmp2 = tmp1; // split only rhs + assign tmp3 = tmp2; // split only lhs + always_comb tmp4 = tmp3; // split both side + always_comb tmp5 = tmp4; // split only rhs + always_comb tmp6 = tmp5; // split only lhs - assign tmp7 = tmp6; - assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7; - assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1]; - assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3]; - assign tmp11[1] = tmp10; - assign tmp11[-1] = tmp11[1]; - assign tmp11[0] = tmp11[-1]; - assign tmp12 = tmp11[0:1]; - assign out = tmp12[1][DEPTH+OFFSET][OFFSET]; + assign tmp7 = tmp6; + assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7; + assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1]; + assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3]; + assign tmp11[1] = tmp10; + assign tmp11[-1] = tmp11[1]; + assign tmp11[0] = tmp11[-1]; + assign tmp12 = tmp11[0:1]; + assign out = tmp12[1][DEPTH+OFFSET][OFFSET]; endmodule module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = 2; - typedef struct packed { int data; } data_type; - data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; + localparam OFFSET = 2; + typedef struct packed { int data; } data_type; + data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; - localparam [32-WIDTH-1:0] PAD = 0; - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - if (shift[i]) begin - /*verilator lint_off ALWCOMBORDER*/ - tmp[i+1+OFFSET] = {PAD, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; - /*verilator lint_on ALWCOMBORDER*/ - end - else begin - tmp[i+1+OFFSET] = tmp[i+OFFSET]; - end - end - endgenerate - assign tmp[0+OFFSET] = {PAD, in}; - logic _dummy; - always_comb {_dummy, out[WIDTH-1:1], out[0]} = tmp[DEPTH+OFFSET][WIDTH:0]; + localparam [32-WIDTH-1:0] PAD = 0; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always_comb + if (shift[i]) begin + /*verilator lint_off ALWCOMBORDER*/ + tmp[i+1+OFFSET] = {PAD, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; + /*verilator lint_on ALWCOMBORDER*/ + end + else begin + tmp[i+1+OFFSET] = tmp[i+OFFSET]; + end + end + endgenerate + assign tmp[0+OFFSET] = {PAD, in}; + logic _dummy; + always_comb {_dummy, out[WIDTH-1:1], out[0]} = tmp[DEPTH+OFFSET][WIDTH:0]; endmodule module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = -2; - /*verilator lint_off ASCRANGE*/ - reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/; - /*verilator lint_on ASCRANGE*/ + localparam OFFSET = -2; + /*verilator lint_off ASCRANGE*/ + reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/; + /*verilator lint_on ASCRANGE*/ - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always @(shift or tmp) - /*verilator lint_off ALWCOMBORDER*/ - if (shift[i]) begin - tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; - end - else begin - tmp[i+1+OFFSET][1:0] = tmp[i+OFFSET][1:0]; - tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2]; - end - /*verilator lint_on ALWCOMBORDER*/ - end - endgenerate - assign tmp[0+OFFSET] = in; - assign out = tmp[DEPTH+OFFSET]; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always @(shift or tmp) + /*verilator lint_off ALWCOMBORDER*/ + if (shift[i]) begin + tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; + end + else begin + tmp[i+1+OFFSET][1:0] = tmp[i+OFFSET][1:0]; + tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2]; + end + /*verilator lint_on ALWCOMBORDER*/ + end + endgenerate + assign tmp[0+OFFSET] = in; + assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - localparam OFFSET = -2; - /*verilator lint_off ASCRANGE*/ - reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/; - /*verilator lint_on ASCRANGE*/ + localparam OFFSET = -2; + /*verilator lint_off ASCRANGE*/ + reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/; + /*verilator lint_on ASCRANGE*/ - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - /*verilator lint_off ALWCOMBORDER*/ - if (shift[i]) begin - tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]}; - end - else begin // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET] - tmp[i+1+OFFSET][0+OFFSET:2+OFFSET] = tmp[i+OFFSET][0+OFFSET:2+OFFSET]; - tmp[i+1+OFFSET][3+OFFSET] = tmp[i+OFFSET][3+OFFSET]; - {tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]}; - {tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]}; - end - /*verilator lint_on ALWCOMBORDER*/ - end - endgenerate - assign tmp[0+OFFSET] = in; - assign out = tmp[DEPTH+OFFSET]; + generate + for(genvar i = 0; i < DEPTH; ++i) begin + always_comb + /*verilator lint_off ALWCOMBORDER*/ + if (shift[i]) begin + tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]}; + end + else begin // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET] + tmp[i+1+OFFSET][0+OFFSET:2+OFFSET] = tmp[i+OFFSET][0+OFFSET:2+OFFSET]; + tmp[i+1+OFFSET][3+OFFSET] = tmp[i+OFFSET][3+OFFSET]; + {tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]}; + {tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]}; + end + /*verilator lint_on ALWCOMBORDER*/ + end + endgenerate + assign tmp[0+OFFSET] = in; + assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_packed_struct #(localparam DEPTH = 3, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - typedef struct packed { - logic [WIDTH-1:0] v0, v1, v2, v3; - } data_type; - wire data_type tmp /*verilator split_var*/; + typedef struct packed { + logic [WIDTH-1:0] v0, v1, v2, v3; + } data_type; + wire data_type tmp /*verilator split_var*/; - assign tmp.v0 = in; - assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0; - assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1; - assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2; - assign out = tmp.v3; + assign tmp.v0 = in; + assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0; + assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1; + assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2; + assign out = tmp.v3; endmodule module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) - (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); + (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); - /*verilator lint_off ASCRANGE*/ - wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/; - /*verilator lint_on ASCRANGE*/ + /*verilator lint_off ASCRANGE*/ + wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/; + /*verilator lint_on ASCRANGE*/ - generate - for(genvar i = 0; i < DEPTH; ++i) begin - always_comb - if (shift[i]) begin - tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = {tmp[WIDTH*(i+1)-(1<= 4) begin - if (!unpack_sig0[16] || !unpack_sig1[16]) $stop; - if (!unpack_sig2[16] || !unpack_sig3[16]) $stop; - end else begin - if (unpack_sig0[16] || unpack_sig1[16]) $stop; - if (unpack_sig2[16] || unpack_sig3[16]) $stop; - end - end + int c = 0; + always @(posedge clk) begin + c <= c + 1; + if (c >= 4) begin + if (!unpack_sig0[16] || !unpack_sig1[16]) $stop; + if (!unpack_sig2[16] || !unpack_sig3[16]) $stop; + end else begin + if (unpack_sig0[16] || unpack_sig1[16]) $stop; + if (unpack_sig2[16] || unpack_sig3[16]) $stop; + end + end endmodule module hash_descending ( @@ -429,92 +429,92 @@ module hash_ascending ( endmodule module t(/*AUTOARG*/ clk); - input clk; - localparam DEPTH = 3; - localparam WIDTH = 2**DEPTH; - localparam NUMSUB = 9; + input clk; + localparam DEPTH = 3; + localparam WIDTH = 2**DEPTH; + localparam NUMSUB = 9; - logic [WIDTH-1:0] in; - logic [WIDTH-1:0] out[0:NUMSUB-1]; - logic [WIDTH-1:0] through_tmp; - logic [DEPTH-1:0] shift = 0; + logic [WIDTH-1:0] in; + logic [WIDTH-1:0] out[0:NUMSUB-1]; + logic [WIDTH-1:0] through_tmp; + logic [DEPTH-1:0] shift = 0; - // barrel shifter - barshift_1d_unpacked #(.DEPTH(DEPTH)) shifter0(.in(in), .out(out[0]), .shift(shift)); - barshift_1d_unpacked_le #(.DEPTH(DEPTH)) shifter1(.in(in), .out(out[1]), .shift(shift)); - barshift_1d_unpacked_struct0 #(.DEPTH(DEPTH)) shifter2(.in(in), .out(out[2]), .shift(shift)); - barshift_2d_unpacked #(.DEPTH(DEPTH)) shifter3(.in(in), .out(out[3]), .shift(shift)); - barshift_1d_unpacked_struct1 #(.DEPTH(DEPTH)) shifter4(.in(in), .out(out[4]), .shift(shift)); - barshift_2d_packed_array #(.DEPTH(DEPTH)) shifter5(.in(in), .out(out[5]), .shift(shift)); - barshift_2d_packed_array_le #(.DEPTH(DEPTH)) shifter6(.in(in), .out(out[6]), .shift(shift)); - barshift_1d_packed_struct shifter7(.in(in), .out(out[7]), .shift(shift)); - barshift_bitslice #(.DEPTH(DEPTH)) shifter8(.in(in), .out(out[8]), .shift(shift)); - through #(.WIDTH(WIDTH)) though0 (.in(out[8]), .out(through_tmp)); - delay delay0(.clk(clk)); - var_decl_with_init i_var_decl_with_init(); - t_array_rev i_t_array_rev(clk); + // barrel shifter + barshift_1d_unpacked #(.DEPTH(DEPTH)) shifter0(.in(in), .out(out[0]), .shift(shift)); + barshift_1d_unpacked_le #(.DEPTH(DEPTH)) shifter1(.in(in), .out(out[1]), .shift(shift)); + barshift_1d_unpacked_struct0 #(.DEPTH(DEPTH)) shifter2(.in(in), .out(out[2]), .shift(shift)); + barshift_2d_unpacked #(.DEPTH(DEPTH)) shifter3(.in(in), .out(out[3]), .shift(shift)); + barshift_1d_unpacked_struct1 #(.DEPTH(DEPTH)) shifter4(.in(in), .out(out[4]), .shift(shift)); + barshift_2d_packed_array #(.DEPTH(DEPTH)) shifter5(.in(in), .out(out[5]), .shift(shift)); + barshift_2d_packed_array_le #(.DEPTH(DEPTH)) shifter6(.in(in), .out(out[6]), .shift(shift)); + barshift_1d_packed_struct shifter7(.in(in), .out(out[7]), .shift(shift)); + barshift_bitslice #(.DEPTH(DEPTH)) shifter8(.in(in), .out(out[8]), .shift(shift)); + through #(.WIDTH(WIDTH)) though0 (.in(out[8]), .out(through_tmp)); + delay delay0(.clk(clk)); + var_decl_with_init i_var_decl_with_init(); + t_array_rev i_t_array_rev(clk); - logic [31:1] hash_input_d = 31'h3210abcd; // 1 based on purpose - /*verilator lint_off ASCRANGE*/ - logic [1:31] hash_input_a = 31'h3210abcd; // 1 based on purpose - /*verilator lint_on ASCRANGE*/ - logic [8:0] hash_output_dd; - logic [8:0] hash_output_da; - logic [8:0] hash_output_ad; - logic [8:0] hash_output_aa; - hash_descending i_hash_dd(hash_input_d, hash_output_dd); - hash_descending i_hash_da(hash_input_a, hash_output_da); - hash_ascending i_hash_ad(hash_input_d, hash_output_ad); - hash_ascending i_hash_aa(hash_input_a, hash_output_aa); + logic [31:1] hash_input_d = 31'h3210abcd; // 1 based on purpose + /*verilator lint_off ASCRANGE*/ + logic [1:31] hash_input_a = 31'h3210abcd; // 1 based on purpose + /*verilator lint_on ASCRANGE*/ + logic [8:0] hash_output_dd; + logic [8:0] hash_output_da; + logic [8:0] hash_output_ad; + logic [8:0] hash_output_aa; + hash_descending i_hash_dd(hash_input_d, hash_output_dd); + hash_descending i_hash_da(hash_input_a, hash_output_da); + hash_ascending i_hash_ad(hash_input_d, hash_output_ad); + hash_ascending i_hash_aa(hash_input_a, hash_output_aa); - assign in = 8'b10001110; - /*verilator lint_off ASCRANGE*/ - logic [7:0] [7:0] expc - = {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001, - 8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101}; - /*verilator lint_on ASCRANGE*/ - always @(posedge clk) begin : always_block - automatic bit failed = 0; - automatic logic [8:0] hash_expected = hash_input_d[23:15] ^ hash_input_d[14:6]; - $display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]); - for (int i = 0; i < NUMSUB; ++i) begin - if (out[i] != expc[7-shift]) begin - $display("Missmatch out[%d]:%b", i, out[i]); - failed = 1; - end - end - if (through_tmp != expc[7-shift]) begin - $display("Missmatch through_tmp:%b", through_tmp); - failed = 1; - end - if (hash_output_dd != hash_expected) begin - $display("Missmatch hash_output_dd: in=0x%08x out=0x%02x expected=0x%02x", - hash_input_d, hash_output_dd, hash_expected); + assign in = 8'b10001110; + /*verilator lint_off ASCRANGE*/ + logic [7:0] [7:0] expc + = {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001, + 8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101}; + /*verilator lint_on ASCRANGE*/ + always @(posedge clk) begin : always_block + automatic bit failed = 0; + automatic logic [8:0] hash_expected = hash_input_d[23:15] ^ hash_input_d[14:6]; + $display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]); + for (int i = 0; i < NUMSUB; ++i) begin + if (out[i] != expc[7-shift]) begin + $display("Missmatch out[%d]:%b", i, out[i]); failed = 1; end - if (hash_output_da != hash_expected) begin - $display("Missmatch hash_output_da: in=0x%08x out=0x%02x expected=0x%02x", - hash_input_a, hash_output_da, hash_expected); - failed = 1; - end - if (hash_output_ad != hash_expected) begin - $display("Missmatch hash_output_ad: in=0x%08x out=0x%02x expected=0x%02x", - hash_input_d, hash_output_ad, hash_expected); - failed = 1; - end - if (hash_output_aa != hash_expected) begin - $display("Missmatch hash_output_aa: in=0x%08x out=0x%02x expected=0x%02x", - hash_input_a, hash_output_aa, hash_expected); - failed = 1; - end - hash_input_d = {hash_input_d[ 1], hash_input_d[31:2]}; - hash_input_a = {hash_input_a[31], hash_input_a[1:30]}; - if (failed) $stop; - if (shift == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - shift <= shift + 1; - end + end + if (through_tmp != expc[7-shift]) begin + $display("Missmatch through_tmp:%b", through_tmp); + failed = 1; + end + if (hash_output_dd != hash_expected) begin + $display("Missmatch hash_output_dd: in=0x%08x out=0x%02x expected=0x%02x", + hash_input_d, hash_output_dd, hash_expected); + failed = 1; + end + if (hash_output_da != hash_expected) begin + $display("Missmatch hash_output_da: in=0x%08x out=0x%02x expected=0x%02x", + hash_input_a, hash_output_da, hash_expected); + failed = 1; + end + if (hash_output_ad != hash_expected) begin + $display("Missmatch hash_output_ad: in=0x%08x out=0x%02x expected=0x%02x", + hash_input_d, hash_output_ad, hash_expected); + failed = 1; + end + if (hash_output_aa != hash_expected) begin + $display("Missmatch hash_output_aa: in=0x%08x out=0x%02x expected=0x%02x", + hash_input_a, hash_output_aa, hash_expected); + failed = 1; + end + hash_input_d = {hash_input_d[ 1], hash_input_d[31:2]}; + hash_input_a = {hash_input_a[31], hash_input_a[1:30]}; + if (failed) $stop; + if (shift == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + shift <= shift + 1; + end endmodule diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index 071aefe15..db0d23a16 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -1,83 +1,83 @@ %Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. - 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/; + 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/SPLITVAR?v=latest ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. %Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. - 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/; + 8 | logic [7:0] should_show_warning_global1[1:0] /*verilator split_var*/; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:11:16: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. - 11 | logic [7:0] should_show_warning_ifs0 /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:12:16: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. - 12 | logic [7:0] should_show_warning_ifs1 [1:0] /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:40:14: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. - 40 | i_sub0.cannot_split1[0] = 0; - | ^~~~~~~~~~~~~ -%Warning-SELRANGE: t/t_split_var_1_bad.v:90:33: Selection index out of range: 13 outside 12:10 - : ... note: In instance 't.i_sub3' - 90 | assign outwires[12] = inwires[13]; - | ^ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:11:15: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. + 11 | logic [7:0] should_show_warning_ifs0 /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:12:15: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. + 12 | logic [7:0] should_show_warning_ifs1[1:0] /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:46:12: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. + 46 | i_sub0.cannot_split1[0] = 0; + | ^~~~~~~~~~~~~ +%Warning-SELRANGE: t/t_split_var_1_bad.v:101:32: Selection index out of range: 13 outside 12:10 + : ... note: In instance 't.i_sub3' + 101 | assign outwires[12] = inwires[13]; + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. +%Warning-WIDTHTRUNC: t/t_split_var_1_bad.v:47:29: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. : ... note: In instance 't' - 41 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); - | ^ + 47 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_split_var_1_bad.v:79:16: Illegal assignment of constant to unpacked array +%Error: t/t_split_var_1_bad.v:90:15: Illegal assignment of constant to unpacked array : ... note: In instance 't.i_sub2' - 79 | assign b = a[0]; - | ^ + 90 | assign b = a[0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-SPLITVAR: t/t_split_var_1_bad.v:56:31: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. +%Warning-SPLITVAR: t/t_split_var_1_bad.v:64:39: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. : ... note: In instance 't.i_sub0' - 56 | rd_data = cannot_split0[addr]; - | ^~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:90:34: 'inwires' has split_var metacomment but will not be split because index is out of range. - : ... note: In instance 't.i_sub3' - 90 | assign outwires[12] = inwires[13]; - | ^~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:17:9: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. + 64 | always_comb rd_data = cannot_split0[addr]; + | ^~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:101:33: 'inwires' has split_var metacomment but will not be split because index is out of range. + : ... note: In instance 't.i_sub3' + 101 | assign outwires[12] = inwires[13]; + | ^~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:17:8: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't' - 17 | real should_show_warning0 /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:18:11: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. + 17 | real should_show_warning0 /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:18:10: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't' - 18 | string should_show_warning1 /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:19:11: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1. + 18 | string should_show_warning1 /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:19:8: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1. + : ... note: In instance 't' + 19 | wire should_show_warning2 /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:23:15: 'public_signal' has split_var metacomment but will not be split because it is public. : ... note: In instance 't' - 19 | wire should_show_warning2 /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:23:16: 'public_signal' has split_var metacomment but will not be split because it is public. + 23 | logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; + | ^~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:37:43: 'inout_port' has split_var metacomment but will not be split because it is an inout port. : ... note: In instance 't' - 23 | logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; - | ^~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:31:44: 'inout_port' has split_var metacomment but will not be split because it is an inout port. + 37 | function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, + | ^~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:38:41: 'ref_port' has split_var metacomment but will not be split because it is a ref argument. : ... note: In instance 't' - 31 | function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, - | ^~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:32:42: 'ref_port' has split_var metacomment but will not be split because it is a ref argument. + 38 | ref logic [7:0] ref_port /*verilator split_var*/); + | ^~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:43:17: 'loop_idx' has split_var metacomment but will not be split because it is used as a loop variable. : ... note: In instance 't' - 32 | ref logic [7:0] ref_port /*verilator split_var*/); - | ^~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:37:19: 'loop_idx' has split_var metacomment but will not be split because it is used as a loop variable. - : ... note: In instance 't' - 37 | logic [7:0] loop_idx /*verilator split_var*/; - | ^~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:62:11: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. + 43 | logic [7:0] loop_idx /*verilator split_var*/; + | ^~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:73:10: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't.i_sub1' - 62 | genvar cannot_split_genvar /*verilator split_var*/; - | ^~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:65:71: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. + 73 | genvar cannot_split_genvar /*verilator split_var*/; + | ^~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:76:70: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... note: In instance 't.i_sub1' - 65 | static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; - | ^ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:66:23: 'rd_tmp' has split_var metacomment but will not be split because its bit range cannot be determined statically. + 76 | static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; + | ^ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:77:21: 'rd_tmp' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... note: In instance 't.i_sub1' - 66 | rd_data = rd_tmp[{3'b0, addr[0]}+:8]; - | ^ + 77 | rd_data = rd_tmp[{3'b0, addr[0]}+:8]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index 3e494d990..ae241e055 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -4,89 +4,100 @@ // SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 -logic [7:0] should_show_warning_global0 /* verilator split_var */; -logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */; +logic [7:0] should_show_warning_global0 /* verilator split_var */; +logic [7:0] should_show_warning_global1[1:0] /* verilator split_var */; interface ifs; - logic [7:0] should_show_warning_ifs0 /* verilator split_var */; - logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */; + logic [7:0] should_show_warning_ifs0 /* verilator split_var */; + logic [7:0] should_show_warning_ifs1[1:0] /* verilator split_var */; endinterface module t; - // The following variables can not be splitted. will see warnings. - real should_show_warning0 /*verilator split_var*/; - string should_show_warning1 /*verilator split_var*/; - wire should_show_warning2 /*verilator split_var*/; + // The following variables can not be splitted. will see warnings. + real should_show_warning0 /*verilator split_var*/; + string should_show_warning1 /*verilator split_var*/; + wire should_show_warning2 /*verilator split_var*/; - logic [3:0] addr; - logic [7:0] rd_data0, rd_data1, rd_data2; - logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; + logic [3:0] addr; + logic [7:0] rd_data0, rd_data1, rd_data2; + logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; - sub0 i_sub0(.addr(addr), .rd_data(rd_data0)); - sub1 i_sub1(.addr(addr), .rd_data(rd_data2)); - sub2 i_sub2(); - sub3 i_sub3(); - ifs i_ifs(); + sub0 i_sub0 ( + .addr(addr), + .rd_data(rd_data0) + ); + sub1 i_sub1 ( + .addr(addr), + .rd_data(rd_data2) + ); + sub2 i_sub2 (); + sub3 i_sub3 (); + ifs i_ifs (); - function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, - ref logic [7:0] ref_port /*verilator split_var*/); - return 0; - endfunction + function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, + ref logic [7:0] ref_port /*verilator split_var*/); + return 0; + endfunction - initial begin - logic [7:0] loop_idx /*verilator split_var*/; - addr = 0; - addr = 1; - i_sub0.cannot_split1[0] = 0; - i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); - for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin - addr += 1; - end - $finish; - end + initial begin + logic [7:0] loop_idx /*verilator split_var*/; + addr = 0; + addr = 1; + i_sub0.cannot_split1[0] = 0; + i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); + for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin + addr += 1; + end + $finish; + end endmodule -module sub0(input [3:0]addr, output logic [7:0] rd_data); +module sub0 ( + input [3:0] addr, + output logic [7:0] rd_data +); - logic [7:0] cannot_split0[0:15] /*verilator split_var*/; - logic [7:0] cannot_split1[0:15] /*verilator split_var*/; - always_comb - rd_data = cannot_split0[addr]; + logic [7:0] cannot_split0[0:15] /*verilator split_var*/; + logic [7:0] cannot_split1[0:15] /*verilator split_var*/; + always_comb rd_data = cannot_split0[addr]; endmodule -module sub1(input [3:0]addr, output logic [7:0] rd_data); - genvar cannot_split_genvar /*verilator split_var*/; - logic [15:0] [8:0] cannot_split /*verilator split_var*/; - always_comb begin - static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; - rd_data = rd_tmp[{3'b0, addr[0]}+:8]; - end +module sub1 ( + input [3:0] addr, + output logic [7:0] rd_data +); + genvar cannot_split_genvar /*verilator split_var*/; + logic [15:0][8:0] cannot_split /*verilator split_var*/; + always_comb begin + static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; + rd_data = rd_tmp[{3'b0, addr[0]}+:8]; + end endmodule module sub2; // from t_bitsel_wire_array_bad.v - // a and b are arrays of length 1. - wire a[0:0] /* verilator split_var */ ; // Array of nets - wire b[0:0] /* verilator split_var */ ; + // a and b are arrays of length 1. + wire a[0:0] /* verilator split_var */; // Array of nets + wire b[0:0] /* verilator split_var */; - assign a = 1'b0; // Only net assignment allowed - assign b = a[0]; // Only net assignment allowed + assign a = 1'b0; // Only net assignment allowed + assign b = a[0]; // Only net assignment allowed endmodule module sub3; // from t_select_bad_range3.v - logic [7:0] inwires [12:10] /* verilator split_var */; - wire [7:0] outwires [12:10] /* verilator split_var */; + logic [7:0] inwires[12:10] /* verilator split_var */; + wire [7:0] outwires[12:10] /* verilator split_var */; - assign outwires[10] = inwires[11]; - assign outwires[11] = inwires[12]; - assign outwires[12] = inwires[13]; // must be an error here + assign outwires[10] = inwires[11]; + assign outwires[11] = inwires[12]; + assign outwires[12] = inwires[13]; // must be an error here endmodule diff --git a/test_regress/t/t_split_var_3_wreal.v b/test_regress/t/t_split_var_3_wreal.v index 135508eb7..6b036a683 100644 --- a/test_regress/t/t_split_var_3_wreal.v +++ b/test_regress/t/t_split_var_3_wreal.v @@ -6,49 +6,55 @@ `begin_keywords "VAMS-2.3" -module t (/*autoarg*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc = 0; - integer cyc = 0; + real vin[0:1] /*verilator split_var*/; + wreal vout[0:1] /*verilator split_var*/; + swap i_swap ( + .in0(vin[0]), + .in1(vin[1]), + .out0(vout[0]), + .out1(vout[1]) + ); - real vin[0:1] /*verilator split_var*/; - wreal vout[0:1] /*verilator split_var*/; - swap i_swap(.in0(vin[0]), .in1(vin[1]), .out0(vout[0]), .out1(vout[1])); - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - vin[0] = 1.0; - vin[1] = 2.0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + vin[0] = 1.0; + vin[1] = 2.0; + end + else if (cyc == 2) begin + vin[0] = 3.0; + vin[1] = 4.0; + end + else if (cyc == 3) begin + if (vout[0] == vin[1] && vout[1] == vin[0]) begin + $write("*-* All Finished *-*\n"); + $finish; end - else if (cyc==2) begin - vin[0] = 3.0; - vin[1] = 4.0; + else begin + $write("Mismatch %f %f\n", vout[0], vout[1]); + $stop; end - else if (cyc==3) begin - if (vout[0] == vin[1] && vout[1] == vin[0]) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - $write("Mismatch %f %f\n", vout[0], vout[1]); - $stop; - end - end - end + end + end endmodule -module swap - (input wreal in0, in1, - output wreal out0, out1); - wreal tmp[0:1] /* verilator split_var*/; - assign tmp[0] = in0; - assign tmp[1] = in1; - assign out0 = tmp[1]; - assign out1 = tmp[0]; +module swap ( + input wreal in0, + in1, + output wreal out0, + out1 +); + wreal tmp[0:1] /* verilator split_var*/; + assign tmp[0] = in0; + assign tmp[1] = in1; + assign out0 = tmp[1]; + assign out1 = tmp[0]; endmodule diff --git a/test_regress/t/t_split_var_4.v b/test_regress/t/t_split_var_4.v index 697399b2c..4076b5beb 100644 --- a/test_regress/t/t_split_var_4.v +++ b/test_regress/t/t_split_var_4.v @@ -12,85 +12,85 @@ `endif module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; - wire o0; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire o0; - wire [15:0] vec_i = crc[15:0]; - wire [31:0] i = crc[31:0]; + wire [15:0] vec_i = crc[15:0]; + wire [31:0] i = crc[31:0]; - Test test(/*AUTOINST*/ - // Outputs - .o0 (o0), - // Inputs - .clk (clk), - .i (i[1:0])); + Test test(/*AUTOINST*/ + // Outputs + .o0 (o0), + // Inputs + .clk (clk), + .i (i[1:0])); - // Aggregate outputs into a single result vector - // verilator lint_off WIDTH - wire [63:0] result = {o0}; - // verilator lint_on WIDTH + // Aggregate outputs into a single result vector + // verilator lint_off WIDTH + wire [63:0] result = {o0}; + // verilator lint_on WIDTH - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); - $display("o %b", o0); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $display("o %b", o0); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb58b16c592557b30 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - o0, - // Inputs - clk, i - ); + // Outputs + o0, + // Inputs + clk, i + ); - input wire clk; - input wire [1:0] i; - output reg o0; + input wire clk; + input wire [1:0] i; + output reg o0; - typedef struct packed { - logic v0, v1; - } packed_type0; - packed_type0 value0 `SPLIT_VAR_COMMENT; - wire value0_v0; + typedef struct packed { + logic v0, v1; + } packed_type0; + packed_type0 value0 `SPLIT_VAR_COMMENT; + wire value0_v0; - assign value0.v0 = i[0]; - assign value0.v1 = i[1] & !value0_v0; - assign value0_v0 = value0.v0; + assign value0.v0 = i[0]; + assign value0.v1 = i[1] & !value0_v0; + assign value0_v0 = value0.v0; - always_ff @(posedge clk) begin - o0 <= |value0; - end + always_ff @(posedge clk) begin + o0 <= |value0; + end endmodule diff --git a/test_regress/t/t_split_var_issue.v b/test_regress/t/t_split_var_issue.v index 2f426a83b..32b2896b3 100644 --- a/test_regress/t/t_split_var_issue.v +++ b/test_regress/t/t_split_var_issue.v @@ -6,45 +6,45 @@ module other_sub ( input wire clk, - input wire foo, - output logic [5:0] bar + input wire foo, + output logic [5:0] bar ); - always_comb bar[0] = foo; + always_comb bar[0] = foo; `ifndef NO_ASSERT - assert property (@(posedge clk) (foo == bar[0])); + assert property (@(posedge clk) (foo == bar[0])); `endif - always_ff @(posedge clk) bar[5:1] <= bar[4:0]; + always_ff @(posedge clk) bar[5:1] <= bar[4:0]; endmodule -interface intf - (input wire clk); +interface intf ( + input wire clk +); endinterface module sub ( input logic clk ); - for (genvar k = 0; k < 4; k++) begin - logic [5:0] bar; - other_sub - the_other_sub ( - .clk, - .foo ('1), - .bar - ); - end + for (genvar k = 0; k < 4; k++) begin + logic [5:0] bar; + other_sub the_other_sub ( + .clk, + .foo('1), + .bar + ); + end endmodule module t ( input clk ); - int cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end - sub the_sub (.*); + end + sub the_sub (.*); endmodule diff --git a/test_regress/t/t_split_var_types.v b/test_regress/t/t_split_var_types.v index d73bab308..0ffcde4a9 100644 --- a/test_regress/t/t_split_var_types.v +++ b/test_regress/t/t_split_var_types.v @@ -4,26 +4,25 @@ // SPDX-FileCopyrightText: 2025 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic [7:0] data = 0; - // Test loop - always @ (posedge clk) begin - if (data != 15) begin - data <= data + 8'd1; - end else begin - $write("*-* All Finished *-*\n"); - $finish; - end + logic [7:0] data = 0; + // Test loop + always @(posedge clk) begin + if (data != 15) begin + data <= data + 8'd1; end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - bug5782 u_bug5782(.data_out()); - bug5984 u_bug5984(.in(data)); + bug5782 u_bug5782 (.data_out()); + bug5984 u_bug5984 (.in(data)); endmodule @@ -31,30 +30,30 @@ endmodule module bug5782 ( output logic [31:0][15:0] data_out ); - logic [31:0][15:0] data [8] /*verilator split_var*/; - always begin - data_out = data[7]; - end + logic [31:0][15:0] data[8] /*verilator split_var*/; + always begin + data_out = data[7]; + end endmodule // #5984 inconsistent assignment due to wrong bit range calculation. module bug5984 ( - input logic [1:0][3:0] in - ); + input logic [1:0][3:0] in +); - logic [1:0][5:2] internal; + logic [1:0][5:2] internal; - for (genvar dim1 = 0; dim1 < 2; dim1++) begin - for (genvar dim2 = 0; dim2 < 4; dim2++) begin - assign internal[dim1][dim2+2] = in[dim1][dim2]; + for (genvar dim1 = 0; dim1 < 2; dim1++) begin + for (genvar dim2 = 0; dim2 < 4; dim2++) begin + assign internal[dim1][dim2+2] = in[dim1][dim2]; + end + end + + for (genvar dim1 = 0; dim1 < 2; dim1++) begin + for (genvar dim2 = 0; dim2 < 4; dim2++) begin + always_ff @(negedge internal[dim1][dim2+2]) begin + $display("%0b", internal[dim1][dim2+2]); end - end - - for (genvar dim1 = 0; dim1 < 2; dim1++) begin - for (genvar dim2 = 0; dim2 < 4; dim2++) begin - always_ff @(negedge internal[dim1][dim2+2]) begin - $display("%0b", internal[dim1][dim2+2]); - end - end - end + end + end endmodule diff --git a/test_regress/t/t_srandom_class_dep.v b/test_regress/t/t_srandom_class_dep.v index 300f3d37a..9cfefbbfd 100644 --- a/test_regress/t/t_srandom_class_dep.v +++ b/test_regress/t/t_srandom_class_dep.v @@ -7,44 +7,44 @@ typedef class Cls; class A; - extern function void method(); + extern function void method(); endclass class B; - extern function void method(); + extern function void method(); endclass class C; - extern function void method(); + extern function void method(); endclass class D; - extern function void method(); + extern function void method(); endclass function void A::method(); - B obj = new; - obj.method(); + B obj = new; + obj.method(); endfunction function void B::method(); - this.srandom(0); + this.srandom(0); endfunction function void C::method(); - this.srandom(0); + this.srandom(0); endfunction function void D::method(); - C obj = new; - obj.method(); + C obj = new; + obj.method(); endfunction module t; - A obj1 = new; - D obj2 = new; - initial begin - obj1.method(); - obj2.method(); - end + A obj1 = new; + D obj2 = new; + initial begin + obj1.method(); + obj2.method(); + end endmodule diff --git a/test_regress/t/t_stack_check.v b/test_regress/t/t_stack_check.v index 930c8a006..29b489597 100644 --- a/test_regress/t/t_stack_check.v +++ b/test_regress/t/t_stack_check.v @@ -6,9 +6,9 @@ module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_static_elab.v b/test_regress/t/t_static_elab.v index 013b5ed93..6a5339935 100644 --- a/test_regress/t/t_static_elab.v +++ b/test_regress/t/t_static_elab.v @@ -6,47 +6,45 @@ module t; - typedef struct packed { - logic [ 31 : 0 ] _five; - } five_t; + typedef struct packed {logic [31 : 0] _five;} five_t; - typedef enum { - LOW_FIVE = 32'hdeadbeef, - HIGH_FIVE - } five_style_t; + typedef enum { + LOW_FIVE = 32'hdeadbeef, + HIGH_FIVE + } five_style_t; - function five_t gimme_five (); - automatic five_t result; + function five_t gimme_five(); + automatic five_t result; - result._five = 5; + result._five = 5; - return result; - endfunction + return result; + endfunction - function five_style_t gimme_high_five (); - automatic five_style_t result; + function five_style_t gimme_high_five(); + automatic five_style_t result; - result = HIGH_FIVE; + result = HIGH_FIVE; - return result; - endfunction + return result; + endfunction - localparam five_t FIVE = gimme_five(); - localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); + localparam five_t FIVE = gimme_five(); + localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); - initial begin - if (FIVE._five != 5) begin - $display("%%Error: Got 0b%b instead of 5", FIVE._five); - $stop; - end + initial begin + if (FIVE._five != 5) begin + $display("%%Error: Got 0b%b instead of 5", FIVE._five); + $stop; + end - if (THE_HIGH_FIVE != HIGH_FIVE) begin - $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); - $stop; - end + if (THE_HIGH_FIVE != HIGH_FIVE) begin + $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_std_identifier.v b/test_regress/t/t_std_identifier.v index d1903f00b..e8ba5fd0a 100644 --- a/test_regress/t/t_std_identifier.v +++ b/test_regress/t/t_std_identifier.v @@ -6,12 +6,12 @@ package foo; `ifdef TEST_DECLARE_STD - class std; - static int bar; - endclass + class std; + static int bar; + endclass `endif endpackage module t; - int baz = foo::std::bar; + int baz = foo::std::bar; endmodule diff --git a/test_regress/t/t_std_identifier_bad.out b/test_regress/t/t_std_identifier_bad.out index 4e5bee27e..b729118d2 100644 --- a/test_regress/t/t_std_identifier_bad.out +++ b/test_regress/t/t_std_identifier_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_std_identifier.v:16:20: Package/class for ':: reference' not found: 'std' - 16 | int baz = foo::std::bar; - | ^~~ +%Error: t/t_std_identifier.v:16:18: Package/class for ':: reference' not found: 'std' + 16 | int baz = foo::std::bar; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_std_identifier.v:16:25: Can't find definition of scope/variable/func: 'bar' - 16 | int baz = foo::std::bar; - | ^~~ +%Error: t/t_std_identifier.v:16:23: Can't find definition of scope/variable/func: 'bar' + 16 | int baz = foo::std::bar; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v index 989ad72f6..9d065e57a 100644 --- a/test_regress/t/t_std_randomize.v +++ b/test_regress/t/t_std_randomize.v @@ -11,133 +11,133 @@ class std_randomize_class; - rand bit [7:0] addr; - rand bit [31:0] data; - rand bit [63:0] data_x_4; + rand bit [7:0] addr; + rand bit [31:0] data; + rand bit [63:0] data_x_4; - bit [7:0] old_addr; - bit [31:0] old_data; - bit [63:0] old_data_x_4; + bit [7:0] old_addr; + bit [31:0] old_data; + bit [63:0] old_data_x_4; - function bit std_randomize(); - int success; - bit valid; + function bit std_randomize(); + int success; + bit valid; - old_addr = addr; - old_data = data; - old_data_x_4 = data_x_4; + old_addr = addr; + old_data = data; + old_data_x_4 = data_x_4; - success = std::randomize(addr, data); + success = std::randomize(addr, data); - valid = (success == 1) && !(addr == old_addr || data == old_data) && data_x_4 == old_data_x_4; + valid = (success == 1) && !(addr == old_addr || data == old_data) && data_x_4 == old_data_x_4; - return valid; - endfunction + return valid; + endfunction endclass parameter int PARAM = 123; module t_scope_std_randomize; - bit [7:0] addr; - bit [15:0] data; - int limit[10]; - bit [6:0] limit_7bits[10]; - bit [14:0] limit_15bits[10]; - bit [30:0] limit_31bits[10]; - bit [62:0] limit_63bits[10]; - bit [94:0] limit_95bits[10]; - int x; - int y = 50; - int arr1[2]; - int arr2[2]; + bit [7:0] addr; + bit [15:0] data; + int limit[10]; + bit [6:0] limit_7bits[10]; + bit [14:0] limit_15bits[10]; + bit [30:0] limit_31bits[10]; + bit [62:0] limit_63bits[10]; + bit [94:0] limit_95bits[10]; + int x; + int y = 50; + int arr1[2]; + int arr2[2]; - function bit run(); - int ready; - int success; + function bit run(); + int ready; + int success; - bit [7:0] old_addr; - bit [15:0] old_data; - int old_ready; + bit [7:0] old_addr; + bit [15:0] old_data; + int old_ready; - old_addr = addr; - old_data = data; - old_ready = ready; - success = randomize(addr, ready); // std::randomize - if (success == 0) return 0; - if (addr == old_addr && data != old_data && ready == old_ready) begin - return 0; - end - return 1; - endfunction - - std_randomize_class test; - - initial begin - // Test class member randomization - test = new(); - test.old_addr = test.addr; - test.old_data = test.data; - test.old_data_x_4 = test.data_x_4; - `checkd(std::randomize(test.addr, test.data), 1); - if (test.addr == test.old_addr && test.data == test.old_data) $stop; - `checkd(test.data_x_4, test.old_data_x_4); - - // Test function-based randomization - `checkd(run(), 1); - `checkd(test.std_randomize(), 1); - - // Test array randomization with constraints - `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 32'd100;}}, 1); - foreach (limit[i]) if (limit[i] >= 32'd100) $stop; - - `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 7'd10;}}, 1); - foreach (limit_7bits[i]) if (limit_7bits[i] >= 7'd10) $stop; - - `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 15'd1000;}}, 1); - foreach (limit_15bits[i]) if (limit_15bits[i] >= 15'd1000) $stop; - - `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 31'd100000;}}, 1); - foreach (limit_31bits[i]) if (limit_31bits[i] >= 31'd100000) $stop; - - `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 63'd10000000000;}}, 1); - foreach (limit_63bits[i]) if (limit_63bits[i] >= 63'd10000000000) $stop; - - `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 95'd1000000000000;}}, 1); - foreach (limit_95bits[i]) if (limit_95bits[i] >= 95'd1000000000000) $stop; - - foreach (limit_63bits[i]) begin - `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 63'd50; limit_63bits[i] < 63'd100;}, 1); - if ((limit_63bits[i] < 63'd50) || (limit_63bits[i] >= 63'd100)) `stop; - end - - foreach (limit_95bits[i]) begin - `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 95'd50; limit_95bits[i] < 95'd1000;}, 1); - if (limit_95bits[i] < 95'd50 || limit_95bits[i] >= 95'd1000) $stop; - end - - // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints - `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { - addr > 8'd10; addr < 8'd50; - test.addr > addr; test.addr < 8'd100; - limit_31bits[0] > 31'(test.addr); limit_31bits[0] < 31'd200; - }, 1); - if (addr <= 8'd10 || addr >= 8'd50) `stop; - if (test.addr <= addr || test.addr >= 8'd100) `stop; - if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; - - // Test parameter in with clause - void'(std::randomize(x) with { x > PARAM; }); - if (x <= PARAM) $stop; - void'(std::randomize(x) with { x < PARAM; x > y; }); - if (x >= PARAM || x <= y) $stop; - - arr1[0] = 1000; - arr2[0] = 42; - void'(std::randomize(arr1[0]) with { arr1[0] == arr2[0]; }); - if (arr1[0] != 42) $stop; - - $write("*-* All Finished *-*\n"); - $finish; + old_addr = addr; + old_data = data; + old_ready = ready; + success = randomize(addr, ready); // std::randomize + if (success == 0) return 0; + if (addr == old_addr && data != old_data && ready == old_ready) begin + return 0; end + return 1; + endfunction + + std_randomize_class test; + + initial begin + // Test class member randomization + test = new(); + test.old_addr = test.addr; + test.old_data = test.data; + test.old_data_x_4 = test.data_x_4; + `checkd(std::randomize(test.addr, test.data), 1); + if (test.addr == test.old_addr && test.data == test.old_data) $stop; + `checkd(test.data_x_4, test.old_data_x_4); + + // Test function-based randomization + `checkd(run(), 1); + `checkd(test.std_randomize(), 1); + + // Test array randomization with constraints + `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 32'd100;}}, 1); + foreach (limit[i]) if (limit[i] >= 32'd100) $stop; + + `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 7'd10;}}, 1); + foreach (limit_7bits[i]) if (limit_7bits[i] >= 7'd10) $stop; + + `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 15'd1000;}}, 1); + foreach (limit_15bits[i]) if (limit_15bits[i] >= 15'd1000) $stop; + + `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 31'd100000;}}, 1); + foreach (limit_31bits[i]) if (limit_31bits[i] >= 31'd100000) $stop; + + `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 63'd10000000000;}}, 1); + foreach (limit_63bits[i]) if (limit_63bits[i] >= 63'd10000000000) $stop; + + `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 95'd1000000000000;}}, 1); + foreach (limit_95bits[i]) if (limit_95bits[i] >= 95'd1000000000000) $stop; + + foreach (limit_63bits[i]) begin + `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 63'd50; limit_63bits[i] < 63'd100;}, 1); + if ((limit_63bits[i] < 63'd50) || (limit_63bits[i] >= 63'd100)) `stop; + end + + foreach (limit_95bits[i]) begin + `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 95'd50; limit_95bits[i] < 95'd1000;}, 1); + if (limit_95bits[i] < 95'd50 || limit_95bits[i] >= 95'd1000) $stop; + end + + // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints + `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { + addr > 8'd10; addr < 8'd50; + test.addr > addr; test.addr < 8'd100; + limit_31bits[0] > 31'(test.addr); limit_31bits[0] < 31'd200; + }, 1); + if (addr <= 8'd10 || addr >= 8'd50) `stop; + if (test.addr <= addr || test.addr >= 8'd100) `stop; + if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; + + // Test parameter in with clause + void'(std::randomize(x) with { x > PARAM; }); + if (x <= PARAM) $stop; + void'(std::randomize(x) with { x < PARAM; x > y; }); + if (x >= PARAM || x <= y) $stop; + + arr1[0] = 1000; + arr2[0] = 42; + void'(std::randomize(arr1[0]) with { arr1[0] == arr2[0]; }); + if (arr1[0] != 42) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_std_randomize_bad1.out b/test_regress/t/t_std_randomize_bad1.out index 57bd3584d..da88d6549 100644 --- a/test_regress/t/t_std_randomize_bad1.out +++ b/test_regress/t/t_std_randomize_bad1.out @@ -1,10 +1,10 @@ -%Error: t/t_std_randomize_bad1.v:12:36: Non-variable arguments for 'std::randomize()'. +%Error: t/t_std_randomize_bad1.v:12:32: Non-variable arguments for 'std::randomize()'. : ... note: In instance 't_std_randomize_bad1' - 12 | success = std::randomize(a + 1); - | ^ + 12 | success = std::randomize(a + 1); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_std_randomize_bad1.v:19:30: 'std::randomize()' does not accept 'null' as arguments. +%Error: t/t_std_randomize_bad1.v:19:26: 'std::randomize()' does not accept 'null' as arguments. : ... note: In instance 't_std_randomize_bad1' - 19 | void'(std::randomize(null)); - | ^~~~ + 19 | void'(std::randomize(null)); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_std_randomize_bad1.v b/test_regress/t/t_std_randomize_bad1.v index 01a87f69a..a0e353c6d 100644 --- a/test_regress/t/t_std_randomize_bad1.v +++ b/test_regress/t/t_std_randomize_bad1.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 module t_std_randomize_bad1; - bit [3:0] a; + bit [3:0] a; - function int run(); - int success; - success = std::randomize(a + 1); // ERROR: argument is not a variable - return success; - endfunction + function int run(); + int success; + success = std::randomize(a + 1); // ERROR: argument is not a variable + return success; + endfunction - initial begin - int ok, x; - ok = run(); - void'(std::randomize(null)); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int ok, x; + ok = run(); + void'(std::randomize(null)); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_std_randomize_no_args.v b/test_regress/t/t_std_randomize_no_args.v index ba0ec7f3a..3bc0a05fa 100644 --- a/test_regress/t/t_std_randomize_no_args.v +++ b/test_regress/t/t_std_randomize_no_args.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 module t_no_args; - bit [7:0] addr; - bit [15:0] data; - bit [7:0] old_addr; - bit [15:0] old_data; - int success; - bit valid; + bit [7:0] addr; + bit [15:0] data; + bit [7:0] old_addr; + bit [15:0] old_data; + int success; + bit valid; - initial begin - old_addr = addr; - old_data = data; + initial begin + old_addr = addr; + old_data = data; - success = std::randomize(); - valid = (success == 1) && (addr == old_addr) && (data == old_data); - if (!valid) $stop; + success = std::randomize(); + valid = (success == 1) && (addr == old_addr) && (data == old_data); + if (!valid) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_stmt_incr_unsup.out b/test_regress/t/t_stmt_incr_unsup.out index cd390f877..09d333b76 100644 --- a/test_regress/t/t_stmt_incr_unsup.out +++ b/test_regress/t/t_stmt_incr_unsup.out @@ -1,7 +1,7 @@ -%Warning-SIDEEFFECT: t/t_stmt_incr_unsup.v:17:31: Expression side effect may be mishandled +%Warning-SIDEEFFECT: t/t_stmt_incr_unsup.v:17:27: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression - 17 | arr[postincrement_i()][postincrement_i()]++; - | ^ + 17 | arr[postincrement_i()][postincrement_i()]++; + | ^ ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=latest ... Use "/* verilator lint_off SIDEEFFECT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_stmt_incr_unsup.v b/test_regress/t/t_stmt_incr_unsup.v index e95bc9a4f..4707bf813 100644 --- a/test_regress/t/t_stmt_incr_unsup.v +++ b/test_regress/t/t_stmt_incr_unsup.v @@ -7,14 +7,14 @@ int i = 0; function int postincrement_i; - return i++; + return i++; endfunction module t; - initial begin - automatic int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; - i = 0; - arr[postincrement_i()][postincrement_i()]++; - $display("Value: %d", i); - end + initial begin + automatic int arr[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; + i = 0; + arr[postincrement_i()][postincrement_i()]++; + $display("Value: %d", i); + end endmodule diff --git a/test_regress/t/t_stop_bad.v b/test_regress/t/t_stop_bad.v index 62d255e2b..ff008f3df 100644 --- a/test_regress/t/t_stop_bad.v +++ b/test_regress/t/t_stop_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $write("Intentional stop\n"); - $stop; - end + initial begin + $write("Intentional stop\n"); + $stop; + end endmodule diff --git a/test_regress/t/t_stop_winos_bad.v b/test_regress/t/t_stop_winos_bad.v index d01654f1a..99322b8b5 100644 --- a/test_regress/t/t_stop_winos_bad.v +++ b/test_regress/t/t_stop_winos_bad.v @@ -7,11 +7,11 @@ `line 7 "C:\\some\\windows\\path\\t_stop_winos_bad.v" 0 module t; - localparam string FILENAME = `__FILE__; - initial begin - $write("Intentional stop\n"); - // Print length to make sure \\ counts as 1 character - $write("Filename '%s' Length = %0d\n", FILENAME, FILENAME.len()); - $stop; - end + localparam string FILENAME = `__FILE__; + initial begin + $write("Intentional stop\n"); + // Print length to make sure \\ counts as 1 character + $write("Filename '%s' Length = %0d\n", FILENAME, FILENAME.len()); + $stop; + end endmodule diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index dd7ccef27..491883c66 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -4,309 +4,307 @@ // SPDX-FileCopyrightText: 2014 Glen Gibb // SPDX-License-Identifier: CC0-1.0 -//module t; -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - // The 'initial' code block below tests compilation-time - // evaluation/optimization of the stream operator. All occurences of the stream - // operator within this block are replaced prior to generation of C code. - logic [3:0] dout; - logic [31:0] dout32; - logic [10:0] dout11; + // The 'initial' code block below tests compilation-time + // evaluation/optimization of the stream operator. All occurences of the stream + // operator within this block are replaced prior to generation of C code. + logic [3:0] dout; + logic [31:0] dout32; + logic [10:0] dout11; - initial begin + // verilog_format: off + initial begin - // Stream operator: << - // Location: rhs of assignment - // - // Test slice sizes from 1 - 5 - dout = { << {4'b0001}}; if (dout != 4'b1000) $stop; - dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop; - dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop; - dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; - dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; + // Stream operator: << + // Location: rhs of assignment + // + // Test slice sizes from 1 - 5 + dout = { << {4'b0001}}; if (dout != 4'b1000) $stop; + dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop; + dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop; + dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; - // Stream operator: >> - // Location: rhs of assignment - // - // Right-streaming operator on RHS does not reorder bits - dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop; - dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop; - dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop; - dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop; - dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop; + // Stream operator: >> + // Location: rhs of assignment + // + // Right-streaming operator on RHS does not reorder bits + dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop; - // Stream operator: << - // Location: lhs of assignment - { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop; - { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop; - { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop; - { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + // Stream operator: << + // Location: lhs of assignment + { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop; + { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop; + { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop; + { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - // Stream operator: >> - // Location: lhs of assignment - { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + // Stream operator: >> + // Location: lhs of assignment + { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; - // Stream operator: << - // Location: lhs of assignment - // RHS is *wider* than LHS - /* verilator lint_off WIDTH */ - { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop; - { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop; - { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop; - { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop; - { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - /* verilator lint_on WIDTH */ + // Stream operator: << + // Location: lhs of assignment + // RHS is *wider* than LHS + /* verilator lint_off WIDTH */ + { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop; + { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop; + { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop; + { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop; + { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + /* verilator lint_on WIDTH */ - // Stream operator: >> - // Location: lhs of assignment - // RHS is *wider* than LHS - /* verilator lint_off WIDTH */ - { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; - /* verilator lint_on WIDTH */ + // Stream operator: >> + // Location: lhs of assignment + // RHS is *wider* than LHS + /* verilator lint_off WIDTH */ + { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + /* verilator lint_on WIDTH */ - // Stream operator: << - // Location: both sides of assignment - { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop; - { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop; - { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop; - { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; - { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; + // Stream operator: << + // Location: both sides of assignment + { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop; + { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop; + { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop; + { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; + { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; - // Stream operator: << - // Location: as an operand within a statement - // - // Test slice sizes from 1 - 5 - if (4'({ << {4'b0001}}) != 4'b1000) $stop; - if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop; - if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop; - if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop; - if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop; + // Stream operator: << + // Location: as an operand within a statement + // + // Test slice sizes from 1 - 5 + if (4'({ << {4'b0001}}) != 4'b1000) $stop; + if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop; + if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop; + if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop; + if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop; - // case - dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop; - dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop; - end + // case + dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop; + dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop; + end + // verilog_format: on - // The two always blocks below test run-time evaluation of the stream - // operator in generated C code. - // - // Various stream operators are optimized away. Here's a brief summary: - // - // Stream op on RHS of assign - // -------------------------- - // X = { << a { Y } } --- C function evaluates stream operator - // -- if log2(a) == int --> "fast" eval func - // -- if log2(a) != int --> "slow" eval func - // X = { >> a { Y } } --- stream operator is optimized away - // - // Stream op on LHS of assign - // -------------------------- - // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs! - // { << a { X } } = Y --- stream operator is moved to RHS, eval as above - // { >> a { X } } = Y --- stream operator is optimized away + // The two always blocks below test run-time evaluation of the stream + // operator in generated C code. + // + // Various stream operators are optimized away. Here's a brief summary: + // + // Stream op on RHS of assign + // -------------------------- + // X = { << a { Y } } --- C function evaluates stream operator + // -- if log2(a) == int --> "fast" eval func + // -- if log2(a) != int --> "slow" eval func + // X = { >> a { Y } } --- stream operator is optimized away + // + // Stream op on LHS of assign + // -------------------------- + // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs! + // { << a { X } } = Y --- stream operator is moved to RHS, eval as above + // { >> a { X } } = Y --- stream operator is optimized away - logic [31:0] din_i; - logic [63:0] din_q; - logic [95:0] din_w; + logic [31:0] din_i; + logic [63:0] din_q; + logic [95:0] din_w; - // Stream op on RHS, left-stream operator - logic [31:0] dout_rhs_ls_i; - logic [63:0] dout_rhs_ls_q; - logic [95:0] dout_rhs_ls_w; + // Stream op on RHS, left-stream operator + logic [31:0] dout_rhs_ls_i; + logic [63:0] dout_rhs_ls_q; + logic [95:0] dout_rhs_ls_w; - // Stream op on RHS, right-stream operator - logic [31:0] dout_rhs_rs_i; - logic [63:0] dout_rhs_rs_q; - logic [95:0] dout_rhs_rs_w; + // Stream op on RHS, right-stream operator + logic [31:0] dout_rhs_rs_i; + logic [63:0] dout_rhs_rs_q; + logic [95:0] dout_rhs_rs_w; - // Stream op on both sides, left-stream operator - logic [31:0] dout_bhs_ls_i; - logic [63:0] dout_bhs_ls_q; - logic [95:0] dout_bhs_ls_w; + // Stream op on both sides, left-stream operator + logic [31:0] dout_bhs_ls_i; + logic [63:0] dout_bhs_ls_q; + logic [95:0] dout_bhs_ls_w; - // Stream op on both sides, right-stream operator - logic [31:0] dout_bhs_rs_i; - logic [63:0] dout_bhs_rs_q; - logic [95:0] dout_bhs_rs_w; + // Stream op on both sides, right-stream operator + logic [31:0] dout_bhs_rs_i; + logic [63:0] dout_bhs_rs_q; + logic [95:0] dout_bhs_rs_w; - // Stream operator on LHS (with concatenation on LHS) - logic [3:0] din_lhs; - logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b; - logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b; + // Stream operator on LHS (with concatenation on LHS) + logic [3:0] din_lhs; + logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b; + logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b; - // Addition operator on LHS, right-shift tests: - // Testing various shift sizes to exercise fast + slow funcs - logic [22:0] dout_rhs_ls_i_23_3; - logic [22:0] dout_rhs_ls_i_23_4; + // Addition operator on LHS, right-shift tests: + // Testing various shift sizes to exercise fast + slow funcs + logic [22:0] dout_rhs_ls_i_23_3; + logic [22:0] dout_rhs_ls_i_23_4; - logic [36:0] dout_rhs_ls_q_37_3; - logic [36:0] dout_rhs_ls_q_37_4; + logic [36:0] dout_rhs_ls_q_37_3; + logic [36:0] dout_rhs_ls_q_37_4; - always @* - begin - // Stream operator: << - // Location: rhs of assignment - // - // Test each data type (I, Q, W) - dout_rhs_ls_i = { << {din_i}}; - dout_rhs_ls_q = { << {din_q}}; - dout_rhs_ls_w = { << {din_w}}; + always @* begin + // Stream operator: << + // Location: rhs of assignment + // + // Test each data type (I, Q, W) + dout_rhs_ls_i = {<<{din_i}}; + dout_rhs_ls_q = {<<{din_q}}; + dout_rhs_ls_w = {<<{din_w}}; - // Stream operator: >> - // Location: rhs of assignment - dout_rhs_rs_i = { >> {din_i}}; - dout_rhs_rs_q = { >> {din_q}}; - dout_rhs_rs_w = { >> {din_w}}; + // Stream operator: >> + // Location: rhs of assignment + dout_rhs_rs_i = {>>{din_i}}; + dout_rhs_rs_q = {>>{din_q}}; + dout_rhs_rs_w = {>>{din_w}}; - // Stream operator: << - // Location: lhs of assignment - { << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs; + // Stream operator: << + // Location: lhs of assignment + {<<2{dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs; - // Stream operator: >> - // Location: lhs of assignment - { >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs; + // Stream operator: >> + // Location: lhs of assignment + {>>2{dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs; - // Stream operator: << - // Location: both sides of assignment - { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; - { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; - { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; + // Stream operator: << + // Location: both sides of assignment + {<<5{dout_bhs_ls_i}} = {<<5{din_i}}; + {<<5{dout_bhs_ls_q}} = {<<5{din_q}}; + {<<5{dout_bhs_ls_w}} = {<<5{din_w}}; - // Stream operator: >> - // Location: both sides of assignment - { >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}}; - { >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}}; - { >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}}; + // Stream operator: >> + // Location: both sides of assignment + {>>5{dout_bhs_rs_i}} = {>>5{din_i}}; + {>>5{dout_bhs_rs_q}} = {>>5{din_q}}; + {>>5{dout_bhs_rs_w}} = {>>5{din_w}}; - // Stream operator: << - // Location: both sides of assignment - { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; - { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; - { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; + // Stream operator: << + // Location: both sides of assignment + {<<5{dout_bhs_ls_i}} = {<<5{din_i}}; + {<<5{dout_bhs_ls_q}} = {<<5{din_q}}; + {<<5{dout_bhs_ls_w}} = {<<5{din_w}}; - // Stream operator: << - // Location: rhs of assignment - // - // Verify both fast and slow paths (fast: sliceSize = power of 2) - dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW - dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST + // Stream operator: << + // Location: rhs of assignment + // + // Verify both fast and slow paths (fast: sliceSize = power of 2) + dout_rhs_ls_i_23_3 = {<<3{din_i[22:0]}}; // SLOW + dout_rhs_ls_i_23_4 = {<<4{din_i[22:0]}}; // FAST - dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW - dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST - end + dout_rhs_ls_q_37_3 = {<<3{din_q[36:0]}}; // SLOW + dout_rhs_ls_q_37_4 = {<<4{din_q[36:0]}}; // FAST + end - always @(posedge clk) - begin - if (cyc != 0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; - if (cyc == 1) begin - din_i <= 32'h00_00_00_01; - din_q <= 64'h00_00_00_00_00_00_00_01; - din_w <= 96'h00_00_00_00_00_00_00_00_00_00_00_01; + if (cyc == 1) begin + din_i <= 32'h00_00_00_01; + din_q <= 64'h00_00_00_00_00_00_00_01; + din_w <= 96'h00_00_00_00_00_00_00_00_00_00_00_01; - din_lhs <= 4'b00_01; - end - if (cyc == 2) begin - din_i <= 32'h04_03_02_01; - din_q <= 64'h08_07_06_05_04_03_02_01; - din_w <= 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01; - - din_lhs <= 4'b01_11; - - if (dout_rhs_ls_i != 32'h80_00_00_00) $stop; - if (dout_rhs_ls_q != 64'h80_00_00_00_00_00_00_00) $stop; - if (dout_rhs_ls_w != 96'h80_00_00_00_00_00_00_00_00_00_00_00) $stop; - - if (dout_rhs_rs_i != 32'h00_00_00_01) $stop; - if (dout_rhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; - if (dout_rhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - - if (dout_lhs_ls_a != 2'b01) $stop; - if (dout_lhs_ls_b != 2'b00) $stop; - - if (dout_lhs_rs_a != 2'b00) $stop; - if (dout_lhs_rs_b != 2'b01) $stop; - - if (dout_bhs_rs_i != 32'h00_00_00_01) $stop; - if (dout_bhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - - if (dout_bhs_ls_i != 32'h00_00_00_10) $stop; - if (dout_bhs_ls_q != 64'h00_00_00_00_00_00_01_00) $stop; - if (dout_bhs_ls_w != 96'h00_00_00_00_00_00_00_00_00_00_00_04) $stop; - - if (dout_rhs_ls_i_23_3 != 23'h10_00_00) $stop; - if (dout_rhs_ls_i_23_4 != 23'h08_00_00) $stop; - - if (dout_rhs_ls_q_37_3 != 37'h04_00_00_00_00) $stop; - if (dout_rhs_ls_q_37_4 != 37'h02_00_00_00_00) $stop; - end - if (cyc == 3) begin - // The values below test the strange shift-merge done at the end of - // the fast stream operators. - // All-1s in the bits being streamed should end up as all-1s. - din_i <= 32'h00_7f_ff_ff; - din_q <= 64'h00_00_00_1f_ff_ff_ff_ff; - - if (dout_rhs_ls_i != 32'h80_40_c0_20) $stop; - if (dout_rhs_ls_q != 64'h80_40_c0_20_a0_60_e0_10) $stop; - if (dout_rhs_ls_w != 96'h80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; - - if (dout_rhs_rs_i != 32'h04_03_02_01) $stop; - if (dout_rhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; - if (dout_rhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - - if (dout_bhs_ls_i != 32'h40_30_00_18) $stop; - if (dout_bhs_ls_q != 64'h06_00_c1_81_41_00_c1_80) $stop; - if (dout_bhs_ls_w != 96'h30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; - - if (dout_bhs_rs_i != 32'h04_03_02_01) $stop; - if (dout_bhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - - if (dout_lhs_ls_a != 2'b11) $stop; - if (dout_lhs_ls_b != 2'b01) $stop; - - if (dout_lhs_rs_a != 2'b01) $stop; - if (dout_lhs_rs_b != 2'b11) $stop; - - if (dout_rhs_ls_i_23_3 != 23'h10_08_c0) $stop; - if (dout_rhs_ls_i_23_4 != 23'h08_10_18) $stop; - - if (dout_rhs_ls_q_37_3 != 37'h04_02_30_10_44) $stop; - if (dout_rhs_ls_q_37_4 != 37'h02_04_06_08_0a) $stop; - end - if (cyc == 4) begin - if (dout_rhs_ls_i_23_3 != 23'h7f_ff_ff) $stop; - if (dout_rhs_ls_i_23_4 != 23'h7f_ff_ff) $stop; - - if (dout_rhs_ls_q_37_3 != 37'h1f_ff_ff_ff_ff) $stop; - if (dout_rhs_ls_q_37_4 != 37'h1f_ff_ff_ff_ff) $stop; - end - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + din_lhs <= 4'b00_01; end - end + if (cyc == 2) begin + din_i <= 32'h04_03_02_01; + din_q <= 64'h08_07_06_05_04_03_02_01; + din_w <= 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01; + + din_lhs <= 4'b01_11; + + if (dout_rhs_ls_i != 32'h80_00_00_00) $stop; + if (dout_rhs_ls_q != 64'h80_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_w != 96'h80_00_00_00_00_00_00_00_00_00_00_00) $stop; + + if (dout_rhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_rhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; + + if (dout_lhs_ls_a != 2'b01) $stop; + if (dout_lhs_ls_b != 2'b00) $stop; + + if (dout_lhs_rs_a != 2'b00) $stop; + if (dout_lhs_rs_b != 2'b01) $stop; + + if (dout_bhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_bhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; + + if (dout_bhs_ls_i != 32'h00_00_00_10) $stop; + if (dout_bhs_ls_q != 64'h00_00_00_00_00_00_01_00) $stop; + if (dout_bhs_ls_w != 96'h00_00_00_00_00_00_00_00_00_00_00_04) $stop; + + if (dout_rhs_ls_i_23_3 != 23'h10_00_00) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_00_00) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h04_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_00_00_00_00) $stop; + end + if (cyc == 3) begin + // The values below test the strange shift-merge done at the end of + // the fast stream operators. + // All-1s in the bits being streamed should end up as all-1s. + din_i <= 32'h00_7f_ff_ff; + din_q <= 64'h00_00_00_1f_ff_ff_ff_ff; + + if (dout_rhs_ls_i != 32'h80_40_c0_20) $stop; + if (dout_rhs_ls_q != 64'h80_40_c0_20_a0_60_e0_10) $stop; + if (dout_rhs_ls_w != 96'h80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; + + if (dout_rhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_rhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + + if (dout_bhs_ls_i != 32'h40_30_00_18) $stop; + if (dout_bhs_ls_q != 64'h06_00_c1_81_41_00_c1_80) $stop; + if (dout_bhs_ls_w != 96'h30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; + + if (dout_bhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_bhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + + if (dout_lhs_ls_a != 2'b11) $stop; + if (dout_lhs_ls_b != 2'b01) $stop; + + if (dout_lhs_rs_a != 2'b01) $stop; + if (dout_lhs_rs_b != 2'b11) $stop; + + if (dout_rhs_ls_i_23_3 != 23'h10_08_c0) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_10_18) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h04_02_30_10_44) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_04_06_08_0a) $stop; + end + if (cyc == 4) begin + if (dout_rhs_ls_i_23_3 != 23'h7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_4 != 23'h7f_ff_ff) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_4 != 37'h1f_ff_ff_ff_ff) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v index 260f03628..548216c7e 100644 --- a/test_regress/t/t_stream2.v +++ b/test_regress/t/t_stream2.v @@ -4,81 +4,81 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [67:0] left; // From test of Test.v - wire [67:0] right; // From test of Test.v - // End of automatics + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [67:0] left; // From test of Test.v + wire [67:0] right; // From test of Test.v + // End of automatics - wire [6:0] amt = crc[6:0]; - wire [67:0] in = {crc[3:0], crc[63:0]}; + wire [6:0] amt = crc[6:0]; + wire [67:0] in = {crc[3:0], crc[63:0]}; - Test test (/*AUTOINST*/ - // Outputs - .left (left[67:0]), - .right (right[67:0]), - // Inputs - .amt (amt[6:0]), - .in (in[67:0])); + Test test ( /*AUTOINST*/ + // Outputs + .left(left[67:0]), + .right(right[67:0]), + // Inputs + .amt(amt[6:0]), + .in(in[67:0]) + ); - wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} - ^ right[63:0] ^ {60'h0, right[67:64]}); + wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} ^ right[63:0] ^ {60'h0, right[67:64]}); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", - $time, cyc, crc, result, amt, left, right); + $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", $time, cyc, crc, result, + amt, left, right); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h0da01049b480c38a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h0da01049b480c38a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - left, right, - // Inputs - amt, in - ); +module Test ( /*AUTOARG*/ + // Outputs + left, + right, + // Inputs + amt, + in +); - input [6:0] amt; - input [67:0] in; + input [6:0] amt; + input [67:0] in; - // amt must be constant - output wire [67:0] left; - output wire [67:0] right; - assign right = { << 33 {in}}; - assign left = { >> 33 {in}}; + // amt must be constant + output wire [67:0] left; + output wire [67:0] right; + assign right = {<<33{in}}; + assign left = {>>33{in}}; endmodule diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v index 766f5f2f3..c6b226c5c 100644 --- a/test_regress/t/t_stream3.v +++ b/test_regress/t/t_stream3.v @@ -4,98 +4,101 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - /*AUTOWIRE*/ + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + /*AUTOWIRE*/ - generate - for (genvar width=1; width<=16; width++) begin - for (genvar amt=1; amt<=width; amt++) begin - Test #(.WIDTH(width), - .AMT(amt)) - test (.ins(crc[width-1:0])); - end + generate + for (genvar width = 1; width <= 16; width++) begin + for (genvar amt = 1; amt <= width; amt++) begin + Test #( + .WIDTH(width), + .AMT(amt) + ) test ( + .ins(crc[width-1:0]) + ); end - endgenerate + end + endgenerate - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x\n", - $time, cyc, crc); + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Inputs - ins - ); +module Test ( /*AUTOARG*/ + // Inputs + ins +); - parameter WIDTH = 1; - parameter AMT = 1; + parameter WIDTH = 1; + parameter AMT = 1; - input [WIDTH-1:0] ins; - reg [WIDTH-1:0] got; - reg [WIDTH-1:0] expec; - int istart; - int bitn; - int ostart; + input [WIDTH-1:0] ins; + reg [WIDTH-1:0] got; + reg [WIDTH-1:0] expec; + int istart; + int bitn; + int ostart; - always @* begin - got = { << AMT {ins}}; + always @* begin + got = {<= 0 && (ostart+bitn) < WIDTH && (ostart+bitn) >= 0) begin - expec[ostart+bitn] = ins[istart+bitn]; - end - end + expec[ostart+bitn] = ins[istart+bitn]; + end end + end `ifdef TEST_VERBOSE - $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); + $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, + got, AMT, WIDTH, ins); `endif - `checkh(got, expec); - end + `checkh(got, expec); + end endmodule diff --git a/test_regress/t/t_stream4.v b/test_regress/t/t_stream4.v index 4a5fa7e56..e38d40e47 100644 --- a/test_regress/t/t_stream4.v +++ b/test_regress/t/t_stream4.v @@ -4,39 +4,37 @@ // SPDX-FileCopyrightText: 2021 Adrien Le Masle // SPDX-License-Identifier: CC0-1.0 -//module t; -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - logic [63:0] din; - logic [63:0] dout; + logic [63:0] din; + logic [63:0] dout; - always_comb begin - dout = {<<8{din}}; - end + always_comb begin + dout = {<<8{din}}; + end - always @(posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; - if (cyc == 1) begin - din <= 64'h1122334455667788; - end - - if (cyc == 2) begin - if (dout != 64'h8877665544332211) $stop; - end - - if (cyc == 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 1) begin + din <= 64'h1122334455667788; end - end + + if (cyc == 2) begin + if (dout != 64'h8877665544332211) $stop; + end + + if (cyc == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_stream5.v b/test_regress/t/t_stream5.v index 9dce11cae..a8cad2eb6 100644 --- a/test_regress/t/t_stream5.v +++ b/test_regress/t/t_stream5.v @@ -6,41 +6,41 @@ module t; - logic [15:0] i16; - logic [15:0] o16; - logic [3:0][3:0] p16; - logic [31:0] i32; - logic [31:0] o32; - logic [7:0][3:0] p32; - logic [63:0] i64; - logic [63:0] o64; - logic [15:0][3:0] p64; + logic [15:0] i16; + logic [15:0] o16; + logic [3:0][3:0] p16; + logic [31:0] i32; + logic [31:0] o32; + logic [7:0][3:0] p32; + logic [63:0] i64; + logic [63:0] o64; + logic [15:0][3:0] p64; - always_comb begin - o16 = {<<4{i16}}; - p16 = {<<4{i16}}; - o32 = {<<4{i32}}; - p32 = {<<4{i32}}; - o64 = {<<4{i64}}; - p64 = {<<4{i64}}; - end + always_comb begin + o16 = {<<4{i16}}; + p16 = {<<4{i16}}; + o32 = {<<4{i32}}; + p32 = {<<4{i32}}; + o64 = {<<4{i64}}; + p64 = {<<4{i64}}; + end - initial begin - i16 = 16'hfade; - i32 = 32'hcafefade; - i64 = 64'hdeaddeedcafefade; - #100ns; - $display("o16=0x%h p16=0x%h i16=0x%h", o16, p16, i16); - if (o16 != 16'hEDAF) $stop; - if (p16 != 16'hEDAF) $stop; - $display("o32=0x%h p32=0x%h i32=0x%h", o32, p32, i32); - if (o32 != 32'hEDAFEFAC) $stop; - if (p32 != 32'hEDAFEFAC) $stop; - $display("o64=0x%h p64=0x%h i64=0x%h", o64, p64, i64); - if (o64 != 64'hEDAFEFACDEEDDAED) $stop; - if (p64 != 64'hEDAFEFACDEEDDAED) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + i16 = 16'hfade; + i32 = 32'hcafefade; + i64 = 64'hdeaddeedcafefade; + #100ns; + $display("o16=0x%h p16=0x%h i16=0x%h", o16, p16, i16); + if (o16 != 16'hEDAF) $stop; + if (p16 != 16'hEDAF) $stop; + $display("o32=0x%h p32=0x%h i32=0x%h", o32, p32, i32); + if (o32 != 32'hEDAFEFAC) $stop; + if (p32 != 32'hEDAFEFAC) $stop; + $display("o64=0x%h p64=0x%h i64=0x%h", o64, p64, i64); + if (o64 != 64'hEDAFEFACDEEDDAED) $stop; + if (p64 != 64'hEDAFEFACDEEDDAED) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_stream_dynamic.v b/test_regress/t/t_stream_dynamic.v index b278e061a..e144fb4ca 100644 --- a/test_regress/t/t_stream_dynamic.v +++ b/test_regress/t/t_stream_dynamic.v @@ -4,201 +4,201 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on typedef enum bit [5:0] { - A = 6'b111000, - B = 6,b111111 + A = 6'b111000, + B = 6, + b111111 } enum_t; module t; - task test1; - bit arr[]; - bit [1:0] arr2[$]; - bit [5:0] arr6[$]; - bit [5:0] bit6; - bit [5:0] ans; - bit [3:0] arr4[]; - bit [7:0] arr8[]; - bit [63:0] arr64[]; - bit [159:0] arr160[]; - bit [63:0] bit64; - bit [99:0] bit100; - bit [319:0] bit320; - enum_t ans_enum; + task test1; + bit arr[]; + bit [1:0] arr2[$]; + bit [5:0] arr6[$]; + bit [5:0] bit6; + bit [5:0] ans; + bit [3:0] arr4[]; + bit [7:0] arr8[]; + bit [63:0] arr64[]; + bit [159:0] arr160[]; + bit [63:0] bit64; + bit [99:0] bit100; + bit [319:0] bit320; + enum_t ans_enum; - bit6 = 6'b111000; - arr4 = '{25{4'b1000}}; - arr8 = '{8{8'b00110011}}; - arr64 = '{5{64'h0123456789abcdef}}; - arr160 = '{2{160'h0123456789abcdef0123456789abcdef01234567}}; + bit6 = 6'b111000; + arr4 = '{25{4'b1000}}; + arr8 = '{8{8'b00110011}}; + arr64 = '{5{64'h0123456789abcdef}}; + arr160 = '{2{160'h0123456789abcdef0123456789abcdef01234567}}; - { >> bit {arr}} = bit6; - `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); - ans = { >> bit {arr} }; - `checkh(ans, bit6); + {>>bit{arr}} = bit6; + `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); + ans = {>>bit{arr}}; + `checkh(ans, bit6); - ans_enum = enum_t'({ >> bit {arr} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({>>bit{arr}}); + `checkh(ans_enum, bit6); - { << bit {arr}} = bit6; - `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); + {<> bit[1:0] {arr2}} = bit6; - `checkp(arr2, "'{'h3, 'h2, 'h0}"); + // This set flags errors on other simulators + {>>bit[1:0] {arr2}} = bit6; + `checkp(arr2, "'{'h3, 'h2, 'h0}"); - ans = { >> bit[1:0] {arr2} }; - `checkh(ans, bit6); + ans = {>>bit[1:0] {arr2}}; + `checkh(ans, bit6); - ans_enum = enum_t'({ >> bit[1:0] {arr2} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({>>bit[1:0] {arr2}}); + `checkh(ans_enum, bit6); - { << bit[1:0] {arr2}} = bit6; - `checkp(arr2, "'{'h0, 'h2, 'h3}"); + {<> bit [5:0] {arr6} } = bit6; - `checkp(arr6, "'{'h38}"); + {>>bit[5:0] {arr6}} = bit6; + `checkp(arr6, "'{'h38}"); - ans = { >> bit[5:0] {arr6} }; - `checkh(ans, bit6); + ans = {>>bit[5:0] {arr6}}; + `checkh(ans, bit6); - ans_enum = enum_t'({ >> bit[5:0] {arr6} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({>>bit[5:0] {arr6}}); + `checkh(ans_enum, bit6); - { << bit [5:0] {arr6} } = bit6; - `checkp(arr6, "'{'h38}"); + {<> bit {arr8} }; - `checkh(bit64[7:0], 8'b00110011); - bit64 = { << bit {arr8} }; - `checkh(bit64[7:0], 8'b11001100); + bit64 = {>>bit{arr8}}; + `checkh(bit64[7:0], 8'b00110011); + bit64 = {<> bit {arr8} } = bit64; - `checkh(arr8[0], 8'b11001100); - { << bit {arr8} } = bit64; - `checkh(arr8[0], 8'b00110011); + {>>bit{arr8}} = bit64; + `checkh(arr8[0], 8'b11001100); + {<> bit {arr4} }; - `checkh(bit100[3:0], 4'b1000); - bit100 = { << bit {arr4} }; - `checkh(bit100[3:0], 4'b0001); + bit100 = {>>bit{arr4}}; + `checkh(bit100[3:0], 4'b1000); + bit100 = {<> bit {arr4} } = bit100; - `checkh(arr4[0], 4'b0001); - { << bit {arr4} } = bit100; - `checkh(arr4[0], 4'b1000); + {>>bit{arr4}} = bit100; + `checkh(arr4[0], 4'b0001); + {<> byte {arr64} }; - `checkh(bit320[63:0], 64'h0123456789abcdef); - bit320 = { << byte {arr64} }; - `checkh(bit320[63:0], 64'hefcdab8967452301); + bit320 = {>>byte{arr64}}; + `checkh(bit320[63:0], 64'h0123456789abcdef); + bit320 = {<> byte {arr64} } = bit320; - `checkh(arr64[0], 64'hefcdab8967452301); - { << byte {arr64} } = bit320; - `checkh(arr64[0], 64'h0123456789abcdef); + {>>byte{arr64}} = bit320; + `checkh(arr64[0], 64'hefcdab8967452301); + {<> bit {arr64} } = bit64; - `checkh(arr64[0], 64'hcccccccccccccccc); - { << bit {arr64} } = bit64; - `checkh(arr64[0], 64'h3333333333333333); + {>>bit{arr64}} = bit64; + `checkh(arr64[0], 64'hcccccccccccccccc); + {<> bit {arr64} }; - `checkh(bit64, 64'h3333333333333333); - bit64 = { << bit {arr64} }; - `checkh(bit64, 64'hcccccccccccccccc); + bit64 = {>>bit{arr64}}; + `checkh(bit64, 64'h3333333333333333); + bit64 = {<> byte {arr160} }; - `checkh(bit320[159:0], 160'h0123456789abcdef0123456789abcdef01234567); - bit320 = { << byte {arr160} }; - `checkh(bit320[159:0], 160'h67452301efcdab8967452301efcdab8967452301); + bit320 = {>>byte{arr160}}; + `checkh(bit320[159:0], 160'h0123456789abcdef0123456789abcdef01234567); + bit320 = {<> byte {arr160} } = bit320; - `checkh(arr160[0], 160'h67452301efcdab8967452301efcdab8967452301); - { << byte {arr160} } = bit320; - `checkh(arr160[0], 160'h0123456789abcdef0123456789abcdef01234567); - endtask + {>>byte{arr160}} = bit320; + `checkh(arr160[0], 160'h67452301efcdab8967452301efcdab8967452301); + {<>{bits}}; - `checkh(word, 64'hfadecafedeadbeef); - word = {<<8{bits}}; - `checkh(word, 64'hefbeaddefecadefa); + // Using packed bits + $display("Test2"); + bits = {8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; + word = {>>{bits}}; + `checkh(word, 64'hfadecafedeadbeef); + word = {<<8{bits}}; + `checkh(word, 64'hefbeaddefecadefa); - // Using byte unpacked array - unpack = '{8'hfa, 8'hde, 8'hca, 8'hfe, - 8'hde, 8'had, 8'hbe, 8'hef}; - `checkh(unpack[0], 8'hfa); - `checkh(unpack[7], 8'hef); - word = {>>{unpack}}; - `checkh(word, 64'hfadecafedeadbeef); - word = {<<8{unpack}}; - `checkh(word, 64'hefbeaddefecadefa); - endtask + // Using byte unpacked array + unpack = '{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; + `checkh(unpack[0], 8'hfa); + `checkh(unpack[7], 8'hef); + word = {>>{unpack}}; + `checkh(word, 64'hfadecafedeadbeef); + word = {<<8{unpack}}; + `checkh(word, 64'hefbeaddefecadefa); + endtask - task test3; - byte dyn8 []; // [0] is left-most for purposes of streaming - longint word; // [63] is left-most for purposes of streaming - // verilator lint_off ASCRANGE - bit [0:63] rbits; // [63] is still left-most for purposes of streaming - // verilator lint_on ASCRANGE + task test3; + byte dyn8[]; // [0] is left-most for purposes of streaming + longint word; // [63] is left-most for purposes of streaming + // verilator lint_off ASCRANGE + bit [0:63] rbits; // [63] is still left-most for purposes of streaming + // verilator lint_on ASCRANGE - // Using byte dynamic array - dyn8 = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, - 8'hde, 8'had, 8'hbe, 8'hef}); - `checkh(dyn8[0], 8'hfa); - `checkh(dyn8[7], 8'hef); - word = {>>{dyn8}}; - `checkh(word, 64'hfadecafedeadbeef); - word = {<<1{dyn8}}; - `checkh(word, 64'hf77db57b7f537b5f); - word = {<<8{dyn8}}; - `checkh(word, 64'hefbeaddefecadefa); + // Using byte dynamic array + dyn8 = new[8] ('{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}); + `checkh(dyn8[0], 8'hfa); + `checkh(dyn8[7], 8'hef); + word = {>>{dyn8}}; + `checkh(word, 64'hfadecafedeadbeef); + word = {<<1{dyn8}}; + `checkh(word, 64'hf77db57b7f537b5f); + word = {<<8{dyn8}}; + `checkh(word, 64'hefbeaddefecadefa); - rbits = {>>{dyn8}}; - `checkh(rbits, 64'hfadecafedeadbeef); - rbits = {<<1{dyn8}}; - `checkh(rbits, 64'hf77db57b7f537b5f); - rbits = {<<8{dyn8}}; - `checkh(rbits, 64'hefbeaddefecadefa); - endtask + rbits = {>>{dyn8}}; + `checkh(rbits, 64'hfadecafedeadbeef); + rbits = {<<1{dyn8}}; + `checkh(rbits, 64'hf77db57b7f537b5f); + rbits = {<<8{dyn8}}; + `checkh(rbits, 64'hefbeaddefecadefa); + endtask - initial begin - test1(); - test2(); - test3(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + test1(); + test2(); + test3(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_stream_integer_type.v b/test_regress/t/t_stream_integer_type.v index 7b0d6945d..d548e4178 100644 --- a/test_regress/t/t_stream_integer_type.v +++ b/test_regress/t/t_stream_integer_type.v @@ -17,331 +17,331 @@ module t; - logic [31:0] packed_data_32; - logic [31:0] packed_data_32_ref; + logic [31:0] packed_data_32; + logic [31:0] packed_data_32_ref; - logic [31:0] v_packed_data_32; - logic [31:0] v_packed_data_32_ref; + logic [31:0] v_packed_data_32; + logic [31:0] v_packed_data_32_ref; - logic [63:0] packed_data_64; - logic [63:0] packed_data_64_ref; + logic [63:0] packed_data_64; + logic [63:0] packed_data_64_ref; - logic [63:0] v_packed_data_64; - logic [63:0] v_packed_data_64_ref; + logic [63:0] v_packed_data_64; + logic [63:0] v_packed_data_64_ref; - logic [127:0] packed_data_128; - logic [127:0] packed_data_128_ref; + logic [127:0] packed_data_128; + logic [127:0] packed_data_128_ref; - logic [127:0] v_packed_data_128; - logic [127:0] v_packed_data_128_ref; + logic [127:0] v_packed_data_128; + logic [127:0] v_packed_data_128_ref; - logic [127:0] packed_data_128_i; - logic [127:0] packed_data_128_i_ref; + logic [127:0] packed_data_128_i; + logic [127:0] packed_data_128_i_ref; - logic [255:0] packed_data_256; - logic [255:0] packed_data_256_ref; + logic [255:0] packed_data_256; + logic [255:0] packed_data_256_ref; - logic [255:0] packed_time_256; - logic [255:0] packed_time_256_ref; + logic [255:0] packed_time_256; + logic [255:0] packed_time_256_ref; - logic [511:0] v_packed_data_512; - logic [511:0] v_packed_data_512_ref; - // - //integer_atom_type - // - byte byte_in[4]; - byte byte_out[4]; - // - int int_in[4]; - int int_out[4]; - // - // - shortint shortint_in[4]; - shortint shortint_out[4]; - // - longint longint_in[4]; - longint longint_out[4]; - // - integer integer_in[4]; - integer integer_out[4]; - // - time time_in[4]; - time time_out[4]; + logic [511:0] v_packed_data_512; + logic [511:0] v_packed_data_512_ref; + // + //integer_atom_type + // + byte byte_in[4]; + byte byte_out[4]; + // + int int_in[4]; + int int_out[4]; + // + // + shortint shortint_in[4]; + shortint shortint_out[4]; + // + longint longint_in[4]; + longint longint_out[4]; + // + integer integer_in[4]; + integer integer_out[4]; + // + time time_in[4]; + time time_out[4]; - //integer_vector_type - typedef bit [7:0] test_byte; - typedef bit [15:0] test_short; - typedef bit [31:0] test_word; - typedef bit [63:0] test_long; - typedef bit [127:0] test_wide; - // - test_byte bit_in[4]; - test_byte bit_out[4]; - // - test_short logic_in[4]; - test_short logic_out[4]; - // - test_word reg_in[4]; - test_word reg_out[4]; - // - test_wide wide_in[4]; - test_wide wide_out[4]; - // - string error = ""; + //integer_vector_type + typedef bit [7:0] test_byte; + typedef bit [15:0] test_short; + typedef bit [31:0] test_word; + typedef bit [63:0] test_long; + typedef bit [127:0] test_wide; + // + test_byte bit_in[4]; + test_byte bit_out[4]; + // + test_short logic_in[4]; + test_short logic_out[4]; + // + test_word reg_in[4]; + test_word reg_out[4]; + // + test_wide wide_in[4]; + test_wide wide_out[4]; + // + string error = ""; - initial begin - //init - $write("*-* START t_stream_pack_unpack *-*\n"); - error = test_integer_type_1(error); + initial begin + //init + $write("*-* START t_stream_pack_unpack *-*\n"); + error = test_integer_type_1(error); `ifdef TEST_VERBOSE - print_all_data("test_integer_type_1"); + print_all_data("test_integer_type_1"); `endif - error = test_integer_type_2(error); + error = test_integer_type_2(error); `ifdef TEST_VERBOSE - print_all_data("test_integer_type_2"); + print_all_data("test_integer_type_2"); `endif - // - if (error == "") $write("*-* All Finished *-*\n"); - else begin - $write("*-* TEST failed error %s *-*:\n", error); - print_data_error(error); - end - $finish; - end // initial begin + // + if (error == "") $write("*-* All Finished *-*\n"); + else begin + $write("*-* TEST failed error %s *-*:\n", error); + print_data_error(error); + end + $finish; + end // initial begin - function string test_integer_type_1(string error); - automatic string error_; - automatic string function_name_ = "test_integer_type_1"; + function string test_integer_type_1(string error); + automatic string error_; + automatic string function_name_ = "test_integer_type_1"; - error_ = error; - if (error_ == "") begin - clean_packed_data (); - init_data(); - //pack - packed_data_32 = {<<8{byte_in}}; - packed_data_64 = {<<16{shortint_in}}; - packed_data_128 = {<<32{int_in}}; - packed_data_128_i = {<<32{integer_in}}; - packed_data_256 = {<<64{longint_in}}; - packed_time_256 = {<<64{time_in}}; - v_packed_data_32 = {<<8{bit_in}}; - v_packed_data_64 = {<<16{logic_in}}; - v_packed_data_128 = {<<32{reg_in}}; - v_packed_data_512 = {<<32{wide_in}}; - //unpack - {<<8{byte_out}} = packed_data_32; - {<<16{shortint_out}} = packed_data_64; - {<<32{int_out}} = packed_data_128; - {<<32{integer_out}} = packed_data_128_i; - {<<64{longint_out}} = packed_data_256; - {<<64{time_out}} = packed_time_256; - {<<8{bit_out}} = v_packed_data_32; - {<<16{logic_out}} = v_packed_data_64; - {<<32{reg_out}} = v_packed_data_128; - {<<32{wide_out}} = v_packed_data_512; - error_ = comp_in_out(); - end // if (error == "") - return error_; - endfunction : test_integer_type_1 + error_ = error; + if (error_ == "") begin + clean_packed_data (); + init_data(); + //pack + packed_data_32 = {<<8{byte_in}}; + packed_data_64 = {<<16{shortint_in}}; + packed_data_128 = {<<32{int_in}}; + packed_data_128_i = {<<32{integer_in}}; + packed_data_256 = {<<64{longint_in}}; + packed_time_256 = {<<64{time_in}}; + v_packed_data_32 = {<<8{bit_in}}; + v_packed_data_64 = {<<16{logic_in}}; + v_packed_data_128 = {<<32{reg_in}}; + v_packed_data_512 = {<<32{wide_in}}; + //unpack + {<<8{byte_out}} = packed_data_32; + {<<16{shortint_out}} = packed_data_64; + {<<32{int_out}} = packed_data_128; + {<<32{integer_out}} = packed_data_128_i; + {<<64{longint_out}} = packed_data_256; + {<<64{time_out}} = packed_time_256; + {<<8{bit_out}} = v_packed_data_32; + {<<16{logic_out}} = v_packed_data_64; + {<<32{reg_out}} = v_packed_data_128; + {<<32{wide_out}} = v_packed_data_512; + error_ = comp_in_out(); + end // if (error == "") + return error_; + endfunction : test_integer_type_1 - function string test_integer_type_2(string error); - automatic string error_; - automatic string function_name_ = "test_integer_type_2"; - error_ = error; - if (error_ == "") begin - clean_packed_data (); - init_data(); - //pack - packed_data_32 = {<>{qs}}; - if (s != "") $stop; + string qs[$]; + string as[]; + string s; + initial begin + s = {>>{qs}}; + if (s != "") $stop; - s = {>>{as}}; - if (s != "") $stop; + s = {>>{as}}; + if (s != "") $stop; - qs = '{"ab", "c", ""}; - s = {>>{qs}}; - if (s != "abc") $stop; + qs = '{"ab", "c", ""}; + s = {>>{qs}}; + if (s != "abc") $stop; - as = new[3]; - as[0] = "abcd"; - as[2] = "ef"; - s = {>>{as}}; - if (s != "abcdef") $stop; + as = new[3]; + as[0] = "abcd"; + as[2] = "ef"; + s = {>>{as}}; + if (s != "abcdef") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_stream_struct.v b/test_regress/t/t_stream_struct.v index 6cbec64b3..dbfcee89c 100644 --- a/test_regress/t/t_stream_struct.v +++ b/test_regress/t/t_stream_struct.v @@ -4,71 +4,69 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [63:0] in = crc[63:0]; + // Take CRC data and apply to testblock inputs + wire [63:0] in = crc[63:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [63:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [63:0] out; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .out (out[63:0]), - // Inputs - .in (in[63:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[63:0]), + // Inputs + .in(in[63:0]) + ); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x out=%x\n", $time, cyc, crc, out); + $write("[%0t] cyc==%0d crc=%x out=%x\n", $time, cyc, crc, out); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= out ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h29271cf844d6f90c - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= out ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h29271cf844d6f90c + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input wire [63:0] in, - output logic [63:0] out); + input wire [63:0] in, + output logic [63:0] out +); - typedef struct packed { - logic [63:0] dummy; - } data_t; + typedef struct packed {logic [63:0] dummy;} data_t; - function automatic logic [63:0] reverse(data_t d); - return {<<{d}}; - endfunction + function automatic logic [63:0] reverse(data_t d); + return {<<{d}}; + endfunction - assign out = reverse(in); + assign out = reverse(in); endmodule diff --git a/test_regress/t/t_stream_trace.v b/test_regress/t/t_stream_trace.v index bac5e8ab7..7bebd0165 100644 --- a/test_regress/t/t_stream_trace.v +++ b/test_regress/t/t_stream_trace.v @@ -4,23 +4,25 @@ // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - integer cyc = 0; +module t ( + input clk +); - logic [2:0] cmd_ready; - logic cmd_ready_unpack[3]; - logic cmd_ready_o[3]; + integer cyc = 0; - assign cmd_ready = {1'b1, clk, ~clk}; - assign cmd_ready_unpack = {<<{cmd_ready}}; - assign cmd_ready_o = cmd_ready_unpack; + logic [2:0] cmd_ready; + logic cmd_ready_unpack[3]; + logic cmd_ready_o[3]; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + assign cmd_ready = {1'b1, clk, ~clk}; + assign cmd_ready_unpack = {<<{cmd_ready}}; + assign cmd_ready_o = cmd_ready_unpack; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_stream_unpack.v b/test_regress/t/t_stream_unpack.v index 924f91e86..ac7b8c748 100644 --- a/test_regress/t/t_stream_unpack.v +++ b/test_regress/t/t_stream_unpack.v @@ -4,286 +4,288 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on typedef enum bit [5:0] { - A = 6'b111000, - B = 6,b111111 + A = 6'b111000, + B = 6,b111111 } enum_t; module t; - initial begin - typedef bit [5:0] bit6_t; - typedef bit bit6_unpacked_t[6]; - automatic bit6_unpacked_t arr; - automatic bit [1:0] arr2[3]; - automatic bit6_t arr6[1]; - automatic bit6_t [0:0] parr6; - automatic bit6_t bit6 = 6'b111000; - automatic bit [5:0] ans; - automatic bit [2:0][1:0] ans_packed; - automatic enum_t ans_enum; - automatic logic [1:0] a [3] = {1, 0, 3}; - automatic logic [1:0] b [3] = {1, 2, 0}; - automatic logic c [4] = {1, 1, 0, 0}; - automatic logic [15:0] d; - automatic logic [3:0] e [2]; - automatic logic f [8]; - automatic logic [1:0][7:0] g; - automatic logic [1:0][1:0][3:0] h; - automatic byte i []; - automatic longint j; - automatic int k; - automatic int l []; - automatic logic [127:0] m; - automatic longint n []; - automatic logic [255:0] o; - automatic logic [127:0] p[]; + initial begin + typedef bit [5:0] bit6_t; + typedef bit bit6_unpacked_t[6]; + automatic bit6_unpacked_t arr; + automatic bit [1:0] arr2[3]; + automatic bit6_t arr6[1]; + automatic bit6_t [0:0] parr6; + automatic bit6_t bit6 = 6'b111000; + automatic bit [5:0] ans; + automatic bit [2:0][1:0] ans_packed; + automatic enum_t ans_enum; + automatic logic [1:0] a [3] = {1, 0, 3}; + automatic logic [1:0] b [3] = {1, 2, 0}; + automatic logic c [4] = {1, 1, 0, 0}; + automatic logic [15:0] d; + automatic logic [3:0] e [2]; + automatic logic f [8]; + automatic logic [1:0][7:0] g; + automatic logic [1:0][1:0][3:0] h; + automatic byte i []; + automatic longint j; + automatic int k; + automatic int l []; + automatic logic [127:0] m; + automatic longint n []; + automatic logic [255:0] o; + automatic logic [127:0] p[]; - { >> bit {arr}} = bit6; - `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); + { >> bit {arr}} = bit6; + `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); - arr = { >> bit {bit6}}; - `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); + arr = { >> bit {bit6}}; + `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); - ans = { >> bit {arr} }; - `checkh(ans, bit6); + ans = { >> bit {arr} }; + `checkh(ans, bit6); - { >> bit {ans}} = arr; - `checkh(ans, bit6); + { >> bit {ans}} = arr; + `checkh(ans, bit6); - ans_packed = { >> bit {arr} }; - `checkh(ans_packed, bit6); + ans_packed = { >> bit {arr} }; + `checkh(ans_packed, bit6); - { >> bit {ans_packed}} = arr; - `checkh(ans_packed, bit6); + { >> bit {ans_packed}} = arr; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ >> bit {arr} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ >> bit {arr} }); + `checkh(ans_enum, bit6); - { << bit {arr}} = bit6; - `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); + { << bit {arr}} = bit6; + `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); - arr = { << bit {bit6}}; - `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); + arr = { << bit {bit6}}; + `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); - ans = { << bit {arr} }; - `checkh(ans, bit6); + ans = { << bit {arr} }; + `checkh(ans, bit6); - { << bit {ans} } = arr; - `checkh(ans, bit6); + { << bit {ans} } = arr; + `checkh(ans, bit6); - ans_packed = { << bit {arr} }; - `checkh(ans_packed, bit6); + ans_packed = { << bit {arr} }; + `checkh(ans_packed, bit6); - { << bit {ans_packed} } = arr; - `checkh(ans_packed, bit6); + { << bit {ans_packed} } = arr; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ << bit {arr} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ << bit {arr} }); + `checkh(ans_enum, bit6); - { >> bit[1:0] {arr2}} = bit6; - `checkp(arr2, "'{'h3, 'h2, 'h0}"); + { >> bit[1:0] {arr2}} = bit6; + `checkp(arr2, "'{'h3, 'h2, 'h0}"); - arr2 = { >> bit[1:0] {bit6}}; - `checkp(arr2, "'{'h3, 'h2, 'h0}"); + arr2 = { >> bit[1:0] {bit6}}; + `checkp(arr2, "'{'h3, 'h2, 'h0}"); - ans = { >> bit[1:0] {arr2} }; - `checkh(ans, bit6); + ans = { >> bit[1:0] {arr2} }; + `checkh(ans, bit6); - { >> bit[1:0] {ans} } = arr2; - `checkh(ans, bit6); + { >> bit[1:0] {ans} } = arr2; + `checkh(ans, bit6); - ans_packed = { >> bit[1:0] {arr2} }; - `checkh(ans_packed, bit6); + ans_packed = { >> bit[1:0] {arr2} }; + `checkh(ans_packed, bit6); - { >> bit[1:0] {ans_packed} } = arr2; - `checkh(ans_packed, bit6); + { >> bit[1:0] {ans_packed} } = arr2; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ >> bit[1:0] {arr2} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ >> bit[1:0] {arr2} }); + `checkh(ans_enum, bit6); - { << bit[1:0] {arr2}} = bit6; - `checkp(arr2, "'{'h0, 'h2, 'h3}"); + { << bit[1:0] {arr2}} = bit6; + `checkp(arr2, "'{'h0, 'h2, 'h3}"); - ans = { << bit[1:0] {arr2} }; - `checkh(ans, bit6); + ans = { << bit[1:0] {arr2} }; + `checkh(ans, bit6); - { << bit[1:0] {ans} } = arr2; - `checkh(ans, bit6); + { << bit[1:0] {ans} } = arr2; + `checkh(ans, bit6); - ans_packed = { << bit[1:0] {arr2} }; - `checkh(ans_packed, bit6); + ans_packed = { << bit[1:0] {arr2} }; + `checkh(ans_packed, bit6); - { << bit[1:0] {ans_packed} } = arr2; - `checkh(ans_packed, bit6); + { << bit[1:0] {ans_packed} } = arr2; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ << bit[1:0] {arr2} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ << bit[1:0] {arr2} }); + `checkh(ans_enum, bit6); - { >> bit [5:0] {arr6} } = bit6; - `checkp(arr6, "'{'h38}"); + { >> bit [5:0] {arr6} } = bit6; + `checkp(arr6, "'{'h38}"); - arr6 = { >> bit [5:0] {bit6}}; - `checkp(arr6, "'{'h38}"); + arr6 = { >> bit [5:0] {bit6}}; + `checkp(arr6, "'{'h38}"); - ans = { >> bit[5:0] {arr6} }; - `checkh(ans, bit6); + ans = { >> bit[5:0] {arr6} }; + `checkh(ans, bit6); - { >> bit[5:0] {ans} } = arr6; - `checkh(ans, bit6); + { >> bit[5:0] {ans} } = arr6; + `checkh(ans, bit6); - ans_packed = { >> bit[5:0] {arr6} }; - `checkh(ans_packed, bit6); + ans_packed = { >> bit[5:0] {arr6} }; + `checkh(ans_packed, bit6); - { >> bit[5:0] {ans_packed} } = arr6; - `checkh(ans_packed, bit6); + { >> bit[5:0] {ans_packed} } = arr6; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ >> bit[5:0] {arr6} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ >> bit[5:0] {arr6} }); + `checkh(ans_enum, bit6); - { << bit [5:0] {arr6} } = bit6; - `checkp(arr6, "'{'h38}"); + { << bit [5:0] {arr6} } = bit6; + `checkp(arr6, "'{'h38}"); - arr6 = { << bit [5:0] {bit6}}; - `checkp(arr6, "'{'h38}"); + arr6 = { << bit [5:0] {bit6}}; + `checkp(arr6, "'{'h38}"); - ans = { << bit[5:0] {arr6} }; - `checkh(ans, bit6); + ans = { << bit[5:0] {arr6} }; + `checkh(ans, bit6); - { << bit[5:0] {ans} } = arr6; - `checkh(ans, bit6); + { << bit[5:0] {ans} } = arr6; + `checkh(ans, bit6); - ans_packed = { << bit[5:0] {arr6} }; - `checkh(ans_packed, bit6); + ans_packed = { << bit[5:0] {arr6} }; + `checkh(ans_packed, bit6); - { << bit[5:0] {ans_packed} } = arr6; - `checkh(ans_packed, bit6); + { << bit[5:0] {ans_packed} } = arr6; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ << bit[5:0] {arr6} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ << bit[5:0] {arr6} }); + `checkh(ans_enum, bit6); - { >> bit [5:0] {parr6} } = bit6; - `checkh(parr6, bit6); + { >> bit [5:0] {parr6} } = bit6; + `checkh(parr6, bit6); - parr6 = { >> bit [5:0] {bit6}}; - `checkh(parr6, bit6); + parr6 = { >> bit [5:0] {bit6}}; + `checkh(parr6, bit6); - ans = { >> bit[5:0] {parr6} }; - `checkh(ans, bit6); + ans = { >> bit[5:0] {parr6} }; + `checkh(ans, bit6); - { >> bit[5:0] {ans} } = parr6; - `checkh(ans, bit6); + { >> bit[5:0] {ans} } = parr6; + `checkh(ans, bit6); - ans_packed = { >> bit[5:0] {parr6} }; - `checkh(ans_packed, bit6); + ans_packed = { >> bit[5:0] {parr6} }; + `checkh(ans_packed, bit6); - { >> bit[5:0] {ans_packed} } = parr6; - `checkh(ans_packed, bit6); + { >> bit[5:0] {ans_packed} } = parr6; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ >> bit[5:0] {parr6} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ >> bit[5:0] {parr6} }); + `checkh(ans_enum, bit6); - { << bit [5:0] {parr6} } = bit6; - `checkh(parr6, bit6); + { << bit [5:0] {parr6} } = bit6; + `checkh(parr6, bit6); - parr6 = { << bit [5:0] {bit6}}; - `checkh(parr6, bit6); + parr6 = { << bit [5:0] {bit6}}; + `checkh(parr6, bit6); - ans = { << bit[5:0] {parr6} }; - `checkh(ans, bit6); + ans = { << bit[5:0] {parr6} }; + `checkh(ans, bit6); - { << bit[5:0] {ans} } = parr6; - `checkh(ans, bit6); + { << bit[5:0] {ans} } = parr6; + `checkh(ans, bit6); - ans_packed = { << bit[5:0] {parr6} }; - `checkh(ans_packed, bit6); + ans_packed = { << bit[5:0] {parr6} }; + `checkh(ans_packed, bit6); - { << bit[5:0] {ans_packed} } = parr6; - `checkh(ans_packed, bit6); + { << bit[5:0] {ans_packed} } = parr6; + `checkh(ans_packed, bit6); - ans_enum = enum_t'({ << bit[5:0] {parr6} }); - `checkh(ans_enum, bit6); + ans_enum = enum_t'({ << bit[5:0] {parr6} }); + `checkh(ans_enum, bit6); - d = { >> {a, b, c}}; - `checkh(d, 16'b0100110110001100); + d = { >> {a, b, c}}; + `checkh(d, 16'b0100110110001100); - { >> {e, f}} = d; - `checkp(e, "'{'h4, 'hd}"); - `checkp(f, "'{'h1, 'h0, 'h0, 'h0, 'h1, 'h1, 'h0, 'h0}"); + { >> {e, f}} = d; + `checkp(e, "'{'h4, 'hd}"); + `checkp(f, "'{'h1, 'h0, 'h0, 'h0, 'h1, 'h1, 'h0, 'h0}"); - d = { << 4 {a, b, c}}; - `checkh(d, 16'b1100100011010100); + d = { << 4 {a, b, c}}; + `checkh(d, 16'b1100100011010100); - { << 2 {e, f}} = d; - `checkp(e, "'{'h1, 'h7}"); - `checkp(f, "'{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h1, 'h1}"); + { << 2 {e, f}} = d; + `checkp(e, "'{'h1, 'h7}"); + `checkp(f, "'{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h1, 'h1}"); - g = { << 8 {16'hABCD}}; - `checkh(g, 16'hCDAB); + g = { << 8 {16'hABCD}}; + `checkh(g, 16'hCDAB); - h = { << 8 {16'hABCD}}; - `checkh(h, 16'hCDAB); + h = { << 8 {16'hABCD}}; + `checkh(h, 16'hCDAB); - i = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, - 8'hde, 8'had, 8'hbe, 8'hef}); - `checkh(i[0], 8'hfa); - `checkh(i[7], 8'hef); - j = {>>{i}}; - `checkh(j, 64'hfadecafedeadbeef); - j = {<<8{i}}; - `checkh(j, 64'hefbeaddefecadefa); + i = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, + 8'hde, 8'had, 8'hbe, 8'hef}); + `checkh(i[0], 8'hfa); + `checkh(i[7], 8'hef); + j = {>>{i}}; + `checkh(j, 64'hfadecafedeadbeef); + j = {<<8{i}}; + `checkh(j, 64'hefbeaddefecadefa); - i = new[4]('{8'hba, 8'hbe, 8'hfa, 8'hce}); - k = {>>{i}}; - `checkh(k, 32'hbabeface); - k = {<<8{i}}; - `checkh(k, 32'hcefabeba); + i = new[4]('{8'hba, 8'hbe, 8'hfa, 8'hce}); + k = {>>{i}}; + `checkh(k, 32'hbabeface); + k = {<<8{i}}; + `checkh(k, 32'hcefabeba); - i = new[8]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef}); - j = {>>{i}}; - `checkh(j, 64'hbabefacedeadbeef); - j = {<<8{i}}; - `checkh(j, 64'hefbeaddecefabeba); + i = new[8]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef}); + j = {>>{i}}; + `checkh(j, 64'hbabefacedeadbeef); + j = {<<8{i}}; + `checkh(j, 64'hefbeaddecefabeba); - i = new[16]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef, - 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef}); - m = {>>{i}}; - `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); - m = {<<8{i}}; - `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); - - l = new[2]('{32'hbabeface, 32'hdeadbeef}); - j = {>>{l}}; - `checkh(j, 64'hbabefacedeadbeef); - j = {<<8{l}}; - `checkh(j, 64'hefbeaddecefabeba); - - l = new[4]('{32'hbabeface, 32'hdeadbeef, 32'hdeadbeef, 32'hdeadbeef}); - m = {>>{l}}; - `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); - m = {<<8{l}}; - `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); - - n = new[2]('{64'hfadecafedeadbeef, 64'habcd0123456789ab}); - m = {>>{n}}; - `checkh(m, 128'hfadecafedeadbeefabcd0123456789ab); - m = {<<64{n}}; - `checkh(m, 128'habcd0123456789abfadecafedeadbeef); - - p = new[2]('{128'hfadecafedeadbeefabcd0123456789ab, - 128'habcd0123456789abfadecafedeadbeef}); - o = {>>{p}}; - `checkh(o, 256'hfadecafedeadbeefabcd0123456789ababcd0123456789abfadecafedeadbeef); - o = {<<128{p}}; - `checkh(o, 256'habcd0123456789abfadecafedeadbeeffadecafedeadbeefabcd0123456789ab); - {>>{p}} = o; - `checkh(p[0], 128'habcd0123456789abfadecafedeadbeef); - `checkh(p[1], 128'hfadecafedeadbeefabcd0123456789ab); - - $write("*-* All Finished *-*\n"); - $finish; - end + i = new[16]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef, + 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef}); + m = {>>{i}}; + `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); + m = {<<8{i}}; + `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); + + l = new[2]('{32'hbabeface, 32'hdeadbeef}); + j = {>>{l}}; + `checkh(j, 64'hbabefacedeadbeef); + j = {<<8{l}}; + `checkh(j, 64'hefbeaddecefabeba); + + l = new[4]('{32'hbabeface, 32'hdeadbeef, 32'hdeadbeef, 32'hdeadbeef}); + m = {>>{l}}; + `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); + m = {<<8{l}}; + `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); + + n = new[2]('{64'hfadecafedeadbeef, 64'habcd0123456789ab}); + m = {>>{n}}; + `checkh(m, 128'hfadecafedeadbeefabcd0123456789ab); + m = {<<64{n}}; + `checkh(m, 128'habcd0123456789abfadecafedeadbeef); + + p = new[2]('{128'hfadecafedeadbeefabcd0123456789ab, + 128'habcd0123456789abfadecafedeadbeef}); + o = {>>{p}}; + `checkh(o, 256'hfadecafedeadbeefabcd0123456789ababcd0123456789abfadecafedeadbeef); + o = {<<128{p}}; + `checkh(o, 256'habcd0123456789abfadecafedeadbeeffadecafedeadbeefabcd0123456789ab); + {>>{p}} = o; + `checkh(p[0], 128'habcd0123456789abfadecafedeadbeef); + `checkh(p[1], 128'hfadecafedeadbeefabcd0123456789ab); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_stream_unpack_lhs.out b/test_regress/t/t_stream_unpack_lhs.out index f6b32be22..b43bab2b8 100644 --- a/test_regress/t/t_stream_unpack_lhs.out +++ b/test_regress/t/t_stream_unpack_lhs.out @@ -1,22 +1,22 @@ -%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:113:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ +%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:112:34: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' - 113 | if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - | ^~ + 112 | if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:114:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ +%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:113:34: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' - 114 | if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - | ^~ -%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:115:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ + 113 | if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + | ^~ +%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:114:34: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' - 115 | if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; - | ^~ -%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:117:36: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ + 114 | if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; + | ^~ +%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:116:32: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' - 117 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - | ^~ -%Error: Internal Error: t/t_stream_unpack_lhs.v:117:36: ../V3Width.cpp:#: Node has no type + 116 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + | ^~ +%Error: Internal Error: t/t_stream_unpack_lhs.v:116:32: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' - 117 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - | ^~ + 116 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + | ^~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_stream_unpack_lhs.v b/test_regress/t/t_stream_unpack_lhs.v index 969b03889..9896adfd1 100644 --- a/test_regress/t/t_stream_unpack_lhs.v +++ b/test_regress/t/t_stream_unpack_lhs.v @@ -5,133 +5,132 @@ // SPDX-FileCopyrightText: 2020 Victor Besyakov // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // 1D packed array into concatenation - logic [32-1:0] concat_din; - logic [8-1:0] concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0; // same size - logic [8-1:0] concat3_dout3, concat3_dout2, concat3_dout1 ; // smaller - logic [8-1:0] concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0; // larger + // 1D packed array into concatenation + logic [32-1:0] concat_din; + logic [8-1:0] concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0; // same size + logic [8-1:0] concat3_dout3, concat3_dout2, concat3_dout1; // smaller + logic [8-1:0] + concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0; // larger - // 2D packed array into unpacked array - /* verilator lint_off ASCRANGE */ - logic [0:4-1][8-1:0] packed_siz_din; - logic [0:4-1][8-1:0] packed_asc_din; - /* verilator lint_on ASCRANGE */ - logic [4-1:0][8-1:0] packed_des_din; - logic [8-1:0] unpacked_siz_dout [4]; - logic [8-1:0] unpacked_asc_dout [0:4-1]; - logic [8-1:0] unpacked_des_dout [4-1:0]; + // 2D packed array into unpacked array + /* verilator lint_off ASCRANGE */ + logic [0:4-1][8-1:0] packed_siz_din; + logic [0:4-1][8-1:0] packed_asc_din; + /* verilator lint_on ASCRANGE */ + logic [4-1:0][8-1:0] packed_des_din; + logic [8-1:0] unpacked_siz_dout[4]; + logic [8-1:0] unpacked_asc_dout[0:4-1]; + logic [8-1:0] unpacked_des_dout[4-1:0]; - // 2D unpacked array into packed array - logic [8-1:0] unpacked_siz_din [4]; - logic [8-1:0] unpacked_asc_din [0:4-1]; - logic [8-1:0] unpacked_des_din [4-1:0]; - /* verilator lint_off ASCRANGE */ - logic [0:4-1][8-1:0] packed_siz_dout; - logic [0:4-1][8-1:0] packed_asc_dout; - /* verilator lint_on ASCRANGE */ - logic [4-1:0][8-1:0] packed_des_dout; + // 2D unpacked array into packed array + logic [8-1:0] unpacked_siz_din[4]; + logic [8-1:0] unpacked_asc_din[0:4-1]; + logic [8-1:0] unpacked_des_din[4-1:0]; + /* verilator lint_off ASCRANGE */ + logic [0:4-1][8-1:0] packed_siz_dout; + logic [0:4-1][8-1:0] packed_asc_dout; + /* verilator lint_on ASCRANGE */ + logic [4-1:0][8-1:0] packed_des_dout; - // 2D packed array into queue - logic [8-1:0] packed_siz_queue_dout [$]; - logic [8-1:0] packed_asc_queue_dout [$]; - logic [8-1:0] packed_des_queue_dout [$]; - // 2D unpacked array into queue - logic [8-1:0] unpacked_siz_queue_dout [$]; - logic [8-1:0] unpacked_asc_queue_dout [$]; - logic [8-1:0] unpacked_des_queue_dout [$]; + // 2D packed array into queue + logic [8-1:0] packed_siz_queue_dout[$]; + logic [8-1:0] packed_asc_queue_dout[$]; + logic [8-1:0] packed_des_queue_dout[$]; + // 2D unpacked array into queue + logic [8-1:0] unpacked_siz_queue_dout[$]; + logic [8-1:0] unpacked_asc_queue_dout[$]; + logic [8-1:0] unpacked_des_queue_dout[$]; - integer cyc = 1; + integer cyc = 1; - always_comb begin - // 1D packed array into concatenation - {>>{ concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0}} = concat_din; - /* verilator lint_off WIDTHTRUNC */ - {>>{ concat3_dout3, concat3_dout2, concat3_dout1 }} = concat_din; - /* verilator lint_on WIDTHTRUNC */ - /* verilator lint_off WIDTHEXPAND */ - {>>{concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0}} = concat_din; - /* verilator lint_on WIDTHEXPAND */ - // 2D packed array into unpacked array - {>>{unpacked_siz_dout}} = packed_asc_din; - {>>{unpacked_asc_dout}} = packed_asc_din; - {>>{unpacked_des_dout}} = packed_des_din; - // 2D unpacked array into packed array - {>>{packed_siz_dout}} = unpacked_siz_din; - {>>{packed_asc_dout}} = unpacked_asc_din; - {>>{packed_des_dout}} = unpacked_des_din; - // 2D packed array into queue - {>>{packed_siz_queue_dout}} = packed_siz_din; - {>>{packed_asc_queue_dout}} = packed_asc_din; - {>>{packed_des_queue_dout}} = packed_des_din; - // 2D unpacked array into queue - {>>{unpacked_siz_queue_dout}} = unpacked_siz_din; - {>>{unpacked_asc_queue_dout}} = unpacked_asc_din; - {>>{unpacked_des_queue_dout}} = unpacked_des_din; - end + always_comb begin + // 1D packed array into concatenation + {>>{concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0}} = concat_din; + /* verilator lint_off WIDTHTRUNC */ + {>>{concat3_dout3, concat3_dout2, concat3_dout1}} = concat_din; + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ + {>>{concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0}} = concat_din; + /* verilator lint_on WIDTHEXPAND */ + // 2D packed array into unpacked array + {>>{unpacked_siz_dout}} = packed_asc_din; + {>>{unpacked_asc_dout}} = packed_asc_din; + {>>{unpacked_des_dout}} = packed_des_din; + // 2D unpacked array into packed array + {>>{packed_siz_dout}} = unpacked_siz_din; + {>>{packed_asc_dout}} = unpacked_asc_din; + {>>{packed_des_dout}} = unpacked_des_din; + // 2D packed array into queue + {>>{packed_siz_queue_dout}} = packed_siz_din; + {>>{packed_asc_queue_dout}} = packed_asc_din; + {>>{packed_des_queue_dout}} = packed_des_din; + // 2D unpacked array into queue + {>>{unpacked_siz_queue_dout}} = unpacked_siz_din; + {>>{unpacked_asc_queue_dout}} = unpacked_asc_din; + {>>{unpacked_des_queue_dout}} = unpacked_des_din; + end - always @(posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; - if (cyc == 1) begin - // 1D packed array into concatenation - concat_din <= 32'h76543210; - // 2D packed array into unpacked array - packed_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; - packed_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; - packed_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; - // 2D unpacked array into packed array - unpacked_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; - unpacked_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; - unpacked_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; - end - - if (cyc == 2) begin - // 1D packed array into concatenation (same size) - if (concat4_dout0 != 8'h10) $stop; - if (concat4_dout1 != 8'h32) $stop; - if (concat4_dout2 != 8'h54) $stop; - if (concat4_dout3 != 8'h76) $stop; - // 1D packed array into concatenation (smaller) - if (concat3_dout1 != 8'h32) $stop; - if (concat3_dout2 != 8'h54) $stop; - if (concat3_dout3 != 8'h76) $stop; - // 1D packed array into concatenation (larger) - if (concat5_dout0 != 8'h00) $stop; - if (concat5_dout1 != 8'h10) $stop; - if (concat5_dout2 != 8'h32) $stop; - if (concat5_dout3 != 8'h54) $stop; - if (concat5_dout4 != 8'h76) $stop; - // 2D packed array into unpacked array - if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; - // 2D unpacked array into packed array - if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (packed_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (packed_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; - // 2D packed array into queue - if (packed_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (packed_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (packed_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; - // 2D unpacked array into queue - if (unpacked_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (unpacked_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; - if (unpacked_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; - end - - if (cyc == 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 1) begin + // 1D packed array into concatenation + concat_din <= 32'h76543210; + // 2D packed array into unpacked array + packed_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; + packed_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; + packed_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; + // 2D unpacked array into packed array + unpacked_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; + unpacked_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; + unpacked_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; end - end + + if (cyc == 2) begin + // 1D packed array into concatenation (same size) + if (concat4_dout0 != 8'h10) $stop; + if (concat4_dout1 != 8'h32) $stop; + if (concat4_dout2 != 8'h54) $stop; + if (concat4_dout3 != 8'h76) $stop; + // 1D packed array into concatenation (smaller) + if (concat3_dout1 != 8'h32) $stop; + if (concat3_dout2 != 8'h54) $stop; + if (concat3_dout3 != 8'h76) $stop; + // 1D packed array into concatenation (larger) + if (concat5_dout0 != 8'h00) $stop; + if (concat5_dout1 != 8'h10) $stop; + if (concat5_dout2 != 8'h32) $stop; + if (concat5_dout3 != 8'h54) $stop; + if (concat5_dout4 != 8'h76) $stop; + // 2D packed array into unpacked array + if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; + // 2D unpacked array into packed array + if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (packed_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (packed_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; + // 2D packed array into queue + if (packed_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (packed_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (packed_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; + // 2D unpacked array into queue + if (unpacked_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (unpacked_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; + if (unpacked_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; + end + + if (cyc == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_stream_unpack_wider.v b/test_regress/t/t_stream_unpack_wider.v index 5d53b551c..e32dd7798 100644 --- a/test_regress/t/t_stream_unpack_wider.v +++ b/test_regress/t/t_stream_unpack_wider.v @@ -4,74 +4,76 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - initial begin - automatic logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source - automatic logic [1:0] dst_1 [3]; // 6 bits wide target - automatic logic [1:0] exp_1 [3]; // 6 bits wide target + initial begin + automatic logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source + automatic logic [1:0] dst_1[3]; // 6 bits wide target + automatic logic [1:0] exp_1[3]; // 6 bits wide target - automatic logic [1:0] src_2 [3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source - automatic logic [7:0] dst_2; // 8 bits wide target - automatic logic [7:0] exp_2; // 8 bits wide target + automatic logic [1:0] src_2[3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source + automatic logic [7:0] dst_2; // 8 bits wide target + automatic logic [7:0] exp_2; // 8 bits wide target - automatic logic [7:0] src_3 = 8'hA5; // 8 bits wide source - automatic logic [27:0] dst_3; // 28 bits wide target - automatic logic [27:0] exp_3; // 28 bits wide target + automatic logic [7:0] src_3 = 8'hA5; // 8 bits wide source + automatic logic [27:0] dst_3; // 28 bits wide target + automatic logic [27:0] exp_3; // 28 bits wide target - automatic string expv; - automatic string gotv; + automatic string expv; + automatic string gotv; - // unpack as target, StreamR - {>>{dst_1}} = src_1; - exp_1 = '{2'b10, 2'b10, 2'b00}; - expv = $sformatf("%p", exp_1); - gotv = $sformatf("%p", dst_1); - `checks(gotv, expv); + // unpack as target, StreamR + {>>{dst_1}} = src_1; + exp_1 = '{2'b10, 2'b10, 2'b00}; + expv = $sformatf("%p", exp_1); + gotv = $sformatf("%p", dst_1); + `checks(gotv, expv); - // unpack as target, StreamL - {<<{dst_1}} = src_1; - exp_1 = '{2'b00, 2'b01, 2'b01}; - expv = $sformatf("%p", exp_1); - gotv = $sformatf("%p", dst_1); - `checks(gotv, expv); + // unpack as target, StreamL + {<<{dst_1}} = src_1; + exp_1 = '{2'b00, 2'b01, 2'b01}; + expv = $sformatf("%p", exp_1); + gotv = $sformatf("%p", dst_1); + `checks(gotv, expv); - // unpack as source, StreamR - dst_2 = {>>{src_2}}; - exp_2 = 8'b10101000; - expv = $sformatf("%p", exp_2); - gotv = $sformatf("%p", dst_2); - `checks(gotv, expv); + // unpack as source, StreamR + dst_2 = {>>{src_2}}; + exp_2 = 8'b10101000; + expv = $sformatf("%p", exp_2); + gotv = $sformatf("%p", dst_2); + `checks(gotv, expv); - // unpack as source, StreamL - dst_2 = {<<{src_2}}; - exp_2 = 8'b01010100; - expv = $sformatf("%p", exp_2); - gotv = $sformatf("%p", dst_2); - `checks(gotv, expv); + // unpack as source, StreamL + dst_2 = {<<{src_2}}; + exp_2 = 8'b01010100; + expv = $sformatf("%p", exp_2); + gotv = $sformatf("%p", dst_2); + `checks(gotv, expv); - // unpack as source, StreamL - // verilator lint_off WIDTHEXPAND - dst_3 = {<<{src_3}}; - // verilator lint_on WIDTHEXPAND - exp_3 = 28'hA500000; - expv = $sformatf("%p", exp_3); - gotv = $sformatf("%p", dst_3); - `checks(gotv, expv); + // unpack as source, StreamL + // verilator lint_off WIDTHEXPAND + dst_3 = {<<{src_3}}; + // verilator lint_on WIDTHEXPAND + exp_3 = 28'hA500000; + expv = $sformatf("%p", exp_3); + gotv = $sformatf("%p", dst_3); + `checks(gotv, expv); - // unpack as source, StreamR - // verilator lint_off WIDTHEXPAND - dst_3 = {>>{src_3}}; - // verilator lint_on WIDTHEXPAND - exp_3 = 28'hA500000; - expv = $sformatf("%p", exp_3); - gotv = $sformatf("%p", dst_3); - `checks(gotv, expv); + // unpack as source, StreamR + // verilator lint_off WIDTHEXPAND + dst_3 = {>>{src_3}}; + // verilator lint_on WIDTHEXPAND + exp_3 = 28'hA500000; + expv = $sformatf("%p", exp_3); + gotv = $sformatf("%p", dst_3); + `checks(gotv, expv); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_strength_2_uneq_assign.out b/test_regress/t/t_strength_2_uneq_assign.out index 6b249fe8d..79025edd5 100644 --- a/test_regress/t/t_strength_2_uneq_assign.out +++ b/test_regress/t/t_strength_2_uneq_assign.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:10:30: Unsupported: Unable to resolve unequal strength specifier +%Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:12:29: Unsupported: Unable to resolve unequal strength specifier : ... note: In instance 't' - 10 | assign (weak0, strong1) a = clk ? 'z : '0; - | ^ + 12 | assign (weak0, strong1) a = clk ? 'z : '0; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:11:30: Unsupported: Unable to resolve unequal strength specifier +%Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:13:29: Unsupported: Unable to resolve unequal strength specifier : ... note: In instance 't' - 11 | assign (strong0, pull1) a = 6'b110001; - | ^ + 13 | assign (strong0, pull1) a = 6'b110001; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_strength_2_uneq_assign.v b/test_regress/t/t_strength_2_uneq_assign.v index 9c5bb2e6a..0d1ff0edc 100644 --- a/test_regress/t/t_strength_2_uneq_assign.v +++ b/test_regress/t/t_strength_2_uneq_assign.v @@ -4,16 +4,18 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - wire [5:0] a; - assign (weak0, strong1) a = clk ? 'z : '0; - assign (strong0, pull1) a = 6'b110001; - initial begin - if (a === 6'b110001) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end +module t ( + input clk +); + + wire [5:0] a; + assign (weak0, strong1) a = clk ? 'z : '0; + assign (strong0, pull1) a = 6'b110001; + initial begin + if (a === 6'b110001) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_strength_bufif1.out b/test_regress/t/t_strength_bufif1.out index 0ac300369..87de80282 100644 --- a/test_regress/t/t_strength_bufif1.out +++ b/test_regress/t/t_strength_bufif1.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_strength_bufif1.v:9:11: Unsupported: Strength specifier on this gate type - 9 | bufif1 (strong0, strong1) (a, 1'b1, 1'b1); - | ^ +%Error-UNSUPPORTED: t/t_strength_bufif1.v:9:10: Unsupported: Strength specifier on this gate type + 9 | bufif1 (strong0, strong1) (a, 1'b1, 1'b1); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_strength_bufif1.v b/test_regress/t/t_strength_bufif1.v index 1d100b30f..11d7fd72c 100644 --- a/test_regress/t/t_strength_bufif1.v +++ b/test_regress/t/t_strength_bufif1.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire a; - bufif1 (strong0, strong1) (a, 1'b1, 1'b1); + wire a; + bufif1 (strong0, strong1) (a, 1'b1, 1'b1); - always begin - if (a) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always begin + if (a) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_strength_equal_strength.v b/test_regress/t/t_strength_equal_strength.v index ac7c4b28f..8fab7b8b2 100644 --- a/test_regress/t/t_strength_equal_strength.v +++ b/test_regress/t/t_strength_equal_strength.v @@ -5,45 +5,45 @@ // SPDX-License-Identifier: CC0-1.0 interface inter - #(parameter W) - (input logic cond, output wire a); - // Example: - wire (weak0, weak1) [W-1:0] b = '1; - assign (strong0, strong1) b = cond ? 'b0 : 'bz; + #(parameter W) + (input logic cond, output wire a); + // Example: + wire (weak0, weak1) [W-1:0] b = '1; + assign (strong0, strong1) b = cond ? 'b0 : 'bz; - assign a = b[10]; + assign a = b[10]; endinterface module t (clk1, clk2); - input wire clk1; - input wire clk2; + input wire clk1; + input wire clk2; - wire (weak0, weak1) a = 0; - assign (supply0, supply1) a = 1'bz; - assign (pull0, pull1) a = 1; + wire (weak0, weak1) a = 0; + assign (supply0, supply1) a = 1'bz; + assign (pull0, pull1) a = 1; - wire [2:0] b; - assign b = 3'b101; - assign (supply0, supply1) b = 3'b01z; + wire [2:0] b; + assign b = 3'b101; + assign (supply0, supply1) b = 3'b01z; - wire c; - and (weak0, weak1) (c, clk1, clk2); - assign (strong0, strong1) c = 'z; - assign (pull0, pull1) c = 0; + wire c; + and (weak0, weak1) (c, clk1, clk2); + assign (strong0, strong1) c = 'z; + assign (pull0, pull1) c = 0; - wire d; - inter #(.W(32)) i(.cond(1'b1), .a(d)); + wire d; + inter #(.W(32)) i(.cond(1'b1), .a(d)); - always begin - if (a === 1 && b === 3'b011 && c === 0 && d === 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Error: a = %b, b = %b, c = %b, d = %b", a, b, c, d); - $write("expected: a = %b, b = %b, c = %b, d = %b\n", clk1, 3'b011, 0, 0); - $stop; - end - end + always begin + if (a === 1 && b === 3'b011 && c === 0 && d === 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Error: a = %b, b = %b, c = %b, d = %b", a, b, c, d); + $write("expected: a = %b, b = %b, c = %b, d = %b\n", clk1, 3'b011, 0, 0); + $stop; + end + end endmodule diff --git a/test_regress/t/t_strength_highz.out b/test_regress/t/t_strength_highz.out index 06f32f6e9..02823c9f2 100644 --- a/test_regress/t/t_strength_highz.out +++ b/test_regress/t/t_strength_highz.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_strength_highz.v:8:17: Unsupported: highz strength - 8 | wire (weak0, highz1) a = 1; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_strength_highz.v:8:16: Unsupported: highz strength + 8 | wire (weak0, highz1) a = 1; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_strength_highz.v:9:19: Unsupported: highz strength - 9 | wire (strong1, highz0) b = 0; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_strength_highz.v:10:10: Unsupported: highz strength - 10 | wire (highz0, pull1) c = 0; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_strength_highz.v:11:10: Unsupported: highz strength - 11 | wire (highz1, supply0) d = 1; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_strength_highz.v:9:18: Unsupported: highz strength + 9 | wire (strong1, highz0) b = 0; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_strength_highz.v:10:9: Unsupported: highz strength + 10 | wire (highz0, pull1) c = 0; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_strength_highz.v:11:9: Unsupported: highz strength + 11 | wire (highz1, supply0) d = 1; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_strength_highz.v b/test_regress/t/t_strength_highz.v index 37519d278..7299d7a8f 100644 --- a/test_regress/t/t_strength_highz.v +++ b/test_regress/t/t_strength_highz.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire (weak0, highz1) a = 1; - wire (strong1, highz0) b = 0; - wire (highz0, pull1) c = 0; - wire (highz1, supply0) d = 1; + wire (weak0, highz1) a = 1; + wire (strong1, highz0) b = 0; + wire (highz0, pull1) c = 0; + wire (highz1, supply0) d = 1; - always begin - if (a === 1'bz && b === 1'bz && c === 1'bz && d === 1'bz) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always begin + if (a === 1'bz && b === 1'bz && c === 1'bz && d === 1'bz) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_strength_strong1_strong1_bad.out b/test_regress/t/t_strength_strong1_strong1_bad.out index 2705ad874..024dff37c 100644 --- a/test_regress/t/t_strength_strong1_strong1_bad.out +++ b/test_regress/t/t_strength_strong1_strong1_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_strength_strong1_strong1_bad.v:8:19: syntax error, unexpected strong1 - 8 | wire (strong1, strong1) a = 1; - | ^~~~~~~ +%Error: t/t_strength_strong1_strong1_bad.v:8:18: syntax error, unexpected strong1 + 8 | wire (strong1, strong1) a = 1; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_strength_strong1_strong1_bad.v b/test_regress/t/t_strength_strong1_strong1_bad.v index d6ea93b20..40ba4011b 100644 --- a/test_regress/t/t_strength_strong1_strong1_bad.v +++ b/test_regress/t/t_strength_strong1_strong1_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire (strong1, strong1) a = 1; - initial begin - $stop; - end + wire (strong1, strong1) a = 1; + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_strength_strongest_constant.v b/test_regress/t/t_strength_strongest_constant.v index 343078601..e5089520b 100644 --- a/test_regress/t/t_strength_strongest_constant.v +++ b/test_regress/t/t_strength_strongest_constant.v @@ -4,30 +4,33 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (clk1, clk2); - input wire clk1; - input wire clk2; +module t ( + clk1, + clk2 +); + input wire clk1; + input wire clk2; - wire a; - nor (pull0, weak1) n1(a, 0, 0); - assign (strong0, weak1) a = 0; + wire a; + nor (pull0, weak1) n1 (a, 0, 0); + assign (strong0, weak1) a = 0; - wire [1:0] b; - assign (weak0, supply1) b = '1; - assign b = clk1 ? '0 : 'z; + wire [1:0] b; + assign (weak0, supply1) b = '1; + assign b = clk1 ? '0 : 'z; - wire c = 1; - assign (weak0, pull1) c = clk1 & clk2; + wire c = 1; + assign (weak0, pull1) c = clk1 & clk2; - always begin - if (!a && b === '1 && c) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Error: a = %b, b = %b, c = %b ", a, b, c); - $write("expected: a = 0, b = 11, c = 1\n"); - $stop; - end - end + always begin + if (!a && b === '1 && c) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Error: a = %b, b = %b, c = %b ", a, b, c); + $write("expected: a = 0, b = 11, c = 1\n"); + $stop; + end + end endmodule diff --git a/test_regress/t/t_strength_strongest_non_tristate.v b/test_regress/t/t_strength_strongest_non_tristate.v index b8affbb9b..28e2b0c18 100644 --- a/test_regress/t/t_strength_strongest_non_tristate.v +++ b/test_regress/t/t_strength_strongest_non_tristate.v @@ -5,31 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); - input wire clk1; - input wire clk2; + input wire clk1; + input wire clk2; - wire (weak0, weak1) a = 0; - assign (strong0, supply1) a = clk1; - assign (pull0, pull1) a = 1; + wire (weak0, weak1) a = 0; + assign (strong0, supply1) a = clk1; + assign (pull0, pull1) a = 1; - wire b; - xor (strong0, strong1) (b, clk1, clk2); - and (weak0, pull1) (b, clk1, clk2); + wire b; + xor (strong0, strong1) (b, clk1, clk2); + and (weak0, pull1) (b, clk1, clk2); - wire [7:0] c; - assign (supply0, strong1) c = clk1 ? '1 : '0; - assign (weak0, supply1) c = '0; - assign (weak0, pull1) c = 'z; + wire [7:0] c; + assign (supply0, strong1) c = clk1 ? '1 : '0; + assign (weak0, supply1) c = '0; + assign (weak0, pull1) c = 'z; - always begin - if (a === clk1 && b === clk1 ^ clk2 && c[0] === clk1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Error: a = %b, b = %b, c[0] = %b, ", a, b, c[0]); - $write("expected: a = %b, b = %b, c[0] = %b\n", clk1, clk1 ^ clk2, clk1); - $stop; - end - end + always begin + if (a === clk1 && b === clk1 ^ clk2 && c[0] === clk1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Error: a = %b, b = %b, c[0] = %b, ", a, b, c[0]); + $write("expected: a = %b, b = %b, c[0] = %b\n", clk1, clk1 ^ clk2, clk1); + $stop; + end + end endmodule diff --git a/test_regress/t/t_string.v b/test_regress/t/t_string.v index cf24c7f08..0e6d0f03e 100644 --- a/test_regress/t/t_string.v +++ b/test_regress/t/t_string.v @@ -4,133 +4,133 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [1*8:1] vstr1; - reg [2*8:1] vstr2; - reg [6*8:1] vstr6; + reg [1*8:1] vstr1; + reg [2*8:1] vstr2; + reg [6*8:1] vstr6; - reg [4*8:1] vstr; - const string s = "a"; // Check static assignment - string s2; - string s3; - reg eq; + reg [4*8:1] vstr; + const string s = "a"; // Check static assignment + string s2; + string s3; + reg eq; - byte unpack1[0:4]; + byte unpack1[0:4]; - // Operators == != < <= > >= {a,b} {a{b}} a[b] - // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr - // a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal, - // a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa + // Operators == != < <= > >= {a,b} {a{b}} a[b] + // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr + // a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal, + // a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa - initial begin - $sformat(vstr1, "%s", s); - `checks(vstr1, "a"); + initial begin + $sformat(vstr1, "%s", s); + `checks(vstr1, "a"); - $sformat(vstr2, "=%s", s); - `checks(vstr2, "=a"); + $sformat(vstr2, "=%s", s); + `checks(vstr2, "=a"); - $sformat(vstr6, "--a=%s", s); - `checks(vstr6, "--a=a"); + $sformat(vstr6, "--a=%s", s); + `checks(vstr6, "--a=a"); - $sformat(vstr, "s=%s", s); - `checks(vstr, "s=a"); - `checks(string'(vstr), "s=a"); - `checks(s, "a"); - `checks({s,s,s}, "aaa"); - `checks({4{s}}, "aaaa"); - // Constification - `checkh(s == "a", 1'b1); - `checkh(s == "b", 1'b0); - `checkh(s != "a", 1'b0); - `checkh(s != "b", 1'b1); - `checkh(s > " ", 1'b1); - `checkh(s > "a", 1'b0); - `checkh(s >= "a", 1'b1); - `checkh(s >= "b", 1'b0); - `checkh(s < "a", 1'b0); - `checkh(s < "b", 1'b1); - `checkh(s <= " ", 1'b0); - `checkh(s <= "a", 1'b1); + $sformat(vstr, "s=%s", s); + `checks(vstr, "s=a"); + `checks(string'(vstr), "s=a"); + `checks(s, "a"); + `checks({s, s, s}, "aaa"); + `checks({4{s}}, "aaaa"); + // Constification + `checkh(s == "a", 1'b1); + `checkh(s == "b", 1'b0); + `checkh(s != "a", 1'b0); + `checkh(s != "b", 1'b1); + `checkh(s > " ", 1'b1); + `checkh(s > "a", 1'b0); + `checkh(s >= "a", 1'b1); + `checkh(s >= "b", 1'b0); + `checkh(s < "a", 1'b0); + `checkh(s < "b", 1'b1); + `checkh(s <= " ", 1'b0); + `checkh(s <= "a", 1'b1); `ifndef VCS `ifndef VERILATOR `ifndef NC - // IEEE 1800-2023 5.9 assignment to byte array - unpack1 = "five"; - `checkh(unpack1[0], "f"); - `checkh(unpack1[1], "i"); - `checkh(unpack1[2], "v"); - `checkh(unpack1[3], "e"); - `checkh(unpack1[4], 8'h0); + // IEEE 1800-2023 5.9 assignment to byte array + unpack1 = "five"; + `checkh(unpack1[0], "f"); + `checkh(unpack1[1], "i"); + `checkh(unpack1[2], "v"); + `checkh(unpack1[3], "e"); + `checkh(unpack1[4], 8'h0); `endif `endif `endif - end + end - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - s2 = "c0"; - end - else if (cyc==1) begin - $sformat(vstr, "s2%s", s2); - `checks(vstr, "s2c0"); - end - else if (cyc==2) begin - s3 = s2; - $sformat(vstr, "s2%s", s3); - `checks(vstr, "s2c0"); - end - else if (cyc==3) begin - s2 = "a"; - s3 = "b"; - end - else if (cyc==4) begin - `checks({s2,s3}, "ab"); - `checks({3{s3}}, "bbb"); - `checkh(s == "a", 1'b1); - `checkh(s == "b", 1'b0); - `checkh(s != "a", 1'b0); - `checkh(s != "b", 1'b1); - `checkh(s > " ", 1'b1); - `checkh(s > "a", 1'b0); - `checkh(s >= "a", 1'b1); - `checkh(s >= "b", 1'b0); - `checkh(s < "a", 1'b0); - `checkh(s < "b", 1'b1); - `checkh(s <= " ", 1'b0); - `checkh(s <= "a", 1'b1); - end - // String character references - else if (cyc==10) begin - s2 = "astring"; - end - else if (cyc==11) begin - `checks(s2, "astring"); - `checkh(s2.len(), 7); - `checkh(s2[1], "s"); - s2[0] = "0"; - s2[3] = "3"; - `checks(s2, "0st3ing"); - end - // - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + s2 = "c0"; + end + else if (cyc == 1) begin + $sformat(vstr, "s2%s", s2); + `checks(vstr, "s2c0"); + end + else if (cyc == 2) begin + s3 = s2; + $sformat(vstr, "s2%s", s3); + `checks(vstr, "s2c0"); + end + else if (cyc == 3) begin + s2 = "a"; + s3 = "b"; + end + else if (cyc == 4) begin + `checks({s2, s3}, "ab"); + `checks({3{s3}}, "bbb"); + `checkh(s == "a", 1'b1); + `checkh(s == "b", 1'b0); + `checkh(s != "a", 1'b0); + `checkh(s != "b", 1'b1); + `checkh(s > " ", 1'b1); + `checkh(s > "a", 1'b0); + `checkh(s >= "a", 1'b1); + `checkh(s >= "b", 1'b0); + `checkh(s < "a", 1'b0); + `checkh(s < "b", 1'b1); + `checkh(s <= " ", 1'b0); + `checkh(s <= "a", 1'b1); + end + // String character references + else if (cyc == 10) begin + s2 = "astring"; + end + else if (cyc == 11) begin + `checks(s2, "astring"); + `checkh(s2.len(), 7); + `checkh(s2[1], "s"); + s2[0] = "0"; + s2[3] = "3"; + `checks(s2, "0st3ing"); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_string_byte.v b/test_regress/t/t_string_byte.v index 6faf28161..178c5105b 100644 --- a/test_regress/t/t_string_byte.v +++ b/test_regress/t/t_string_byte.v @@ -4,26 +4,28 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - // Unpacked byte from string IEEE 1800-2023 5.9 - byte bh[3:0] = "hi2"; - byte bl[0:3] = "lo2"; + // Unpacked byte from string IEEE 1800-2023 5.9 + byte bh[3:0] = "hi2"; + byte bl[0:3] = "lo2"; - initial begin - `checkh(bh[0], "2"); - `checkh(bh[1], "i"); - `checkh(bh[2], "h"); - `checkh(bh[3], 0); - `checkh(bl[0], 0); - `checkh(bl[1], "l"); - `checkh(bl[2], "o"); - `checkh(bl[3], "2"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `checkh(bh[0], "2"); + `checkh(bh[1], "i"); + `checkh(bh[2], "h"); + `checkh(bh[3], 0); + `checkh(bl[0], 0); + `checkh(bl[1], "l"); + `checkh(bl[2], "o"); + `checkh(bl[3], "2"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_string_convert2.v b/test_regress/t/t_string_convert2.v index ef5e4059c..1f3dd7369 100644 --- a/test_regress/t/t_string_convert2.v +++ b/test_regress/t/t_string_convert2.v @@ -4,30 +4,30 @@ // SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; - wire [31:0] in = cyc; + integer cyc; + initial cyc = 1; + wire [31:0] in = cyc; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[31:0]) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule @@ -50,25 +50,26 @@ endpackage //internal error happens when lpcm_pkg is not imported //import lpcm_pkg::*; -module Test (/*AUTOARG*/ - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Inputs + clk, + in +); - input clk; - input [31:0] in; + input clk; + input [31:0] in; - initial begin - string s; - lpcm_pkg::lpcm_tr tr; // internal error happens when lpcm_pkg is not imported - tr = new(); - tr.sample = 1; - tr.latency = 2; - s = tr.convert2string(); - $display("hello %s", tr.convert2string()); - if (s != "sample=0x1 latency=2") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + string s; + lpcm_pkg::lpcm_tr tr; // internal error happens when lpcm_pkg is not imported + tr = new(); + tr.sample = 1; + tr.latency = 2; + s = tr.convert2string(); + $display("hello %s", tr.convert2string()); + if (s != "sample=0x1 latency=2") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_string_dyn_num.v b/test_regress/t/t_string_dyn_num.v index d0affad6f..dd4ca699f 100644 --- a/test_regress/t/t_string_dyn_num.v +++ b/test_regress/t/t_string_dyn_num.v @@ -4,54 +4,52 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [31:0] istr; - string sstr; - string v; + reg [31:0] istr; + string sstr; + string v; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d istr='%s' sstr='%s'\n", $time, cyc, istr, sstr); + $write("[%0t] cyc==%0d istr='%s' sstr='%s'\n", $time, cyc, istr, sstr); `endif - cyc <= cyc + 1; - sstr <= string'(istr); // Note takes another cycle - if (cyc < 10) begin - istr <= 32'h00_00_00_00; - end - else if (cyc == 13) begin - // These displays are needed to check padding of %s - $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); - if (sstr.len() != 0) $stop; - if (sstr != "") $stop; - end - else if (cyc == 20) begin - istr <= 32'h00_00_41_00; - end - else if (cyc == 23) begin - $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); - if (sstr.len() != 1) $stop; - if (sstr != "A") $stop; - end - else if (cyc == 30) begin - istr <= 32'h42_00_41_00; - end - else if (cyc == 33) begin - $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); - if (sstr.len() != 2) $stop; - if (sstr != "BA") $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + sstr <= string'(istr); // Note takes another cycle + if (cyc < 10) begin + istr <= 32'h00_00_00_00; + end + else if (cyc == 13) begin + // These displays are needed to check padding of %s + $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); + if (sstr.len() != 0) $stop; + if (sstr != "") $stop; + end + else if (cyc == 20) begin + istr <= 32'h00_00_41_00; + end + else if (cyc == 23) begin + $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); + if (sstr.len() != 1) $stop; + if (sstr != "A") $stop; + end + else if (cyc == 30) begin + istr <= 32'h42_00_41_00; + end + else if (cyc == 33) begin + $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); + if (sstr.len() != 2) $stop; + if (sstr != "BA") $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_string_octal.v b/test_regress/t/t_string_octal.v index 948592f9e..26c918854 100644 --- a/test_regress/t/t_string_octal.v +++ b/test_regress/t/t_string_octal.v @@ -10,36 +10,36 @@ // verilog_format: on module t; - string s; - initial begin - s = $sformatf("\099 \119 \121"); // Q Q Q - // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); - // Results vary by simulator. Some possibilities: - // 0 0 0 0 0 - // 40 71 71 40 11 - // 71 71 40 11 071 + string s; + initial begin + s = $sformatf("\099 \119 \121"); // Q Q Q + // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); + // Results vary by simulator. Some possibilities: + // 0 0 0 0 0 + // 40 71 71 40 11 + // 71 71 40 11 071 - s = $sformatf("\088 \108 \110"); // H H H - // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); - // Results vary by simulator. Some possibilities: - // 0 0 0 0 0 - // 40 70 70 40 10 - // 70 70 40 10 70 + s = $sformatf("\088 \108 \110"); // H H H + // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); + // Results vary by simulator. Some possibilities: + // 0 0 0 0 0 + // 40 70 70 40 10 + // 70 70 40 10 70 - s = $sformatf("\102\3\12."); // B\023\312. - // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); - `checko(s[0], 8'o102); - `checko(s[1], 8'o003); - `checko(s[2], 8'o012); - `checko(s[3], 8'o056); + s = $sformatf("\102\3\12."); // B\023\312. + // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); + `checko(s[0], 8'o102); + `checko(s[1], 8'o003); + `checko(s[2], 8'o012); + `checko(s[3], 8'o056); - s = $sformatf("\102.\3.\12\103"); // B.\023.C - // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); - `checko(s[0], 8'o102); - `checko(s[2], 8'o003); - `checko(s[4], 8'o012); - `checko(s[5], 8'o103); - $display("*-* All Finished *-*"); - $finish; - end + s = $sformatf("\102.\3.\12\103"); // B.\023.C + // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); + `checko(s[0], 8'o102); + `checko(s[2], 8'o003); + `checko(s[4], 8'o012); + `checko(s[5], 8'o103); + $display("*-* All Finished *-*"); + $finish; + end endmodule diff --git a/test_regress/t/t_string_repl.v b/test_regress/t/t_string_repl.v index b42a45c99..b252a8b60 100644 --- a/test_regress/t/t_string_repl.v +++ b/test_regress/t/t_string_repl.v @@ -4,30 +4,28 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - string s, s2; + string s, s2; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - s = {s2, {cyc{"*"}}}; - if (cyc != s.len()) $stop; - if (cyc == 0 && s != "") $stop; - if (cyc == 1 && s != "*") $stop; - if (cyc == 2 && s != "**") $stop; - if (cyc == 3 && s != "***") $stop; - if (cyc == 4 && s != "****") $stop; - if (cyc == 5 && s != "*****") $stop; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + s = {s2, {cyc{"*"}}}; + if (cyc != s.len()) $stop; + if (cyc == 0 && s != "") $stop; + if (cyc == 1 && s != "*") $stop; + if (cyc == 2 && s != "**") $stop; + if (cyc == 3 && s != "***") $stop; + if (cyc == 4 && s != "****") $stop; + if (cyc == 5 && s != "*****") $stop; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_string_sel.v b/test_regress/t/t_string_sel.v index d0334c030..49c82f261 100644 --- a/test_regress/t/t_string_sel.v +++ b/test_regress/t/t_string_sel.v @@ -5,56 +5,56 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct { - string str; + string str; } str_s; class c; - string str; - function new(); - str = "foo"; - endfunction - function string get_str(); - return str; - endfunction + string str; + function new(); + str = "foo"; + endfunction + function string get_str(); + return str; + endfunction endclass module t; - string str = "bar"; + string str = "bar"; - function string get_str(); - return str; - endfunction + function string get_str(); + return str; + endfunction - initial begin - automatic c o = new; - automatic str_s st = '{"qux"}; - automatic string sc = {"foo", "bar"}; + initial begin + automatic c o = new; + automatic str_s st = '{"qux"}; + automatic string sc = {"foo", "bar"}; - // read - if (str[0] != "b") $stop; - if (get_str()[1] != "a") $stop; - if (str[3] != "\0") $stop; - if (st.str[2] != "x") $stop; - if (st.str[99] != "\0") $stop; - if (o.str[0] != "f") $stop; - if (o.get_str()[1] != "o") $stop; - if (o.str[-1] != "\0") $stop; - if (sc[2] != "o") $stop; - if ($sformatf("foo%s", "bar")[3] != "b") $stop; - if (sc[-1] != "\0") $stop; - if (sc[6] != "\0") $stop; - if (sc[99] != "\0") $stop; + // read + if (str[0] != "b") $stop; + if (get_str()[1] != "a") $stop; + if (str[3] != "\0") $stop; + if (st.str[2] != "x") $stop; + if (st.str[99] != "\0") $stop; + if (o.str[0] != "f") $stop; + if (o.get_str()[1] != "o") $stop; + if (o.str[-1] != "\0") $stop; + if (sc[2] != "o") $stop; + if ($sformatf("foo%s", "bar")[3] != "b") $stop; + if (sc[-1] != "\0") $stop; + if (sc[6] != "\0") $stop; + if (sc[99] != "\0") $stop; - // write - sc[5] = "z"; - if (sc != "foobaz") $stop; - o.str[0] = "b"; - if (o.str != "boo") $stop; - st.str[2] = "z"; - if (st.str != "quz") $stop; + // write + sc[5] = "z"; + if (sc != "foobaz") $stop; + o.str[0] = "b"; + if (o.str != "boo") $stop; + st.str[2] = "z"; + if (st.str != "quz") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_string_size.v b/test_regress/t/t_string_size.v index 9c91a4f82..505959cbd 100644 --- a/test_regress/t/t_string_size.v +++ b/test_regress/t/t_string_size.v @@ -4,86 +4,86 @@ // SPDX-FileCopyrightText: 2021 wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - outempty64 - ); - output [63:0] outempty64; +module t ( /*AUTOARG*/ + // Outputs + outempty64 +); + output [63:0] outempty64; - parameter string OS = "O"; - parameter OI = "O"; // B is an integer of width 8 + parameter string OS = "O"; + parameter OI = "O"; // B is an integer of width 8 - // verilator lint_off WIDTH - parameter string EMPTYS = ""; - parameter EMPTYI = ""; // B is an integer of width 8 - parameter bit [23:0] EMPTY24 = ""; - parameter bit [63:0] EMPTY64 = ""; - // verilator lint_on WIDTH - parameter bit [31:0] NEST = "NEST"; - parameter bit [31:0] TEST = "TEST"; - string s; + // verilator lint_off WIDTH + parameter string EMPTYS = ""; + parameter EMPTYI = ""; // B is an integer of width 8 + parameter bit [23:0] EMPTY24 = ""; + parameter bit [63:0] EMPTY64 = ""; + // verilator lint_on WIDTH + parameter bit [31:0] NEST = "NEST"; + parameter bit [31:0] TEST = "TEST"; + string s; - // verilator lint_off WIDTH - assign outempty64 = ""; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + assign outempty64 = ""; + // verilator lint_on WIDTH - initial begin - // IEEE: "Leading 0s are never printed" but that does not mean spaces are not - $display(">%s< == >< (or > < also legal)", "\000"); - $display(">%s< == >< (or > < also legal)", ""); - $display(">%s< == > <", 32'h0); + initial begin + // IEEE: "Leading 0s are never printed" but that does not mean spaces are not + $display(">%s< == >< (or > < also legal)", "\000"); + $display(">%s< == >< (or > < also legal)", ""); + $display(">%s< == > <", 32'h0); - // Numeric context, so IEEE 1800-2023 11.10.3 "" is a "\000" - if ($bits("") != 8) $stop; - if ("" != "\000") $stop; + // Numeric context, so IEEE 1800-2023 11.10.3 "" is a "\000" + if ($bits("") != 8) $stop; + if ("" != "\000") $stop; - if ($bits("A") != 8) $stop; + if ($bits("A") != 8) $stop; - s = ""; - if (s.len != 0) $stop; + s = ""; + if (s.len != 0) $stop; - // IEEE 1800-2023 6.16 "\000" assigned to string is ignored - s = "\000yo\000"; - if (s.len != 2) $stop; - if (s != "yo") $stop; + // IEEE 1800-2023 6.16 "\000" assigned to string is ignored + s = "\000yo\000"; + if (s.len != 2) $stop; + if (s != "yo") $stop; - if ($bits(EMPTYI) != 8) $stop; - if (EMPTYI != "\000") $stop; - // verilator lint_off WIDTH - if (EMPTYI == "TEST") $stop; - if (EMPTYI == TEST) $stop; - // verilator lint_on WIDTH + if ($bits(EMPTYI) != 8) $stop; + if (EMPTYI != "\000") $stop; + // verilator lint_off WIDTH + if (EMPTYI == "TEST") $stop; + if (EMPTYI == TEST) $stop; + // verilator lint_on WIDTH - if ($bits(EMPTY24) != 24) $stop; - if (EMPTY24 != 0) $stop; - $display(">%s< == > <", EMPTY24); + if ($bits(EMPTY24) != 24) $stop; + if (EMPTY24 != 0) $stop; + $display(">%s< == > <", EMPTY24); - if ($bits(EMPTY64) != 64) $stop; - if (EMPTY64 != 0) $stop; - $display(">%s< == > <", EMPTY64); + if ($bits(EMPTY64) != 64) $stop; + if (EMPTY64 != 0) $stop; + $display(">%s< == > <", EMPTY64); - if ($bits(EMPTYS) != 0) $stop; - if (EMPTYS == "TEST") $stop; // Illegal in some simulators as not both strings - if (EMPTYS == TEST) $stop; - $display(">%s< == ><", EMPTYS); + if ($bits(EMPTYS) != 0) $stop; + if (EMPTYS == "TEST") $stop; // Illegal in some simulators as not both strings + if (EMPTYS == TEST) $stop; + $display(">%s< == ><", EMPTYS); - if ($bits(OS) != 8) $stop; - if (OS != "O") $stop; - if (OS == "TEST") $stop; // Illegal in some simulators as not both strings - if (OS == TEST) $stop; + if ($bits(OS) != 8) $stop; + if (OS != "O") $stop; + if (OS == "TEST") $stop; // Illegal in some simulators as not both strings + if (OS == TEST) $stop; - if ($bits(OI) != 8) $stop; - if (OI != "O") $stop; + if ($bits(OI) != 8) $stop; + if (OI != "O") $stop; - // verilator lint_off WIDTH - if (OI == "TEST") $stop; - if (OI == TEST) $stop; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + if (OI == "TEST") $stop; + if (OI == TEST) $stop; + // verilator lint_on WIDTH - if ($bits(outempty64) != 64) $stop; - if (outempty64 != 64'h00_00_00_00_00_00_00_00) $stop; + if ($bits(outempty64) != 64) $stop; + if (outempty64 != 64'h00_00_00_00_00_00_00_00) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_string_to_bit.v b/test_regress/t/t_string_to_bit.v index 1dcaba8ea..0e1f0cff4 100644 --- a/test_regress/t/t_string_to_bit.v +++ b/test_regress/t/t_string_to_bit.v @@ -4,104 +4,104 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - string str0; - string str1; - string str2; + string str0; + string str1; + string str2; - typedef bit [31:0] bit_t; - typedef logic [31:0] logic_t; - typedef bit [55:0] quad_t; - typedef bit [87:0] wide_t; + typedef bit [31:0] bit_t; + typedef logic [31:0] logic_t; + typedef bit [55:0] quad_t; + typedef bit [87:0] wide_t; - bit_t bdata[3]; - bit_t ldata[3]; - quad_t qdata[3]; - wide_t wdata[3]; + bit_t bdata[3]; + bit_t ldata[3]; + quad_t qdata[3]; + wide_t wdata[3]; - initial begin - str0 = "sm"; - str1 = "medium"; - str2 = "veryverylongwilltruncate"; + initial begin + str0 = "sm"; + str1 = "medium"; + str2 = "veryverylongwilltruncate"; + bdata[0] = bit_t'(str0); + bdata[1] = bit_t'(str1); + bdata[2] = bit_t'(str2); + `checks(bdata[0], "sm"); + `checks(bdata[1], "dium"); + `checks(bdata[2], "cate"); + if (bdata[0] != 32'h0000736d) $stop; + if (bdata[1] != 32'h6469756d) $stop; + ldata[0] = logic_t'(str0); + ldata[1] = logic_t'(str1); + ldata[2] = logic_t'(str2); + `checks(ldata[0], "sm"); + `checks(ldata[1], "dium"); + `checks(ldata[2], "cate"); + qdata[0] = quad_t'(str0); + qdata[1] = quad_t'(str1); + qdata[2] = quad_t'(str2); + `checks(qdata[0], "sm"); + `checks(qdata[1], "medium"); + `checks(qdata[2], "runcate"); + wdata[0] = wide_t'(str0); + wdata[1] = wide_t'(str1); + wdata[2] = wide_t'(str2); + `checks(wdata[0], "sm"); + `checks(wdata[1], "medium"); + `checks(wdata[2], "illtruncate"); + end + + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + str0 = "z"; + str1 = "zmedi"; + str2 = "ziggylonglonglongtruncate"; + end + else if (cyc == 2) begin bdata[0] = bit_t'(str0); bdata[1] = bit_t'(str1); bdata[2] = bit_t'(str2); - `checks(bdata[0], "sm"); - `checks(bdata[1], "dium"); - `checks(bdata[2], "cate"); - if (bdata[0] != 32'h0000736d) $stop; - if (bdata[1] != 32'h6469756d) $stop; ldata[0] = logic_t'(str0); ldata[1] = logic_t'(str1); ldata[2] = logic_t'(str2); - `checks(ldata[0], "sm"); - `checks(ldata[1], "dium"); - `checks(ldata[2], "cate"); qdata[0] = quad_t'(str0); qdata[1] = quad_t'(str1); qdata[2] = quad_t'(str2); - `checks(qdata[0], "sm"); - `checks(qdata[1], "medium"); - `checks(qdata[2], "runcate"); wdata[0] = wide_t'(str0); wdata[1] = wide_t'(str1); wdata[2] = wide_t'(str2); - `checks(wdata[0], "sm"); - `checks(wdata[1], "medium"); - `checks(wdata[2], "illtruncate"); - end - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - str0 = "z"; - str1 = "zmedi"; - str2 = "ziggylonglonglongtruncate"; - end - else if (cyc == 2) begin - bdata[0] = bit_t'(str0); - bdata[1] = bit_t'(str1); - bdata[2] = bit_t'(str2); - ldata[0] = logic_t'(str0); - ldata[1] = logic_t'(str1); - ldata[2] = logic_t'(str2); - qdata[0] = quad_t'(str0); - qdata[1] = quad_t'(str1); - qdata[2] = quad_t'(str2); - wdata[0] = wide_t'(str0); - wdata[1] = wide_t'(str1); - wdata[2] = wide_t'(str2); - end - else if (cyc == 3) begin - `checks(bdata[0], "z"); - `checks(bdata[1], "medi"); - `checks(bdata[2], "cate"); - `checks(ldata[0], "z"); - `checks(ldata[1], "medi"); - `checks(ldata[2], "cate"); - `checks(qdata[0], "z"); - `checks(qdata[1], "zmedi"); - `checks(qdata[2], "runcate"); - `checks(wdata[0], "z"); - `checks(wdata[1], "zmedi"); - `checks(wdata[2], "ongtruncate"); - end - // - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 3) begin + `checks(bdata[0], "z"); + `checks(bdata[1], "medi"); + `checks(bdata[2], "cate"); + `checks(ldata[0], "z"); + `checks(ldata[1], "medi"); + `checks(ldata[2], "cate"); + `checks(qdata[0], "z"); + `checks(qdata[1], "zmedi"); + `checks(qdata[2], "runcate"); + `checks(wdata[0], "z"); + `checks(wdata[1], "zmedi"); + `checks(wdata[2], "ongtruncate"); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_string_type_methods.v b/test_regress/t/t_string_type_methods.v index 2a55069c4..1255a9565 100644 --- a/test_regress/t/t_string_type_methods.v +++ b/test_regress/t/t_string_type_methods.v @@ -4,158 +4,160 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkg(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - string s; + string s; - integer cyc = 0; + integer cyc = 0; - // Check constification - initial begin - s="1234"; `checkh(s.len(),4); - s="ab7CD"; `checks(s.toupper(), "AB7CD"); - s="ab7CD"; `checks(s.tolower(), "ab7cd"); - s="1234"; s.putc(-1, "z"); `checks(s, "1234"); - s="1234"; s.putc(4, "z"); `checks(s, "1234"); - s="1234"; s.putc(2, 0); `checks(s, "1234"); - s="1234"; s.putc(2, "z"); `checks(s, "12z4"); - s="1234"; `checkh(s.getc(-1), 0); - s="1234"; `checkh(s.getc(4), 0); - s="1234"; `checkh(s.getc(2), "3"); - s="b"; if (s.compare("a") <= 0) $stop; - s="b"; if (s.compare("b") != 0) $stop; - s="b"; if (s.compare("c") >= 0) $stop; - s="b"; if (s.compare("A") <= 0) $stop; - s="b"; if (s.compare("B") <= 0) $stop; - s="b"; if (s.compare("C") <= 0) $stop; - s="B"; if (s.compare("a") >= 0) $stop; - s="B"; if (s.compare("b") >= 0) $stop; - s="B"; if (s.compare("c") >= 0) $stop; - s="b"; if (s.icompare("A") < 0) $stop; - s="b"; if (s.icompare("B") != 0) $stop; - s="b"; if (s.icompare("C") >= 0) $stop; - s="abcd"; `checks(s.substr(-1,1), ""); - s="abcd"; `checks(s.substr(1,0), ""); - s="abcd"; `checks(s.substr(1,4), ""); - s="abcd"; `checks(s.substr(2,3), "cd"); - s="101"; `checkh(s.atoi(), 'd101); - s="101"; `checkh(s.atohex(), 'h101); - s="101"; `checkh(s.atooct(), 'o101); - s="101"; `checkh(s.atobin(), 'b101); - s="1.23"; `checkg(s.atoreal(), 1.23); - s.itoa(123); `checks(s, "123"); - s.hextoa(123); `checks(s, "7b"); - s.octtoa(123); `checks(s, "173"); - s.bintoa(123); `checks(s, "1111011"); - s.realtoa(1.23); `checks(s, "1.23"); - s = "bAr"; - s = s.toupper; `checks(s, "BAR"); - s = s.tolower; `checks(s, "bar"); - end + // Check constification + // verilog_format: off + initial begin + s="1234"; `checkh(s.len(),4); + s="ab7CD"; `checks(s.toupper(), "AB7CD"); + s="ab7CD"; `checks(s.tolower(), "ab7cd"); + s="1234"; s.putc(-1, "z"); `checks(s, "1234"); + s="1234"; s.putc(4, "z"); `checks(s, "1234"); + s="1234"; s.putc(2, 0); `checks(s, "1234"); + s="1234"; s.putc(2, "z"); `checks(s, "12z4"); + s="1234"; `checkh(s.getc(-1), 0); + s="1234"; `checkh(s.getc(4), 0); + s="1234"; `checkh(s.getc(2), "3"); + s="b"; if (s.compare("a") <= 0) $stop; + s="b"; if (s.compare("b") != 0) $stop; + s="b"; if (s.compare("c") >= 0) $stop; + s="b"; if (s.compare("A") <= 0) $stop; + s="b"; if (s.compare("B") <= 0) $stop; + s="b"; if (s.compare("C") <= 0) $stop; + s="B"; if (s.compare("a") >= 0) $stop; + s="B"; if (s.compare("b") >= 0) $stop; + s="B"; if (s.compare("c") >= 0) $stop; + s="b"; if (s.icompare("A") < 0) $stop; + s="b"; if (s.icompare("B") != 0) $stop; + s="b"; if (s.icompare("C") >= 0) $stop; + s="abcd"; `checks(s.substr(-1,1), ""); + s="abcd"; `checks(s.substr(1,0), ""); + s="abcd"; `checks(s.substr(1,4), ""); + s="abcd"; `checks(s.substr(2,3), "cd"); + s="101"; `checkh(s.atoi(), 'd101); + s="101"; `checkh(s.atohex(), 'h101); + s="101"; `checkh(s.atooct(), 'o101); + s="101"; `checkh(s.atobin(), 'b101); + s="1.23"; `checkg(s.atoreal(), 1.23); + s.itoa(123); `checks(s, "123"); + s.hextoa(123); `checks(s, "7b"); + s.octtoa(123); `checks(s, "173"); + s.bintoa(123); `checks(s, "1111011"); + s.realtoa(1.23); `checks(s, "1.23"); + s = "bAr"; + s = s.toupper; `checks(s, "BAR"); + s = s.tolower; `checks(s, "bar"); + end + // verilog_format: on - // Check runtime - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - s = "1234"; - end - else if (cyc==1) begin - `checkh(s.len(),4); - end - else if (cyc==2) begin - s.putc(-1, "z"); - end - else if (cyc==3) begin - `checks(s, "1234"); - s.putc(4, "z"); - end - else if (cyc==4) begin - `checks(s, "1234"); - s.putc(2, 0); - end - else if (cyc==5) begin - `checks(s, "1234"); - s.putc(2, "z"); - end - else if (cyc==6) begin - `checks(s, "12z4"); - end - else if (cyc==7) begin - `checkh(s.getc(-1), 0); - `checkh(s.getc(4), 0); - `checkh(s.getc(2), "z"); - s="ab3CD"; - end - else if (cyc==8) begin - `checks(s.toupper(), "AB3CD"); - `checks(s.tolower(), "ab3cd"); - s="b"; - end - else if (cyc==9) begin - if (s.compare("a") <= 0) $stop; - if (s.compare("b") != 0) $stop; - if (s.compare("c") >= 0) $stop; - if (s.compare("A") <= 0) $stop; - if (s.compare("B") <= 0) $stop; - if (s.compare("C") <= 0) $stop; - if (s.icompare("A") < 0) $stop; - if (s.icompare("B") != 0) $stop; - if (s.icompare("C") >= 0) $stop; - s="abcd"; - end - else if (cyc==10) begin - `checks(s.substr(-1,1), ""); - `checks(s.substr(1,0), ""); - `checks(s.substr(1,4), ""); - `checks(s.substr(2,3), "cd"); - s="101"; - end - else if (cyc==11) begin - `checkh(s.atoi(), 'd101); - `checkh(s.atohex(), 'h101); - `checkh(s.atooct(), 'o101); - `checkh(s.atobin(), 'b101); - s="1.23"; - end - else if (cyc==12) begin - `checkg(s.atoreal(), 1.23); - end - else if (cyc==13) begin - s.itoa(123); - end - else if (cyc==14) begin - `checks(s, "123"); - s.hextoa(123); - end - else if (cyc==15) begin - `checks(s, "7b"); - s.octtoa(123); - end - else if (cyc==16) begin - `checks(s, "173"); - s.bintoa(123); - end - else if (cyc==17) begin - `checks(s, "1111011"); - s.realtoa(1.23); - end - else if (cyc==18) begin - `checks(s, "1.23"); - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Check runtime + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + s = "1234"; + end + else if (cyc == 1) begin + `checkh(s.len(), 4); + end + else if (cyc == 2) begin + s.putc(-1, "z"); + end + else if (cyc == 3) begin + `checks(s, "1234"); + s.putc(4, "z"); + end + else if (cyc == 4) begin + `checks(s, "1234"); + s.putc(2, 0); + end + else if (cyc == 5) begin + `checks(s, "1234"); + s.putc(2, "z"); + end + else if (cyc == 6) begin + `checks(s, "12z4"); + end + else if (cyc == 7) begin + `checkh(s.getc(-1), 0); + `checkh(s.getc(4), 0); + `checkh(s.getc(2), "z"); + s = "ab3CD"; + end + else if (cyc == 8) begin + `checks(s.toupper(), "AB3CD"); + `checks(s.tolower(), "ab3cd"); + s = "b"; + end + else if (cyc == 9) begin + if (s.compare("a") <= 0) $stop; + if (s.compare("b") != 0) $stop; + if (s.compare("c") >= 0) $stop; + if (s.compare("A") <= 0) $stop; + if (s.compare("B") <= 0) $stop; + if (s.compare("C") <= 0) $stop; + if (s.icompare("A") < 0) $stop; + if (s.icompare("B") != 0) $stop; + if (s.icompare("C") >= 0) $stop; + s = "abcd"; + end + else if (cyc == 10) begin + `checks(s.substr(-1, 1), ""); + `checks(s.substr(1, 0), ""); + `checks(s.substr(1, 4), ""); + `checks(s.substr(2, 3), "cd"); + s = "101"; + end + else if (cyc == 11) begin + `checkh(s.atoi(), 'd101); + `checkh(s.atohex(), 'h101); + `checkh(s.atooct(), 'o101); + `checkh(s.atobin(), 'b101); + s = "1.23"; + end + else if (cyc == 12) begin + `checkg(s.atoreal(), 1.23); + end + else if (cyc == 13) begin + s.itoa(123); + end + else if (cyc == 14) begin + `checks(s, "123"); + s.hextoa(123); + end + else if (cyc == 15) begin + `checks(s, "7b"); + s.octtoa(123); + end + else if (cyc == 16) begin + `checks(s, "173"); + s.bintoa(123); + end + else if (cyc == 17) begin + `checks(s, "1111011"); + s.realtoa(1.23); + end + else if (cyc == 18) begin + `checks(s, "1.23"); + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_string_type_methods_bad.out b/test_regress/t/t_string_type_methods_bad.out index 775bb4aa0..58de90e34 100644 --- a/test_regress/t/t_string_type_methods_bad.out +++ b/test_regress/t/t_string_type_methods_bad.out @@ -1,18 +1,18 @@ -%Error: t/t_string_type_methods_bad.v:15:13: The 1 arguments passed to .len method does not match its requiring 0 arguments +%Error: t/t_string_type_methods_bad.v:15:11: The 1 arguments passed to .len method does not match its requiring 0 arguments : ... note: In instance 't' - 15 | i = s.len(0); - | ^~~ + 15 | i = s.len(0); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_string_type_methods_bad.v:16:9: The 0 arguments passed to .itoa method does not match its requiring 1 arguments +%Error: t/t_string_type_methods_bad.v:16:7: The 0 arguments passed to .itoa method does not match its requiring 1 arguments : ... note: In instance 't' - 16 | s.itoa; - | ^~~~ -%Error: t/t_string_type_methods_bad.v:17:9: The 3 arguments passed to .itoa method does not match its requiring 1 arguments + 16 | s.itoa; + | ^~~~ +%Error: t/t_string_type_methods_bad.v:17:7: The 3 arguments passed to .itoa method does not match its requiring 1 arguments : ... note: In instance 't' - 17 | s.itoa(1,2,3); - | ^~~~ -%Error: t/t_string_type_methods_bad.v:18:9: Unknown built-in string method 'bad_no_such_method' + 17 | s.itoa(1, 2, 3); + | ^~~~ +%Error: t/t_string_type_methods_bad.v:18:7: Unknown built-in string method 'bad_no_such_method' : ... note: In instance 't' - 18 | s.bad_no_such_method(); - | ^~~~~~~~~~~~~~~~~~ + 18 | s.bad_no_such_method(); + | ^~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_string_type_methods_bad.v b/test_regress/t/t_string_type_methods_bad.v index b8434e746..4b43c4085 100644 --- a/test_regress/t/t_string_type_methods_bad.v +++ b/test_regress/t/t_string_type_methods_bad.v @@ -6,16 +6,16 @@ module t; - string s; - integer i; + string s; + integer i; - // Check constification - initial begin - s="1234"; - i = s.len(0); // BAD - s.itoa; // BAD - s.itoa(1,2,3); // BAD - s.bad_no_such_method(); // BAD - end + // Check constification + initial begin + s = "1234"; + i = s.len(0); // BAD + s.itoa; // BAD + s.itoa(1, 2, 3); // BAD + s.bad_no_such_method(); // BAD + end endmodule diff --git a/test_regress/t/t_struct_anon.v b/test_regress/t/t_struct_anon.v index c2a62119a..7ccafed05 100644 --- a/test_regress/t/t_struct_anon.v +++ b/test_regress/t/t_struct_anon.v @@ -6,21 +6,21 @@ // Anonymous struct packed { - logic [31:0] val1; - logic [31:0] val2; + logic [31:0] val1; + logic [31:0] val2; } struct1; struct packed { - logic [31:0] val3; - logic [31:0] val4; + logic [31:0] val3; + logic [31:0] val4; } struct2; module t ( output logic [63:0] s1, output logic [63:0] s2 ); - initial struct1 = 64'h123456789_abcdef0; - always_comb s1 = struct1; - initial struct2 = 64'h123456789_abcdef0; - always_comb s2 = struct2; + initial struct1 = 64'h123456789_abcdef0; + always_comb s1 = struct1; + initial struct2 = 64'h123456789_abcdef0; + always_comb s2 = struct2; endmodule diff --git a/test_regress/t/t_struct_array.v b/test_regress/t/t_struct_array.v index 71f069fc7..fd4b85594 100644 --- a/test_regress/t/t_struct_array.v +++ b/test_regress/t/t_struct_array.v @@ -5,33 +5,34 @@ // SPDX-License-Identifier: CC0-1.0 package TEST_TYPES; - typedef struct a_struct_t; // Forward - typedef struct packed { - logic stuff; - } a_struct_t; -endpackage // TEST_TYPES + typedef struct a_struct_t; // Forward + typedef struct packed {logic stuff;} a_struct_t; +endpackage // TEST_TYPES -module t(clk); - input clk; - TEST_TYPES::a_struct_t [3:0] a_out; - sub sub (.a_out); - always @ (posedge clk) begin - if (a_out[0] != 1'b0) $stop; - if (a_out[1] != 1'b1) $stop; - if (a_out[2] != 1'b0) $stop; - if (a_out[3] != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end +module t ( + clk +); + input clk; + TEST_TYPES::a_struct_t [3:0] a_out; + sub sub (.a_out); + always @(posedge clk) begin + if (a_out[0] != 1'b0) $stop; + if (a_out[1] != 1'b1) $stop; + if (a_out[2] != 1'b0) $stop; + if (a_out[3] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub(a_out); - parameter N = 4; - output TEST_TYPES::a_struct_t [N-1:0] a_out; - always_comb begin - for (int i=0;i 0) begin - bar_in = '1; // Switch to 1 after the first cycle - end - - @(negedge clk); - - // Check if the output field0 has changed - $display("bar_out.field0 = %h", bar_out.field0); - $display("initOut.field0 = %h", initOut.field0); - if (bar_out.field0 !== initOut.field0) begin - $display("%%Error: bar_out value changed when it should not have"); - $stop; - end + // Apply stimulus for 10 clock cycles + for (i = 0; i < 10; i = i + 1) begin + if (i > 0) begin + bar_in = '1; // Switch to 1 after the first cycle end - $write("*-* All Finished *-*\n"); - $finish; + @(negedge clk); + + // Check if the output field0 has changed + $display("bar_out.field0 = %h", bar_out.field0); + $display("initOut.field0 = %h", initOut.field0); + if (bar_out.field0 !== initOut.field0) begin + $display("%%Error: bar_out value changed when it should not have"); + $stop; + end end + $write("*-* All Finished *-*\n"); + $finish; + end + endmodule -module Sub - ( - input str_t bar_in, - output str_t bar_out - ); +module Sub ( + input str_t bar_in, + output str_t bar_out +); - // This is a continuous assignment - always_comb begin - bar_out.field1 = bar_in.field1; - end + // This is a continuous assignment + always_comb begin + bar_out.field1 = bar_in.field1; + end - // This should be an initial assignment, but verilator thinks it's a continous assignment - logic temp0 = bar_in.field0; - // If it is observed (verilator public, coverage, etc.), then it switches correctly to initial - // logic temp0 /* verilator public */ = bar_in.field0; + // This should be an initial assignment, but verilator thinks it's a continous assignment + logic temp0 = bar_in.field0; + // If it is observed (verilator public, coverage, etc.), then it switches correctly to initial + // logic temp0 /* verilator public */ = bar_in.field0; - always_comb begin - bar_out.field0 = temp0; - end + always_comb begin + bar_out.field0 = temp0; + end endmodule diff --git a/test_regress/t/t_struct_literal_param.v b/test_regress/t/t_struct_literal_param.v index ed4e6d354..7fef3081f 100644 --- a/test_regress/t/t_struct_literal_param.v +++ b/test_regress/t/t_struct_literal_param.v @@ -5,9 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 package Some_pkg; - typedef struct packed { - int foo; - } some_struct_t; + typedef struct packed {int foo;} some_struct_t; endpackage module sub #( @@ -15,24 +13,16 @@ module sub #( ) (); endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - sub #( - .the_some_struct( - Some_pkg::some_struct_t'{ - foo: 1 - })) - the_sub (); + sub #(.the_some_struct(Some_pkg::some_struct_t'{foo: 1})) the_sub (); endmodule diff --git a/test_regress/t/t_struct_nest.v b/test_regress/t/t_struct_nest.v index 145233c83..7516c6bc4 100644 --- a/test_regress/t/t_struct_nest.v +++ b/test_regress/t/t_struct_nest.v @@ -5,34 +5,34 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - logic [1:0] b1; - logic [1:0] b2; - logic [1:0] b3; - logic [1:0] b4; + logic [1:0] b1; + logic [1:0] b2; + logic [1:0] b3; + logic [1:0] b4; } t__aa_bbbbbbb_ccccc_dddddd_eee; typedef struct packed { - logic [31:0] a; - union packed { - logic [7:0] fbyte; - t__aa_bbbbbbb_ccccc_dddddd_eee pairs; - } b1; - logic [23:0] b2; - logic [7:0] c1; - logic [23:0] c2; - logic [31:0] d; + logic [31:0] a; + union packed { + logic [7:0] fbyte; + t__aa_bbbbbbb_ccccc_dddddd_eee pairs; + } b1; + logic [23:0] b2; + logic [7:0] c1; + logic [23:0] c2; + logic [31:0] d; } t__aa_bbbbbbb_ccccc_dddddd; typedef struct packed { - logic [31:0] a; - logic [31:0] b; - logic [31:0] c; - logic [31:0] d; + logic [31:0] a; + logic [31:0] b; + logic [31:0] c; + logic [31:0] d; } t__aa_bbbbbbb_ccccc_eee; typedef union packed { - t__aa_bbbbbbb_ccccc_dddddd dddddd; - t__aa_bbbbbbb_ccccc_eee eee; + t__aa_bbbbbbb_ccccc_dddddd dddddd; + t__aa_bbbbbbb_ccccc_eee eee; } t__aa_bbbbbbb_ccccc; @@ -40,6 +40,6 @@ module t ( input t__aa_bbbbbbb_ccccc xxxxxxx_yyyyy_zzzz, output logic [15:0] datao_pre ); - always_comb datao_pre = { xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1 }; + always_comb datao_pre = {xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1}; endmodule diff --git a/test_regress/t/t_struct_nest_uarray.v b/test_regress/t/t_struct_nest_uarray.v index 875e290e3..0a2148d4f 100644 --- a/test_regress/t/t_struct_nest_uarray.v +++ b/test_regress/t/t_struct_nest_uarray.v @@ -4,39 +4,42 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on +// verilog_format: off typedef struct { - struct { - struct { - logic [31:0] next; - } val; - } el[1]; + struct { + struct { + logic [31:0] next; + } val; + } el[1]; } pstr_t; module t; - typedef struct { + typedef struct { + struct { struct { - struct { - logic [31:0] next; - } val; - } el[1]; - } str_t; + logic [31:0] next; + } val; + } el[1]; + } str_t; - str_t str; - pstr_t pstr; + str_t str; + pstr_t pstr; - initial begin - str.el[0].val.next = 6; - `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); + initial begin + str.el[0].val.next = 6; + `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); - pstr.el[0].val.next = 6; - `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); + pstr.el[0].val.next = 6; + `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_notfound_bad.out b/test_regress/t/t_struct_notfound_bad.out index 37612f978..954cc5b06 100644 --- a/test_regress/t/t_struct_notfound_bad.out +++ b/test_regress/t/t_struct_notfound_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_struct_notfound_bad.v:13:9: Member 'nfmember' not found in structure +%Error: t/t_struct_notfound_bad.v:13:7: Member 'nfmember' not found in structure : ... note: In instance 't' - 13 | s.nfmember = 0; - | ^~~~~~~~ + 13 | s.nfmember = 0; + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_struct_notfound_bad.v b/test_regress/t/t_struct_notfound_bad.v index 1bcdac5e4..ce26fe84d 100644 --- a/test_regress/t/t_struct_notfound_bad.v +++ b/test_regress/t/t_struct_notfound_bad.v @@ -6,11 +6,11 @@ module t; - typedef struct packed { bit m; } struct_t; - struct_t s; + typedef struct packed {bit m;} struct_t; + struct_t s; - initial begin - s.nfmember = 0; // Member not found - $finish; - end + initial begin + s.nfmember = 0; // Member not found + $finish; + end endmodule diff --git a/test_regress/t/t_struct_packed_init_bad.out b/test_regress/t/t_struct_packed_init_bad.out index 7b43998e6..7447b4bc7 100644 --- a/test_regress/t/t_struct_packed_init_bad.out +++ b/test_regress/t/t_struct_packed_init_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_struct_packed_init_bad.v:12:17: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.2) +%Error: t/t_struct_packed_init_bad.v:12:15: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.2) : ... note: In instance 't' - 12 | bit [3:0] m_lo = P; - | ^~~~ + 12 | bit [3:0] m_lo = P; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_struct_packed_init_bad.v b/test_regress/t/t_struct_packed_init_bad.v index e372dd52f..06c9dd321 100644 --- a/test_regress/t/t_struct_packed_init_bad.v +++ b/test_regress/t/t_struct_packed_init_bad.v @@ -6,16 +6,16 @@ module t; - parameter P = 4'h5; + parameter P = 4'h5; - struct packed { - bit [3:0] m_lo = P; // Bad - bit [3:0] m_hi; - } s; + struct packed { + bit [3:0] m_lo = P; // Bad + bit [3:0] m_hi; + } s; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_packed_sysfunct.v b/test_regress/t/t_struct_packed_sysfunct.v index 915801203..7cf0e883b 100644 --- a/test_regress/t/t_struct_packed_sysfunct.v +++ b/test_regress/t/t_struct_packed_sysfunct.v @@ -4,60 +4,56 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_dsc; // descendng range structure + /* verilator lint_off ASCRANGE */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ - // packed structures - struct packed { - logic e0; - logic [1:0] e1; - logic [3:0] e2; - logic [7:0] e3; - } struct_dsc; // descendng range structure - /* verilator lint_off ASCRANGE */ - struct packed { - logic e0; - logic [0:1] e1; - logic [0:3] e2; - logic [0:7] e3; - } struct_asc; // ascending range structure - /* verilator lint_on ASCRANGE */ + integer cnt = 0; - integer cnt = 0; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) - begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if (cnt==2) begin + // finish report + always @(posedge clk) + if (cnt == 2) begin $write("*-* All Finished *-*\n"); $finish; - end + end - always @ (posedge clk) - if (cnt==1) begin + always @(posedge clk) + if (cnt == 1) begin // descending range - if ($bits (struct_dsc ) != 15) $stop; - if ($bits (struct_dsc.e0) != 1) $stop; - if ($bits (struct_dsc.e1) != 2) $stop; - if ($bits (struct_dsc.e2) != 4) $stop; - if ($bits (struct_dsc.e3) != 8) $stop; - if ($increment (struct_dsc, 1) != 1) $stop; + if ($bits(struct_dsc) != 15) $stop; + if ($bits(struct_dsc.e0) != 1) $stop; + if ($bits(struct_dsc.e1) != 2) $stop; + if ($bits(struct_dsc.e2) != 4) $stop; + if ($bits(struct_dsc.e3) != 8) $stop; + if ($increment(struct_dsc, 1) != 1) $stop; // ascending range - if ($bits (struct_asc ) != 15) $stop; - if ($bits (struct_asc.e0) != 1) $stop; - if ($bits (struct_asc.e1) != 2) $stop; - if ($bits (struct_asc.e2) != 4) $stop; - if ($bits (struct_asc.e3) != 8) $stop; - if ($increment (struct_asc, 1) != 1) $stop; // Structure itself always big numbered - end + if ($bits(struct_asc) != 15) $stop; + if ($bits(struct_asc.e0) != 1) $stop; + if ($bits(struct_asc.e1) != 2) $stop; + if ($bits(struct_asc.e2) != 4) $stop; + if ($bits(struct_asc.e3) != 8) $stop; + if ($increment(struct_asc, 1) != 1) $stop; // Structure itself always big numbered + end endmodule diff --git a/test_regress/t/t_struct_packed_value_list.v b/test_regress/t/t_struct_packed_value_list.v index 284c0eae6..f582fcefe 100644 --- a/test_regress/t/t_struct_packed_value_list.v +++ b/test_regress/t/t_struct_packed_value_list.v @@ -4,112 +4,184 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + localparam NO = 7; // number of access events - localparam NO = 7; // number of access events + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_dsc; // descending range structure + /* verilator lint_off ASCRANGE */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ - // packed structures - struct packed { - logic e0; - logic [1:0] e1; - logic [3:0] e2; - logic [7:0] e3; - } struct_dsc; // descending range structure - /* verilator lint_off ASCRANGE */ - struct packed { - logic e0; - logic [0:1] e1; - logic [0:3] e2; - logic [0:7] e3; - } struct_asc; // ascending range structure - /* verilator lint_on ASCRANGE */ + localparam WS = 15; // $bits(struct_dsc) - localparam WS = 15; // $bits(struct_dsc) + integer cnt = 0; - integer cnt = 0; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) - begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + // finish report + always @(posedge clk) + if ((cnt[30:2] == (NO - 1)) && (cnt[1:0] == 2'd3)) begin $write("*-* All Finished *-*\n"); $finish; - end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin + // descending range + always @(posedge clk) + if (cnt[1:0] == 2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]==0) struct_dsc <= '0; - else if (cnt[30:2]==1) struct_dsc <= '0; - else if (cnt[30:2]==2) struct_dsc <= '0; - else if (cnt[30:2]==3) struct_dsc <= '0; - else if (cnt[30:2]==4) struct_dsc <= '0; - else if (cnt[30:2]==5) struct_dsc <= '0; - else if (cnt[30:2]==6) struct_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin + if (cnt[30:2] == 0) struct_dsc <= '0; + else if (cnt[30:2] == 1) struct_dsc <= '0; + else if (cnt[30:2] == 2) struct_dsc <= '0; + else if (cnt[30:2] == 3) struct_dsc <= '0; + else if (cnt[30:2] == 4) struct_dsc <= '0; + else if (cnt[30:2] == 5) struct_dsc <= '0; + else if (cnt[30:2] == 6) struct_dsc <= '0; + end + else if (cnt[1:0] == 2'd1) begin // write data into whole or part of the array using literals - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_dsc <= '{0 ,1 , 2, 3}; - else if (cnt[30:2]==2) struct_dsc <= '{e0:1, e1:2, e2:3, e3:4}; - else if (cnt[30:2]==3) struct_dsc <= '{e3:6, e2:4, e1:2, e0:0}; + if (cnt[30:2] == 0) begin + end + else if (cnt[30:2] == 1) struct_dsc <= '{0, 1, 2, 3}; + else if (cnt[30:2] == 2) struct_dsc <= '{e0: 1, e1: 2, e2: 3, e3: 4}; + else if (cnt[30:2] == 3) struct_dsc <= '{e3: 6, e2: 4, e1: 2, e0: 0}; // verilator lint_off WIDTH - else if (cnt[30:2]==4) struct_dsc <= '{default:13}; - else if (cnt[30:2]==5) struct_dsc <= '{e2:8'haa, default:1}; - else if (cnt[30:2]==6) struct_dsc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + else if (cnt[30:2] == 4) struct_dsc <= '{default: 13}; + else if (cnt[30:2] == 5) struct_dsc <= '{e2: 8'haa, default: 1}; + else if (cnt[30:2] == 6) struct_dsc <= '{cnt + 0, cnt + 1, cnt + 2, cnt + 3}; // verilator lint_on WIDTH - end else if (cnt[1:0]==2'd2) begin + end + else if (cnt[1:0] == 2'd2) begin // chack array agains expected value - if (cnt[30:2]==0) begin if (struct_dsc !== 15'b0_00_0000_00000000) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b0_01_0010_00000011) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b1_10_0011_00000100) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b0_10_0100_00000110) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b1_01_1101_00001101) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b1_01_1010_00000001) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==6) begin if (struct_dsc !== 15'b1_10_1011_00011100) begin $display("%b", struct_dsc); $stop(); end end - end + if (cnt[30:2] == 0) begin + if (struct_dsc !== 15'b0_00_0000_00000000) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 1) begin + if (struct_dsc !== 15'b0_01_0010_00000011) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 2) begin + if (struct_dsc !== 15'b1_10_0011_00000100) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 3) begin + if (struct_dsc !== 15'b0_10_0100_00000110) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 4) begin + if (struct_dsc !== 15'b1_01_1101_00001101) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 5) begin + if (struct_dsc !== 15'b1_01_1010_00000001) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 6) begin + if (struct_dsc !== 15'b1_10_1011_00011100) begin + $display("%b", struct_dsc); + $stop(); + end + end + end - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin + // ascending range + always @(posedge clk) + if (cnt[1:0] == 2'd0) begin // initialize to defaults (all bits 1'b0) - if (cnt[30:2]==0) struct_asc <= '0; - else if (cnt[30:2]==1) struct_asc <= '0; - else if (cnt[30:2]==2) struct_asc <= '0; - else if (cnt[30:2]==3) struct_asc <= '0; - else if (cnt[30:2]==4) struct_asc <= '0; - else if (cnt[30:2]==5) struct_asc <= '0; - else if (cnt[30:2]==6) struct_asc <= '0; - end else if (cnt[1:0]==2'd1) begin + if (cnt[30:2] == 0) struct_asc <= '0; + else if (cnt[30:2] == 1) struct_asc <= '0; + else if (cnt[30:2] == 2) struct_asc <= '0; + else if (cnt[30:2] == 3) struct_asc <= '0; + else if (cnt[30:2] == 4) struct_asc <= '0; + else if (cnt[30:2] == 5) struct_asc <= '0; + else if (cnt[30:2] == 6) struct_asc <= '0; + end + else if (cnt[1:0] == 2'd1) begin // write data into whole or part of the array using literals - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_asc <= '{0 ,1 , 2, 3}; - else if (cnt[30:2]==2) struct_asc <= '{e0:1, e1:2, e2:3, e3:4}; - else if (cnt[30:2]==3) struct_asc <= '{e3:6, e2:4, e1:2, e0:0}; + if (cnt[30:2] == 0) begin + end + else if (cnt[30:2] == 1) struct_asc <= '{0, 1, 2, 3}; + else if (cnt[30:2] == 2) struct_asc <= '{e0: 1, e1: 2, e2: 3, e3: 4}; + else if (cnt[30:2] == 3) struct_asc <= '{e3: 6, e2: 4, e1: 2, e0: 0}; // verilator lint_off WIDTH - else if (cnt[30:2]==4) struct_asc <= '{default:13}; - else if (cnt[30:2]==5) struct_asc <= '{e2:8'haa, default:1}; - else if (cnt[30:2]==6) struct_asc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + else if (cnt[30:2] == 4) struct_asc <= '{default: 13}; + else if (cnt[30:2] == 5) struct_asc <= '{e2: 8'haa, default: 1}; + else if (cnt[30:2] == 6) struct_asc <= '{cnt + 0, cnt + 1, cnt + 2, cnt + 3}; // verilator lint_on WIDTH - end else if (cnt[1:0]==2'd2) begin + end + else if (cnt[1:0] == 2'd2) begin // chack array agains expected value - if (cnt[30:2]==0) begin if (struct_asc !== 15'b0_00_0000_00000000) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_asc !== 15'b0_01_0010_00000011) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_asc !== 15'b1_10_0011_00000100) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_asc !== 15'b0_10_0100_00000110) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_asc !== 15'b1_01_1101_00001101) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_asc !== 15'b1_01_1010_00000001) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==6) begin if (struct_asc !== 15'b1_10_1011_00011100) begin $display("%b", struct_asc); $stop(); end end - end + if (cnt[30:2] == 0) begin + if (struct_asc !== 15'b0_00_0000_00000000) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 1) begin + if (struct_asc !== 15'b0_01_0010_00000011) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 2) begin + if (struct_asc !== 15'b1_10_0011_00000100) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 3) begin + if (struct_asc !== 15'b0_10_0100_00000110) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 4) begin + if (struct_asc !== 15'b1_01_1101_00001101) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 5) begin + if (struct_asc !== 15'b1_01_1010_00000001) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 6) begin + if (struct_asc !== 15'b1_10_1011_00011100) begin + $display("%b", struct_asc); + $stop(); + end + end + end endmodule diff --git a/test_regress/t/t_struct_packed_write_read.v b/test_regress/t/t_struct_packed_write_read.v index 80e434440..77288c89c 100644 --- a/test_regress/t/t_struct_packed_write_read.v +++ b/test_regress/t/t_struct_packed_write_read.v @@ -4,118 +4,206 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + localparam NO = 10; // number of access events - localparam NO = 10; // number of access events + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_dsc; // descending range structure + /* verilator lint_off ASCRANGE */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_asc; // ascending range structure + /* verilator lint_on ASCRANGE */ - // packed structures - struct packed { - logic e0; - logic [1:0] e1; - logic [3:0] e2; - logic [7:0] e3; - } struct_dsc; // descending range structure - /* verilator lint_off ASCRANGE */ - struct packed { - logic e0; - logic [0:1] e1; - logic [0:3] e2; - logic [0:7] e3; - } struct_asc; // ascending range structure - /* verilator lint_on ASCRANGE */ + localparam WS = 15; // $bits(struct_dsc) - localparam WS = 15; // $bits(struct_dsc) + integer cnt = 0; - integer cnt = 0; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) - begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + // finish report + always @(posedge clk) + if ((cnt[30:2] == NO) && (cnt[1:0] == 2'd0)) begin $write("*-* All Finished *-*\n"); $finish; - end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin + // descending range + always @(posedge clk) + if (cnt[1:0] == 2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) struct_dsc <= '0; - else if (cnt[30:2]==1) struct_dsc <= '0; - else if (cnt[30:2]==2) struct_dsc <= '0; - else if (cnt[30:2]==3) struct_dsc <= '0; - else if (cnt[30:2]==4) struct_dsc <= '0; - else if (cnt[30:2]==5) struct_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin + if (cnt[30:2] == 0) struct_dsc <= '0; + else if (cnt[30:2] == 1) struct_dsc <= '0; + else if (cnt[30:2] == 2) struct_dsc <= '0; + else if (cnt[30:2] == 3) struct_dsc <= '0; + else if (cnt[30:2] == 4) struct_dsc <= '0; + else if (cnt[30:2] == 5) struct_dsc <= '0; + end + else if (cnt[1:0] == 2'd1) begin // write value to structure - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_dsc <= '1; - else if (cnt[30:2]==2) struct_dsc.e0 <= '1; - else if (cnt[30:2]==3) struct_dsc.e1 <= '1; - else if (cnt[30:2]==4) struct_dsc.e2 <= '1; - else if (cnt[30:2]==5) struct_dsc.e3 <= '1; - end else if (cnt[1:0]==2'd2) begin + if (cnt[30:2] == 0) begin + end + else if (cnt[30:2] == 1) struct_dsc <= '1; + else if (cnt[30:2] == 2) struct_dsc.e0 <= '1; + else if (cnt[30:2] == 3) struct_dsc.e1 <= '1; + else if (cnt[30:2] == 4) struct_dsc.e2 <= '1; + else if (cnt[30:2] == 5) struct_dsc.e3 <= '1; + end + else if (cnt[1:0] == 2'd2) begin // check structure value - if (cnt[30:2]==0) begin if (struct_dsc !== 15'b000000000000000) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b111111111111111) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b100000000000000) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b011000000000000) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b000111100000000) begin $display("%b", struct_dsc); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b000000011111111) begin $display("%b", struct_dsc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin + if (cnt[30:2] == 0) begin + if (struct_dsc !== 15'b000000000000000) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 1) begin + if (struct_dsc !== 15'b111111111111111) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 2) begin + if (struct_dsc !== 15'b100000000000000) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 3) begin + if (struct_dsc !== 15'b011000000000000) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 4) begin + if (struct_dsc !== 15'b000111100000000) begin + $display("%b", struct_dsc); + $stop(); + end + end + else if (cnt[30:2] == 5) begin + if (struct_dsc !== 15'b000000011111111) begin + $display("%b", struct_dsc); + $stop(); + end + end + end + else if (cnt[1:0] == 2'd3) begin // read value from structure (not a very good test for now) - if (cnt[30:2]==0) begin if (struct_dsc !== {WS{1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (struct_dsc !== {WS{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (struct_dsc.e0 !== { 1{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (struct_dsc.e1 !== { 2{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (struct_dsc.e2 !== { 4{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (struct_dsc.e3 !== { 8{1'b1}}) $stop(); end - end + if (cnt[30:2] == 0) begin + if (struct_dsc !== {WS{1'b0}}) $stop(); + end + else if (cnt[30:2] == 1) begin + if (struct_dsc !== {WS{1'b1}}) $stop(); + end + else if (cnt[30:2] == 2) begin + if (struct_dsc.e0 !== {1{1'b1}}) $stop(); + end + else if (cnt[30:2] == 3) begin + if (struct_dsc.e1 !== {2{1'b1}}) $stop(); + end + else if (cnt[30:2] == 4) begin + if (struct_dsc.e2 !== {4{1'b1}}) $stop(); + end + else if (cnt[30:2] == 5) begin + if (struct_dsc.e3 !== {8{1'b1}}) $stop(); + end + end - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin + // ascending range + always @(posedge clk) + if (cnt[1:0] == 2'd0) begin // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) struct_asc <= '0; - else if (cnt[30:2]==1) struct_asc <= '0; - else if (cnt[30:2]==2) struct_asc <= '0; - else if (cnt[30:2]==3) struct_asc <= '0; - else if (cnt[30:2]==4) struct_asc <= '0; - else if (cnt[30:2]==5) struct_asc <= '0; - end else if (cnt[1:0]==2'd1) begin + if (cnt[30:2] == 0) struct_asc <= '0; + else if (cnt[30:2] == 1) struct_asc <= '0; + else if (cnt[30:2] == 2) struct_asc <= '0; + else if (cnt[30:2] == 3) struct_asc <= '0; + else if (cnt[30:2] == 4) struct_asc <= '0; + else if (cnt[30:2] == 5) struct_asc <= '0; + end + else if (cnt[1:0] == 2'd1) begin // write value to structure - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) struct_asc <= '1; - else if (cnt[30:2]==2) struct_asc.e0 <= '1; - else if (cnt[30:2]==3) struct_asc.e1 <= '1; - else if (cnt[30:2]==4) struct_asc.e2 <= '1; - else if (cnt[30:2]==5) struct_asc.e3 <= '1; - end else if (cnt[1:0]==2'd2) begin + if (cnt[30:2] == 0) begin + end + else if (cnt[30:2] == 1) struct_asc <= '1; + else if (cnt[30:2] == 2) struct_asc.e0 <= '1; + else if (cnt[30:2] == 3) struct_asc.e1 <= '1; + else if (cnt[30:2] == 4) struct_asc.e2 <= '1; + else if (cnt[30:2] == 5) struct_asc.e3 <= '1; + end + else if (cnt[1:0] == 2'd2) begin // check structure value - if (cnt[30:2]==0) begin if (struct_asc !== 15'b000000000000000) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==1) begin if (struct_asc !== 15'b111111111111111) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==2) begin if (struct_asc !== 15'b100000000000000) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==3) begin if (struct_asc !== 15'b011000000000000) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==4) begin if (struct_asc !== 15'b000111100000000) begin $display("%b", struct_asc); $stop(); end end - else if (cnt[30:2]==5) begin if (struct_asc !== 15'b000000011111111) begin $display("%b", struct_asc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin + if (cnt[30:2] == 0) begin + if (struct_asc !== 15'b000000000000000) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 1) begin + if (struct_asc !== 15'b111111111111111) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 2) begin + if (struct_asc !== 15'b100000000000000) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 3) begin + if (struct_asc !== 15'b011000000000000) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 4) begin + if (struct_asc !== 15'b000111100000000) begin + $display("%b", struct_asc); + $stop(); + end + end + else if (cnt[30:2] == 5) begin + if (struct_asc !== 15'b000000011111111) begin + $display("%b", struct_asc); + $stop(); + end + end + end + else if (cnt[1:0] == 2'd3) begin // read value from structure (not a very good test for now) - if (cnt[30:2]==0) begin if (struct_asc !== {WS{1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (struct_asc !== {WS{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (struct_asc.e0 !== { 1{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (struct_asc.e1 !== { 2{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (struct_asc.e2 !== { 4{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (struct_asc.e3 !== { 8{1'b1}}) $stop(); end - end + if (cnt[30:2] == 0) begin + if (struct_asc !== {WS{1'b0}}) $stop(); + end + else if (cnt[30:2] == 1) begin + if (struct_asc !== {WS{1'b1}}) $stop(); + end + else if (cnt[30:2] == 2) begin + if (struct_asc.e0 !== {1{1'b1}}) $stop(); + end + else if (cnt[30:2] == 3) begin + if (struct_asc.e1 !== {2{1'b1}}) $stop(); + end + else if (cnt[30:2] == 4) begin + if (struct_asc.e2 !== {4{1'b1}}) $stop(); + end + else if (cnt[30:2] == 5) begin + if (struct_asc.e3 !== {8{1'b1}}) $stop(); + end + end endmodule diff --git a/test_regress/t/t_struct_param_overflow.v b/test_regress/t/t_struct_param_overflow.v index d74bbdc27..c5a6f0e33 100644 --- a/test_regress/t/t_struct_param_overflow.v +++ b/test_regress/t/t_struct_param_overflow.v @@ -33,12 +33,10 @@ package config_pkg; endpackage : config_pkg -module t ( /*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; import config_pkg::*; parameter config_struct_t MY_CONFIG = '{ diff --git a/test_regress/t/t_struct_pat.v b/test_regress/t/t_struct_pat.v index 3f14934b3..5f19946ee 100644 --- a/test_regress/t/t_struct_pat.v +++ b/test_regress/t/t_struct_pat.v @@ -6,108 +6,108 @@ module t; - typedef struct { - int a; - int b; - byte c; - } sabcu_t; + typedef struct { + int a; + int b; + byte c; + } sabcu_t; - typedef struct packed { - int a; - int b; - byte c; - } sabcp_t; + typedef struct packed { + int a; + int b; + byte c; + } sabcp_t; - sabcu_t abcu; - sabcp_t abcp; + sabcu_t abcu; + sabcp_t abcp; - typedef struct { - int a; - int b4[4]; - } sab4u_t; + typedef struct { + int a; + int b4[4]; + } sab4u_t; - typedef struct packed { - int a; - bit [3:0][31:0] b4; - } sab4p_t; + typedef struct packed { + int a; + bit [3:0][31:0] b4; + } sab4p_t; - typedef struct { - int i; - real r; - } sir_t; + typedef struct { + int i; + real r; + } sir_t; - sab4u_t ab4u[2][3]; - sab4p_t ab4p[2][3]; - sir_t sir; + sab4u_t ab4u[2][3]; + sab4p_t ab4p[2][3]; + sir_t sir; - initial begin - abcp = '{1, 2, 3}; - abcu = '{1, 2, 3}; - if (abcp.a !== 1) $stop; - if (abcp.b !== 2) $stop; - if (abcp.c !== 3) $stop; - if (abcu.a !== 1) $stop; - if (abcu.b !== 2) $stop; - if (abcu.c !== 3) $stop; + initial begin + abcp = '{1, 2, 3}; + abcu = '{1, 2, 3}; + if (abcp.a !== 1) $stop; + if (abcp.b !== 2) $stop; + if (abcp.c !== 3) $stop; + if (abcu.a !== 1) $stop; + if (abcu.b !== 2) $stop; + if (abcu.c !== 3) $stop; - abcp = '{3{40}}; - abcu = '{3{40}}; - if (abcp.a !== 40) $stop; - if (abcp.b !== 40) $stop; - if (abcp.c !== 40) $stop; - if (abcu.a !== 40) $stop; - if (abcu.b !== 40) $stop; - if (abcu.c !== 40) $stop; + abcp = '{3{40}}; + abcu = '{3{40}}; + if (abcp.a !== 40) $stop; + if (abcp.b !== 40) $stop; + if (abcp.c !== 40) $stop; + if (abcu.a !== 40) $stop; + if (abcu.b !== 40) $stop; + if (abcu.c !== 40) $stop; - abcp = '{default:4, int:5}; - abcu = '{default:4, int:5}; - if (abcp.a !== 5) $stop; - if (abcp.b !== 5) $stop; - if (abcp.c !== 4) $stop; - if (abcu.a !== 5) $stop; - if (abcu.b !== 5) $stop; - if (abcu.c !== 4) $stop; + abcp = '{default: 4, int : 5}; + abcu = '{default: 4, int : 5}; + if (abcp.a !== 5) $stop; + if (abcp.b !== 5) $stop; + if (abcp.c !== 4) $stop; + if (abcu.a !== 5) $stop; + if (abcu.b !== 5) $stop; + if (abcu.c !== 4) $stop; - abcp = '{int:6, byte:7, int:8}; - abcu = '{int:6, byte:7, int:8}; - if (abcp.a !== 8) $stop; - if (abcp.b !== 8) $stop; - if (abcp.c !== 7) $stop; - if (abcu.a !== 8) $stop; - if (abcu.b !== 8) $stop; - if (abcu.c !== 7) $stop; + abcp = '{int : 6, byte : 7, int : 8}; + abcu = '{int : 6, byte : 7, int : 8}; + if (abcp.a !== 8) $stop; + if (abcp.b !== 8) $stop; + if (abcp.c !== 7) $stop; + if (abcu.a !== 8) $stop; + if (abcu.b !== 8) $stop; + if (abcu.c !== 7) $stop; - ab4p = '{2{'{3{'{10, '{2{20, 30}}}}}}}; - ab4u = '{2{'{3{'{10, '{2{20, 30}}}}}}}; - $display("%p", ab4p); - if (ab4p[0][0].a !== 10) $stop; - if (ab4p[0][0].b4[0] !== 30) $stop; - if (ab4p[0][0].b4[1] !== 20) $stop; - if (ab4p[0][0].b4[2] !== 30) $stop; - if (ab4p[0][0].b4[3] !== 20) $stop; - if (ab4p[1][2].a !== 10) $stop; - if (ab4p[1][2].b4[0] !== 30) $stop; - if (ab4p[1][2].b4[1] !== 20) $stop; - if (ab4p[1][2].b4[2] !== 30) $stop; - if (ab4p[1][2].b4[3] !== 20) $stop; - $display("%p", ab4u); - if (ab4u[0][0].a !== 10) $stop; - if (ab4u[0][0].b4[0] !== 20) $stop; - if (ab4u[0][0].b4[1] !== 30) $stop; - if (ab4u[0][0].b4[2] !== 20) $stop; - if (ab4u[0][0].b4[3] !== 30) $stop; - if (ab4u[1][2].a !== 10) $stop; - if (ab4u[1][2].b4[0] !== 20) $stop; - if (ab4u[1][2].b4[1] !== 30) $stop; - if (ab4u[1][2].b4[2] !== 20) $stop; - if (ab4u[1][2].b4[3] !== 30) $stop; + ab4p = '{2{'{3{'{10, '{2{20, 30}}}}}}}; + ab4u = '{2{'{3{'{10, '{2{20, 30}}}}}}}; + $display("%p", ab4p); + if (ab4p[0][0].a !== 10) $stop; + if (ab4p[0][0].b4[0] !== 30) $stop; + if (ab4p[0][0].b4[1] !== 20) $stop; + if (ab4p[0][0].b4[2] !== 30) $stop; + if (ab4p[0][0].b4[3] !== 20) $stop; + if (ab4p[1][2].a !== 10) $stop; + if (ab4p[1][2].b4[0] !== 30) $stop; + if (ab4p[1][2].b4[1] !== 20) $stop; + if (ab4p[1][2].b4[2] !== 30) $stop; + if (ab4p[1][2].b4[3] !== 20) $stop; + $display("%p", ab4u); + if (ab4u[0][0].a !== 10) $stop; + if (ab4u[0][0].b4[0] !== 20) $stop; + if (ab4u[0][0].b4[1] !== 30) $stop; + if (ab4u[0][0].b4[2] !== 20) $stop; + if (ab4u[0][0].b4[3] !== 30) $stop; + if (ab4u[1][2].a !== 10) $stop; + if (ab4u[1][2].b4[0] !== 20) $stop; + if (ab4u[1][2].b4[1] !== 30) $stop; + if (ab4u[1][2].b4[2] !== 20) $stop; + if (ab4u[1][2].b4[3] !== 30) $stop; - sir = '{1, 2.2}; - if (sir.i !== 1) $stop; - if (sir.r !== 2.2) $stop; + sir = '{1, 2.2}; + if (sir.i !== 1) $stop; + if (sir.r !== 2.2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_pat_width.v b/test_regress/t/t_struct_pat_width.v index 412266eca..fd0ab5ffd 100644 --- a/test_regress/t/t_struct_pat_width.v +++ b/test_regress/t/t_struct_pat_width.v @@ -4,36 +4,35 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - typedef struct packed { - logic [2:0] _foo; - logic [2:0] _bar; - } struct_t; +module t ( + input clk +); - logic [2:0] meh; - struct_t param; - localparam integer TWENTYONE = 21; + typedef struct packed { + logic [2:0] _foo; + logic [2:0] _bar; + } struct_t; - // verilator lint_off WIDTH - assign param = '{ - _foo: TWENTYONE % 8 + 1, - _bar: (TWENTYONE / 8) + 1 - }; - assign meh = TWENTYONE % 8 + 1; - // verilator lint_on WIDTH + logic [2:0] meh; + struct_t param; + localparam integer TWENTYONE = 21; - always @ (posedge clk) begin + // verilator lint_off WIDTH + assign param = '{_foo: TWENTYONE % 8 + 1, _bar: (TWENTYONE / 8) + 1}; + assign meh = TWENTYONE % 8 + 1; + // verilator lint_on WIDTH + + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh); + $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh); `endif - if (param._foo != 6) $stop; - if (param._bar != 3) $stop; - if (param != 6'b110011) $stop; - if (meh != 6) $stop; + if (param._foo != 6) $stop; + if (param._bar != 3) $stop; + if (param != 6'b110011) $stop; + if (meh != 6) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_port.v b/test_regress/t/t_struct_port.v index d4da06ee8..0ae3cd336 100644 --- a/test_regress/t/t_struct_port.v +++ b/test_regress/t/t_struct_port.v @@ -5,79 +5,79 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - bit b9; - byte b1; - bit b0; + bit b9; + byte b1; + bit b0; } pack_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - pack_t in; - always @* in = crc[9:0]; + // Take CRC data and apply to testblock inputs + pack_t in; + always @* in = crc[9:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - pack_t out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + pack_t out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out), - // Inputs - .in (in)); + Test test ( /*AUTOINST*/ + // Outputs + .out(out), + // Inputs + .in(in) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {54'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {54'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n", $time, cyc, crc, in, result); + $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n", $time, cyc, crc, in, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h99c434d9b08c2a8a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h99c434d9b08c2a8a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input pack_t in, - output pack_t out); + input pack_t in, + output pack_t out +); - always @* begin - out = in; - out.b1 = in.b1 + 1; - out.b0 = 1'b1; - end + always @* begin + out = in; + out.b1 = in.b1 + 1; + out.b0 = 1'b1; + end endmodule // Local Variables: diff --git a/test_regress/t/t_struct_portsel.v b/test_regress/t/t_struct_portsel.v index f5b451f1d..3d45b8e11 100644 --- a/test_regress/t/t_struct_portsel.v +++ b/test_regress/t/t_struct_portsel.v @@ -4,102 +4,101 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [19:0] in = crc[19:0]; + // Take CRC data and apply to testblock inputs + wire [19:0] in = crc[19:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [19:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [19:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[19:0]), - // Inputs - .in (in[19:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[19:0]), + // Inputs + .in(in[19:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {44'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {44'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hdb7bc61592f31b99 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hdb7bc61592f31b99 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule typedef struct packed { - logic [7:0] cn; - logic vbfval; - logic vabval; + logic [7:0] cn; + logic vbfval; + logic vabval; } rel_t; -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); - input [19:0] in; - output [19:0] out; + input [19:0] in; + output [19:0] out; - rel_t [1:0] i; // From ifb0 of ifb.v, ... - rel_t [1:0] o; // From ifb0 of ifb.v, ... + rel_t [1:0] i; // From ifb0 of ifb.v, ... + rel_t [1:0] o; // From ifb0 of ifb.v, ... - assign i = in; - assign out = o; + assign i = in; + assign out = o; - sub sub - ( - .i (i[1:0]), - .o (o[1:0])); + sub sub ( + .i(i[1:0]), + .o(o[1:0]) + ); endmodule -module sub (/*AUTOARG*/ - // Outputs - o, - // Inputs - i - ); +module sub ( /*AUTOARG*/ + // Outputs + o, + // Inputs + i +); - input rel_t [1:0] i; - output rel_t [1:0] o; - assign o = i; + input rel_t [1:0] i; + output rel_t [1:0] o; + assign o = i; endmodule // Local Variables: diff --git a/test_regress/t/t_struct_type_bad.out b/test_regress/t/t_struct_type_bad.out index df9829d25..a2c650884 100644 --- a/test_regress/t/t_struct_type_bad.out +++ b/test_regress/t/t_struct_type_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_struct_type_bad.v:13:7: Expecting a data type: 'i' - 13 | i badi; - | ^ +%Error: t/t_struct_type_bad.v:13:5: Expecting a data type: 'i' + 13 | i badi; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_struct_type_bad.v b/test_regress/t/t_struct_type_bad.v index f31b67ec7..622f2e8e8 100644 --- a/test_regress/t/t_struct_type_bad.v +++ b/test_regress/t/t_struct_type_bad.v @@ -6,11 +6,11 @@ module t; - int i; + int i; - typedef struct packed { - int i; - i badi; // Bad - } struct_t; + typedef struct packed { + int i; + i badi; // Bad + } struct_t; endmodule diff --git a/test_regress/t/t_struct_unaligned.v b/test_regress/t/t_struct_unaligned.v index e8a608ed2..e33c66046 100644 --- a/test_regress/t/t_struct_unaligned.v +++ b/test_regress/t/t_struct_unaligned.v @@ -6,31 +6,29 @@ // SPDX-FileCopyrightText: 2014 Jeff Bush // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - struct packed { - logic flag; - logic [130:0] data; - } foo[1]; + struct packed { + logic flag; + logic [130:0] data; + } foo[1]; - integer cyc = 0; + integer cyc = 0; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - foo[0].data <= 0; - foo[0].flag <= !foo[0].flag; - if (cyc==10) begin - if (foo[0].data != 0) begin - $display("bad data value %x", foo[0].data); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + foo[0].data <= 0; + foo[0].flag <= !foo[0].flag; + if (cyc == 10) begin + if (foo[0].data != 0) begin + $display("bad data value %x", foo[0].data); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule diff --git a/test_regress/t/t_struct_unpacked.v b/test_regress/t/t_struct_unpacked.v index ed912ef0f..374ee2fb8 100644 --- a/test_regress/t/t_struct_unpacked.v +++ b/test_regress/t/t_struct_unpacked.v @@ -4,63 +4,63 @@ // SPDX-FileCopyrightText: 2009-2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on class Cls; - typedef struct { - string m_strg; - } underclass_t; + typedef struct {string m_strg;} underclass_t; - underclass_t m_cstr; - function underclass_t get_cstr(); - m_cstr.m_strg = "foo"; - return m_cstr; - endfunction + underclass_t m_cstr; + function underclass_t get_cstr(); + m_cstr.m_strg = "foo"; + return m_cstr; + endfunction endclass module x; - typedef struct { - int a, b; - logic [3:0] c; - } embedded_t; + typedef struct { + int a, b; + logic [3:0] c; + } embedded_t; - typedef struct { - embedded_t b; - embedded_t tab [3:0]; - } notembedded_t; + typedef struct { + embedded_t b; + embedded_t tab[3:0]; + } notembedded_t; - typedef struct { - logic [15:0] m_i; - string m_s; - } istr_t; + typedef struct { + logic [15:0] m_i; + string m_s; + } istr_t; - notembedded_t p; - embedded_t t [1:0]; - istr_t istr; - string s; - Cls c; + notembedded_t p; + embedded_t t[1:0]; + istr_t istr; + string s; + Cls c; - initial begin - t[1].a = 2; - p.b.a = 1; - if (t[1].a != 2) $stop; - if (p.b.a != 1) $stop; + initial begin + t[1].a = 2; + p.b.a = 1; + if (t[1].a != 2) $stop; + if (p.b.a != 1) $stop; - istr.m_i = 12; - istr.m_s = "str1"; - `checkp(istr, "'{m_i:'hc, m_s:\"str1\"}"); + istr.m_i = 12; + istr.m_s = "str1"; + `checkp(istr, "'{m_i:'hc, m_s:\"str1\"}"); - istr = '{m_i: '1, m_s: "str2"}; - `checkp(istr, "'{m_i:'hffff, m_s:\"str2\"}"); + istr = '{m_i: '1, m_s: "str2"}; + `checkp(istr, "'{m_i:'hffff, m_s:\"str2\"}"); - c = new; - s = c.get_cstr().m_strg; - `checks(s, "foo"); + c = new; + s = c.get_cstr().m_strg; + `checks(s, "foo"); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_unpacked_array.v b/test_regress/t/t_struct_unpacked_array.v index 606a8a351..13183d133 100644 --- a/test_regress/t/t_struct_unpacked_array.v +++ b/test_regress/t/t_struct_unpacked_array.v @@ -5,37 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 -typedef struct { - logic a; -} Data_t; +typedef struct {logic a;} Data_t; -module t (/*AUTOARG*/ - clk +module t ( + input clk ); - input clk; - int cyc = 0; - localparam int SIZE = 20; - reg[$clog2(SIZE)-1 : 0] ptr; - Data_t buffer[SIZE]; - Data_t out; - reg out1; + int cyc = 0; - always_ff @( posedge clk ) begin - int i; - cyc <= cyc + 1; - if (cyc == 0) begin - for (i=0;i(b) ? ((a)-(b)) : ((b)-(a))) /(a)) `define stop $stop `define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - integer file; - integer file_a[1]; + integer file; + integer file_a[1]; - integer chars; - reg [1*8:1] letterl; - reg [8*8:1] letterq; - reg signed [8*8:1] letterqs; - reg [16*8:1] letterw; - reg [16*8:1] letterz; - real r; - string s; - reg [16*8:1] si; - integer i; + integer chars; + reg [1*8:1] letterl; + reg [8*8:1] letterq; + reg signed [8*8:1] letterqs; + reg [16*8:1] letterw; + reg [16*8:1] letterz; + real r; + string s; + reg [16*8:1] si; + integer i; - reg [7:0] v_a,v_b,v_c,v_d; - reg [31:0] v_worda; - reg [31:0] v_wordb; + reg [7:0] v_a,v_b,v_c,v_d; + reg [31:0] v_worda; + reg [31:0] v_wordb; - integer v_length, v_off; + integer v_length, v_off; - wire signed [16:0] wire17 = 17'h1ffff; - logic signed [16:0] scan17; + wire signed [16:0] wire17 = 17'h1ffff; + logic signed [16:0] scan17; `ifdef TEST_VERBOSE `define verbose 1'b1 @@ -41,293 +43,293 @@ module t; `define verbose 1'b0 `endif - initial begin - // Display formatting + initial begin + // Display formatting `ifdef verilator - if (file != 0) $stop; - $fwrite(file, "Never printed, file closed\n"); - if (!$feof(file)) $stop; + if (file != 0) $stop; + $fwrite(file, "Never printed, file closed\n"); + if (!$feof(file)) $stop; `endif `ifdef AUTOFLUSH - // The "w" is required so we get a FD not a MFD - file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w"); + // The "w" is required so we get a FD not a MFD + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w"); `else - // The "w" is required so we get a FD not a MFD - file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w"); + // The "w" is required so we get a FD not a MFD + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w"); `endif + if ($feof(file)) $stop; + + $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667); + $fwrite(file, "[%0t] %s\n", $time, "Hello2"); + + i = 12; + $fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i); + $fdisplay(file); + $fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i); + $fdisplayh(file); + $fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i); + $fdisplayo(file); + $fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i); + $fdisplayb(file); + + $fflush(file); + $fflush(); + $fflush; + + $fclose(file); + $fwrite(file, "Never printed, file closed\n"); + + begin + // Check for opening errors + // The "r" is required so we get a FD not a MFD + file = $fopen("DOES_NOT_EXIST","r"); + if (|file) $stop; // Should not exist, IE must return 0 + // Check error function + s = ""; + i = $ferror(file, s); + `checkh(i, 2); + `checks(s, "No such file or directory"); + si = "xx"; + i = $ferror(file, si); + `checkh(i, 2); + end + + begin + // Check quadword access; a little strange, but it's legal to open "." + // Also checks using array reference + file_a[0] = $fopen(".","r"); + if (file_a[0] == 0) $stop; + $fclose(file_a[0]); + end + + begin + // Check read functions w/string + s = "t/t_sys_file_basic_input.dat"; + file = $fopen(s,"r"); + if ($feof(file)) $stop; + $fclose(file); + end + + begin + // Check read functions + file = $fopen("t/t_sys_file_basic_input.dat","r"); if ($feof(file)) $stop; - $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667); - $fwrite(file, "[%0t] %s\n", $time, "Hello2"); + // $fgetc + if ($fgetc(file) != "h") $stop; + if ($fgetc(file) != "i") $stop; + if ($fgetc(file) != "\n") $stop; - i = 12; - $fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i); - $fdisplay(file); - $fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i); - $fdisplayh(file); - $fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i); - $fdisplayo(file); - $fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i); - $fdisplayb(file); + // $ungetc + if ($ungetc("x", file) != 0) $stop; + if ($fgetc(file) != "x") $stop; - $fflush(file); - $fflush(); - $fflush; + // $fgets + chars = $fgets(letterl, file); + if (`verbose) $write("c=%0d l=%s\n", chars, letterl); + if (chars != 1) $stop; + if (letterl != "l") $stop; + + chars = $fgets(letterq, file); + if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline + if (chars != 5) $stop; + if (letterq != "\0\0\0quad\n") $stop; + + letterw = "5432109876543210"; + chars = $fgets(letterw, file); + if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline + if (chars != 10) $stop; + if (letterw != "\0\0\0\0\0\0widestuff\n") $stop; + + s = ""; + chars = $fgets(s, file); + if (`verbose) $write("c=%0d w=%s", chars, s); // Output includes newline + if (chars != 7) $stop; + if (s != "string\n") $stop; + + // $sscanf + if ($sscanf("x","")!=0) $stop; + if ($sscanf("z","z")!=0) $stop; + + chars = $sscanf("blabcdefghijklmnop", + "%s", letterq); + if (`verbose) $write("c=%0d sa=%s\n", chars, letterq); + if (chars != 1) $stop; + if (letterq != "ijklmnop") $stop; + + chars = $sscanf("xa=1f ign=22 xb=12898971238912389712783490823_abcdef689_02348923", + "xa=%x ign=%*d xb=%x", letterq, letterw); + if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h1f) $stop; + if (letterw != 128'h389712783490823_abcdef689_02348923) $stop; + + chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ", + "ba=%b bb=%b%s", letterq, letterw, letterz); + if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz); + if (chars != 3) $stop; + if (letterq != 64'h2) $stop; + if (letterw != 128'hd2a55) $stop; + if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop; + + chars = $sscanf("oa=23 oi=11 ob=125634123615234123681236", + "oa=%o oi=%*o ob=%o", letterq, letterw); + if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h13) $stop; + if (letterw != 128'h55ce14f1a9c29e) $stop; + + chars = $sscanf("r=0.1 d=-236123", + "r=%g d=%d", r, letterq); + if (`verbose) $write("c=%0d d=%d\n", chars, letterq); + if (chars != 2) $stop; + `checkr(r, 0.1); + if (letterq != 64'hfffffffffffc65a5) $stop; + + chars = $sscanf("scan from string", + "scan %s string", s); + if (`verbose) $write("c=%0d s=%s\n", chars, s); + if (chars != 1) $stop; + if (s != "from") $stop; + + // Cover quad and %e/%f + chars = $sscanf("r=0.2", + "r=%e", r); + if (`verbose) $write("c=%0d r=%e\n", chars, r); + `checkr(r, 0.2); + + chars = $sscanf("r=0.3", + "r=%f", r); + if (`verbose) $write("c=%0d r=%f\n", chars, r); + `checkr(r, 0.3); + + s = "r=0.2 d=-236124"; + chars = $sscanf(s, "r=%g d=%d", r, letterq); + if (`verbose) $write("c=%0d d=%d\n", chars, letterq); + if (chars != 2) $stop; + `checkr(r, 0.2); + if (letterq != 64'hfffffffffffc65a4) $stop; + + // $fscanf + if ($fscanf(file,"")!=0) $stop; + + if (!sync("*")) $stop; + chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw); + if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h1f) $stop; + if (letterw != 128'h23790468902348923) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz); + if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz); + if (chars != 3) $stop; + if (letterq != 64'h2) $stop; + if (letterw != 128'hd2a55) $stop; + if (letterz != "\0\0\0\0note_the_two") $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw); + if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h13) $stop; + if (letterw != 128'h1573) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "d=%d", letterq); + if (`verbose) $write("c=%0d d=%0x\n", chars, letterq); + if (chars != 1) $stop; + if (letterq != 64'hfffffffffffc65a5) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "u=%d", letterqs); + if (`verbose) $write("c=%0d u=%0x\n", chars, letterqs); + if (chars != 1) $stop; + if (letterqs != -236124) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "%c%s", letterl, letterw); + if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw); + if (chars != 2) $stop; + if (letterl != "f") $stop; + if (letterw != "\0\0\0\0\0redfishblah") $stop; + + chars = $fscanf(file, "%c", letterl); + if (`verbose) $write("c=%0d l=%x\n", chars, letterl); + if (chars != 1) $stop; + if (letterl != "\n") $stop; + + chars = $fscanf(file, "%c%s not_included\n", letterl, s); + if (`verbose) $write("c=%0d l=%s\n", chars, s); + if (chars != 2) $stop; + if (s != "BCD") $stop; + + // msg1229 + v_a = $fgetc(file); + v_b = $fgetc(file); + v_c = $fgetc(file); + v_d = $fgetc(file); + v_worda = { v_d, v_c, v_b, v_a }; + if (v_worda != "4321") $stop; + + v_wordb[7:0] = $fgetc(file); + v_wordb[15:8] = $fgetc(file); + v_wordb[23:16] = $fgetc(file); + v_wordb[31:24] = $fgetc(file); + if (v_wordb != "9876") $stop; + + if ($fgetc(file) != "\n") $stop; + + + v_length = $ftell(file); + $frewind(file); + v_off = $ftell(file); + if (v_off != 0) $stop; + $fseek(file, 10, 0); + v_off = $ftell(file); + if (v_off != 10) $stop; + $fseek(file, 1, 1); + v_off = $ftell(file); + if (v_off != 11) $stop; + $fseek(file, -1, 1); + v_off = $ftell(file); + if (v_off != 10) $stop; + $fseek(file, v_length, 0); + v_off = $ftell(file); + if (v_off != v_length) $stop; + if ($fseek(file, 0, 2) != 0) $stop; + v_off = $ftell(file); + if (v_off < v_length) $stop; + if ($rewind(file) != 0) $stop; + v_off = $ftell(file); + if (v_off != 0) $stop; $fclose(file); - $fwrite(file, "Never printed, file closed\n"); + end - begin - // Check for opening errors - // The "r" is required so we get a FD not a MFD - file = $fopen("DOES_NOT_EXIST","r"); - if (|file) $stop; // Should not exist, IE must return 0 - // Check error function - s = ""; - i = $ferror(file, s); - `checkh(i, 2); - `checks(s, "No such file or directory"); - si = "xx"; - i = $ferror(file, si); - `checkh(i, 2); - end + begin + $sscanf("-1", "%d", scan17); + if (scan17 !== wire17) $stop; + end - begin - // Check quadword access; a little strange, but it's legal to open "." - // Also checks using array reference - file_a[0] = $fopen(".","r"); - if (file_a[0] == 0) $stop; - $fclose(file_a[0]); - end + $write("*-* All Finished *-*\n"); + $finish(0); // Test arguments to finish + end - begin - // Check read functions w/string - s = "t/t_sys_file_basic_input.dat"; - file = $fopen(s,"r"); - if ($feof(file)) $stop; - $fclose(file); - end - - begin - // Check read functions - file = $fopen("t/t_sys_file_basic_input.dat","r"); - if ($feof(file)) $stop; - - // $fgetc - if ($fgetc(file) != "h") $stop; - if ($fgetc(file) != "i") $stop; - if ($fgetc(file) != "\n") $stop; - - // $ungetc - if ($ungetc("x", file) != 0) $stop; - if ($fgetc(file) != "x") $stop; - - // $fgets - chars = $fgets(letterl, file); - if (`verbose) $write("c=%0d l=%s\n", chars, letterl); - if (chars != 1) $stop; - if (letterl != "l") $stop; - - chars = $fgets(letterq, file); - if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline - if (chars != 5) $stop; - if (letterq != "\0\0\0quad\n") $stop; - - letterw = "5432109876543210"; - chars = $fgets(letterw, file); - if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline - if (chars != 10) $stop; - if (letterw != "\0\0\0\0\0\0widestuff\n") $stop; - - s = ""; - chars = $fgets(s, file); - if (`verbose) $write("c=%0d w=%s", chars, s); // Output includes newline - if (chars != 7) $stop; - if (s != "string\n") $stop; - - // $sscanf - if ($sscanf("x","")!=0) $stop; - if ($sscanf("z","z")!=0) $stop; - - chars = $sscanf("blabcdefghijklmnop", - "%s", letterq); - if (`verbose) $write("c=%0d sa=%s\n", chars, letterq); - if (chars != 1) $stop; - if (letterq != "ijklmnop") $stop; - - chars = $sscanf("xa=1f ign=22 xb=12898971238912389712783490823_abcdef689_02348923", - "xa=%x ign=%*d xb=%x", letterq, letterw); - if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw); - if (chars != 2) $stop; - if (letterq != 64'h1f) $stop; - if (letterw != 128'h389712783490823_abcdef689_02348923) $stop; - - chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ", - "ba=%b bb=%b%s", letterq, letterw, letterz); - if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz); - if (chars != 3) $stop; - if (letterq != 64'h2) $stop; - if (letterw != 128'hd2a55) $stop; - if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop; - - chars = $sscanf("oa=23 oi=11 ob=125634123615234123681236", - "oa=%o oi=%*o ob=%o", letterq, letterw); - if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw); - if (chars != 2) $stop; - if (letterq != 64'h13) $stop; - if (letterw != 128'h55ce14f1a9c29e) $stop; - - chars = $sscanf("r=0.1 d=-236123", - "r=%g d=%d", r, letterq); - if (`verbose) $write("c=%0d d=%d\n", chars, letterq); - if (chars != 2) $stop; - `checkr(r, 0.1); - if (letterq != 64'hfffffffffffc65a5) $stop; - - chars = $sscanf("scan from string", - "scan %s string", s); - if (`verbose) $write("c=%0d s=%s\n", chars, s); - if (chars != 1) $stop; - if (s != "from") $stop; - - // Cover quad and %e/%f - chars = $sscanf("r=0.2", - "r=%e", r); - if (`verbose) $write("c=%0d r=%e\n", chars, r); - `checkr(r, 0.2); - - chars = $sscanf("r=0.3", - "r=%f", r); - if (`verbose) $write("c=%0d r=%f\n", chars, r); - `checkr(r, 0.3); - - s = "r=0.2 d=-236124"; - chars = $sscanf(s, "r=%g d=%d", r, letterq); - if (`verbose) $write("c=%0d d=%d\n", chars, letterq); - if (chars != 2) $stop; - `checkr(r, 0.2); - if (letterq != 64'hfffffffffffc65a4) $stop; - - // $fscanf - if ($fscanf(file,"")!=0) $stop; - - if (!sync("*")) $stop; - chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw); - if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw); - if (chars != 2) $stop; - if (letterq != 64'h1f) $stop; - if (letterw != 128'h23790468902348923) $stop; - - if (!sync("\n")) $stop; - if (!sync("*")) $stop; - chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz); - if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz); - if (chars != 3) $stop; - if (letterq != 64'h2) $stop; - if (letterw != 128'hd2a55) $stop; - if (letterz != "\0\0\0\0note_the_two") $stop; - - if (!sync("\n")) $stop; - if (!sync("*")) $stop; - chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw); - if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw); - if (chars != 2) $stop; - if (letterq != 64'h13) $stop; - if (letterw != 128'h1573) $stop; - - if (!sync("\n")) $stop; - if (!sync("*")) $stop; - chars = $fscanf(file, "d=%d", letterq); - if (`verbose) $write("c=%0d d=%0x\n", chars, letterq); - if (chars != 1) $stop; - if (letterq != 64'hfffffffffffc65a5) $stop; - - if (!sync("\n")) $stop; - if (!sync("*")) $stop; - chars = $fscanf(file, "u=%d", letterqs); - if (`verbose) $write("c=%0d u=%0x\n", chars, letterqs); - if (chars != 1) $stop; - if (letterqs != -236124) $stop; - - if (!sync("\n")) $stop; - if (!sync("*")) $stop; - chars = $fscanf(file, "%c%s", letterl, letterw); - if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw); - if (chars != 2) $stop; - if (letterl != "f") $stop; - if (letterw != "\0\0\0\0\0redfishblah") $stop; - - chars = $fscanf(file, "%c", letterl); - if (`verbose) $write("c=%0d l=%x\n", chars, letterl); - if (chars != 1) $stop; - if (letterl != "\n") $stop; - - chars = $fscanf(file, "%c%s not_included\n", letterl, s); - if (`verbose) $write("c=%0d l=%s\n", chars, s); - if (chars != 2) $stop; - if (s != "BCD") $stop; - - // msg1229 - v_a = $fgetc(file); - v_b = $fgetc(file); - v_c = $fgetc(file); - v_d = $fgetc(file); - v_worda = { v_d, v_c, v_b, v_a }; - if (v_worda != "4321") $stop; - - v_wordb[7:0] = $fgetc(file); - v_wordb[15:8] = $fgetc(file); - v_wordb[23:16] = $fgetc(file); - v_wordb[31:24] = $fgetc(file); - if (v_wordb != "9876") $stop; - - if ($fgetc(file) != "\n") $stop; - - - v_length = $ftell(file); - $frewind(file); - v_off = $ftell(file); - if (v_off != 0) $stop; - $fseek(file, 10, 0); - v_off = $ftell(file); - if (v_off != 10) $stop; - $fseek(file, 1, 1); - v_off = $ftell(file); - if (v_off != 11) $stop; - $fseek(file, -1, 1); - v_off = $ftell(file); - if (v_off != 10) $stop; - $fseek(file, v_length, 0); - v_off = $ftell(file); - if (v_off != v_length) $stop; - if ($fseek(file, 0, 2) != 0) $stop; - v_off = $ftell(file); - if (v_off < v_length) $stop; - if ($rewind(file) != 0) $stop; - v_off = $ftell(file); - if (v_off != 0) $stop; - - $fclose(file); - end - - begin - $sscanf("-1", "%d", scan17); - if (scan17 !== wire17) $stop; - end - - $write("*-* All Finished *-*\n"); - $finish(0); // Test arguments to finish - end - - function sync; - input [7:0] cexp; - reg [7:0] cgot; - begin - cgot = $fgetc(file); - if (`verbose) $write("sync=%x='%c'\n", cgot,cgot); - sync = (cgot == cexp); - end - endfunction + function sync; + input [7:0] cexp; + reg [7:0] cgot; + begin + cgot = $fgetc(file); + if (`verbose) $write("sync=%x='%c'\n", cgot,cgot); + sync = (cgot == cexp); + end + endfunction endmodule diff --git a/test_regress/t/t_sys_file_basic_mcd.v b/test_regress/t/t_sys_file_basic_mcd.v index ddf5b8ff2..b3269a8d6 100644 --- a/test_regress/t/t_sys_file_basic_mcd.v +++ b/test_regress/t/t_sys_file_basic_mcd.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; `define STR(__s) `"__s`" diff --git a/test_regress/t/t_sys_file_eof.v b/test_regress/t/t_sys_file_eof.v index 38e385cc4..bfcc377f3 100644 --- a/test_regress/t/t_sys_file_eof.v +++ b/test_regress/t/t_sys_file_eof.v @@ -4,30 +4,32 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - integer f; - integer i; - integer j; + integer f; + integer i; + integer j; - initial begin - f = $fopen("/does-not-exist", "r"); - `checkd(f, 0); - i = $fscanf(f, "check %d", j); - `checkd(i, -1); - i = $fgetc(f); - `checkd(i, -1); - i = $ftell(f); - `checkd(i, -1); - i = $rewind(f); - `checkd(i, -1); - i = $fseek(f, 0, 0); - `checkd(i, -1); + initial begin + f = $fopen("/does-not-exist", "r"); + `checkd(f, 0); + i = $fscanf(f, "check %d", j); + `checkd(i, -1); + i = $fgetc(f); + `checkd(i, -1); + i = $ftell(f); + `checkd(i, -1); + i = $rewind(f); + `checkd(i, -1); + i = $fseek(f, 0, 0); + `checkd(i, -1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_file_null.v b/test_regress/t/t_sys_file_null.v index 8bc135006..80e32e728 100644 --- a/test_regress/t/t_sys_file_null.v +++ b/test_regress/t/t_sys_file_null.v @@ -7,15 +7,13 @@ `define STRINGIFY(x) `"x`" module t; - integer fd, cnt; - initial begin - fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/zeros.log"}, "w"); - for (cnt = 0; cnt < 4; cnt = cnt + 1) - $fwrite(fd, "%c", 8'd0); - for (cnt = 0; cnt < 16; cnt = cnt + 4) - $fwrite(fd, "%u", 32'd0); - $fclose(fd); - $write("*-* All Finished *-*\n"); - $finish; - end + integer fd, cnt; + initial begin + fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/zeros.log"}, "w"); + for (cnt = 0; cnt < 4; cnt = cnt + 1) $fwrite(fd, "%c", 8'd0); + for (cnt = 0; cnt < 16; cnt = cnt + 4) $fwrite(fd, "%u", 32'd0); + $fclose(fd); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_file_scan.v b/test_regress/t/t_sys_file_scan.v index 88daf2456..be0766692 100644 --- a/test_regress/t/t_sys_file_scan.v +++ b/test_regress/t/t_sys_file_scan.v @@ -7,30 +7,30 @@ `define STRINGIFY(x) `"x`" module t; - integer infile, outfile; - integer count, a; + integer infile, outfile; + integer count, a; - initial begin - infile = $fopen("t/t_sys_file_scan.dat", "r"); - outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w"); + initial begin + infile = $fopen("t/t_sys_file_scan.dat", "r"); + outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_file_scan_test.log"}, "w"); - count = 1234; + count = 1234; `ifdef TEST_VERBOSE - $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); + $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif - count = $fscanf(infile, "%d\n", a); + count = $fscanf(infile, "%d\n", a); `ifdef TEST_VERBOSE - // Ifdefing this out gave bug248 - $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); + // Ifdefing this out gave bug248 + $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif - if (count == 0) $stop; - $fwrite(outfile, "# a\n"); - $fwrite(outfile, "%d\n", a); - $fclose(infile); - $fclose(outfile); + if (count == 0) $stop; + $fwrite(outfile, "# a\n"); + $fwrite(outfile, "%d\n", a); + $fclose(infile); + $fclose(outfile); - $write("*-* All Finished *-*\n"); - $finish(0); // Test arguments to finish - end + $write("*-* All Finished *-*\n"); + $finish(0); // Test arguments to finish + end endmodule diff --git a/test_regress/t/t_sys_file_scan2.v b/test_regress/t/t_sys_file_scan2.v index f1a53b7df..d1d868e60 100644 --- a/test_regress/t/t_sys_file_scan2.v +++ b/test_regress/t/t_sys_file_scan2.v @@ -11,29 +11,29 @@ // verilog_format: on module t; - int cfg_file, f_stat; - reg [8*8:1] fname; - int index; - int count; + int cfg_file, f_stat; + reg [8*8:1] fname; + int index; + int count; - initial begin - cfg_file = $fopen("t/t_sys_file_scan2.dat", "r"); + initial begin + cfg_file = $fopen("t/t_sys_file_scan2.dat", "r"); - f_stat = $fscanf(cfg_file, "%s", fname); - `checkd(f_stat, 1); - `checks(fname, "vec"); - f_stat = $fscanf(cfg_file, "%d", index); - `checkd(f_stat, 1); - `checkd(index, 6163); - f_stat = $fscanf(cfg_file, "%d", count); - `checkd(f_stat, 1); - `checkd(count, 16); + f_stat = $fscanf(cfg_file, "%s", fname); + `checkd(f_stat, 1); + `checks(fname, "vec"); + f_stat = $fscanf(cfg_file, "%d", index); + `checkd(f_stat, 1); + `checkd(index, 6163); + f_stat = $fscanf(cfg_file, "%d", count); + `checkd(f_stat, 1); + `checkd(count, 16); - //eof - f_stat = $fscanf(cfg_file, "%s", fname); - `checkd(f_stat, -1); + //eof + f_stat = $fscanf(cfg_file, "%s", fname); + `checkd(f_stat, -1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_file_zero.v b/test_regress/t/t_sys_file_zero.v index 87c5e9b9b..315b4a273 100644 --- a/test_regress/t/t_sys_file_zero.v +++ b/test_regress/t/t_sys_file_zero.v @@ -4,40 +4,42 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int i; - int v; - string s; - reg [100*8:1] letterl; + int i; + int v; + string s; + reg [100*8:1] letterl; - initial begin - // Display formatting - $fwrite(0, "Never printed, file closed\n"); - i = $feof(0); - if (i == 0) $stop; - $fflush(0); - $fclose(0); - i = $ferror(0, letterl); - i = $fgetc(0); - `checkd(i, -1); - i = $ungetc(0, 0); - `checkd(i, -1); - i = $fgets(letterl, 0); - `checkd(i, 0); - i = $fscanf(0, "%x", v); - `checkd(i, -1); - i = $ftell(0); - `checkd(i, -1); - i = $rewind(0); - `checkd(i, -1); - i = $fseek(0, 10, 0); - `checkd(i, -1); + initial begin + // Display formatting + $fwrite(0, "Never printed, file closed\n"); + i = $feof(0); + if (i == 0) $stop; + $fflush(0); + $fclose(0); + i = $ferror(0, letterl); + i = $fgetc(0); + `checkd(i, -1); + i = $ungetc(0, 0); + `checkd(i, -1); + i = $fgets(letterl, 0); + `checkd(i, 0); + i = $fscanf(0, "%x", v); + `checkd(i, -1); + i = $ftell(0); + `checkd(i, -1); + i = $rewind(0); + `checkd(i, -1); + i = $fseek(0, 10, 0); + `checkd(i, -1); - $write("*-* All Finished *-*\n"); - $finish(0); // Test arguments to finish - end + $write("*-* All Finished *-*\n"); + $finish(0); // Test arguments to finish + end endmodule diff --git a/test_regress/t/t_sys_fmonitor.v b/test_regress/t/t_sys_fmonitor.v index aeb4661a5..a7e88a476 100644 --- a/test_regress/t/t_sys_fmonitor.v +++ b/test_regress/t/t_sys_fmonitor.v @@ -6,52 +6,49 @@ `define STRINGIFY(x) `"x`" -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; + int fd; - int cyc = 0; - int fd; - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); - end - else if (cyc == 10) begin - $fmonitor(fd, "[%0t] cyc=%0d", $time, cyc); - $fmonitor(fd, "[%0t] cyc=%0d also", $time, cyc); - end - else if (cyc == 17) begin - $fmonitorb(fd, cyc, "b"); - end - else if (cyc == 18) begin - $fmonitorh(fd, cyc, "h"); - end - else if (cyc == 19) begin - $fmonitoro(fd, cyc, "o"); - end - else if (cyc == 22) begin - $fmonitor(fd, "[%0t] cyc=%0d new-monitor", $time, cyc); - end - else if (cyc == 24) begin - // IEEE suggests $monitoroff doesn't affect $fmonitor, but - // other simulators believe it does - $monitoroff; - end - else if (cyc == 26) begin - $monitoron; - end - else if (cyc == 27) begin - $fclose(fd); - end - else if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/open.log"}, "w"); + end + else if (cyc == 10) begin + $fmonitor(fd, "[%0t] cyc=%0d", $time, cyc); + $fmonitor(fd, "[%0t] cyc=%0d also", $time, cyc); + end + else if (cyc == 17) begin + $fmonitorb(fd, cyc, "b"); + end + else if (cyc == 18) begin + $fmonitorh(fd, cyc, "h"); + end + else if (cyc == 19) begin + $fmonitoro(fd, cyc, "o"); + end + else if (cyc == 22) begin + $fmonitor(fd, "[%0t] cyc=%0d new-monitor", $time, cyc); + end + else if (cyc == 24) begin + // IEEE suggests $monitoroff doesn't affect $fmonitor, but + // other simulators believe it does + $monitoroff; + end + else if (cyc == 26) begin + $monitoron; + end + else if (cyc == 27) begin + $fclose(fd); + end + else if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_sys_fscanf_bad.out b/test_regress/t/t_sys_fscanf_bad.out index fb5b42426..1667d755d 100644 --- a/test_regress/t/t_sys_fscanf_bad.out +++ b/test_regress/t/t_sys_fscanf_bad.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:13:7: Unsupported: %l in $fscanf - 13 | $fscanf(file, "%l", i); - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:13:5: Unsupported: %l in $fscanf + 13 | $fscanf(file, "%l", i); + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:14:7: Unsupported: %m in $fscanf - 14 | $fscanf(file, "%m", i); - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:14:5: Unsupported: %m in $fscanf + 14 | $fscanf(file, "%m", i); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sys_fscanf_bad.v b/test_regress/t/t_sys_fscanf_bad.v index 8e93da1a8..6065310b3 100644 --- a/test_regress/t/t_sys_fscanf_bad.v +++ b/test_regress/t/t_sys_fscanf_bad.v @@ -6,13 +6,13 @@ module t; - integer file; - integer i; + integer file; + integer i; - initial begin - $fscanf(file, "%l", i); // Bad - $fscanf(file, "%m", i); // Bad - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $fscanf(file, "%l", i); // Bad + $fscanf(file, "%m", i); // Bad + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_fstrobe.v b/test_regress/t/t_sys_fstrobe.v index 9f935fc8a..4037ef334 100644 --- a/test_regress/t/t_sys_fstrobe.v +++ b/test_regress/t/t_sys_fstrobe.v @@ -6,50 +6,47 @@ `define STRINGIFY(x) `"x`" -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; + int fd; - int cyc = 0; - int fd; - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); - end - else if (cyc == 10) begin - $fstrobe(fd, "[%0t] cyc=%0d", $time, cyc); - $fstrobe(fd, "[%0t] cyc=%0d also", $time, cyc); - end - else if (cyc == 17) begin - $fstrobeb(fd, cyc, "b"); - end - else if (cyc == 18) begin - $fstrobeh(fd, cyc, "h"); - end - else if (cyc == 19) begin - $fstrobeo(fd, cyc, "o"); - end - else if (cyc == 22) begin - $fstrobe(fd, "[%0t] cyc=%0d new-strobe", $time, cyc); - end - else if (cyc == 24) begin - $monitoroff; - end - else if (cyc == 26) begin - $monitoron; - end - else if (cyc == 27) begin - $fclose(fd); - end - else if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/open.log"}, "w"); + end + else if (cyc == 10) begin + $fstrobe(fd, "[%0t] cyc=%0d", $time, cyc); + $fstrobe(fd, "[%0t] cyc=%0d also", $time, cyc); + end + else if (cyc == 17) begin + $fstrobeb(fd, cyc, "b"); + end + else if (cyc == 18) begin + $fstrobeh(fd, cyc, "h"); + end + else if (cyc == 19) begin + $fstrobeo(fd, cyc, "o"); + end + else if (cyc == 22) begin + $fstrobe(fd, "[%0t] cyc=%0d new-strobe", $time, cyc); + end + else if (cyc == 24) begin + $monitoroff; + end + else if (cyc == 26) begin + $monitoron; + end + else if (cyc == 27) begin + $fclose(fd); + end + else if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_sys_monitor.v b/test_regress/t/t_sys_monitor.v index 4e2f9bde2..8ca8321e2 100644 --- a/test_regress/t/t_sys_monitor.v +++ b/test_regress/t/t_sys_monitor.v @@ -4,43 +4,40 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; - int cyc = 0; - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $monitor("[%0t] cyc=%0d", $time, cyc); - end - else if (cyc == 17) begin - $monitorb(cyc, "b"); - end - else if (cyc == 18) begin - $monitorh(cyc, "h"); - end - else if (cyc == 19) begin - $monitoro(cyc, "o"); - end - else if (cyc == 22) begin - $monitor("[%0t] cyc=%0d new-monitor", $time, cyc); - end - else if (cyc == 24) begin - $monitoroff; - end - else if (cyc == 26) begin - $monitoron; - end - else if (cyc == 30) begin - $monitoroff; // To avoid inconsistent output between --vlt and --vltmt - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $monitor("[%0t] cyc=%0d", $time, cyc); + end + else if (cyc == 17) begin + $monitorb(cyc, "b"); + end + else if (cyc == 18) begin + $monitorh(cyc, "h"); + end + else if (cyc == 19) begin + $monitoro(cyc, "o"); + end + else if (cyc == 22) begin + $monitor("[%0t] cyc=%0d new-monitor", $time, cyc); + end + else if (cyc == 24) begin + $monitoroff; + end + else if (cyc == 26) begin + $monitoron; + end + else if (cyc == 30) begin + $monitoroff; // To avoid inconsistent output between --vlt and --vltmt + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_sys_monitor_changes.v b/test_regress/t/t_sys_monitor_changes.v index a0996f0a4..2473a3852 100644 --- a/test_regress/t/t_sys_monitor_changes.v +++ b/test_regress/t/t_sys_monitor_changes.v @@ -6,26 +6,26 @@ module t; - bit clk; - int a, b; + bit clk; + int a, b; - always #10 clk = ~clk; + always #10 clk = ~clk; - initial begin - $monitor("[%0t] a=%0d b=%0d", $time, a, b); - #1; // So not on clock edge - #100; - a = 10; - #10; - b = 20; - #10; - a = 11; - #10; - b = 22; - #100; - #10; - $monitoroff; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $monitor("[%0t] a=%0d b=%0d", $time, a, b); + #1; // So not on clock edge + #100; + a = 10; + #10; + b = 20; + #10; + a = 11; + #10; + b = 22; + #100; + #10; + $monitoroff; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_monitor_dotted.v b/test_regress/t/t_sys_monitor_dotted.v index 2ed12ab3a..25f21b7fb 100644 --- a/test_regress/t/t_sys_monitor_dotted.v +++ b/test_regress/t/t_sys_monitor_dotted.v @@ -5,51 +5,50 @@ // SPDX-License-Identifier: CC0-1.0 interface addsub_ifc; - logic [7:0] a, b; - logic doAdd0; - logic clk; - logic rst_n; - logic [7:0] result; - logic overflow; + logic [7:0] a, b; + logic doAdd0; + logic clk; + logic rst_n; + logic [7:0] result; + logic overflow; endinterface -module adder_sub_8bit - ( - input logic clk, - input logic rst_n, - input logic [7:0] a, - input logic [7:0] b, - input logic doAdd0, - output logic [7:0] result, - output logic overflow - ); +module adder_sub_8bit ( + input logic clk, + input logic rst_n, + input logic [7:0] a, + input logic [7:0] b, + input logic doAdd0, + output logic [7:0] result, + output logic overflow +); - logic [7:0] b_modified; - logic [8:0] temp_result; + logic [7:0] b_modified; + logic [8:0] temp_result; - assign b_modified = doAdd0 ? b : ~b + 8'b1; + assign b_modified = doAdd0 ? b : ~b + 8'b1; - always_comb begin - temp_result = {1'b0, a} + {1'b0, b_modified}; - end + always_comb begin + temp_result = {1'b0, a} + {1'b0, b_modified}; + end - always_ff @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - result <= 8'h0; - overflow <= 1'b0; - end else begin - result <= temp_result[7:0]; - overflow <= (a[7] == b_modified[7] && result[7] != a[7]); - end - end + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + result <= 8'h0; + overflow <= 1'b0; + end + else begin + result <= temp_result[7:0]; + overflow <= (a[7] == b_modified[7] && result[7] != a[7]); + end + end endmodule module t; - addsub_ifc dut_ifc(); + addsub_ifc dut_ifc (); - adder_sub_8bit dut - ( + adder_sub_8bit dut ( .clk(dut_ifc.clk), .rst_n(dut_ifc.rst_n), .a(dut_ifc.a), @@ -57,38 +56,36 @@ module t; .doAdd0(dut_ifc.doAdd0), .result(dut_ifc.result), .overflow(dut_ifc.overflow) - ); + ); - initial begin - dut_ifc.clk = 0; - forever #5 dut_ifc.clk = ~dut_ifc.clk; - end + initial begin + dut_ifc.clk = 0; + forever #5 dut_ifc.clk = ~dut_ifc.clk; + end - initial begin - dut_ifc.rst_n = 0; - dut_ifc.a = 8'h0; - dut_ifc.b = 8'h0; - dut_ifc.doAdd0 = 1'b1; + initial begin + dut_ifc.rst_n = 0; + dut_ifc.a = 8'h0; + dut_ifc.b = 8'h0; + dut_ifc.doAdd0 = 1'b1; - #10 dut_ifc.rst_n = 1; + #10 dut_ifc.rst_n = 1; - #10; - dut_ifc.a = 8'h35; - dut_ifc.b = 8'h42; - dut_ifc.doAdd0 = 1'b1; + #10; + dut_ifc.a = 8'h35; + dut_ifc.b = 8'h42; + dut_ifc.doAdd0 = 1'b1; - #20; - $write("*-* All Finished *-*\n"); - $finish; - end + #20; + $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - $display("[%0t] Initial rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", - $time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, - dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); - $monitor("[%0t] Monitor rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", - $time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, - dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); - end + initial begin + $display("[%0t] Initial rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", $time, + dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); + $monitor("[%0t] Monitor rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", $time, + dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); + end endmodule diff --git a/test_regress/t/t_sys_plusargs.v b/test_regress/t/t_sys_plusargs.v index 0d8ce3b80..45efb4c88 100644 --- a/test_regress/t/t_sys_plusargs.v +++ b/test_regress/t/t_sys_plusargs.v @@ -6,129 +6,129 @@ module t; - integer p_i; // signal type IData - reg [15:0] p_s; // signal type SData - reg [7:0] p_c; // signal type CData - real p_r; // signal type double - reg [7*8:1] p_str; - string sv_str; - reg [7*8:1] p_in; - string sv_in; - integer unread; // never read + integer p_i; // signal type IData + reg [15:0] p_s; // signal type SData + reg [7:0] p_c; // signal type CData + real p_r; // signal type double + reg [7*8:1] p_str; + string sv_str; + reg [7*8:1] p_in; + string sv_in; + integer unread; // never read - initial begin - if ($test$plusargs("PLUS")!==1) $stop; - if ($test$plusargs("PLUSNOT")!==0) $stop; - if ($test$plusargs("PL")!==1) $stop; - //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer - if ($test$plusargs("NOTTHERE")!==0) $stop; + initial begin + if ($test$plusargs("PLUS") !== 1) $stop; + if ($test$plusargs("PLUSNOT") !== 0) $stop; + if ($test$plusargs("PL") !== 1) $stop; + //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer + if ($test$plusargs("NOTTHERE") !== 0) $stop; - sv_in = "PLUS"; + sv_in = "PLUS"; `ifdef VERILATOR - if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation + if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif - if ($test$plusargs(sv_in)!==1) $stop; + if ($test$plusargs(sv_in) !== 1) $stop; - p_i = 10; - if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop; - if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop; - if (p_i !== 10) $stop; + p_i = 10; + if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop; + if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop; + if (p_i !== 10) $stop; - p_i = 0; - if ($value$plusargs("INT=%d", p_i) !== 1) $stop; - if (p_i !== 32'd1234) $stop; + p_i = 0; + if ($value$plusargs("INT=%d", p_i) !== 1) $stop; + if (p_i !== 32'd1234) $stop; - p_i = 0; - if ($value$plusargs("INT=%0d", p_i) !== 1) $stop; - if (p_i !== 32'd1234) $stop; + p_i = 0; + if ($value$plusargs("INT=%0d", p_i) !== 1) $stop; + if (p_i !== 32'd1234) $stop; - p_i = 0; - if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also - if (p_i !== 32'h1234) $stop; + p_i = 0; + if ($value$plusargs("INT=%H", p_i) !== 1) $stop; // tests uppercase % also + if (p_i !== 32'h1234) $stop; - p_i = 0; - // Check octal and WIDTH - if (!$value$plusargs("INT=%o", p_i)) $stop; - if (p_i !== 32'o1234) $stop; + p_i = 0; + // Check octal and WIDTH + if (!$value$plusargs("INT=%o", p_i)) $stop; + if (p_i !== 32'o1234) $stop; - // Check handling of 'SData' type signals (issue #1592) - p_s = 0; - if (!$value$plusargs("INT=%d", p_s)) $stop; - if (p_s !== 16'd1234) $stop; + // Check handling of 'SData' type signals (issue #1592) + p_s = 0; + if (!$value$plusargs("INT=%d", p_s)) $stop; + if (p_s !== 16'd1234) $stop; - // Check handling of 'CData' type signals (issue #1592) - p_c = 0; - if (!$value$plusargs("INT=%d", p_c)) $stop; - if (p_c !== 8'd210) $stop; + // Check handling of 'CData' type signals (issue #1592) + p_c = 0; + if (!$value$plusargs("INT=%d", p_c)) $stop; + if (p_c !== 8'd210) $stop; - // Check handling of 'double' type signals (issue #1619) - p_r = 0; - if (!$value$plusargs("REAL=%e", p_r)) $stop; - $display("r='%e'", p_r); - if (p_r !== 1.2345) $stop; + // Check handling of 'double' type signals (issue #1619) + p_r = 0; + if (!$value$plusargs("REAL=%e", p_r)) $stop; + $display("r='%e'", p_r); + if (p_r !== 1.2345) $stop; - p_r = 0; - if (!$value$plusargs("REAL=%f", p_r)) $stop; - $display("r='%f'", p_r); - if (p_r !== 1.2345) $stop; + p_r = 0; + if (!$value$plusargs("REAL=%f", p_r)) $stop; + $display("r='%f'", p_r); + if (p_r !== 1.2345) $stop; - p_r = 0; - if (!$value$plusargs("REAL=%g", p_r)) $stop; - $display("r='%g'", p_r); - if (p_r !== 1.2345) $stop; + p_r = 0; + if (!$value$plusargs("REAL=%g", p_r)) $stop; + $display("r='%g'", p_r); + if (p_r !== 1.2345) $stop; - p_str = "none"; - if ($value$plusargs("IN%s", p_str)!==1) $stop; - $display("str='%s'",p_str); - if (p_str !== "T=1234") $stop; + p_str = "none"; + if ($value$plusargs("IN%s", p_str) !== 1) $stop; + $display("str='%s'", p_str); + if (p_str !== "T=1234") $stop; - sv_str = "none"; - if ($value$plusargs("IN%s", sv_str)!==1) $stop; - $display("str='%s'",sv_str); - if (sv_str != "T=1234") $stop; + sv_str = "none"; + if ($value$plusargs("IN%s", sv_str) !== 1) $stop; + $display("str='%s'", sv_str); + if (sv_str != "T=1234") $stop; - sv_str = "none"; - $value$plusargs("IN%s", sv_str); - $display("str='%s'",sv_str); - if (sv_str != "T=1234") $stop; + sv_str = "none"; + $value$plusargs("IN%s", sv_str); + $display("str='%s'", sv_str); + if (sv_str != "T=1234") $stop; - p_in = "IN%s"; + p_in = "IN%s"; `ifdef VERILATOR - p_in = $c(p_in); // Prevent constant propagation + p_in = $c(p_in); // Prevent constant propagation `endif - sv_str = "none"; - if ($value$plusargs(p_in, sv_str)!==1) $stop; - $display("str='%s'",sv_str); - if (sv_str != "T=1234") $stop; + sv_str = "none"; + if ($value$plusargs(p_in, sv_str) !== 1) $stop; + $display("str='%s'", sv_str); + if (sv_str != "T=1234") $stop; - sv_str = "none"; - if ($value$plusargs("IP%%P%b", p_i)!==1) $stop; - $display("str='%s'",sv_str); - if (p_i != 'b101) $stop; + sv_str = "none"; + if ($value$plusargs("IP%%P%b", p_i) !== 1) $stop; + $display("str='%s'", sv_str); + if (p_i != 'b101) $stop; - sv_in = "INT=%d"; + sv_in = "INT=%d"; `ifdef VERILATOR - if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation + if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif - p_i = 0; - if ($value$plusargs(sv_in, p_i)!==1) $stop; - $display("i='%d'",p_i); - if (p_i !== 32'd1234) $stop; + p_i = 0; + if ($value$plusargs(sv_in, p_i) !== 1) $stop; + $display("i='%d'", p_i); + if (p_i !== 32'd1234) $stop; - // bug3131 - really "if" side effect test - p_i = 0; - if ($value$plusargs("INT=%d", p_i)) ; - if (p_i !== 32'd1234) $stop; + // bug3131 - really "if" side effect test + p_i = 0; + if ($value$plusargs("INT=%d", p_i)); + if (p_i !== 32'd1234) $stop; - // bug5127 - assign side effect test - p_i = 0; - p_r = 0; - unread = $value$plusargs("INT=%d", p_i); - unread = $value$plusargs("REAL=%e", p_r); - if (p_i !== 32'd1234) $stop; - if (p_r !== 1.2345) $stop; + // bug5127 - assign side effect test + p_i = 0; + p_r = 0; + unread = $value$plusargs("INT=%d", p_i); + unread = $value$plusargs("REAL=%e", p_r); + if (p_i !== 32'd1234) $stop; + if (p_r !== 1.2345) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_plusargs_bad.v b/test_regress/t/t_sys_plusargs_bad.v index 98dfe4dc9..656a9fd1b 100644 --- a/test_regress/t/t_sys_plusargs_bad.v +++ b/test_regress/t/t_sys_plusargs_bad.v @@ -6,19 +6,19 @@ module t; - integer p_i; + integer p_i; - initial begin - // BAD: Missing argument - if ($value$plusargs("NOTTHERE", p_i)!==0) $stop; + initial begin + // BAD: Missing argument + if ($value$plusargs("NOTTHERE", p_i) !== 0) $stop; - // BAD: Bad letter - if ($value$plusargs("INT=%z", p_i)!==0) $stop; + // BAD: Bad letter + if ($value$plusargs("INT=%z", p_i) !== 0) $stop; - // BAD: Multi letter - if ($value$plusargs("INT=%x%x", p_i)!==0) $stop; + // BAD: Multi letter + if ($value$plusargs("INT=%x%x", p_i) !== 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_psprintf.v b/test_regress/t/t_sys_psprintf.v index 84b865e40..4673a6ce3 100644 --- a/test_regress/t/t_sys_psprintf.v +++ b/test_regress/t/t_sys_psprintf.v @@ -6,24 +6,26 @@ module t; - // Note $sformatf already tested elsewhere + // Note $sformatf already tested elsewhere - reg [3:0] n; - reg [63:0] q; - reg [16*8:1] wide; + reg [3:0] n; + reg [63:0] q; + reg [16*8:1] wide; - string str; + string str; - initial begin - n = 4'b1100; - q = 64'h1234_5678_abcd_0123; - wide = "hello-there12345"; - str = $psprintf("n=%b q=%d w=%s", n, q, wide); -`ifdef TEST_VERBOSE $display("str=%0s",str); `endif - if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; + initial begin + n = 4'b1100; + q = 64'h1234_5678_abcd_0123; + wide = "hello-there12345"; + str = $psprintf("n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE + $display("str=%0s", str); +`endif + if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_psprintf_warn_bad.out b/test_regress/t/t_sys_psprintf_warn_bad.out index 0982832f5..6c4f97aa9 100644 --- a/test_regress/t/t_sys_psprintf_warn_bad.out +++ b/test_regress/t/t_sys_psprintf_warn_bad.out @@ -1,6 +1,6 @@ -%Warning-NONSTD: t/t_sys_psprintf.v:21:13: Non-standard system function '$psprintf'; suggest use standard '$sformatf' (IEEE 1800-2023 21.3.3) - 21 | str = $psprintf("n=%b q=%d w=%s", n, q, wide); - | ^~~~~~~~~ +%Warning-NONSTD: t/t_sys_psprintf.v:21:11: Non-standard system function '$psprintf'; suggest use standard '$sformatf' (IEEE 1800-2023 21.3.3) + 21 | str = $psprintf("n=%b q=%d w=%s", n, q, wide); + | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/NONSTD?v=latest ... Use "/* verilator lint_off NONSTD */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_sys_readmem.v b/test_regress/t/t_sys_readmem.v index 1f9d56034..7ac5bfbad 100644 --- a/test_regress/t/t_sys_readmem.v +++ b/test_regress/t/t_sys_readmem.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); @@ -14,271 +15,272 @@ `define READMEMX $readmemh `define WRITEMEMX $writememh `endif +// verilog_format: on module t; - // verilator lint_off ASCRANGE - reg [5:0] binary_string [2:15]; - reg [5:0] binary_nostart [2:15]; - reg [5:0] binary_start [0:15]; - reg [175:0] hex [0:15]; - reg [(32*6)-1:0] hex_align [0:15]; - reg [55:0] qdata [0:15]; - reg [25:0] idata [0:15]; - reg [10:0] sdata [0:15]; - reg [6:0] cdata [0:15]; - string fns; + // verilator lint_off ASCRANGE + reg [5:0] binary_string[2:15]; + reg [5:0] binary_nostart[2:15]; + reg [5:0] binary_start[0:15]; + reg [175:0] hex[0:15]; + reg [(32*6)-1:0] hex_align[0:15]; + reg [55:0] qdata[0:15]; + reg [25:0] idata[0:15]; + reg [10:0] sdata[0:15]; + reg [6:0] cdata[0:15]; + string fns; `ifdef WRITEMEM_READ_BACK - reg [5:0] binary_string_tmp [2:15]; - reg [5:0] binary_nostart_tmp [2:15]; - reg [5:0] binary_start_tmp [0:15]; - reg [175:0] hex_tmp [0:15]; - reg [(32*6)-1:0] hex_align_tmp [0:15]; - reg [55:0] qdata_tmp [0:15]; - reg [25:0] idata_tmp [0:15]; - reg [10:0] sdata_tmp [0:15]; - reg [6:0] cdata_tmp [0:15]; - string fns_tmp; + reg [5:0] binary_string_tmp[2:15]; + reg [5:0] binary_nostart_tmp[2:15]; + reg [5:0] binary_start_tmp[0:15]; + reg [175:0] hex_tmp[0:15]; + reg [(32*6)-1:0] hex_align_tmp[0:15]; + reg [55:0] qdata_tmp[0:15]; + reg [25:0] idata_tmp[0:15]; + reg [10:0] sdata_tmp[0:15]; + reg [6:0] cdata_tmp[0:15]; + string fns_tmp; `endif - // verilator lint_on ASCRANGE + // verilator lint_on ASCRANGE - integer i; + integer i; - initial begin - begin - // Initialize memories to zero, - // avoid differences between 2-state and 4-state. - for (i=0; i<16; i=i+1) begin - binary_start[i] = '0; - hex[i] = '0; - hex_align[i] = '0; - qdata[i] = '0; - idata[i] = '0; - sdata[i] = '0; - cdata[i] = '0; + initial begin + begin + // Initialize memories to zero, + // avoid differences between 2-state and 4-state. + for (i = 0; i < 16; i = i + 1) begin + binary_start[i] = '0; + hex[i] = '0; + hex_align[i] = '0; + qdata[i] = '0; + idata[i] = '0; + sdata[i] = '0; + cdata[i] = '0; `ifdef WRITEMEM_READ_BACK - binary_start_tmp[i] = '0; - hex_tmp[i] = '0; - hex_align_tmp[i] = '0; - qdata_tmp[i] = '0; - idata_tmp[i] = '0; - sdata_tmp[i] = '0; - cdata_tmp[i] = '0; + binary_start_tmp[i] = '0; + hex_tmp[i] = '0; + hex_align_tmp[i] = '0; + qdata_tmp[i] = '0; + idata_tmp[i] = '0; + sdata_tmp[i] = '0; + cdata_tmp[i] = '0; `endif - end - for (i=2; i<16; i=i+1) begin - binary_string[i] = 6'h0; - binary_nostart[i] = 6'h0; -`ifdef WRITEMEM_READ_BACK - binary_string_tmp[i] = 6'h0; - binary_nostart_tmp[i] = 6'h0; -`endif - end end - - begin + for (i = 2; i < 16; i = i + 1) begin + binary_string[i] = 6'h0; + binary_nostart[i] = 6'h0; `ifdef WRITEMEM_READ_BACK - $readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp); - // Do a round-trip $writememh(b) and $readmemh(b) cycle. - // This covers $writememh and ensures we can read our - // own memh output file. - // If WRITEMEM_BIN is also defined, use $writememb and - // $readmemb, otherwise use $writememh and $readmemh. - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP1); - `endif - `WRITEMEMX(`OUT_TMP1, binary_nostart_tmp); - `READMEMX(`OUT_TMP1, binary_nostart); + binary_string_tmp[i] = 6'h0; + binary_nostart_tmp[i] = 6'h0; +`endif + end + end + + begin +`ifdef WRITEMEM_READ_BACK + $readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp); + // Do a round-trip $writememh(b) and $readmemh(b) cycle. + // This covers $writememh and ensures we can read our + // own memh output file. + // If WRITEMEM_BIN is also defined, use $writememb and + // $readmemb, otherwise use $writememh and $readmemh. +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP1); +`endif + `WRITEMEMX(`OUT_TMP1, binary_nostart_tmp); + `READMEMX(`OUT_TMP1, binary_nostart); `else - $readmemb("t/t_sys_readmem_b.mem", binary_nostart); + $readmemb("t/t_sys_readmem_b.mem", binary_nostart); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, binary_nostart[i]); `endif - if (binary_nostart['h2] != 6'h02) $stop; - if (binary_nostart['h3] != 6'h03) $stop; - if (binary_nostart['h4] != 6'h04) $stop; - if (binary_nostart['h5] != 6'h05) $stop; - if (binary_nostart['h6] != 6'h06) $stop; - if (binary_nostart['h7] != 6'h07) $stop; - if (binary_nostart['h8] != 6'h10) $stop; - if (binary_nostart['hc] != 6'h14) $stop; - if (binary_nostart['hd] != 6'h15) $stop; - end + if (binary_nostart['h2] != 6'h02) $stop; + if (binary_nostart['h3] != 6'h03) $stop; + if (binary_nostart['h4] != 6'h04) $stop; + if (binary_nostart['h5] != 6'h05) $stop; + if (binary_nostart['h6] != 6'h06) $stop; + if (binary_nostart['h7] != 6'h07) $stop; + if (binary_nostart['h8] != 6'h10) $stop; + if (binary_nostart['hc] != 6'h14) $stop; + if (binary_nostart['hd] != 6'h15) $stop; + end - begin - binary_start['h0c] = 6'h3f; // Not in read range - // + begin + binary_start['h0c] = 6'h3f; // Not in read range + // `ifdef WRITEMEM_READ_BACK - $readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4+7); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP2); - `endif - `WRITEMEMX(`OUT_TMP2, binary_start_tmp, 4, 4+7); - `READMEMX(`OUT_TMP2, binary_start, 4, 4+7); + $readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4 + 7); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP2); +`endif + `WRITEMEMX(`OUT_TMP2, binary_start_tmp, 4, 4 + 7); + `READMEMX(`OUT_TMP2, binary_start, 4, 4 + 7); `else - $readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7); // 4-11 + $readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4 + 7); // 4-11 `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, binary_start[i]); `endif - if (binary_start['h04] != 6'h10) $stop; - if (binary_start['h05] != 6'h11) $stop; - if (binary_start['h06] != 6'h12) $stop; - if (binary_start['h07] != 6'h13) $stop; - if (binary_start['h08] != 6'h14) $stop; - if (binary_start['h09] != 6'h15) $stop; - if (binary_start['h0a] != 6'h16) $stop; - if (binary_start['h0b] != 6'h17) $stop; - // - if (binary_start['h0c] != 6'h3f) $stop; - end + if (binary_start['h04] != 6'h10) $stop; + if (binary_start['h05] != 6'h11) $stop; + if (binary_start['h06] != 6'h12) $stop; + if (binary_start['h07] != 6'h13) $stop; + if (binary_start['h08] != 6'h14) $stop; + if (binary_start['h09] != 6'h15) $stop; + if (binary_start['h0a] != 6'h16) $stop; + if (binary_start['h0b] != 6'h17) $stop; + // + if (binary_start['h0c] != 6'h3f) $stop; + end - begin - // The 'hex' array is a non-exact multiple of word size - // (possible corner case) + begin + // The 'hex' array is a non-exact multiple of word size + // (possible corner case) `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP3); - `endif - `WRITEMEMX(`OUT_TMP3, hex_tmp, 0); - `READMEMX(`OUT_TMP3, hex, 0); + $readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP3); +`endif + `WRITEMEMX(`OUT_TMP3, hex_tmp, 0); + `READMEMX(`OUT_TMP3, hex, 0); `else - $readmemh("t/t_sys_readmem_h.mem", hex, 0); + $readmemh("t/t_sys_readmem_h.mem", hex, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, hex[i]); `endif - if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop; - if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop; - if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; - if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; - end + if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop; + if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop; + if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; + if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; + end - begin - // The 'hex align' array is similar to 'hex', but it is an - // exact multiple of word size -- another possible corner case. + begin + // The 'hex align' array is similar to 'hex', but it is an + // exact multiple of word size -- another possible corner case. `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP4); - `endif - `WRITEMEMX(`OUT_TMP4, hex_align_tmp, 0); - `READMEMX(`OUT_TMP4, hex_align, 0); + $readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP4); +`endif + `WRITEMEMX(`OUT_TMP4, hex_align_tmp, 0); + `READMEMX(`OUT_TMP4, hex_align, 0); `else - $readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0); + $readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex_align[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, hex_align[i]); `endif - if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop; - if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop; - if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop; - if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop; - end + if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop; + if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop; + if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop; + if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop; + end - begin + begin `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_q.mem", qdata_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP5); - `endif - `WRITEMEMX(`OUT_TMP5, qdata_tmp, 0); - `READMEMX(`OUT_TMP5, qdata, 0); + $readmemh("t/t_sys_readmem_q.mem", qdata_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP5); +`endif + `WRITEMEMX(`OUT_TMP5, qdata_tmp, 0); + `READMEMX(`OUT_TMP5, qdata, 0); `else - $readmemh("t/t_sys_readmem_q.mem", qdata, 0); + $readmemh("t/t_sys_readmem_q.mem", qdata, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, qdata[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, qdata[i]); `endif - `checkh(qdata['h04], 56'hdcba9876540004); - `checkh(qdata['h0a], 56'hdcba987654000a); - `checkh(qdata['h0b], 56'hdcba987654000b); - `checkh(qdata['h0c], 56'hdcba987654000c); - end + `checkh(qdata['h04], 56'hdcba9876540004); + `checkh(qdata['h0a], 56'hdcba987654000a); + `checkh(qdata['h0b], 56'hdcba987654000b); + `checkh(qdata['h0c], 56'hdcba987654000c); + end - begin + begin `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_i.mem", idata_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP6); - `endif - `WRITEMEMX(`OUT_TMP6, idata_tmp, 0); - `READMEMX(`OUT_TMP6, idata, 0); + $readmemh("t/t_sys_readmem_i.mem", idata_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP6); +`endif + `WRITEMEMX(`OUT_TMP6, idata_tmp, 0); + `READMEMX(`OUT_TMP6, idata, 0); `else - $readmemh("t/t_sys_readmem_i.mem", idata, 0); + $readmemh("t/t_sys_readmem_i.mem", idata, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, idata[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, idata[i]); `endif - `checkh(idata['h04], 26'h6540004); - `checkh(idata['h0a], 26'h654000a); - `checkh(idata['h0b], 26'h654000b); - `checkh(idata['h0c], 26'h654000c); - end + `checkh(idata['h04], 26'h6540004); + `checkh(idata['h0a], 26'h654000a); + `checkh(idata['h0b], 26'h654000b); + `checkh(idata['h0c], 26'h654000c); + end - begin + begin `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_s.mem", sdata_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP7); - `endif - `WRITEMEMX(`OUT_TMP7, sdata_tmp, 0); - `READMEMX(`OUT_TMP7, sdata, 0); + $readmemh("t/t_sys_readmem_s.mem", sdata_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP7); +`endif + `WRITEMEMX(`OUT_TMP7, sdata_tmp, 0); + `READMEMX(`OUT_TMP7, sdata, 0); `else - $readmemh("t/t_sys_readmem_s.mem", sdata, 0); + $readmemh("t/t_sys_readmem_s.mem", sdata, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, sdata[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, sdata[i]); `endif - `checkh(sdata['h04], 11'h654); - `checkh(sdata['h0a], 11'h65a); - `checkh(sdata['h0b], 11'h65b); - `checkh(sdata['h0c], 11'h65c); - end + `checkh(sdata['h04], 11'h654); + `checkh(sdata['h0a], 11'h65a); + `checkh(sdata['h0b], 11'h65b); + `checkh(sdata['h0c], 11'h65c); + end - begin + begin `ifdef WRITEMEM_READ_BACK - $readmemh("t/t_sys_readmem_c.mem", cdata_tmp, 0); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP8); - `endif - `WRITEMEMX(`OUT_TMP8, cdata_tmp, 0); - `READMEMX(`OUT_TMP8, cdata, 0); + $readmemh("t/t_sys_readmem_c.mem", cdata_tmp, 0); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP8); +`endif + `WRITEMEMX(`OUT_TMP8, cdata_tmp, 0); + `READMEMX(`OUT_TMP8, cdata, 0); `else - $readmemh("t/t_sys_readmem_c.mem", cdata, 0); + $readmemh("t/t_sys_readmem_c.mem", cdata, 0); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, cdata[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, cdata[i]); `endif - `checkh(cdata['h04], 7'h14); - `checkh(cdata['h0a], 7'h1a); - `checkh(cdata['h0b], 7'h1b); - `checkh(cdata['h0c], 7'h1c); - end + `checkh(cdata['h04], 7'h14); + `checkh(cdata['h0a], 7'h1a); + `checkh(cdata['h0b], 7'h1b); + `checkh(cdata['h0c], 7'h1c); + end - begin - fns = "t/t_sys_readmem_b.mem"; + begin + fns = "t/t_sys_readmem_b.mem"; `ifdef WRITEMEM_READ_BACK - fns_tmp = `OUT_TMP8; - $readmemb(fns, binary_string_tmp); - `ifdef TEST_VERBOSE - $display("-Writing %s", `OUT_TMP8); - `endif - `WRITEMEMX(fns_tmp, binary_string_tmp); - `READMEMX(fns_tmp, binary_string); + fns_tmp = `OUT_TMP8; + $readmemb(fns, binary_string_tmp); +`ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP8); +`endif + `WRITEMEMX(fns_tmp, binary_string_tmp); + `READMEMX(fns_tmp, binary_string); `else - $readmemb(fns, binary_string); + $readmemb(fns, binary_string); `endif `ifdef TEST_VERBOSE - for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_string[i]); + for (i = 0; i < 16; i = i + 1) $write(" @%x = %x\n", i, binary_string[i]); `endif - if (binary_string['h2] != 6'h02) $stop; - end + if (binary_string['h2] != 6'h02) $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_4state.v b/test_regress/t/t_sys_readmem_4state.v index f51af3035..b2ab8c7f5 100644 --- a/test_regress/t/t_sys_readmem_4state.v +++ b/test_regress/t/t_sys_readmem_4state.v @@ -7,19 +7,19 @@ `define STRINGIFY(x) `"x`" module t; - reg [3:0] MEMB [6]; - reg [3:0] MEMH [6]; + reg [3:0] MEMB[6]; + reg [3:0] MEMH[6]; - initial begin - $readmemb("t/t_sys_readmem_4state.mem", MEMB); - $display("MEMB=%p", MEMB); - $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_readmem_4state_b.mem"}, MEMB); + initial begin + $readmemb("t/t_sys_readmem_4state.mem", MEMB); + $display("MEMB=%p", MEMB); + $writememh({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_readmem_4state_b.mem"}, MEMB); - $readmemh("t/t_sys_readmem_4state.mem", MEMH); - $display("MEMH=%p", MEMH); - $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_readmem_4state_h.mem"}, MEMH); + $readmemh("t/t_sys_readmem_4state.mem", MEMH); + $display("MEMH=%p", MEMH); + $writememh({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_readmem_4state_h.mem"}, MEMH); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_assoc.v b/test_regress/t/t_sys_readmem_assoc.v index f4322c997..9884c1b2a 100644 --- a/test_regress/t/t_sys_readmem_assoc.v +++ b/test_regress/t/t_sys_readmem_assoc.v @@ -6,37 +6,35 @@ `define STRINGIFY(x) `"x`" -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc; + int cyc; - reg [5:0] assoc_c[int]; - reg [95:0] assoc_w[int]; + reg [5:0] assoc_c[int]; + reg [95:0] assoc_w[int]; - always_ff @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - assoc_c[300] = 10; // See if clearing must happen first - // Also checks no BLKANDNBLK due to readmem/writemem - end - else if (cyc == 2) begin - $readmemb("t/t_sys_readmem_b.mem", assoc_c); - $display("assoc_c=%p", assoc_c); - $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c); - end - else if (cyc == 3) begin - $readmemb("t/t_sys_readmem_b.mem", assoc_w); - // Not conditional with TEST_VERBOSE as found bug with wide display - $display("assoc_w=%p", assoc_w); - $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w); - end - else if (cyc == 4) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always_ff @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + assoc_c[300] = 10; // See if clearing must happen first + // Also checks no BLKANDNBLK due to readmem/writemem + end + else if (cyc == 2) begin + $readmemb("t/t_sys_readmem_b.mem", assoc_c); + $display("assoc_c=%p", assoc_c); + $writememh({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_writemem_c_b.mem"}, assoc_c); + end + else if (cyc == 3) begin + $readmemb("t/t_sys_readmem_b.mem", assoc_w); + // Not conditional with TEST_VERBOSE as found bug with wide display + $display("assoc_w=%p", assoc_w); + $writememh({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_writemem_w_h.mem"}, assoc_w); + end + else if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_sys_readmem_assoc_bad.out b/test_regress/t/t_sys_readmem_assoc_bad.out index 70ace013e..c3a6d245d 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.out +++ b/test_regress/t/t_sys_readmem_assoc_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_sys_readmem_assoc_bad.v:13:24: $readmemb address/key must be integral (IEEE 1800-2023 21.4.1) +%Error: t/t_sys_readmem_assoc_bad.v:13:22: $readmemb address/key must be integral (IEEE 1800-2023 21.4.1) : ... note: In instance 't' - 13 | $readmemb("not", assoc_bad_key); - | ^~~~~~~~~~~~~ + 13 | $readmemb("not", assoc_bad_key); + | ^~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_sys_readmem_assoc_bad.v:14:24: Unsupported: $readmemb array values must be integral +%Error-UNSUPPORTED: t/t_sys_readmem_assoc_bad.v:14:22: Unsupported: $readmemb array values must be integral : ... note: In instance 't' - 14 | $readmemb("not", assoc_bad_value); - | ^~~~~~~~~~~~~~~ + 14 | $readmemb("not", assoc_bad_value); + | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_sys_readmem_assoc_bad.v b/test_regress/t/t_sys_readmem_assoc_bad.v index ec692956e..958b9a0b4 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.v +++ b/test_regress/t/t_sys_readmem_assoc_bad.v @@ -6,13 +6,13 @@ module t; - reg [5:0] assoc_bad_key[real]; - real assoc_bad_value[int]; + reg [5:0] assoc_bad_key[real]; + real assoc_bad_value[int]; - initial begin - $readmemb("not", assoc_bad_key); - $readmemb("not", assoc_bad_value); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $readmemb("not", assoc_bad_key); + $readmemb("not", assoc_bad_value); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_bad_addr.v b/test_regress/t/t_sys_readmem_bad_addr.v index f2f5ddcd1..5a6754a6f 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.v +++ b/test_regress/t/t_sys_readmem_bad_addr.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg [175:0] hex [15:0]; + reg [175:0] hex[15:0]; - initial begin - $readmemh("t/t_sys_readmem_bad_addr.mem", hex); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $readmemh("t/t_sys_readmem_bad_addr.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_bad_addr2.v b/test_regress/t/t_sys_readmem_bad_addr2.v index c8ffd9b5d..f6c7a3cf3 100644 --- a/test_regress/t/t_sys_readmem_bad_addr2.v +++ b/test_regress/t/t_sys_readmem_bad_addr2.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg [175:0] hex [15:0]; + reg [175:0] hex[15:0]; - initial begin - $readmemh("t/t_sys_readmem_bad_addr2.mem", hex); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $readmemh("t/t_sys_readmem_bad_addr2.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_bad_digit.v b/test_regress/t/t_sys_readmem_bad_digit.v index ddab6c8af..a504397bb 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.v +++ b/test_regress/t/t_sys_readmem_bad_digit.v @@ -6,11 +6,11 @@ module t; - reg [175:0] hex [15:0]; + reg [175:0] hex[15:0]; - initial begin - $readmemb("t/t_sys_readmem_bad_digit.mem", hex); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $readmemb("t/t_sys_readmem_bad_digit.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_bad_end.v b/test_regress/t/t_sys_readmem_bad_end.v index 3f9de2a3d..c1e10318d 100644 --- a/test_regress/t/t_sys_readmem_bad_end.v +++ b/test_regress/t/t_sys_readmem_bad_end.v @@ -6,16 +6,16 @@ module t; - reg [175:0] hex [15:0]; + reg [175:0] hex[15:0]; - integer i; + integer i; - initial begin - // No warning as has addresses - $readmemh("t/t_sys_readmem_bad_end2.mem", hex, 0, 15); - // Warning as wrong end address - $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // No warning as has addresses + $readmemh("t/t_sys_readmem_bad_end2.mem", hex, 0, 15); + // Warning as wrong end address + $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_bad_notfound.v b/test_regress/t/t_sys_readmem_bad_notfound.v index ec6d990c9..f28729a91 100644 --- a/test_regress/t/t_sys_readmem_bad_notfound.v +++ b/test_regress/t/t_sys_readmem_bad_notfound.v @@ -6,11 +6,11 @@ module t; - reg [175:0] hex [15:0]; + reg [175:0] hex[15:0]; - initial begin - $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_readmem_eof.v b/test_regress/t/t_sys_readmem_eof.v index 0a6b604a1..fb229aed7 100644 --- a/test_regress/t/t_sys_readmem_eof.v +++ b/test_regress/t/t_sys_readmem_eof.v @@ -4,19 +4,21 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define STRINGIFY(x) `"x`" +// verilog_format: on module t; - reg [7:0] rom [4]; - initial begin - $readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom); - `checkh(rom[0], 8'h1); - `checkh(rom[1], 8'h10); - `checkh(rom[2], 8'h20); - `checkh(rom[3], 8'h30); - $write("*-* All Finished *-*\n"); - $finish; - end + reg [7:0] rom[4]; + initial begin + $readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom); + `checkh(rom[0], 8'h1); + `checkh(rom[1], 8'h10); + `checkh(rom[2], 8'h20); + `checkh(rom[3], 8'h30); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index 9e370f6af..cc2cadb17 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -6,95 +6,117 @@ module t; - // Note $sscanf already tested elsewhere + // Note $sscanf already tested elsewhere - reg [3:0] n; - reg [63:0] q; - reg [16*8:1] wide; + reg [3:0] n; + reg [63:0] q; + reg [16*8:1] wide; - reg [8:1] ochar; - reg [48*8:1] str; - reg [48*8:1] str2; - string str3; + reg [8:1] ochar; + reg [48*8:1] str; + reg [48*8:1] str2; + string str3; - reg [39:0] instruction_str [1:0]; + reg [39:0] instruction_str[1:0]; - real r; + real r; - initial begin - n = 4'b1100; - q = 64'h1234_5678_abcd_0123; - wide = "hello-there12345"; - $sformat(str, "n=%b q=%d w=%s", n, q, wide); -`ifdef TEST_VERBOSE $display("str=%0s",str); `endif - if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; + initial begin + n = 4'b1100; + q = 64'h1234_5678_abcd_0123; + wide = "hello-there12345"; + $sformat(str, "n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE + $display("str=%0s", str); +`endif + if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; - q = {q[62:0],1'b1}; - $swrite(str2, "n=%b q=%d w=%s", n, q, wide); -`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif - if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + q = {q[62:0], 1'b1}; + $swrite(str2, "n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE + $display("str2=%0s", str2); +`endif + if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; - str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); -`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif - if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE + $display("str3=%0s", str3); +`endif + if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; - $swrite(str2, "e=%e", r); - $swrite(str2, "e=%f", r); - $swrite(str2, "e=%g", r); + $swrite(str2, "e=%e", r); + $swrite(str2, "e=%f", r); + $swrite(str2, "e=%g", r); - str3 = "hello"; - $swrite(str2, {str3, str3}); -`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif - if (str2 !== "hellohello") $stop; + str3 = "hello"; + $swrite(str2, {str3, str3}); +`ifdef TEST_VERBOSE + $display("str2=%0s", str2); +`endif + if (str2 !== "hellohello") $stop; - r = 0.01; - $swrite(str2, "e=%e f=%f g=%g", r, r, r); -`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif - if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; + r = 0.01; + $swrite(str2, "e=%e f=%f g=%g", r, r, r); +`ifdef TEST_VERBOSE + $display("str2=%0s", str2); +`endif + if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; - $swrite(str2, "mod=%m"); -`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif - if (str2 !== "mod=top.t") $stop; + $swrite(str2, "mod=%m"); +`ifdef TEST_VERBOSE + $display("str2=%0s", str2); +`endif + if (str2 !== "mod=top.t") $stop; - $swrite(str2, "lib=%l"); -`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif - if (str2 !== "lib=work.t") $stop; + $swrite(str2, "lib=%l"); +`ifdef TEST_VERBOSE + $display("chkl %0s", str2); +`endif + if (str2 !== "lib=work.t") $stop; - str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable -`ifdef TEST_VERBOSE $display("chku %s", str3); `endif - if (str3 !== "u=dcba") $stop; + str3 = $sformatf("u=%u", {"a", "b", "c", "d"}); // Value selected so is printable +`ifdef TEST_VERBOSE + $display("chku %s", str3); +`endif + if (str3 !== "u=dcba") $stop; - str3 = $sformatf("v=%v", 4'b01xz); // Value selected so is printable -`ifdef TEST_VERBOSE $display("chkv %s", str3); `endif + str3 = $sformatf("v=%v", 4'b01xz); // Value selected so is printable +`ifdef TEST_VERBOSE + $display("chkv %s", str3); +`endif - str3 = $sformatf("z=%z", {"a","b","c","d"}); // Value selected so is printable -`ifdef TEST_VERBOSE $display("chkz %s", str3); `endif + str3 = $sformatf("z=%z", {"a", "b", "c", "d"}); // Value selected so is printable +`ifdef TEST_VERBOSE + $display("chkz %s", str3); +`endif - $sformat(ochar,"%s","c"); - if (ochar != "c") $stop; + $sformat(ochar, "%s", "c"); + if (ochar != "c") $stop; - $swrite(str2, 4'd12); - if (str2 != "12") $stop; - $swriteb(str2, 4'd12); - if (str2 != "1100") $stop; - $swriteh(str2, 4'd12); - if (str2 != "c") $stop; - $swriteo(str2, 4'd12); - if (str2 != "14") $stop; + $swrite(str2, 4'd12); + if (str2 != "12") $stop; + $swriteb(str2, 4'd12); + if (str2 != "1100") $stop; + $swriteh(str2, 4'd12); + if (str2 != "c") $stop; + $swriteo(str2, 4'd12); + if (str2 != "14") $stop; - str3 = "foo"; - $sformat(str3, "%s", str3); // $sformat twice so verilator does not - $sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo") -`ifdef TEST_VERBOSE $display("str3=%0s", str3); `endif - if (str3 != "foo") $stop; + str3 = "foo"; + $sformat(str3, "%s", str3); // $sformat twice so verilator does not + $sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo") +`ifdef TEST_VERBOSE + $display("str3=%0s", str3); +`endif + if (str3 != "foo") $stop; - $sformat(instruction_str[0], "%s", "Hello"); - $sformat(instruction_str[1], "%s", "World"); - if (instruction_str[0] != "Hello") $stop; - if (instruction_str[1] != "World") $stop; + $sformat(instruction_str[0], "%s", "Hello"); + $sformat(instruction_str[1], "%s", "World"); + if (instruction_str[0] != "Hello") $stop; + if (instruction_str[1] != "World") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_strobe.v b/test_regress/t/t_sys_strobe.v index 318e84aa3..868079d38 100644 --- a/test_regress/t/t_sys_strobe.v +++ b/test_regress/t/t_sys_strobe.v @@ -4,43 +4,40 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; - int cyc = 0; - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $strobe("[%0t] cyc=%0d", $time, cyc); - $strobe("[%0t] cyc=%0d also", $time, cyc); - end - else if (cyc == 17) begin - $strobeb(cyc, "b"); - end - else if (cyc == 18) begin - $strobeh(cyc, "h"); - end - else if (cyc == 19) begin - $strobeo(cyc, "o"); - end - else if (cyc == 22) begin - $strobe("[%0t] cyc=%0d new-strobe", $time, cyc); - end - else if (cyc == 24) begin - $monitoroff; - end - else if (cyc == 26) begin - $monitoron; - end - else if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $strobe("[%0t] cyc=%0d", $time, cyc); + $strobe("[%0t] cyc=%0d also", $time, cyc); + end + else if (cyc == 17) begin + $strobeb(cyc, "b"); + end + else if (cyc == 18) begin + $strobeh(cyc, "h"); + end + else if (cyc == 19) begin + $strobeo(cyc, "o"); + end + else if (cyc == 22) begin + $strobe("[%0t] cyc=%0d new-strobe", $time, cyc); + end + else if (cyc == 24) begin + $monitoroff; + end + else if (cyc == 26) begin + $monitoron; + end + else if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_sys_system.v b/test_regress/t/t_sys_system.v index 424ffd380..a15151943 100644 --- a/test_regress/t/t_sys_system.v +++ b/test_regress/t/t_sys_system.v @@ -6,34 +6,34 @@ module t; - integer i; - string s; + integer i; + string s; - initial begin + initial begin `ifndef VERILATOR - `ifndef VCS - `ifndef NC - $system(); // Legal per spec, but not supported everywhere and nonsensical - `endif - `endif -`endif - $system("ls"); // IData - $system("exit 0"); // QData - $system("echo hello"); // WDATA `ifndef VCS - i = $system("exit 0"); - if (i!==0) $stop; - i = $system("exit 10"); - if (i!==10) $stop; - i = $system("exit 20"); // Wide - if (i!==20) $stop; - s = "exit 10"; - i = $system(s); // String - if (i!==10) $stop; +`ifndef NC + $system(); // Legal per spec, but not supported everywhere and nonsensical +`endif +`endif +`endif + $system("ls"); // IData + $system("exit 0"); // QData + $system("echo hello"); // WDATA +`ifndef VCS + i = $system("exit 0"); + if (i !== 0) $stop; + i = $system("exit 10"); + if (i !== 10) $stop; + i = $system("exit 20"); // Wide + if (i !== 20) $stop; + s = "exit 10"; + i = $system(s); // String + if (i !== 10) $stop; `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v index 7be9b496b..b07dfc496 100644 --- a/test_regress/t/t_sys_time.v +++ b/test_regress/t/t_sys_time.v @@ -4,32 +4,30 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [63:0] time64; + reg [63:0] time64; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - end - else if (cyc<10) begin - end - else if (cyc<90) begin - time64 = $time; - if ($stime != time64[31:0]) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + end + else if (cyc < 10) begin + end + else if (cyc < 90) begin + time64 = $time; + if ($stime != time64[31:0]) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_tagged.out b/test_regress/t/t_tagged.out index 513aa3976..4b51273fe 100644 --- a/test_regress/t/t_tagged.out +++ b/test_regress/t/t_tagged.out @@ -1,69 +1,69 @@ -%Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions) - 10 | void m_invalid; - | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:10:5: Unsupported: void (for tagged unions) + 10 | void m_invalid; + | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_tagged.v:19:14: Unsupported: tagged union - 19 | u = tagged m_invalid; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:24:7: Unsupported: case matches (for tagged union) - 24 | case (u) matches - | ^~~~ -%Error-UNSUPPORTED: t/t_tagged.v:28:7: Unsupported: case matches (for tagged union) - 28 | case (u) matches - | ^~~~ -%Error-UNSUPPORTED: t/t_tagged.v:29:9: Unsupported: tagged union - 29 | tagged m_invalid: ; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:30:9: Unsupported: tagged union - 30 | tagged m_int: $stop; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:33:13: Unsupported: matches operator - 33 | if (u matches tagged m_invalid) ; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:33:21: Unsupported: tagged union - 33 | if (u matches tagged m_invalid) ; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:34:13: Unsupported: matches operator - 34 | if (u matches tagged m_int .n) $stop; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:34:21: Unsupported: tagged pattern - 34 | if (u matches tagged m_int .n) $stop; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:34:34: Unsupported: pattern variable - 34 | if (u matches tagged m_int .n) $stop; - | ^ -%Error-UNSUPPORTED: t/t_tagged.v:36:11: Unsupported: tagged union - 36 | u = tagged m_int (123); +%Error-UNSUPPORTED: t/t_tagged.v:19:11: Unsupported: tagged union + 19 | u = tagged m_invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:39:7: Unsupported: case matches (for tagged union) - 39 | case (u) matches - | ^~~~ -%Error-UNSUPPORTED: t/t_tagged.v:40:9: Unsupported: tagged union - 40 | tagged m_invalid: $stop; +%Error-UNSUPPORTED: t/t_tagged.v:24:5: Unsupported: case matches (for tagged union) + 24 | case (u) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:28:5: Unsupported: case matches (for tagged union) + 28 | case (u) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:29:7: Unsupported: tagged union + 29 | tagged m_invalid: ; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:30:7: Unsupported: tagged union + 30 | tagged m_int: $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:33:11: Unsupported: matches operator + 33 | if (u matches tagged m_invalid) ; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:33:19: Unsupported: tagged union + 33 | if (u matches tagged m_invalid) ; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:34:11: Unsupported: matches operator + 34 | if (u matches tagged m_int .n) $stop; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:34:19: Unsupported: tagged pattern + 34 | if (u matches tagged m_int .n) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:34:32: Unsupported: pattern variable + 34 | if (u matches tagged m_int .n) $stop; + | ^ +%Error-UNSUPPORTED: t/t_tagged.v:36:9: Unsupported: tagged union + 36 | u = tagged m_int (123); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:41:9: Unsupported: tagged pattern - 41 | tagged m_int .n: if (n !== 123) $stop; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:41:22: Unsupported: pattern variable - 41 | tagged m_int .n: if (n !== 123) $stop; - | ^ -%Error-UNSUPPORTED: t/t_tagged.v:44:13: Unsupported: matches operator - 44 | if (u matches tagged m_invalid) $stop; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:44:21: Unsupported: tagged union - 44 | if (u matches tagged m_invalid) $stop; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:45:13: Unsupported: matches operator - 45 | if (u matches tagged m_int .n) if (n != 123) $stop; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:45:21: Unsupported: tagged pattern - 45 | if (u matches tagged m_int .n) if (n != 123) $stop; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:45:34: Unsupported: pattern variable - 45 | if (u matches tagged m_int .n) if (n != 123) $stop; - | ^ -%Error: t/t_tagged.v:41:30: Can't find definition of variable: 'n' - 41 | tagged m_int .n: if (n !== 123) $stop; - | ^ +%Error-UNSUPPORTED: t/t_tagged.v:39:5: Unsupported: case matches (for tagged union) + 39 | case (u) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:40:7: Unsupported: tagged union + 40 | tagged m_invalid: $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:41:7: Unsupported: tagged pattern + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:41:20: Unsupported: pattern variable + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^ +%Error-UNSUPPORTED: t/t_tagged.v:44:11: Unsupported: matches operator + 44 | if (u matches tagged m_invalid) $stop; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:44:19: Unsupported: tagged union + 44 | if (u matches tagged m_invalid) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:45:11: Unsupported: matches operator + 45 | if (u matches tagged m_int .n) if (n != 123) $stop; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:45:19: Unsupported: tagged pattern + 45 | if (u matches tagged m_int .n) if (n != 123) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:45:32: Unsupported: pattern variable + 45 | if (u matches tagged m_int .n) if (n != 123) $stop; + | ^ +%Error: t/t_tagged.v:41:28: Can't find definition of variable: 'n' + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_tagged.v b/test_regress/t/t_tagged.v index 9dacfaa52..b8c08d865 100644 --- a/test_regress/t/t_tagged.v +++ b/test_regress/t/t_tagged.v @@ -6,46 +6,46 @@ module t; - typedef union tagged { - void m_invalid; - int m_int; - } u_t; + typedef union tagged { + void m_invalid; + int m_int; + } u_t; - u_t u; - string s; + u_t u; + string s; - initial begin - begin - u = tagged m_invalid; - s = $sformatf("%p", u); - $display("%s e.g. '{tagged m_invalid:void}", s); - end - - case (u) matches - default: ; - endcase - - case (u) matches - tagged m_invalid: ; - tagged m_int: $stop; - default: $stop; - endcase - if (u matches tagged m_invalid) ; - if (u matches tagged m_int .n) $stop; - - u = tagged m_int (123); + initial begin + begin + u = tagged m_invalid; s = $sformatf("%p", u); - $display("'%s e.g. '{tagged m_int:123}", s); - case (u) matches - tagged m_invalid: $stop; - tagged m_int .n: if (n !== 123) $stop; - default: $stop; - endcase - if (u matches tagged m_invalid) $stop; - if (u matches tagged m_int .n) if (n != 123) $stop; + $display("%s e.g. '{tagged m_invalid:void}", s); + end - $write("*-* All Finished *-*\n"); - $finish; - end + case (u) matches + default: ; + endcase + + case (u) matches + tagged m_invalid: ; + tagged m_int: $stop; + default: $stop; + endcase + if (u matches tagged m_invalid) ; + if (u matches tagged m_int .n) $stop; + + u = tagged m_int (123); + s = $sformatf("%p", u); + $display("'%s e.g. '{tagged m_int:123}", s); + case (u) matches + tagged m_invalid: $stop; + tagged m_int .n: if (n !== 123) $stop; + default: $stop; + endcase + if (u matches tagged m_invalid) $stop; + if (u matches tagged m_int .n) if (n != 123) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_tagged_case.out b/test_regress/t/t_tagged_case.out index 36008d067..e7965a85d 100644 --- a/test_regress/t/t_tagged_case.out +++ b/test_regress/t/t_tagged_case.out @@ -1,152 +1,152 @@ -%Error-UNSUPPORTED: t/t_tagged_case.v:27:5: Unsupported: void (for tagged unions) - 27 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:29:5: Unsupported: void (for tagged unions) + 29 | void Invalid; | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_tagged_case.v:33:5: Unsupported: void (for tagged unions) - 33 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:35:5: Unsupported: void (for tagged unions) + 35 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:42:5: Unsupported: void (for tagged unions) - 42 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:44:5: Unsupported: void (for tagged unions) + 44 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:63:5: Unsupported: void (for tagged unions) - 63 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:65:5: Unsupported: void (for tagged unions) + 65 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:69:5: Unsupported: void (for tagged unions) - 69 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:71:5: Unsupported: void (for tagged unions) + 71 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:78:5: Unsupported: void (for tagged unions) - 78 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:80:5: Unsupported: void (for tagged unions) + 80 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:85:5: Unsupported: void (for tagged unions) - 85 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:87:5: Unsupported: void (for tagged unions) + 87 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:91:5: Unsupported: void (for tagged unions) - 91 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:93:5: Unsupported: void (for tagged unions) + 93 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:100:5: Unsupported: void (for tagged unions) - 100 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:102:5: Unsupported: void (for tagged unions) + 102 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:124:9: Unsupported: tagged union - 124 | v = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_case.v:126:9: Unsupported: tagged union + 126 | v = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:126:5: Unsupported: case matches (for tagged union) - 126 | case (v) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:128:5: Unsupported: case matches (for tagged union) + 128 | case (v) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:127:7: Unsupported: tagged union - 127 | tagged Invalid : result = 1; +%Error-UNSUPPORTED: t/t_tagged_case.v:129:7: Unsupported: tagged union + 129 | tagged Invalid : result = 1; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:128:7: Unsupported: tagged pattern - 128 | tagged Valid .n : result = n; +%Error-UNSUPPORTED: t/t_tagged_case.v:130:7: Unsupported: tagged pattern + 130 | tagged Valid .n : result = n; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:128:20: Unsupported: pattern variable - 128 | tagged Valid .n : result = n; +%Error-UNSUPPORTED: t/t_tagged_case.v:130:20: Unsupported: pattern variable + 130 | tagged Valid .n : result = n; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:133:9: Unsupported: tagged union - 133 | v = tagged Valid (123); +%Error-UNSUPPORTED: t/t_tagged_case.v:135:9: Unsupported: tagged union + 135 | v = tagged Valid (123); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:135:5: Unsupported: case matches (for tagged union) - 135 | case (v) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:137:5: Unsupported: case matches (for tagged union) + 137 | case (v) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:136:7: Unsupported: tagged union - 136 | tagged Invalid : result = -1; +%Error-UNSUPPORTED: t/t_tagged_case.v:138:7: Unsupported: tagged union + 138 | tagged Invalid : result = -1; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:137:7: Unsupported: tagged pattern - 137 | tagged Valid .n : result = n; +%Error-UNSUPPORTED: t/t_tagged_case.v:139:7: Unsupported: tagged pattern + 139 | tagged Valid .n : result = n; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:137:20: Unsupported: pattern variable - 137 | tagged Valid .n : result = n; +%Error-UNSUPPORTED: t/t_tagged_case.v:139:20: Unsupported: pattern variable + 139 | tagged Valid .n : result = n; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:142:10: Unsupported: tagged union - 142 | wt = tagged Wide60 (60'hFEDCBA987654321); +%Error-UNSUPPORTED: t/t_tagged_case.v:144:10: Unsupported: tagged union + 144 | wt = tagged Wide60 (60'hFEDCBA987654321); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:144:5: Unsupported: case matches (for tagged union) - 144 | case (wt) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:146:5: Unsupported: case matches (for tagged union) + 146 | case (wt) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:145:7: Unsupported: tagged union - 145 | tagged Invalid : wide60_result = 0; +%Error-UNSUPPORTED: t/t_tagged_case.v:147:7: Unsupported: tagged union + 147 | tagged Invalid : wide60_result = 0; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:146:7: Unsupported: tagged pattern - 146 | tagged Wide60 .w : wide60_result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:148:7: Unsupported: tagged pattern + 148 | tagged Wide60 .w : wide60_result = w; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:146:21: Unsupported: pattern variable - 146 | tagged Wide60 .w : wide60_result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:148:21: Unsupported: pattern variable + 148 | tagged Wide60 .w : wide60_result = w; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:152:10: Unsupported: tagged union - 152 | wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456); +%Error-UNSUPPORTED: t/t_tagged_case.v:154:10: Unsupported: tagged union + 154 | wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:154:5: Unsupported: case matches (for tagged union) - 154 | case (wt) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:156:5: Unsupported: case matches (for tagged union) + 156 | case (wt) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:155:7: Unsupported: tagged union - 155 | tagged Invalid : wide90_result = 0; +%Error-UNSUPPORTED: t/t_tagged_case.v:157:7: Unsupported: tagged union + 157 | tagged Invalid : wide90_result = 0; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:156:7: Unsupported: tagged pattern - 156 | tagged Wide90 .w : wide90_result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:158:7: Unsupported: tagged pattern + 158 | tagged Wide90 .w : wide90_result = w; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:156:21: Unsupported: pattern variable - 156 | tagged Wide90 .w : wide90_result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:158:21: Unsupported: pattern variable + 158 | tagged Wide90 .w : wide90_result = w; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:162:10: Unsupported: tagged union - 162 | wt = tagged Byte8NonZeroLSB (8'hA5); +%Error-UNSUPPORTED: t/t_tagged_case.v:164:10: Unsupported: tagged union + 164 | wt = tagged Byte8NonZeroLSB (8'hA5); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:164:5: Unsupported: case matches (for tagged union) - 164 | case (wt) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:166:5: Unsupported: case matches (for tagged union) + 166 | case (wt) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:165:7: Unsupported: tagged pattern - 165 | tagged Byte8NonZeroLSB .b : result = b; +%Error-UNSUPPORTED: t/t_tagged_case.v:167:7: Unsupported: tagged pattern + 167 | tagged Byte8NonZeroLSB .b : result = b; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:165:30: Unsupported: pattern variable - 165 | tagged Byte8NonZeroLSB .b : result = b; +%Error-UNSUPPORTED: t/t_tagged_case.v:167:30: Unsupported: pattern variable + 167 | tagged Byte8NonZeroLSB .b : result = b; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:171:10: Unsupported: tagged union - 171 | wt = tagged Word32LittleEndian (32'hDEADBEEF); +%Error-UNSUPPORTED: t/t_tagged_case.v:173:10: Unsupported: tagged union + 173 | wt = tagged Word32LittleEndian (32'hDEADBEEF); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:173:5: Unsupported: case matches (for tagged union) - 173 | case (wt) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:175:5: Unsupported: case matches (for tagged union) + 175 | case (wt) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:174:7: Unsupported: tagged pattern - 174 | tagged Word32LittleEndian .w : result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:176:7: Unsupported: tagged pattern + 176 | tagged Word32LittleEndian .w : result = w; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:174:33: Unsupported: pattern variable - 174 | tagged Word32LittleEndian .w : result = w; +%Error-UNSUPPORTED: t/t_tagged_case.v:176:33: Unsupported: pattern variable + 176 | tagged Word32LittleEndian .w : result = w; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:180:10: Unsupported: tagged union - 180 | at = tagged Arr '{10, 20, 30, 40}; +%Error-UNSUPPORTED: t/t_tagged_case.v:182:10: Unsupported: tagged union + 182 | at = tagged Arr '{10, 20, 30, 40}; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:182:5: Unsupported: case matches (for tagged union) - 182 | case (at) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:184:5: Unsupported: case matches (for tagged union) + 184 | case (at) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:183:7: Unsupported: tagged union - 183 | tagged Invalid : result = -1; +%Error-UNSUPPORTED: t/t_tagged_case.v:185:7: Unsupported: tagged union + 185 | tagged Invalid : result = -1; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:184:7: Unsupported: tagged pattern - 184 | tagged Scalar .s : result = s; +%Error-UNSUPPORTED: t/t_tagged_case.v:186:7: Unsupported: tagged pattern + 186 | tagged Scalar .s : result = s; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:184:21: Unsupported: pattern variable - 184 | tagged Scalar .s : result = s; +%Error-UNSUPPORTED: t/t_tagged_case.v:186:21: Unsupported: pattern variable + 186 | tagged Scalar .s : result = s; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:185:7: Unsupported: tagged pattern - 185 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; +%Error-UNSUPPORTED: t/t_tagged_case.v:187:7: Unsupported: tagged pattern + 187 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:185:18: Unsupported: pattern variable - 185 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; +%Error-UNSUPPORTED: t/t_tagged_case.v:187:18: Unsupported: pattern variable + 187 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; | ^ -%Error-UNSUPPORTED: t/t_tagged_case.v:190:13: Unsupported: tagged union - 190 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); +%Error-UNSUPPORTED: t/t_tagged_case.v:192:13: Unsupported: tagged union + 192 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:190:25: Unsupported: tagged union - 190 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); +%Error-UNSUPPORTED: t/t_tagged_case.v:192:25: Unsupported: tagged union + 192 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:192:5: Unsupported: case matches (for tagged union) - 192 | case (instr) matches +%Error-UNSUPPORTED: t/t_tagged_case.v:194:5: Unsupported: case matches (for tagged union) + 194 | case (instr) matches | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:193:7: Unsupported: tagged pattern - 193 | tagged Add .* : result = -1; +%Error-UNSUPPORTED: t/t_tagged_case.v:195:7: Unsupported: tagged pattern + 195 | tagged Add .* : result = -1; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_case.v:193:18: Unsupported: pattern wildcard - 193 | tagged Add .* : result = -1; +%Error-UNSUPPORTED: t/t_tagged_case.v:195:18: Unsupported: pattern wildcard + 195 | tagged Add .* : result = -1; | ^~ -%Error-UNSUPPORTED: t/t_tagged_case.v:194:7: Unsupported: tagged union - 194 | tagged Jmp (tagged JmpU .a) : result = a; +%Error-UNSUPPORTED: t/t_tagged_case.v:196:7: Unsupported: tagged union + 196 | tagged Jmp (tagged JmpU .a) : result = a; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_tagged_case.v b/test_regress/t/t_tagged_case.v index 37f4ff28f..a2ebf02fc 100644 --- a/test_regress/t/t_tagged_case.v +++ b/test_regress/t/t_tagged_case.v @@ -17,8 +17,10 @@ class TestClass; endfunction endclass +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_tagged_if.out b/test_regress/t/t_tagged_if.out index 42c5ebee7..31b7cc0bb 100644 --- a/test_regress/t/t_tagged_if.out +++ b/test_regress/t/t_tagged_if.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_tagged_if.v:216:37: Unsupported: &&& expression - 216 | if (instr matches tagged Jmp .j &&& +%Error-UNSUPPORTED: t/t_tagged_if.v:218:37: Unsupported: &&& expression + 218 | if (instr matches tagged Jmp .j &&& | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_tagged_if.v:226:35: Unsupported: &&& expression - 226 | if (v matches tagged Valid .n &&& (n > 50)) +%Error-UNSUPPORTED: t/t_tagged_if.v:228:35: Unsupported: &&& expression + 228 | if (v matches tagged Valid .n &&& (n > 50)) | ^~~ -%Error-UNSUPPORTED: t/t_tagged_if.v:235:35: Unsupported: &&& expression - 235 | if (v matches tagged Valid .n &&& (n > 50)) +%Error-UNSUPPORTED: t/t_tagged_if.v:237:35: Unsupported: &&& expression + 237 | if (v matches tagged Valid .n &&& (n > 50)) | ^~~ -%Error-UNSUPPORTED: t/t_tagged_if.v:264:37: Unsupported: &&& expression - 264 | if (instr matches tagged Jmp .j &&& +%Error-UNSUPPORTED: t/t_tagged_if.v:266:37: Unsupported: &&& expression + 266 | if (instr matches tagged Jmp .j &&& | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_tagged_if.v b/test_regress/t/t_tagged_if.v index b3c816756..46be66135 100644 --- a/test_regress/t/t_tagged_if.v +++ b/test_regress/t/t_tagged_if.v @@ -17,8 +17,10 @@ class TestClass; endfunction endclass +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_tagged_union.out b/test_regress/t/t_tagged_union.out index 843b15977..ab08889dc 100644 --- a/test_regress/t/t_tagged_union.out +++ b/test_regress/t/t_tagged_union.out @@ -1,152 +1,152 @@ -%Error-UNSUPPORTED: t/t_tagged_union.v:27:5: Unsupported: void (for tagged unions) - 27 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:29:5: Unsupported: void (for tagged unions) + 29 | void Invalid; | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_tagged_union.v:34:5: Unsupported: void (for tagged unions) - 34 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:36:5: Unsupported: void (for tagged unions) + 36 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:55:5: Unsupported: void (for tagged unions) - 55 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:57:5: Unsupported: void (for tagged unions) + 57 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:77:5: Unsupported: void (for tagged unions) - 77 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:79:5: Unsupported: void (for tagged unions) + 79 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:83:5: Unsupported: void (for tagged unions) - 83 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:85:5: Unsupported: void (for tagged unions) + 85 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:92:5: Unsupported: void (for tagged unions) - 92 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:94:5: Unsupported: void (for tagged unions) + 94 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:99:5: Unsupported: void (for tagged unions) - 99 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:101:5: Unsupported: void (for tagged unions) + 101 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:105:5: Unsupported: void (for tagged unions) - 105 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:107:5: Unsupported: void (for tagged unions) + 107 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:114:5: Unsupported: void (for tagged unions) - 114 | void Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:116:5: Unsupported: void (for tagged unions) + 116 | void Invalid; | ^~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:135:11: Unsupported: tagged union - 135 | vi1 = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:137:11: Unsupported: tagged union + 137 | vi1 = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:136:11: Unsupported: tagged union - 136 | vi2 = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:138:11: Unsupported: tagged union + 138 | vi2 = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:139:11: Unsupported: tagged union - 139 | vi1 = tagged Valid (42); +%Error-UNSUPPORTED: t/t_tagged_union.v:141:11: Unsupported: tagged union + 141 | vi1 = tagged Valid (42); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:142:11: Unsupported: tagged union - 142 | vi2 = tagged Valid (23 + 34); +%Error-UNSUPPORTED: t/t_tagged_union.v:144:11: Unsupported: tagged union + 144 | vi2 = tagged Valid (23 + 34); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:146:10: Unsupported: tagged union - 146 | mt = tagged Invalid; - | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged_union.v:148:10: Unsupported: tagged union - 148 | mt = tagged IntVal (32'h12345678); + 148 | mt = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:151:10: Unsupported: tagged union - 151 | mt = tagged ShortVal (16'hABCD); +%Error-UNSUPPORTED: t/t_tagged_union.v:150:10: Unsupported: tagged union + 150 | mt = tagged IntVal (32'h12345678); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:154:10: Unsupported: tagged union - 154 | mt = tagged ByteVal (8'h5A); +%Error-UNSUPPORTED: t/t_tagged_union.v:153:10: Unsupported: tagged union + 153 | mt = tagged ShortVal (16'hABCD); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:157:10: Unsupported: tagged union - 157 | mt = tagged BitVal (1'b1); +%Error-UNSUPPORTED: t/t_tagged_union.v:156:10: Unsupported: tagged union + 156 | mt = tagged ByteVal (8'h5A); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:161:10: Unsupported: tagged union - 161 | mt = tagged Byte8NonZeroLSB (8'hA5); +%Error-UNSUPPORTED: t/t_tagged_union.v:159:10: Unsupported: tagged union + 159 | mt = tagged BitVal (1'b1); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:164:10: Unsupported: tagged union - 164 | mt = tagged Word16NonZeroLSB (16'h1234); +%Error-UNSUPPORTED: t/t_tagged_union.v:163:10: Unsupported: tagged union + 163 | mt = tagged Byte8NonZeroLSB (8'hA5); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:168:10: Unsupported: tagged union - 168 | mt = tagged Word32LittleEndian (32'hDEADBEEF); +%Error-UNSUPPORTED: t/t_tagged_union.v:166:10: Unsupported: tagged union + 166 | mt = tagged Word16NonZeroLSB (16'h1234); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:171:10: Unsupported: tagged union - 171 | mt = tagged Word16LittleEndian (16'hCAFE); +%Error-UNSUPPORTED: t/t_tagged_union.v:170:10: Unsupported: tagged union + 170 | mt = tagged Word32LittleEndian (32'hDEADBEEF); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:175:10: Unsupported: tagged union - 175 | mt = tagged Wide60 (60'hFEDCBA987654321); +%Error-UNSUPPORTED: t/t_tagged_union.v:173:10: Unsupported: tagged union + 173 | mt = tagged Word16LittleEndian (16'hCAFE); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:178:10: Unsupported: tagged union - 178 | mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF); +%Error-UNSUPPORTED: t/t_tagged_union.v:177:10: Unsupported: tagged union + 177 | mt = tagged Wide60 (60'hFEDCBA987654321); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:181:10: Unsupported: tagged union - 181 | mt = tagged Wide60LittleEndian (60'hABCDEF012345678); +%Error-UNSUPPORTED: t/t_tagged_union.v:180:10: Unsupported: tagged union + 180 | mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:185:10: Unsupported: tagged union - 185 | mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF); +%Error-UNSUPPORTED: t/t_tagged_union.v:183:10: Unsupported: tagged union + 183 | mt = tagged Wide60LittleEndian (60'hABCDEF012345678); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:188:10: Unsupported: tagged union - 188 | mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456); +%Error-UNSUPPORTED: t/t_tagged_union.v:187:10: Unsupported: tagged union + 187 | mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:191:10: Unsupported: tagged union - 191 | mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333); +%Error-UNSUPPORTED: t/t_tagged_union.v:190:10: Unsupported: tagged union + 190 | mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:195:10: Unsupported: tagged union - 195 | at = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:193:10: Unsupported: tagged union + 193 | mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333); | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged_union.v:197:10: Unsupported: tagged union - 197 | at = tagged Scalar (999); + 197 | at = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:200:10: Unsupported: tagged union - 200 | at = tagged UnpackedArr '{100, 200, 300, 400}; +%Error-UNSUPPORTED: t/t_tagged_union.v:199:10: Unsupported: tagged union + 199 | at = tagged Scalar (999); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:206:10: Unsupported: tagged union - 206 | at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}}; +%Error-UNSUPPORTED: t/t_tagged_union.v:202:10: Unsupported: tagged union + 202 | at = tagged UnpackedArr '{100, 200, 300, 400}; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:215:13: Unsupported: tagged union - 215 | instr = tagged Add '{5'd1, 5'd2, 5'd3}; +%Error-UNSUPPORTED: t/t_tagged_union.v:208:10: Unsupported: tagged union + 208 | at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:217:13: Unsupported: tagged union + 217 | instr = tagged Add '{5'd1, 5'd2, 5'd3}; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:221:13: Unsupported: tagged union - 221 | instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5}; +%Error-UNSUPPORTED: t/t_tagged_union.v:223:13: Unsupported: tagged union + 223 | instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5}; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:227:13: Unsupported: tagged union - 227 | instr = tagged Jmp (tagged JmpU 10'd512); +%Error-UNSUPPORTED: t/t_tagged_union.v:229:13: Unsupported: tagged union + 229 | instr = tagged Jmp (tagged JmpU 10'd512); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:227:25: Unsupported: tagged union - 227 | instr = tagged Jmp (tagged JmpU 10'd512); +%Error-UNSUPPORTED: t/t_tagged_union.v:229:25: Unsupported: tagged union + 229 | instr = tagged Jmp (tagged JmpU 10'd512); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:231:13: Unsupported: tagged union - 231 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); +%Error-UNSUPPORTED: t/t_tagged_union.v:233:13: Unsupported: tagged union + 233 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:231:25: Unsupported: tagged union - 231 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); +%Error-UNSUPPORTED: t/t_tagged_union.v:233:25: Unsupported: tagged union + 233 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:236:13: Unsupported: tagged union - 236 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); +%Error-UNSUPPORTED: t/t_tagged_union.v:238:13: Unsupported: tagged union + 238 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:236:25: Unsupported: tagged union - 236 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); +%Error-UNSUPPORTED: t/t_tagged_union.v:238:25: Unsupported: tagged union + 238 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:241:11: Unsupported: tagged union - 241 | cht = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:243:11: Unsupported: tagged union + 243 | cht = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:242:11: Unsupported: tagged union - 242 | cht = tagged Handle (null); +%Error-UNSUPPORTED: t/t_tagged_union.v:244:11: Unsupported: tagged union + 244 | cht = tagged Handle (null); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:246:11: Unsupported: tagged union - 246 | clt = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:248:11: Unsupported: tagged union + 248 | clt = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:247:11: Unsupported: tagged union - 247 | clt = tagged Obj (obj); +%Error-UNSUPPORTED: t/t_tagged_union.v:249:11: Unsupported: tagged union + 249 | clt = tagged Obj (obj); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:251:10: Unsupported: tagged union - 251 | rt = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:253:10: Unsupported: tagged union + 253 | rt = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:252:10: Unsupported: tagged union - 252 | rt = tagged RealVal (3.14159); +%Error-UNSUPPORTED: t/t_tagged_union.v:254:10: Unsupported: tagged union + 254 | rt = tagged RealVal (3.14159); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:256:10: Unsupported: tagged union - 256 | rt = tagged ShortRealVal (2.5); +%Error-UNSUPPORTED: t/t_tagged_union.v:258:10: Unsupported: tagged union + 258 | rt = tagged ShortRealVal (2.5); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:260:10: Unsupported: tagged union - 260 | st = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:262:10: Unsupported: tagged union + 262 | st = tagged Invalid; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:261:10: Unsupported: tagged union - 261 | st = tagged StrVal ("hello"); +%Error-UNSUPPORTED: t/t_tagged_union.v:263:10: Unsupported: tagged union + 263 | st = tagged StrVal ("hello"); | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged_union.v:265:10: Unsupported: tagged union - 265 | et = tagged Invalid; +%Error-UNSUPPORTED: t/t_tagged_union.v:267:10: Unsupported: tagged union + 267 | et = tagged Invalid; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_tagged_union.v b/test_regress/t/t_tagged_union.v index b207c5b88..59642f503 100644 --- a/test_regress/t/t_tagged_union.v +++ b/test_regress/t/t_tagged_union.v @@ -17,8 +17,10 @@ class TestClass; endfunction endclass +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_threads_counter.v b/test_regress/t/t_threads_counter.v index c54808c4b..91c53ced8 100644 --- a/test_regress/t/t_threads_counter.v +++ b/test_regress/t/t_threads_counter.v @@ -4,22 +4,19 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; - int cyc; - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc!=0) begin - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc != 0) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_threads_crazy.v b/test_regress/t/t_threads_crazy.v index c54808c4b..91c53ced8 100644 --- a/test_regress/t/t_threads_crazy.v +++ b/test_regress/t/t_threads_crazy.v @@ -4,22 +4,19 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; - int cyc; - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc!=0) begin - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc != 0) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_time.v b/test_regress/t/t_time.v index 02cb20e08..3b108a8be 100644 --- a/test_regress/t/t_time.v +++ b/test_regress/t/t_time.v @@ -11,8 +11,10 @@ ** For 32ns $time should return 3 **/ +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; timeunit 10ns; diff --git a/test_regress/t/t_time_literals.v b/test_regress/t/t_time_literals.v index f533ec552..525003cc9 100644 --- a/test_regress/t/t_time_literals.v +++ b/test_regress/t/t_time_literals.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on `timescale 1ns/1ps diff --git a/test_regress/t/t_time_passed.v b/test_regress/t/t_time_passed.v index 45a8f5096..9923cd8ec 100644 --- a/test_regress/t/t_time_passed.v +++ b/test_regress/t/t_time_passed.v @@ -5,11 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps -module t ( /*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); integer cyc = 0; diff --git a/test_regress/t/t_timescale_parse.v b/test_regress/t/t_timescale_parse.v index d6ae573b5..3d7a40806 100644 --- a/test_regress/t/t_timescale_parse.v +++ b/test_regress/t/t_timescale_parse.v @@ -5,6 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 //verilator lint_off REALCVT +// verilog_format: off `define testmod(modname) \ module modname; \ diff --git a/test_regress/t/t_timing_always.v b/test_regress/t/t_timing_always.v index 5f670b70e..c002c2b3d 100644 --- a/test_regress/t/t_timing_always.v +++ b/test_regress/t/t_timing_always.v @@ -4,40 +4,42 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif +// verilog_format: on module t; - bit clk = 0; - always #3 clk = ~clk; + bit clk = 0; + always #3 clk = ~clk; - bit flag_a; - bit flag_b; - always @(posedge clk) - begin - `WRITE_VERBOSE(("[%0t] b <= 0\n", $time)); - flag_b <= 1'b0; - #2 - `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); - flag_a <= 1'b1; - #2 - `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); - flag_b <= 1'b1; - end - always @(flag_a) if ($time > 0) - begin - #1 - `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); - if (flag_b !== 1'b0) $stop; - #2 - `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); - if (flag_b !== 1'b1) $stop; - #10 - $write("*-* All Finished *-*\n"); - $finish; - end - initial #20 $stop; // timeout + bit flag_a; + bit flag_b; + always @(posedge clk) + begin + `WRITE_VERBOSE(("[%0t] b <= 0\n", $time)); + flag_b <= 1'b0; + #2 + `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); + flag_a <= 1'b1; + #2 + `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); + flag_b <= 1'b1; + end + always @(flag_a) if ($time > 0) + begin + #1 + `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); + if (flag_b !== 1'b0) $stop; + #2 + `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); + if (flag_b !== 1'b1) $stop; + #10 + $write("*-* All Finished *-*\n"); + $finish; + end + initial #20 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_class.v b/test_regress/t/t_timing_class.v index 4029ddd36..561e12a98 100644 --- a/test_regress/t/t_timing_class.v +++ b/test_regress/t/t_timing_class.v @@ -4,151 +4,154 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif +// verilog_format: on class BaseClass; - virtual task sleep; - endtask + virtual task sleep; + endtask - virtual task await; - endtask + virtual task await; + endtask endclass module t; - // ============================================= - // EVENTS - class EventClass extends BaseClass; - event e; - int trig_count; + // ============================================= + // EVENTS + class EventClass extends BaseClass; + event e; + int trig_count; - function new; - trig_count = 0; - endfunction + function new; + trig_count = 0; + endfunction - task inc_trig_count; - trig_count++; - endtask; + task inc_trig_count; + trig_count++; + endtask + ; - task sleep; - @e inc_trig_count; - `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); - endtask + task sleep; + @e inc_trig_count; + `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); + endtask - task wake; - ->e; - endtask - endclass + task wake; + ->e; + endtask + endclass - class WaitClass extends BaseClass; - int a; - int b; - logic ok; + class WaitClass extends BaseClass; + int a; + int b; + logic ok; - function new; - a = 0; - b = 0; - ok = 0; - endfunction + function new; + a = 0; + b = 0; + ok = 0; + endfunction - task await; - wait(a == 4 && b > 16) if (a != 4 || b <= 16) $stop; - ok = 1; - `WRITE_VERBOSE(("Condition in object met at time %0t!\n", $time)); - endtask - endclass + task await; + wait (a == 4 && b > 16) if (a != 4 || b <= 16) $stop; + ok = 1; + `WRITE_VERBOSE(("Condition in object met at time %0t!\n", $time)); + endtask + endclass - class LocalWaitClass extends BaseClass; - logic ok; + class LocalWaitClass extends BaseClass; + logic ok; - function new; - ok = 0; - endfunction + function new; + ok = 0; + endfunction - task await; - int a = 0; - int b = 100; - fork - wait(a == 42 || b != 100) if (a != 42 && b == 100) $stop; - #10 a = 42; - join - ok = 1; - `WRITE_VERBOSE(("Condition with local variables met at time %0t!\n", $time)); - endtask - endclass + task await; + int a = 0; + int b = 100; + fork + wait (a == 42 || b != 100) if (a != 42 && b == 100) $stop; + #10 a = 42; + join + ok = 1; + `WRITE_VERBOSE(("Condition with local variables met at time %0t!\n", $time)); + endtask + endclass - class ClkClass; - logic clk; - int count; + class ClkClass; + logic clk; + int count; - function new; - clk = 0; - count = 0; - endfunction + function new; + clk = 0; + count = 0; + endfunction - task flip; - clk = ~clk; - endtask; + task flip; + clk = ~clk; + endtask + ; - task count_5; - @(posedge clk) count++; - @(posedge clk) count++; - @(posedge clk) count++; - @(posedge clk) count++; - @(posedge clk) count++; - endtask - endclass + task count_5; + @(posedge clk) count++; + @(posedge clk) count++; + @(posedge clk) count++; + @(posedge clk) count++; + @(posedge clk) count++; + endtask + endclass - EventClass ec = new; - WaitClass wc = new; - LocalWaitClass lc = new; - ClkClass cc = new; + EventClass ec = new; + WaitClass wc = new; + LocalWaitClass lc = new; + ClkClass cc = new; - initial begin - @ec.e; - ec.sleep; - if (wc.ok) $stop; - wc.await; - if (lc.ok) $stop; - lc.await; - end + initial begin + @ec.e; + ec.sleep; + if (wc.ok) $stop; + wc.await; + if (lc.ok) $stop; + lc.await; + end - initial #20 ec.wake; - initial #40 ->ec.e; - initial begin - wc.a = #50 4; - wc.b = #10 32; - end + initial #20 ec.wake; + initial #40->ec.e; + initial begin + wc.a = #50 4; + wc.b = #10 32; + end - always @ec.e begin - ec.inc_trig_count; - `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); - end + always @ec.e begin + ec.inc_trig_count; + `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); + end - always #5 cc.flip; + always #5 cc.flip; - initial cc.count_5; + initial cc.count_5; - initial begin - #80 - if (cc.count != 5) $stop; - if (ec.trig_count != 3) $stop; - if (!wc.ok) $stop; - if (!lc.ok) $stop; - end + initial begin + #80 if (cc.count != 5) $stop; + if (ec.trig_count != 3) $stop; + if (!wc.ok) $stop; + if (!lc.ok) $stop; + end - // ============================================= - // DELAYS - virtual class DelayClass; - pure virtual task do_delay; - pure virtual task do_sth_else; - endclass + // ============================================= + // DELAYS + virtual class DelayClass; + pure virtual task do_delay; + pure virtual task do_sth_else; + endclass - `ifdef TEST_VERBOSE - `define DELAY_CLASS(dt) \ +`ifdef TEST_VERBOSE + `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ $write("Starting a #%0d delay\n", dt); \ @@ -159,8 +162,8 @@ module t; $write("Task with no delay (in Delay%0d)\n", dt); \ endtask \ endclass - `else - `define DELAY_CLASS(dt) \ +`else + `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ #dt; \ @@ -168,108 +171,114 @@ module t; virtual task do_sth_else; \ endtask \ endclass - `endif +`endif - `DELAY_CLASS(10); - `DELAY_CLASS(20); - `DELAY_CLASS(40); + `DELAY_CLASS(10); + `DELAY_CLASS(20); + `DELAY_CLASS(40); - class NoDelay extends DelayClass; - virtual task do_delay; - `WRITE_VERBOSE(("Task with no delay\n")); - endtask - virtual task do_sth_else; - `WRITE_VERBOSE(("Task with no delay (in NoDelay)\n")); - endtask - endclass + class NoDelay extends DelayClass; + virtual task do_delay; + `WRITE_VERBOSE(("Task with no delay\n")); + endtask + virtual task do_sth_else; + `WRITE_VERBOSE(("Task with no delay (in NoDelay)\n")); + endtask + endclass - class AssignDelayClass; - logic x; - logic y; - task do_assign; - y = #10 x; - `WRITE_VERBOSE(("Did assignment with delay\n")); - endtask - endclass + class AssignDelayClass; + logic x; + logic y; + task do_assign; + y = #10 x; + `WRITE_VERBOSE(("Did assignment with delay\n")); + endtask + endclass - initial begin - static DelayClass dc; - static Delay10 d10 = new; - static Delay20 d20 = new; - static Delay40 d40 = new; - static NoDelay dNo = new; - static AssignDelayClass dAsgn = new; - `WRITE_VERBOSE(("I'm at time %0t\n", $time)); - dc = d10; - dc.do_delay; - dc.do_sth_else; - `WRITE_VERBOSE(("I'm at time %0t\n", $time)); - if ($time != 10) $stop; - dc = d20; - dc.do_delay; - dc.do_sth_else; - `WRITE_VERBOSE(("I'm at time %0t\n", $time)); - if ($time != 30) $stop; - dc = d40; - dc.do_delay; - dc.do_sth_else; - `WRITE_VERBOSE(("I'm at time %0t\n", $time)); - if ($time != 70) $stop; - dc = dNo; - dc.do_delay; - dc.do_sth_else; - `WRITE_VERBOSE(("I'm at time %0t\n", $time)); - dAsgn.x = 1; - dAsgn.y = 0; - fork #5 dAsgn.x = 0; join_none - dAsgn.do_assign; - if ($time != 80) $stop; - if (dAsgn.y != 1) $stop; - // Test if the object is deleted before do_assign finishes: - fork dAsgn.do_assign; join_none - #5 dAsgn = null; - #15 $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + static DelayClass dc; + static Delay10 d10 = new; + static Delay20 d20 = new; + static Delay40 d40 = new; + static NoDelay dNo = new; + static AssignDelayClass dAsgn = new; + `WRITE_VERBOSE(("I'm at time %0t\n", $time)); + dc = d10; + dc.do_delay; + dc.do_sth_else; + `WRITE_VERBOSE(("I'm at time %0t\n", $time)); + if ($time != 10) $stop; + dc = d20; + dc.do_delay; + dc.do_sth_else; + `WRITE_VERBOSE(("I'm at time %0t\n", $time)); + if ($time != 30) $stop; + dc = d40; + dc.do_delay; + dc.do_sth_else; + `WRITE_VERBOSE(("I'm at time %0t\n", $time)); + if ($time != 70) $stop; + dc = dNo; + dc.do_delay; + dc.do_sth_else; + `WRITE_VERBOSE(("I'm at time %0t\n", $time)); + dAsgn.x = 1; + dAsgn.y = 0; + fork + #5 dAsgn.x = 0; + join_none + dAsgn.do_assign; + if ($time != 80) $stop; + if (dAsgn.y != 1) $stop; + // Test if the object is deleted before do_assign finishes: + fork + dAsgn.do_assign; + join_none + #5 dAsgn = null; + #15 $write("*-* All Finished *-*\n"); + $finish; + end - // ============================================= - // FORKS - class ForkDelayClass; - task do_delay; #40; endtask - endclass + // ============================================= + // FORKS + class ForkDelayClass; + task do_delay; + #40; + endtask + endclass - class ForkClass; - int done = 0; - task do_fork(); - ForkDelayClass d; - fork - begin - #10 done++; - `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); - end - fork - begin - #20 done++; - `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); - d = new; - end - begin - #30 d.do_delay; - done++; - `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); - end - join - join + class ForkClass; + int done = 0; + task do_fork(); + ForkDelayClass d; + fork + begin + #10 done++; + `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); + end + fork + begin + #20 done++; + `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); + d = new; + end + begin + #30 d.do_delay; done++; - `WRITE_VERBOSE(("All forked processes ended at time %0t\n", $time)); - endtask - endclass + `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); + end + join + join + done++; + `WRITE_VERBOSE(("All forked processes ended at time %0t\n", $time)); + endtask + endclass - initial begin - automatic ForkClass fc = new; - fc.do_fork; - if (fc.done != 4 || $time != 70) $stop; - end + initial begin + automatic ForkClass fc = new; + fc.do_fork; + if (fc.done != 4 || $time != 70) $stop; + end - initial #101 $stop; // timeout + initial #101 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_clkgen1.v b/test_regress/t/t_timing_clkgen1.v index c0e12e5eb..961522c93 100644 --- a/test_regress/t/t_timing_clkgen1.v +++ b/test_regress/t/t_timing_clkgen1.v @@ -5,37 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module clkgen(output bit clk); - initial begin - #(8.0:5:3) clk = 1; // Middle is default - forever begin - #5 clk = ~clk; - end - end + initial begin + #(8.0:5:3) clk = 1; // Middle is default + forever begin + #5 clk = ~clk; + end + end endmodule module t; - wire logic clk; + wire logic clk; - clkgen clkgen (.clk); + clkgen clkgen (.clk); - int cyc; - always @ (posedge clk) begin - cyc <= cyc + 1; + int cyc; + always @ (posedge clk) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $display("[%0t] cyc=%0d", $time, cyc); + $display("[%0t] cyc=%0d", $time, cyc); `endif - if (cyc == 0) begin - if ($time != 5) $stop; - end - else if (cyc == 1) begin - if ($time != 15) $stop; - end - else if (cyc == 2) begin - if ($time != 25) $stop; - end - else if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 0) begin + if ($time != 5) $stop; + end + else if (cyc == 1) begin + if ($time != 15) $stop; + end + else if (cyc == 2) begin + if ($time != 25) $stop; + end + else if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_timing_clkgen2.v b/test_regress/t/t_timing_clkgen2.v index 2b9eec094..df094bad7 100644 --- a/test_regress/t/t_timing_clkgen2.v +++ b/test_regress/t/t_timing_clkgen2.v @@ -4,33 +4,37 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif +// verilog_format: on module t; - logic clk = 0; - logic clk_inv; - int cnt1 = 0; - int cnt2 = 0; + logic clk = 0; + logic clk_inv; + int cnt1 = 0; + int cnt2 = 0; - always #4 clk = ~clk; - always @(posedge clk) begin - cnt1 <= cnt1 + 1; - `WRITE_VERBOSE(("[%0t] clk (%b)\n", $time, clk)); - end + always #4 clk = ~clk; + always @(posedge clk) begin + cnt1 <= cnt1 + 1; + `WRITE_VERBOSE(("[%0t] clk (%b)\n", $time, clk)); + end - assign #2 clk_inv = ~clk; - initial forever begin - @(posedge clk_inv) cnt2++; - `WRITE_VERBOSE(("[%0t] clk_inv (%b)\n", $time, clk_inv)); - end + assign #2 clk_inv = ~clk; + initial + forever begin + @(posedge clk_inv) cnt2++; + `WRITE_VERBOSE(("[%0t] clk_inv (%b)\n", $time, clk_inv)); + end - initial #81 begin - if (cnt1 != 10 && cnt2 != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial + #81 begin + if (cnt1 != 10 && cnt2 != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_clkgen3.v b/test_regress/t/t_timing_clkgen3.v index 2d6113506..314a81cd6 100644 --- a/test_regress/t/t_timing_clkgen3.v +++ b/test_regress/t/t_timing_clkgen3.v @@ -6,41 +6,43 @@ `timescale 10ns / 1ns +// verilog_format: off `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif +// verilog_format: on module t; - logic clk = 0; - logic clk_copy; - int cyc = 0; - int cnt1 = 0; - int cnt2 = 0; + logic clk = 0; + logic clk_copy; + int cyc = 0; + int cnt1 = 0; + int cnt2 = 0; - initial forever #1 clk = ~clk; + initial forever #1 clk = ~clk; - always @(negedge clk) begin - #0.75 cnt1++; - `WRITE_VERBOSE(("[%0t] NEG clk (%b)\n", $time, clk)); - end + always @(negedge clk) begin + #0.75 cnt1++; + `WRITE_VERBOSE(("[%0t] NEG clk (%b)\n", $time, clk)); + end - always @(posedge clk) begin - cyc <= cyc + 1; - #0.5 `WRITE_VERBOSE(("[%0t] POS clk (%b)\n", $time, clk)); - if (cyc == 5) begin - if (cnt1 != 4 && cnt2 != 9) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + #0.5 `WRITE_VERBOSE(("[%0t] POS clk (%b)\n", $time, clk)); + if (cyc == 5) begin + if (cnt1 != 4 && cnt2 != 9) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - assign clk_copy = clk; - always @(posedge clk_copy or negedge clk_copy) begin - #0.25 cnt2++; - `WRITE_VERBOSE(("[%0t] POS/NEG clk_copy (%b)\n", $time, clk_copy)); - end + assign clk_copy = clk; + always @(posedge clk_copy or negedge clk_copy) begin + #0.25 cnt2++; + `WRITE_VERBOSE(("[%0t] POS/NEG clk_copy (%b)\n", $time, clk_copy)); + end - initial #100 $stop; // timeout + initial #100 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_clkgen_unsup.out b/test_regress/t/t_timing_clkgen_unsup.out index 8ee56209f..7e751d249 100644 --- a/test_regress/t/t_timing_clkgen_unsup.out +++ b/test_regress/t/t_timing_clkgen_unsup.out @@ -1,6 +1,6 @@ -%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:9:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay - 9 | #(8.0:5:3) clk = 1; - | ^ +%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:9:11: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay + 9 | #(8.0:5:3) clk = 1; + | ^ ... For warning description see https://verilator.org/warn/MINTYPMAXDLY?v=latest ... Use "/* verilator lint_off MINTYPMAXDLY */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out index 3c603fba5..30a33788b 100644 --- a/test_regress/t/t_timing_debug1.out +++ b/test_regress/t/t_timing_debug1.out @@ -136,7 +136,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -252,7 +252,7 @@ -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -350,7 +350,7 @@ -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -411,7 +411,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -520,7 +520,7 @@ -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -630,7 +630,7 @@ -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 @@ -734,7 +734,7 @@ -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -795,7 +795,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -911,7 +911,7 @@ -V{t#,#} Awaiting time 18: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1009,7 +1009,7 @@ -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -1070,7 +1070,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1179,7 +1179,7 @@ -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1277,7 +1277,7 @@ -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1375,7 +1375,7 @@ -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -1436,7 +1436,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1545,7 +1545,7 @@ -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1643,7 +1643,7 @@ -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -1704,7 +1704,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -1830,7 +1830,7 @@ -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -1891,7 +1891,7 @@ -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1992,7 +1992,7 @@ -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -2053,7 +2053,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2169,7 +2169,7 @@ -V{t#,#} Awaiting time 42: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2267,7 +2267,7 @@ -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -2328,7 +2328,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2431,7 +2431,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2540,7 +2540,7 @@ -V{t#,#} Awaiting time 48: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2638,7 +2638,7 @@ -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -2699,7 +2699,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2808,7 +2808,7 @@ -V{t#,#} Awaiting time 54: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2906,7 +2906,7 @@ -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -3022,7 +3022,7 @@ -V{t#,#} Awaiting time 56: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -3083,7 +3083,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -3199,7 +3199,7 @@ -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -3297,7 +3297,7 @@ -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -3358,7 +3358,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -3467,7 +3467,7 @@ -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -3572,7 +3572,7 @@ -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -3633,7 +3633,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -3742,7 +3742,7 @@ -V{t#,#} Awaiting time 72: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -3840,7 +3840,7 @@ -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 @@ -3901,7 +3901,7 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -4008,7 +4008,7 @@ -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 79: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming delayed processes @@ -4116,13 +4116,13 @@ -V{t#,#} No process to resume waiting for @(posedge t.clk2) -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:51 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 79: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 88: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:50 +-V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:51 *-* All Finished *-* -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 diff --git a/test_regress/t/t_timing_debug2.out b/test_regress/t/t_timing_debug2.out index 15008c9d5..ebcf2aac4 100644 --- a/test_regress/t/t_timing_debug2.out +++ b/test_regress/t/t_timing_debug2.out @@ -56,13 +56,13 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_initial -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__0 -V{t#,#}+ Vt_timing_debug2___024root____VbeforeTrig_h########__0 --V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:111 +-V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:115 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__1 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__2 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__3 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__4 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_count_5 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__5 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_delay @@ -74,8 +74,8 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1____Vfork_2__1 --V{t#,#} Awaiting join of fork at: t/t_timing_class.v:250 --V{t#,#} Awaiting join of fork at: t/t_timing_class.v:245 +-V{t#,#} Awaiting join of fork at: t/t_timing_class.v:259 +-V{t#,#} Awaiting join of fork at: t/t_timing_class.v:254 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__8 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__9 -V{t#,#}+ Vt_timing_debug2___024root___eval_settle @@ -84,9 +84,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:97 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -105,9 +105,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:97 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -118,28 +118,28 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 5: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 5: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:176 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:256 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:123 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:261 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:97 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 --V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 awaiting resumption +-V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 +-V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -150,18 +150,18 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:97 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -177,9 +177,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -198,9 +198,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -211,33 +211,33 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:176 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:256 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:123 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:261 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:173 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:176 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::__VnoInFunc_do_delay --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:247 --V{t#,#} Process forked at t/t_timing_class.v:246 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:256 +-V{t#,#} Process forked at t/t_timing_class.v:255 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -253,9 +253,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -274,9 +274,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -287,27 +287,27 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 15: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 15: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:123 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:261 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:177 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 awaiting resumption +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:102 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -318,18 +318,18 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:98 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:102 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:102 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -345,9 +345,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -366,9 +366,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -379,36 +379,36 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Not triggered processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:123 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:261 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:177 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:119 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:123 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_wake --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:252 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:261 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::_ctor_var_reset --V{t#,#} Process forked at t/t_timing_class.v:251 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Process forked at t/t_timing_class.v:260 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#} Committing processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act @@ -417,27 +417,27 @@ -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Moving to resume queue processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Processes to resume waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} - Process waiting at t/t_timing_class.v:115 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:115 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_sleep --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -455,17 +455,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -484,17 +484,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -506,30 +506,30 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 25: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 25: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:177 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:99 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 awaiting resumption --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:103 awaiting resumption +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -541,23 +541,23 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:99 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:103 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:103 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -573,17 +573,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -602,17 +602,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -624,35 +624,35 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:266 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:177 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:257 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:266 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::__VnoInFunc_do_delay --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:174 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:177 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_delay --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -668,17 +668,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -697,17 +697,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -719,30 +719,30 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 35: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 35: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:100 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 awaiting resumption --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:104 awaiting resumption +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -754,23 +754,23 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:100 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:104 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:104 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -786,17 +786,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -815,17 +815,17 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -837,31 +837,31 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:120 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:124 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting the post update step -V{t#,#} Doing post updates for processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 --V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting resumption +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 +-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:40 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -874,21 +874,21 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:37 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 +-V{t#,#} - Process waiting at t/t_timing_class.v:40 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:40 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass::__VnoInFunc_await --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -906,13 +906,13 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -931,13 +931,13 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -949,25 +949,25 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 45: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 45: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 --V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 awaiting resumption --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 +-V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:105 awaiting resumption +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -979,14 +979,14 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:101 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 +-V{t#,#} - Process waiting at t/t_timing_class.v:105 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:105 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1002,9 +1002,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1023,9 +1023,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1037,22 +1037,22 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:122 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:126 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1068,9 +1068,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1089,9 +1089,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1103,21 +1103,21 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 55: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 55: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:127 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1133,9 +1133,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1154,9 +1154,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1168,22 +1168,22 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 --V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:127 +-V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:123 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:127 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 --V{t#,#} Process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 awaiting resumption +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 +-V{t#,#} Process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:61 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1195,19 +1195,19 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:58 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 +-V{t#,#} - Process waiting at t/t_timing_class.v:61 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:61 -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await____Vfork_1__0 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await____Vfork_1__1 --V{t#,#} Awaiting join of fork at: t/t_timing_class.v:74 +-V{t#,#} Awaiting join of fork at: t/t_timing_class.v:77 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1223,9 +1223,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1244,9 +1244,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1258,21 +1258,21 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 65: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 65: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:79 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1288,9 +1288,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1309,9 +1309,9 @@ -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1323,35 +1323,35 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:178 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:79 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:238 --V{t#,#} Process forked at t/t_timing_class.v:256 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:250 --V{t#,#} Process forked at t/t_timing_class.v:250 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:245 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:175 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:246 +-V{t#,#} Process forked at t/t_timing_class.v:265 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:259 +-V{t#,#} Process forked at t/t_timing_class.v:259 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:254 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:178 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_1__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:76 --V{t#,#} Process forked at t/t_timing_class.v:76 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:79 +-V{t#,#} Process forked at t/t_timing_class.v:79 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:227 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 awaiting resumption +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:78 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_ready -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act @@ -1363,10 +1363,10 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 --V{t#,#} Process forked at t/t_timing_class.v:75 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:74 +-V{t#,#} - Process waiting at t/t_timing_class.v:78 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:78 +-V{t#,#} Process forked at t/t_timing_class.v:78 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:77 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation @@ -1414,15 +1414,15 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:224 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:228 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:193 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:228 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation @@ -1470,17 +1470,17 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:193 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:136 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:140 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:193 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_2__0 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:229 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:234 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act @@ -1529,13 +1529,13 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:230 --V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:237 +-V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:193 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:230 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:237 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act @@ -1584,13 +1584,13 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 --V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:193 +-V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:193 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act @@ -1639,11 +1639,11 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 95: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 95: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act @@ -1692,13 +1692,13 @@ -V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 --V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:135 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:283 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:231 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:238 *-* All Finished *-* --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:135 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act diff --git a/test_regress/t/t_timing_delay_callstack.v b/test_regress/t/t_timing_delay_callstack.v index d4bbe5959..ff2b19851 100644 --- a/test_regress/t/t_timing_delay_callstack.v +++ b/test_regress/t/t_timing_delay_callstack.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int counter = 0; + int counter = 0; - // As Verilator doesn't support recursive calls, let's use macros to - // generate tasks for a deep call stack - `ifdef TEST_VERBOSE - `define DEEP_STACK_DELAY_END(i) \ + // As Verilator doesn't support recursive calls, let's use macros to + // generate tasks for a deep call stack +`ifdef TEST_VERBOSE + `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter++; \ $write("[%0t] at depth %0d\n", $time, i); \ counter++; \ endtask - `define DEEP_STACK_DELAY(i, j) \ + `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ $write("[%0t] entering depth %0d\n", $time, i); \ #1 delay``j; \ @@ -25,37 +25,37 @@ module t; #1 $write("[%0t] leaving depth %0d\n", $time, i); \ counter++; \ endtask - `else - `define DEEP_STACK_DELAY_END(i) \ +`else + `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter += 2; \ endtask - `define DEEP_STACK_DELAY(i, j) \ + `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ #1 delay``j; \ counter++; \ #1; \ counter++; \ endtask - `endif +`endif - `DEEP_STACK_DELAY_END(10); - `DEEP_STACK_DELAY(9, 10); - `DEEP_STACK_DELAY(8, 9); - `DEEP_STACK_DELAY(7, 8); - `DEEP_STACK_DELAY(6, 7); - `DEEP_STACK_DELAY(5, 6); - `DEEP_STACK_DELAY(4, 5); - `DEEP_STACK_DELAY(3, 4); - `DEEP_STACK_DELAY(2, 3); - `DEEP_STACK_DELAY(1, 2); + `DEEP_STACK_DELAY_END(10); + `DEEP_STACK_DELAY(9, 10); + `DEEP_STACK_DELAY(8, 9); + `DEEP_STACK_DELAY(7, 8); + `DEEP_STACK_DELAY(6, 7); + `DEEP_STACK_DELAY(5, 6); + `DEEP_STACK_DELAY(4, 5); + `DEEP_STACK_DELAY(3, 4); + `DEEP_STACK_DELAY(2, 3); + `DEEP_STACK_DELAY(1, 2); - initial begin - delay1; - if ($time != 9*2) $stop; - if (counter != 10*2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + delay1; + if ($time != 9 * 2) $stop; + if (counter != 10 * 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_dlyassign.v b/test_regress/t/t_timing_dlyassign.v index 5b7e05054..27753cb00 100644 --- a/test_regress/t/t_timing_dlyassign.v +++ b/test_regress/t/t_timing_dlyassign.v @@ -6,26 +6,28 @@ // bug3781 module t; - logic clk; - logic [7:0] data; - logic [3:0] ptr; - logic [7:0] mem[16]; + logic clk; + logic [7:0] data; + logic [3:0] ptr; + logic [7:0] mem[16]; - initial begin - clk = 1'b0; - fork forever #5 clk = ~clk; join_none - ptr = '0; - #10 data = 1; - #10 if (mem[ptr] != data) $stop; - #10 data = 2; - #10 if (mem[ptr] != data) $stop; - #10 data = 3; - #10 if (mem[ptr] != data) $stop; - #10 $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + clk = 1'b0; + fork + forever #5 clk = ~clk; + join_none + ptr = '0; + #10 data = 1; + #10 if (mem[ptr] != data) $stop; + #10 data = 2; + #10 if (mem[ptr] != data) $stop; + #10 data = 3; + #10 if (mem[ptr] != data) $stop; + #10 $write("*-* All Finished *-*\n"); + $finish; + end - always @(posedge clk) begin - mem[ptr] <= #1 data; - end + always @(posedge clk) begin + mem[ptr] <= #1 data; + end endmodule diff --git a/test_regress/t/t_timing_dpi_unsup.out b/test_regress/t/t_timing_dpi_unsup.out index c4cc70ed0..1887a20c6 100644 --- a/test_regress/t/t_timing_dpi_unsup.out +++ b/test_regress/t/t_timing_dpi_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_timing_dpi_unsup.v:28:19: Unsupported: Timing controls inside DPI-exported tasks - 28 | repeat(n) @(negedge clk); - | ^ +%Error-UNSUPPORTED: t/t_timing_dpi_unsup.v:28:15: Unsupported: Timing controls inside DPI-exported tasks + 28 | repeat(n) @(negedge clk); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_timing_dpi_unsup.v b/test_regress/t/t_timing_dpi_unsup.v index 1762761e7..19d6a4010 100644 --- a/test_regress/t/t_timing_dpi_unsup.v +++ b/test_regress/t/t_timing_dpi_unsup.v @@ -15,32 +15,32 @@ module t; - localparam cycle = 1000.0 / 100.0; - localparam halfcycle = 0.5 * cycle; + localparam cycle = 1000.0 / 100.0; + localparam halfcycle = 0.5 * cycle; - logic clk = '0; + logic clk = '0; - import "DPI-C" context task tb_c_wait(); + import "DPI-C" context task tb_c_wait(); - export "DPI-C" task tb_sv_wait; - task automatic tb_sv_wait(input int n); - `WRITE_VERBOSE("tb_sv_wait start...\n"); - repeat(n) @(negedge clk); - `WRITE_VERBOSE("tb_sv_wait done!\n"); - endtask + export "DPI-C" task tb_sv_wait; + task automatic tb_sv_wait(input int n); + `WRITE_VERBOSE("tb_sv_wait start...\n"); + repeat(n) @(negedge clk); + `WRITE_VERBOSE("tb_sv_wait done!\n"); + endtask - always #halfcycle clk = ~clk; + always #halfcycle clk = ~clk; - initial begin - `WRITE_VERBOSE("test start\n"); - repeat(10) @(posedge clk); - `WRITE_VERBOSE("calling tb_c_wait...\n"); - tb_c_wait(); - `WRITE_VERBOSE("tb_c_wait finish\n"); - repeat(10) @(posedge clk); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `WRITE_VERBOSE("test start\n"); + repeat(10) @(posedge clk); + `WRITE_VERBOSE("calling tb_c_wait...\n"); + tb_c_wait(); + `WRITE_VERBOSE("tb_c_wait finish\n"); + repeat(10) @(posedge clk); + $write("*-* All Finished *-*\n"); + $finish; + end - initial #(cycle*30) $stop; // timeout + initial #(cycle*30) $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_events.v b/test_regress/t/t_timing_events.v index e78e4bf60..15d01aaa5 100644 --- a/test_regress/t/t_timing_events.v +++ b/test_regress/t/t_timing_events.v @@ -5,37 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event e1; - event e2; - event e3; - initial forever begin - #2 - ->e1; - #2 - ->e2; - #2 - ->e3; - end - initial begin - for (int i = 0; i < 10; i++) begin - @(e1, e2, e3) - if (!e1.triggered && !e2.triggered && !e3.triggered) $stop; + event e1; + event e2; + event e3; + initial forever begin + #2 + ->e1; + #2 + ->e2; + #2 + ->e3; + end + initial begin + for (int i = 0; i < 10; i++) begin + @(e1, e2, e3) + if (!e1.triggered && !e2.triggered && !e3.triggered) $stop; `ifdef TEST_VERBOSE - $write("got event %0d\n", i); + $write("got event %0d\n", i); `endif - end - $write("*-* All Finished *-*\n"); - $finish; - end + end + $write("*-* All Finished *-*\n"); + $finish; + end - int x; - initial begin - x = # 1_1 'd 12_34; // Checks we parse _ correctly - if (x != 1234) $stop; - if ($time != 11) $stop; - end + int x; + initial begin + x = # 1_1 'd 12_34; // Checks we parse _ correctly + if (x != 1234) $stop; + if ($time != 11) $stop; + end - initial #21 $stop; // timeout + initial #21 $stop; // timeout endmodule `ifndef VERILATOR_TIMING diff --git a/test_regress/t/t_timing_finish2.v b/test_regress/t/t_timing_finish2.v index 0bb0c6b44..8b135bdea 100644 --- a/test_regress/t/t_timing_finish2.v +++ b/test_regress/t/t_timing_finish2.v @@ -10,26 +10,26 @@ // verilog_format: on module tb2 (); - parameter CLK_PERIOD = 2; + parameter CLK_PERIOD = 2; - reg clk = 1'b0; - int messages; + reg clk = 1'b0; + int messages; - always #(CLK_PERIOD / 2) clk = ~clk; + always #(CLK_PERIOD / 2) clk = ~clk; - always begin - static int counter = 0; - while (counter < 3) begin - counter += 1; - $display("[%0t] Running loop %0d", $time, counter); - messages += 1; - @(posedge clk); - end + always begin + static int counter = 0; + while (counter < 3) begin + counter += 1; + $display("[%0t] Running loop %0d", $time, counter); + messages += 1; + @(posedge clk); + end - $write("[%0t] *-* All Finished *-*\n", $time); - $finish; - end + $write("[%0t] *-* All Finished *-*\n", $time); + $finish; + end - final `checkd(messages, 3); + final `checkd(messages, 3); endmodule diff --git a/test_regress/t/t_timing_fork_comb.v b/test_regress/t/t_timing_fork_comb.v index 86f45aaff..756ed73a8 100644 --- a/test_regress/t/t_timing_fork_comb.v +++ b/test_regress/t/t_timing_fork_comb.v @@ -5,54 +5,55 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit clk; + bit clk; - assign #5 clk = ~clk; + assign #5 clk = ~clk; - int a = 0; - always @(posedge clk) begin - a <= a + 1; + int a = 0; + always @(posedge clk) begin + a <= a + 1; `ifdef TEST_VERBOSE - $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); + $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif - end + end - int b = 0, c = 0, d = 0, e = 0, f = 0; - always @a begin - b = a << 1; - fork - #10 d = b + c; - e = c + d; - #5 f = d + e; - join_none - c = a + b; - end + int b = 0, c = 0, d = 0, e = 0, f = 0; + always @a begin + b = a << 1; + fork + #10 d = b + c; + e = c + d; + #5 f = d + e; + join_none + c = a + b; + end - bit [5:0] v; - always @a begin - v[0] = a[0]; - fork - begin - v[1] = a[1]; - #5 v[2] = a[2]; - end - #10 v[3] = a[3]; - join_none - v[4] = a[4]; - end + bit [5:0] v; + always @a begin + v[0] = a[0]; + fork + begin + v[1] = a[1]; + #5 v[2] = a[2]; + end + #10 v[3] = a[3]; + join_none + v[4] = a[4]; + end - initial #100 begin + initial + #100 begin `ifdef TEST_VERBOSE - $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); + $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif - if (a != 10) $stop; - if (b != 20) $stop; - if (c != 30) $stop; - if (d != 45) $stop; - if (e != 75) $stop; - if (f != 107) $stop; - if (v != 'b001010) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (a != 10) $stop; + if (b != 20) $stop; + if (c != 30) $stop; + if (d != 45) $stop; + if (e != 75) $stop; + if (f != 107) $stop; + if (v != 'b001010) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_fork_join.v b/test_regress/t/t_timing_fork_join.v index dc1253ca5..377742e08 100644 --- a/test_regress/t/t_timing_fork_join.v +++ b/test_regress/t/t_timing_fork_join.v @@ -5,80 +5,85 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event event1; - event event2; - event event3; + event event1; + event event2; + event event3; - initial begin - fork - begin /*empty*/ end - #8 $write("[%0t] fork..join process 1\n", $time); - #4 $write("[%0t] fork..join process 2\n", $time); - #2 $write("[%0t] fork..join process 3\n", $time); - $write("[%0t] fork..join process 4\n", $time); - begin : fork_in_fork #16 - $write("[%0t] fork in fork starts\n", $time); - fork - #16 $write("[%0t] fork..join process 5\n", $time); - #8 $write("[%0t] fork..join process 6\n", $time); - #4 $write("[%0t] fork..join process 7\n", $time); - $write("[%0t] fork..join process 8\n", $time); - join - $write("[%0t] fork..join in fork ends\n", $time); - end - join - #32 $write("[%0t] main process\n", $time); - fork - begin - @event1; - $write("fork..join_any process 1\n"); - ->event1; - end - $write("fork..join_any process 2\n"); - join_any - $write("back in main process\n"); - #1 ->event1; - #1 fork + initial begin + fork + begin /*empty*/ + end + #8 $write("[%0t] fork..join process 1\n", $time); + #4 $write("[%0t] fork..join process 2\n", $time); + #2 $write("[%0t] fork..join process 3\n", $time); + $write("[%0t] fork..join process 4\n", $time); + begin : fork_in_fork + #16 $write("[%0t] fork in fork starts\n", $time); + fork + #16 $write("[%0t] fork..join process 5\n", $time); + #8 $write("[%0t] fork..join process 6\n", $time); + #4 $write("[%0t] fork..join process 7\n", $time); + $write("[%0t] fork..join process 8\n", $time); + join + $write("[%0t] fork..join in fork ends\n", $time); + end + join + #32 $write("[%0t] main process\n", $time); + fork + begin + @event1; + $write("fork..join_any process 1\n"); + ->event1; + end + $write("fork..join_any process 2\n"); + join_any + $write("back in main process\n"); + #1->event1; + #1 + fork #2 $write("fork..join_any process 1\n"); - begin - @event1; - $write("fork..join_any process 2\n"); - ->event1; - end - join_any - $write("back in main process\n"); - #1 ->event1; - @event1; - // Order of triggering: - // p1->event2 ==> p2->event3 ==> p3->event3 ==> p2->event2 ==> p1->event3 ==> p3->event1 - fork - begin - #1 $write("fork..join_none process 1\n"); - ->event2; - @event2 $write("fork..join_none process 1 again\n"); - #1 ->event3; - end - begin - @event2 $write("fork..join_none process 2\n"); - #1 ->event3; - @event3 $write("fork..join_none process 2 again\n"); - #1 ->event2; - end - begin - @event3 $write("fork..join_none process 3\n"); - #1 ->event3; - @event3 $write("fork..join_none process 3 again\n"); - ->event1; - end - join_none - $write("in main process\n"); - @event1; - $write("*-* All Finished *-*\n"); - $finish; - end - initial #100 $stop; // timeout + begin + @event1; + $write("fork..join_any process 2\n"); + ->event1; + end + join_any + $write("back in main process\n"); + #1->event1; + @event1; + // Order of triggering: + // p1->event2 ==> p2->event3 ==> p3->event3 ==> p2->event2 ==> p1->event3 ==> p3->event1 + fork + begin + #1 $write("fork..join_none process 1\n"); + ->event2; + @event2 $write("fork..join_none process 1 again\n"); + #1->event3; + end + begin + @event2 $write("fork..join_none process 2\n"); + #1->event3; + @event3 $write("fork..join_none process 2 again\n"); + #1->event2; + end + begin + @event3 $write("fork..join_none process 3\n"); + #1->event3; + @event3 $write("fork..join_none process 3 again\n"); + ->event1; + end + join_none + $write("in main process\n"); + @event1; + $write("*-* All Finished *-*\n"); + $finish; + end + initial #100 $stop; // timeout - // Test optimized-out fork statements: - reg a; - initial fork a = 1; join + // Test optimized-out fork statements: + reg a; + initial + fork + a = 1; + join endmodule diff --git a/test_regress/t/t_timing_fork_many.v b/test_regress/t/t_timing_fork_many.v index 1acd7168f..b172a753f 100644 --- a/test_regress/t/t_timing_fork_many.v +++ b/test_regress/t/t_timing_fork_many.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int counter = 0; + int counter = 0; - // As Verilator doesn't support recursive calls, let's use macros to generate tasks - `define FORK2_END(i) \ + // As Verilator doesn't support recursive calls, let's use macros to generate tasks + `define FORK2_END(i) \ task fork2_``i; \ #1 counter++; \ endtask - `define FORK2(i, j) \ + `define FORK2(i, j) \ task fork2_``i; \ fork \ #1 fork2_``j; \ @@ -21,23 +21,23 @@ module t; join \ endtask - `FORK2_END(0); - `FORK2(1, 0); - `FORK2(2, 1); - `FORK2(3, 2); - `FORK2(4, 3); - `FORK2(5, 4); - `FORK2(6, 5); - `FORK2(7, 6); - `FORK2(8, 7); + `FORK2_END(0); + `FORK2(1, 0); + `FORK2(2, 1); + `FORK2(3, 2); + `FORK2(4, 3); + `FORK2(5, 4); + `FORK2(6, 5); + `FORK2(7, 6); + `FORK2(8, 7); - initial begin - fork2_8; + initial begin + fork2_8; `ifdef TEST_VERBOSE - $write("[%0t] process counter == %0d\n", $time, counter); + $write("[%0t] process counter == %0d\n", $time, counter); `endif - if (counter != 1 << 8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (counter != 1 << 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_fork_nba.v b/test_regress/t/t_timing_fork_nba.v index fea6be44c..687ac5ea9 100644 --- a/test_regress/t/t_timing_fork_nba.v +++ b/test_regress/t/t_timing_fork_nba.v @@ -4,17 +4,16 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg b = 0, c = 1; +module t ( + input clk +); - always @(posedge clk) begin - fork - b <= c; - c <= b; - join - end + reg b = 0, c = 1; + + always @(posedge clk) begin + fork + b <= c; + c <= b; + join + end endmodule diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.v b/test_regress/t/t_timing_fork_no_timing_ctrl.v index bd360c32c..edc66a841 100644 --- a/test_regress/t/t_timing_fork_no_timing_ctrl.v +++ b/test_regress/t/t_timing_fork_no_timing_ctrl.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial - fork - begin - $write("*-* All Finished *-*\n"); - $finish; - end - join_none + initial + fork + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join_none endmodule diff --git a/test_regress/t/t_timing_fork_rec_method.v b/test_regress/t/t_timing_fork_rec_method.v index f1ee319ee..9487186b5 100644 --- a/test_regress/t/t_timing_fork_rec_method.v +++ b/test_regress/t/t_timing_fork_rec_method.v @@ -5,23 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 class RecFork; - int cnt = 0; - task run(int n); - if (n > 0) begin - cnt++; - fork - run(n - 1); - join - end - endtask + int cnt = 0; + task run(int n); + if (n > 0) begin + cnt++; + fork + run(n - 1); + join + end + endtask endclass module t; - initial begin - automatic RecFork rec = new; - rec.run(7); - if (rec.cnt != 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; + initial begin + automatic RecFork rec = new; + rec.run(7); + if (rec.cnt != 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_timing_func_bad.out b/test_regress/t/t_timing_func_bad.out index 4d3b2eff3..05b81cb9d 100644 --- a/test_regress/t/t_timing_func_bad.out +++ b/test_regress/t/t_timing_func_bad.out @@ -1,26 +1,26 @@ -%Error: t/t_timing_func_bad.v:10:7: Delays are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) +%Error: t/t_timing_func_bad.v:10:5: Delays are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' - 10 | #1 $stop; - | ^ + 10 | #1 $stop; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_timing_func_bad.v:15:12: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) +%Error: t/t_timing_func_bad.v:15:10: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' - 15 | f2 = #5 0; $stop; - | ^ -%Error: t/t_timing_func_bad.v:20:7: Event controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) + 15 | f2 = #5 0; + | ^ +%Error: t/t_timing_func_bad.v:21:5: Event controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' - 20 | @e $stop; - | ^ -%Error: t/t_timing_func_bad.v:25:12: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) + 21 | @e $stop; + | ^ +%Error: t/t_timing_func_bad.v:26:10: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' - 25 | f4 = @e 0; $stop; - | ^ -%Error: t/t_timing_func_bad.v:31:7: Wait statements are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) + 26 | f4 = @e 0; + | ^ +%Error: t/t_timing_func_bad.v:33:5: Wait statements are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' - 31 | wait(i == 0) $stop; - | ^~~~ -%Error: t/t_timing_func_bad.v:42:7: Delays are not legal in final blocks (IEEE 1800-2023 9.2.3) + 33 | wait (i == 0) $stop; + | ^~~~ +%Error: t/t_timing_func_bad.v:44:5: Delays are not legal in final blocks (IEEE 1800-2023 9.2.3) : ... note: In instance 't' - 42 | #1; - | ^ + 44 | #1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_timing_func_bad.v b/test_regress/t/t_timing_func_bad.v index 4c59dd44a..e54da7673 100644 --- a/test_regress/t/t_timing_func_bad.v +++ b/test_regress/t/t_timing_func_bad.v @@ -6,41 +6,43 @@ module t; - function int f1; - #1 $stop; - f1 = 0; - endfunction + function int f1; + #1 $stop; + f1 = 0; + endfunction - function int f2; - f2 = #5 0; $stop; - endfunction + function int f2; + f2 = #5 0; + $stop; + endfunction - event e; - function int f3; - @e $stop; - f3 = 0; - endfunction + event e; + function int f3; + @e $stop; + f3 = 0; + endfunction - function int f4; - f4 = @e 0; $stop; - endfunction + function int f4; + f4 = @e 0; + $stop; + endfunction - int i; + int i; - function int f5; - wait(i == 0) $stop; - f5 = 0; - endfunction + function int f5; + wait (i == 0) $stop; + f5 = 0; + endfunction - initial begin - i = f1(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + i = f1(); + $write("*-* All Finished *-*\n"); + $finish; + end - final begin - #1; - $stop; - end + final begin + #1; + $stop; + end endmodule diff --git a/test_regress/t/t_timing_func_fork_bad.out b/test_regress/t/t_timing_func_fork_bad.out index 5a45c2d73..b9fa6bbce 100644 --- a/test_regress/t/t_timing_func_fork_bad.out +++ b/test_regress/t/t_timing_func_fork_bad.out @@ -1,42 +1,42 @@ -%Error: t/t_timing_func_fork_bad.v:12:7: Writing to an output variable of a function after a timing control is not allowed +%Error: t/t_timing_func_fork_bad.v:13:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 12 | f1 = 0; - | ^~ + 13 | f1 = 0; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_timing_func_fork_bad.v:13:7: Writing to an output variable of a function after a timing control is not allowed +%Error: t/t_timing_func_fork_bad.v:14:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 13 | o1 = 0; - | ^~ -%Error: t/t_timing_func_fork_bad.v:19:7: Writing to an output variable of a function after a timing control is not allowed + 14 | o1 = 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:22:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 19 | f2 = #5 0; $stop; - | ^~ -%Error: t/t_timing_func_fork_bad.v:20:7: Writing to an inout variable of a function after a timing control is not allowed + 22 | f2 = #5 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:24:9: Writing to an inout variable of a function after a timing control is not allowed : ... note: In instance 't' - 20 | io2 = 0; - | ^~~ -%Error: t/t_timing_func_fork_bad.v:28:7: Writing to an output variable of a function after a timing control is not allowed + 24 | io2 = 0; + | ^~~ +%Error: t/t_timing_func_fork_bad.v:34:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 28 | f3 = 0; - | ^~ -%Error: t/t_timing_func_fork_bad.v:29:7: Writing to an output variable of a function after a timing control is not allowed + 34 | f3 = 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:35:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 29 | o3 = 0; - | ^~ -%Error: t/t_timing_func_fork_bad.v:35:7: Writing to an output variable of a function after a timing control is not allowed + 35 | o3 = 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:43:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 35 | f4 = @e 0; $stop; - | ^~ -%Error: t/t_timing_func_fork_bad.v:36:7: Writing to an inout variable of a function after a timing control is not allowed + 43 | f4 = @e 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:45:9: Writing to an inout variable of a function after a timing control is not allowed : ... note: In instance 't' - 36 | io4 = 0; - | ^~~ -%Error: t/t_timing_func_fork_bad.v:45:7: Writing to an output variable of a function after a timing control is not allowed + 45 | io4 = 0; + | ^~~ +%Error: t/t_timing_func_fork_bad.v:56:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 45 | f5 = 0; - | ^~ -%Error: t/t_timing_func_fork_bad.v:46:7: Writing to an output variable of a function after a timing control is not allowed + 56 | f5 = 0; + | ^~ +%Error: t/t_timing_func_fork_bad.v:57:9: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' - 46 | o5 = 0; - | ^~ + 57 | o5 = 0; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_timing_func_fork_bad.v b/test_regress/t/t_timing_func_fork_bad.v index f2329ddba..d3319513a 100644 --- a/test_regress/t/t_timing_func_fork_bad.v +++ b/test_regress/t/t_timing_func_fork_bad.v @@ -7,44 +7,56 @@ module t; function int f1(output int o1); - fork begin - #1 $stop; - f1 = 0; - o1 = 0; - end join_none + fork + begin + #1 $stop; + f1 = 0; + o1 = 0; + end + join_none endfunction function int f2(inout io2); - fork begin - f2 = #5 0; $stop; - io2 = 0; - end join_none + fork + begin + f2 = #5 0; + $stop; + io2 = 0; + end + join_none endfunction event e; function int f3(output int o3); - fork begin - @e $stop; - f3 = 0; - o3 = 0; - end join_none + fork + begin + @e $stop; + f3 = 0; + o3 = 0; + end + join_none endfunction function int f4(inout int io4); - fork begin - f4 = @e 0; $stop; - io4 = 0; - end join_none + fork + begin + f4 = @e 0; + $stop; + io4 = 0; + end + join_none endfunction int i; function int f5(output int o5); - fork begin - wait(i == 0) $stop; - f5 = 0; - o5 = 0; - end join_none + fork + begin + wait (i == 0) $stop; + f5 = 0; + o5 = 0; + end + join_none endfunction endmodule diff --git a/test_regress/t/t_timing_func_join.v b/test_regress/t/t_timing_func_join.v index 2bd942ffc..96233b07b 100644 --- a/test_regress/t/t_timing_func_join.v +++ b/test_regress/t/t_timing_func_join.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - function int fun(int val); - fork - $display("abc"); - $display("def"); - join_none // Although join is illegal, join_none legal (IEEE 1800-2023 13.4) - return val + 2; - endfunction + function int fun(int val); + fork + $display("abc"); + $display("def"); + join_none // Although join is illegal, join_none legal (IEEE 1800-2023 13.4) + return val + 2; + endfunction - task tsk(); - fork - $display("ghi"); - $display("jkl"); - join_none - endtask + task tsk(); + fork + $display("ghi"); + $display("jkl"); + join_none + endtask - initial begin - $display("$d", fun(2)); - tsk(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("$d", fun(2)); + tsk(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_localevent.v b/test_regress/t/t_timing_localevent.v index 0616d0676..42ff6ae71 100644 --- a/test_regress/t/t_timing_localevent.v +++ b/test_regress/t/t_timing_localevent.v @@ -5,35 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 module t; - class Foo; - task sleep; - event e; - fork - @e; - #1 ->e; - join - endtask - task trigger_later1(event e); - fork #2 ->e; join_none - endtask - task trigger_later2(ref event e); - fork #3 ->e; join_none - endtask - task test; - for (int i = 0; i < 10; i++) begin - event e1, e2; - trigger_later1(e1); - trigger_later2(e2); - sleep; - @e1; @e2; - end - endtask - endclass + class Foo; + task sleep; + event e; + fork + @e; + #1 ->e; + join + endtask + task trigger_later1(event e); + fork #2 ->e; join_none + endtask + task trigger_later2(ref event e); + fork #3 ->e; join_none + endtask + task test; + for (int i = 0; i < 10; i++) begin + event e1, e2; + trigger_later1(e1); + trigger_later2(e2); + sleep; + @e1; @e2; + end + endtask + endclass - initial begin - automatic Foo foo = new; - foo.test; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic Foo foo = new; + foo.test; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_nba_1.v b/test_regress/t/t_timing_nba_1.v index 23f78baee..0620a2597 100644 --- a/test_regress/t/t_timing_nba_1.v +++ b/test_regress/t/t_timing_nba_1.v @@ -5,37 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer cyc = 0; + integer cyc = 0; - reg [7:0] a; - reg [127:0] b; + reg [7:0] a; + reg [127:0] b; - always #1 begin - cyc <= cyc + 1; - if (cyc == 0) begin - a <= 8'hFF; - a[7] <= 1'b0; - end - else if (cyc == 1) begin + always #1 begin + cyc <= cyc + 1; + if (cyc == 0) begin + a <= 8'hFF; + a[7] <= 1'b0; + end + else if (cyc == 1) begin `ifdef TEST_VERBOSE - $write("a = %x\n", a); + $write("a = %x\n", a); `endif - if (a != 8'h7F) $stop; - end - else if (cyc == 2) begin - b <= 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; - b[127] <= 1'b0; - end - else if (cyc == 3) begin + if (a != 8'h7F) $stop; + end + else if (cyc == 2) begin + b <= 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + b[127] <= 1'b0; + end + else if (cyc == 3) begin `ifdef TEST_VERBOSE - $write("b = %x\n", b); + $write("b = %x\n", b); `endif - if (b != 128'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) $stop; - end - else if (cyc > 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (b != 128'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) $stop; + end + else if (cyc > 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_timing_nba_2.v b/test_regress/t/t_timing_nba_2.v index edc969edd..f31fc29bb 100644 --- a/test_regress/t/t_timing_nba_2.v +++ b/test_regress/t/t_timing_nba_2.v @@ -5,40 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic clk1 = 0, clk2 = 0, clk3 = 0, clk4 = 0; - always #2 clk1 = ~clk1; - assign #1 clk2 = clk1; - assign #1 clk3 = clk2; - assign #1 clk4 = clk3; + logic clk1 = 0, clk2 = 0, clk3 = 0, clk4 = 0; + always #2 clk1 = ~clk1; + assign #1 clk2 = clk1; + assign #1 clk3 = clk2; + assign #1 clk4 = clk3; - int x = 0; - int cyc = 0; + int x = 0; + int cyc = 0; - always @(posedge clk1) begin - if (x != 0) $stop; + always @(posedge clk1) begin + if (x != 0) $stop; `ifdef TEST_VERBOSE - $display("[%0t] clk1 | x=%0d cyc=%0d", $realtime, x, cyc); + $display("[%0t] clk1 | x=%0d cyc=%0d", $realtime, x, cyc); `endif - @(posedge clk2); + @(posedge clk2); `ifdef TEST_VERBOSE - $display("[%0t] clk2 | x=%0d cyc=%0d", $realtime, x, cyc); + $display("[%0t] clk2 | x=%0d cyc=%0d", $realtime, x, cyc); `endif - x <= x + 1; - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + x <= x + 1; + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge clk3) begin + always @(posedge clk3) begin `ifdef TEST_VERBOSE - $display("[%0t] clk3 | x=%0d cyc=%0d", $realtime, x, cyc); + $display("[%0t] clk3 | x=%0d cyc=%0d", $realtime, x, cyc); `endif - @(posedge clk4); + @(posedge clk4); `ifdef TEST_VERBOSE - $display("[%0t] clk4 | x=%0d cyc=%0d", $realtime, x, cyc); + $display("[%0t] clk4 | x=%0d cyc=%0d", $realtime, x, cyc); `endif - x <= x - 1; - end + x <= x - 1; + end endmodule diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.v b/test_regress/t/t_timing_nested_assignment_on_lhs.v index 1bc99f5ce..132526cc8 100644 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.v +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 class uvm_object_wrapper; - function string get_type_name; - return "abcd"; - endfunction + function string get_type_name; + return "abcd"; + endfunction endclass class uvm_default_factory; - int m_type_names[string]; - virtual function int register; - uvm_object_wrapper obj; - string name; - m_type_names[(name = obj.get_type_name())] = 1; - return m_type_names[name]; - endfunction + int m_type_names[string]; + virtual function int register; + uvm_object_wrapper obj; + string name; + m_type_names[(name=obj.get_type_name())] = 1; + return m_type_names[name]; + endfunction endclass module t; - initial begin - uvm_default_factory u = new; - if (u.register() != 1) $stop; - #1; // Needed only visit assignments in V3Timing - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + uvm_default_factory u = new; + if (u.register() != 1) $stop; + #1; // Needed only visit assignments in V3Timing + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_off.v b/test_regress/t/t_timing_off.v index 5e6d4c8a4..0db6131ef 100644 --- a/test_regress/t/t_timing_off.v +++ b/test_regress/t/t_timing_off.v @@ -5,35 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event e1; - event e2; + event e1; + event e2; - initial begin - int x; - // verilator timing_off - #1 - fork @e1; @e2; join; - @e1 - wait(x == 4) - x = #1 8; - // verilator timing_on - if (x != 8) $stop; - if ($time != 0) $stop; - // verilator timing_off - @e2; - // verilator timing_on - @e1; - if ((e1.triggered && e2.triggered) - || (!e1.triggered && !e2.triggered)) $stop; - if ($time != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int x; + // verilator timing_off + #1 + fork + @e1; + @e2; + join + ; + @e1 wait (x == 4) x = #1 8; + // verilator timing_on + if (x != 8) $stop; + if ($time != 0) $stop; + // verilator timing_off + @e2; + // verilator timing_on + @e1; + if ((e1.triggered && e2.triggered) || (!e1.triggered && !e2.triggered)) $stop; + if ($time != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - initial #2 ->e1; - // verilator timing_off - initial #2 ->e2; - // verilator timing_on - initial #3 $stop; // timeout - initial #1 @(e1, e2) #1 $stop; // timeout + initial #2->e1; + // verilator timing_off + initial #2->e2; + // verilator timing_on + initial #3 $stop; // timeout + initial #1 @(e1, e2) #1 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_osc.v b/test_regress/t/t_timing_osc.v index 410d9ecb2..85932c54d 100644 --- a/test_regress/t/t_timing_osc.v +++ b/test_regress/t/t_timing_osc.v @@ -8,65 +8,63 @@ module tb_osc; - timeunit 1s; - timeprecision 1fs; + timeunit 1s; timeprecision 1fs; - logic dco_out; + logic dco_out; - bhv_dco dco ( - // Inputs - .coarse_cw(8.0), - .medium_cw(8.0), - .fine_cw(32.0), + bhv_dco dco ( + // Inputs + .coarse_cw(8.0), + .medium_cw(8.0), + .fine_cw(32.0), - // Outputs - .rf_out(dco_out) - ); + // Outputs + .rf_out(dco_out) + ); - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars; + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; `ifdef TEST_BENCHMARK - #200ns; + #200ns; `else - #3ns; + #3ns; `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module bhv_dco ( - input real coarse_cw, - input real medium_cw, - input real fine_cw, - output logic rf_out - ); + input real coarse_cw, + input real medium_cw, + input real fine_cw, + output logic rf_out +); - parameter realtime coarse_ofst = 600ps; - parameter realtime coarse_res = 60ps; - parameter realtime medium_ofst = 130ps; - parameter realtime medium_res = 6ps; - parameter realtime fine_ofst = 70ps; - parameter realtime fine_res = 0.2ps; + parameter realtime coarse_ofst = 600ps; + parameter realtime coarse_res = 60ps; + parameter realtime medium_ofst = 130ps; + parameter realtime medium_res = 6ps; + parameter realtime fine_ofst = 70ps; + parameter realtime fine_res = 0.2ps; - timeunit 1s; - timeprecision 1fs; + timeunit 1s; timeprecision 1fs; - realtime coarse_delay, medium_delay, fine_delay, jitter; - assign coarse_delay = 0.5 * (coarse_cw * coarse_res + coarse_ofst ); - assign medium_delay = 0.5 * (medium_cw * medium_res + medium_ofst ); - assign fine_delay = 0.5 * ( fine_cw * fine_res + fine_ofst + jitter); - assign jitter = 0; + realtime coarse_delay, medium_delay, fine_delay, jitter; + assign coarse_delay = 0.5 * (coarse_cw * coarse_res + coarse_ofst); + assign medium_delay = 0.5 * (medium_cw * medium_res + medium_ofst); + assign fine_delay = 0.5 * (fine_cw * fine_res + fine_ofst + jitter); + assign jitter = 0; - logic coarse_out, medium_out, fine_out; + logic coarse_out, medium_out, fine_out; - initial coarse_out = 0; - always @ (fine_out) coarse_out <= #coarse_delay ~fine_out; - assign #medium_delay medium_out = ~coarse_out; - assign #fine_delay fine_out = ~medium_out; + initial coarse_out = 0; + always @(fine_out) coarse_out <= #coarse_delay ~fine_out; + assign #medium_delay medium_out = ~coarse_out; + assign #fine_delay fine_out = ~medium_out; - assign #50ps rf_out = fine_out; + assign #50ps rf_out = fine_out; endmodule diff --git a/test_regress/t/t_timing_pong.v b/test_regress/t/t_timing_pong.v index bf90b8a29..6a175aefe 100644 --- a/test_regress/t/t_timing_pong.v +++ b/test_regress/t/t_timing_pong.v @@ -5,31 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event ping; - event pong; + event ping; + event pong; - int cnt = 0; + int cnt = 0; - initial forever @ping begin + initial + forever + @ping begin `ifdef TEST_VERBOSE - $write("ping\n"); + $write("ping\n"); `endif - cnt++; - ->pong; - end + cnt++; + ->pong; + end - initial forever @pong begin + initial + forever + @pong begin `ifdef TEST_VERBOSE - $write("pong\n"); + $write("pong\n"); `endif - if (cnt < 10) ->ping; - end + if (cnt < 10)->ping; + end - initial #1 ->ping; - initial #2 - if (cnt == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end else $stop; - initial #3 $stop; // timeout + initial #1->ping; + initial + #2 + if (cnt == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else $stop; + initial #3 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_reentry.v b/test_regress/t/t_timing_reentry.v index 18d44441d..9e9a0eaeb 100644 --- a/test_regress/t/t_timing_reentry.v +++ b/test_regress/t/t_timing_reentry.v @@ -5,31 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event a, b; + event a, b; - int order = 0; + int order = 0; - initial begin - order++; if (order != 1) $stop; - #10; - $display("[%0t]%0d -> a", $time, order); - order++; if (order != 2) $stop; - -> a; - #10; - $display("[%0t]%0d -> b", $time, order); - order++; if (order != 4) $stop; - -> b; - #100; - order++; if (order != 6) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + order++; + if (order != 1) $stop; + #10; + $display("[%0t]%0d -> a", $time, order); + order++; + if (order != 2) $stop; + ->a; + #10; + $display("[%0t]%0d -> b", $time, order); + order++; + if (order != 4) $stop; + ->b; + #100; + order++; + if (order != 6) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - always @ (a or b) begin - $display("[%0t]%0d entering", $time, order); - order++; if (order != 3) $stop; - #15; - $display("[%0t]%0d 15 later", $time, order); - order++; if (order != 5) $stop; - end + always @(a or b) begin + $display("[%0t]%0d entering", $time, order); + order++; + if (order != 3) $stop; + #15; + $display("[%0t]%0d 15 later", $time, order); + order++; + if (order != 5) $stop; + end endmodule diff --git a/test_regress/t/t_timing_sched.v b/test_regress/t/t_timing_sched.v index f7cb05d99..b70918aa5 100644 --- a/test_regress/t/t_timing_sched.v +++ b/test_regress/t/t_timing_sched.v @@ -5,59 +5,60 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic clk1 = 0; + logic clk1 = 0; - assign #3 clk1 = ~clk1; + assign #3 clk1 = ~clk1; - logic clk2 = 0; - assign #11 clk2 = ~clk2; + logic clk2 = 0; + assign #11 clk2 = ~clk2; - int a1 = 0; - int b1 = 0; - always @(posedge clk1) #4 a1 = a1 + 1; - always @(posedge clk1) @(posedge clk2) b1 = b1 + 1; + int a1 = 0; + int b1 = 0; + always @(posedge clk1) #4 a1 = a1 + 1; + always @(posedge clk1) @(posedge clk2) b1 = b1 + 1; - int a2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - a2 = a1 << 1; - // verilator lint_on MULTIDRIVEN + int a2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + a2 = a1 << 1; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] a2 = %0d", $time, a2); + $display("[%0t] a2 = %0d", $time, a2); `endif - end + end - int b2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - b2 = b1 << 2; - // verilator lint_on MULTIDRIVEN + int b2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + b2 = b1 << 2; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] b2 = %0d", $time, b2); + $display("[%0t] b2 = %0d", $time, b2); `endif - end + end - int c1 = 0; - int c2 = 0; - always @(b2, c1) begin - c2 = c1 >> 3; - c1 = b2 << 3; - end + int c1 = 0; + int c2 = 0; + always @(b2, c1) begin + c2 = c1 >> 3; + c1 = b2 << 3; + end - always @(posedge clk1) if (a2 != a1 << 1) $stop; - always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; + always @(posedge clk1) if (a2 != a1 << 1) $stop; + always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; - initial #78 begin + initial + #78 begin `ifdef TEST_VERBOSE - $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d, c1=%0d, c2=%0d", a1, b1, a2, b2, c1, c2); + $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d, c1=%0d, c2=%0d", a1, b1, a2, b2, c1, c2); `endif - if (a1 != 12) $stop; - if (b1 != 4) $stop; - if (a2 != a1 << 1) $stop; - if (b2 != b1 << 2) $stop; - if (c1 != b2 << 3) $stop; - if (c2 != c1 >> 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (a1 != 12) $stop; + if (b1 != 4) $stop; + if (a2 != a1 << 1) $stop; + if (b2 != b1 << 2) $stop; + if (c1 != b2 << 3) $stop; + if (c2 != c1 >> 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_sched_if.v b/test_regress/t/t_timing_sched_if.v index ff199da8b..744560eb6 100644 --- a/test_regress/t/t_timing_sched_if.v +++ b/test_regress/t/t_timing_sched_if.v @@ -5,71 +5,72 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit clk1 = 0; + bit clk1 = 0; - assign #3 clk1 = ~clk1; + assign #3 clk1 = ~clk1; - bit clk2 = 0; - assign #11 clk2 = ~clk2; + bit clk2 = 0; + assign #11 clk2 = ~clk2; - bit flag = 0; - int a1 = 0; - int b1 = 0; - int c1 = 0; - always @(posedge clk1) begin - if (flag) #4 a1 = a1 + 1; - else @(posedge clk2) b1 = b1 + 1; - c1 = c1 + 1; - flag = ~flag; - end + bit flag = 0; + int a1 = 0; + int b1 = 0; + int c1 = 0; + always @(posedge clk1) begin + if (flag) #4 a1 = a1 + 1; + else @(posedge clk2) b1 = b1 + 1; + c1 = c1 + 1; + flag = ~flag; + end - int a2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - a2 = a1 << 1; - // verilator lint_on MULTIDRIVEN + int a2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + a2 = a1 << 1; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] a2 = %0d", $time, a2); + $display("[%0t] a2 = %0d", $time, a2); `endif - end + end - int b2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - b2 = b1 << 2; - // verilator lint_on MULTIDRIVEN + int b2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + b2 = b1 << 2; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] b2 = %0d", $time, b2); + $display("[%0t] b2 = %0d", $time, b2); `endif - end + end - int c2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - c2 = c1 << 3; - // verilator lint_on MULTIDRIVEN + int c2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + c2 = c1 << 3; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] c2 = %0d", $time, c2); + $display("[%0t] c2 = %0d", $time, c2); `endif - end + end - always @(posedge clk1) begin - #1 if (c2 != c1 << 3) $stop; - #5 if (a2 != a1 << 1) $stop; - end - always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; + always @(posedge clk1) begin + #1 if (c2 != c1 << 3) $stop; + #5 if (a2 != a1 << 1) $stop; + end + always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; - initial #78 begin + initial + #78 begin `ifdef TEST_VERBOSE - $display("a1=%0d, b1=%0d, c1=%0d, a2=%0d, b2=%0d, c2=%0d", a1, b1, c1, a2, b2, c2); + $display("a1=%0d, b1=%0d, c1=%0d, a2=%0d, b2=%0d, c2=%0d", a1, b1, c1, a2, b2, c2); `endif - if (a1 != 3) $stop; - if (b1 != 4) $stop; - if (c1 != a1 + b1) $stop; - if (a2 != a1 << 1) $stop; - if (b2 != b1 << 2) $stop; - if (c2 != c1 << 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (a1 != 3) $stop; + if (b1 != 4) $stop; + if (c1 != a1 + b1) $stop; + if (a2 != a1 << 1) $stop; + if (b2 != b1 << 2) $stop; + if (c2 != c1 << 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_sched_nba.v b/test_regress/t/t_timing_sched_nba.v index 1650c1b62..f22537313 100644 --- a/test_regress/t/t_timing_sched_nba.v +++ b/test_regress/t/t_timing_sched_nba.v @@ -5,50 +5,51 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit clk1 = 0; + bit clk1 = 0; - assign #3 clk1 = ~clk1; + assign #3 clk1 = ~clk1; - bit clk2 = 0; - assign #11 clk2 = ~clk2; + bit clk2 = 0; + assign #11 clk2 = ~clk2; - int a1 = 0; - int b1 = 0; - always @(posedge clk1) #4 a1 <= a1 + 1; - always @(posedge clk1) @(posedge clk2) b1 <= b1 + 1; + int a1 = 0; + int b1 = 0; + always @(posedge clk1) #4 a1 <= a1 + 1; + always @(posedge clk1) @(posedge clk2) b1 <= b1 + 1; - int a2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - a2 = a1 << 1; - // verilator lint_on MULTIDRIVEN + int a2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + a2 = a1 << 1; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] a2 = %0d", $time, a2); + $display("[%0t] a2 = %0d", $time, a2); `endif - end + end - int b2 = 0; - always_comb begin - // verilator lint_off MULTIDRIVEN - b2 = b1 << 2; - // verilator lint_on MULTIDRIVEN + int b2 = 0; + always_comb begin + // verilator lint_off MULTIDRIVEN + b2 = b1 << 2; + // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE - $display("[%0t] b2 = %0d", $time, b2); + $display("[%0t] b2 = %0d", $time, b2); `endif - end + end - always @(posedge clk1) #5 if (a2 != a1 << 1) $stop; - always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; + always @(posedge clk1) #5 if (a2 != a1 << 1) $stop; + always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; - initial #78 begin + initial + #78 begin `ifdef TEST_VERBOSE - $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d", a1, b1, a2, b2); + $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d", a1, b1, a2, b2); `endif - if (a1 != 12) $stop; - if (b1 != 4) $stop; - if (a2 != a1 << 1) $stop; - if (b2 != b1 << 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (a1 != 12) $stop; + if (b1 != 4) $stop; + if (a2 != a1 << 1) $stop; + if (b2 != b1 << 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_split.v b/test_regress/t/t_timing_split.v index 0850ce7c8..93b95b12f 100644 --- a/test_regress/t/t_timing_split.v +++ b/test_regress/t/t_timing_split.v @@ -5,31 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic clk = 0; - logic data = 0; + logic clk = 0; + logic data = 0; - always #5 clk <= ~clk; + always #5 clk <= ~clk; - task static foo(); - @(negedge clk); - data = 1; - @(negedge clk); - data = 0; - endtask + task static foo(); + @(negedge clk); + data = 1; + @(negedge clk); + data = 0; + endtask -`define foo8()\ + `define foo8() \ foo();foo();foo();foo();foo();foo();foo();foo() -`define foo64()\ + `define foo64() \ `foo8();`foo8();`foo8();`foo8();`foo8();`foo8();`foo8();`foo8() -`define foo512()\ + `define foo512() \ `foo64();`foo64();`foo64();`foo64();`foo64();`foo64();`foo64();`foo64() - initial begin - `foo512(); - `foo512(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `foo512(); + `foo512(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_strobe.v b/test_regress/t/t_timing_strobe.v index 0e1fb82a1..87ca8abfe 100644 --- a/test_regress/t/t_timing_strobe.v +++ b/test_regress/t/t_timing_strobe.v @@ -6,23 +6,29 @@ module t; - event e1; - event e2; - int v = 0; + event e1; + event e2; + int v = 0; - initial begin - #1 $strobe("v = %0d", v); ->e1; - @e2 $strobe("v = %0d", v); ->e1; - @e2 $strobe("v = %0d", v); ->e1; - @e2 $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #1 $strobe("v = %0d", v); + ->e1; + @e2 $strobe("v = %0d", v); + ->e1; + @e2 $strobe("v = %0d", v); + ->e1; + @e2 $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - @e1 v = 1; #1 ->e2; - @e1 v = 2; #1 ->e2; - @e1 v = 3; #1 ->e2; - end + initial begin + @e1 v = 1; + #1->e2; + @e1 v = 2; + #1->e2; + @e1 v = 3; + #1->e2; + end - initial #5 $stop; // timeout + initial #5 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_timescale.v b/test_regress/t/t_timing_timescale.v index 74a834ee7..8983069dc 100644 --- a/test_regress/t/t_timing_timescale.v +++ b/test_regress/t/t_timing_timescale.v @@ -5,57 +5,61 @@ // SPDX-License-Identifier: CC0-1.0 module t; - timeunit 1ns; - timeprecision 1ps; - logic clkb, clk; + timeunit 1ns; timeprecision 1ps; + logic clkb, clk; - initial begin - clkb = 0; - end + initial begin + clkb = 0; + end - always @(clk) begin - clkb <= ~clk; - end + always @(clk) begin + clkb <= ~clk; + end - bot bot (.clkb(clkb), .clk(clk)); + bot bot ( + .clkb(clkb), + .clk(clk) + ); - final begin - $display("[%g] final (%m)", $realtime()); - end + final begin + $display("[%g] final (%m)", $realtime()); + end endmodule -module bot (input logic clkb, output logic clk); - timeunit 1s; - timeprecision 1fs; - integer count; - real delay; +module bot ( + input logic clkb, + output logic clk +); + timeunit 1s; timeprecision 1fs; + integer count; + real delay; - initial begin - count = 0; - delay = 500e-9; - clk = clkb; - #(3.5 * delay) $display("[%g] Initial finishing, clkb = %b", $realtime(), clkb); - end + initial begin + count = 0; + delay = 500e-9; + clk = clkb; + #(3.5 * delay) $display("[%g] Initial finishing, clkb = %b", $realtime(), clkb); + end - always @(clkb) begin - $display("[%g] clkb is %b", $realtime(), clkb); - count++; - #(delay) clk = clkb; - end + always @(clkb) begin + $display("[%g] clkb is %b", $realtime(), clkb); + count++; + #(delay) clk = clkb; + end - always @(count) begin - if (count > 20) begin - $display("[%g] Finishing (%m)", $realtime()); - if ($realtime() < (delay * 20)) begin - $display("[%g] %%Error: That was too quick!", $realtime()); - end - $write("*-* All Finished *-*\n"); - $finish; + always @(count) begin + if (count > 20) begin + $display("[%g] Finishing (%m)", $realtime()); + if ($realtime() < (delay * 20)) begin + $display("[%g] %%Error: That was too quick!", $realtime()); end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end - final begin - $display("[%g] final (%m) count was %0d", $realtime(), count); - end + final begin + $display("[%g] final (%m) count was %0d", $realtime(), count); + end endmodule diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v index c9ebb3a6f..2b32b968e 100644 --- a/test_regress/t/t_timing_trace.v +++ b/test_regress/t/t_timing_trace.v @@ -7,42 +7,44 @@ `define STRINGIFY(x) `"x`" module t; - localparam CLK_PERIOD = 10; - localparam CLK_HALF_PERIOD = CLK_PERIOD / 2; + localparam CLK_PERIOD = 10; + localparam CLK_HALF_PERIOD = CLK_PERIOD / 2; - logic rst; - logic clk; - logic a; - logic b; - logic c; - logic d; - event ev; + logic rst; + logic clk; + logic a; + logic b; + logic c; + logic d; + event ev; - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars; - forever clk = #CLK_HALF_PERIOD ~clk; + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; + forever clk = #CLK_HALF_PERIOD ~clk; + end + + always begin + rst = 1; + clk = 0; + a = 0; + c = 0; + b = ~b; + d = 0; + + fork + #(10 * CLK_PERIOD) b = 0; + join_none + + while (b) begin + c = ~c; + ->ev; + #CLK_PERIOD; end - always begin - rst = 1; - clk = 0; - a = 0; - c = 0; - b = ~b; - d = 0; - - fork #(10 * CLK_PERIOD) b = 0; join_none - - while (b) begin - c = ~c; - -> ev; - #CLK_PERIOD; - end - - $write("[%0t] Done\n", $time); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("[%0t] Done\n", $time); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_timing_unset1.out b/test_regress/t/t_timing_unset1.out index 5f441d693..38fd3f1ad 100644 --- a/test_regress/t/t_timing_unset1.out +++ b/test_regress/t/t_timing_unset1.out @@ -1,50 +1,50 @@ -%Error-NEEDTIMINGOPT: t/t_notiming.v:12:8: Use --timing or --no-timing to specify how delays should be handled +%Error-NEEDTIMINGOPT: t/t_notiming.v:12:6: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' - 12 | #1 - | ^ + 12 | #1 + | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest -%Error-NEEDTIMINGOPT: t/t_notiming.v:13:8: Use --timing or --no-timing to specify how forks should be handled +%Error-NEEDTIMINGOPT: t/t_notiming.v:13:6: Use --timing or --no-timing to specify how forks should be handled : ... note: In instance 't' - 13 | fork @e; @e; join; + 13 | fork @e; @e; join; + | ^~~~ +%Error-NEEDTIMINGOPT: t/t_notiming.v:14:6: Use --timing or --no-timing to specify how event controls should be handled + : ... note: In instance 't' + 14 | @e + | ^ +%Error-NEEDTIMINGOPT: t/t_notiming.v:15:6: Use --timing or --no-timing to specify how wait statements should be handled + : ... note: In instance 't' + 15 | wait(x == 4) + | ^~~~ +%Error-NEEDTIMINGOPT: t/t_notiming.v:16:10: Use --timing or --no-timing to specify how timing controls should be handled + : ... note: In instance 't' + 16 | x = #1 8; + | ^ +%Error-NEEDTIMINGOPT: t/t_notiming.v:19:6: Use --timing or --no-timing to specify how event controls should be handled + : ... note: In instance 't' + 19 | @e + | ^ +%Error-NEEDTIMINGOPT: t/t_notiming.v:26:11: Use --timing or --no-timing to specify how delays should be handled + : ... note: In instance 't' + 26 | initial #1 ->e; + | ^ +%Error-NEEDTIMINGOPT: t/t_notiming.v:27:11: Use --timing or --no-timing to specify how delays should be handled + : ... note: In instance 't' + 27 | initial #2 $stop; + | ^ +%Error-NEEDTIMINGOPT: t/t_notiming.v:33:8: Use --timing or --no-timing to specify how mailbox::put() should be handled + : ... note: In instance 't' + 33 | m.put(i); + | ^~~ +%Error-NEEDTIMINGOPT: t/t_notiming.v:34:8: Use --timing or --no-timing to specify how mailbox::get() should be handled + : ... note: In instance 't' + 34 | m.get(i); + | ^~~ +%Error-NEEDTIMINGOPT: t/t_notiming.v:35:8: Use --timing or --no-timing to specify how mailbox::peek() should be handled + : ... note: In instance 't' + 35 | m.peek(i); | ^~~~ -%Error-NEEDTIMINGOPT: t/t_notiming.v:14:8: Use --timing or --no-timing to specify how event controls should be handled +%Error-NEEDTIMINGOPT: t/t_notiming.v:36:8: Use --timing or --no-timing to specify how semaphore::get() should be handled : ... note: In instance 't' - 14 | @e - | ^ -%Error-NEEDTIMINGOPT: t/t_notiming.v:15:8: Use --timing or --no-timing to specify how wait statements should be handled - : ... note: In instance 't' - 15 | wait(x == 4) - | ^~~~ -%Error-NEEDTIMINGOPT: t/t_notiming.v:16:12: Use --timing or --no-timing to specify how timing controls should be handled - : ... note: In instance 't' - 16 | x = #1 8; - | ^ -%Error-NEEDTIMINGOPT: t/t_notiming.v:19:8: Use --timing or --no-timing to specify how event controls should be handled - : ... note: In instance 't' - 19 | @e - | ^ -%Error-NEEDTIMINGOPT: t/t_notiming.v:26:12: Use --timing or --no-timing to specify how delays should be handled - : ... note: In instance 't' - 26 | initial #1 ->e; - | ^ -%Error-NEEDTIMINGOPT: t/t_notiming.v:27:12: Use --timing or --no-timing to specify how delays should be handled - : ... note: In instance 't' - 27 | initial #2 $stop; - | ^ -%Error-NEEDTIMINGOPT: t/t_notiming.v:33:10: Use --timing or --no-timing to specify how mailbox::put() should be handled - : ... note: In instance 't' - 33 | m.put(i); - | ^~~ -%Error-NEEDTIMINGOPT: t/t_notiming.v:34:10: Use --timing or --no-timing to specify how mailbox::get() should be handled - : ... note: In instance 't' - 34 | m.get(i); - | ^~~ -%Error-NEEDTIMINGOPT: t/t_notiming.v:35:10: Use --timing or --no-timing to specify how mailbox::peek() should be handled - : ... note: In instance 't' - 35 | m.peek(i); - | ^~~~ -%Error-NEEDTIMINGOPT: t/t_notiming.v:36:10: Use --timing or --no-timing to specify how semaphore::get() should be handled - : ... note: In instance 't' - 36 | s.get(); - | ^~~ + 36 | s.get(); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_timing_unset2.out b/test_regress/t/t_timing_unset2.out index cccbcc862..f8892e723 100644 --- a/test_regress/t/t_timing_unset2.out +++ b/test_regress/t/t_timing_unset2.out @@ -1,26 +1,26 @@ -%Error-NEEDTIMINGOPT: t/t_timing_off.v:25:8: Use --timing or --no-timing to specify how event controls should be handled +%Error-NEEDTIMINGOPT: t/t_timing_off.v:27:5: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' - 25 | @e1; - | ^ + 27 | @e1; + | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest -%Error-NEEDTIMINGOPT: t/t_timing_off.v:33:12: Use --timing or --no-timing to specify how delays should be handled +%Error-NEEDTIMINGOPT: t/t_timing_off.v:34:11: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' - 33 | initial #2 ->e1; - | ^ -%Error-NEEDTIMINGOPT: t/t_timing_off.v:37:12: Use --timing or --no-timing to specify how delays should be handled + 34 | initial #2->e1; + | ^ +%Error-NEEDTIMINGOPT: t/t_timing_off.v:38:11: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' - 37 | initial #3 $stop; - | ^ -%Error-NEEDTIMINGOPT: t/t_timing_off.v:38:12: Use --timing or --no-timing to specify how delays should be handled + 38 | initial #3 $stop; + | ^ +%Error-NEEDTIMINGOPT: t/t_timing_off.v:39:11: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ -%Error-NEEDTIMINGOPT: t/t_timing_off.v:38:15: Use --timing or --no-timing to specify how event controls should be handled + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ +%Error-NEEDTIMINGOPT: t/t_timing_off.v:39:14: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ -%Error-NEEDTIMINGOPT: t/t_timing_off.v:38:25: Use --timing or --no-timing to specify how delays should be handled + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ +%Error-NEEDTIMINGOPT: t/t_timing_off.v:39:24: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' - 38 | initial #1 @(e1, e2) #1 $stop; - | ^ + 39 | initial #1 @(e1, e2) #1 $stop; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_timing_wait1.v b/test_regress/t/t_timing_wait1.v index 0506ea95f..d50ddb4c5 100644 --- a/test_regress/t/t_timing_wait1.v +++ b/test_regress/t/t_timing_wait1.v @@ -11,52 +11,52 @@ `endif module t; - int a = 0; - int b = 0; - int c = 0; - int q[$]; + int a = 0; + int b = 0; + int c = 0; + int q[$]; - initial begin - `WRITE_VERBOSE("start with a==0, b==0, c==0\n"); - #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n"); - #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // a==2 - #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n"); - #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // 1a - #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n"); - #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n"); // a+bc - b = 5; `WRITE_VERBOSE("push_back b to q\n"); - q.push_back(b); - end + initial begin + `WRITE_VERBOSE("start with a==0, b==0, c==0\n"); + #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n"); + #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // a==2 + #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n"); + #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // 1a + #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n"); + #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n"); // a+bc + b = 5; `WRITE_VERBOSE("push_back b to q\n"); + q.push_back(b); + end - initial begin - #1 `WRITE_VERBOSE("waiting for a==2\n"); - wait(a == 2) if (a != 2) $stop; - `WRITE_VERBOSE("waiting for a<2\n"); - wait(a < 2) if (a >= 2) $stop; - `WRITE_VERBOSE("waiting for a==0\n"); - wait(a == 0) if (a != 0) $stop; - `WRITE_VERBOSE("waiting for 1 1 && a < 3) if (a <= 1 || a >= 3) $stop; - `WRITE_VERBOSE("waiting for b>a\n"); - wait(b > a) if (b <= a) $stop; - `WRITE_VERBOSE("waiting for a+b= c) $stop; - `WRITE_VERBOSE("waiting for ac\n"); - wait(a < b && b > c) if (a >= b || b <= c) $stop; - `WRITE_VERBOSE("waiting for q.size() > 0\n"); - wait(q.size() > 0) if (q.size() <= 0) $stop; + initial begin + #1 `WRITE_VERBOSE("waiting for a==2\n"); + wait(a == 2) if (a != 2) $stop; + `WRITE_VERBOSE("waiting for a<2\n"); + wait(a < 2) if (a >= 2) $stop; + `WRITE_VERBOSE("waiting for a==0\n"); + wait(a == 0) if (a != 0) $stop; + `WRITE_VERBOSE("waiting for 1 1 && a < 3) if (a <= 1 || a >= 3) $stop; + `WRITE_VERBOSE("waiting for b>a\n"); + wait(b > a) if (b <= a) $stop; + `WRITE_VERBOSE("waiting for a+b= c) $stop; + `WRITE_VERBOSE("waiting for ac\n"); + wait(a < b && b > c) if (a >= b || b <= c) $stop; + `WRITE_VERBOSE("waiting for q.size() > 0\n"); + wait(q.size() > 0) if (q.size() <= 0) $stop; - wait(1); + wait(1); - wait(0 < 1) $write("*-* All Finished *-*\n"); - $finish; - end + wait(0 < 1) $write("*-* All Finished *-*\n"); + $finish; + end - initial wait(0) $stop; // Note this doesn't give WAITCONST - initial wait(1 == 0) $stop; + initial wait(0) $stop; // Note this doesn't give WAITCONST + initial wait(1 == 0) $stop; - initial #12 $stop; // timeout + initial #12 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_wait2.v b/test_regress/t/t_timing_wait2.v index ec9bd33f8..c7950e1a6 100644 --- a/test_regress/t/t_timing_wait2.v +++ b/test_regress/t/t_timing_wait2.v @@ -5,31 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit s[3:0] = {0, 0, 0, 0}; + bit s[3:0] = {0, 0, 0, 0}; - initial begin - wait (s[1]); - s[0] = 1; - $display("0"); - end + initial begin + wait (s[1]); + s[0] = 1; + $display("0"); + end - initial begin - wait (s[2]); - s[1] = 1; - $display("1"); - #1 $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + wait (s[2]); + s[1] = 1; + $display("1"); + #1 $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - wait (s[3]); - s[2] = 1; - $display("2"); - end + initial begin + wait (s[3]); + s[2] = 1; + $display("2"); + end - initial begin - s[3] = 1; - end + initial begin + s[3] = 1; + end - initial #2 $stop; // timeout + initial #2 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_wait3.v b/test_regress/t/t_timing_wait3.v index 157bef253..10d14154d 100644 --- a/test_regress/t/t_timing_wait3.v +++ b/test_regress/t/t_timing_wait3.v @@ -6,38 +6,38 @@ module t; - typedef process pr; - pr p[4]; - int n = 0; + typedef process pr; + pr p[4]; + int n = 0; - initial begin - wait (p[1]); - p[1].await(); - p[0] = process::self(); - if (n == 3) n++; - #2 $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + wait (p[1]); + p[1].await(); + p[0] = process::self(); + if (n == 3) n++; + #2 $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - wait (p[2]); - p[2].await(); - p[1] = process::self(); - if (n == 2) n++; - end + initial begin + wait (p[2]); + p[2].await(); + p[1] = process::self(); + if (n == 2) n++; + end - initial begin - wait (p[3]); - p[3].await(); - p[2] = process::self(); - if (n == 1) n++; - end + initial begin + wait (p[3]); + p[3].await(); + p[2] = process::self(); + if (n == 1) n++; + end - initial begin - p[3] = process::self(); - if (n == 0) n++; - end + initial begin + p[3] = process::self(); + if (n == 0) n++; + end - initial #1 if (n != 4) $stop; - initial #3 $stop; // timeout + initial #1 if (n != 4) $stop; + initial #3 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_wait_long.v b/test_regress/t/t_timing_wait_long.v index 55dc9ae53..8400dfbdc 100644 --- a/test_regress/t/t_timing_wait_long.v +++ b/test_regress/t/t_timing_wait_long.v @@ -4,43 +4,44 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ps +`timescale 1ns / 1ps -module timing_wait_long(); - localparam real FULL_TIME = 5e6; - /* verilator lint_off WIDTHTRUNC */ - localparam [22:0] FIT_TIME = int'(5e6); - localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696 - /* verilator lint_on WIDTHTRUNC */ +module timing_wait_long (); + localparam real FULL_TIME = 5e6; + /* verilator lint_off WIDTHTRUNC */ + localparam [22:0] FIT_TIME = int'(5e6); + localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696 + /* verilator lint_on WIDTHTRUNC */ - real realvar_time = 5e6; - time timevar; - initial begin - #5ms; - $display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9)); + real realvar_time = 5e6; + time timevar; + initial begin + #5ms; + $display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9)); - realvar_time = realvar_time + 1; - #realvar_time; - $display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1)); + realvar_time = realvar_time + 1; + #realvar_time; + $display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1)); - timevar = time'(realvar_time - 2); - #timevar; - $display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6)); + timevar = time'(realvar_time - 2); + #timevar; + $display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6)); - $display("FULL_TIME: %f", FULL_TIME); - #FULL_TIME; - $display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6)); + $display("FULL_TIME: %f", FULL_TIME); + #FULL_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6)); - $display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME)); - #FIT_TIME; - $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6)); + $display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME)); + #FIT_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6)); - $display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME)); - #TRUNCATED_TIME; - $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6 + real'(int'(5e6) % 2**22))); + $display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME)); + #TRUNCATED_TIME; + $display("Current realtime: %d == %d", time'($realtime), + time'(5 * 5e6 + real'(int'(5e6) % 2 ** 22))); - $write("*-* All Finished *-*\n"); - $finish(); - end + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_timing_write_expr.v b/test_regress/t/t_timing_write_expr.v index f8d1d4bfc..bee3eb160 100644 --- a/test_regress/t/t_timing_write_expr.v +++ b/test_regress/t/t_timing_write_expr.v @@ -5,23 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg [7:0] vec1 [3:0], vec2 [3:0]; + reg [7:0] vec1[3:0], vec2[3:0]; - always - for (int i = 0; i < 4; i++) - vec2[i] = vec1[i]; + always for (int i = 0; i < 4; i++) vec2[i] = vec1[i]; - initial begin - #1 vec1[0] = 8'h0f; - #1 vec1[1] = 8'h04; - #1 vec1[2] = 8'h0e; - #1 vec1[3] = 8'h0a; + initial begin + #1 vec1[0] = 8'h0f; + #1 vec1[1] = 8'h04; + #1 vec1[2] = 8'h0e; + #1 vec1[3] = 8'h0a; - #1 - for (int i = 0; i < 4; i++) - if (vec1[i] != vec2[i]) $stop; + #1 for (int i = 0; i < 4; i++) if (vec1[i] != vec2[i]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_abort.v b/test_regress/t/t_trace_abort.v index 94daf2528..2b7806547 100644 --- a/test_regress/t/t_trace_abort.v +++ b/test_regress/t/t_trace_abort.v @@ -4,18 +4,16 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [2:0] cyc = 0; + reg [2:0] cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 3'd1; - // Exit via abort to make sure trace is flushed - if (&cyc) $stop; - end + always @(posedge clk) begin + cyc <= cyc + 3'd1; + // Exit via abort to make sure trace is flushed + if (&cyc) $stop; + end endmodule diff --git a/test_regress/t/t_trace_array.v b/test_regress/t/t_trace_array.v index 7fa389382..04c0b322c 100644 --- a/test_regress/t/t_trace_array.v +++ b/test_regress/t/t_trace_array.v @@ -4,24 +4,24 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - integer cyc = 0; +module t ( + input clk +); - // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk + integer cyc = 0; - typedef struct packed { - logic [128*1024:0] d; - } s1_t; // 128 b + // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk - s1_t biggie; + typedef struct packed {logic [128*1024:0] d;} s1_t; // 128 b - always @ (posedge clk) begin - cyc <= cyc + 1; - biggie [ cyc +: 32 ] <= 32'hfeedface; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + s1_t biggie; + + always @(posedge clk) begin + cyc <= cyc + 1; + biggie[cyc+:32] <= 32'hfeedface; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_ascendingrange.v b/test_regress/t/t_trace_ascendingrange.v index 0ff3c8116..c8a02f2f0 100644 --- a/test_regress/t/t_trace_ascendingrange.v +++ b/test_regress/t/t_trace_ascendingrange.v @@ -5,93 +5,93 @@ // SPDX-License-Identifier: CC0-1.0 module t #( - parameter [0:7] P = 8'd10 - )(/*AUTOARG*/ - // Inputs - clk - ); - input clk; - int cyc = 0; + parameter [0:7] P = 8'd10 +) ( + input clk +); - localparam [0:7] Q = 8'd20; + int cyc = 0; - logic [ 0: 0] v_a = '0; - logic [ 0: 1] v_b = '0; - logic [ 0: 7] v_c = '0; - logic [ 0: 8] v_d = '0; - logic [ 0: 15] v_e = '0; - logic [ 0: 16] v_f = '0; - logic [ 0: 31] v_g = '0; - logic [ 0: 32] v_h = '0; - logic [ 0: 63] v_i = '0; - logic [ 0: 64] v_j = '0; - logic [ 0:127] v_k = '0; - logic [ 0:128] v_l = '0; - logic [ 0:255] v_m = '0; - logic [ 0:256] v_n = '0; - logic [ 0:511] v_o = '0; - logic [ -1: 1] v_p = '0; - logic [ -7: 7] v_q = '0; - logic [ -15: 15] v_r = '0; - logic [ -31: 31] v_s = '0; - logic [ -63: 63] v_t = '0; - logic [-127:127] v_u = '0; - logic [-255:255] v_v = '0; + localparam [0:7] Q = 8'd20; - always @(posedge clk) begin - if (cyc == 0) begin - v_a <= '1; - v_b <= '1; - v_c <= '1; - v_d <= '1; - v_e <= '1; - v_f <= '1; - v_g <= '1; - v_h <= '1; - v_i <= '1; - v_j <= '1; - v_k <= '1; - v_l <= '1; - v_m <= '1; - v_n <= '1; - v_o <= '1; - v_p <= '1; - v_q <= '1; - v_r <= '1; - v_s <= '1; - v_t <= '1; - v_u <= '1; - v_v <= '1; - end else begin - v_a <= v_a << 1; - v_b <= v_b << 1; - v_c <= v_c << 1; - v_d <= v_d << 1; - v_e <= v_e << 1; - v_f <= v_f << 1; - v_g <= v_g << 1; - v_h <= v_h << 1; - v_i <= v_i << 1; - v_j <= v_j << 1; - v_k <= v_k << 1; - v_l <= v_l << 1; - v_m <= v_m << 1; - v_n <= v_n << 1; - v_o <= v_o << 1; - v_p <= v_p << 1; - v_q <= v_q << 1; - v_r <= v_r << 1; - v_s <= v_s << 1; - v_t <= v_t << 1; - v_u <= v_u << 1; - v_v <= v_v << 1; - end + logic [0:0] v_a = '0; + logic [0:1] v_b = '0; + logic [0:7] v_c = '0; + logic [0:8] v_d = '0; + logic [0:15] v_e = '0; + logic [0:16] v_f = '0; + logic [0:31] v_g = '0; + logic [0:32] v_h = '0; + logic [0:63] v_i = '0; + logic [0:64] v_j = '0; + logic [0:127] v_k = '0; + logic [0:128] v_l = '0; + logic [0:255] v_m = '0; + logic [0:256] v_n = '0; + logic [0:511] v_o = '0; + logic [-1:1] v_p = '0; + logic [-7:7] v_q = '0; + logic [-15:15] v_r = '0; + logic [-31:31] v_s = '0; + logic [-63:63] v_t = '0; + logic [-127:127] v_u = '0; + logic [-255:255] v_v = '0; - cyc <= cyc + 1; - if (cyc == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 0) begin + v_a <= '1; + v_b <= '1; + v_c <= '1; + v_d <= '1; + v_e <= '1; + v_f <= '1; + v_g <= '1; + v_h <= '1; + v_i <= '1; + v_j <= '1; + v_k <= '1; + v_l <= '1; + v_m <= '1; + v_n <= '1; + v_o <= '1; + v_p <= '1; + v_q <= '1; + v_r <= '1; + v_s <= '1; + v_t <= '1; + v_u <= '1; + v_v <= '1; + end + else begin + v_a <= v_a << 1; + v_b <= v_b << 1; + v_c <= v_c << 1; + v_d <= v_d << 1; + v_e <= v_e << 1; + v_f <= v_f << 1; + v_g <= v_g << 1; + v_h <= v_h << 1; + v_i <= v_i << 1; + v_j <= v_j << 1; + v_k <= v_k << 1; + v_l <= v_l << 1; + v_m <= v_m << 1; + v_n <= v_n << 1; + v_o <= v_o << 1; + v_p <= v_p << 1; + v_q <= v_q << 1; + v_r <= v_r << 1; + v_s <= v_s << 1; + v_t <= v_t << 1; + v_u <= v_u << 1; + v_v <= v_v << 1; + end + + cyc <= cyc + 1; + if (cyc == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_binary.v b/test_regress/t/t_trace_binary.v index 79f5da68d..39bcb252e 100644 --- a/test_regress/t/t_trace_binary.v +++ b/test_regress/t/t_trace_binary.v @@ -7,14 +7,14 @@ `define STRINGIFY(x) `"x`" module t; - int sig; - initial begin - sig = 10; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(); - #20; - sig = 20; - $write("*-* All Finished *-*\n"); - $finish; - end + int sig; + initial begin + sig = 10; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(); + #20; + sig = 20; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_cat.v b/test_regress/t/t_trace_cat.v index d7adc992c..d27661a43 100644 --- a/test_regress/t/t_trace_cat.v +++ b/test_regress/t/t_trace_cat.v @@ -4,14 +4,14 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - ( - input wire clk - ); +module t ( + input wire clk +); - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end endmodule diff --git a/test_regress/t/t_trace_cat_fst.v b/test_regress/t/t_trace_cat_fst.v index f74fec5d5..05b64fdb0 100644 --- a/test_regress/t/t_trace_cat_fst.v +++ b/test_regress/t/t_trace_cat_fst.v @@ -4,15 +4,16 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - ( - input wire clk - ); +module t ( + input wire clk +); - integer cyc; initial cyc = 0; - integer unchanged; initial unchanged = 42; + integer cyc; + initial cyc = 0; + integer unchanged; + initial unchanged = 42; - always @ (posedge clk) begin - cyc <= cyc + 1; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end endmodule diff --git a/test_regress/t/t_trace_class.v b/test_regress/t/t_trace_class.v index 035eda7ed..5cab1ab99 100644 --- a/test_regress/t/t_trace_class.v +++ b/test_regress/t/t_trace_class.v @@ -6,27 +6,29 @@ `define STRINGIFY(x) `"x`" -class Cls #(parameter int PARAM); - static int s_cls_static = 123; +class Cls #( + parameter int PARAM +); + static int s_cls_static = 123; endclass -module top(); - typedef Cls#(.PARAM(0)) Cls_t; +module top (); + typedef Cls#(.PARAM(0)) Cls_t; - Cls_t obj; + Cls_t obj; - initial begin - obj = new; + initial begin + obj = new; `ifdef verilator - obj.s_cls_static = $c("100"); // no-opt + obj.s_cls_static = $c("100"); // no-opt `else - obj.s_cls_static = 100; + obj.s_cls_static = 100; `endif - if (obj.s_cls_static != 100) $stop; - if (obj.PARAM != 0) $stop; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0); - $write("*-* All Finished *-*\n"); - $finish; - end + if (obj.s_cls_static != 100) $stop; + if (obj.PARAM != 0) $stop; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 578a3c5c8..0391bbe8c 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -6,115 +6,129 @@ bit global_bit; -module t (clk); - input clk; - integer cyc = 0; +module t ( + clk +); + input clk; + integer cyc = 0; - typedef struct packed { - bit b1; - bit b0; - } strp_t; + typedef struct packed { + bit b1; + bit b0; + } strp_t; - typedef struct packed { - strp_t x1; - strp_t x0; - } strp_strp_t; + typedef struct packed { + strp_t x1; + strp_t x0; + } strp_strp_t; - typedef union packed { - strp_t x1; - strp_t x0; - } unip_strp_t; + typedef union packed { + strp_t x1; + strp_t x0; + } unip_strp_t; - typedef bit [2:1] arrp_t; - typedef arrp_t [4:3] arrp_arrp_t; + typedef bit [2:1] arrp_t; + typedef arrp_t [4:3] arrp_arrp_t; - typedef strp_t [4:3] arrp_strp_t; + typedef strp_t [4:3] arrp_strp_t; - typedef bit arru_t [2:1]; - typedef arru_t arru_arru_t [4:3]; - typedef arrp_t arru_arrp_t [4:3]; - typedef strp_t arru_strp_t [4:3]; + typedef bit arru_t[2:1]; + typedef arru_t arru_arru_t[4:3]; + typedef arrp_t arru_arrp_t[4:3]; + typedef strp_t arru_strp_t[4:3]; - strp_t v_strp; - strp_strp_t v_strp_strp; - unip_strp_t v_unip_strp; - arrp_t v_arrp; - arrp_arrp_t v_arrp_arrp; - arrp_strp_t v_arrp_strp; - arru_t v_arru; - arru_arru_t v_arru_arru; - arru_arrp_t v_arru_arrp; - arru_strp_t v_arru_strp; + strp_t v_strp; + strp_strp_t v_strp_strp; + unip_strp_t v_unip_strp; + arrp_t v_arrp; + arrp_arrp_t v_arrp_arrp; + arrp_strp_t v_arrp_strp; + arru_t v_arru; + arru_arru_t v_arru_arru; + arru_arrp_t v_arru_arrp; + arru_strp_t v_arru_strp; - real v_real; - real v_arr_real [2]; - string v_string; - chandle v_chandle; + real v_real; + real v_arr_real[2]; + string v_string; + chandle v_chandle; - string v_assoc[string]; - initial v_assoc["key"] = "value"; + string v_assoc[string]; + initial v_assoc["key"] = "value"; - typedef struct packed { - logic [31:0] data; - } str32_t; - str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 - initial v_str32x2[0] = 32'hff; - initial v_str32x2[1] = 0; + typedef struct packed {logic [31:0] data;} str32_t; + str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 + initial v_str32x2[0] = 32'hff; + initial v_str32x2[1] = 0; - typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; - enumed_t v_enumed; - enumed_t v_enumed2; - typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; - enumb_t v_enumb; - typedef struct packed { - enumb_t a; - enumb_t b; - } enumb2_str_t; - enumb2_str_t v_enumb2_str; + typedef enum int { + ZERO = 0, + ONE, + TWO, + THREE + } enumed_t; + enumed_t v_enumed; + enumed_t v_enumed2; + typedef enum logic [2:0] { + BZERO = 0, + BONE, + BTWO, + BTHREE + } enumb_t; + enumb_t v_enumb; + typedef struct packed { + enumb_t a; + enumb_t b; + } enumb2_str_t; + enumb2_str_t v_enumb2_str; - logic [7:0] unpacked_array[-2:0]; + logic [7:0] unpacked_array[-2:0]; - bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; + bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; - p #(.PARAM(2)) p2 (); - p #(.PARAM(3)) p3 (); + p #(.PARAM(2)) p2 (); + p #(.PARAM(3)) p3 (); - p #(.PARAM(4)) a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (); + p #( + .PARAM(4) + ) + a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed + (); - always @ (posedge clk) begin - cyc <= cyc + 1; - v_strp <= ~v_strp; - v_strp_strp <= ~v_strp_strp; - v_unip_strp <= ~v_unip_strp; - v_arrp_strp <= ~v_arrp_strp; - v_arrp <= ~v_arrp; - v_arrp_arrp <= ~v_arrp_arrp; - v_real <= v_real + 0.1; - v_string <= cyc[0] ? "foo" : "bar"; - v_arr_real[0] <= v_arr_real[0] + 0.2; - v_arr_real[1] <= v_arr_real[1] + 0.3; - v_enumed <= enumed_t'(v_enumed + 1); - v_enumed2 <= enumed_t'(v_enumed2 + 2); - v_enumb <= enumb_t'(v_enumb - 3'd1); - v_enumb2_str <= {v_enumb, v_enumb}; - for (integer b=3; b<=4; b++) begin - v_arru[b] <= ~v_arru[b]; - v_arru_strp[b] <= ~v_arru_strp[b]; - v_arru_arrp[b] <= ~v_arru_arrp[b]; - for (integer a=3; a<=4; a++) begin - v_arru_arru[a][b] = ~v_arru_arru[a][b]; - end + always @(posedge clk) begin + cyc <= cyc + 1; + v_strp <= ~v_strp; + v_strp_strp <= ~v_strp_strp; + v_unip_strp <= ~v_unip_strp; + v_arrp_strp <= ~v_arrp_strp; + v_arrp <= ~v_arrp; + v_arrp_arrp <= ~v_arrp_arrp; + v_real <= v_real + 0.1; + v_string <= cyc[0] ? "foo" : "bar"; + v_arr_real[0] <= v_arr_real[0] + 0.2; + v_arr_real[1] <= v_arr_real[1] + 0.3; + v_enumed <= enumed_t'(v_enumed + 1); + v_enumed2 <= enumed_t'(v_enumed2 + 2); + v_enumb <= enumb_t'(v_enumb - 3'd1); + v_enumb2_str <= {v_enumb, v_enumb}; + for (integer b = 3; b <= 4; b++) begin + v_arru[b] <= ~v_arru[b]; + v_arru_strp[b] <= ~v_arru_strp[b]; + v_arru_arrp[b] <= ~v_arru_arrp[b]; + for (integer a = 3; a <= 4; a++) begin + v_arru_arru[a][b] = ~v_arru_arru[a][b]; end - v_str32x2[0] <= v_str32x2[0] - 1; - v_str32x2[1] <= v_str32x2[1] + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + v_str32x2[0] <= v_str32x2[0] - 1; + v_str32x2[1] <= v_str32x2[1] + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module p; - parameter PARAM = 1; - initial global_bit = 1; + parameter PARAM = 1; + initial global_bit = 1; endmodule diff --git a/test_regress/t/t_trace_decoration.v b/test_regress/t/t_trace_decoration.v index f953d4dd1..91ffcb4eb 100644 --- a/test_regress/t/t_trace_decoration.v +++ b/test_regress/t/t_trace_decoration.v @@ -4,20 +4,22 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - integer a_very_long_name_which_we_will_hash_eventually=0; +module t ( + input clk +); - always @ (posedge clk) begin - a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; - if (a_very_long_name_which_we_will_hash_eventually == 5) begin - fin(); - end - end + integer a_very_long_name_which_we_will_hash_eventually = 0; - task fin; - $write("*-* All Finished *-*\n"); - $finish; - endtask + always @(posedge clk) begin + a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; + if (a_very_long_name_which_we_will_hash_eventually == 5) begin + fin(); + end + end + + task fin; + $write("*-* All Finished *-*\n"); + $finish; + endtask endmodule diff --git a/test_regress/t/t_trace_dumporder_bad.v b/test_regress/t/t_trace_dumporder_bad.v index 2356f76e4..99d3ee3bc 100644 --- a/test_regress/t/t_trace_dumporder_bad.v +++ b/test_regress/t/t_trace_dumporder_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - // Check error when this missing: $dumpfile("/should/not/be/opened"); - $dumpvars; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Check error when this missing: $dumpfile("/should/not/be/opened"); + $dumpvars; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_dumpvars_dyn.v b/test_regress/t/t_trace_dumpvars_dyn.v index ff0cc6ec5..6b3aa2f0b 100644 --- a/test_regress/t/t_trace_dumpvars_dyn.v +++ b/test_regress/t/t_trace_dumpvars_dyn.v @@ -4,41 +4,45 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc; + int cyc; - sub1 #(10) sub1a (.*); - sub1 #(20) sub1b (.*); + sub1 #(10) sub1a (.*); + sub1 #(20) sub1b (.*); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub1 #(parameter int ADD) - (input int cyc); +module sub1 #( + parameter int ADD +) ( + input int cyc +); - int value; - always_comb value = cyc + ADD; + int value; + always_comb value = cyc + ADD; - sub2 #(ADD + 1) sub2a(.*); - sub2 #(ADD + 2) sub2b(.*); - sub2 #(ADD + 3) sub2c(.*); + sub2 #(ADD + 1) sub2a (.*); + sub2 #(ADD + 2) sub2b (.*); + sub2 #(ADD + 3) sub2c (.*); endmodule -module sub2 #(parameter int ADD) - (input int cyc); +module sub2 #( + parameter int ADD +) ( + input int cyc +); - int value; - always_comb value = cyc + ADD; + int value; + always_comb value = cyc + ADD; endmodule diff --git a/test_regress/t/t_trace_empty.v b/test_regress/t/t_trace_empty.v index ba9aa442a..f7ad2e234 100644 --- a/test_regress/t/t_trace_empty.v +++ b/test_regress/t/t_trace_empty.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - /* verilator tracing_off */ + /* verilator tracing_off */ - input clk; + input clk; - reg [7:0] cyc = 8'd0; + reg [7:0] cyc = 8'd0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_ena.v b/test_regress/t/t_trace_ena.v index b58ae0541..628ceff9d 100644 --- a/test_regress/t/t_trace_ena.v +++ b/test_regress/t/t_trace_ena.v @@ -4,42 +4,40 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; + // verilator tracing_off + integer b_trace_off; + // verilator tracing_on + integer c_trace_on; + real r; - integer cyc; initial cyc=1; - // verilator tracing_off - integer b_trace_off; - // verilator tracing_on - integer c_trace_on; - real r; + // verilator tracing_off + sub sub (); + // verilator tracing_on - // verilator tracing_off - sub sub (); - // verilator tracing_on - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - b_trace_off <= cyc; - c_trace_on <= b_trace_off; - r <= r + 0.1; - if (cyc==4) begin - if (c_trace_on != 2) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + b_trace_off <= cyc; + c_trace_on <= b_trace_off; + r <= r + 0.1; + if (cyc == 4) begin + if (c_trace_on != 2) $stop; end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module sub; - integer inside_sub = 0; + integer inside_sub = 0; endmodule diff --git a/test_regress/t/t_trace_enum.v b/test_regress/t/t_trace_enum.v index 1d46134c0..b8c46b209 100644 --- a/test_regress/t/t_trace_enum.v +++ b/test_regress/t/t_trace_enum.v @@ -4,24 +4,35 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t; +typedef enum logic [1:0] { + VAL_A, + VAL_B, + VAL_C, + VAL_D +} state_t; interface MyIntf; - state_t state; + state_t state; endinterface -module t (clk); - input clk; +module t ( + clk +); + input clk; - MyIntf #() sink (); - state_t v_enumed; + MyIntf #() sink (); + state_t v_enumed; - typedef enum logic [1:0] {VAL_X, VAL_Y, VAL_Z} other_state_t; - other_state_t v_other_enumed; + typedef enum logic [1:0] { + VAL_X, + VAL_Y, + VAL_Z + } other_state_t; + other_state_t v_other_enumed; - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_event.v b/test_regress/t/t_trace_event.v index f6b9baca2..4837399a8 100644 --- a/test_regress/t/t_trace_event.v +++ b/test_regress/t/t_trace_event.v @@ -8,36 +8,35 @@ module t; - event ev_test; + event ev_test; - int i; + int i; - bit toggle = 1'b0; + bit toggle = 1'b0; - bit clk; - always #10 clk = ~clk; + bit clk; + always #10 clk = ~clk; - initial begin + initial begin + @(posedge clk); + + @(ev_test); + toggle = ~toggle; + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0, top); + for (i = 0; i < 10; i++) begin @(posedge clk); - @(ev_test); - toggle = ~toggle; - end + if (i == 5)->ev_test; + end - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0, top); - for(i=0; i < 10; i++) begin - @(posedge clk); + @(posedge clk); - if (i == 5) - ->ev_test; - end - - @(posedge clk); - - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_flag_off.v b/test_regress/t/t_trace_flag_off.v index e17fb1aae..6b7e7fd07 100644 --- a/test_regress/t/t_trace_flag_off.v +++ b/test_regress/t/t_trace_flag_off.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $dumpfile("/should/not/be/opened"); - $dumpvars(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $dumpfile("/should/not/be/opened"); + $dumpvars(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v index 3d3a7c322..ddc6af821 100644 --- a/test_regress/t/t_trace_fst.v +++ b/test_regress/t/t_trace_fst.v @@ -4,107 +4,106 @@ // SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - state, - // Inouts - fst_inout, - // Inputs - clk +module t ( /*AUTOARG*/ + // Outputs + state, + // Inouts + fst_inout, + // Inputs + clk +); + + input clk; + + int cyc; + reg rstn; + output [4:0] state; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + time fst_time; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + triand fst_triand; + trior fst_trior; + //trireg fst_trireg; // Error-UNSUPPORTED + wand fst_wand; + wor fst_wor; + wire fst_wire; + uwire fst_uwire; + inout fst_inout; + + Test test ( /*AUTOINST*/ + // Outputs + .state(state[4:0]), + // Inputs + .clk(clk), + .rstn(rstn) ); - input clk; - - int cyc; - reg rstn; - output [4:0] state; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - time fst_time; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - triand fst_triand; - trior fst_trior; - //trireg fst_trireg; // Error-UNSUPPORTED - wand fst_wand; - wor fst_wor; - wire fst_wire; - uwire fst_uwire; - inout fst_inout; - - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - fst_time <= $time; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + fst_time <= $time; + if (cyc == 0) begin + // Setup + rstn <= ~'1; + end + else if (cyc < 10) begin + rstn <= ~'1; + end + else if (cyc < 90) begin + rstn <= ~'0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input clk, - input rstn, - output logic [4:0] state - ); + input clk, + input rstn, + output logic [4:0] state +); - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; + logic [4:0] state_w; + logic [4:0] state_array[3]; + assign state = state_array[0]; - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end endmodule diff --git a/test_regress/t/t_trace_fst_cmake.v b/test_regress/t/t_trace_fst_cmake.v index fa3159e84..cc095ef19 100644 --- a/test_regress/t/t_trace_fst_cmake.v +++ b/test_regress/t/t_trace_fst_cmake.v @@ -4,96 +4,95 @@ // SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - state, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + state, + // Inputs + clk +); - input clk; + input clk; - int cyc; - reg rstn; - output [4:0] state; + int cyc; + reg rstn; + output [4:0] state; - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); + Test test ( /*AUTOINST*/ + // Outputs + .state(state[4:0]), + // Inputs + .clk(clk), + .rstn(rstn) + ); - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + rstn <= ~'1; + end + else if (cyc < 10) begin + rstn <= ~'1; + end + else if (cyc < 90) begin + rstn <= ~'0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input clk, - input rstn, - output logic [4:0] state - ); + input clk, + input rstn, + output logic [4:0] state +); - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; + logic [4:0] state_w; + logic [4:0] state_array[3]; + assign state = state_array[0]; - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end endmodule diff --git a/test_regress/t/t_trace_fst_sc.v b/test_regress/t/t_trace_fst_sc.v index 7b0bfb40c..1eb7e76a3 100644 --- a/test_regress/t/t_trace_fst_sc.v +++ b/test_regress/t/t_trace_fst_sc.v @@ -4,95 +4,91 @@ // SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; + reg rstn; - int cyc; - reg rstn; + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; + logic [4:0] state; - logic [4:0] state; + Test test ( /*AUTOINST*/ + // Outputs + .state(state[4:0]), + // Inputs + .clk(clk), + .rstn(rstn) + ); - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + rstn <= ~'1; + end + else if (cyc < 10) begin + rstn <= ~'1; + end + else if (cyc < 90) begin + rstn <= ~'0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input clk, - input rstn, - output logic [4:0] state - ); + input clk, + input rstn, + output logic [4:0] state +); - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; + logic [4:0] state_w; + logic [4:0] state_array[3]; + assign state = state_array[0]; - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end endmodule diff --git a/test_regress/t/t_trace_fst_sc_cmake.v b/test_regress/t/t_trace_fst_sc_cmake.v index 7b0bfb40c..1eb7e76a3 100644 --- a/test_regress/t/t_trace_fst_sc_cmake.v +++ b/test_regress/t/t_trace_fst_sc_cmake.v @@ -4,95 +4,91 @@ // SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; + reg rstn; - int cyc; - reg rstn; + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; + logic [4:0] state; - logic [4:0] state; + Test test ( /*AUTOINST*/ + // Outputs + .state(state[4:0]), + // Inputs + .clk(clk), + .rstn(rstn) + ); - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + rstn <= ~'1; + end + else if (cyc < 10) begin + rstn <= ~'1; + end + else if (cyc < 90) begin + rstn <= ~'0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input clk, - input rstn, - output logic [4:0] state - ); + input clk, + input rstn, + output logic [4:0] state +); - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; + logic [4:0] state_w; + logic [4:0] state_array[3]; + assign state = state_array[0]; - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end endmodule diff --git a/test_regress/t/t_trace_iface.v b/test_regress/t/t_trace_iface.v index f04cd7624..d00bff161 100644 --- a/test_regress/t/t_trace_iface.v +++ b/test_regress/t/t_trace_iface.v @@ -5,73 +5,75 @@ // SPDX-License-Identifier: CC0-1.0 interface counter_if; - logic valid; - logic [3:0] value; - logic reset; - modport counter_mp (input reset, output valid, output value); - modport core_mp (output reset, input valid, input value); + logic valid; + logic [3:0] value; + logic reset; + modport counter_mp(input reset, output valid, output value); + modport core_mp(output reset, input valid, input value); endinterface -interface counter_if2 (counter_if.counter_mp c_mp); - task automatic reset(); - c_mp.valid = '0; - c_mp.value = '0; - endtask - task automatic init(); - c_mp.valid = '0; - c_mp.value = '1; - endtask +interface counter_if2 ( + counter_if.counter_mp c_mp +); + task automatic reset(); + c_mp.valid = '0; + c_mp.value = '0; + endtask + task automatic init(); + c_mp.valid = '0; + c_mp.value = '1; + endtask endinterface -interface counter_if3 (counter_if.counter_mp c_mp); - task automatic reset(); - c_mp.valid = '0; - c_mp.value = '0; - endtask - task automatic init(); - c_mp.valid = '1; - c_mp.value = 4'ha; - endtask +interface counter_if3 ( + counter_if.counter_mp c_mp +); + task automatic reset(); + c_mp.valid = '0; + c_mp.value = '0; + endtask + task automatic init(); + c_mp.valid = '1; + c_mp.value = 4'ha; + endtask endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - counter_if c5_data(); - counter_if c6_data(); + counter_if c5_data (); + counter_if c6_data (); - counter_if2 cif2(c5_data.counter_mp); - counter_if3 cif3(c6_data.counter_mp); + counter_if2 cif2 (c5_data.counter_mp); + counter_if3 cif3 (c6_data.counter_mp); - initial begin - cif2.reset(); - cif3.reset(); - end + initial begin + cif2.reset(); + cif3.reset(); + end - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc<2) begin - if (c5_data.valid != '0) $stop; - if (c5_data.value != '0) $stop; - if (c6_data.valid != '0) $stop; - if (c6_data.value != '0) $stop; - end - if (cyc==2) begin - cif2.init(); - cif3.init(); - end - if (cyc==20) begin - if (c5_data.valid != '0) $stop; - if (c5_data.value != '1) $stop; - if (c6_data.valid != '1) $stop; - if (c6_data.value != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc < 2) begin + if (c5_data.valid != '0) $stop; + if (c5_data.value != '0) $stop; + if (c6_data.valid != '0) $stop; + if (c6_data.value != '0) $stop; + end + if (cyc == 2) begin + cif2.init(); + cif3.init(); + end + if (cyc == 20) begin + if (c5_data.valid != '0) $stop; + if (c5_data.value != '1) $stop; + if (c6_data.valid != '1) $stop; + if (c6_data.value != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_no_top_name.v b/test_regress/t/t_trace_no_top_name.v index 2e314b20f..0a9f7129c 100644 --- a/test_regress/t/t_trace_no_top_name.v +++ b/test_regress/t/t_trace_no_top_name.v @@ -7,15 +7,15 @@ `define STRINGIFY(x) `"x`" module t; - wire a = 0; - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars; - $write("*-* All Finished *-*\n"); - $finish; - end + wire a = 0; + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module another_top; - wire b = 0; + wire b = 0; endmodule diff --git a/test_regress/t/t_trace_no_top_name2.v b/test_regress/t/t_trace_no_top_name2.v index 4b8e61c75..aaf7e5b89 100644 --- a/test_regress/t/t_trace_no_top_name2.v +++ b/test_regress/t/t_trace_no_top_name2.v @@ -5,33 +5,32 @@ // SPDX-License-Identifier: CC0-1.0 package foo_pkg; - function int foo_func; - input int b; - int b_current; - return 0; - endfunction + function int foo_func; + input int b; + int b_current; + return 0; + endfunction endpackage module sub; - int a = 1212; + int a = 1212; endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - int cyc; +module t ( + input clk +); - import foo_pkg::*; + int cyc; - sub sub(); + import foo_pkg::*; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + sub sub (); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_noflag_bad.v b/test_regress/t/t_trace_noflag_bad.v index 54a5eefc8..9e9cc5760 100644 --- a/test_regress/t/t_trace_noflag_bad.v +++ b/test_regress/t/t_trace_noflag_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int i; - initial begin - i = 10; - $write("*-* All Finished *-*\n"); - $finish; - end + int i; + initial begin + i = 10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_open_wrong_order_bad.v b/test_regress/t/t_trace_open_wrong_order_bad.v index 38f8789fb..acffe3b25 100644 --- a/test_regress/t/t_trace_open_wrong_order_bad.v +++ b/test_regress/t/t_trace_open_wrong_order_bad.v @@ -4,5 +4,7 @@ // SPDX-FileCopyrightText: 2022 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t(input clk); +module t ( + input clk +); endmodule diff --git a/test_regress/t/t_trace_packed_struct.v b/test_regress/t/t_trace_packed_struct.v index 2b60a99f5..dd3cd61ba 100644 --- a/test_regress/t/t_trace_packed_struct.v +++ b/test_regress/t/t_trace_packed_struct.v @@ -4,34 +4,30 @@ // SPDX-FileCopyrightText: 2017 Andrew Bardsley // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cnt; + int cnt; - // This won't compile with tracing as an incorrect declaration is made for - // the temp variables used to represent the elements of localparam v - typedef struct packed { - logic [2:0][31:0] a; - } t; + // This won't compile with tracing as an incorrect declaration is made for + // the temp variables used to represent the elements of localparam v + typedef struct packed {logic [2:0][31:0] a;} t; - localparam t v[2:0] = '{ - '{'{32'h10000002, 32'h10000001, 32'h10000000}}, - '{'{32'h20000002, 32'h20000001, 32'h20000000}}, - '{'{32'h30000002, 32'h30000001, 32'h30000000}} - }; + localparam t v[2:0] = '{ + '{'{32'h10000002, 32'h10000001, 32'h10000000}}, + '{'{32'h20000002, 32'h20000001, 32'h20000000}}, + '{'{32'h30000002, 32'h30000001, 32'h30000000}} + }; - initial cnt = 0; - always@(posedge clk) begin - if (cnt < 3) begin - cnt = cnt + 1; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial cnt = 0; + always @(posedge clk) begin + if (cnt < 3) begin + cnt = cnt + 1; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_param.v b/test_regress/t/t_trace_param.v index b89bc2f83..544bad7ca 100644 --- a/test_regress/t/t_trace_param.v +++ b/test_regress/t/t_trace_param.v @@ -5,33 +5,32 @@ // SPDX-License-Identifier: CC0-1.0 package my_funcs; - function automatic int simple_func (input int value); - begin - simple_func = value; - end - endfunction + function automatic int simple_func(input int value); + begin + simple_func = value; + end + endfunction endpackage package my_module_types; - import my_funcs::*; + import my_funcs::*; - localparam MY_PARAM = 3; - localparam MY_PARAM2 /*verilator public*/ = simple_func(12); + localparam MY_PARAM = 3; + localparam MY_PARAM2 /*verilator public*/ = simple_func(12); endpackage module t import my_module_types::*; - ( - input i_clk, - input [MY_PARAM-1:0] i_d, +( + input i_clk, + input [MY_PARAM-1:0] i_d, output logic [MY_PARAM-1:0] o_q - ); +); - always_ff @(posedge i_clk) - o_q <= i_d; + always_ff @(posedge i_clk) o_q <= i_d; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_param_override.v b/test_regress/t/t_trace_param_override.v index 9b48c447c..9cfa417fa 100644 --- a/test_regress/t/t_trace_param_override.v +++ b/test_regress/t/t_trace_param_override.v @@ -7,15 +7,15 @@ `define STRINGIFY(x) `"x`" module t #( - parameter int POVERRODE = 16, - parameter int PORIG = 16 - ); + parameter int POVERRODE = 16, + parameter int PORIG = 16 +); - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars; + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_primitive.v b/test_regress/t/t_trace_primitive.v index 2df471972..8051a6db4 100644 --- a/test_regress/t/t_trace_primitive.v +++ b/test_regress/t/t_trace_primitive.v @@ -6,40 +6,40 @@ module t ( - clk - ); + clk + ); - input clk; - integer cyc; initial cyc = 0; + input clk; + integer cyc; initial cyc = 0; - reg a; - reg b; - reg z; - sub_t sub_t_i (z, a, b); + reg a; + reg b; + reg z; + sub_t sub_t_i (z, a, b); - always @ (posedge clk) begin - cyc <= cyc + 1; - a <= cyc[0]; - b <= cyc[1]; + always @ (posedge clk) begin + cyc <= cyc + 1; + a <= cyc[0]; + b <= cyc[1]; - if (cyc > 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule primitive CINV (a, b); - output b; - input a; + output b; + input a; `ifdef VERILATOR - assign b = ~a; + assign b = ~a; `else - table - //b a - 0 : ? : 1; - 1 : ? : 0; - endtable + table + //b a + 0 : ? : 1; + 1 : ? : 0; + endtable `endif endprimitive diff --git a/test_regress/t/t_trace_public.v b/test_regress/t/t_trace_public.v index cebbd5258..0e553f7e0 100644 --- a/test_regress/t/t_trace_public.v +++ b/test_regress/t/t_trace_public.v @@ -5,78 +5,78 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input wire CLK, - output reg RESET - ); + input wire CLK, + output reg RESET +); - neg neg (.clk(CLK)); - little little (.clk(CLK)); - glbl glbl (); + neg neg (.clk(CLK)); + little little (.clk(CLK)); + glbl glbl (); - // A vector - logic [2:1] vec [4:3]; + // A vector + logic [2:1] vec [4:3]; - integer val = 0; - always @ (posedge CLK) begin - if (RESET) val <= 0; - else val <= val + 1; - vec[3] <= val[1:0]; - vec[4] <= val[3:2]; - end + integer val = 0; + always @ (posedge CLK) begin + if (RESET) val <= 0; + else val <= val + 1; + vec[3] <= val[1:0]; + vec[4] <= val[3:2]; + end - initial RESET = 1'b1; - always @ (posedge CLK) - RESET <= glbl.GSR; + initial RESET = 1'b1; + always @ (posedge CLK) + RESET <= glbl.GSR; endmodule module glbl(); `ifdef PUB_FUNC - reg GSR; - task setGSR; + reg GSR; + task setGSR; `ifdef ATTRIBUTES - /* verilator public */ + /* verilator public */ `endif - input value; - GSR = value; - endtask + input value; + GSR = value; + endtask `else `ifdef ATTRIBUTES - reg GSR /*verilator public*/; + reg GSR /*verilator public*/; `else - reg GSR; + reg GSR; `endif `endif endmodule module neg ( - input clk - ); + input clk +); - reg [0:-7] i8; initial i8 = '0; - reg [-1:-48] i48; initial i48 = '0; - reg [63:-64] i128; initial i128 = '0; + reg [0:-7] i8; initial i8 = '0; + reg [-1:-48] i48; initial i48 = '0; + reg [63:-64] i128; initial i128 = '0; - always @ (posedge clk) begin - i8 <= ~i8; - i48 <= ~i48; - i128 <= ~i128; - end + always @ (posedge clk) begin + i8 <= ~i8; + i48 <= ~i48; + i128 <= ~i128; + end endmodule module little ( - input clk - ); + input clk +); - // verilator lint_off ASCRANGE - reg [0:7] i8; initial i8 = '0; - reg [1:49] i48; initial i48 = '0; - reg [63:190] i128; initial i128 = '0; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + reg [0:7] i8; initial i8 = '0; + reg [1:49] i48; initial i48 = '0; + reg [63:190] i128; initial i128 = '0; + // verilator lint_on ASCRANGE - always @ (posedge clk) begin - i8 <= ~i8; - i48 <= ~i48; - i128 <= ~i128; - end + always @ (posedge clk) begin + i8 <= ~i8; + i48 <= ~i48; + i128 <= ~i128; + end endmodule diff --git a/test_regress/t/t_trace_sc_empty.v b/test_regress/t/t_trace_sc_empty.v index a78a4f756..d452dc1be 100644 --- a/test_regress/t/t_trace_sc_empty.v +++ b/test_regress/t/t_trace_sc_empty.v @@ -4,11 +4,10 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - ( - output id0 - ); +module t ( + output id0 +); - assign id0 = 0; + assign id0 = 0; endmodule diff --git a/test_regress/t/t_trace_scope_no_inline.v b/test_regress/t/t_trace_scope_no_inline.v index 45f0f3a09..66ae3cbb9 100644 --- a/test_regress/t/t_trace_scope_no_inline.v +++ b/test_regress/t/t_trace_scope_no_inline.v @@ -4,32 +4,38 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - integer cyc = 0; +module t ( + input clk +); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + integer cyc = 0; - mid mid_a(clk); - mid mid_b(clk); - mid mid_c(clk); + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + mid mid_a (clk); + mid mid_b (clk); + mid mid_c (clk); endmodule -module mid(input wire clk); - int cnt = 0; - always @(posedge clk) cnt += 1; - sub sub_a(clk); - sub sub_b(clk); - sub sub_c(clk); +module mid ( + input wire clk +); + int cnt = 0; + always @(posedge clk) cnt += 1; + sub sub_a (clk); + sub sub_b (clk); + sub sub_c (clk); endmodule -module sub(input wire clk); - int cnt = 0; - always @(posedge clk) cnt += 2; +module sub ( + input wire clk +); + int cnt = 0; + always @(posedge clk) cnt += 2; endmodule diff --git a/test_regress/t/t_trace_scope_vlt.v b/test_regress/t/t_trace_scope_vlt.v index ff0cc6ec5..6b3aa2f0b 100644 --- a/test_regress/t/t_trace_scope_vlt.v +++ b/test_regress/t/t_trace_scope_vlt.v @@ -4,41 +4,45 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc; + int cyc; - sub1 #(10) sub1a (.*); - sub1 #(20) sub1b (.*); + sub1 #(10) sub1a (.*); + sub1 #(20) sub1b (.*); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub1 #(parameter int ADD) - (input int cyc); +module sub1 #( + parameter int ADD +) ( + input int cyc +); - int value; - always_comb value = cyc + ADD; + int value; + always_comb value = cyc + ADD; - sub2 #(ADD + 1) sub2a(.*); - sub2 #(ADD + 2) sub2b(.*); - sub2 #(ADD + 3) sub2c(.*); + sub2 #(ADD + 1) sub2a (.*); + sub2 #(ADD + 2) sub2b (.*); + sub2 #(ADD + 3) sub2c (.*); endmodule -module sub2 #(parameter int ADD) - (input int cyc); +module sub2 #( + parameter int ADD +) ( + input int cyc +); - int value; - always_comb value = cyc + ADD; + int value; + always_comb value = cyc + ADD; endmodule diff --git a/test_regress/t/t_trace_scstruct.v b/test_regress/t/t_trace_scstruct.v index 4196f42d6..37ce84e91 100644 --- a/test_regress/t/t_trace_scstruct.v +++ b/test_regress/t/t_trace_scstruct.v @@ -10,18 +10,17 @@ //bug858 typedef struct packed { - logic m_1; - logic m_2; + logic m_1; + logic m_2; } struct_t; typedef struct packed { - logic [94:0] m_1; - logic m_2; + logic [94:0] m_1; + logic m_2; } struct96_t; -module t - ( - input struct_t test_input, - input struct96_t t96 - ); +module t ( + input struct_t test_input, + input struct96_t t96 +); endmodule diff --git a/test_regress/t/t_trace_split_cfuncs.v b/test_regress/t/t_trace_split_cfuncs.v index a4adac3ac..6542803e5 100644 --- a/test_regress/t/t_trace_split_cfuncs.v +++ b/test_regress/t/t_trace_split_cfuncs.v @@ -6,9 +6,9 @@ module t; - initial begin - $dumpfile("dump.vcd"); - $dumpvars(); - end + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + end endmodule diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.v b/test_regress/t/t_trace_split_cfuncs_dpi_export.v index 6bd0d4ca5..784f0ca80 100644 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.v +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.v @@ -6,13 +6,13 @@ module t; - function automatic void func(); - endfunction - export "DPI-C" function func; + function automatic void func(); + endfunction + export "DPI-C" function func; - initial begin - $dumpfile("dump.vcd"); - $dumpvars(); - end + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + end endmodule diff --git a/test_regress/t/t_trace_string.v b/test_regress/t/t_trace_string.v index 8e7220c8f..940ae3077 100644 --- a/test_regress/t/t_trace_string.v +++ b/test_regress/t/t_trace_string.v @@ -4,43 +4,41 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilog_format: off + localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; - localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; + initial begin + $display("%s", SVEC[3'd1]); + $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - $display("%s", SVEC[3'd1]); - $write("*-* All Finished *-*\n"); - $finish; - end + localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; + // verilog_format: on - localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; + function automatic string regx(logic [5-1:0] r, bit abi = 1'b0); + regx = abi ? REGX[r] : $sformatf("x%0d", r); + endfunction : regx - function automatic string regx (logic [5-1:0] r, bit abi=1'b0); - regx = abi ? REGX[r] : $sformatf("x%0d", r); - endfunction: regx + function string dis32(logic [32-1:0] op); + casez (op) + 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); + 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); + 32'b????_????_????_????_?000_????_?110_0111: + dis32 = $sformatf("jalr %s, 0x%03x (%s)", regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); + default: dis32 = "illegal"; + endcase + endfunction : dis32 - function string dis32 (logic [32-1:0] op); - casez (op) - 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); - 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); - 32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)", - regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); - default: dis32 = "illegal"; - endcase - endfunction: dis32 - - always @(posedge clk) begin - for (int unsigned i=0; i<32; i++) - $display("REGX: %s", regx(i[4:0])); - $display("OP: %s", dis32(32'h00000000)); - $finish(); - end + always @(posedge clk) begin + for (int unsigned i = 0; i < 32; i++) $display("REGX: %s", regx(i[4:0])); + $display("OP: %s", dis32(32'h00000000)); + $finish(); + end endmodule diff --git a/test_regress/t/t_trace_timescale.v b/test_regress/t/t_trace_timescale.v index aed05df84..ad798b7b4 100644 --- a/test_regress/t/t_trace_timescale.v +++ b/test_regress/t/t_trace_timescale.v @@ -4,25 +4,22 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 1ms/1ms +`timescale 1ms / 1ms // See also t_time_sc_*.v/pl -module t - (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; - integer cyc; initial cyc = 0; - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_timing1.v b/test_regress/t/t_trace_timing1.v index 9c628a93f..bac51d569 100644 --- a/test_regress/t/t_trace_timing1.v +++ b/test_regress/t/t_trace_timing1.v @@ -8,32 +8,32 @@ module t; - localparam CLOCK_CYCLE = 10; + localparam CLOCK_CYCLE = 10; - logic rst; - logic clk; + logic rst; + logic clk; - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars; - end + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; + end - always #(CLOCK_CYCLE/2) clk = ~clk; + always #(CLOCK_CYCLE / 2) clk = ~clk; - always begin - rst = 1; - clk = 0; - $display("[%0t] rst: %d, rst: %d", $time, rst, rst); + always begin + rst = 1; + clk = 0; + $display("[%0t] rst: %d, rst: %d", $time, rst, rst); - #CLOCK_CYCLE; - rst = 0; - $display("[%0t] rst: %d, rst: %d", $time, rst, rst); + #CLOCK_CYCLE; + rst = 0; + $display("[%0t] rst: %d, rst: %d", $time, rst, rst); - #CLOCK_CYCLE; - $display("[%0t] rst: %d, rst: %d", $time, rst, rst); + #CLOCK_CYCLE; + $display("[%0t] rst: %d, rst: %d", $time, rst, rst); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v index 2d2db3180..2d5829ede 100644 --- a/test_regress/t/t_trace_two_a.v +++ b/test_regress/t/t_trace_two_a.v @@ -7,77 +7,75 @@ `define CONCAT(a, b) a``b `define STRINGIFY(x) `"x`" -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; + integer c_trace_on; - integer cyc; initial cyc=1; - integer c_trace_on; + sub sub (); - sub sub (); + // verilator tracing_off + string filename; + // verilator tracing_on - // verilator tracing_off - string filename; - // verilator tracing_on - - initial begin + initial begin `ifdef TEST_FST - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"}; + filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"}; `else - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"}; + filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"}; `endif `ifdef TEST_DUMP - $dumpfile(filename); - $dumpvars(0); // Intentionally no ", top" for parsing coverage with just (expr) - $dumpvars(1, top); // Intentionally checking parsing coverage - $dumpvars(1, top, top); // Intentionally checking parsing coverage - $dumplimit(10 * 1024 * 1024); + $dumpfile(filename); + $dumpvars(0); // Intentionally no ", top" for parsing coverage with just (expr) + $dumpvars(1, top); // Intentionally checking parsing coverage + $dumpvars(1, top, top); // Intentionally checking parsing coverage + $dumplimit(10 * 1024 * 1024); `elsif TEST_DUMPPORTS - $dumpports(top, filename); - $dumpportslimit(10 * 1024 * 1024, filename); + $dumpports(top, filename); + $dumpportslimit(10 * 1024 * 1024, filename); `endif - end + end - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - c_trace_on <= cyc + 2; - if (cyc == 3) begin + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + c_trace_on <= cyc + 2; + if (cyc == 3) begin `ifdef TEST_DUMP - $dumpoff; + $dumpoff; `elsif TEST_DUMPPORTS - $dumpportsoff(filename); + $dumpportsoff(filename); `endif - end - else if (cyc == 5) begin -`ifdef TEST_DUMP - $dumpall; - $dumpflush; -`elsif TEST_DUMPPORTS - $dumpportsall(filename); - $dumpportsflush(filename); -`endif - end - else if (cyc == 7) begin -`ifdef TEST_DUMP - $dumpon; -`elsif TEST_DUMPPORTS - $dumpportson(filename); -`endif - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + else if (cyc == 5) begin +`ifdef TEST_DUMP + $dumpall; + $dumpflush; +`elsif TEST_DUMPPORTS + $dumpportsall(filename); + $dumpportsflush(filename); +`endif + end + else if (cyc == 7) begin +`ifdef TEST_DUMP + $dumpon; +`elsif TEST_DUMPPORTS + $dumpportson(filename); +`endif + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module sub; - integer inside_sub_a = 1; + integer inside_sub_a = 1; endmodule diff --git a/test_regress/t/t_trace_two_b.v b/test_regress/t/t_trace_two_b.v index a5bcad4c4..8b68702e0 100644 --- a/test_regress/t/t_trace_two_b.v +++ b/test_regress/t/t_trace_two_b.v @@ -4,26 +4,24 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; + integer c_trace_on; + real r; - integer cyc; initial cyc=1; - integer c_trace_on; - real r; + sub sub (); - sub sub (); - - always @ (posedge clk) begin - if (cyc != 0) begin - r <= r + 0.1; - end - end + always @(posedge clk) begin + if (cyc != 0) begin + r <= r + 0.1; + end + end endmodule module sub; - integer inside_sub_a = 2; + integer inside_sub_a = 2; endmodule diff --git a/test_regress/t/t_trace_wide_struct.v b/test_regress/t/t_trace_wide_struct.v index 25439fb8c..8ec7a6a03 100644 --- a/test_regress/t/t_trace_wide_struct.v +++ b/test_regress/t/t_trace_wide_struct.v @@ -4,20 +4,16 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef struct { - logic [64:0] long_signal; - } mystruct_t; + typedef struct {logic [64:0] long_signal;} mystruct_t; - mystruct_t mystruct; + mystruct_t mystruct; - initial begin - $finish; - end + initial begin + $finish; + end endmodule diff --git a/test_regress/t/t_tri_and_eqcase.out b/test_regress/t/t_tri_and_eqcase.out index 5555b3000..5a19e60d8 100644 --- a/test_regress/t/t_tri_and_eqcase.out +++ b/test_regress/t/t_tri_and_eqcase.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:9:29: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp - 9 | logic b = 1'bz === (clk1 & clk2); - | ^ +%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:12:28: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp + 12 | logic b = 1'bz === (clk1 & clk2); + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Internal Error: t/t_tri_and_eqcase.v:9:19: ../V3Ast.cpp:#: Null item passed to setOp2p - 9 | logic b = 1'bz === (clk1 & clk2); - | ^~~ +%Error: Internal Error: t/t_tri_and_eqcase.v:12:18: ../V3Ast.cpp:#: Null item passed to setOp2p + 12 | logic b = 1'bz === (clk1 & clk2); + | ^~~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_tri_and_eqcase.v b/test_regress/t/t_tri_and_eqcase.v index e7c0a4ea3..86b4da23b 100644 --- a/test_regress/t/t_tri_and_eqcase.v +++ b/test_regress/t/t_tri_and_eqcase.v @@ -4,14 +4,17 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (clk1, clk2); - input wire clk1, clk2; - logic b = 1'bz === (clk1 & clk2); +module t ( + clk1, + clk2 +); + input wire clk1, clk2; + logic b = 1'bz === (clk1 & clk2); - always begin - if (!b) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always begin + if (!b) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_tri_array.out b/test_regress/t/t_tri_array.out index c18ab6ffb..1fe07421a 100644 --- a/test_regress/t/t_tri_array.out +++ b/test_regress/t/t_tri_array.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_tri_array.v:25:25: Unsupported LHS tristate construct: ARRAYSEL +%Error-UNSUPPORTED: t/t_tri_array.v:24:17: Unsupported LHS tristate construct: ARRAYSEL : ... note: In instance 't' - 25 | Pad pad1 (.pad(pad[g]), - | ^ + 24 | .pad(pad[g]), + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_tri_array.v:28:25: Unsupported LHS tristate construct: ARRAYSEL +%Error-UNSUPPORTED: t/t_tri_array.v:29:17: Unsupported LHS tristate construct: ARRAYSEL : ... note: In instance 't' - 28 | Pad pad0 (.pad(pad[g]), - | ^ + 29 | .pad(pad[g]), + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v index d1fe77daf..256f16ad5 100644 --- a/test_regress/t/t_tri_array.v +++ b/test_regress/t/t_tri_array.v @@ -4,67 +4,69 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - parameter NPAD = 4; + parameter NPAD = 4; - tri pad [NPAD-1:0]; // Array - wire [NPAD-1:0] data0 = crc[0 +: 4]; - wire [NPAD-1:0] data1 = crc[8 +: 4]; - wire [NPAD-1:0] en = crc[16 +: 4]; + tri pad[NPAD-1:0]; // Array + wire [NPAD-1:0] data0 = crc[0+:4]; + wire [NPAD-1:0] data1 = crc[8+:4]; + wire [NPAD-1:0] en = crc[16+:4]; - for (genvar g=0; g 32) begin + $display("%%Error:(v): Excessive loop count"); + $display("drv_en = %b, test_en = %b", drv_en, test_en); $finish(1); - end + end + end - always @(loop_cnt) - begin - if (loop_cnt > 32) begin - $display("%%Error:(v): Excessive loop count"); - $display("drv_en = %b, test_en = %b", drv_en, test_en); - $finish(1); - end - end + final begin + $display("Info:(v): All done at %t", $time); + $display("Info:(v): Error count = %0d", error_cnt); + chk_err: assert(error_cnt == 0); + end - final begin - $display("Info:(v): All done at %t", $time); - $display("Info:(v): Error count = %0d", error_cnt); - chk_err: assert(error_cnt == 0); - end + wire internal_sub_io; - wire internal_sub_io; + logic [15:0] my_64_segment; + logic [31:0] my_128_segment; - logic [15:0] my_64_segment; - logic [31:0] my_128_segment; + task chk_sigs; + begin + #(1ps); + $display("Info:(v): rand_bit = %b", rand_bit); + if (|drv_en) begin + $display("Info:(v): drv_en = %b", drv_en); + $display("Info:(v): bidir_single_bit_io = %b", bidir_single_bit_io); + $display("Info:(v): bidir_bus_64_io = %b,%b,%b,%b", + bidir_bus_64_io[63:48], bidir_bus_64_io[47:32], + bidir_bus_64_io[31:16],bidir_bus_64_io[15:0]); + $display("Info:(v): bidir_bus_128_io = %b,%b,%b,%b", + bidir_bus_128_io[127:96], bidir_bus_128_io[95:64], + bidir_bus_128_io[63:32], bidir_bus_128_io[31:0]); - task chk_sigs; - begin - #(1ps); - $display("Info:(v): rand_bit = %b", rand_bit); - if (|drv_en) begin - $display("Info:(v): drv_en = %b", drv_en); - $display("Info:(v): bidir_single_bit_io = %b", bidir_single_bit_io); - $display("Info:(v): bidir_bus_64_io = %b,%b,%b,%b", - bidir_bus_64_io[63:48], bidir_bus_64_io[47:32], - bidir_bus_64_io[31:16],bidir_bus_64_io[15:0]); - $display("Info:(v): bidir_bus_128_io = %b,%b,%b,%b", - bidir_bus_128_io[127:96], bidir_bus_128_io[95:64], - bidir_bus_128_io[63:32], bidir_bus_128_io[31:0]); + for (int i=0;i<4;i++) begin + if (drv_en[0]) begin + if (bidir_single_bit_io !== rand_bit) begin + $display("%%Error:(v): bidir_single_bit_io is wrong (expect %b got %b)", + rand_bit, bidir_single_bit_io); + error_cnt++; + end + if (sub_io !== rand_bit) begin + $display("%%Error:(v): sub_io is wrong (expect %b, got %b)", + rand_bit, sub_io); + end + end - for (int i=0;i<4;i++) begin - if (drv_en[0]) begin - if (bidir_single_bit_io !== rand_bit) begin - $display("%%Error:(v): bidir_single_bit_io is wrong (expect %b got %b)", - rand_bit, bidir_single_bit_io); - error_cnt++; - end - if (sub_io !== rand_bit) begin - $display("%%Error:(v): sub_io is wrong (expect %b, got %b)", - rand_bit, sub_io); - end + if (drv_en[1]) begin + if (internal_sub_io !== ~rand_bit) begin + $display("%%Error:(v): sub_io is wrong"); + error_cnt++; + end + end + + if (drv_en[i]) begin + int msb, lsb; + msb = ((i+1)*16-1); + lsb = i*16; + + case(i) + 'd0: my_64_segment = bidir_bus_64_io[15:0]; + 'd1: my_64_segment = bidir_bus_64_io[31:16]; + 'd2: my_64_segment = bidir_bus_64_io[47:32]; + default: my_64_segment = bidir_bus_64_io[63:48]; + endcase + + case(i) + 'd0: my_128_segment = bidir_bus_128_io[31:0]; + 'd1: my_128_segment = bidir_bus_128_io[63:32]; + 'd2: my_128_segment = bidir_bus_128_io[95:64]; + default: my_128_segment = bidir_bus_128_io[127:96]; + endcase + + if (my_64_segment !== {16{rand_bit}}) begin + $display("%%Error:(v): bidir_bus_64_io is wrong"); + $display("Error:(v): Should be bidir_bus_64_io[%0d:%0d] = %b, was = %b", + msb, lsb, {16{rand_bit}}, my_64_segment); + error_cnt++; + end + else begin + $display("Info:(v): Pass: bidir_bus_64_io[%0d:%0d] = %b", + msb, lsb, {16{rand_bit}}); end - if (drv_en[1]) begin - if (internal_sub_io !== ~rand_bit) begin - $display("%%Error:(v): sub_io is wrong"); - error_cnt++; - end + msb = ((i+1)*32-1); + lsb = i*32; + if (my_128_segment !== {32{rand_bit}}) begin + $display("%%Error:(v): bidir_bus_128_io is wrong"); + $display("Error:(v):Should be bidir_bus_128_io[%0d:%0d] = %b, was = %b", + msb, lsb, {32{rand_bit}}, my_128_segment); + error_cnt++; end - - if (drv_en[i]) begin - int msb, lsb; - msb = ((i+1)*16-1); - lsb = i*16; - - case(i) - 'd0: my_64_segment = bidir_bus_64_io[15:0]; - 'd1: my_64_segment = bidir_bus_64_io[31:16]; - 'd2: my_64_segment = bidir_bus_64_io[47:32]; - default: my_64_segment = bidir_bus_64_io[63:48]; - endcase - - case(i) - 'd0: my_128_segment = bidir_bus_128_io[31:0]; - 'd1: my_128_segment = bidir_bus_128_io[63:32]; - 'd2: my_128_segment = bidir_bus_128_io[95:64]; - default: my_128_segment = bidir_bus_128_io[127:96]; - endcase - - if (my_64_segment !== {16{rand_bit}}) begin - $display("%%Error:(v): bidir_bus_64_io is wrong"); - $display("Error:(v): Should be bidir_bus_64_io[%0d:%0d] = %b, was = %b", - msb, lsb, {16{rand_bit}}, my_64_segment); - error_cnt++; - end - else begin - $display("Info:(v): Pass: bidir_bus_64_io[%0d:%0d] = %b", - msb, lsb, {16{rand_bit}}); - end - - msb = ((i+1)*32-1); - lsb = i*32; - if (my_128_segment !== {32{rand_bit}}) begin - $display("%%Error:(v): bidir_bus_128_io is wrong"); - $display("Error:(v):Should be bidir_bus_128_io[%0d:%0d] = %b, was = %b", - msb, lsb, {32{rand_bit}}, my_128_segment); - error_cnt++; - end - else - begin - $display("Info:(v): Pass: bidir_bus_128_io[%0d:%0d] = %b", - msb, lsb, {32{rand_bit}}); - end - end - end - end - end + else + begin + $display("Info:(v): Pass: bidir_bus_128_io[%0d:%0d] = %b", + msb, lsb, {32{rand_bit}}); + end + end + end + end + end endtask // Connects to top level t_sub_io - t_sub_io - ( - .my_io (sub_io), - .drv_en (drv_en[0]), - .op_val (rand_bit) - ); + t_sub_io + ( + .my_io (sub_io), + .drv_en (drv_en[0]), + .op_val (rand_bit) + ); // Does not connect to top-level t_sub_io - t_sub_io_internal - ( - .my_io (internal_sub_io), - .drv_en (drv_en[1]), - .op_val (~rand_bit) - ); + t_sub_io_internal + ( + .my_io (internal_sub_io), + .drv_en (drv_en[1]), + .op_val (~rand_bit) + ); endmodule diff --git a/test_regress/t/t_tri_unconn.v b/test_regress/t/t_tri_unconn.v index c1989faac..4cfca1c46 100644 --- a/test_regress/t/t_tri_unconn.v +++ b/test_regress/t/t_tri_unconn.v @@ -5,121 +5,121 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; + integer cyc = 0; - wire one = '1; - wire z0 = 'z; - wire z1 = 'z; - wire z2 = 'z; - wire z3 = 'z; - wire tog = cyc[0]; + wire one = '1; + wire z0 = 'z; + wire z1 = 'z; + wire z2 = 'z; + wire z3 = 'z; + wire tog = cyc[0]; - // verilator lint_off PINMISSING - t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing - t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); - t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); - t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); - t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); - t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect - t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); - t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); - t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); - t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + // verilator lint_off PINMISSING + t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing + t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); + t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); + t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); + t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect + t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); - t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing - t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); - t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); - t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); - t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect - t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); - t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); - t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); - t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); - t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing + t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); + t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); + t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); + t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect + t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); - t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing - t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); - t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); - t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); - t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); - t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); - t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); - t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); - t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); - t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing + t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); + t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); + t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); + t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); - t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing - t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); - t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); - t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); - t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); - t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); - t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); - t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); - t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); - t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); - // verilator lint_on PINMISSING + t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing + t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); + t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); + t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); + t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + // verilator lint_on PINMISSING - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module t_tri0 (line, expval, tn); - input integer line; - input expval; - input tn; // Illegal to be inout; spec requires net connection to any inout - tri0 tn; - wire clk = t.clk; - always @(posedge clk) if (tn !== expval) begin - $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; - end + input integer line; + input expval; + input tn; // Illegal to be inout; spec requires net connection to any inout + tri0 tn; + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end endmodule module t_tri1 (line, expval, tn); - input integer line; - input expval; - input tn; - tri1 tn; - wire clk = t.clk; - always @(posedge clk) if (tn !== expval) begin - $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; - end + input integer line; + input expval; + input tn; + tri1 tn; + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end endmodule module t_tri2 (line, expval, tn); - input integer line; - input expval; - input tn; - pulldown(tn); - wire clk = t.clk; - always @(posedge clk) if (tn !== expval) begin - $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; - end + input integer line; + input expval; + input tn; + pulldown(tn); + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end endmodule module t_tri3 (line, expval, tn); - input integer line; - input expval; - input tn; - pullup(tn); - wire clk = t.clk; - always @(negedge clk) if (tn !== expval) begin - $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; - end + input integer line; + input expval; + input tn; + pullup(tn); + wire clk = t.clk; + always @(negedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end endmodule diff --git a/test_regress/t/t_tri_various.v b/test_regress/t/t_tri_various.v index 7a9b332e7..55ce845b3 100644 --- a/test_regress/t/t_tri_various.v +++ b/test_regress/t/t_tri_various.v @@ -5,9 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - clk + input clk ); - input clk; reg [31:0] state; initial state = 0; @@ -19,52 +18,59 @@ module t ( wire Z11; Test1 test1 ( /*AUTOINST*/ - // Inouts - .Z1 (Z1), - // Inputs - .OE (OE), - .A (A)); + // Inouts + .Z1(Z1), + // Inputs + .OE(OE), + .A(A) + ); Test2 test2 ( /*AUTOINST*/ - // Inouts - .Z2 (Z2), - // Inputs - .OE (OE), - .A (A)); + // Inouts + .Z2(Z2), + // Inputs + .OE(OE), + .A(A) + ); Test3 test3 ( /*AUTOINST*/ - // Inouts - .Z3 (Z3), - // Inputs - .OE (OE), - .A (A)); + // Inouts + .Z3(Z3), + // Inputs + .OE(OE), + .A(A) + ); Test4 test4 ( /*AUTOINST*/ - // Outputs - .Z4 (Z4), - // Inouts - .Z5 (Z5)); + // Outputs + .Z4(Z4), + // Inouts + .Z5(Z5) + ); Test5 test5 ( /*AUTOINST*/ - // Inouts - .Z6 (Z6), - .Z7 (Z7), - .Z8 (Z8), - .Z9 (Z9), - // Inputs - .OE (OE)); + // Inouts + .Z6(Z6), + .Z7(Z7), + .Z8(Z8), + .Z9(Z9), + // Inputs + .OE(OE) + ); Test6 test6 ( /*AUTOINST*/ - // Inouts - .Z10 (Z10[3:0]), - // Inputs - .OE (OE)); + // Inouts + .Z10(Z10[3:0]), + // Inputs + .OE(OE) + ); Test7 test7 ( /*AUTOINST*/ - // Outputs - .Z11 (Z11), - // Inputs - .state (state[2:0])); + // Outputs + .Z11(Z11), + // Inputs + .state(state[2:0]) + ); always @(posedge clk) begin state <= state + 1; diff --git a/test_regress/t/t_type.v b/test_regress/t/t_type.v index 486f1940c..f3153cea5 100644 --- a/test_regress/t/t_type.v +++ b/test_regress/t/t_type.v @@ -6,42 +6,42 @@ module t; - real x; - real y; - var type(x+y) z; - localparam type x_type = type(x); - x_type value; + real x; + real y; + var type (x + y) z; + localparam type x_type = type (x); + x_type value; - initial begin - value = 1.234; - if (value != 1.234) $stop(); - x = 1.2; - y = 2.3; - z = x + y; - if (z != (1.2+2.3)) $stop; - z = type(z)'(22); - if (z != 22.0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + value = 1.234; + if (value != 1.234) $stop(); + x = 1.2; + y = 2.3; + z = x + y; + if (z != (1.2 + 2.3)) $stop; + z = type (z)'(22); + if (z != 22.0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - localparam type x_minus_y_type = type(x-y); - sub_real #(.the_type (x_minus_y_type)) the_sub_real_1(); - sub_real #(.the_type (type(x-y))) the_sub_real_2(); - localparam type type1 = type(x*y); - type1 type1_var; - localparam type type2 = type(type1_var/y); - sub_real #(.the_type (type2)) the_sub_real_3(); + localparam type x_minus_y_type = type (x - y); + sub_real #(.the_type(x_minus_y_type)) the_sub_real_1 (); + sub_real #(.the_type(type (x - y))) the_sub_real_2 (); + localparam type type1 = type (x * y); + type1 type1_var; + localparam type type2 = type (type1_var / y); + sub_real #(.the_type(type2)) the_sub_real_3 (); endmodule module sub_real #( parameter type the_type = bit ) (); - the_type the_value; + the_type the_value; - initial begin - the_value = 4.567; - if (the_value != 4.567) $stop(); - end + initial begin + the_value = 4.567; + if (the_value != 4.567) $stop(); + end endmodule diff --git a/test_regress/t/t_type_array.v b/test_regress/t/t_type_array.v index ad29322c2..fb73f237c 100644 --- a/test_regress/t/t_type_array.v +++ b/test_regress/t/t_type_array.v @@ -6,17 +6,17 @@ module t; - typedef int arr_t [5]; - arr_t arr; - localparam type arr_type = type(arr); - arr_type arr_prime; + typedef int arr_t[5]; + arr_t arr; + localparam type arr_type = type (arr); + arr_type arr_prime; - initial begin - arr[3] = 123; - arr_prime = arr; - if (arr_prime[3] != 123) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + arr[3] = 123; + arr_prime = arr; + if (arr_prime[3] != 123) $stop(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_type_compare.v b/test_regress/t/t_type_compare.v index 49b519a18..28b555907 100644 --- a/test_regress/t/t_type_compare.v +++ b/test_regress/t/t_type_compare.v @@ -9,60 +9,60 @@ endmodule module t; - int case_ok; + int case_ok; - Sub #(.T(int)) sub(); + Sub #(.T(int)) sub(); - typedef logic [12:0] logic12_t; + typedef logic [12:0] logic12_t; - // Generate if - if (type(logic[12:0]) !== type(logic[12:0])) initial $stop; - if (type(logic[12:0]) != type(logic12_t)) initial $stop; - if (type(logic[12:0]) !== type(logic12_t)) initial $stop; - if (type(logic[22:0]) == type(logic12_t)) initial $stop; - if (type(logic[22:0]) === type(logic12_t)) initial $stop; - // Generate case - case (type(real)) - type(int): initial $stop; - type(real): ; - default: initial $stop; - endcase + // Generate if + if (type(logic[12:0]) !== type(logic[12:0])) initial $stop; + if (type(logic[12:0]) != type(logic12_t)) initial $stop; + if (type(logic[12:0]) !== type(logic12_t)) initial $stop; + if (type(logic[22:0]) == type(logic12_t)) initial $stop; + if (type(logic[22:0]) === type(logic12_t)) initial $stop; + // Generate case + case (type(real)) + type(int): initial $stop; + type(real): ; + default: initial $stop; + endcase - initial begin - if (type(real) == type(logic[12:0])) $stop; - if (type(real) === type(logic[12:0])) $stop; - if (type(real) != type(real)) $stop; - if (type(real) !== type(real)) $stop; - if (type(logic[12:0]) !== type(logic[12:0])) $stop; - if (type(logic[12:0]) != type(logic12_t)) $stop; - if (type(logic[12:0]) !== type(logic12_t)) $stop; - if (type(logic[22:0]) == type(logic12_t)) $stop; - if (type(logic[22:0]) === type(logic12_t)) $stop; + initial begin + if (type(real) == type(logic[12:0])) $stop; + if (type(real) === type(logic[12:0])) $stop; + if (type(real) != type(real)) $stop; + if (type(real) !== type(real)) $stop; + if (type(logic[12:0]) !== type(logic[12:0])) $stop; + if (type(logic[12:0]) != type(logic12_t)) $stop; + if (type(logic[12:0]) !== type(logic12_t)) $stop; + if (type(logic[22:0]) == type(logic12_t)) $stop; + if (type(logic[22:0]) === type(logic12_t)) $stop; - // Item selected - case (type(real)) - type(real): case_ok = 1; - type(int): $stop; - type(chandle): $stop; - default: $stop; - endcase - if (case_ok != 1) $stop; + // Item selected + case (type(real)) + type(real): case_ok = 1; + type(int): $stop; + type(chandle): $stop; + default: $stop; + endcase + if (case_ok != 1) $stop; - // Default selected - case (type(real)) - type(int): $stop; - default: case_ok = 2; - endcase - if (case_ok != 2) $stop; + // Default selected + case (type(real)) + type(int): $stop; + default: case_ok = 2; + endcase + if (case_ok != 2) $stop; - // No body selected - case (type(real)) - type(int): $stop; - endcase - if (case_ok != 2) $stop; + // No body selected + case (type(real)) + type(int): $stop; + endcase + if (case_ok != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_type_compare_bad.out b/test_regress/t/t_type_compare_bad.out index f8b2fafaa..47353b6ae 100644 --- a/test_regress/t/t_type_compare_bad.out +++ b/test_regress/t/t_type_compare_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_type_compare_bad.v:12:9: Case(type) statement requires items that have type() items +%Error: t/t_type_compare_bad.v:12:7: Case(type) statement requires items that have type() items : ... note: In instance 't' - 12 | 1: $stop; - | ^ + 12 | 1: $stop; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_type_compare_bad.v b/test_regress/t/t_type_compare_bad.v index 01a01402b..90598c63b 100644 --- a/test_regress/t/t_type_compare_bad.v +++ b/test_regress/t/t_type_compare_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - // Syntax error, so not checking: if (type(real) == 1)) $stop; // Bad + initial begin + // Syntax error, so not checking: if (type(real) == 1)) $stop; // Bad - case (type(real)) - 1: $stop; // Bad - default: $finish; - endcase + case (type(real)) + 1: $stop; // Bad + default: $finish; + endcase - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_type_match.v b/test_regress/t/t_type_match.v index c792bbdf5..e24d9e970 100644 --- a/test_regress/t/t_type_match.v +++ b/test_regress/t/t_type_match.v @@ -9,70 +9,66 @@ // SPDX-FileCopyrightText: 2024 Pawel Jewstafjew // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - logic a; - logic d; + logic a; + logic d; - top i_top(.*); + top i_top (.*); - integer cnt; - initial cnt=1; + integer cnt; + initial cnt = 1; - always @ (posedge clk) - begin - cnt <= cnt + 1; + always @(posedge clk) begin + cnt <= cnt + 1; - a <= cnt[0]; - $display("%d %d %d", cnt, a, d); - if (d != a) - $stop; + a <= cnt[0]; + $display("%d %d %d", cnt, a, d); + if (d != a) $stop; - if (cnt == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cnt == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module top ( - input a, - output d - ); + input a, + output d +); - logic b; - logic c[1]; - assign c[0] = b; + logic b; + logic c[1]; + assign c[0] = b; - unit i_unit - ( - .a (a), - .b (b), - .c (c), - .d (d) - ); + unit i_unit ( + .a(a), + .b(b), + .c(c), + .d(d) + ); endmodule -module unit - ( - input a, - input c[1], - output logic b, - output logic d - ); +module unit ( + input a, + input c[1], + output logic b, + output logic d +); - // no_inline required to prevent optimising away the interesing part ... - /*verilator no_inline_module*/ + // no_inline required to prevent optimising away the interesing part ... + /*verilator no_inline_module*/ - always_comb - begin - b = a; - d = b && c[0]; - end + always_comb begin + b = a; + d = b && c[0]; + end endmodule diff --git a/test_regress/t/t_type_non_type.v b/test_regress/t/t_type_non_type.v index 22137ddb0..d21a8f3ce 100644 --- a/test_regress/t/t_type_non_type.v +++ b/test_regress/t/t_type_non_type.v @@ -8,30 +8,30 @@ class Cls; endclass package Pkg; - // Issue #2956 - typedef string STYPE; - typedef string line; - task automatic testf; - inout STYPE line; - endtask + // Issue #2956 + typedef string STYPE; + typedef string line; + task automatic testf; + inout STYPE line; + endtask endpackage module t; - localparam type T = Cls; + localparam type T = Cls; - // Issue #2412 - typedef T this_thing; // this_thing now a type + // Issue #2412 + typedef T this_thing; // this_thing now a type - function T newer(); - T this_thing; // this_thing now a class reference - this_thing = new; - return this_thing; - endfunction + function T newer(); + T this_thing; // this_thing now a class reference + this_thing = new; + return this_thing; + endfunction - initial begin - Cls c; - c = newer(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c = newer(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index 89e2b51d0..f8509ec7c 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -5,146 +5,135 @@ // SPDX-License-Identifier: CC0-1.0 package some_package; - typedef logic [15:0] two_bytes_t; + typedef logic [15:0] two_bytes_t; endpackage -module foo - #(parameter type bar = logic) - (output int bar_size); +module foo #( + parameter type bar = logic +) ( + output int bar_size +); - localparam baz = $bits(bar); + localparam baz = $bits(bar); - assign bar_size = baz; + assign bar_size = baz; endmodule -module foo_wrapper - #(parameter bar_bits = 9) - (output int bar_size); +module foo_wrapper #( + parameter bar_bits = 9 +) ( + output int bar_size +); - foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size)); + foo #(.bar(logic [bar_bits-1:0])) foo_inst (.bar_size(bar_size)); endmodule module t; - logic [7:0] qux1; - int bar_size1; + logic [7:0] qux1; + int bar_size1; - foo #(.bar (logic [ $bits(qux1) - 1 : 0])) - foo_inst1 (.bar_size (bar_size1)); + foo #(.bar(logic [$bits(qux1) - 1 : 0])) foo_inst1 (.bar_size(bar_size1)); - logic [7:0] qux2; - int bar_size2; + logic [7:0] qux2; + int bar_size2; - foo #(.bar (logic [ $bits(qux2) - 1 : 0])) - foo_inst2 (.bar_size (bar_size2)); + foo #(.bar(logic [$bits(qux2) - 1 : 0])) foo_inst2 (.bar_size(bar_size2)); - logic [7:0] qux3; - int bar_size3; + logic [7:0] qux3; + int bar_size3; - foo #(.bar (logic [ $bits(qux3) - 1 : 0])) - foo_inst3 (.bar_size (bar_size3)); + foo #(.bar(logic [$bits(qux3) - 1 : 0])) foo_inst3 (.bar_size(bar_size3)); - typedef struct packed { - logic foo; - logic bar; - } some_struct_t; - int bar_size4; + typedef struct packed { + logic foo; + logic bar; + } some_struct_t; + int bar_size4; - foo #(.bar (some_struct_t [7:0])) - foo_inst4 (.bar_size (bar_size4)); + foo #(.bar(some_struct_t[7:0])) foo_inst4 (.bar_size(bar_size4)); - int bar_size5; + int bar_size5; - foo #(.bar (some_struct_t [2:0] [5:0])) - foo_inst5 (.bar_size (bar_size5)); + foo #(.bar(some_struct_t[2:0][5:0])) foo_inst5 (.bar_size(bar_size5)); - int bar_size6; + int bar_size6; - foo #(.bar (some_package::two_bytes_t [4-1:0])) - foo_inst6 (.bar_size (bar_size6)); + foo #(.bar(some_package::two_bytes_t[4-1:0])) foo_inst6 (.bar_size(bar_size6)); - localparam bar_bits = 13; - int bar_size_wrapper; + localparam bar_bits = 13; + int bar_size_wrapper; - foo_wrapper #(.bar_bits (bar_bits)) - foo_wrapper_inst (.bar_size (bar_size_wrapper)); + foo_wrapper #(.bar_bits(bar_bits)) foo_wrapper_inst (.bar_size(bar_size_wrapper)); - initial begin - if ($bits(qux1) != foo_inst1.baz) begin - $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", - $bits(qux1), foo_inst1.baz); + initial begin + if ($bits(qux1) != foo_inst1.baz) begin + $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", $bits(qux1), foo_inst1.baz); + $stop(); + end + if ($bits(qux2) != foo_inst2.baz) begin + $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", $bits(qux2), foo_inst2.baz); + $stop(); + end + if ($bits(qux3) != foo_inst3.baz) begin + $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", $bits(qux3), foo_inst3.baz); + $stop(); + end + if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin + $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", bar_bits, + foo_wrapper_inst.foo_inst.baz); + $stop(); + end + if (bar_size1 != $bits(qux1)) begin + $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", bar_size1, $bits(qux1)); + $stop(); + end + if (bar_size2 != $bits(qux2)) begin + $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", bar_size2, $bits(qux2)); + $stop(); + end + if (bar_size3 != $bits(qux3)) begin + $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", bar_size3, $bits(qux3)); + $stop(); + end + if (bar_size4 != $bits(some_struct_t) * 8) begin + $display("%m: bar_size4 != bits of some_struct_t * 8 (%0d, %0d)", bar_size4, $bits + (some_struct_t) * 8); + $stop(); + end + if (bar_size5 != $bits(some_struct_t) * 3 * 6) begin + $display("%m: bar_size5 != bits of some_struct_t * 3 * 6 (%0d, %0d)", bar_size5, $bits + (some_struct_t) * 3 * 6); + $stop(); + end + if (bar_size6 != $bits(some_package::two_bytes_t) * 4) begin + $display("%m: bar_size6 != bits of some_package::two_bytes_t * 4 (%0d, %0d)", bar_size6, + $bits(some_package::two_bytes_t) * 4); + $stop(); + end + if (bar_size_wrapper != bar_bits) begin + $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", bar_size_wrapper, bar_bits); + $stop(); + end + end + + genvar m; + generate + for (m = 1; m <= 8; m += 1) begin : gen_m + initial begin + if (m != foo_inst.baz) begin + $display("%m: m != bits of foo_inst.baz (%0d, %0d)", m, foo_inst.baz); $stop(); - end - if ($bits(qux2) != foo_inst2.baz) begin - $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", - $bits(qux2), foo_inst2.baz); - $stop(); - end - if ($bits(qux3) != foo_inst3.baz) begin - $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", - $bits(qux3), foo_inst3.baz); - $stop(); - end - if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin - $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", - bar_bits, foo_wrapper_inst.foo_inst.baz); - $stop(); - end - if (bar_size1 != $bits(qux1)) begin - $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", - bar_size1, $bits(qux1)); - $stop(); + end end - if (bar_size2 != $bits(qux2)) begin - $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", - bar_size2, $bits(qux2)); - $stop(); - end - if (bar_size3 != $bits(qux3)) begin - $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", - bar_size3, $bits(qux3)); - $stop(); - end - if (bar_size4 != $bits(some_struct_t)*8) begin - $display("%m: bar_size4 != bits of some_struct_t * 8 (%0d, %0d)", - bar_size4, $bits(some_struct_t) * 8); - $stop(); - end - if (bar_size5 != $bits(some_struct_t)*3*6) begin - $display("%m: bar_size5 != bits of some_struct_t * 3 * 6 (%0d, %0d)", - bar_size5, $bits(some_struct_t) * 3 * 6); - $stop(); - end - if (bar_size6 != $bits(some_package::two_bytes_t)*4) begin - $display("%m: bar_size6 != bits of some_package::two_bytes_t * 4 (%0d, %0d)", - bar_size6, $bits(some_package::two_bytes_t) * 4); - $stop(); - end - if (bar_size_wrapper != bar_bits) begin - $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", - bar_size_wrapper, bar_bits); - $stop(); - end - end - genvar m; - generate - for (m = 1; m <= 8; m+=1) begin : gen_m - initial begin - if (m != foo_inst.baz) begin - $display("%m: m != bits of foo_inst.baz (%0d, %0d)", - m, foo_inst.baz); - $stop(); - end - end + foo #(.bar(logic [m-1:0])) foo_inst (.bar_size()); + end + endgenerate - foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); - end - endgenerate - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_type_param_circ_bad.out b/test_regress/t/t_type_param_circ_bad.out index 58dc74892..4ecd3047f 100644 --- a/test_regress/t/t_type_param_circ_bad.out +++ b/test_regress/t/t_type_param_circ_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_type_param_circ_bad.v:14:22: Recursive type definition +%Error: t/t_type_param_circ_bad.v:15:20: Recursive type definition : ... note: In instance 't' - t/t_type_param_circ_bad.v:14:22: ... Type chain: PARAMTYPEDTYPE 'SZ' - 14 | # (parameter type SZ = SZ) - | ^~ - t/t_type_param_circ_bad.v:14:27: ... Type chain: REFDTYPE 'SZ' - 14 | # (parameter type SZ = SZ) - | ^~ + t/t_type_param_circ_bad.v:15:20: ... Type chain: PARAMTYPEDTYPE 'SZ' + 15 | parameter type SZ = SZ + | ^~ + t/t_type_param_circ_bad.v:15:25: ... Type chain: REFDTYPE 'SZ' + 15 | parameter type SZ = SZ + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_type_param_circ_bad.v b/test_regress/t/t_type_param_circ_bad.v index 9def0a114..4437150df 100644 --- a/test_regress/t/t_type_param_circ_bad.v +++ b/test_regress/t/t_type_param_circ_bad.v @@ -5,16 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - parameter [7:0] WIDTH = 8; - typedef logic [WIDTH-1:0] SZ; -endpackage // pkg + parameter [7:0] WIDTH = 8; + typedef logic [WIDTH-1:0] SZ; +endpackage // pkg module t import pkg::*; - # (parameter type SZ = SZ) - (input SZ i, - output SZ o); +#( + parameter type SZ = SZ +) ( + input SZ i, + output SZ o +); - always_comb o = i; + always_comb o = i; endmodule diff --git a/test_regress/t/t_typedef_array.v b/test_regress/t/t_typedef_array.v index f640d1a01..4b582a6ac 100644 --- a/test_regress/t/t_typedef_array.v +++ b/test_regress/t/t_typedef_array.v @@ -7,20 +7,20 @@ typedef logic logic_alias_t; module t; - logic_alias_t [6:1] signal; - // verilator lint_off ASCRANGE - logic_alias_t [1:6] signal2; - // verilator lint_on ASCRANGE + logic_alias_t [6:1] signal; + // verilator lint_off ASCRANGE + logic_alias_t [1:6] signal2; + // verilator lint_on ASCRANGE - initial begin - signal[6:1] = 'b100001; - signal[3] = 'b1; - signal2[1:6] = 'b100001; - signal2[4] = 'b1; + initial begin + signal[6:1] = 'b100001; + signal[3] = 'b1; + signal2[1:6] = 'b100001; + signal2[4] = 'b1; - if (signal != 'b100101) $stop; - if (signal2 != 'b100101) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (signal != 'b100101) $stop; + if (signal2 != 'b100101) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_typedef_consistency_0.v b/test_regress/t/t_typedef_consistency_0.v index e8b1adad7..c9ec4e070 100644 --- a/test_regress/t/t_typedef_consistency_0.v +++ b/test_regress/t/t_typedef_consistency_0.v @@ -5,32 +5,32 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef logic l; + typedef logic l; endpackage module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - wire logic o_logic; - // Using 'pkg::l' instead of 'logic' should make no difference - wire pkg::l o_alias; + wire logic o_logic; + // Using 'pkg::l' instead of 'logic' should make no difference + wire pkg::l o_alias; - sub sub_logic(o_logic); - sub sub_alias(o_alias); + sub sub_logic(o_logic); + sub sub_alias(o_alias); - assign o_logic = clk; - assign o_alias = clk; + assign o_logic = clk; + assign o_alias = clk; - always @(posedge clk) begin - $display("o_logic: %b o_alias: %b", o_logic, o_alias); - // Whatever the answer is, it should be the same - if (o_logic !== o_alias) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $display("o_logic: %b o_alias: %b", o_logic, o_alias); + // Whatever the answer is, it should be the same + if (o_logic !== o_alias) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_typedef_fwd_nested.v b/test_regress/t/t_typedef_fwd_nested.v index 7c330cbba..6628ce31c 100644 --- a/test_regress/t/t_typedef_fwd_nested.v +++ b/test_regress/t/t_typedef_fwd_nested.v @@ -7,42 +7,49 @@ typedef class Bar; typedef Bar Baz; typedef class Quux; -typedef Quux #(16, 32) Quux_t; +typedef Quux#(16, 32) Quux_t; typedef Quux_t Quuux_t; module t; - initial begin - Bar::Qux::boo(1); - Baz::Qux::boo(1); - Quux_t::Qux::boo(1); - Quuux_t::Qux::boo(1); - if (!Bar::Qux::finish) $stop; - if (!Quux_t::Qux::finish) $stop; - if (!Quuux_t::Qux::finish) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Bar::Qux::boo(1); + Baz::Qux::boo(1); + Quux_t::Qux::boo(1); + Quuux_t::Qux::boo(1); + if (!Bar::Qux::finish) $stop; + if (!Quux_t::Qux::finish) $stop; + if (!Quuux_t::Qux::finish) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -class Foo #(type T); - static logic finish = 0; - static function void boo(input logic rec); - if (rec) Bar::Qux::boo(0); - finish = 1; - endfunction +class Foo #( + type T +); + static logic finish = 0; + static function void boo(input logic rec); + if (rec) Bar::Qux::boo(0); + finish = 1; + endfunction endclass -class Goo #(type T); - function void goo(); - T::Qux::boo(1); - endfunction +class Goo #( + type T +); + function void goo(); + T::Qux::boo(1); + endfunction endclass class Bar; - typedef Foo#(Bar) Qux; + typedef Foo#(Bar) Qux; endclass -class Quux #(PARA_A = 1, PARA_B = 2); - typedef Quux #(PARA_A, PARA_B) this_t; - typedef Foo#(this_t) Qux; +class Quux #( + PARA_A = 1, + PARA_B = 2 +); + typedef Quux#(PARA_A, PARA_B) this_t; + typedef Foo#(this_t) Qux; endclass diff --git a/test_regress/t/t_typedef_no_bad.out b/test_regress/t/t_typedef_no_bad.out index 51f0b9eb3..23b07ff82 100644 --- a/test_regress/t/t_typedef_no_bad.out +++ b/test_regress/t/t_typedef_no_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef/interface: 'sometype' - 10 | sometype p; - | ^~~~~~~~ +%Error: t/t_typedef_no_bad.v:10:3: Can't find typedef/interface: 'sometype' + 10 | sometype p; + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_typedef_no_bad.v b/test_regress/t/t_typedef_no_bad.v index b6fe352db..50dbd75f1 100644 --- a/test_regress/t/t_typedef_no_bad.v +++ b/test_regress/t/t_typedef_no_bad.v @@ -7,5 +7,5 @@ typedef sometype; module t; - sometype p; + sometype p; endmodule diff --git a/test_regress/t/t_typedef_param.v b/test_regress/t/t_typedef_param.v index f39c8522a..00f5a38fc 100644 --- a/test_regress/t/t_typedef_param.v +++ b/test_regress/t/t_typedef_param.v @@ -6,103 +6,106 @@ typedef reg [2:0] threeansi_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [2:0] in = crc[2:0]; + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; - localparam type three_t = reg [2:0]; + localparam type three_t = reg [2:0]; - three_t outna; - three_t outa; + three_t outna; + three_t outa; - TestNonAnsi #( .p_t (reg [2:0]) ) - test (// Outputs - .out (outna), - /*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[2:0])); + TestNonAnsi #( + .p_t(reg [2:0]) + ) test ( // Outputs + .out(outna), + /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[2:0]) + ); - TestAnsi #( .p_t (reg [2:0])) - testa (// Outputs - .out (outa), - /*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[2:0])); + TestAnsi #( + .p_t(reg [2:0]) + ) testa ( // Outputs + .out(outa), + /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in[2:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {57'h0, outna, 1'b0, outa}; + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, outna, 1'b0, outa}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h018decfea0a8828a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h018decfea0a8828a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module TestNonAnsi (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); - /*verilator hier_block*/ - parameter type p_t = shortint; +module TestNonAnsi ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); + /*verilator hier_block*/ + parameter type p_t = shortint; - input clk; - input p_t in; - output p_t out; + input clk; + input p_t in; + output p_t out; - always @(posedge clk) begin - out <= ~in; - end + always @(posedge clk) begin + out <= ~in; + end endmodule -module TestAnsi - #( parameter type p_t = shortint ) - ( +module TestAnsi #( + parameter type p_t = shortint +) ( input clk, input p_t in, output p_t out - ); - /*verilator hier_block*/ - always @(posedge clk) begin - out <= ~in; - end +); + /*verilator hier_block*/ + always @(posedge clk) begin + out <= ~in; + end endmodule // Local Variables: diff --git a/test_regress/t/t_typedef_port.v b/test_regress/t/t_typedef_port.v index 4f0d0bce2..e50ad8d81 100644 --- a/test_regress/t/t_typedef_port.v +++ b/test_regress/t/t_typedef_port.v @@ -6,100 +6,101 @@ typedef reg [2:0] threeansi_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef reg [2:0] three_t; + typedef reg [2:0] three_t; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [2:0] in = crc[2:0]; + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - threeansi_t outa; // From testa of TestAnsi.v - three_t outna; // From test of TestNonAnsi.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + threeansi_t outa; // From testa of TestAnsi.v + three_t outna; // From test of TestNonAnsi.v + // End of automatics - TestNonAnsi test (// Outputs - .out (outna), - /*AUTOINST*/ - // Inputs - .clk (clk), - .in (in)); + TestNonAnsi test ( // Outputs + .out(outna), + /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in) + ); - TestAnsi testa (// Outputs - .out (outa), - /*AUTOINST*/ - // Inputs - .clk (clk), - .in (in)); + TestAnsi testa ( // Outputs + .out(outa), + /*AUTOINST*/ + // Inputs + .clk(clk), + .in(in) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {57'h0, outna, 1'b0, outa}; + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, outna, 1'b0, outa}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h018decfea0a8828a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h018decfea0a8828a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module TestNonAnsi (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); - typedef reg [2:0] three_t; +module TestNonAnsi ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); + typedef reg [2:0] three_t; - input clk; - input three_t in; - output three_t out; + input clk; + input three_t in; + output three_t out; - always @(posedge clk) begin - out <= ~in; - end + always @(posedge clk) begin + out <= ~in; + end endmodule module TestAnsi ( - input clk, - input threeansi_t in, - output threeansi_t out - ); - always @(posedge clk) begin - out <= ~in; - end + input clk, + input threeansi_t in, + output threeansi_t out +); + always @(posedge clk) begin + out <= ~in; + end endmodule // Local Variables: diff --git a/test_regress/t/t_typedef_signed.v b/test_regress/t/t_typedef_signed.v index 9d2052814..7d72f8f38 100644 --- a/test_regress/t/t_typedef_signed.v +++ b/test_regress/t/t_typedef_signed.v @@ -8,82 +8,83 @@ typedef logic signed [34:0] rc_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [34:0] rc = crc[34:0]; + // Take CRC data and apply to testblock inputs + wire [34:0] rc = crc[34:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic o; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic o; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .o (o), - // Inputs - .rc (rc), - .clk (clk)); + Test test ( /*AUTOINST*/ + // Outputs + .o(o), + // Inputs + .rc(rc), + .clk(clk) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'h0, o}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, o}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h7211d24a17b25ec9 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h7211d24a17b25ec9 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test( output logic o, - input rc_t rc, - input logic clk); +module Test ( + output logic o, + input rc_t rc, + input logic clk +); - localparam RATIO = 2; + localparam RATIO = 2; - rc_t rc_d[RATIO:1]; + rc_t rc_d[RATIO:1]; - always_ff @(posedge clk) begin - integer k; + always_ff @(posedge clk) begin + integer k; - rc_d[1] <= rc; + rc_d[1] <= rc; - for( k=2; k"); // Some have just "enum " + `printtype( + A::X, + "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::"); // Some have just "enum " - `printtype(AB_t, "struct{bit A;bit B;}"); + `printtype(AB_t, "struct{bit A;bit B;}"); - `printtype(AB, "struct{bit A;bit B;}top.AB_t$[0:9]"); - `printtype(UAB_t, "union{bit A;bit B;}"); + `printtype(AB, "struct{bit A;bit B;}top.AB_t$[0:9]"); + `printtype(UAB_t, "union{bit A;bit B;}"); - `printtype(Cls, "class{}t.Cls "); + `printtype(Cls, "class{}t.Cls "); - $display; - $write("*-* All Finished *-*\n"); - $finish; - end + $display; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_typename_min.v b/test_regress/t/t_typename_min.v index eb02ed5dd..c11e6f65e 100644 --- a/test_regress/t/t_typename_min.v +++ b/test_regress/t/t_typename_min.v @@ -4,32 +4,34 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int unsigned array[3] = {1, 2, 3}; - int unsigned queue[$] = '{1, 2, 3}; - int unsigned q[$]; - int unsigned assoc[string] = '{"1":1, "2":2, "3":3}; - string s; - initial begin - s = $typename(array.min); - `checks(s, "int$[$]"); - s = $sformatf("%p", array.min); - `checks(s, "'{'h1}"); + int unsigned array[3] = {1, 2, 3}; + int unsigned queue[$] = '{1, 2, 3}; + int unsigned q[$]; + int unsigned assoc[string] = '{"1": 1, "2": 2, "3": 3}; + string s; + initial begin + s = $typename(array.min); + `checks(s, "int$[$]"); + s = $sformatf("%p", array.min); + `checks(s, "'{'h1}"); - s = $typename(queue.min); - `checks(s, "int$[$]"); - s = $sformatf("%p", queue.min); - `checks(s, "'{'h1}"); + s = $typename(queue.min); + `checks(s, "int$[$]"); + s = $sformatf("%p", queue.min); + `checks(s, "'{'h1}"); - s = $typename(assoc.min); - `checks(s, "int$[$]"); - s = $sformatf("%p", assoc.min); - `checks(s, "'{'h1}"); + s = $typename(assoc.min); + `checks(s, "int$[$]"); + s = $sformatf("%p", assoc.min); + `checks(s, "'{'h1}"); - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index 6e235b3c5..d7a3318fe 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -1,6 +1,6 @@ -%Warning-PINMISSING: t/t_udp_bad.v:10:10: Instance has missing pin: 'c_bad' - 10 | udp_x x (a, b); - | ^ +%Warning-PINMISSING: t/t_udp_bad.v:10:9: Instance has missing pin: 'c_bad' + 10 | udp_x x (a, b); + | ^ t/t_udp_bad.v:14:28: ... Location of port declaration 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ @@ -10,17 +10,17 @@ 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' - 10 | udp_x x (a, b); - | ^ +%Error-PINNOTFOUND: t/t_udp_bad.v:10:12: Pin not found: '__pinNumber1' + 10 | udp_x x (a, b); + | ^ : ... Location of instance's primitive declaration 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest -%Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules - 17 | output c_bad; - | ^~~~~ -%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules - 15 | tri a_bad; - | ^~~~~ +%Error: t/t_udp_bad.v:17:10: Multiple outputs not allowed in udp modules + 17 | output c_bad; + | ^~~~~ +%Error: t/t_udp_bad.v:15:8: Only inputs and outputs are allowed in udp modules + 15 | tri a_bad; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad.v b/test_regress/t/t_udp_bad.v index 8a9cc5b10..35a875fdf 100644 --- a/test_regress/t/t_udp_bad.v +++ b/test_regress/t/t_udp_bad.v @@ -6,18 +6,18 @@ module t; - wire a, b; - udp_x x (a, b); + wire a, b; + udp_x x (a, b); endmodule primitive udp_x (a_bad, b, c_bad); - tri a_bad; - output b; - output c_bad; - table - //a b - 0 : 1; - 1 : 0; - endtable + tri a_bad; + output b; + output c_bad; + table + //a b + 0 : 1; + 1 : 0; + endtable endprimitive diff --git a/test_regress/t/t_udp_bad_comb_trigger.out b/test_regress/t/t_udp_bad_comb_trigger.out index cdd792653..0d6380189 100644 --- a/test_regress/t/t_udp_bad_comb_trigger.out +++ b/test_regress/t/t_udp_bad_comb_trigger.out @@ -1,6 +1,6 @@ -%Error: t/t_udp_bad_comb_trigger.v:14:10: There should not be a edge trigger for combinational UDP table line - : ... note: In instance 'top' - 14 | (01) 1 0 : 0; - | ^ +%Error: t/t_udp_bad_comb_trigger.v:14:6: There should not be a edge trigger for combinational UDP table line + : ... note: In instance 'top' + 14 | (01) 1 0 : 0; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad_comb_trigger.v b/test_regress/t/t_udp_bad_comb_trigger.v index 129ed99f5..9e124b7b5 100644 --- a/test_regress/t/t_udp_bad_comb_trigger.v +++ b/test_regress/t/t_udp_bad_comb_trigger.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); -output dout; -input a, b, c; + output dout; + input a, b, c; - table - x 0 1 : 1; - 0 ? 1 : 1; - (01) 1 0 : 0; - 1 1 ? : 1; - 1 0 0 : 0; - 0 0 0 : 1; + table + x 0 1 : 1; + 0 ? 1 : 1; + (01) 1 0 : 0; + 1 1 ? : 1; + 1 0 0 : 0; + 0 0 0 : 1; - endtable + endtable endprimitive module top (o, a, b, c); - output o; - input a, b, c; - t_gate(o, a, b, c); + output o; + input a, b, c; + t_gate(o, a, b, c); endmodule diff --git a/test_regress/t/t_udp_bad_first_input.out b/test_regress/t/t_udp_bad_first_input.out index 6dec0adc5..a4563152b 100644 --- a/test_regress/t/t_udp_bad_first_input.out +++ b/test_regress/t/t_udp_bad_first_input.out @@ -1,6 +1,6 @@ -%Error: t/t_udp_bad_first_input.v:8:7: First UDP port must be the output port +%Error: t/t_udp_bad_first_input.v:8:9: First UDP port must be the output port : ... note: In instance 'top' - 8 | input a, b, c; - | ^ + 8 | input a, b, c; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad_first_input.v b/test_regress/t/t_udp_bad_first_input.v index b6ff5b160..1ba9381b9 100644 --- a/test_regress/t/t_udp_bad_first_input.v +++ b/test_regress/t/t_udp_bad_first_input.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 primitive t_gate(a, b, c, dout); -input a, b, c; -output dout; + input a, b, c; + output dout; - table - x 0 1 : 1; - 0 ? 1 : 1; - 0 1 0 : 0; - 1 1 ? : 1; - 1 0 0 : 0; - 0 0 0 : 1; + table + x 0 1 : 1; + 0 ? 1 : 1; + 0 1 0 : 0; + 1 1 ? : 1; + 1 0 0 : 0; + 0 0 0 : 1; - endtable + endtable endprimitive module top (a, b, c, o); - input a, b, c; - output o; - t_gate(a, b, c, o); + input a, b, c; + output o; + t_gate(a, b, c, o); endmodule diff --git a/test_regress/t/t_udp_bad_illegal_output.out b/test_regress/t/t_udp_bad_illegal_output.out index a6ee8b651..fc1e3e3ca 100644 --- a/test_regress/t/t_udp_bad_illegal_output.out +++ b/test_regress/t/t_udp_bad_illegal_output.out @@ -1,30 +1,30 @@ -%Error: t/t_udp_bad_illegal_output.v:9:8: For sequential UDP, the output must be of 'reg' data type - : ... note: In instance 'top' - 9 | output dout; - | ^~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_udp_bad_illegal_output.v:16:22: Illegal value for sequential UDP line output - : ... note: In instance 'top' - 16 | 1 1 ? : ?: *; - | ^ -%Error: t/t_udp_bad_illegal_output.v:17:11: There can be only one edge trigger signal - : ... note: In instance 'top' - 17 | f r 0 : ?: 0; - | ^ -%Error: t/t_udp_bad_illegal_output.v:18:22: Illegal value for sequential UDP line output - : ... note: In instance 'top' - 18 | 0 0 0 : ?: *; - | ^ -%Error: t/t_udp_bad_illegal_output.v:29:9: There should not be a edge trigger for combinational UDP table line +%Error: t/t_udp_bad_illegal_output.v:9:10: For sequential UDP, the output must be of 'reg' data type : ... note: In instance 'top' - 29 | r ? 1 : 1; - | ^ -%Error: t/t_udp_bad_illegal_output.v:31:20: Illegal value for combinational UDP line output + 9 | output dout; + | ^~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_udp_bad_illegal_output.v:16:18: Illegal value for sequential UDP line output : ... note: In instance 'top' - 31 | 1 1 ? : *; - | ^ -%Error: t/t_udp_bad_illegal_output.v:33:20: Illegal value for combinational UDP line output + 16 | 1 1 ? : ?: *; + | ^ +%Error: t/t_udp_bad_illegal_output.v:17:7: There can be only one edge trigger signal + : ... note: In instance 'top' + 17 | f r 0 : ?: 0; + | ^ +%Error: t/t_udp_bad_illegal_output.v:18:18: Illegal value for sequential UDP line output : ... note: In instance 'top' - 33 | 0 0 0 : *; - | ^ + 18 | 0 0 0 : ?: *; + | ^ +%Error: t/t_udp_bad_illegal_output.v:29:5: There should not be a edge trigger for combinational UDP table line + : ... note: In instance 'top' + 29 | r ? 1 : 1; + | ^ +%Error: t/t_udp_bad_illegal_output.v:31:16: Illegal value for combinational UDP line output + : ... note: In instance 'top' + 31 | 1 1 ? : *; + | ^ +%Error: t/t_udp_bad_illegal_output.v:33:16: Illegal value for combinational UDP line output + : ... note: In instance 'top' + 33 | 0 0 0 : *; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad_illegal_output.v b/test_regress/t/t_udp_bad_illegal_output.v index af6ee1fe1..b8d41176f 100644 --- a/test_regress/t/t_udp_bad_illegal_output.v +++ b/test_regress/t/t_udp_bad_illegal_output.v @@ -5,39 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 primitive t_gate_comb(dout, a, b, c); -input a, b, c; -output dout; + input a, b, c; + output dout; - table - r 0 1 : ?: 1; - r ? 1 : ?: 1; - r ? 0 : ?: 1; - 0 1 0 : ?: 0; - 1 1 ? : ?: *; - f r 0 : ?: 0; - 0 0 0 : ?: *; + table + r 0 1 : ?: 1; + r ? 1 : ?: 1; + r ? 0 : ?: 1; + 0 1 0 : ?: 0; + 1 1 ? : ?: *; + f r 0 : ?: 0; + 0 0 0 : ?: *; - endtable + endtable endprimitive primitive t_gate_seq(dout, a, b, c); -input a, b, c; -output dout; + input a, b, c; + output dout; - table - x 0 1 : 1; - r ? 1 : 1; - 0 1 0 : 0; - 1 1 ? : *; - 1 0 0 : 0; - 0 0 0 : *; + table + x 0 1 : 1; + r ? 1 : 1; + 0 1 0 : 0; + 1 1 ? : *; + 1 0 0 : 0; + 0 0 0 : *; - endtable + endtable endprimitive module top (a, b, c, o1, o2); - input a, b, c; - output o1, o2; - t_gate_comb(o1, a, b, c); - t_gate_seq(o2, a, b, c); + input a, b, c; + output o1, o2; + t_gate_comb(o1, a, b, c); + t_gate_seq(o2, a, b, c); endmodule diff --git a/test_regress/t/t_udp_bad_input_num.out b/test_regress/t/t_udp_bad_input_num.out index 5051e1738..770f0380c 100644 --- a/test_regress/t/t_udp_bad_input_num.out +++ b/test_regress/t/t_udp_bad_input_num.out @@ -1,6 +1,6 @@ -%Error: t/t_udp_bad_input_num.v:14:9: Incorrect number of input values, expected 3, got 2 +%Error: t/t_udp_bad_input_num.v:14:7: Incorrect number of input values, expected 3, got 2 : ... note: In instance 'top' - 14 | 1 0 : 0; - | ^ + 14 | 1 0 : 0; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad_input_num.v b/test_regress/t/t_udp_bad_input_num.v index 9acb61225..543b491bf 100644 --- a/test_regress/t/t_udp_bad_input_num.v +++ b/test_regress/t/t_udp_bad_input_num.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); -output dout; -input a, b, c; + output dout; + input a, b, c; - table - x 0 1 : 1; - 0 ? 1 : 1; - 1 0 : 0; - 1 1 ? : 1; - 1 0 0 : 0; - 0 0 0 : 1; + table + x 0 1 : 1; + 0 ? 1 : 1; + 1 0 : 0; + 1 1 ? : 1; + 1 0 0 : 0; + 0 0 0 : 1; - endtable + endtable endprimitive module top (a, b, c, o); - input a, b, c; - output o; - t_gate(o, a, b, c); + input a, b, c; + output o; + t_gate(o, a, b, c); endmodule diff --git a/test_regress/t/t_udp_bad_multi_output.out b/test_regress/t/t_udp_bad_multi_output.out index 11dbedd10..97129093a 100644 --- a/test_regress/t/t_udp_bad_multi_output.out +++ b/test_regress/t/t_udp_bad_multi_output.out @@ -1,6 +1,6 @@ -%Error: t/t_udp_bad_multi_output.v:8:15: 2 output ports for UDP table, there must be one output port +%Error: t/t_udp_bad_multi_output.v:8:17: 2 output ports for UDP table, there must be one output port : ... note: In instance 'top' - 8 | output dout1, dout2; - | ^~~~~ + 8 | output dout1, dout2; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad_multi_output.v b/test_regress/t/t_udp_bad_multi_output.v index 296df8726..2ca167121 100644 --- a/test_regress/t/t_udp_bad_multi_output.v +++ b/test_regress/t/t_udp_bad_multi_output.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout1, dout2, a, b, c); -output dout1, dout2; -input a, b, c; + output dout1, dout2; + input a, b, c; - table - x 0 1 : 1; - 0 ? 1 : 1; - 0 1 0 : 0; - 1 1 ? : 1; - 1 0 0 : 0; - 0 0 0 : 1; + table + x 0 1 : 1; + 0 ? 1 : 1; + 0 1 0 : 0; + 1 1 ? : 1; + 1 0 0 : 0; + 0 0 0 : 1; - endtable + endtable endprimitive module top (a, b, c, o1, o2); - input a, b, c; - output o1, o2; - t_gate(o1, o2, a, b, c); + input a, b, c; + output o1, o2; + t_gate(o1, o2, a, b, c); endmodule diff --git a/test_regress/t/t_udp_noname.v b/test_regress/t/t_udp_noname.v index 94128c664..84abb0d46 100644 --- a/test_regress/t/t_udp_noname.v +++ b/test_regress/t/t_udp_noname.v @@ -5,47 +5,47 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - reg a1; - wire a2 = ~a1; - wire o1, o2; - udp (o1, a1); - udp (o2, a2); + reg a1; + wire a2 = ~a1; + wire o1, o2; + udp (o1, a1); + udp (o2, a2); - integer cyc; initial cyc = 0; + integer cyc; initial cyc = 0; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - a1 <= cyc[0]; - if (cyc==0) begin - end - else if (cyc<90) begin - if (o1 != cyc[0]) $stop; - if (o2 != !cyc[0]) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + a1 <= cyc[0]; + if (cyc==0) begin + end + else if (cyc<90) begin + if (o1 != cyc[0]) $stop; + if (o2 != !cyc[0]) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule primitive udp(o,a); - output o; - input a; + output o; + input a; `ifdef verilator - wire o = ~a; + wire o = ~a; `else - table - //o a - 0 : 1; - 1 : 0; - endtable + table + //o a + 0 : 1; + 1 : 0; + endtable `endif endprimitive diff --git a/test_regress/t/t_udp_param_bad.v b/test_regress/t/t_udp_param_bad.v index 37e09e82b..4a11d1c3e 100644 --- a/test_regress/t/t_udp_param_bad.v +++ b/test_regress/t/t_udp_param_bad.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire a, b; - udp i_udp (a, b); + wire a, b; + udp i_udp (a, b); endmodule primitive udp #( - parameter A = 1 + parameter A = 1 ) (o, a); - output o; - input a; - table - //o a - 0 : 1; - 1 : 0; - endtable + output o; + input a; + table + //o a + 0 : 1; + 1 : 0; + endtable endprimitive diff --git a/test_regress/t/t_udp_sequential.v b/test_regress/t/t_udp_sequential.v index 8b86b6f7d..b8cb3a38e 100644 --- a/test_regress/t/t_udp_sequential.v +++ b/test_regress/t/t_udp_sequential.v @@ -5,62 +5,60 @@ // SPDX-License-Identifier: CC0-1.0 primitive d_edge_ff (q, clock, data); - output q; reg q; - input clock, data; - initial q = 1'b1; - table - // clock data q q+ - // obtain output on rising edge of clock - F 0 : ? : 0 ; - (10) 1 : ? : 1 ; - R 0 : ? : 1 ; - (0?) 1 : ? : 0 ; - endtable + output q; reg q; + input clock, data; + initial q = 1'b1; + table + // clock data q q+ + // obtain output on rising edge of clock + F 0 : ? : 0 ; + (10) 1 : ? : 1 ; + R 0 : ? : 1 ; + (0?) 1 : ? : 0 ; + endtable endprimitive -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg d, q; - d_edge_ff g (q, clk, d); +module t ( + input clk +); + reg d, q; + d_edge_ff g (q, clk, d); - int cycle=0; - initial d = 0; - always @(posedge clk or negedge clk) begin - cycle <= cycle+1; - if (cycle==0) begin - d = 1; - end - else if (cycle==1) begin - d = 0; - if (q != 1) $stop; - end - else if (cycle==2) begin - if (q != 1) $stop; - end - else if (cycle==3) begin - if (q != 0) $stop; - end - else if (cycle==4) begin - d = 1; - if (q != 1) $stop; - end - else if (cycle==5) begin - $display("d=%d clk=%d cycle=%0d", d, clk, cycle); - if (q != 1) $stop; - end - else if (cycle==6) begin - if (q != 0) $stop; - end - else if (cycle==7) begin - if (q != 1) $stop; - end - else if (cycle >= 8) begin - if (q != 0) $stop;; - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cycle=0; + initial d = 0; + always @(posedge clk or negedge clk) begin + cycle <= cycle+1; + if (cycle==0) begin + d = 1; + end + else if (cycle==1) begin + d = 0; + if (q != 1) $stop; + end + else if (cycle==2) begin + if (q != 1) $stop; + end + else if (cycle==3) begin + if (q != 0) $stop; + end + else if (cycle==4) begin + d = 1; + if (q != 1) $stop; + end + else if (cycle==5) begin + $display("d=%d clk=%d cycle=%0d", d, clk, cycle); + if (q != 1) $stop; + end + else if (cycle==6) begin + if (q != 0) $stop; + end + else if (cycle==7) begin + if (q != 1) $stop; + end + else if (cycle >= 8) begin + if (q != 0) $stop;; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_udp_sequential_bad.out b/test_regress/t/t_udp_sequential_bad.out index 6e165004b..2d5d5a616 100644 --- a/test_regress/t/t_udp_sequential_bad.out +++ b/test_regress/t/t_udp_sequential_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_udp_sequential_bad.v:8:8: For combinational UDP, the output must not be a 'reg' data type - : ... note: In instance 'top' - 8 | output dout; - | ^~~~ +%Error: t/t_udp_sequential_bad.v:8:10: For combinational UDP, the output must not be a 'reg' data type + : ... note: In instance 'top' + 8 | output dout; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_udp_sequential_bad.v b/test_regress/t/t_udp_sequential_bad.v index 892a9ed09..23516daef 100644 --- a/test_regress/t/t_udp_sequential_bad.v +++ b/test_regress/t/t_udp_sequential_bad.v @@ -5,23 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 primitive or_gate(dout, a, b, c); -output dout; -input a, b, c; -reg dout; + output dout; + input a, b, c; + reg dout; - table - x 0 1 : 1; - 0 ? 1 : 1; - 0 1 0 : 0; - 1 1 ? : 1; - 1 0 0 : 0; - 0 0 0 : 1; - - endtable + table + x 0 1 : 1; + 0 ? 1 : 1; + 0 1 0 : 0; + 1 1 ? : 1; + 1 0 0 : 0; + 0 0 0 : 1; + endtable endprimitive module top (a, b, c, o); - input a, b, c; - output o; - or_gate(o, a, b, c); + input a, b, c; + output o; + or_gate(o, a, b, c); endmodule diff --git a/test_regress/t/t_unbounded_bad.out b/test_regress/t/t_unbounded_bad.out index 0dd41a51d..1e83db3fa 100644 --- a/test_regress/t/t_unbounded_bad.out +++ b/test_regress/t/t_unbounded_bad.out @@ -1,12 +1,12 @@ -%Error-UNSUPPORTED: t/t_unbounded_bad.v:9:11: Unsupported/illegal unbounded ('$') in this context. - : ... note: In instance 't' - 9 | if ($) $stop; - | ^ +%Error-UNSUPPORTED: t/t_unbounded_bad.v:9:9: Unsupported/illegal unbounded ('$') in this context. + : ... note: In instance 't' + 9 | if ($) $stop; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-WIDTHTRUNC: t/t_unbounded_bad.v:9:7: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits. +%Warning-WIDTHTRUNC: t/t_unbounded_bad.v:9:5: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits. : ... note: In instance 't' - 9 | if ($) $stop; - | ^~ + 9 | if ($) $stop; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_unbounded_bad.v b/test_regress/t/t_unbounded_bad.v index c555933b5..8bd25c482 100644 --- a/test_regress/t/t_unbounded_bad.v +++ b/test_regress/t/t_unbounded_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - if ($) $stop; - end + initial begin + if ($) $stop; + end endmodule diff --git a/test_regress/t/t_unconnected.v b/test_regress/t/t_unconnected.v index d90551318..149237748 100644 --- a/test_regress/t/t_unconnected.v +++ b/test_regress/t/t_unconnected.v @@ -4,43 +4,50 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire o_n; - wire o_0; - wire o_1; + wire o_n; + wire o_0; + wire o_1; - // verilator lint_off PINMISSING - sub_0 sub_0(.o_0); - sub_1 sub_1(.o_1); - sub_n sub_n(.o_n); - // verilator lint_on PINMISSING + // verilator lint_off PINMISSING + sub_0 sub_0 (.o_0); + sub_1 sub_1 (.o_1); + sub_n sub_n (.o_n); + // verilator lint_on PINMISSING - always @ (posedge clk) begin - if (o_0 !== 1'b0) $stop; - if (o_1 !== 1'b1) $stop; - //4-state if (o_n !== 1'bz) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (o_0 !== 1'b0) $stop; + if (o_1 !== 1'b1) $stop; + //4-state if (o_n !== 1'bz) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule `unconnected_drive pull0 -module sub_0 (input i, output wire o_0); - assign o_0 = i; +module sub_0 ( + input i, + output wire o_0 +); + assign o_0 = i; endmodule `unconnected_drive pull1 -module sub_1 (input i, output wire o_1); - assign o_1 = i; +module sub_1 ( + input i, + output wire o_1 +); + assign o_1 = i; endmodule `nounconnected_drive -module sub_n (input i, output wire o_n); - assign o_n = i; +module sub_n ( + input i, + output wire o_n +); + assign o_n = i; endmodule diff --git a/test_regress/t/t_union_hard_bad.out b/test_regress/t/t_union_hard_bad.out index c58460a4c..e4120b1ea 100644 --- a/test_regress/t/t_union_hard_bad.out +++ b/test_regress/t/t_union_hard_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_union_hard_bad.v:11:21: Hard packed union members must have equal size (IEEE 1800-2023 7.3.1) +%Error: t/t_union_hard_bad.v:10:17: Hard packed union members must have equal size (IEEE 1800-2023 7.3.1) : ... note: In instance 't' - 11 | bit [7 : 0] val1; - | ^~~~ + 10 | bit [7 : 0] val1; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_union_hard_bad.v b/test_regress/t/t_union_hard_bad.v index 9f100e060..676e5b621 100644 --- a/test_regress/t/t_union_hard_bad.v +++ b/test_regress/t/t_union_hard_bad.v @@ -4,22 +4,21 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t -; +module t; - union packed { - bit [7 : 0] val1; - bit [3 : 0] val2; - } u; + union packed { + bit [7 : 0] val1; + bit [3 : 0] val2; + } u; - initial begin - u.val1 = 8'h7c; - if(u.val1 != 8'h7c) $stop; - u.val2 = 4'h6; - if(u.val2 != 4'h6) $stop; - $display("%p", u); - if(u.val1 != 8'h76) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + u.val1 = 8'h7c; + if (u.val1 != 8'h7c) $stop; + u.val2 = 4'h6; + if (u.val2 != 4'h6) $stop; + $display("%p", u); + if (u.val1 != 8'h76) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_union_soft.v b/test_regress/t/t_union_soft.v index 972c7ba78..1500c34a6 100644 --- a/test_regress/t/t_union_soft.v +++ b/test_regress/t/t_union_soft.v @@ -6,31 +6,31 @@ module t; - union soft { - bit [7:0] val1; - bit [3:0] val2; - } u; + union soft { + bit [7:0] val1; + bit [3:0] val2; + } u; - union soft packed { - bit [7 : 0] val1; - bit [3 : 0] val2; - } u2; + union soft packed { + bit [7 : 0] val1; + bit [3 : 0] val2; + } u2; - initial begin - u.val1 = 8'h7c; - if (u.val1 != 8'h7c) $stop; - u.val2 = 4'h6; - if (u.val2 != 4'h6) $stop; - $display("%p", u); - if(u.val1 != 8'h76) $stop; - u2.val1 = 8'h7c; - if(u2.val1 != 8'h7c) $stop; - u2.val2 = 4'h6; - if(u2.val2 != 4'h6) $stop; - $display("%p", u2); - if(u2.val1 != 8'h76) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + u.val1 = 8'h7c; + if (u.val1 != 8'h7c) $stop; + u.val2 = 4'h6; + if (u.val2 != 4'h6) $stop; + $display("%p", u); + if(u.val1 != 8'h76) $stop; + u2.val1 = 8'h7c; + if(u2.val1 != 8'h7c) $stop; + u2.val2 = 4'h6; + if(u2.val2 != 4'h6) $stop; + $display("%p", u2); + if(u2.val1 != 8'h76) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_union_unpacked.v b/test_regress/t/t_union_unpacked.v index de0971571..85d1f405b 100644 --- a/test_regress/t/t_union_unpacked.v +++ b/test_regress/t/t_union_unpacked.v @@ -6,21 +6,21 @@ module t; - union { - bit [7:0] val1; - bit [3:0] val2; - real r; - } u; + union { + bit [7:0] val1; + bit [3:0] val2; + real r; + } u; - initial begin - u.val1 = 8'h7c; - if (u.val1 != 8'h7c) $stop; - if (u.val2 != 4'hc) $stop; - u.r = 1.24; - if (u.r != 1.24) $stop; - $display("%p", u); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + u.val1 = 8'h7c; + if (u.val1 != 8'h7c) $stop; + if (u.val2 != 4'hc) $stop; + u.r = 1.24; + if (u.r != 1.24) $stop; + $display("%p", u); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_uniqueif.v b/test_regress/t/t_uniqueif.v index 6270cba1c..8a084e9c6 100644 --- a/test_regress/t/t_uniqueif.v +++ b/test_regress/t/t_uniqueif.v @@ -4,109 +4,84 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc = 1; + integer a, b, c, d, e, f, g, h, i, j, k, l; - integer cyc=1; - integer a, b, c, d, e, f, g, h, i, j, k, l; + always @(posedge clk) begin + cyc <= cyc + 1; - always @ (posedge clk) begin - cyc <= cyc + 1; + //==================== + // Positive test cases + //==================== - //==================== - // Positive test cases - //==================== + // Single if, which is untrue sometimes + unique0 if (cyc > 5) a <= 17; - // Single if, which is untrue sometimes - unique0 if (cyc > 5) - a <= 17; + // single if with else + unique0 if (cyc < 3) b <= 17; + else b <= 19; - // single if with else - unique0 if (cyc < 3) - b <= 17; - else - b <= 19; + // multi if, some cases may not be true + unique0 if (cyc < 3) c <= 17; + else if (cyc > 3) c <= 19; - // multi if, some cases may not be true - unique0 if (cyc < 3) - c <= 17; - else if (cyc > 3) - c <= 19; + // multi if with else, else clause hit in some cases + unique0 if (cyc < 3) d <= 17; + else if (cyc > 3) d <= 19; + else d <= 21; - // multi if with else, else clause hit in some cases - unique0 if (cyc < 3) - d <= 17; - else if (cyc > 3) - d <= 19; - else - d <= 21; + // single if with else + unique if (cyc < 3) f <= 17; + else f <= 19; - // single if with else - unique if (cyc < 3) - f <= 17; - else - f <= 19; + // multi if + unique if (cyc < 3) g <= 17; + else if (cyc >= 3) g <= 19; - // multi if - unique if (cyc < 3) - g <= 17; - else if (cyc >= 3) - g <= 19; + // multi if with else, else clause hit in some cases + unique if (cyc < 3) h <= 17; + else if (cyc > 3) h <= 19; + else h <= 21; - // multi if with else, else clause hit in some cases - unique if (cyc < 3) - h <= 17; - else if (cyc > 3) - h <= 19; - else - h <= 21; - - //==================== - // Negative test cases - //==================== + //==================== + // Negative test cases + //==================== `ifdef FAILING_ASSERTION1 - $display("testing fail 1: %d", cyc); - // multi if, multiple cases true - unique0 if (cyc < 3) - i <= 17; - else if (cyc < 5) - i <= 19; + $display("testing fail 1: %d", cyc); + // multi if, multiple cases true + unique0 if (cyc < 3) i <= 17; + else if (cyc < 5) i <= 19; `endif `ifdef FAILING_ASSERTION2 - // multi if, multiple cases true - unique if (cyc < 3) - j <= 17; - else if (cyc < 5) - j <= 19; + // multi if, multiple cases true + unique if (cyc < 3) j <= 17; + else if (cyc < 5) j <= 19; `endif `ifdef FAILING_ASSERTION3 - // multi if, no cases true - unique if (cyc > 1000) - k <= 17; - else if (cyc > 2000) - k <= 19; + // multi if, no cases true + unique if (cyc > 1000) k <= 17; + else if (cyc > 2000) k <= 19; `endif `ifdef FAILING_ASSERTION4 - // Single if, which is untrue sometimes. - // The LRM states: "A software tool shall also issue an error if it determines that no condition' - // is true, or it is possible that no condition is true, and the final if does not have a - // corresponding else." In this case, the final if is the only if, but I think the clause - // still applies. - unique if (cyc > 5) - l <= 17; + // Single if, which is untrue sometimes. + // The LRM states: "A software tool shall also issue an error if it determines that no condition' + // is true, or it is possible that no condition is true, and the final if does not have a + // corresponding else." In this case, the final if is the only if, but I think the clause + // still applies. + unique if (cyc > 5) l <= 17; `endif - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_uniqueif_fail1.out b/test_regress/t/t_uniqueif_fail1.out index 7767184d8..3726ece64 100644 --- a/test_regress/t/t_uniqueif_fail1.out +++ b/test_regress/t/t_uniqueif_fail1.out @@ -1,4 +1,4 @@ testing fail 1: 1 -[10] %Error: t_uniqueif.v:74: Assertion failed in top.t: 'unique if' statement violated -%Error: t/t_uniqueif.v:74: Verilog $stop +[10] %Error: t_uniqueif.v:56: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:56: Verilog $stop Aborting... diff --git a/test_regress/t/t_uniqueif_fail2.out b/test_regress/t/t_uniqueif_fail2.out index cba3a812b..02f8bb189 100644 --- a/test_regress/t/t_uniqueif_fail2.out +++ b/test_regress/t/t_uniqueif_fail2.out @@ -1,3 +1,3 @@ -[10] %Error: t_uniqueif.v:82: Assertion failed in top.t: 'unique if' statement violated -%Error: t/t_uniqueif.v:82: Verilog $stop +[10] %Error: t_uniqueif.v:62: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:62: Verilog $stop Aborting... diff --git a/test_regress/t/t_uniqueif_fail3.out b/test_regress/t/t_uniqueif_fail3.out index 02b41441b..3d638aa80 100644 --- a/test_regress/t/t_uniqueif_fail3.out +++ b/test_regress/t/t_uniqueif_fail3.out @@ -1,3 +1,3 @@ -[10] %Error: t_uniqueif.v:90: Assertion failed in top.t: 'unique if' statement violated -%Error: t/t_uniqueif.v:90: Verilog $stop +[10] %Error: t_uniqueif.v:68: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:68: Verilog $stop Aborting... diff --git a/test_regress/t/t_uniqueif_fail4.out b/test_regress/t/t_uniqueif_fail4.out index 3e327cbff..6c36ae044 100644 --- a/test_regress/t/t_uniqueif_fail4.out +++ b/test_regress/t/t_uniqueif_fail4.out @@ -1,3 +1,3 @@ -[10] %Error: t_uniqueif.v:102: Assertion failed in top.t: 'unique if' statement violated -%Error: t/t_uniqueif.v:102: Verilog $stop +[10] %Error: t_uniqueif.v:78: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:78: Verilog $stop Aborting... diff --git a/test_regress/t/t_unopt_array.v b/test_regress/t/t_unopt_array.v index 9908764c6..809f49de3 100644 --- a/test_regress/t/t_unopt_array.v +++ b/test_regress/t/t_unopt_array.v @@ -4,93 +4,93 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[31:0]), + // Inputs + .clk(clk), + .in(in[31:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h458c2de282e30f8b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h458c2de282e30f8b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - input clk; - input [31:0] in; - output wire [31:0] out; + input clk; + input [31:0] in; + output wire [31:0] out; `ifdef USE_TYPEDEF - typedef reg [3:0][31:0] stage_t [3:0]; - stage_t stage; + typedef reg [3:0][31:0] stage_t[3:0]; + stage_t stage; `else - reg [3:0][31:0] stage [3:0]; + reg [3:0][31:0] stage[3:0]; `endif - genvar g; + genvar g; - generate - for (g=0; g<4; g++) begin - always_comb begin - if (g==0) stage[g] = {4{in}}; - else stage[g] = {4{stage[g-1][0][30:0],1'b1}}; - end + generate + for (g = 0; g < 4; g++) begin + always_comb begin + if (g == 0) stage[g] = {4{in}}; + else stage[g] = {4{stage[g-1][0][30:0], 1'b1}}; end - endgenerate + end + endgenerate - assign out = stage[3][0]; + assign out = stage[3][0]; endmodule diff --git a/test_regress/t/t_unopt_bound.v b/test_regress/t/t_unopt_bound.v index 0c93555e6..66aa98e93 100644 --- a/test_regress/t/t_unopt_bound.v +++ b/test_regress/t/t_unopt_bound.v @@ -6,27 +6,30 @@ // bug630 -module t ( clk, out ); - input clk; - output out; +module t ( + clk, + out +); + input clk; + output out; - reg a; - reg b; + reg a; + reg b; - typedef struct packed { - logic config_a; - logic config_b; - } param_t; - // verilator lint_off UNOPTFLAT - param_t conf [1:2] ; - // verilator lint_on UNOPTFLAT + typedef struct packed { + logic config_a; + logic config_b; + } param_t; + // verilator lint_off UNOPTFLAT + param_t conf[1:2]; + // verilator lint_on UNOPTFLAT - always @ (posedge clk) begin - conf[2].config_b <= a; - $write("*-* All Finished *-*\n"); - $finish; - end - always @ (posedge conf[2].config_b) begin - a = conf[2].config_a; - end + always @(posedge clk) begin + conf[2].config_b <= a; + $write("*-* All Finished *-*\n"); + $finish; + end + always @(posedge conf[2].config_b) begin + a = conf[2].config_a; + end endmodule diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v index 961f0bb3d..5b51b9310 100644 --- a/test_regress/t/t_unopt_combo.v +++ b/test_regress/t/t_unopt_combo.v @@ -5,138 +5,138 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - input clk; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + input clk; + integer cyc; initial cyc = 0; + reg [63:0] crc; + reg [63:0] sum; `ifdef ALLOW_UNOPT - /*verilator lint_off UNOPTFLAT*/ + /*verilator lint_off UNOPTFLAT*/ `endif - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] b; // From file of file.v - wire [31:0] c; // From file of file.v - wire [31:0] d; // From file of file.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] b; // From file of file.v + wire [31:0] c; // From file of file.v + wire [31:0] d; // From file of file.v + // End of automatics - file file (/*AUTOINST*/ - // Outputs - .b (b[31:0]), - .c (c[31:0]), - .d (d[31:0]), - // Inputs - .crc (crc[31:0])); + file file (/*AUTOINST*/ + // Outputs + .b (b[31:0]), + .c (c[31:0]), + .d (d[31:0]), + // Inputs + .crc (crc[31:0])); - always @ (posedge clk) begin + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n", $time, cyc, crc, sum, b, d); + $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n", $time, cyc, crc, sum, b, d); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {b, d} - ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h649ee1713d624dd9) $stop; - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {b, d} + ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h649ee1713d624dd9) $stop; + $finish; + end + end endmodule module file (/*AUTOARG*/ - // Outputs - b, c, d, - // Inputs - crc - ); + // Outputs + b, c, d, + // Inputs + crc + ); - input [31:0] crc; + input [31:0] crc; `ifdef ISOLATE - output reg [31:0] b /* verilator isolate_assignments*/; + output reg [31:0] b /* verilator isolate_assignments*/; `else - output reg [31:0] b; + output reg [31:0] b; `endif - output reg [31:0] c; - output reg [31:0] d; + output reg [31:0] c; + output reg [31:0] d; - always @* begin - // Note that while c and b depend on crc, b doesn't depend on c. - casez (crc[3:0]) - 4'b??01: begin - b = {crc[15:0],get_31_16(crc)}; - d = c; - end - 4'b??00: begin - b = {crc[15:0],~crc[31:16]}; - d = {crc[15:0],~c[31:16]}; - end - default: begin - set_b_d(crc, c); - end - endcase - end - -`ifdef ISOLATE - function [31:16] get_31_16 /* verilator isolate_assignments*/; - input [31:0] t_crc /* verilator isolate_assignments*/; - get_31_16 = t_crc[31:16]; - endfunction -`else - function [31:16] get_31_16; - input [31:0] t_crc; - get_31_16 = t_crc[31:16]; - endfunction -`endif - - task set_b_d; -`ifdef ISOLATE - input [31:0] t_crc /* verilator isolate_assignments*/; - input [31:0] t_c /* verilator isolate_assignments*/; -`else - input [31:0] t_crc; - input [31:0] t_c; -`endif - begin - b = {t_crc[31:16],~t_crc[23:8]}; - d = {t_crc[31:16], ~t_c[23:8]}; + always @* begin + // Note that while c and b depend on crc, b doesn't depend on c. + casez (crc[3:0]) + 4'b??01: begin + b = {crc[15:0],get_31_16(crc)}; + d = c; end - endtask + 4'b??00: begin + b = {crc[15:0],~crc[31:16]}; + d = {crc[15:0],~c[31:16]}; + end + default: begin + set_b_d(crc, c); + end + endcase + end - always @* begin - // Any complicated equation we can't optimize - casez (crc[3:0]) - 4'b00??: begin - c = {b[29:0],2'b11}; - end - 4'b01??: begin - c = {b[30:1],2'b01}; - end - 4'b10??: begin - c = {b[31:2],2'b10}; - end - 4'b11??: begin - c = {b[31:2],2'b00}; - end - endcase - end +`ifdef ISOLATE + function [31:16] get_31_16 /* verilator isolate_assignments*/; + input [31:0] t_crc /* verilator isolate_assignments*/; + get_31_16 = t_crc[31:16]; + endfunction +`else + function [31:16] get_31_16; + input [31:0] t_crc; + get_31_16 = t_crc[31:16]; + endfunction +`endif + + task set_b_d; +`ifdef ISOLATE + input [31:0] t_crc /* verilator isolate_assignments*/; + input [31:0] t_c /* verilator isolate_assignments*/; +`else + input [31:0] t_crc; + input [31:0] t_c; +`endif + begin + b = {t_crc[31:16],~t_crc[23:8]}; + d = {t_crc[31:16], ~t_c[23:8]}; + end + endtask + + always @* begin + // Any complicated equation we can't optimize + casez (crc[3:0]) + 4'b00??: begin + c = {b[29:0],2'b11}; + end + 4'b01??: begin + c = {b[30:1],2'b01}; + end + 4'b10??: begin + c = {b[31:2],2'b10}; + end + 4'b11??: begin + c = {b[31:2],2'b00}; + end + endcase + end endmodule diff --git a/test_regress/t/t_unopt_combo_bad.out b/test_regress/t/t_unopt_combo_bad.out index 8cd58f59f..69e037558 100644 --- a/test_regress/t/t_unopt_combo_bad.out +++ b/test_regress/t/t_unopt_combo_bad.out @@ -1,11 +1,11 @@ -%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:25: Signal unoptimizable: Circular combinational logic: 't.b' - 23 | wire [31:0] b; - | ^ +%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:24: Signal unoptimizable: Circular combinational logic: 't.b' + 23 | wire [31:0] b; + | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unopt_combo.v:23:25: Example path: t.b - t/t_unopt_combo.v:124:4: Example path: ALWAYS - t/t_unopt_combo.v:24:25: Example path: t.c - t/t_unopt_combo.v:81:4: Example path: ALWAYS - t/t_unopt_combo.v:23:25: Example path: t.b + t/t_unopt_combo.v:23:24: Example path: t.b + t/t_unopt_combo.v:124:3: Example path: ALWAYS + t/t_unopt_combo.v:24:24: Example path: t.c + t/t_unopt_combo.v:81:3: Example path: ALWAYS + t/t_unopt_combo.v:23:24: Example path: t.b %Error: Exiting due to diff --git a/test_regress/t/t_unopt_converge.v b/test_regress/t/t_unopt_converge.v index 324d6fdf8..dc74892bb 100644 --- a/test_regress/t/t_unopt_converge.v +++ b/test_regress/t/t_unopt_converge.v @@ -4,23 +4,23 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - x, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + x, + // Inputs + clk +); `ifdef ALLOW_UNOPT - /*verilator lint_off UNOPTFLAT*/ + /*verilator lint_off UNOPTFLAT*/ `endif - input clk; - output x; // Avoid eliminating x + input clk; + output x; // Avoid eliminating x - reg x; - always @* begin - x = ~x; - end + reg x; + always @* begin + x = ~x; + end endmodule diff --git a/test_regress/t/t_unopt_converge_initial.v b/test_regress/t/t_unopt_converge_initial.v index 3fea89cef..eeda21129 100644 --- a/test_regress/t/t_unopt_converge_initial.v +++ b/test_regress/t/t_unopt_converge_initial.v @@ -4,23 +4,23 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - x, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + x, + // Inputs + clk +); `ifdef ALLOW_UNOPT - /*verilator lint_off UNOPTFLAT*/ + /*verilator lint_off UNOPTFLAT*/ `endif - input clk; - output [31:0] x; // Avoid eliminating x + input clk; + output [31:0] x; // Avoid eliminating x - reg [31:0] x; - always @* begin - x = x ^ $random; - end + reg [31:0] x; + always @* begin + x = x ^ $random; + end endmodule diff --git a/test_regress/t/t_unopt_converge_unopt_bad.out b/test_regress/t/t_unopt_converge_unopt_bad.out index ad410cbb3..eaf6c942a 100644 --- a/test_regress/t/t_unopt_converge_unopt_bad.out +++ b/test_regress/t/t_unopt_converge_unopt_bad.out @@ -1,9 +1,9 @@ -%Warning-UNOPTFLAT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Circular combinational logic: 'x' - 19 | output x; - | ^ +%Warning-UNOPTFLAT: t/t_unopt_converge.v:19:10: Signal unoptimizable: Circular combinational logic: 'x' + 19 | output x; + | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unopt_converge.v:19:11: Example path: x - t/t_unopt_converge.v:22:4: Example path: ALWAYS - t/t_unopt_converge.v:19:11: Example path: x + t/t_unopt_converge.v:19:10: Example path: x + t/t_unopt_converge.v:22:3: Example path: ALWAYS + t/t_unopt_converge.v:19:10: Example path: x %Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple.v b/test_regress/t/t_unoptflat_simple.v index 72b31227e..83487c05c 100644 --- a/test_regress/t/t_unoptflat_simple.v +++ b/test_regress/t/t_unoptflat_simple.v @@ -6,24 +6,24 @@ // SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - wire [1:0] x = { x[0], clk }; + wire [1:0] x = {x[0], clk}; - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE - $write("x = %x\n", x); + $write("x = %x\n", x); `endif - if (x[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_unoptflat_simple_2.v b/test_regress/t/t_unoptflat_simple_2.v index cf72d6643..c97ec97e8 100644 --- a/test_regress/t/t_unoptflat_simple_2.v +++ b/test_regress/t/t_unoptflat_simple_2.v @@ -6,29 +6,29 @@ // SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - /* verilator lint_off MULTIDRIVEN */ - wire [2:0] x; - /* verilator lint_on MULTIDRIVEN */ + /* verilator lint_off MULTIDRIVEN */ + wire [2:0] x; + /* verilator lint_on MULTIDRIVEN */ - assign x[1:0] = { x[0], clk }; - assign x[2:1] = x[1:0]; + assign x[1:0] = {x[0], clk}; + assign x[2:1] = x[1:0]; - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE - $write("x = %x\n", x); + $write("x = %x\n", x); `endif - if (x[2] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (x[2] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end -endmodule // t +endmodule // t diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out index 5bcb5a581..8588ac55c 100644 --- a/test_regress/t/t_unoptflat_simple_2_bad.out +++ b/test_regress/t/t_unoptflat_simple_2_bad.out @@ -1,14 +1,14 @@ -%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x' - 16 | wire [2:0] x; - | ^ +%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:16:14: Signal unoptimizable: Circular combinational logic: 't.x' + 16 | wire [2:0] x; + | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unoptflat_simple_2.v:16:15: Example path: t.x - t/t_unoptflat_simple_2.v:19:18: Example path: ASSIGNW - t/t_unoptflat_simple_2.v:16:15: Example path: t.x + t/t_unoptflat_simple_2.v:16:14: Example path: t.x + t/t_unoptflat_simple_2.v:19:17: Example path: ASSIGNW + t/t_unoptflat_simple_2.v:16:14: Example path: t.x ... Widest variables candidate to splitting: - t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 2, can split_var + t/t_unoptflat_simple_2.v:16:14: t.x, width 3, circular fanout 2, can split_var ... Candidates with the highest fanout: - t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 2, can split_var + t/t_unoptflat_simple_2.v:16:14: t.x, width 3, circular fanout 2, can split_var ... Suggest add /*verilator split_var*/ or /*verilator isolate_assignments*/ to appropriate variables above. %Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple_3.v b/test_regress/t/t_unoptflat_simple_3.v index 55eae8aa5..113eb5fe6 100644 --- a/test_regress/t/t_unoptflat_simple_3.v +++ b/test_regress/t/t_unoptflat_simple_3.v @@ -7,70 +7,72 @@ // SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - wire [2:0] x; + wire [2:0] x; - test1 test1i ( .clk (clk), - .xvecin (x[1:0]), - .xvecout (x[2:1])); + test1 test1i ( + .clk(clk), + .xvecin(x[1:0]), + .xvecout(x[2:1]) + ); - test2 test2i ( .clk (clk), - .xvecin (x[2:1]), - .xvecout (x[1:0])); + test2 test2i ( + .clk(clk), + .xvecin(x[2:1]), + .xvecout(x[1:0]) + ); - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE - $write("x = %x\n", x); + $write("x = %x\n", x); `endif - if (x[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end -endmodule // t +endmodule // t -module test1 - (/*AUTOARG*/ - // Inputs - clk, - xvecin, - // Outputs - xvecout - ); +module test1 ( /*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout +); - input clk; - input wire [1:0] xvecin; + input clk; + input wire [1:0] xvecin; - output wire [1:0] xvecout; + output wire [1:0] xvecout; - assign xvecout = {xvecin[0], clk}; + assign xvecout = {xvecin[0], clk}; -endmodule // test +endmodule // test -module test2 - (/*AUTOARG*/ - // Inputs - clk, - xvecin, - // Outputs - xvecout - ); +module test2 ( /*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout +); - input clk; - input wire [1:0] xvecin; + input clk; + input wire [1:0] xvecin; - output wire [1:0] xvecout; + output wire [1:0] xvecout; - assign xvecout = {clk, xvecin[1]}; + assign xvecout = {clk, xvecin[1]}; -endmodule // test +endmodule // test diff --git a/test_regress/t/t_unoptflat_simple_3_bad.out b/test_regress/t/t_unoptflat_simple_3_bad.out index 58aac8860..f5ef439ae 100644 --- a/test_regress/t/t_unoptflat_simple_3_bad.out +++ b/test_regress/t/t_unoptflat_simple_3_bad.out @@ -1,11 +1,11 @@ -%Warning-UNOPTFLAT: t/t_unoptflat_simple_3.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x' - 16 | wire [2:0] x; - | ^ +%Warning-UNOPTFLAT: t/t_unoptflat_simple_3.v:16:14: Signal unoptimizable: Circular combinational logic: 't.x' + 16 | wire [2:0] x; + | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unoptflat_simple_3.v:16:15: Example path: t.x - t/t_unoptflat_simple_3.v:55:19: Example path: ASSIGNW - t/t_unoptflat_simple_3.v:53:22: Example path: t.__Vcellout__test1i__xvecout - t/t_unoptflat_simple_3.v:20:20: Example path: ASSIGNW - t/t_unoptflat_simple_3.v:16:15: Example path: t.x + t/t_unoptflat_simple_3.v:16:14: Example path: t.x + t/t_unoptflat_simple_3.v:58:18: Example path: ASSIGNW + t/t_unoptflat_simple_3.v:56:21: Example path: t.__Vcellout__test1i__xvecout + t/t_unoptflat_simple_3.v:21:8: Example path: ASSIGNW + t/t_unoptflat_simple_3.v:16:14: Example path: t.x %Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple_bad.out b/test_regress/t/t_unoptflat_simple_bad.out index e0a88d651..f4baea1ef 100644 --- a/test_regress/t/t_unoptflat_simple_bad.out +++ b/test_regress/t/t_unoptflat_simple_bad.out @@ -1,9 +1,9 @@ -%Warning-UNOPTFLAT: t/t_unoptflat_simple.v:15:15: Signal unoptimizable: Circular combinational logic: 't.x' - 15 | wire [1:0] x = { x[0], clk }; - | ^ +%Warning-UNOPTFLAT: t/t_unoptflat_simple.v:15:14: Signal unoptimizable: Circular combinational logic: 't.x' + 15 | wire [1:0] x = {x[0], clk}; + | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unoptflat_simple.v:15:15: Example path: t.x - t/t_unoptflat_simple.v:15:17: Example path: ASSIGNW - t/t_unoptflat_simple.v:15:15: Example path: t.x + t/t_unoptflat_simple.v:15:14: Example path: t.x + t/t_unoptflat_simple.v:15:16: Example path: ASSIGNW + t/t_unoptflat_simple.v:15:14: Example path: t.x %Error: Exiting due to diff --git a/test_regress/t/t_unpack_array_no_expand.v b/test_regress/t/t_unpack_array_no_expand.v index 9bbd61ed0..2a5144b65 100644 --- a/test_regress/t/t_unpack_array_no_expand.v +++ b/test_regress/t/t_unpack_array_no_expand.v @@ -4,39 +4,38 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - ( - output logic [255:0] data_out - ); - localparam int NUM_STAGES = 3; +module t ( + output logic [255:0] data_out +); + localparam int NUM_STAGES = 3; - /* verilator lint_off ALWCOMBORDER */ - /* verilator lint_off UNOPTFLAT */ + /* verilator lint_off ALWCOMBORDER */ + /* verilator lint_off UNOPTFLAT */ -`define INPUT 256'hbabecafe + `define INPUT 256'hbabecafe - logic [255:0] stage_data [NUM_STAGES+1]; + logic [255:0] stage_data[NUM_STAGES+1]; - genvar stage; - generate + genvar stage; + generate + always_comb begin + stage_data[0] = `INPUT; + end + for (stage = 0; stage < NUM_STAGES; ++stage) begin : stage_gen always_comb begin - stage_data[0] = `INPUT; + stage_data[stage+1] = stage_data[stage]; end - for (stage = 0; stage < NUM_STAGES; ++stage) begin : stage_gen - always_comb begin - stage_data[stage+1] = stage_data[stage]; - end - end - endgenerate + end + endgenerate - /* verilator lint_on UNOPTFLAT */ - /* verilator lint_on ALWCOMBORDER */ + /* verilator lint_on UNOPTFLAT */ + /* verilator lint_on ALWCOMBORDER */ - always_comb begin - data_out = stage_data[NUM_STAGES]; - if (data_out !== `INPUT) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always_comb begin + data_out = stage_data[NUM_STAGES]; + if (data_out !== `INPUT) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_array_order.v b/test_regress/t/t_unpacked_array_order.v index d37fa7aa7..08bac4af3 100644 --- a/test_regress/t/t_unpacked_array_order.v +++ b/test_regress/t/t_unpacked_array_order.v @@ -4,27 +4,25 @@ // SPDX-FileCopyrightText: 2015 Duraid Madina // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - parameter logic [1:0] t0 [ 2][ 2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; - parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; - parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}}; + parameter logic [1:0] t0[2][2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; + parameter logic [1:0] t1[0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; + parameter logic [1:0] t2[1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}}; - always @ (posedge clk) begin - if (t0[0][0] != t1[0][0]) $stop; - if (t0[0][1] != t1[0][1]) $stop; - if (t0[1][0] != t1[1][0]) $stop; - if (t0[1][1] != t1[1][1]) $stop; - if (t0[0][0] != t2[0][0]) $stop; - if (t0[0][1] != t2[0][1]) $stop; - if (t0[1][0] != t2[1][0]) $stop; - if (t0[1][1] != t2[1][1]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (t0[0][0] != t1[0][0]) $stop; + if (t0[0][1] != t1[0][1]) $stop; + if (t0[1][0] != t1[1][0]) $stop; + if (t0[1][1] != t1[1][1]) $stop; + if (t0[0][0] != t2[0][0]) $stop; + if (t0[0][1] != t2[0][1]) $stop; + if (t0[1][0] != t2[1][0]) $stop; + if (t0[1][1] != t2[1][1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_array_p_fmt.v b/test_regress/t/t_unpacked_array_p_fmt.v index b04ad1586..30b41d7ec 100644 --- a/test_regress/t/t_unpacked_array_p_fmt.v +++ b/test_regress/t/t_unpacked_array_p_fmt.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg arr [15:0]; - reg mat [3:0] [3:0]; + reg arr[15:0]; + reg mat[3:0][3:0]; - initial begin - for (int i = 0; i < 16; i++) begin - arr[i] = ^i; - mat[i/4][i%4] = ^i; - end + initial begin + for (int i = 0; i < 16; i++) begin + arr[i] = ^i; + mat[i/4][i%4] = ^i; + end - $display("%%p=%p", arr); - $display("%%p=%p", mat); - $write("*-* All Finished *-*\n"); - $finish; - end + $display("%%p=%p", arr); + $display("%%p=%p", mat); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_concat.v b/test_regress/t/t_unpacked_concat.v index f78b44540..dc9156331 100644 --- a/test_regress/t/t_unpacked_concat.v +++ b/test_regress/t/t_unpacked_concat.v @@ -6,92 +6,92 @@ module t; - typedef int ai3_t[1:3]; - ai3_t a3; - int a9[1:9]; + typedef int ai3_t[1:3]; + ai3_t a3; + int a9[1:9]; - logic [2:0] s0; - logic [2:0] s1[1:3]; - logic [2:0] s1b[3:1]; - logic [2:0] s3[2:8]; - logic [2:0] s3b[8:2]; + logic [2:0] s0; + logic [2:0] s1[1:3]; + logic [2:0] s1b[3:1]; + logic [2:0] s3[2:8]; + logic [2:0] s3b[8:2]; - initial begin - s0 = 3'd1; - s1[1] = 3'd2; - s1[2] = 3'd3; - s1[3] = 3'd4; - s1b[1] = 3'd5; - s1b[2] = 3'd6; - s1b[3] = 3'd7; + initial begin + s0 = 3'd1; + s1[1] = 3'd2; + s1[2] = 3'd3; + s1[3] = 3'd4; + s1b[1] = 3'd5; + s1b[2] = 3'd6; + s1b[3] = 3'd7; - a3 = '{1, 2, 3}; - a9 = {a3, 4, 5, a3, 6}; - if (a9[1] != 1) $stop; - if (a9[2] != 2) $stop; - if (a9[3] != 3) $stop; - if (a9[4] != 4) $stop; - if (a9[5] != 5) $stop; - if (a9[6] != 1) $stop; - if (a9[7] != 2) $stop; - if (a9[8] != 3) $stop; - if (a9[9] != 6) $stop; + a3 = '{1, 2, 3}; + a9 = {a3, 4, 5, a3, 6}; + if (a9[1] != 1) $stop; + if (a9[2] != 2) $stop; + if (a9[3] != 3) $stop; + if (a9[4] != 4) $stop; + if (a9[5] != 5) $stop; + if (a9[6] != 1) $stop; + if (a9[7] != 2) $stop; + if (a9[8] != 3) $stop; + if (a9[9] != 6) $stop; - s3 = {s0, s1, s1b}; - if (s3[2] != s0) $stop; - if (s3[3] != s1[1]) $stop; - if (s3[4] != s1[2]) $stop; - if (s3[5] != s1[3]) $stop; - if (s3[6] != s1b[3]) $stop; - if (s3[7] != s1b[2]) $stop; - if (s3[8] != s1b[1]) $stop; + s3 = {s0, s1, s1b}; + if (s3[2] != s0) $stop; + if (s3[3] != s1[1]) $stop; + if (s3[4] != s1[2]) $stop; + if (s3[5] != s1[3]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; - if (s3[2] != s0) $stop; - if (s3[3] != s1[1]) $stop; - if (s3[4] != s1[2]) $stop; - if (s3[5] != s1[3]) $stop; - if (s3[6] != s1b[3]) $stop; - if (s3[7] != s1b[2]) $stop; - if (s3[8] != s1b[1]) $stop; + s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; + if (s3[2] != s0) $stop; + if (s3[3] != s1[1]) $stop; + if (s3[4] != s1[2]) $stop; + if (s3[5] != s1[3]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; - if (s3[2] != s0) $stop; - if (s3[3] != s1[1]) $stop; - if (s3[4] != s1[2]) $stop; - if (s3[5] != s1[3]) $stop; - if (s3[6] != s1b[3]) $stop; - if (s3[7] != s1b[2]) $stop; - if (s3[8] != s1b[1]) $stop; + s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; + if (s3[2] != s0) $stop; + if (s3[3] != s1[1]) $stop; + if (s3[4] != s1[2]) $stop; + if (s3[5] != s1[3]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s3b = {s0, s1, s1b}; - if (s3b[8] != s0) $stop; - if (s3b[7] != s1[1]) $stop; - if (s3b[6] != s1[2]) $stop; - if (s3b[5] != s1[3]) $stop; - if (s3b[4] != s1b[3]) $stop; - if (s3b[3] != s1b[2]) $stop; - if (s3b[2] != s1b[1]) $stop; + s3b = {s0, s1, s1b}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; - s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; - if (s3b[8] != s0) $stop; - if (s3b[7] != s1[1]) $stop; - if (s3b[6] != s1[2]) $stop; - if (s3b[5] != s1[3]) $stop; - if (s3b[4] != s1b[3]) $stop; - if (s3b[3] != s1b[2]) $stop; - if (s3b[2] != s1b[1]) $stop; + s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; - s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; - if (s3b[8] != s0) $stop; - if (s3b[7] != s1[1]) $stop; - if (s3b[6] != s1[2]) $stop; - if (s3b[5] != s1[3]) $stop; - if (s3b[4] != s1b[3]) $stop; - if (s3b[3] != s1b[2]) $stop; - if (s3b[2] != s1b[1]) $stop; + s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out index 6268aa47b..6969760a0 100644 --- a/test_regress/t/t_unpacked_concat_bad.out +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:12:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type +%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:12:44: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type : ... note: In instance 't' - 12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; - | ^ + 12 | localparam bit_int_t count_bits[1:0] = {2{$bits(count_t)}}; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_unpacked_concat_bad.v:12:46: Assignment pattern missed initializing elements: 0 +%Error: t/t_unpacked_concat_bad.v:12:44: Assignment pattern missed initializing elements: 0 : ... note: In instance 't' - 12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; - | ^ + 12 | localparam bit_int_t count_bits[1:0] = {2{$bits(count_t)}}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad.v b/test_regress/t/t_unpacked_concat_bad.v index 905760dbb..e4a2dbb38 100644 --- a/test_regress/t/t_unpacked_concat_bad.v +++ b/test_regress/t/t_unpacked_concat_bad.v @@ -6,18 +6,18 @@ module t; - typedef logic [15:0] count_t; - typedef bit [31:0] bit_int_t; + typedef logic [15:0] count_t; + typedef bit [31:0] bit_int_t; - localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; - localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; + localparam bit_int_t count_bits[1:0] = {2{$bits(count_t)}}; + localparam bit_int_t count_bitsc[1:0] = {$bits(count_t), $bits(count_t)}; - initial begin - if (count_bits[0] != 16) $stop; - if (count_bits[1] != 16) $stop; - if (count_bitsc[0] != 16) $stop; - if (count_bitsc[1] != 16) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (count_bits[0] != 16) $stop; + if (count_bits[1] != 16) $stop; + if (count_bitsc[0] != 16) $stop; + if (count_bitsc[1] != 16) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_concat_bad2.out b/test_regress/t/t_unpacked_concat_bad2.out index 68b53335a..bb6b955c8 100644 --- a/test_regress/t/t_unpacked_concat_bad2.out +++ b/test_regress/t/t_unpacked_concat_bad2.out @@ -1,14 +1,14 @@ -%Error: t/t_unpacked_concat_bad2.v:20:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. - 20 | s1 = {s0, s2}; - | ^ +%Error: t/t_unpacked_concat_bad2.v:20:13: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. + 20 | s1 = {s0, s2}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_unpacked_concat_bad2.v:21:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. - 21 | s2 = {s1, s0, s0, s0}; - | ^ -%Error: t/t_unpacked_concat_bad2.v:23:17: Item is incompatible with the array type. - 23 | s2 = {s0, s3}; +%Error: t/t_unpacked_concat_bad2.v:21:21: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. + 21 | s2 = {s1, s0, s0, s0}; + | ^ +%Error: t/t_unpacked_concat_bad2.v:23:15: Item is incompatible with the array type. + 23 | s2 = {s0, s3}; + | ^~ +%Error: t/t_unpacked_concat_bad2.v:25:17: Item is incompatible with the array type. + 25 | A9_logic = {A3, 4, 5, A3, 6}; | ^~ -%Error: t/t_unpacked_concat_bad2.v:25:19: Item is incompatible with the array type. - 25 | A9_logic = {A3, 4, 5, A3, 6}; - | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad2.v b/test_regress/t/t_unpacked_concat_bad2.v index 420333134..14ce01d48 100644 --- a/test_regress/t/t_unpacked_concat_bad2.v +++ b/test_regress/t/t_unpacked_concat_bad2.v @@ -6,24 +6,24 @@ module t; - logic [7:0] s0; - logic [7:0] s1[1:2]; - logic [7:0] s2[1:4]; - logic [7:0] s3[2][2]; + logic [7:0] s0; + logic [7:0] s1[1:2]; + logic [7:0] s2[1:4]; + logic [7:0] s3[2][2]; - typedef int AI3[1:3]; - AI3 A3; - logic [31:0] A9_logic[1:9]; + typedef int AI3[1:3]; + AI3 A3; + logic [31:0] A9_logic[1:9]; - initial begin - // RHS has too many elements. - s1 = {s0, s2}; - s2 = {s1, s0, s0, s0}; - // Incompatible type - s2 = {s0, s3}; + initial begin + // RHS has too many elements. + s1 = {s0, s2}; + s2 = {s1, s0, s0, s0}; + // Incompatible type + s2 = {s0, s3}; - A9_logic = {A3, 4, 5, A3, 6}; - $write("*-* All Finished *-*\n"); - $finish; - end + A9_logic = {A3, 4, 5, A3, 6}; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_concat_bad3.out b/test_regress/t/t_unpacked_concat_bad3.out index 1674c1ac6..defb14b83 100644 --- a/test_regress/t/t_unpacked_concat_bad3.out +++ b/test_regress/t/t_unpacked_concat_bad3.out @@ -1,10 +1,10 @@ -%Error: t/t_unpacked_concat_bad3.v:9:41: Assignment pattern missed initializing elements: 3 +%Error: t/t_unpacked_concat_bad3.v:9:39: Assignment pattern missed initializing elements: 3 : ... note: In instance 't' - 9 | localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; - | ^~ + 9 | localparam logic [7:0] TOO_FEW[5] = '{0, 1, 2 ** 8 - 1}; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_unpacked_concat_bad3.v:9:41: Assignment pattern missed initializing elements: 4 +%Error: t/t_unpacked_concat_bad3.v:9:39: Assignment pattern missed initializing elements: 4 : ... note: In instance 't' - 9 | localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; - | ^~ + 9 | localparam logic [7:0] TOO_FEW[5] = '{0, 1, 2 ** 8 - 1}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad3.v b/test_regress/t/t_unpacked_concat_bad3.v index 6ac6eebd8..0fd1571bd 100644 --- a/test_regress/t/t_unpacked_concat_bad3.v +++ b/test_regress/t/t_unpacked_concat_bad3.v @@ -6,10 +6,10 @@ module t; - localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; // Bad + localparam logic [7:0] TOO_FEW[5] = '{0, 1, 2 ** 8 - 1}; // Bad - initial begin - $display("%p", TOO_FEW); - $stop; - end + initial begin + $display("%p", TOO_FEW); + $stop; + end endmodule diff --git a/test_regress/t/t_unpacked_init.v b/test_regress/t/t_unpacked_init.v index a233e26b2..a666cfce9 100644 --- a/test_regress/t/t_unpacked_init.v +++ b/test_regress/t/t_unpacked_init.v @@ -4,38 +4,40 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - int a1[2] = '{12, 13}; - int a2[2] = {14, 15}; - int a3[1] = '{16}; - int a4[1] = {17}; + int a1[2] = '{12, 13}; + int a2[2] = {14, 15}; + int a3[1] = '{16}; + int a4[1] = {17}; - int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}}; + int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}}; - initial begin - `checkh(a1[0], 12); - `checkh(a1[1], 13); + initial begin + `checkh(a1[0], 12); + `checkh(a1[1], 13); - `checkh(a2[0], 14); - `checkh(a2[1], 15); + `checkh(a2[0], 14); + `checkh(a2[1], 15); - `checkh(a3[0], 16); + `checkh(a3[0], 16); - `checkh(a4[0], 17); + `checkh(a4[0], 17); - `checkh(a5[0][0], 10); - `checkh(a5[0][1], 11); - `checkh(a5[0][2], 12); - `checkh(a5[1][0], 13); - `checkh(a5[1][1], 14); - `checkh(a5[1][2], 15); + `checkh(a5[0][0], 10); + `checkh(a5[0][1], 11); + `checkh(a5[0][2], 12); + `checkh(a5[1][0], 13); + `checkh(a5[1][1], 14); + `checkh(a5[1][2], 15); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_slice.v b/test_regress/t/t_unpacked_slice.v index 24bcb5dec..ae2c6c9da 100644 --- a/test_regress/t/t_unpacked_slice.v +++ b/test_regress/t/t_unpacked_slice.v @@ -4,55 +4,57 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - parameter int sliceddn[4:-3] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; - parameter int slicedup[-3:4] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; - int alldn[7:0]; - int allup[0:7]; - int twodn[1:0]; - int twoup[0:1]; + parameter int sliceddn[4:-3] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; + parameter int slicedup[-3:4] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; + int alldn[7:0]; + int allup[0:7]; + int twodn[1:0]; + int twoup[0:1]; - initial begin - `checkh(sliceddn[4], 'h100); - alldn[7:0] = sliceddn[4:-3]; - `checkh(alldn[7], 'h100); - alldn[7:0] = sliceddn[-3 +: 8]; // down: lsb/lo +: width - `checkh(alldn[7], 'h100); - alldn[7:0] = sliceddn[4 -: 8]; // down: msb/hi -: width - `checkh(alldn[7], 'h100); - twodn[1:0] = sliceddn[3:2]; - `checkh(twodn[1], 'h101); - `checkh(twodn[0], 'h102); - twodn[1:0] = sliceddn[1 +: 2]; - `checkh(twodn[1], 'h102); - `checkh(twodn[0], 'h103); - twodn[1:0] = sliceddn[1 -: 2]; - `checkh(twodn[1], 'h103); - `checkh(twodn[0], 'h104); + initial begin + `checkh(sliceddn[4], 'h100); + alldn[7:0] = sliceddn[4:-3]; + `checkh(alldn[7], 'h100); + alldn[7:0] = sliceddn[-3+:8]; // down: lsb/lo +: width + `checkh(alldn[7], 'h100); + alldn[7:0] = sliceddn[4-:8]; // down: msb/hi -: width + `checkh(alldn[7], 'h100); + twodn[1:0] = sliceddn[3:2]; + `checkh(twodn[1], 'h101); + `checkh(twodn[0], 'h102); + twodn[1:0] = sliceddn[1+:2]; + `checkh(twodn[1], 'h102); + `checkh(twodn[0], 'h103); + twodn[1:0] = sliceddn[1-:2]; + `checkh(twodn[1], 'h103); + `checkh(twodn[0], 'h104); - `checkh(slicedup[4], 'h107); - allup[0:7] = slicedup[-3:4]; - `checkh(alldn[7], 'h100); - allup[0:7] = slicedup[-3 +: 8]; // up: msb/lo +: width - `checkh(alldn[7], 'h100); - allup[0:7] = slicedup[4 -: 8]; // up: lsb/hi -: width - `checkh(alldn[7], 'h100); - twoup[0:1] = slicedup[2:3]; - `checkh(twoup[1], 'h106); - `checkh(twoup[0], 'h105); - twoup[0:1] = slicedup[1 +: 2]; - `checkh(twoup[1], 'h105); - `checkh(twoup[0], 'h104); - twoup[0:1] = slicedup[1 -: 2]; - `checkh(twoup[1], 'h104); - `checkh(twoup[0], 'h103); + `checkh(slicedup[4], 'h107); + allup[0:7] = slicedup[-3:4]; + `checkh(alldn[7], 'h100); + allup[0:7] = slicedup[-3+:8]; // up: msb/lo +: width + `checkh(alldn[7], 'h100); + allup[0:7] = slicedup[4-:8]; // up: lsb/hi -: width + `checkh(alldn[7], 'h100); + twoup[0:1] = slicedup[2:3]; + `checkh(twoup[1], 'h106); + `checkh(twoup[0], 'h105); + twoup[0:1] = slicedup[1+:2]; + `checkh(twoup[1], 'h105); + `checkh(twoup[0], 'h104); + twoup[0:1] = slicedup[1-:2]; + `checkh(twoup[1], 'h104); + `checkh(twoup[0], 'h103); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_slice_range.v b/test_regress/t/t_unpacked_slice_range.v index 9d31e3359..ec3282640 100644 --- a/test_regress/t/t_unpacked_slice_range.v +++ b/test_regress/t/t_unpacked_slice_range.v @@ -5,60 +5,66 @@ // SPDX-License-Identifier: Unlicense module t ( - clk - ); - input clk; + clk +); + input clk; - int c = 0; + int c = 0; - t2 #(0) i_0(.*); - t2 #(-1) i_1(.*); // lo is -1, hi is 5 - t2 #(-4) i_2(.*); // lo is -4, hi is 1 - t2 #(-10) i_3(.*); // lo is -10, hi is -4 - t2 #(+1) i_4(.*); // lo is 1, hi is 7 - t2 #(+4) i_5(.*); // lo is 4, hi is 10 - t2 #(+10) i_6(.*); // lo is 10, hi is 16 + t2 #(0) i_0 (.*); + t2 #(-1) i_1 (.*); // lo is -1, hi is 5 + t2 #(-4) i_2 (.*); // lo is -4, hi is 1 + t2 #(-10) i_3 (.*); // lo is -10, hi is -4 + t2 #(+1) i_4 (.*); // lo is 1, hi is 7 + t2 #(+4) i_5 (.*); // lo is 4, hi is 10 + t2 #(+10) i_6 (.*); // lo is 10, hi is 16 - always @(posedge clk) begin - c <= c + 1; - if (c == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + c <= c + 1; + if (c == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module t2 #(parameter ORIGIN = 0) (input wire clk, input int c); - localparam WIDTH = 7; - localparam OFFSET = 3; - localparam FULL_LO = ORIGIN; - localparam FULL_HI = ORIGIN + WIDTH - 1; - localparam PART_LO = FULL_LO + OFFSET; - localparam PART_HI = FULL_HI; - bit unpack_sig0 [FULL_LO:FULL_HI]; - bit unpack_sig1 [PART_LO:PART_HI]; - bit unpack_sig2 [FULL_HI:FULL_LO]; - bit unpack_sig3 [PART_HI:PART_LO]; - initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI); +module t2 #( + parameter ORIGIN = 0 +) ( + input wire clk, + input int c +); + localparam WIDTH = 7; + localparam OFFSET = 3; + localparam FULL_LO = ORIGIN; + localparam FULL_HI = ORIGIN + WIDTH - 1; + localparam PART_LO = FULL_LO + OFFSET; + localparam PART_HI = FULL_HI; + bit unpack_sig0[FULL_LO:FULL_HI]; + bit unpack_sig1[PART_LO:PART_HI]; + bit unpack_sig2[FULL_HI:FULL_LO]; + bit unpack_sig3[PART_HI:PART_LO]; + initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI); - always @(posedge clk) begin - unpack_sig0[PART_LO] <= 1'b1; - unpack_sig1[PART_LO] <= 1'b1; - unpack_sig0 [PART_LO+1:FULL_HI] <= unpack_sig0[PART_LO:FULL_HI-1]; - unpack_sig1 [PART_LO+1:PART_HI] <= unpack_sig1[PART_LO:PART_HI-1]; - unpack_sig2[PART_LO] <= 1'b1; - unpack_sig3[PART_LO] <= 1'b1; - unpack_sig2 [FULL_HI:PART_LO+1] <= unpack_sig2[FULL_HI-1:PART_LO]; - unpack_sig3 [PART_HI:PART_LO+1] <= unpack_sig3[PART_HI-1:PART_LO]; - end + always @(posedge clk) begin + unpack_sig0[PART_LO] <= 1'b1; + unpack_sig1[PART_LO] <= 1'b1; + unpack_sig0[PART_LO+1:FULL_HI] <= unpack_sig0[PART_LO:FULL_HI-1]; + unpack_sig1[PART_LO+1:PART_HI] <= unpack_sig1[PART_LO:PART_HI-1]; + unpack_sig2[PART_LO] <= 1'b1; + unpack_sig3[PART_LO] <= 1'b1; + unpack_sig2[FULL_HI:PART_LO+1] <= unpack_sig2[FULL_HI-1:PART_LO]; + unpack_sig3[PART_HI:PART_LO+1] <= unpack_sig3[PART_HI-1:PART_LO]; + end - always @(posedge clk) begin - if (c >= 4) begin - if (!unpack_sig0[FULL_HI] || !unpack_sig1[PART_HI]) $stop; - if (!unpack_sig2[FULL_HI] || !unpack_sig3[PART_HI]) $stop; - end else begin - if (unpack_sig0[FULL_HI] || unpack_sig1[PART_HI]) $stop; - if (unpack_sig2[FULL_HI] || unpack_sig3[PART_HI]) $stop; - end - end + always @(posedge clk) begin + if (c >= 4) begin + if (!unpack_sig0[FULL_HI] || !unpack_sig1[PART_HI]) $stop; + if (!unpack_sig2[FULL_HI] || !unpack_sig3[PART_HI]) $stop; + end + else begin + if (unpack_sig0[FULL_HI] || unpack_sig1[PART_HI]) $stop; + if (unpack_sig2[FULL_HI] || unpack_sig3[PART_HI]) $stop; + end + end endmodule diff --git a/test_regress/t/t_unpacked_str_init.v b/test_regress/t/t_unpacked_str_init.v index 114c04d89..803b269a9 100644 --- a/test_regress/t/t_unpacked_str_init.v +++ b/test_regress/t/t_unpacked_str_init.v @@ -5,24 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - localparam string REGS [0:31] - = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", - "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", - "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", - "ft10", "ft11"}; - function string disasm32(logic [4:0] op); - return $sformatf("lui %s" , REGS[op]); - endfunction + // verilog_format: off + localparam string REGS [0:31] + = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", + "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", + "ft10", "ft11"}; + // verilog_format: on + function string disasm32(logic [4:0] op); + return $sformatf("lui %s", REGS[op]); + endfunction endpackage -module t(/*AUTOARG*/ - // Inputs - op - ); - import pkg::*; - input [4:0] op; - always_comb begin - $display("OP: 0x%08x: %s", op, disasm32(op)); - end +module t ( /*AUTOARG*/ + // Inputs + op +); + import pkg::*; + input [4:0] op; + always_comb begin + $display("OP: 0x%08x: %s", op, disasm32(op)); + end endmodule diff --git a/test_regress/t/t_unpacked_str_init2.v b/test_regress/t/t_unpacked_str_init2.v index 11a7dc7b4..344ad14ba 100644 --- a/test_regress/t/t_unpacked_str_init2.v +++ b/test_regress/t/t_unpacked_str_init2.v @@ -8,32 +8,34 @@ module t; - localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", - "t1", "t2", "s0/fp", "s1", "a0", "a1", - "a2", "a3", "a4", "a5", "a6", "a7", "s2", - "s3", "s4", "s5", "s6", "s7", "s8", "s9", - "s10", "s11", "t3", "t4", "t5", "t6"}; + // verilog_format: off + localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", + "t1", "t2", "s0/fp", "s1", "a0", "a1", + "a2", "a3", "a4", "a5", "a6", "a7", "s2", + "s3", "s4", "s5", "s6", "s7", "s8", "s9", + "s10", "s11", "t3", "t4", "t5", "t6"}; + // verilog_format: on - function automatic string reg_x (logic [4:0] r, bit abi=1'b0); - reg_x = abi ? REG_X[r] : $sformatf("x%0d", r); - endfunction + function automatic string reg_x(logic [4:0] r, bit abi = 1'b0); + reg_x = abi ? REG_X[r] : $sformatf("x%0d", r); + endfunction - // the issue is triggered by a second function containing a case statement - function automatic string f2 (logic [4:0] r, bit abi=0); - case (r) - 5'd0: f2 = $sformatf("nop"); - 5'd1: f2 = $sformatf("reg %s", reg_x(r[4:0], abi)); - default: f2 = $sformatf("ILLEGAL"); - endcase - endfunction + // the issue is triggered by a second function containing a case statement + function automatic string f2(logic [4:0] r, bit abi = 0); + case (r) + 5'd0: f2 = $sformatf("nop"); + 5'd1: f2 = $sformatf("reg %s", reg_x(r[4:0], abi)); + default: f2 = $sformatf("ILLEGAL"); + endcase + endfunction - initial begin - for (int unsigned i = 0; i < 32; ++i) begin - $display("REGX: %s", reg_x(i[4:0], 1'b1)); - end - $display("OP: %s", f2(5'd7)); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + for (int unsigned i = 0; i < 32; ++i) begin + $display("REGX: %s", reg_x(i[4:0], 1'b1)); + end + $display("OP: %s", f2(5'd7)); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_str_pair.v b/test_regress/t/t_unpacked_str_pair.v index 60b68735b..0a7b36845 100644 --- a/test_regress/t/t_unpacked_str_pair.v +++ b/test_regress/t/t_unpacked_str_pair.v @@ -6,44 +6,43 @@ module t; - typedef string array_of_string_t[]; + typedef string array_of_string_t[]; - typedef struct { - string positive; - string negative; - } filter_expression_parts_t; + typedef struct { + string positive; + string negative; + } filter_expression_parts_t; - function automatic array_of_string_t split_by_char(string c, string s); - string parts[$]; - int last_char_position = -1; + function automatic array_of_string_t split_by_char(string c, string s); + string parts[$]; + int last_char_position = -1; - for (int i = 0; i < s.len(); i++) begin - if (i == s.len()-1) - parts.push_back(s.substr(last_char_position+1, i)); - if (string'(s[i]) == c) begin - parts.push_back(s.substr(last_char_position+1, i-1)); - last_char_position = i; - end + for (int i = 0; i < s.len(); i++) begin + if (i == s.len() - 1) parts.push_back(s.substr(last_char_position + 1, i)); + if (string'(s[i]) == c) begin + parts.push_back(s.substr(last_char_position + 1, i - 1)); + last_char_position = i; end + end - $display("%p", parts); - return parts; - endfunction + $display("%p", parts); + return parts; + endfunction - function filter_expression_parts_t get_filter_expression_parts(string raw_filter); - string parts[]; - parts = split_by_char("-", raw_filter); - return '{ parts[0], parts[1] }; - endfunction + function filter_expression_parts_t get_filter_expression_parts(string raw_filter); + string parts[]; + parts = split_by_char("-", raw_filter); + return '{parts[0], parts[1]}; + endfunction - initial begin - automatic string raw_filter = "parta-partb"; - automatic filter_expression_parts_t parts = get_filter_expression_parts(raw_filter); - $display("%p", parts); - if (parts.positive != "parta") $stop; - if (parts.negative != "partb") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic string raw_filter = "parta-partb"; + automatic filter_expression_parts_t parts = get_filter_expression_parts(raw_filter); + $display("%p", parts); + if (parts.positive != "parta") $stop; + if (parts.negative != "partb") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_struct_eq.v b/test_regress/t/t_unpacked_struct_eq.v index 6f656dea9..4f4fe3388 100644 --- a/test_regress/t/t_unpacked_struct_eq.v +++ b/test_regress/t/t_unpacked_struct_eq.v @@ -5,52 +5,51 @@ // SPDX-License-Identifier: CC0-1.0 module t; - typedef struct{ - bit [31:0] subarr[4]; - } arr_str_t; - typedef struct { - string txt; - struct { - bit m0; - bit [3:0] m1; - bit [7:0] arr[2][3]; - arr_str_t str[5]; - } sub; - } struct_t; - struct_t s1; - struct_t s2; - struct_t s3; + typedef struct {bit [31:0] subarr[4];} arr_str_t; + typedef struct { + string txt; + struct { + bit m0; + bit [3:0] m1; + bit [7:0] arr[2][3]; + arr_str_t str[5]; + } sub; + } struct_t; + struct_t s1; + struct_t s2; + struct_t s3; - assign {s1.sub.m0, s1.sub.m1} = {1'b0, 4'h5}; - assign {s2.sub.m0, s2.sub.m1} = {1'b0, 4'h5}; - assign s1.txt = "text"; - assign s2.txt = "text"; + assign {s1.sub.m0, s1.sub.m1} = {1'b0, 4'h5}; + assign {s2.sub.m0, s2.sub.m1} = {1'b0, 4'h5}; + assign s1.txt = "text"; + assign s2.txt = "text"; - assign {s1.sub.arr[0][0], s2.sub.arr[0][0]} = {8'h01, 8'h01}; - assign {s1.sub.arr[0][1], s2.sub.arr[0][1]} = {8'h02, 8'h02}; - assign {s1.sub.arr[0][2], s2.sub.arr[0][2]} = {8'h03, 8'h03}; - assign {s1.sub.arr[1][0], s2.sub.arr[1][0]} = {8'h04, 8'h04}; - assign {s1.sub.arr[1][1], s2.sub.arr[1][1]} = {8'h05, 8'h05}; - assign {s1.sub.arr[1][2], s2.sub.arr[1][2]} = {8'h06, 8'h06}; + assign {s1.sub.arr[0][0], s2.sub.arr[0][0]} = {8'h01, 8'h01}; + assign {s1.sub.arr[0][1], s2.sub.arr[0][1]} = {8'h02, 8'h02}; + assign {s1.sub.arr[0][2], s2.sub.arr[0][2]} = {8'h03, 8'h03}; + assign {s1.sub.arr[1][0], s2.sub.arr[1][0]} = {8'h04, 8'h04}; + assign {s1.sub.arr[1][1], s2.sub.arr[1][1]} = {8'h05, 8'h05}; + assign {s1.sub.arr[1][2], s2.sub.arr[1][2]} = {8'h06, 8'h06}; - assign {s3.sub.m0, s3.sub.m1} = {1'b0, 4'h5}; - assign s3.txt = "text"; + assign {s3.sub.m0, s3.sub.m1} = {1'b0, 4'h5}; + assign s3.txt = "text"; - assign s3.sub.arr[0][0] = 8'h01; - assign s3.sub.arr[0][1] = 8'h02; - assign s3.sub.arr[0][2] = 8'h03; - assign s3.sub.arr[1][0] = 8'h24; // One mismatch - assign s3.sub.arr[1][1] = 8'h05; - assign s3.sub.arr[1][2] = 8'h06; + assign s3.sub.arr[0][0] = 8'h01; + assign s3.sub.arr[0][1] = 8'h02; + assign s3.sub.arr[0][2] = 8'h03; + assign s3.sub.arr[1][0] = 8'h24; // One mismatch + assign s3.sub.arr[1][1] = 8'h05; + assign s3.sub.arr[1][2] = 8'h06; - initial begin - #1; - if(s3 == s1) $stop; - if(s1 == s2 && s3 != s1) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - $fatal; - end + initial begin + #1; + if (s3 == s1) $stop; + if (s1 == s2 && s3 != s1) begin + $write("*-* All Finished *-*\n"); + $finish; end + else begin + $fatal; + end + end endmodule diff --git a/test_regress/t/t_unpacked_struct_redef.v b/test_regress/t/t_unpacked_struct_redef.v index 2ad084b83..5ca4fcfc8 100644 --- a/test_regress/t/t_unpacked_struct_redef.v +++ b/test_regress/t/t_unpacked_struct_redef.v @@ -4,23 +4,23 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Class#(parameter WIDTH); - typedef logic [WIDTH-1:0] word; - typedef struct { - word w; - } Struct; +class Class #( + parameter WIDTH +); + typedef logic [WIDTH-1:0] word; + typedef struct {word w;} Struct; endclass module t; - Class#(1)::Struct s1; - Class#(1)::Struct s2; - Class#(2)::Struct s3; + Class #(1)::Struct s1; + Class #(1)::Struct s2; + Class #(2)::Struct s3; - initial begin - $display("%p", s1); - $display("%p", s2); - $display("%p", s3); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("%p", s1); + $display("%p", s2); + $display("%p", s3); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_struct_sel.v b/test_regress/t/t_unpacked_struct_sel.v index db59b70eb..78789aa8c 100644 --- a/test_regress/t/t_unpacked_struct_sel.v +++ b/test_regress/t/t_unpacked_struct_sel.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -typedef struct { - bit [3:0] byte_en; -} my_struct; +typedef struct {bit [3:0] byte_en;} my_struct; module t; - initial begin - my_struct ms; - ms.byte_en[0] = 1; - if (ms.byte_en[0] != 1) $stop; + initial begin + my_struct ms; + ms.byte_en[0] = 1; + if (ms.byte_en[0] != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unpacked_to_packed_param.v b/test_regress/t/t_unpacked_to_packed_param.v index 69a37d234..ca3a6b23a 100644 --- a/test_regress/t/t_unpacked_to_packed_param.v +++ b/test_regress/t/t_unpacked_to_packed_param.v @@ -4,35 +4,28 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + localparam logic [1:0][7:0] foo_unpacked[2:0] = '{"12", "34", "56"}; + localparam logic [2:0][1:0][7:0] foo_packed = '{"12", "34", "56"}; - localparam logic [1:0][7:0] foo_unpacked [2:0] = '{"12", "34", "56"}; - localparam logic [2:0][1:0][7:0] foo_packed = '{"12", "34", "56"}; + sub #(.foos({foo_unpacked[0], foo_unpacked[1], foo_unpacked[2]})) the_unpacked_sub (); - sub #( - .foos ({foo_unpacked[0], foo_unpacked[1], foo_unpacked[2]}) - ) the_unpacked_sub(); - - sub #( - .foos ({foo_packed[0], foo_packed[1], foo_packed[2]}) - ) the_packed_sub(); + sub #(.foos({foo_packed[0], foo_packed[1], foo_packed[2]})) the_packed_sub (); endmodule module sub #( parameter logic [2:0][1:0][7:0] foos ); - initial begin - if (foos != "563412") $stop; - end + initial begin + if (foos != "563412") $stop; + end endmodule diff --git a/test_regress/t/t_unpacked_to_queue.v b/test_regress/t/t_unpacked_to_queue.v index fdd4e99dd..fc010313a 100644 --- a/test_regress/t/t_unpacked_to_queue.v +++ b/test_regress/t/t_unpacked_to_queue.v @@ -7,96 +7,90 @@ // verilog_format: off `define stop $stop() -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", \ - `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); \ - `stop; end while(0); -`define checks(gotv,expv) do if ((gotv) != (expv)) begin \ - $write("%%Error: %s:%0d: got='%s' exp='%s'\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on +class check #( + parameter WIDTH = 8 +); + static function automatic void check_array(int n, logic [WIDTH-1:0] array[]); + for (int r = 0; r < n; r++) begin + `checkh(array[r], WIDTH'(r)) + end + endfunction -class check #(parameter WIDTH=8); - static function automatic void check_array (int n, - logic [WIDTH-1:0] array []); - for (int r=0; r 1); i++) begin - tmp[i] <= tmp[i-i]; - end - if (tmp[0] != 4'b0000) $stop; - if (tmp[3] != 4'b0011) $stop; + // Test loop + always @(posedge clk) begin + int i; + int j; + for (i = 0; (i < 4) && (i > 1); i++) begin + tmp[i] <= tmp[i-i]; + end + if (tmp[0] != 4'b0000) $stop; + if (tmp[3] != 4'b0011) $stop; - j = 0; for (i=$c32("1"); i<3; ++i) j++; - if (j!=2) $stop; - j = 0; for (i=1; i<$c32("3"); ++i) j++; - if (j!=2) $stop; - j = 0; for (i=1; i<3; i=i+$c32("1")) j++; - if (j!=2) $stop; + j = 0; + for (i = $c32("1"); i < 3; ++i) j++; + if (j != 2) $stop; + j = 0; + for (i = 1; i < $c32("3"); ++i) j++; + if (j != 2) $stop; + j = 0; + for (i = 1; i < 3; i = i + $c32("1")) j++; + if (j != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unroll_delay.v b/test_regress/t/t_unroll_delay.v index 59985b851..9914b81a4 100644 --- a/test_regress/t/t_unroll_delay.v +++ b/test_regress/t/t_unroll_delay.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer i; - integer j; + integer i; + integer j; - always @(i, j) $display("[%0t] B %0d %0d", $time, i, j); + always @(i, j) $display("[%0t] B %0d %0d", $time, i, j); - // See issue #4237 + // See issue #4237 - initial begin - for(i = 1; i < 3 ; i = i + 1) begin - $display(""); - for(j = 6; j < 8; j = j + 1) begin - $display("[%0t] A %0d %0d", $time, i, j); - #1; - $display("[%0t] C %0d %0d", $time, i, j); - end - #9; + initial begin + for (i = 1; i < 3; i = i + 1) begin + $display(""); + for (j = 6; j < 8; j = j + 1) begin + $display("[%0t] A %0d %0d", $time, i, j); + #1; + $display("[%0t] C %0d %0d", $time, i, j); end - #10; - $write("*-* All Finished *-*\n"); - $finish; - end + #9; + end + #10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unroll_forfor.v b/test_regress/t/t_unroll_forfor.v index 20aed5e4a..bdf1db6a5 100644 --- a/test_regress/t/t_unroll_forfor.v +++ b/test_regress/t/t_unroll_forfor.v @@ -8,28 +8,28 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk, in - ); - input clk; - input [71:0] in; + // Inputs + clk, in + ); + input clk; + input [71:0] in; - reg [71:0] in_tmp; + reg [71:0] in_tmp; - localparam [71:0] TEST_PARAM = {72{1'b0}}; + localparam [71:0] TEST_PARAM = {72{1'b0}}; - // Test loop - always @* - begin: testmap - byte i, j; - // bug1044 - for ( i = 0; i < 9; i = i + 1 ) - // verilator lint_off WIDTH - for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin - in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; - end - // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @* + begin: testmap + byte i, j; + // bug1044 + for ( i = 0; i < 9; i = i + 1 ) + // verilator lint_off WIDTH + for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin + in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; + end + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unroll_genf.v b/test_regress/t/t_unroll_genf.v index 4ddabf1f2..ee2302f87 100644 --- a/test_regress/t/t_unroll_genf.v +++ b/test_regress/t/t_unroll_genf.v @@ -5,26 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 //bug830 -module sub(); +module sub (); endmodule function integer cdiv(input integer x); - begin - cdiv = 10; - end + begin + cdiv = 10; + end endfunction module t; - genvar j; - generate - for (j = 0; j < cdiv(10); j=j+1) - sub #() sub (); // #() for code coverage in verilog.y - endgenerate + genvar j; + generate + for (j = 0; j < cdiv(10); j = j + 1) sub #() sub (); // #() for code coverage in verilog.y + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unroll_pragma.v b/test_regress/t/t_unroll_pragma.v index 281caf8b4..8b256a568 100644 --- a/test_regress/t/t_unroll_pragma.v +++ b/test_regress/t/t_unroll_pragma.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef TEST_DISABLE `define PRAGMA /*verilator unroll_disable*/ `elsif TEST_FULL @@ -11,35 +12,36 @@ `elsif TEST_NONE `define PRAGMA `endif +// verilog_format: on module t; - int i, j; + int i, j; - // This must always unroll - for (genvar g = 0; g < 10; ++g) begin - initial $c("gened();"); - end + // This must always unroll + for (genvar g = 0; g < 10; ++g) begin + initial $c("gened();"); + end - initial begin - // Test a loop equal to --unroll-count - should unroll without pragma + initial begin + // Test a loop equal to --unroll-count - should unroll without pragma + `PRAGMA + for (i = 0; i < 4; ++i) begin `PRAGMA - for (i = 0; i < 4; ++i) begin - `PRAGMA - for (j = 0; j < 4; ++j) begin - $c("small();"); - end + for (j = 0; j < 4; ++j) begin + $c("small();"); end - // Test a loop larger than --unroll-count + end + // Test a loop larger than --unroll-count + `PRAGMA + for (i = 0; i < 5; ++i) begin `PRAGMA - for (i = 0; i < 5; ++i) begin - `PRAGMA - for (j = 0; j < 5; ++j) begin - $c("large();"); - end + for (j = 0; j < 5; ++j) begin + $c("large();"); end - $write("*-* All Finished *-*\n"); - $finish; - end + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v index 68347998c..1ce4850a4 100644 --- a/test_regress/t/t_unroll_signed.v +++ b/test_regress/t/t_unroll_signed.v @@ -4,149 +4,146 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - // Check empty blocks - task EmptyFor; - /* verilator public */ - integer i; - begin - for (i = 0; i < 2; i = i+1) - begin - end + // Check empty blocks + task EmptyFor; + /* verilator public */ + integer i; + begin + for (i = 0; i < 2; i = i + 1) begin end - endtask + end + endtask - // Check look unroller - reg signed signed_tests_only = 1'sb1; - integer total; + // Check look unroller + reg signed signed_tests_only = 1'sb1; + integer total; - integer i; - reg [31:0] iu; - reg [31:0] dly_to_ensure_was_unrolled [1:0]; - reg [2:0] i3; + integer i; + reg [31:0] iu; + reg [31:0] dly_to_ensure_was_unrolled[1:0]; + reg [2:0] i3; - integer cyc; initial cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - case (cyc) - 1: begin - // >= signed - total = 0; - for (i=5; i>=0; i=i-1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -21) $stop; + integer cyc; + initial cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + case (cyc) + 1: begin + // >= signed + total = 0; + for (i = 5; i >= 0; i = i - 1) begin + total = total - i - 1; + dly_to_ensure_was_unrolled[i] <= i; end - 2: begin - // > signed - total = 0; - for (i=5; i>0; i=i-1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -20) $stop; + if (total != -21) $stop; + end + 2: begin + // > signed + total = 0; + for (i = 5; i > 0; i = i - 1) begin + total = total - i - 1; + dly_to_ensure_was_unrolled[i] <= i; end - 3: begin - // < signed - total = 0; - for (i=1; i<5; i=i+1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -14) $stop; + if (total != -20) $stop; + end + 3: begin + // < signed + total = 0; + for (i = 1; i < 5; i = i + 1) begin + total = total - i - 1; + dly_to_ensure_was_unrolled[i] <= i; end - 4: begin - // <= signed - total = 0; - for (i=1; i<=5; i=i+1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -20) $stop; + if (total != -14) $stop; + end + 4: begin + // <= signed + total = 0; + for (i = 1; i <= 5; i = i + 1) begin + total = total - i - 1; + dly_to_ensure_was_unrolled[i] <= i; end - // UNSIGNED - 5: begin - // >= unsigned - total = 0; - for (iu=5; iu>=1; iu=iu-1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -20) $stop; + if (total != -20) $stop; + end + // UNSIGNED + 5: begin + // >= unsigned + total = 0; + for (iu = 5; iu >= 1; iu = iu - 1) begin + total = total - iu - 1; + dly_to_ensure_was_unrolled[iu] <= iu; end - 6: begin - // > unsigned - total = 0; - for (iu=5; iu>1; iu=iu-1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -18) $stop; + if (total != -20) $stop; + end + 6: begin + // > unsigned + total = 0; + for (iu = 5; iu > 1; iu = iu - 1) begin + total = total - iu - 1; + dly_to_ensure_was_unrolled[iu] <= iu; end - 7: begin - // < unsigned - total = 0; - for (iu=1; iu<5; iu=iu+1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -14) $stop; + if (total != -18) $stop; + end + 7: begin + // < unsigned + total = 0; + for (iu = 1; iu < 5; iu = iu + 1) begin + total = total - iu - 1; + dly_to_ensure_was_unrolled[iu] <= iu; end - 8: begin - // <= unsigned - total = 0; - for (iu=1; iu<=5; iu=iu+1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -20) $stop; + if (total != -14) $stop; + end + 8: begin + // <= unsigned + total = 0; + for (iu = 1; iu <= 5; iu = iu + 1) begin + total = total - iu - 1; + dly_to_ensure_was_unrolled[iu] <= iu; end - //=== - 9: begin - // mostly cover a small index - total = 0; - for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; + if (total != -20) $stop; + end + //=== + 9: begin + // mostly cover a small index + total = 0; + for (i3 = 3'd0; i3 < 3'd7; i3 = i3 + 3'd1) begin + total = total - {29'd0, i3} - 1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; end - //=== - 10: begin - // mostly cover a small index - total = 0; - for (i3=0; i3<3'd7; i3=i3+3'd1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; + if (total != -28) $stop; + end + //=== + 10: begin + // mostly cover a small index + total = 0; + for (i3 = 0; i3 < 3'd7; i3 = i3 + 3'd1) begin + total = total - {29'd0, i3} - 1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; end - //=== - 11: begin - // width violation on <, causes extend - total = 0; - for (i3=3'd0; i3<7; i3=i3+1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; + if (total != -28) $stop; + end + //=== + 11: begin + // width violation on <, causes extend + total = 0; + for (i3 = 3'd0; i3 < 7; i3 = i3 + 1) begin + total = total - {29'd0, i3} - 1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; end - //=== - // width violation on <, causes extend signed - // Unsupported as yet - //=== - 19: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - end + if (total != -28) $stop; + end + //=== + // width violation on <, causes extend signed + // Unsupported as yet + //=== + 19: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end endmodule diff --git a/test_regress/t/t_unroll_unopt_io.v b/test_regress/t/t_unroll_unopt_io.v index 22135915a..6b71b5ace 100644 --- a/test_regress/t/t_unroll_unopt_io.v +++ b/test_regress/t/t_unroll_unopt_io.v @@ -4,23 +4,23 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - zeros, - // Inputs - num - ); +module t ( /*AUTOARG*/ + // Outputs + zeros, + // Inputs + num +); - parameter WIDTH = 1; - input logic [WIDTH-1:0] num; - output logic [$clog2(WIDTH+1)-1:0] zeros; + parameter WIDTH = 1; + input logic [WIDTH-1:0] num; + output logic [$clog2(WIDTH+1)-1:0] zeros; - integer i; + integer i; - always_comb begin - i = 0; - while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1; - zeros = i[$clog2(WIDTH+1) - 1 : 0]; - end + always_comb begin + i = 0; + while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1; + zeros = i[$clog2(WIDTH+1)-1 : 0]; + end endmodule diff --git a/test_regress/t/t_upd_nonsequential.v b/test_regress/t/t_upd_nonsequential.v index bdb5b1d80..c9496ea84 100644 --- a/test_regress/t/t_upd_nonsequential.v +++ b/test_regress/t/t_upd_nonsequential.v @@ -4,65 +4,66 @@ // SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg a, b, sel, z; - udp_mux2(z, a, b, sel); +module t ( + input clk +); - int cycle=0; + reg a, b, sel, z; + udp_mux2( + z, a, b, sel + ); - always @(posedge clk) begin - cycle <= cycle+1; - if (cycle==0) begin - a = 0; - b = 1; - sel = 0; - end - else if (cycle==1) begin - a = 1; - b = 1; - sel = 0; - if (z != 0) $stop; - end - else if (cycle==2) begin - a = 0; - b = 1; - sel = 0; - if (z != 1) $stop; - end - else if (cycle==3) begin - a = 1; - b = 0; - sel = 0; - if (z != 0) $stop; - end - else if (cycle==4) begin - if (z != 1) $stop; - end - else if (cycle >= 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cycle = 0; + + always @(posedge clk) begin + cycle <= cycle + 1; + if (cycle == 0) begin + a = 0; + b = 1; + sel = 0; + end + else if (cycle == 1) begin + a = 1; + b = 1; + sel = 0; + if (z != 0) $stop; + end + else if (cycle == 2) begin + a = 0; + b = 1; + sel = 0; + if (z != 1) $stop; + end + else if (cycle == 3) begin + a = 1; + b = 0; + sel = 0; + if (z != 0) $stop; + end + else if (cycle == 4) begin + if (z != 1) $stop; + end + else if (cycle >= 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -primitive udp_mux2 (z, a, b, sel); - output z; - input a, b, sel; - table - //a b s o - ? 1 1 : 1 ; - ? 0 1 : 0 ; - 1 ? 0 : 1 ; - 0 ? 0 : 0 ; - 1 1 x : 1 ; - // Next blank line is intentional for parser +primitive udp_mux2(z, a, b, sel); + output z; + input a, b, sel; + table + //a b s o + ? 1 1 : 1; + ? 0 1 : 0; + 1 ? 0 : 1; + 0 ? 0 : 0; + 1 1 x : 1; + // Next blank line is intentional for parser - // Next \ at EOL is intentional for parser - 0 0 x \ + // Next \ at EOL is intentional for parser + 0 0 x \ : 0 ; - endtable + endtable endprimitive diff --git a/test_regress/t/t_urandom.v b/test_regress/t/t_urandom.v index 84fab0440..14c2de0db 100644 --- a/test_regress/t/t_urandom.v +++ b/test_regress/t/t_urandom.v @@ -11,86 +11,86 @@ module t; `ifndef VERILATOR - `define PROC + `define PROC `endif `ifdef PROC - process p; + process p; `endif - int unsigned v1; - int unsigned v2; - int unsigned v3; - string s; + int unsigned v1; + int unsigned v2; + int unsigned v3; + string s; - initial begin + initial begin `ifdef PROC - if (p != null) $stop; - p = process::self(); + if (p != null) $stop; + p = process::self(); `endif - v1 = $urandom; - v2 = $urandom; - v3 = $urandom(); - if (v1 == v2 && v1 == v3) $stop; // Possible, but 2^-64 + v1 = $urandom; + v2 = $urandom; + v3 = $urandom(); + if (v1 == v2 && v1 == v3) $stop; // Possible, but 2^-64 - // Range - v2 = $urandom_range(v1, v1); - if (v1 != v2) $stop; + // Range + v2 = $urandom_range(v1, v1); + if (v1 != v2) $stop; - v2 = $urandom_range(0, 32'hffffffff); - if (v2 == v1) $stop; + v2 = $urandom_range(0, 32'hffffffff); + if (v2 == v1) $stop; - for (int test = 0; test < 20; ++test) begin - v1 = 2; - v1 = $urandom_range(0, v1); - if (v1 != 0 && v1 != 1 && v1 != 2) $stop; - v1 = $urandom_range(2, 0); - if (v1 != 0 && v1 != 1 && v1 !=2) $stop; - v1 = $urandom_range(3); - if (v1 != 0 && v1 != 1 && v1 != 2 && v1 != 3) $stop; - end + for (int test = 0; test < 20; ++test) begin + v1 = 2; + v1 = $urandom_range(0, v1); + if (v1 != 0 && v1 != 1 && v1 != 2) $stop; + v1 = $urandom_range(2, 0); + if (v1 != 0 && v1 != 1 && v1 != 2) $stop; + v1 = $urandom_range(3); + if (v1 != 0 && v1 != 1 && v1 != 2 && v1 != 3) $stop; + end - // Seed stability - // Note UVM doesn't use $urandom seeding - v1 = $urandom(1); - v2 = $urandom(1); - if (v1 != v2) $stop; - v2 = $urandom(1); - if (v1 != v2) $stop; + // Seed stability + // Note UVM doesn't use $urandom seeding + v1 = $urandom(1); + v2 = $urandom(1); + if (v1 != v2) $stop; + v2 = $urandom(1); + if (v1 != v2) $stop; `ifdef PROC - // Seed stability via process.srandom - p.srandom(1); - v1 = $urandom(); - p.srandom(1); - v2 = $urandom(); - if (v1 != v2) $stop; - p.srandom(1); - v2 = $urandom(); - if (v1 != v2) $stop; + // Seed stability via process.srandom + p.srandom(1); + v1 = $urandom(); + p.srandom(1); + v2 = $urandom(); + if (v1 != v2) $stop; + p.srandom(1); + v2 = $urandom(); + if (v1 != v2) $stop; - // Seed stability via process.srandom - p.srandom(32'h88888888); // "Large" seed to check a VlRNG::srandom edge case - v1 = $urandom(); - p.srandom(32'h88888888); - v2 = $urandom(); - if (v1 != v2) $stop; - p.srandom(32'h88888888); - v2 = $urandom(); - if (v1 != v2) $stop; + // Seed stability via process.srandom + p.srandom(32'h88888888); // "Large" seed to check a VlRNG::srandom edge case + v1 = $urandom(); + p.srandom(32'h88888888); + v2 = $urandom(); + if (v1 != v2) $stop; + p.srandom(32'h88888888); + v2 = $urandom(); + if (v1 != v2) $stop; - // Seed stability via process.get_randstate - s = p.get_randstate(); - v1 = $urandom(); - p.set_randstate(s); - v2 = $urandom(); - if (v1 != v2) $stop; - p.set_randstate(s); - v2 = $urandom(); - if (v1 != v2) $stop; + // Seed stability via process.get_randstate + s = p.get_randstate(); + v1 = $urandom(); + p.set_randstate(s); + v2 = $urandom(); + if (v1 != v2) $stop; + p.set_randstate(s); + v2 = $urandom(); + if (v1 != v2) $stop; `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_user_type_xassign.v b/test_regress/t/t_user_type_xassign.v index 70f8f5dca..46688194d 100644 --- a/test_regress/t/t_user_type_xassign.v +++ b/test_regress/t/t_user_type_xassign.v @@ -4,40 +4,35 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + typedef logic [31:0] int_t; + typedef int_t [6:0] bar_t; + bar_t the_bar; - typedef logic [31:0] int_t; - typedef int_t [6:0] bar_t; - bar_t the_bar; + logic [31:0] thing_one; + always_comb begin + for (int sel = 0; sel < 1; sel++) thing_one = the_bar[sel]; + end - logic [31:0] thing_one; - always_comb begin - for (int sel = 0; sel < 1; sel++) - thing_one = the_bar[sel]; - end + virtual class SomeClass; + static function logic compare(int a, int b); + return a > b; + endfunction + endclass - virtual class SomeClass; - static function logic compare(int a, int b); - return a > b; - endfunction - endclass + logic [31:0] thing_two; + always_comb begin + for (int sel_a = 0; sel_a < 1; sel_a++) thing_two = the_bar[sel_a]; + end - logic [31:0] thing_two; - always_comb begin - for (int sel_a = 0; sel_a < 1; sel_a++) - thing_two = the_bar[sel_a]; - end - - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index 11f243c2e..49a881f79 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -8,48 +8,48 @@ module t; - task check (integer line, real got, real expec); - real delta; - delta = got-expec; - if (delta > 0.001 || delta < -0.001) begin - $write("Line%0d: Got %g Exp %g\n", line, got, expec); - $stop; - end - endtask + task check(integer line, real got, real expec); + real delta; + delta = got - expec; + if (delta > 0.001 || delta < -0.001) begin + $write("Line%0d: Got %g Exp %g\n", line, got, expec); + $stop; + end + endtask - wreal wr; - assign wr = 1.1; + wreal wr; + assign wr = 1.1; - sub sub (.*); + sub sub (.*); - initial begin - check(`__LINE__, asin(0.5) , 0.523599); - check(`__LINE__, asinh(0.5) , 0.481212); - check(`__LINE__, atan(0.5) , 0.463648); - check(`__LINE__, atan2(0.5, 0.3) , 1.03038); - check(`__LINE__, atanh(0.5) , 0.549306); - check(`__LINE__, ceil(2.5) , 3.0); - check(`__LINE__, cos(0.5) , 0.877583); - check(`__LINE__, cosh(0.5) , 1.12763); - check(`__LINE__, exp(2.0) , 7.38906); - check(`__LINE__, floor(2.5) , 2.0); - check(`__LINE__, ln(2.0) , 0.693147); - check(`__LINE__, log(2.0) , 0.30103); - check(`__LINE__, pow(2.0,2.0) , 4.0); - check(`__LINE__, sin(0.5) , 0.479426); - check(`__LINE__, sinh(0.5) , 0.521095); - check(`__LINE__, sqrt(2.0) , 1.414); - check(`__LINE__, tan(0.5) , 0.546302); - check(`__LINE__, tanh(0.5) , 0.462117); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + check(`__LINE__, asin(0.5), 0.523599); + check(`__LINE__, asinh(0.5), 0.481212); + check(`__LINE__, atan(0.5), 0.463648); + check(`__LINE__, atan2(0.5, 0.3), 1.03038); + check(`__LINE__, atanh(0.5), 0.549306); + check(`__LINE__, ceil(2.5), 3.0); + check(`__LINE__, cos(0.5), 0.877583); + check(`__LINE__, cosh(0.5), 1.12763); + check(`__LINE__, exp(2.0), 7.38906); + check(`__LINE__, floor(2.5), 2.0); + check(`__LINE__, ln(2.0), 0.693147); + check(`__LINE__, log(2.0), 0.30103); + check(`__LINE__, pow(2.0, 2.0), 4.0); + check(`__LINE__, sin(0.5), 0.479426); + check(`__LINE__, sinh(0.5), 0.521095); + check(`__LINE__, sqrt(2.0), 1.414); + check(`__LINE__, tan(0.5), 0.546302); + check(`__LINE__, tanh(0.5), 0.462117); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub ( - input wreal wr - ); - initial begin - if (wr != 1.1) $stop; - end + input wreal wr +); + initial begin + if (wr != 1.1) $stop; + end endmodule diff --git a/test_regress/t/t_vams_kwd_bad.out b/test_regress/t/t_vams_kwd_bad.out index 0cea02097..fc9738f5f 100644 --- a/test_regress/t/t_vams_kwd_bad.out +++ b/test_regress/t/t_vams_kwd_bad.out @@ -1,201 +1,201 @@ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' - 12 | int above; - | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:7: Unsupported: AMS reserved word not implemented: 'above' + 12 | int above; + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting '(' - 12 | int above; - | ^ +%Error: t/t_vams_kwd_bad.v:12:12: syntax error, unexpected ';', expecting '(' + 12 | int above; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:13:8: Unsupported: AMS reserved word not implemented: 'abs' - 13 | int abs; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:14:8: Unsupported: AMS reserved word not implemented: 'absdelay' - 14 | int absdelay; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:15:8: Unsupported: AMS reserved word not implemented: 'abstol' - 15 | int abstol; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:16:8: Unsupported: AMS reserved word not implemented: 'ac_stim' - 16 | int ac_stim; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:17:8: Unsupported: AMS reserved word not implemented: 'access' - 17 | int access; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:18:8: Unsupported: AMS reserved word not implemented: 'acos' - 18 | int acos; - | ^~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:19:8: Unsupported: AMS reserved word not implemented: 'acosh' - 19 | int acosh; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:20:8: Unsupported: AMS reserved word not implemented: 'aliasparam' - 20 | int aliasparam; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:21:8: Unsupported: AMS reserved word not implemented: 'analog' - 21 | int analog; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:22:8: Unsupported: AMS reserved word not implemented: 'analysis' - 22 | int analysis; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:23:8: Unsupported: AMS reserved word not implemented: 'assert' - 23 | int assert; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:24:8: Unsupported: AMS reserved word not implemented: 'branch' - 24 | int branch; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:25:8: Unsupported: AMS reserved word not implemented: 'connect' - 25 | int connect; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:26:8: Unsupported: AMS reserved word not implemented: 'connectmodule' - 26 | int connectmodule; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:27:8: Unsupported: AMS reserved word not implemented: 'connectrules' - 27 | int connectrules; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:28:8: Unsupported: AMS reserved word not implemented: 'continuous' - 28 | int continuous; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:29:8: Unsupported: AMS reserved word not implemented: 'cross' - 29 | int cross; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:30:8: Unsupported: AMS reserved word not implemented: 'ddt' - 30 | int ddt; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:31:8: Unsupported: AMS reserved word not implemented: 'ddt_nature' - 31 | int ddt_nature; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:32:8: Unsupported: AMS reserved word not implemented: 'ddx' - 32 | int ddx; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:33:8: Unsupported: AMS reserved word not implemented: 'discipline' - 33 | int discipline; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:34:8: Unsupported: AMS reserved word not implemented: 'discrete' - 34 | int discrete; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:35:8: Unsupported: AMS reserved word not implemented: 'domain' - 35 | int domain; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:36:8: Unsupported: AMS reserved word not implemented: 'driver_update' - 36 | int driver_update; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:37:8: Unsupported: AMS reserved word not implemented: 'endconnectrules' - 37 | int endconnectrules; - | ^~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:38:8: Unsupported: AMS reserved word not implemented: 'enddiscipline' - 38 | int enddiscipline; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:39:8: Unsupported: AMS reserved word not implemented: 'endnature' - 39 | int endnature; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:40:8: Unsupported: AMS reserved word not implemented: 'endparamset' - 40 | int endparamset; - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:41:8: Unsupported: AMS reserved word not implemented: 'exclude' - 41 | int exclude; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:42:8: Unsupported: AMS reserved word not implemented: 'final_step' - 42 | int final_step; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:43:8: Unsupported: AMS reserved word not implemented: 'flicker_noise' - 43 | int flicker_noise; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:44:8: Unsupported: AMS reserved word not implemented: 'flow' - 44 | int flow; - | ^~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:45:8: Unsupported: AMS reserved word not implemented: 'from' - 45 | int from; - | ^~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:46:8: Unsupported: AMS reserved word not implemented: 'ground' - 46 | int ground; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:47:8: Unsupported: AMS reserved word not implemented: 'idt' - 47 | int idt; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:48:8: Unsupported: AMS reserved word not implemented: 'idt_nature' - 48 | int idt_nature; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:49:8: Unsupported: AMS reserved word not implemented: 'idtmod' - 49 | int idtmod; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:50:8: Unsupported: AMS reserved word not implemented: 'inf' - 50 | int inf; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:51:8: Unsupported: AMS reserved word not implemented: 'initial_step' - 51 | int initial_step; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:52:8: Unsupported: AMS reserved word not implemented: 'laplace_nd' - 52 | int laplace_nd; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:53:8: Unsupported: AMS reserved word not implemented: 'laplace_np' - 53 | int laplace_np; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:54:8: Unsupported: AMS reserved word not implemented: 'laplace_zd' - 54 | int laplace_zd; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:55:8: Unsupported: AMS reserved word not implemented: 'laplace_zp' - 55 | int laplace_zp; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:56:8: Unsupported: AMS reserved word not implemented: 'last_crossing' - 56 | int last_crossing; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:57:8: Unsupported: AMS reserved word not implemented: 'limexp' - 57 | int limexp; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:58:8: Unsupported: AMS reserved word not implemented: 'max' - 58 | int max; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:59:8: Unsupported: AMS reserved word not implemented: 'merged' - 59 | int merged; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:60:8: Unsupported: AMS reserved word not implemented: 'min' - 60 | int min; - | ^~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:61:8: Unsupported: AMS reserved word not implemented: 'nature' - 61 | int nature; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:62:8: Unsupported: AMS reserved word not implemented: 'net_resolution' - 62 | int net_resolution; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:63:8: Unsupported: AMS reserved word not implemented: 'noise_table' - 63 | int noise_table; - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:64:8: Unsupported: AMS reserved word not implemented: 'paramset' - 64 | int paramset; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:65:8: Unsupported: AMS reserved word not implemented: 'potential' - 65 | int potential; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:66:8: Unsupported: AMS reserved word not implemented: 'resolveto' - 66 | int resolveto; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:67:8: Unsupported: AMS reserved word not implemented: 'slew' - 67 | int slew; - | ^~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:68:8: Unsupported: AMS reserved word not implemented: 'split' - 68 | int split; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:69:8: Unsupported: AMS reserved word not implemented: 'timer' - 69 | int timer; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:70:8: Unsupported: AMS reserved word not implemented: 'transition' - 70 | int transition; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:71:8: Unsupported: AMS reserved word not implemented: 'units' - 71 | int units; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:72:8: Unsupported: AMS reserved word not implemented: 'white_noise' - 72 | int white_noise; - | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:73:8: Unsupported: AMS reserved word not implemented: 'zi_nd' - 73 | int zi_nd; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:74:8: Unsupported: AMS reserved word not implemented: 'zi_np' - 74 | int zi_np; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:75:8: Unsupported: AMS reserved word not implemented: 'zi_zd' - 75 | int zi_zd; - | ^~~~~ -%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:76:8: Unsupported: AMS reserved word not implemented: 'zi_zp' - 76 | int zi_zp; - | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:13:7: Unsupported: AMS reserved word not implemented: 'abs' + 13 | int abs; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:14:7: Unsupported: AMS reserved word not implemented: 'absdelay' + 14 | int absdelay; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:15:7: Unsupported: AMS reserved word not implemented: 'abstol' + 15 | int abstol; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:16:7: Unsupported: AMS reserved word not implemented: 'ac_stim' + 16 | int ac_stim; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:17:7: Unsupported: AMS reserved word not implemented: 'access' + 17 | int access; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:18:7: Unsupported: AMS reserved word not implemented: 'acos' + 18 | int acos; + | ^~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:19:7: Unsupported: AMS reserved word not implemented: 'acosh' + 19 | int acosh; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:20:7: Unsupported: AMS reserved word not implemented: 'aliasparam' + 20 | int aliasparam; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:21:7: Unsupported: AMS reserved word not implemented: 'analog' + 21 | int analog; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:22:7: Unsupported: AMS reserved word not implemented: 'analysis' + 22 | int analysis; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:23:7: Unsupported: AMS reserved word not implemented: 'assert' + 23 | int assert; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:24:7: Unsupported: AMS reserved word not implemented: 'branch' + 24 | int branch; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:25:7: Unsupported: AMS reserved word not implemented: 'connect' + 25 | int connect; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:26:7: Unsupported: AMS reserved word not implemented: 'connectmodule' + 26 | int connectmodule; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:27:7: Unsupported: AMS reserved word not implemented: 'connectrules' + 27 | int connectrules; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:28:7: Unsupported: AMS reserved word not implemented: 'continuous' + 28 | int continuous; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:29:7: Unsupported: AMS reserved word not implemented: 'cross' + 29 | int cross; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:30:7: Unsupported: AMS reserved word not implemented: 'ddt' + 30 | int ddt; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:31:7: Unsupported: AMS reserved word not implemented: 'ddt_nature' + 31 | int ddt_nature; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:32:7: Unsupported: AMS reserved word not implemented: 'ddx' + 32 | int ddx; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:33:7: Unsupported: AMS reserved word not implemented: 'discipline' + 33 | int discipline; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:34:7: Unsupported: AMS reserved word not implemented: 'discrete' + 34 | int discrete; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:35:7: Unsupported: AMS reserved word not implemented: 'domain' + 35 | int domain; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:36:7: Unsupported: AMS reserved word not implemented: 'driver_update' + 36 | int driver_update; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:37:7: Unsupported: AMS reserved word not implemented: 'endconnectrules' + 37 | int endconnectrules; + | ^~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:38:7: Unsupported: AMS reserved word not implemented: 'enddiscipline' + 38 | int enddiscipline; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:39:7: Unsupported: AMS reserved word not implemented: 'endnature' + 39 | int endnature; + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:40:7: Unsupported: AMS reserved word not implemented: 'endparamset' + 40 | int endparamset; + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:41:7: Unsupported: AMS reserved word not implemented: 'exclude' + 41 | int exclude; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:42:7: Unsupported: AMS reserved word not implemented: 'final_step' + 42 | int final_step; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:43:7: Unsupported: AMS reserved word not implemented: 'flicker_noise' + 43 | int flicker_noise; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:44:7: Unsupported: AMS reserved word not implemented: 'flow' + 44 | int flow; + | ^~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:45:7: Unsupported: AMS reserved word not implemented: 'from' + 45 | int from; + | ^~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:46:7: Unsupported: AMS reserved word not implemented: 'ground' + 46 | int ground; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:47:7: Unsupported: AMS reserved word not implemented: 'idt' + 47 | int idt; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:48:7: Unsupported: AMS reserved word not implemented: 'idt_nature' + 48 | int idt_nature; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:49:7: Unsupported: AMS reserved word not implemented: 'idtmod' + 49 | int idtmod; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:50:7: Unsupported: AMS reserved word not implemented: 'inf' + 50 | int inf; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:51:7: Unsupported: AMS reserved word not implemented: 'initial_step' + 51 | int initial_step; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:52:7: Unsupported: AMS reserved word not implemented: 'laplace_nd' + 52 | int laplace_nd; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:53:7: Unsupported: AMS reserved word not implemented: 'laplace_np' + 53 | int laplace_np; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:54:7: Unsupported: AMS reserved word not implemented: 'laplace_zd' + 54 | int laplace_zd; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:55:7: Unsupported: AMS reserved word not implemented: 'laplace_zp' + 55 | int laplace_zp; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:56:7: Unsupported: AMS reserved word not implemented: 'last_crossing' + 56 | int last_crossing; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:57:7: Unsupported: AMS reserved word not implemented: 'limexp' + 57 | int limexp; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:58:7: Unsupported: AMS reserved word not implemented: 'max' + 58 | int max; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:59:7: Unsupported: AMS reserved word not implemented: 'merged' + 59 | int merged; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:60:7: Unsupported: AMS reserved word not implemented: 'min' + 60 | int min; + | ^~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:61:7: Unsupported: AMS reserved word not implemented: 'nature' + 61 | int nature; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:62:7: Unsupported: AMS reserved word not implemented: 'net_resolution' + 62 | int net_resolution; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:63:7: Unsupported: AMS reserved word not implemented: 'noise_table' + 63 | int noise_table; + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:64:7: Unsupported: AMS reserved word not implemented: 'paramset' + 64 | int paramset; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:65:7: Unsupported: AMS reserved word not implemented: 'potential' + 65 | int potential; + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:66:7: Unsupported: AMS reserved word not implemented: 'resolveto' + 66 | int resolveto; + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:67:7: Unsupported: AMS reserved word not implemented: 'slew' + 67 | int slew; + | ^~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:68:7: Unsupported: AMS reserved word not implemented: 'split' + 68 | int split; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:69:7: Unsupported: AMS reserved word not implemented: 'timer' + 69 | int timer; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:70:7: Unsupported: AMS reserved word not implemented: 'transition' + 70 | int transition; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:71:7: Unsupported: AMS reserved word not implemented: 'units' + 71 | int units; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:72:7: Unsupported: AMS reserved word not implemented: 'white_noise' + 72 | int white_noise; + | ^~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:73:7: Unsupported: AMS reserved word not implemented: 'zi_nd' + 73 | int zi_nd; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:74:7: Unsupported: AMS reserved word not implemented: 'zi_np' + 74 | int zi_np; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:75:7: Unsupported: AMS reserved word not implemented: 'zi_zd' + 75 | int zi_zd; + | ^~~~~ +%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:76:7: Unsupported: AMS reserved word not implemented: 'zi_zp' + 76 | int zi_zp; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_vams_kwd_bad.v b/test_regress/t/t_vams_kwd_bad.v index d20e82d24..d189970d8 100644 --- a/test_regress/t/t_vams_kwd_bad.v +++ b/test_regress/t/t_vams_kwd_bad.v @@ -8,71 +8,71 @@ module t; - // Just get errors on bad keywords (for code coverage) - int above; - int abs; - int absdelay; - int abstol; - int ac_stim; - int access; - int acos; - int acosh; - int aliasparam; - int analog; - int analysis; - int assert; - int branch; - int connect; - int connectmodule; - int connectrules; - int continuous; - int cross; - int ddt; - int ddt_nature; - int ddx; - int discipline; - int discrete; - int domain; - int driver_update; - int endconnectrules; - int enddiscipline; - int endnature; - int endparamset; - int exclude; - int final_step; - int flicker_noise; - int flow; - int from; - int ground; - int idt; - int idt_nature; - int idtmod; - int inf; - int initial_step; - int laplace_nd; - int laplace_np; - int laplace_zd; - int laplace_zp; - int last_crossing; - int limexp; - int max; - int merged; - int min; - int nature; - int net_resolution; - int noise_table; - int paramset; - int potential; - int resolveto; - int slew; - int split; - int timer; - int transition; - int units; - int white_noise; - int zi_nd; - int zi_np; - int zi_zd; - int zi_zp; + // Just get errors on bad keywords (for code coverage) + int above; + int abs; + int absdelay; + int abstol; + int ac_stim; + int access; + int acos; + int acosh; + int aliasparam; + int analog; + int analysis; + int assert; + int branch; + int connect; + int connectmodule; + int connectrules; + int continuous; + int cross; + int ddt; + int ddt_nature; + int ddx; + int discipline; + int discrete; + int domain; + int driver_update; + int endconnectrules; + int enddiscipline; + int endnature; + int endparamset; + int exclude; + int final_step; + int flicker_noise; + int flow; + int from; + int ground; + int idt; + int idt_nature; + int idtmod; + int inf; + int initial_step; + int laplace_nd; + int laplace_np; + int laplace_zd; + int laplace_zp; + int last_crossing; + int limexp; + int max; + int merged; + int min; + int nature; + int net_resolution; + int noise_table; + int paramset; + int potential; + int resolveto; + int slew; + int split; + int timer; + int transition; + int units; + int white_noise; + int zi_nd; + int zi_np; + int zi_zd; + int zi_zp; endmodule diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v index 6964449f2..573354526 100644 --- a/test_regress/t/t_vams_wreal.v +++ b/test_regress/t/t_vams_wreal.v @@ -6,132 +6,151 @@ `begin_keywords "VAMS-2.3" -module t (/*autoarg*/ - // Inputs - clk, in - ); +module t ( /*autoarg*/ + // Inputs + clk, + in +); - input clk; + input clk; - input [15:0] in; - wreal aout; + input [15:0] in; + wreal aout; - integer cyc = 0; + integer cyc = 0; - real vin; - wreal vpass; - through through (.vin, .vpass); + real vin; + wreal vpass; + through through ( + .vin, + .vpass + ); - real gnd; - wire out; - within_range within_range (/*AUTOINST*/ - // Interfaces - .vpass (vpass), - .gnd (gnd), - // Outputs - .out (out)); + real gnd; + wire out; + within_range within_range ( /*AUTOINST*/ + // Interfaces + .vpass(vpass), + .gnd(gnd), + // Outputs + .out(out) + ); - // wreal bus declaration - wreal vin_upper_bus[1:0]; + // wreal bus declaration + wreal vin_upper_bus[1:0]; - // wreal nets declaration - wreal vout_split_0; - wreal vout_split_1; + // wreal nets declaration + wreal vout_split_0; + wreal vout_split_1; - wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]), - .vout_split_0(vout_split_0), - .vout_split_1(vout_split_1)); + wreal_bus wreal_bus ( + .vin_bus(vin_upper_bus[1:0]), + .vout_split_0(vout_split_0), + .vout_split_1(vout_split_1) + ); - // implicit declaration of wreal + // implicit declaration of wreal `ifdef VERILATOR - wreal wreal_implicit_net; // implicit declaration of wreal not supported yet + wreal wreal_implicit_net; // implicit declaration of wreal not supported yet `endif - // verilator lint_off IMPLICIT - first_level first_level(.in(cyc[0]), .out(wreal_implicit_net)); - // verilator lint_on IMPLICIT + // verilator lint_off IMPLICIT + first_level first_level ( + .in(cyc[0]), + .out(wreal_implicit_net) + ); + // verilator lint_on IMPLICIT - parameter real LSB = 1; - // verilator lint_off WIDTH - assign aout = $itor(in) * LSB; - // verilator lint_on WIDTH + parameter real LSB = 1; + // verilator lint_off WIDTH + assign aout = $itor(in) * LSB; + // verilator lint_on WIDTH - always @ (posedge clk) begin - cyc <= cyc + 1; + always @(posedge clk) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int); + $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int); `endif - if (cyc==0) begin - // Setup - gnd = 0.0; - vin = 0.2; - end - else if (cyc==2) begin - if (out != 0) $stop; - end - else if (cyc==3) begin - gnd = 0.0; - vin = 0.6; - end - else if (cyc==4) begin - if (out != 1) $stop; - end - else if (cyc==5) begin - gnd = 0.6; - vin = 0.8; - end - else if (cyc==6) begin - if (out != 0) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 0) begin + // Setup + gnd = 0.0; + vin = 0.2; + end + else if (cyc == 2) begin + if (out != 0) $stop; + end + else if (cyc == 3) begin + gnd = 0.0; + vin = 0.6; + end + else if (cyc == 4) begin + if (out != 1) $stop; + end + else if (cyc == 5) begin + gnd = 0.6; + vin = 0.8; + end + else if (cyc == 6) begin + if (out != 0) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module through - (input wreal vin, - output wreal vpass); - assign vpass = vin; +module through ( + input wreal vin, + output wreal vpass +); + assign vpass = vin; endmodule -module within_range - (input wreal vpass, - input wreal gnd, - output out); +module within_range ( + input wreal vpass, + input wreal gnd, + output out +); - parameter real V_MIN = 0.5; - parameter real V_MAX = 10; + parameter real V_MIN = 0.5; + parameter real V_MAX = 10; - wreal in_int = vpass - gnd; - assign out = (V_MIN <= in_int && in_int <= V_MAX); + wreal in_int = vpass - gnd; + assign out = (V_MIN <= in_int && in_int <= V_MAX); endmodule -module wreal_bus - (input wreal vin_bus [1:0], - output wreal vout_split_0, - output wreal vout_split_1); - assign vout_split_0 = vin_bus[0]; - assign vout_split_1 = vin_bus[1]; +module wreal_bus ( + input wreal vin_bus[1:0], + output wreal vout_split_0, + output wreal vout_split_1 +); + assign vout_split_0 = vin_bus[0]; + assign vout_split_1 = vin_bus[1]; endmodule -module first_level - (input in, +module first_level ( + input in, `ifdef VERILATOR - output wreal out + output wreal out `else - output out // Implicity becomes real + output out // Implicity becomes real `endif ); - second_level second_level(.in(in), .out(out)); + second_level second_level ( + .in(in), + .out(out) + ); endmodule -module second_level(in, out); - input in; - output out; - wreal out; - assign out = in ? 1.23456: 7.8910; +module second_level ( + in, + out +); + input in; + output out; + wreal out; + assign out = in ? 1.23456 : 7.8910; endmodule diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v index 67669486b..02c2fda7b 100644 --- a/test_regress/t/t_var_assign_landr.v +++ b/test_regress/t/t_var_assign_landr.v @@ -4,88 +4,88 @@ // SPDX-FileCopyrightText: 2014 // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [255:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [255:0] sum; - // Take CRC data and apply to testblock inputs - wire [127:0] in = {~crc[63:0], crc[63:0]}; + // Take CRC data and apply to testblock inputs + wire [127:0] in = {~crc[63:0], crc[63:0]}; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [127:0] o1; // From test of Test.v - wire [127:0] o2; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [127:0] o1; // From test of Test.v + wire [127:0] o2; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .o1 (o1[127:0]), - .o2 (o2[127:0]), - // Inputs - .in (in[127:0])); + Test test ( /*AUTOINST*/ + // Outputs + .o1(o1[127:0]), + .o2(o2[127:0]), + // Inputs + .in(in[127:0]) + ); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2); + $write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {o1, o2} ^ {sum[254:0], sum[255] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - o1, o2, - // Inputs - in - ); +module Test ( /*AUTOARG*/ + // Outputs + o1, + o2, + // Inputs + in +); - input [127:0] in; - output logic [127:0] o1; - output logic [127:0] o2; + input [127:0] in; + output logic [127:0] o1; + output logic [127:0] o2; - always_comb begin: b_test - logic [127:0] tmpp; - logic [127:0] tmp; - tmp = '0; - tmpp = '0; + always_comb begin : b_test + logic [127:0] tmpp; + logic [127:0] tmp; + tmp = '0; + tmpp = '0; - tmp[63:0] = in[63:0]; - tmpp[63:0] = in[63:0]; + tmp[63:0] = in[63:0]; + tmpp[63:0] = in[63:0]; - tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; - tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; + tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; + tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; - o1 = tmp; - o2 = tmpp; - end + o1 = tmp; + o2 = tmpp; + end endmodule diff --git a/test_regress/t/t_var_bad_hide.out b/test_regress/t/t_var_bad_hide.out index 2abf987c3..7a8caf706 100644 --- a/test_regress/t/t_var_bad_hide.out +++ b/test_regress/t/t_var_bad_hide.out @@ -1,15 +1,15 @@ -%Warning-VARHIDDEN: t/t_var_bad_hide.v:16:14: Declaration of signal hides declaration in upper scope: 'top' - 16 | output top; - | ^~~ - t/t_var_bad_hide.v:13:12: ... Location of original declaration - 13 | integer top; +%Warning-VARHIDDEN: t/t_var_bad_hide.v:16:12: Declaration of signal hides declaration in upper scope: 'top' + 16 | output top; | ^~~ + t/t_var_bad_hide.v:13:11: ... Location of original declaration + 13 | integer top; + | ^~~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. -%Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' - 22 | integer top; - | ^~~ - t/t_var_bad_hide.v:13:12: ... Location of original declaration - 13 | integer top; - | ^~~ +%Warning-VARHIDDEN: t/t_var_bad_hide.v:23:15: Declaration of signal hides declaration in upper scope: 'top' + 23 | integer top; + | ^~~ + t/t_var_bad_hide.v:13:11: ... Location of original declaration + 13 | integer top; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide.v b/test_regress/t/t_var_bad_hide.v index 61fa93949..1b33db2ba 100644 --- a/test_regress/t/t_var_bad_hide.v +++ b/test_regress/t/t_var_bad_hide.v @@ -6,21 +6,22 @@ module t; - // Check that the lint_on is obeyed. - // verilator lint_off VARHIDDEN - // verilator lint_on VARHIDDEN + // Check that the lint_on is obeyed. + // verilator lint_off VARHIDDEN + // verilator lint_on VARHIDDEN - integer top; + integer top; - task x; - output top; - begin end - endtask + task x; + output top; + begin + end + endtask - initial begin - begin: lower - integer top; - end - end + initial begin + begin : lower + integer top; + end + end endmodule diff --git a/test_regress/t/t_var_bad_hide2.out b/test_regress/t/t_var_bad_hide2.out index fbb05eba6..be5b268db 100644 --- a/test_regress/t/t_var_bad_hide2.out +++ b/test_regress/t/t_var_bad_hide2.out @@ -1,6 +1,6 @@ -%Warning-VARHIDDEN: t/t_var_bad_hide2.v:14:12: Declaration of signal hides declaration in upper scope: 't' - 14 | integer t; - | ^ +%Warning-VARHIDDEN: t/t_var_bad_hide2.v:16:11: Declaration of signal hides declaration in upper scope: 't' + 16 | integer t; + | ^ t/t_var_bad_hide2.v:7:8: ... Location of original declaration 7 | module t; | ^ diff --git a/test_regress/t/t_var_bad_hide2.v b/test_regress/t/t_var_bad_hide2.v index 125de7068..486d73e99 100644 --- a/test_regress/t/t_var_bad_hide2.v +++ b/test_regress/t/t_var_bad_hide2.v @@ -6,11 +6,13 @@ module t; - // Arguable, but we won't throw a hidden warning on tcp_port - parameter tcp_port = 5678; - import "DPI-C" function int dpii_func ( input integer tcp_port, - output longint obj ); - // 't' is hidden: - integer t; + // Arguable, but we won't throw a hidden warning on tcp_port + parameter tcp_port = 5678; + import "DPI-C" function int dpii_func( + input integer tcp_port, + output longint obj + ); + // 't' is hidden: + integer t; endmodule diff --git a/test_regress/t/t_var_bad_sameas.out b/test_regress/t/t_var_bad_sameas.out index 951de49df..9262423db 100644 --- a/test_regress/t/t_var_bad_sameas.out +++ b/test_regress/t/t_var_bad_sameas.out @@ -1,32 +1,32 @@ -%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Instance has the same name as variable: 'varfirst' - 10 | sub varfirst (); - | ^~~~~~~~ - t/t_var_bad_sameas.v:9:12: ... Location of original declaration - 9 | integer varfirst; - | ^~~~~~~~ +%Error: t/t_var_bad_sameas.v:10:7: Unsupported in C: Instance has the same name as variable: 'varfirst' + 10 | sub varfirst (); + | ^~~~~~~~ + t/t_var_bad_sameas.v:9:11: ... Location of original declaration + 9 | integer varfirst; + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as instance: 'varfirst' - 11 | task varfirst; begin end endtask - | ^~~~~~~~ - t/t_var_bad_sameas.v:10:8: ... Location of original declaration - 10 | sub varfirst (); +%Error: t/t_var_bad_sameas.v:11:8: Unsupported in C: Task has the same name as instance: 'varfirst' + 11 | task varfirst; | ^~~~~~~~ -%Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as instance: 'cellfirst' - 14 | integer cellfirst; - | ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as instance: 'cellfirst' - 15 | task cellfirst; begin end endtask - | ^~~~~~~~~ - t/t_var_bad_sameas.v:13:8: ... Location of original declaration - 13 | sub cellfirst (); + t/t_var_bad_sameas.v:10:7: ... Location of original declaration + 10 | sub varfirst (); + | ^~~~~~~~ +%Error: t/t_var_bad_sameas.v:17:11: Unsupported in C: Variable has same name as instance: 'cellfirst' + 17 | integer cellfirst; + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:18:8: Unsupported in C: Task has the same name as instance: 'cellfirst' + 18 | task cellfirst; | ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst' - 18 | integer taskfirst; - | ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Instance has the same name as task: 'taskfirst' - 19 | sub taskfirst (); + t/t_var_bad_sameas.v:16:7: ... Location of original declaration + 16 | sub cellfirst (); + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:27:11: Unsupported in C: Variable has same name as task: 'taskfirst' + 27 | integer taskfirst; + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:28:7: Unsupported in C: Instance has the same name as task: 'taskfirst' + 28 | sub taskfirst (); + | ^~~~~~~~~ + t/t_var_bad_sameas.v:23:8: ... Location of original declaration + 23 | task taskfirst; | ^~~~~~~~~ - t/t_var_bad_sameas.v:17:9: ... Location of original declaration - 17 | task taskfirst; begin end endtask - | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sameas.v b/test_regress/t/t_var_bad_sameas.v index 9b6f2bf64..9fd1f16d4 100644 --- a/test_regress/t/t_var_bad_sameas.v +++ b/test_regress/t/t_var_bad_sameas.v @@ -6,17 +6,26 @@ module t; - integer varfirst; - sub varfirst (); // Error: Cell hits var - task varfirst; begin end endtask // Error: Task hits var + integer varfirst; + sub varfirst (); // Error: Cell hits var + task varfirst; + begin + end + endtask // Error: Task hits var - sub cellfirst (); - integer cellfirst; // Error: Var hits cell - task cellfirst; begin end endtask // Error: Task hits cell + sub cellfirst (); + integer cellfirst; // Error: Var hits cell + task cellfirst; + begin + end + endtask // Error: Task hits cell - task taskfirst; begin end endtask - integer taskfirst; // Error: Var hits task - sub taskfirst (); // Error: Cell hits task + task taskfirst; + begin + end + endtask + integer taskfirst; // Error: Var hits task + sub taskfirst (); // Error: Cell hits task endmodule diff --git a/test_regress/t/t_var_bad_sv.out b/test_regress/t/t_var_bad_sv.out index 4c9859480..649ade6d6 100644 --- a/test_regress/t/t_var_bad_sv.out +++ b/test_regress/t/t_var_bad_sv.out @@ -1,12 +1,12 @@ -%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. +%Error: t/t_var_bad_sv.v:8:7: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. : ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. - 8 | reg do; - | ^~ + 8 | reg do; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. - 9 | mod mod (.do(bar)); - | ^~ -%Error: t/t_var_bad_sv.v:9:16: syntax error, unexpected '(', expecting ')' - 9 | mod mod (.do(bar)); - | ^ +%Error: t/t_var_bad_sv.v:9:13: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. + 9 | mod mod (.do(bar)); + | ^~ +%Error: t/t_var_bad_sv.v:9:15: syntax error, unexpected '(', expecting ')' + 9 | mod mod (.do(bar)); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sv.v b/test_regress/t/t_var_bad_sv.v index 70ddfa56a..7d1ebb272 100644 --- a/test_regress/t/t_var_bad_sv.v +++ b/test_regress/t/t_var_bad_sv.v @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg do; - mod mod (.do(bar)); + reg do; + mod mod (.do(bar)); endmodule diff --git a/test_regress/t/t_var_const.v b/test_regress/t/t_var_const.v index 8133f9bbf..aa1d2dc76 100644 --- a/test_regress/t/t_var_const.v +++ b/test_regress/t/t_var_const.v @@ -4,24 +4,21 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + const logic [2:0] five = 3'd5; - const logic [2:0] five = 3'd5; + const logic unsigned [31:0] var_const = 22; + logic [7:0] res_const; + assign res_const = var_const[7:0]; // bug693 - const logic unsigned [31:0] var_const = 22; - logic [7:0] res_const; - assign res_const = var_const[7:0]; // bug693 - - always @ (posedge clk) begin - if (five !== 3'd5) $stop; - if (res_const !== 8'd22) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (five !== 3'd5) $stop; + if (res_const !== 8'd22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_const_bad.out b/test_regress/t/t_var_const_bad.out index 8190ff1ed..08c56c9ad 100644 --- a/test_regress/t/t_var_const_bad.out +++ b/test_regress/t/t_var_const_bad.out @@ -1,6 +1,6 @@ -%Error-CONSTWRITTEN: t/t_var_const_bad.v:17:7: Writing to 'const' data-typed variable 'five' (IEEE 1800-2023 6.20.6) +%Error-CONSTWRITTEN: t/t_var_const_bad.v:14:5: Writing to 'const' data-typed variable 'five' (IEEE 1800-2023 6.20.6) : ... note: In instance 't' - 17 | five = 3'd4; - | ^~~~ + 14 | five = 3'd4; + | ^~~~ ... For error description see https://verilator.org/warn/CONSTWRITTEN?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_var_const_bad.v b/test_regress/t/t_var_const_bad.v index 08498d485..f0dea4acb 100644 --- a/test_regress/t/t_var_const_bad.v +++ b/test_regress/t/t_var_const_bad.v @@ -4,20 +4,17 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + const logic [2:0] five = 3'd5; - const logic [2:0] five = 3'd5; - - always @ (posedge clk) begin - five = 3'd4; - if (five !== 3'd5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + five = 3'd4; + if (five !== 3'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_dotted1.v b/test_regress/t/t_var_dotted1.v index 260c0fb91..ba5fe46b2 100644 --- a/test_regress/t/t_var_dotted1.v +++ b/test_regress/t/t_var_dotted1.v @@ -4,100 +4,101 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - // verilator lint_off MULTIDRIVEN + // verilator lint_off MULTIDRIVEN - wire [31:0] outb0c0; - wire [31:0] outb0c1; - wire [31:0] outb1c0; - wire [31:0] outb1c1; + wire [31:0] outb0c0; + wire [31:0] outb0c1; + wire [31:0] outb1c0; + wire [31:0] outb1c1; - reg [7:0] lclmem [7:0]; + reg [7:0] lclmem[7:0]; - ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1), - .outb1c0(outb1c0), .outb1c1(outb1c1) - ); + ma ma0 ( + .outb0c0(outb0c0), + .outb0c1(outb0c1), + .outb1c0(outb1c0), + .outb1c1(outb1c1) + ); - global_mod #(32'hf00d) global_cell (); - global_mod #(32'hf22d) global_cell2 (); + global_mod #(32'hf00d) global_cell (); + global_mod #(32'hf22d) global_cell2 (); - input clk; - integer cyc=1; - always @ (posedge clk) begin - cyc <= cyc + 1; + integer cyc = 1; + always @(posedge clk) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); + $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); `endif - if (cyc==2) begin - if (global_cell.globali != 32'hf00d) $stop; - if (global_cell2.globali != 32'hf22d) $stop; - if ($root.t.global_cell.globali != 32'hf00d) $stop; - if ($root.t.global_cell2.globali != 32'hf22d) $stop; - if (outb0c0 != 32'h00) $stop; - if (outb0c1 != 32'h01) $stop; - if (outb1c0 != 32'h10) $stop; - if (outb1c1 != 32'h11) $stop; - end - if (cyc==3) begin - // Can we scope down and read and write vars? - ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100; - ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100; - ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100; - ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100; - end - if (cyc==4) begin - // Can we do dotted's inside array sels? - ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12; - lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24; - if (outb0c0 != 32'h100) $stop; - if (outb0c1 != 32'h101) $stop; - if (outb1c0 != 32'h110) $stop; - if (outb1c1 != 32'h111) $stop; - end - if (cyc==5) begin - if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop; - if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop; - if (outb0c0 != 32'h1100) $stop; - if (outb0c1 != 32'h2101) $stop; - if (outb1c0 != 32'h2110) $stop; - if (outb1c1 != 32'h3111) $stop; - end - if (cyc==6) begin - if (outb0c0 != 32'h31100) $stop; - if (outb0c1 != 32'h02101) $stop; - if (outb1c0 != 32'h42110) $stop; - if (outb1c1 != 32'h03111) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 2) begin + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf22d) $stop; + if ($root.t.global_cell.globali != 32'hf00d) $stop; + if ($root.t.global_cell2.globali != 32'hf22d) $stop; + if (outb0c0 != 32'h00) $stop; + if (outb0c1 != 32'h01) $stop; + if (outb1c0 != 32'h10) $stop; + if (outb1c1 != 32'h11) $stop; + end + if (cyc == 3) begin + // Can we scope down and read and write vars? + ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100; + ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100; + ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100; + ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100; + end + if (cyc == 4) begin + // Can we do dotted's inside array sels? + ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12; + lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24; + if (outb0c0 != 32'h100) $stop; + if (outb0c1 != 32'h101) $stop; + if (outb1c0 != 32'h110) $stop; + if (outb1c1 != 32'h111) $stop; + end + if (cyc == 5) begin + if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop; + if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop; + if (outb0c0 != 32'h1100) $stop; + if (outb0c1 != 32'h2101) $stop; + if (outb1c0 != 32'h2110) $stop; + if (outb1c1 != 32'h3111) $stop; + end + if (cyc == 6) begin + if (outb0c0 != 32'h31100) $stop; + if (outb0c1 != 32'h02101) $stop; + if (outb1c0 != 32'h42110) $stop; + if (outb1c1 != 32'h03111) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule `ifdef USE_INLINE_MID - `define INLINE_MODULE /*verilator inline_module*/ - `define INLINE_MID_MODULE /*verilator no_inline_module*/ +`define INLINE_MODULE /*verilator inline_module*/ +`define INLINE_MID_MODULE /*verilator no_inline_module*/ `else - `ifdef USE_INLINE - `define INLINE_MODULE /*verilator inline_module*/ - `define INLINE_MID_MODULE /*verilator inline_module*/ - `else - `define INLINE_MODULE /*verilator public_module*/ - `define INLINE_MID_MODULE /*verilator public_module*/ - `endif +`ifdef USE_INLINE +`define INLINE_MODULE /*verilator inline_module*/ +`define INLINE_MID_MODULE /*verilator inline_module*/ +`else +`define INLINE_MODULE /*verilator public_module*/ +`define INLINE_MID_MODULE /*verilator public_module*/ +`endif `endif module global_mod; - `INLINE_MODULE - parameter INITVAL = 0; - integer globali; - initial globali = INITVAL; + `INLINE_MODULE + parameter INITVAL = 0; + integer globali; + initial globali = INITVAL; endmodule module ma ( @@ -105,72 +106,83 @@ module ma ( output wire [31:0] outb0c1, output wire [31:0] outb1c0, output wire [31:0] outb1c1 - ); - `INLINE_MODULE +); + `INLINE_MODULE - reg [7:0] rmtmem [7:0]; + reg [7:0] rmtmem[7:0]; - mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1)); - mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1)); + mb #(0) mb0 ( + .outc0(outb0c0), + .outc1(outb0c1) + ); + mb #(1) mb1 ( + .outc0(outb1c0), + .outc1(outb1c1) + ); endmodule module mb ( output wire [31:0] outc0, output wire [31:0] outc1 - ); - `INLINE_MID_MODULE - parameter P2 = 0; - mc #(P2,0) mc0 (.out(outc0)); - mc #(P2,1) mc1 (.out(outc1)); - global_mod #(32'hf33d) global_cell2 (); +); + `INLINE_MID_MODULE + parameter P2 = 0; + mc #(P2, 0) mc0 (.out(outc0)); + mc #(P2, 1) mc1 (.out(outc1)); + global_mod #(32'hf33d) global_cell2 (); - wire reach_up_clk = t.clk; - always @(reach_up_clk) begin - if (P2==0) begin // Only for mb0 - if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances - if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances - if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances - if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances - if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances - if (outc0 !== mc0.out) $stop; // Lower instances + wire reach_up_clk = t.clk; + always @(reach_up_clk) begin + if (P2 == 0) begin // Only for mb0 + // verilog_format: off + if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances + if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances + if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances + if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances + if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances + if (outc0 !== mc0.out) $stop; // Lower instances - if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances - if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances - if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances - if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances - if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances - if (outc1 !== mc1.out) $stop; // Lower instances - end - end + if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances + if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances + if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances + if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances + if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances + if (outc1 !== mc1.out) $stop; // Lower instances + // verilog_format: on + end + end endmodule -module mc (output reg [31:0] out); - `INLINE_MODULE - parameter P2 = 0; - parameter P3 = 0; - initial begin - out = {24'h0,P2[3:0],P3[3:0]}; - //$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out); - end +module mc ( + output reg [31:0] out +); + `INLINE_MODULE + parameter P2 = 0; + parameter P3 = 0; + initial begin + out = {24'h0, P2[3:0], P3[3:0]}; + //$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out); + end - // Can we look from the top module name down? - wire [31:0] reach_up_cyc = t.cyc; + // Can we look from the top module name down? + wire [31:0] reach_up_cyc = t.cyc; - always @ (posedge t.clk) begin - //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); - if (reach_up_cyc==2) begin - if (global_cell.globali != 32'hf00d) $stop; - if (global_cell2.globali != 32'hf33d) $stop; + always @(posedge t.clk) begin + //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); + if (reach_up_cyc == 2) begin + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf33d) $stop; + end + if (reach_up_cyc == 4) begin + out[15:12] <= {P2[3:0] + P3[3:0] + 4'd1}; + end + if (reach_up_cyc == 5) begin + // Can we set another instance? + if (P3 == 1) begin // Without this, there are two possible correct answers... + mc0.out[19:16] <= {mc0.out[19:16] + P2[3:0] + P3[3:0] + 4'd2}; + $display("%m Set %x->%x %x %x %x %x", mc0.out, {mc0.out[19:16] + P2[3:0] + P3[3:0] + 4'd2 + }, mc0.out[19:16], P2[3:0], P3[3:0], 4'd2); end - if (reach_up_cyc==4) begin - out[15:12] <= {P2[3:0]+P3[3:0]+4'd1}; - end - if (reach_up_cyc==5) begin - // Can we set another instance? - if (P3==1) begin // Without this, there are two possible correct answers... - mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}; - $display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2); - end - end - end + end + end endmodule diff --git a/test_regress/t/t_var_dotted2.v b/test_regress/t/t_var_dotted2.v index 0730d90ff..048a38db8 100644 --- a/test_regress/t/t_var_dotted2.v +++ b/test_regress/t/t_var_dotted2.v @@ -12,121 +12,139 @@ module t; -`define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core -`define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core -`define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core -`define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core + `define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core + `define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core + `define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core + `define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core - initial begin - `DRAM1(0)[3] = 130; - `DRAM1(1)[3] = 131; - `DRAM2(0)[3] = 230; - `DRAM2(1)[3] = 231; - `DRAM3(0)[3] = 330; - `DRAM3(1)[3] = 331; - `DRAM4(0)[3] = 430; - `DRAM4(1)[3] = 431; - if (`DRAM1(0)[3] !== 130) $stop; - if (`DRAM1(1)[3] !== 131) $stop; - if (`DRAM2(0)[3] !== 230) $stop; - if (`DRAM2(1)[3] !== 231) $stop; - if (`DRAM3(0)[3] !== 330) $stop; - if (`DRAM3(1)[3] !== 331) $stop; - if (`DRAM4(0)[3] !== 430) $stop; - if (`DRAM4(1)[3] !== 431) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `DRAM1(0) [3] = 130; + `DRAM1(1) [3] = 131; + `DRAM2(0) [3] = 230; + `DRAM2(1) [3] = 231; + `DRAM3(0) [3] = 330; + `DRAM3(1) [3] = 331; + `DRAM4(0) [3] = 430; + `DRAM4(1) [3] = 431; + if (`DRAM1(0) [3] !== 130) $stop; + if (`DRAM1(1) [3] !== 131) $stop; + if (`DRAM2(0) [3] !== 230) $stop; + if (`DRAM2(1) [3] !== 231) $stop; + if (`DRAM3(0) [3] !== 330) $stop; + if (`DRAM3(1) [3] !== 331) $stop; + if (`DRAM4(0) [3] !== 430) $stop; + if (`DRAM4(1) [3] !== 431) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - eh2_lsu_dccm_mem mem (/*AUTOINST*/); + eh2_lsu_dccm_mem mem ( /*AUTOINST*/); endmodule -module eh2_lsu_dccm_mem -#( - DCCM_INDEX_DEPTH = 8192, - DCCM_NUM_BANKS = 2 - )( -); - `INLINE_MODULE +module eh2_lsu_dccm_mem #( + DCCM_INDEX_DEPTH = 8192, + DCCM_NUM_BANKS = 2 +) (); + `INLINE_MODULE - // 8 Banks, 16KB each (2048 x 72) - for (genvar i=0; i= 34) && (dbgsel_d1r < 65))) begin - // verilator lint_on WIDTH - dout0 = dval1; - end - else begin - dout0 = 0; - end - end + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval1; + end + else begin + dout0 = 0; + end + end - always @(posedge clk) begin - if ((rstn == 0)) begin - dbgsel_d1r <= 0; - end - else begin - dbgsel_d1r <= dbgsel; - end - end + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end endmodule -module sub1 - ( - /*AUTOARG*/ - // Outputs - dout1, - // Inputs - rstn, clk, dval1, dbgsel - ); +module sub1 ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, + clk, + dval1, + dbgsel +); - input rstn; - input clk; - input [7:0] dval1; - input [7:0] dbgsel; - output reg [7:0] dout1; + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; - always_comb begin - // verilator lint_off WIDTH - if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin - // verilator lint_on WIDTH - dout1 = dval1; - end - else begin - dout1 = 0; - end - end + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin + // verilator lint_on WIDTH + dout1 = dval1; + end + else begin + dout1 = 0; + end + end - always @(posedge clk) begin - if ((rstn == 0)) begin - dbgsel_d1r <= 0; - end - else begin - dbgsel_d1r <= dbgsel; - end - end + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end endmodule diff --git a/test_regress/t/t_var_overwidth_bad.v b/test_regress/t/t_var_overwidth_bad.v index 3f0709c9b..90972a42c 100644 --- a/test_regress/t/t_var_overwidth_bad.v +++ b/test_regress/t/t_var_overwidth_bad.v @@ -6,15 +6,12 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_overzero.v b/test_regress/t/t_var_overzero.v index 5cd28f4c6..689314990 100644 --- a/test_regress/t/t_var_overzero.v +++ b/test_regress/t/t_var_overzero.v @@ -4,170 +4,184 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - dout, - // Inputs - clk, rstn, dval0, dval1 - ); +module t ( /*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, + rstn, + dval0, + dval1 +); - input clk; - input rstn; - output wire [7:0] dout; + input clk; + input rstn; + output wire [7:0] dout; - input [7:0] dval0; - input [7:0] dval1; - wire [7:0] dbgsel_w = '0; + input [7:0] dval0; + input [7:0] dval1; + wire [7:0] dbgsel_w = '0; - tsub tsub (/*AUTOINST*/ - // Outputs - .dout (dout[7:0]), - // Inputs - .clk (clk), - .rstn (rstn), - .dval0 (dval0[7:0]), - .dval1 (dval1[7:0]), - .dbgsel_w (dbgsel_w[7:0])); + tsub tsub ( /*AUTOINST*/ + // Outputs + .dout(dout[7:0]), + // Inputs + .clk(clk), + .rstn(rstn), + .dval0(dval0[7:0]), + .dval1(dval1[7:0]), + .dbgsel_w(dbgsel_w[7:0]) + ); endmodule -module tsub (/*AUTOARG*/ - // Outputs - dout, - // Inputs - clk, rstn, dval0, dval1, dbgsel_w - ); +module tsub ( /*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, + rstn, + dval0, + dval1, + dbgsel_w +); - input clk; - input rstn; - input [7:0] dval0; - input [7:0] dval1; - input [7:0] dbgsel_w; - output [7:0] dout; + input clk; + input rstn; + input [7:0] dval0; + input [7:0] dval1; + input [7:0] dbgsel_w; + output [7:0] dout; - wire [7:0] dout = dout0 | dout1; + wire [7:0] dout = dout0 | dout1; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] dout0; // From sub0 of sub0.v - wire [7:0] dout1; // From sub1 of sub1.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v + // End of automatics - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end - reg [7:0] dbgsel_msk; - always_comb begin - reg [7:0] mask; - mask = 8'hff; - dbgsel_msk = (dbgsel_w & mask); - end + reg [7:0] dbgsel_msk; + always_comb begin + reg [7:0] mask; + mask = 8'hff; + dbgsel_msk = (dbgsel_w & mask); + end - // TODO this should optimize away, but presently does not because - // V3Gate constifies then doesn't see all other input edges have disappeared - reg [7:0] dbgsel; - always @(posedge clk) begin - if ((rstn == 0)) begin - dbgsel <= 0; - end - else begin - dbgsel <= dbgsel_msk; - end - end + // TODO this should optimize away, but presently does not because + // V3Gate constifies then doesn't see all other input edges have disappeared + reg [7:0] dbgsel; + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel <= 0; + end + else begin + dbgsel <= dbgsel_msk; + end + end - sub0 sub0 (/*AUTOINST*/ - // Outputs - .dout0 (dout0[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval0 (dval0[7:0]), - .dbgsel (dbgsel[7:0])); - sub1 sub1 (/*AUTOINST*/ - // Outputs - .dout1 (dout1[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval1 (dval1[7:0]), - .dbgsel (dbgsel[7:0])); + sub0 sub0 ( /*AUTOINST*/ + // Outputs + .dout0(dout0[7:0]), + // Inputs + .rstn(rstn), + .clk(clk), + .dval0(dval0[7:0]), + .dbgsel(dbgsel[7:0]) + ); + sub1 sub1 ( /*AUTOINST*/ + // Outputs + .dout1(dout1[7:0]), + // Inputs + .rstn(rstn), + .clk(clk), + .dval1(dval1[7:0]), + .dbgsel(dbgsel[7:0]) + ); endmodule -module sub0 - ( - /*AUTOARG*/ - // Outputs - dout0, - // Inputs - rstn, clk, dval0, dbgsel - ); +module sub0 ( + /*AUTOARG*/ + // Outputs + dout0, + // Inputs + rstn, + clk, + dval0, + dbgsel +); - input rstn; - input clk; - input [7:0] dval0; - input [7:0] dbgsel; - output reg [7:0] dout0; + input rstn; + input clk; + input [7:0] dval0; + input [7:0] dbgsel; + output reg [7:0] dout0; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; - always_comb begin - // verilator lint_off WIDTH - if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin - // verilator lint_on WIDTH - dout0 = dval0; - end - else begin - dout0 = 0; - end - end + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval0; + end + else begin + dout0 = 0; + end + end - always @(posedge clk) begin - if ((rstn == 0)) begin - dbgsel_d1r <= 0; - end - else begin - dbgsel_d1r <= dbgsel; - end - end + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end endmodule -module sub1 - ( - /*AUTOARG*/ - // Outputs - dout1, - // Inputs - rstn, clk, dval1, dbgsel - ); +module sub1 ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, + clk, + dval1, + dbgsel +); - input rstn; - input clk; - input [7:0] dval1; - input [7:0] dbgsel; - output reg [7:0] dout1; + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; - always_comb begin - if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin - dout1 = dval1; - end - else begin - dout1 = 0; - end - end + always_comb begin + if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin + dout1 = dval1; + end + else begin + dout1 = 0; + end + end - always @(posedge clk) begin - if ((rstn == 0)) begin - dbgsel_d1r <= 0; - end - else begin - dbgsel_d1r <= dbgsel; - end - end + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end endmodule diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index f26be1353..59dee4043 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -6,92 +6,91 @@ // Also check that SystemC is ordering properly -module t (/*AUTOARG*/ - // Outputs - o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, - obv1, obv16, obv1_vlt, obv16_vlt, - obu1, obu8, obu16, obu64, obu512, obu1_vlt, obu16_vlt, obu601, - // Inputs - clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, - ibv1, ibv16, ibv1_vlt, ibv16_vlt, - ibu1, ibu8, ibu16, ibu64, ibu512, ibu1_vlt, ibu16_vlt, ibu601 - ); +module t ( /*AUTOARG*/ + // Outputs + o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, + obv16_vlt, obu1, obu8, obu16, obu64, obu512, obu1_vlt, obu16_vlt, obu601, + // Inputs + clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, + ibv1_vlt, ibv16_vlt, ibu1, ibu8, ibu16, ibu64, ibu512, ibu1_vlt, ibu16_vlt, + ibu601 + ); - input clk; + input clk; - input i1; - input [7:0] i8; - input [15:0] i16; - input [31:0] i32; - input [63:0] i64; - input [64:0] i65; - input [127:0] i128; - input [512:0] i513; - input i1a2 [1:0]; - input [93:0] i94a3 [2:0]; + input i1; + input [7:0] i8; + input [15:0] i16; + input [31:0] i32; + input [63:0] i64; + input [64:0] i65; + input [127:0] i128; + input [512:0] i513; + input i1a2[1:0]; + input [93:0] i94a3[2:0]; - output logic o1; - output logic [7:0] o8; - output logic [15:0] o16; - output logic [31:0] o32; - output logic [63:0] o64; - output logic [64:0] o65; - output logic [127:0] o128; - output logic [512:0] o513; - output logic o1a2 [1:0]; - output logic [93:0] o94a3 [2:0]; + output logic o1; + output logic [7:0] o8; + output logic [15:0] o16; + output logic [31:0] o32; + output logic [63:0] o64; + output logic [64:0] o65; + output logic [127:0] o128; + output logic [512:0] o513; + output logic o1a2[1:0]; + output logic [93:0] o94a3[2:0]; - input [0:0] ibv1 /*verilator sc_bv*/; - input [15:0] ibv16 /*verilator sc_bv*/; - input [0:0] ibv1_vlt; - input [15:0] ibv16_vlt; + input [0:0] ibv1 /*verilator sc_bv*/; + input [15:0] ibv16 /*verilator sc_bv*/; + input [0:0] ibv1_vlt; + input [15:0] ibv16_vlt; - output logic [0:0] obv1 /*verilator sc_bv*/; - output logic [15:0] obv16 /*verilator sc_bv*/; - output logic [0:0] obv1_vlt; - output logic [15:0] obv16_vlt; + output logic [0:0] obv1 /*verilator sc_bv*/; + output logic [15:0] obv16 /*verilator sc_bv*/; + output logic [0:0] obv1_vlt; + output logic [15:0] obv16_vlt; - input ibu1 /*verilator sc_biguint*/; - input [7:0] ibu8 /*verilator sc_biguint*/; - input [15:0] ibu16 /*verilator sc_biguint*/; - input [63:0] ibu64 /*verilator sc_biguint*/; - input [511:0] ibu512 /*verilator sc_biguint*/; - input ibu1_vlt; - input [15:0] ibu16_vlt; - input [600:0] ibu601 /*verilator sc_biguint*/; + input ibu1 /*verilator sc_biguint*/; + input [7:0] ibu8 /*verilator sc_biguint*/; + input [15:0] ibu16 /*verilator sc_biguint*/; + input [63:0] ibu64 /*verilator sc_biguint*/; + input [511:0] ibu512 /*verilator sc_biguint*/; + input ibu1_vlt; + input [15:0] ibu16_vlt; + input [600:0] ibu601 /*verilator sc_biguint*/; - output logic obu1 /*verilator sc_biguint*/; - output logic [7:0] obu8 /*verilator sc_biguint*/; - output logic [15:0] obu16 /*verilator sc_biguint*/; - output logic [63:0] obu64 /*verilator sc_biguint*/; - output logic [511:0] obu512 /*verilator sc_biguint*/; - output logic obu1_vlt; - output logic [15:0] obu16_vlt; - output logic [600:0] obu601 /*verilator sc_biguint*/; + output logic obu1 /*verilator sc_biguint*/; + output logic [7:0] obu8 /*verilator sc_biguint*/; + output logic [15:0] obu16 /*verilator sc_biguint*/; + output logic [63:0] obu64 /*verilator sc_biguint*/; + output logic [511:0] obu512 /*verilator sc_biguint*/; + output logic obu1_vlt; + output logic [15:0] obu16_vlt; + output logic [600:0] obu601 /*verilator sc_biguint*/; - always @ (posedge clk) begin - o1 <= i1; - o8 <= i8; - o16 <= i16; - o32 <= i32; - o64 <= i64; - o65 <= i65; - o128 <= i128; - o513 <= i513; - obv1 <= ibv1; - obv16 <= ibv16; - obv1_vlt <= ibv1_vlt; - obv16_vlt <= ibv16_vlt; - o1a2 <= i1a2; - o94a3 <= i94a3; - obu1 <= ibu1; - obu8 <= ibu8; - obu16 <= ibu16; - obu64 <= ibu64; - obu512 <= ibu512; - obu1_vlt <= ibu1_vlt; - obu16_vlt <= ibu16_vlt; - obu601 <= ibu601; - end + always @(posedge clk) begin + o1 <= i1; + o8 <= i8; + o16 <= i16; + o32 <= i32; + o64 <= i64; + o65 <= i65; + o128 <= i128; + o513 <= i513; + obv1 <= ibv1; + obv16 <= ibv16; + obv1_vlt <= ibv1_vlt; + obv16_vlt <= ibv16_vlt; + o1a2 <= i1a2; + o94a3 <= i94a3; + obu1 <= ibu1; + obu8 <= ibu8; + obu16 <= ibu16; + obu64 <= ibu64; + obu512 <= ibu512; + obu1_vlt <= ibu1_vlt; + obu16_vlt <= ibu16_vlt; + obu601 <= ibu601; + end endmodule diff --git a/test_regress/t/t_var_port2_bad.out b/test_regress/t/t_var_port2_bad.out index a1da72d2b..0286f0210 100644 --- a/test_regress/t/t_var_port2_bad.out +++ b/test_regress/t/t_var_port2_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_var_port2_bad.v:7:11: Input/output/inout declaration not found for port: 'portwithoin' - 7 | module t (portwithoin); - | ^~~~~~~~~~~ +%Error: t/t_var_port2_bad.v:8:5: Input/output/inout declaration not found for port: 'portwithoin' + 8 | portwithoin + | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_port2_bad.v:8:10: Input/output/inout does not appear in port list: 'portwithin' - 8 | input portwithin; - | ^~~~~~~~~~ +%Error: t/t_var_port2_bad.v:10:9: Input/output/inout does not appear in port list: 'portwithin' + 10 | input portwithin; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_port2_bad.v b/test_regress/t/t_var_port2_bad.v index a48f90a59..4556b7c92 100644 --- a/test_regress/t/t_var_port2_bad.v +++ b/test_regress/t/t_var_port2_bad.v @@ -4,6 +4,8 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (portwithoin); - input portwithin; +module t ( + portwithoin +); + input portwithin; endmodule diff --git a/test_regress/t/t_var_port_bad.out b/test_regress/t/t_var_port_bad.out index 6725795d0..e7c99f498 100644 --- a/test_regress/t/t_var_port_bad.out +++ b/test_regress/t/t_var_port_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_var_port_bad.v:16:13: Input/output/inout does not appear in port list: 'b' - 16 | input a, b; - | ^ +%Error: t/t_var_port_bad.v:27:12: Input/output/inout does not appear in port list: 'b' + 27 | input a, b; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_var_port_bad.v b/test_regress/t/t_var_port_bad.v index 09d51d14f..a6838ac70 100644 --- a/test_regress/t/t_var_port_bad.v +++ b/test_regress/t/t_var_port_bad.v @@ -5,13 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t; - subok subok (.a(1'b1), .b(1'b0)); - sub sub (.a(1'b1), .b(1'b0)); + subok subok ( + .a(1'b1), + .b(1'b0) + ); + sub sub ( + .a(1'b1), + .b(1'b0) + ); endmodule -module subok (input a,b); +module subok ( + input a, + b +); endmodule -module sub (a); - input a, b; +module sub ( + a +); + input a, b; endmodule diff --git a/test_regress/t/t_var_ref.v b/test_regress/t/t_var_ref.v index e5081e066..867ecdeff 100644 --- a/test_regress/t/t_var_ref.v +++ b/test_regress/t/t_var_ref.v @@ -9,90 +9,96 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int cyc; + int cyc; - int vr; - int va[2]; + int vr; + int va[2]; `ifdef T_NOINLINE - // verilator no_inline_module + // verilator no_inline_module `endif - //==== + //==== - task fun(ref int r, const ref int c); + task fun(ref int r, const ref int c); `ifdef T_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - `checkh(c, 32'h1234); - r = 32'h4567; - endtask + `checkh(c, 32'h1234); + r = 32'h4567; + endtask - initial begin - int ci; - int ri; - ci = 32'h1234; - fun(ri, ci); - `checkh(ri, 32'h4567); - end + initial begin + int ci; + int ri; + ci = 32'h1234; + fun(ri, ci); + `checkh(ri, 32'h4567); + end - //==== + //==== - task fun_array(ref int af[2], const ref int cf[2]); + task fun_array(ref int af[2], const ref int cf[2]); `ifdef T_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - `checkh(cf[0], 32'h1234); - `checkh(cf[1], 32'h2345); - af[0] = 32'h5678; - af[1] = 32'h6789; - endtask - // Not checkint - element of unpacked array + `checkh(cf[0], 32'h1234); + `checkh(cf[1], 32'h2345); + af[0] = 32'h5678; + af[1] = 32'h6789; + endtask + // Not checkint - element of unpacked array - initial begin - int ca[2]; - int ra[2]; - ca[0] = 32'h1234; - ca[1] = 32'h2345; - fun_array(ra, ca); - `checkh(ra[0], 32'h5678); - `checkh(ra[1], 32'h6789); - end + initial begin + int ca[2]; + int ra[2]; + ca[0] = 32'h1234; + ca[1] = 32'h2345; + fun_array(ra, ca); + `checkh(ra[0], 32'h5678); + `checkh(ra[1], 32'h6789); + end - //==== + //==== - sub sub(.clk, .vr, .va); + sub sub ( + .clk, + .vr, + .va + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - vr <= 32'h789; - va[0] <= 32'h89a; - va[1] <= 32'h9ab; - end - else if (cyc == 2) begin - `checkh(vr, 32'h987); - `checkh(va[0], 32'ha98); - `checkh(va[1], 32'ha9b); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + vr <= 32'h789; + va[0] <= 32'h89a; + va[1] <= 32'h9ab; + end + else if (cyc == 2) begin + `checkh(vr, 32'h987); + `checkh(va[0], 32'ha98); + `checkh(va[1], 32'ha9b); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub(input clk, ref int vr, ref int va[2]); +module sub ( + input clk, + ref int vr, + ref int va[2] +); - always @(posedge clk) begin - vr <= 32'h987; - va[0] <= 32'ha98; - va[1] <= 32'ha9b; - end + always @(posedge clk) begin + vr <= 32'h987; + va[0] <= 32'ha98; + va[1] <= 32'ha9b; + end endmodule diff --git a/test_regress/t/t_var_ref_bad1.out b/test_regress/t/t_var_ref_bad1.out index 2861bd2de..4fd5503f4 100644 --- a/test_regress/t/t_var_ref_bad1.out +++ b/test_regress/t/t_var_ref_bad1.out @@ -1,6 +1,6 @@ -%Error: t/t_var_ref_bad1.v:14:8: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. - : ... note: In instance 't' - 14 | (.bad_sub_ref(bad_parent)); - | ^~~~~~~~~~~ +%Error: t/t_var_ref_bad1.v:13:13: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. + : ... note: In instance 't' + 13 | sub sub (.bad_sub_ref(bad_parent)); + | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad1.v b/test_regress/t/t_var_ref_bad1.v index 3c9c4c45a..e03d17859 100644 --- a/test_regress/t/t_var_ref_bad1.v +++ b/test_regress/t/t_var_ref_bad1.v @@ -9,11 +9,12 @@ module t; - bit bad_parent; - sub sub - (.bad_sub_ref(bad_parent)); // Type mismatch + bit bad_parent; + sub sub (.bad_sub_ref(bad_parent)); // Type mismatch endmodule -module sub(ref real bad_sub_ref); +module sub ( + ref real bad_sub_ref +); endmodule diff --git a/test_regress/t/t_var_ref_bad2.out b/test_regress/t/t_var_ref_bad2.out index 70a6427a7..54369d065 100644 --- a/test_regress/t/t_var_ref_bad2.out +++ b/test_regress/t/t_var_ref_bad2.out @@ -1,10 +1,10 @@ -%Error: t/t_var_ref_bad2.v:13:7: Assigning to const ref variable: 'bad_const_set' +%Error: t/t_var_ref_bad2.v:13:5: Assigning to const ref variable: 'bad_const_set' : ... note: In instance 't' - 13 | bad_const_set = 32'h4567; - | ^~~~~~~~~~~~~ + 13 | bad_const_set = 32'h4567; + | ^~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_ref_bad2.v:23:17: Ref argument requires matching types; port 'int_ref' requires 'int' but connection is 'byte'. +%Error: t/t_var_ref_bad2.v:23:15: Ref argument requires matching types; port 'int_ref' requires 'int' but connection is 'byte'. : ... note: In instance 't' - 23 | checkset2(bad_non_int); - | ^~~~~~~~~~~ + 23 | checkset2(bad_non_int); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad2.v b/test_regress/t/t_var_ref_bad2.v index 86d4186fa..bbb1bcc7d 100644 --- a/test_regress/t/t_var_ref_bad2.v +++ b/test_regress/t/t_var_ref_bad2.v @@ -9,17 +9,17 @@ module t; - task checkset(const ref int bad_const_set); - bad_const_set = 32'h4567; // Bad setting const - endtask + task checkset(const ref int bad_const_set); + bad_const_set = 32'h4567; // Bad setting const + endtask - task checkset2(ref int int_ref); - endtask + task checkset2(ref int int_ref); + endtask - initial begin - int i; - byte bad_non_int; - checkset(i); - checkset2(bad_non_int); // Type mismatch - end + initial begin + int i; + byte bad_non_int; + checkset(i); + checkset2(bad_non_int); // Type mismatch + end endmodule diff --git a/test_regress/t/t_var_ref_bad3.out b/test_regress/t/t_var_ref_bad3.out index 9734599c6..5e2b360a5 100644 --- a/test_regress/t/t_var_ref_bad3.out +++ b/test_regress/t/t_var_ref_bad3.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' - 10 | module t(ref int bad_primary_ref); - | ^~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_var_ref_bad3.v:11:13: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' + 11 | ref int bad_primary_ref + | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad3.v b/test_regress/t/t_var_ref_bad3.v index 1890389ea..8a2e9231d 100644 --- a/test_regress/t/t_var_ref_bad3.v +++ b/test_regress/t/t_var_ref_bad3.v @@ -7,5 +7,7 @@ // Make sure type errors aren't suppressable // verilator lint_off WIDTH -module t(ref int bad_primary_ref); +module t ( + ref int bad_primary_ref +); endmodule diff --git a/test_regress/t/t_var_ref_static.out b/test_regress/t/t_var_ref_static.out index 830fd1304..a1be3ffbf 100644 --- a/test_regress/t/t_var_ref_static.out +++ b/test_regress/t/t_var_ref_static.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_var_ref_static.v:12:22: Unsupported: 'ref static' ports - 12 | function void crs(const ref static i); - | ^~~~~ +%Error-UNSUPPORTED: t/t_var_ref_static.v:12:21: Unsupported: 'ref static' ports + 12 | function void crs(const ref static i); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_var_ref_static.v:14:21: Unsupported: 'ref static' ports - 14 | function void rs(ref static i); - | ^~~ +%Error-UNSUPPORTED: t/t_var_ref_static.v:14:20: Unsupported: 'ref static' ports + 14 | function void rs(ref static i); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_static.v b/test_regress/t/t_var_ref_static.v index 4b13091ea..23b42e032 100644 --- a/test_regress/t/t_var_ref_static.v +++ b/test_regress/t/t_var_ref_static.v @@ -8,9 +8,9 @@ // verilator lint_off WIDTH module t; - // TODO make this a proper test - function void crs(const ref static i); - endfunction - function void rs(ref static i); - endfunction + // TODO make this a proper test + function void crs(const ref static i); + endfunction + function void rs(ref static i); + endfunction endmodule diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v index dc972d13b..784b93ebd 100644 --- a/test_regress/t/t_var_rsvd.v +++ b/test_regress/t/t_var_rsvd.v @@ -7,27 +7,27 @@ // verilator lint_off SYMRSVDWORD module t (/*AUTOARG*/ - // Inputs - bool - ); + // Inputs + bool + ); - input bool; // BAD + input bool; // BAD - reg vector; // OK, as not public - reg switch /*verilator public*/; // Bad + reg vector; // OK, as not public + reg switch /*verilator public*/; // Bad - typedef struct packed { - logic [31:0] vector; // OK, as not public - } test; - test t; + typedef struct packed { + logic [31:0] vector; // OK, as not public + } test; + test t; - // global is a 1800-2009 reserved word, but we allow it when possible. - reg global; + // global is a 1800-2009 reserved word, but we allow it when possible. + reg global; - initial begin - t.vector = 1; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + t.vector = 1; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_rsvd_bad.out b/test_regress/t/t_var_rsvd_bad.out index 269c38632..85bd23966 100644 --- a/test_regress/t/t_var_rsvd_bad.out +++ b/test_regress/t/t_var_rsvd_bad.out @@ -1,10 +1,10 @@ -%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' - 12 | input bool; - | ^~~~ +%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:9: Symbol matches C++ keyword: 'bool' + 12 | input bool; + | ^~~~ ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=latest ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. -%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' +%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:7: Symbol matches C++ keyword: 'switch' : ... note: In instance 't' - 15 | reg switch /*verilator public*/; - | ^~~~~~ + 15 | reg switch /*verilator public*/; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_rsvd_port.v b/test_regress/t/t_var_rsvd_port.v index 5cc594967..2884f0f7c 100644 --- a/test_regress/t/t_var_rsvd_port.v +++ b/test_regress/t/t_var_rsvd_port.v @@ -4,19 +4,19 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - bool - ); +module t ( /*AUTOARG*/ + // Inputs + bool +); - input bool; // BAD + input bool; // BAD - reg vector; // OK, as not public - reg switch /*verilator public*/; // Bad - reg free /*verilator public*/; // OK, not actually a keyword + reg vector; // OK, as not public + reg switch /*verilator public*/; // Bad + reg free /*verilator public*/; // OK, not actually a keyword - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_sc_bv.v b/test_regress/t/t_var_sc_bv.v index 499a81da5..c7ade5f35 100644 --- a/test_regress/t/t_var_sc_bv.v +++ b/test_regress/t/t_var_sc_bv.v @@ -4,243 +4,199 @@ // SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - o_29,o_29_old, - o_30,o_30_old, - o_31,o_31_old, - o_32,o_32_old, - o_59,o_59_old, - o_60,o_60_old, - o_62,o_62_old, - o_64,o_64_old, - o_119,o_119_old, - o_120,o_120_old, - o_121,o_121_old, - o_127,o_127_old, - o_128,o_128_old, - o_255,o_255_old, - o_256,o_256_old, - // Inputs - i_29,i_29_old, - i_30,i_30_old, - i_31,i_31_old, - i_32,i_32_old, - i_59,i_59_old, - i_60,i_60_old, - i_62,i_62_old, - i_64,i_64_old, - i_119,i_119_old, - i_120,i_120_old, - i_121,i_121_old, - i_127,i_127_old, - i_128,i_128_old, - i_255,i_255_old, - i_256,i_256_old - ); - input [255:0] i_29; - output wire [255:0] o_29; - input [255:0] i_29_old; - output wire [255:0] o_29_old; - input [255:0] i_30; - output wire [255:0] o_30; - input [255:0] i_30_old; - output wire [255:0] o_30_old; - input [255:0] i_31; - output wire [255:0] o_31; - input [255:0] i_31_old; - output wire [255:0] o_31_old; - input [255:0] i_32; - output wire [255:0] o_32; - input [255:0] i_32_old; - output wire [255:0] o_32_old; - input [255:0] i_59; - output wire [255:0] o_59; - input [255:0] i_59_old; - output wire [255:0] o_59_old; - input [255:0] i_60; - output wire [255:0] o_60; - input [255:0] i_60_old; - output wire [255:0] o_60_old; - input [255:0] i_62; - output wire [255:0] o_62; - input [255:0] i_62_old; - output wire [255:0] o_62_old; - input [255:0] i_64; - output wire [255:0] o_64; - input [255:0] i_64_old; - output wire [255:0] o_64_old; - input [255:0] i_119; - output wire [255:0] o_119; - input [255:0] i_119_old; - output wire [255:0] o_119_old; - input [255:0] i_120; - output wire [255:0] o_120; - input [255:0] i_120_old; - output wire [255:0] o_120_old; - input [255:0] i_121; - output wire [255:0] o_121; - input [255:0] i_121_old; - output wire [255:0] o_121_old; - input [255:0] i_127; - output wire [255:0] o_127; - input [255:0] i_127_old; - output wire [255:0] o_127_old; - input [255:0] i_128; - output wire [255:0] o_128; - input [255:0] i_128_old; - output wire [255:0] o_128_old; - input [255:0] i_255; - output wire [255:0] o_255; - input [255:0] i_255_old; - output wire [255:0] o_255_old; - input [255:0] i_256; - output wire [255:0] o_256; - input [255:0] i_256_old; - output wire [255:0] o_256_old; +module t ( /*AUTOARG*/ + // Outputs + o_29, o_29_old, o_30, o_30_old, o_31, o_31_old, o_32, o_32_old, o_59, + o_59_old, o_60, o_60_old, o_62, o_62_old, o_64, o_64_old, o_119, o_119_old, + o_120, o_120_old, o_121, o_121_old, o_127, o_127_old, o_128, o_128_old, o_255, + o_255_old, o_256, o_256_old, + // Inputs + i_29, i_29_old, i_30, i_30_old, i_31, i_31_old, i_32, i_32_old, i_59, + i_59_old, i_60, i_60_old, i_62, i_62_old, i_64, i_64_old, i_119, i_119_old, + i_120, i_120_old, i_121, i_121_old, i_127, i_127_old, i_128, i_128_old, i_255, + i_255_old, i_256, i_256_old + ); + input [255:0] i_29; + output wire [255:0] o_29; + input [255:0] i_29_old; + output wire [255:0] o_29_old; + input [255:0] i_30; + output wire [255:0] o_30; + input [255:0] i_30_old; + output wire [255:0] o_30_old; + input [255:0] i_31; + output wire [255:0] o_31; + input [255:0] i_31_old; + output wire [255:0] o_31_old; + input [255:0] i_32; + output wire [255:0] o_32; + input [255:0] i_32_old; + output wire [255:0] o_32_old; + input [255:0] i_59; + output wire [255:0] o_59; + input [255:0] i_59_old; + output wire [255:0] o_59_old; + input [255:0] i_60; + output wire [255:0] o_60; + input [255:0] i_60_old; + output wire [255:0] o_60_old; + input [255:0] i_62; + output wire [255:0] o_62; + input [255:0] i_62_old; + output wire [255:0] o_62_old; + input [255:0] i_64; + output wire [255:0] o_64; + input [255:0] i_64_old; + output wire [255:0] o_64_old; + input [255:0] i_119; + output wire [255:0] o_119; + input [255:0] i_119_old; + output wire [255:0] o_119_old; + input [255:0] i_120; + output wire [255:0] o_120; + input [255:0] i_120_old; + output wire [255:0] o_120_old; + input [255:0] i_121; + output wire [255:0] o_121; + input [255:0] i_121_old; + output wire [255:0] o_121_old; + input [255:0] i_127; + output wire [255:0] o_127; + input [255:0] i_127_old; + output wire [255:0] o_127_old; + input [255:0] i_128; + output wire [255:0] o_128; + input [255:0] i_128_old; + output wire [255:0] o_128_old; + input [255:0] i_255; + output wire [255:0] o_255; + input [255:0] i_255_old; + output wire [255:0] o_255_old; + input [255:0] i_256; + output wire [255:0] o_256; + input [255:0] i_256_old; + output wire [255:0] o_256_old; - sub sub (.*); + sub sub (.*); endmodule -module sub (/*AUTOARG*/ - // Outputs - o_29,o_29_old, - o_30,o_30_old, - o_31,o_31_old, - o_32,o_32_old, - o_59,o_59_old, - o_60,o_60_old, - o_62,o_62_old, - o_64,o_64_old, - o_119,o_119_old, - o_120,o_120_old, - o_121,o_121_old, - o_127,o_127_old, - o_128,o_128_old, - o_255,o_255_old, - o_256,o_256_old, - // Inputs - i_29,i_29_old, - i_30,i_30_old, - i_31,i_31_old, - i_32,i_32_old, - i_59,i_59_old, - i_60,i_60_old, - i_62,i_62_old, - i_64,i_64_old, - i_119,i_119_old, - i_120,i_120_old, - i_121,i_121_old, - i_127,i_127_old, - i_128,i_128_old, - i_255,i_255_old, - i_256,i_256_old - ); +module sub ( /*AUTOARG*/ + // Outputs + o_29, o_29_old, o_30, o_30_old, o_31, o_31_old, o_32, o_32_old, o_59, + o_59_old, o_60, o_60_old, o_62, o_62_old, o_64, o_64_old, o_119, o_119_old, + o_120, o_120_old, o_121, o_121_old, o_127, o_127_old, o_128, o_128_old, o_255, + o_255_old, o_256, o_256_old, + // Inputs + i_29, i_29_old, i_30, i_30_old, i_31, i_31_old, i_32, i_32_old, i_59, + i_59_old, i_60, i_60_old, i_62, i_62_old, i_64, i_64_old, i_119, i_119_old, + i_120, i_120_old, i_121, i_121_old, i_127, i_127_old, i_128, i_128_old, i_255, + i_255_old, i_256, i_256_old + ); - input [255:0] i_29; - output wire [255:0] o_29; - input [255:0] i_29_old; - output wire [255:0] o_29_old; - input [255:0] i_30; - output wire [255:0] o_30; - input [255:0] i_30_old; - output wire [255:0] o_30_old; - input [255:0] i_31; - output wire [255:0] o_31; - input [255:0] i_31_old; - output wire [255:0] o_31_old; - input [255:0] i_32; - output wire [255:0] o_32; - input [255:0] i_32_old; - output wire [255:0] o_32_old; - input [255:0] i_59; - output wire [255:0] o_59; - input [255:0] i_59_old; - output wire [255:0] o_59_old; - input [255:0] i_60; - output wire [255:0] o_60; - input [255:0] i_60_old; - output wire [255:0] o_60_old; - input [255:0] i_62; - output wire [255:0] o_62; - input [255:0] i_62_old; - output wire [255:0] o_62_old; - input [255:0] i_64; - output wire [255:0] o_64; - input [255:0] i_64_old; - output wire [255:0] o_64_old; - input [255:0] i_119; - output wire [255:0] o_119; - input [255:0] i_119_old; - output wire [255:0] o_119_old; - input [255:0] i_120; - output wire [255:0] o_120; - input [255:0] i_120_old; - output wire [255:0] o_120_old; - input [255:0] i_121; - output wire [255:0] o_121; - input [255:0] i_121_old; - output wire [255:0] o_121_old; - input [255:0] i_127; - output wire [255:0] o_127; - input [255:0] i_127_old; - output wire [255:0] o_127_old; - input [255:0] i_128; - output wire [255:0] o_128; - input [255:0] i_128_old; - output wire [255:0] o_128_old; - input [255:0] i_255; - output wire [255:0] o_255; - input [255:0] i_255_old; - output wire [255:0] o_255_old; - input [255:0] i_256; - output wire [255:0] o_256; - input [255:0] i_256_old; - output wire [255:0] o_256_old; + input [255:0] i_29; + output wire [255:0] o_29; + input [255:0] i_29_old; + output wire [255:0] o_29_old; + input [255:0] i_30; + output wire [255:0] o_30; + input [255:0] i_30_old; + output wire [255:0] o_30_old; + input [255:0] i_31; + output wire [255:0] o_31; + input [255:0] i_31_old; + output wire [255:0] o_31_old; + input [255:0] i_32; + output wire [255:0] o_32; + input [255:0] i_32_old; + output wire [255:0] o_32_old; + input [255:0] i_59; + output wire [255:0] o_59; + input [255:0] i_59_old; + output wire [255:0] o_59_old; + input [255:0] i_60; + output wire [255:0] o_60; + input [255:0] i_60_old; + output wire [255:0] o_60_old; + input [255:0] i_62; + output wire [255:0] o_62; + input [255:0] i_62_old; + output wire [255:0] o_62_old; + input [255:0] i_64; + output wire [255:0] o_64; + input [255:0] i_64_old; + output wire [255:0] o_64_old; + input [255:0] i_119; + output wire [255:0] o_119; + input [255:0] i_119_old; + output wire [255:0] o_119_old; + input [255:0] i_120; + output wire [255:0] o_120; + input [255:0] i_120_old; + output wire [255:0] o_120_old; + input [255:0] i_121; + output wire [255:0] o_121; + input [255:0] i_121_old; + output wire [255:0] o_121_old; + input [255:0] i_127; + output wire [255:0] o_127; + input [255:0] i_127_old; + output wire [255:0] o_127_old; + input [255:0] i_128; + output wire [255:0] o_128; + input [255:0] i_128_old; + output wire [255:0] o_128_old; + input [255:0] i_255; + output wire [255:0] o_255; + input [255:0] i_255_old; + output wire [255:0] o_255_old; + input [255:0] i_256; + output wire [255:0] o_256; + input [255:0] i_256_old; + output wire [255:0] o_256_old; - assign o_29 = i_29; - assign o_29_old = i_29_old; + assign o_29 = i_29; + assign o_29_old = i_29_old; - assign o_30 = i_30; - assign o_30_old = i_30_old; + assign o_30 = i_30; + assign o_30_old = i_30_old; - assign o_31 = i_31; - assign o_31_old = i_31_old; + assign o_31 = i_31; + assign o_31_old = i_31_old; - assign o_32 = i_32; - assign o_32_old = i_32_old; + assign o_32 = i_32; + assign o_32_old = i_32_old; - assign o_59 = i_59; - assign o_59_old = i_59_old; + assign o_59 = i_59; + assign o_59_old = i_59_old; - assign o_60 = i_60; - assign o_60_old = i_60_old; + assign o_60 = i_60; + assign o_60_old = i_60_old; - assign o_62 = i_62; - assign o_62_old = i_62_old; + assign o_62 = i_62; + assign o_62_old = i_62_old; - assign o_64 = i_64; - assign o_64_old = i_64_old; + assign o_64 = i_64; + assign o_64_old = i_64_old; - assign o_119 = i_119; - assign o_119_old = i_119_old; + assign o_119 = i_119; + assign o_119_old = i_119_old; - assign o_120 = i_120; - assign o_120_old = i_120_old; + assign o_120 = i_120; + assign o_120_old = i_120_old; - assign o_121 = i_121; - assign o_121_old = i_121_old; + assign o_121 = i_121; + assign o_121_old = i_121_old; - assign o_127 = i_127; - assign o_127_old = i_127_old; + assign o_127 = i_127; + assign o_127_old = i_127_old; - assign o_128 = i_128; - assign o_128_old = i_128_old; + assign o_128 = i_128; + assign o_128_old = i_128_old; - assign o_255 = i_255; - assign o_255_old = i_255_old; + assign o_255 = i_255; + assign o_255_old = i_255_old; - assign o_256 = i_256; - assign o_256_old = i_256_old; + assign o_256 = i_256; + assign o_256_old = i_256_old; endmodule diff --git a/test_regress/t/t_var_sc_double.v b/test_regress/t/t_var_sc_double.v index 44fa1cf67..acd432056 100644 --- a/test_regress/t/t_var_sc_double.v +++ b/test_regress/t/t_var_sc_double.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - // Outputs - o_z, - // Inputs - i_a - ); - input real i_a; - output real o_z; + // Outputs + o_z, + // Inputs + i_a + ); + input real i_a; + output real o_z; - assign o_z = i_a; + assign o_z = i_a; endmodule diff --git a/test_regress/t/t_var_set_link.v b/test_regress/t/t_var_set_link.v index 281f405f3..8b922da5d 100644 --- a/test_regress/t/t_var_set_link.v +++ b/test_regress/t/t_var_set_link.v @@ -3,24 +3,24 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - state, - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Outputs + state, + // Inputs + clk +); + input clk; - // Gave "Internal Error: V3Broken.cpp:: Broken link in node" - output [1:0] state; - reg [1:0] state = 2'b11; - always @ (posedge clk) begin - state <= state; - end + // Gave "Internal Error: V3Broken.cpp:: Broken link in node" + output [1:0] state; + reg [1:0] state = 2'b11; + always @(posedge clk) begin + state <= state; + end - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_static.v b/test_regress/t/t_var_static.v index 046eb3370..1f6590732 100644 --- a/test_regress/t/t_var_static.v +++ b/test_regress/t/t_var_static.v @@ -4,131 +4,156 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -function automatic int f_au_st_global (); - static int st = 0; st++; return st; +function automatic int f_au_st_global(); + static int st = 0; + st++; + return st; endfunction package my_pkg; - function int f_no_st_pkg (); - static int st = 0; st++; return st; - endfunction + function int f_no_st_pkg(); + static int st = 0; + st++; + return st; + endfunction endpackage class my_cls; - static function int get_cnt1; - static int cnt = 0; - return ++cnt; - endfunction + static function int get_cnt1; + static int cnt = 0; + return ++cnt; + endfunction endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - function int f_no_no (); - int st = 2; st++; return st; - endfunction - function int f_no_st (); - static int st = 2; st++; return st; - endfunction - function int f_no_au (); - automatic int au = 2; au++; return au; - endfunction + function int f_no_no(); + int st = 2; + st++; + return st; + endfunction + function int f_no_st(); + static int st = 2; + st++; + return st; + endfunction + function int f_no_au(); + automatic int au = 2; + au++; + return au; + endfunction - function static int f_st_no (); - int st = 2; st++; return st; - endfunction - function static int f_st_st (); - static int st = 2; st++; return st; - endfunction - function static int f_st_au (); - automatic int au = 2; au++; return au; - endfunction + function static int f_st_no(); + int st = 2; + st++; + return st; + endfunction + function static int f_st_st(); + static int st = 2; + st++; + return st; + endfunction + function static int f_st_au(); + automatic int au = 2; + au++; + return au; + endfunction - function automatic int f_au_no (); - int au = 2; au++; return au; - endfunction - function automatic int f_au_st (); - static int st = 2; st++; return st; - endfunction - function automatic int f_au_au (); - automatic int au = 2; au++; return au; - endfunction - string plusarg = ""; - bit has_plusarg = |($value$plusargs("plusarg=%s", plusarg)); + function automatic int f_au_no(); + int au = 2; + au++; + return au; + endfunction + function automatic int f_au_st(); + static int st = 2; + st++; + return st; + endfunction + function automatic int f_au_au(); + automatic int au = 2; + au++; + return au; + endfunction + string plusarg = ""; + bit has_plusarg = |($value$plusargs("plusarg=%s", plusarg)); - int v; + int v; - initial begin - if (has_plusarg) begin - if (plusarg == "") begin - $fatal(1, "%m: +plusarg must not be empty"); - end + // verilog_format: off + initial begin + if (has_plusarg) begin + if (plusarg == "") begin + $fatal(1, "%m: +plusarg must not be empty"); end - v = f_no_no(); `checkh(v, 3); - v = f_no_no(); `checkh(v, 4); - v = f_no_st(); `checkh(v, 3); - v = f_no_st(); `checkh(v, 4); - v = f_no_au(); `checkh(v, 3); - v = f_no_au(); `checkh(v, 3); - // - v = f_st_no(); `checkh(v, 3); - v = f_st_no(); `checkh(v, 4); - v = f_st_st(); `checkh(v, 3); - v = f_st_st(); `checkh(v, 4); - v = f_st_au(); `checkh(v, 3); - v = f_st_au(); `checkh(v, 3); - // - v = f_au_no(); `checkh(v, 3); - v = f_au_no(); `checkh(v, 3); - v = f_au_st(); `checkh(v, 3); - v = f_au_st(); `checkh(v, 4); - v = f_au_au(); `checkh(v, 3); - v = f_au_au(); `checkh(v, 3); - // - v = f_au_st_global(); `checkh(v, 1); - v = f_au_st_global(); `checkh(v, 2); - v = my_pkg::f_no_st_pkg(); `checkh(v, 1); - v = my_pkg::f_no_st_pkg(); `checkh(v, 2); - // - v = my_cls::get_cnt1(); `checkh(v, 1); - v = my_cls::get_cnt1(); `checkh(v, 2); - // - end + end + v = f_no_no(); `checkh(v, 3); + v = f_no_no(); `checkh(v, 4); + v = f_no_st(); `checkh(v, 3); + v = f_no_st(); `checkh(v, 4); + v = f_no_au(); `checkh(v, 3); + v = f_no_au(); `checkh(v, 3); + // + v = f_st_no(); `checkh(v, 3); + v = f_st_no(); `checkh(v, 4); + v = f_st_st(); `checkh(v, 3); + v = f_st_st(); `checkh(v, 4); + v = f_st_au(); `checkh(v, 3); + v = f_st_au(); `checkh(v, 3); + // + v = f_au_no(); `checkh(v, 3); + v = f_au_no(); `checkh(v, 3); + v = f_au_st(); `checkh(v, 3); + v = f_au_st(); `checkh(v, 4); + v = f_au_au(); `checkh(v, 3); + v = f_au_au(); `checkh(v, 3); + // + v = f_au_st_global(); `checkh(v, 1); + v = f_au_st_global(); `checkh(v, 2); + v = my_pkg::f_no_st_pkg(); `checkh(v, 1); + v = my_pkg::f_no_st_pkg(); `checkh(v, 2); + // + v = my_cls::get_cnt1(); `checkh(v, 1); + v = my_cls::get_cnt1(); `checkh(v, 2); + // + end - int cyc = 0; - always @ (posedge clk) begin - int ist1; - static int ist2; - automatic int iau3; + int cyc = 0; + always @ (posedge clk) begin + int ist1; + static int ist2; + automatic int iau3; - cyc <= cyc + 1; - if (cyc == 0) begin - ist1 = 10; - ist2 = 20; - iau3 = 30; - v = ist1; `checkh(v, 10); - v = ist2; `checkh(v, 20); - v = iau3; `checkh(v, 30); - ++ist1; - ++ist2; - ++iau3; - end - else if (cyc == 1) begin - v = ist1; `checkh(v, 11); - v = ist2; `checkh(v, 21); - //TODO v = iau3; `checkh(v, 0); - end - else if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 0) begin + ist1 = 10; + ist2 = 20; + iau3 = 30; + v = ist1; `checkh(v, 10); + v = ist2; `checkh(v, 20); + v = iau3; `checkh(v, 30); + ++ist1; + ++ist2; + ++iau3; + end + else if (cyc == 1) begin + v = ist1; `checkh(v, 11); + v = ist2; `checkh(v, 21); + //TODO v = iau3; `checkh(v, 0); + end + else if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_var_static_param.v b/test_regress/t/t_var_static_param.v index 39814a874..af013409b 100644 --- a/test_regress/t/t_var_static_param.v +++ b/test_regress/t/t_var_static_param.v @@ -4,33 +4,42 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - sub #(.P(1)) suba (); - sub #(.P(10)) subb (); + sub #(.P(1)) suba (); + sub #(.P(10)) subb (); - int v; + int v; - initial begin - v = suba.f_no_st(); `checkh(v, 3); - v = suba.f_no_st(); `checkh(v, 4); - v = subb.f_no_st(); `checkh(v, 'hc); - v = subb.f_no_st(); `checkh(v, 'h16); - v = suba.f_no_st(); `checkh(v, 5); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + v = suba.f_no_st(); + `checkh(v, 3); + v = suba.f_no_st(); + `checkh(v, 4); + v = subb.f_no_st(); + `checkh(v, 'hc); + v = subb.f_no_st(); + `checkh(v, 'h16); + v = suba.f_no_st(); + `checkh(v, 5); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub; - parameter P = 1; - // verilator lint_off IMPLICITSTATIC - function int f_no_st (); - // This static is unique within each parameterized module - static int st = 2; st += P; return st; - endfunction + parameter P = 1; + // verilator lint_off IMPLICITSTATIC + function int f_no_st(); + // This static is unique within each parameterized module + static int st = 2; + st += P; + return st; + endfunction endmodule diff --git a/test_regress/t/t_var_suggest_bad.out b/test_regress/t/t_var_suggest_bad.out index 49b8d284f..f5db5ef30 100644 --- a/test_regress/t/t_var_suggest_bad.out +++ b/test_regress/t/t_var_suggest_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_var_suggest_bad.v:13:11: Can't find definition of variable: 'foobat' - : ... Suggested alternative: 'foobar' - 13 | if (foobat) $stop; - | ^~~~~~ +%Error: t/t_var_suggest_bad.v:14:9: Can't find definition of variable: 'foobat' + : ... Suggested alternative: 'foobar' + 14 | if (foobat) $stop; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_suggest_bad.v:14:7: Can't find definition of task/function: 'boobat' +%Error: t/t_var_suggest_bad.v:15:5: Can't find definition of task/function: 'boobat' : ... Suggested alternative: 'boobar' - 14 | boobat; - | ^~~~~~ + 15 | boobat; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_suggest_bad.v b/test_regress/t/t_var_suggest_bad.v index f6f6063f5..350299118 100644 --- a/test_regress/t/t_var_suggest_bad.v +++ b/test_regress/t/t_var_suggest_bad.v @@ -5,12 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg foobar; + reg foobar; - task boobar; endtask + task boobar; + endtask - initial begin - if (foobat) $stop; - boobat; - end + initial begin + if (foobat) $stop; + boobat; + end endmodule diff --git a/test_regress/t/t_var_tieout.v b/test_regress/t/t_var_tieout.v index 967ed5dba..ffb116476 100644 --- a/test_regress/t/t_var_tieout.v +++ b/test_regress/t/t_var_tieout.v @@ -4,43 +4,42 @@ // SPDX-License-Identifier: CC0-1.0 // bug291 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer out18; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire out1; // From test of Test.v - wire out19; // From test of Test.v - wire out1b; // From test of Test.v - // End of automatics + integer out18; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out1; // From test of Test.v + wire out19; // From test of Test.v + wire out1b; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out1 (out1), - .out18 (out18), - .out1b (out1b), - .out19 (out19)); + Test test ( /*AUTOINST*/ + // Outputs + .out1(out1), + .out18(out18), + .out1b(out1b), + .out19(out19) + ); - // Test loop - always @ (posedge clk) begin - if (out1 !== 1'b1) $stop; - if (out18 !== 32'h18) $stop; - if (out1b !== 1'b1) $stop; - if (out19 !== 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + if (out1 !== 1'b1) $stop; + if (out18 !== 32'h18) $stop; + if (out1b !== 1'b1) $stop; + if (out19 !== 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module Test ( - output wire out1 = 1'b1, - output integer out18 = 32'h18, - output var out1b = 1'b1, - output var logic out19 = 1'b1 - ); + output wire out1 = 1'b1, + output integer out18 = 32'h18, + output var out1b = 1'b1, + output var logic out19 = 1'b1 +); endmodule diff --git a/test_regress/t/t_var_top_struct.v b/test_regress/t/t_var_top_struct.v index e468508ec..8dd4d195a 100644 --- a/test_regress/t/t_var_top_struct.v +++ b/test_regress/t/t_var_top_struct.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct { - logic bist; - logic [38:0] web; - logic ceb; + logic bist; + logic [38:0] web; + logic ceb; } mem_t; -module sub - (input bist_0, - input bist_1, - input bist_2, - output y - ); - assign y = bist_0 | bist_1 | bist_2; +module sub ( + input bist_0, + input bist_1, + input bist_2, + output y +); + assign y = bist_0 | bist_1 | bist_2; endmodule -module t - (input mem_t i_ram_mbist [7:0], - output y - ); - sub sub - (.y, +module t ( + input mem_t i_ram_mbist[7:0], + output y +); + sub sub ( + .y, .bist_0(i_ram_mbist[0].bist), .bist_1(i_ram_mbist[1].bist), .bist_2(i_ram_mbist[2].bist) - ); + ); endmodule diff --git a/test_regress/t/t_var_types.v b/test_regress/t/t_var_types.v index d410af232..4e0a5f9b5 100644 --- a/test_regress/t/t_var_types.v +++ b/test_regress/t/t_var_types.v @@ -6,92 +6,92 @@ module t; - // IEEE: integer_atom_type - byte d_byte; - shortint d_shortint; - int d_int; - longint d_longint; - integer d_integer; - time d_time; - chandle d_chandle; + // IEEE: integer_atom_type + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; - // IEEE: integer_atom_type - bit d_bit; - logic d_logic; - reg d_reg; + // IEEE: integer_atom_type + bit d_bit; + logic d_logic; + reg d_reg; - bit [1:0] d_bit2; - logic [1:0] d_logic2; - reg [1:0] d_reg2; + bit [1:0] d_bit2; + logic [1:0] d_logic2; + reg [1:0] d_reg2; - // IEEE: non_integer_type - //UNSUP shortreal d_shortreal; - real d_real; - realtime d_realtime; + // IEEE: non_integer_type + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; - // Declarations using var - var byte v_b; + // Declarations using var + var byte v_b; `ifndef VCS - var [2:0] v_b3; - var signed [2:0] v_bs; + var [2:0] v_b3; + var signed [2:0] v_bs; `endif - // verilator lint_off WIDTH - localparam p_implicit = {96{1'b1}}; - localparam [89:0] p_explicit = {96{1'b1}}; - localparam byte p_byte = {96{1'b1}}; - localparam shortint p_shortint = {96{1'b1}}; - localparam int p_int = {96{1'b1}}; - localparam longint p_longint = {96{1'b1}}; - localparam integer p_integer = {96{1'b1}}; - localparam reg p_reg = {96{1'b1}}; - localparam bit p_bit = {96{1'b1}}; - localparam logic p_logic = {96{1'b1}}; - localparam reg [0:0] p_reg1 = {96{1'b1}}; - localparam bit [0:0] p_bit1 = {96{1'b1}}; - localparam logic [0:0] p_logic1= {96{1'b1}}; - localparam reg [1:0] p_reg2 = {96{1'b1}}; - localparam bit [1:0] p_bit2 = {96{1'b1}}; - localparam logic [1:0] p_logic2= {96{1'b1}}; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + localparam p_implicit = {96{1'b1}}; + localparam [89:0] p_explicit = {96{1'b1}}; + localparam byte p_byte = {96{1'b1}}; + localparam shortint p_shortint = {96{1'b1}}; + localparam int p_int = {96{1'b1}}; + localparam longint p_longint = {96{1'b1}}; + localparam integer p_integer = {96{1'b1}}; + localparam reg p_reg = {96{1'b1}}; + localparam bit p_bit = {96{1'b1}}; + localparam logic p_logic = {96{1'b1}}; + localparam reg [0:0] p_reg1 = {96{1'b1}}; + localparam bit [0:0] p_bit1 = {96{1'b1}}; + localparam logic [0:0] p_logic1= {96{1'b1}}; + localparam reg [1:0] p_reg2 = {96{1'b1}}; + localparam bit [1:0] p_bit2 = {96{1'b1}}; + localparam logic [1:0] p_logic2= {96{1'b1}}; + // verilator lint_on WIDTH - byte v_byte[2]; - shortint v_shortint[2]; - int v_int[2]; - longint v_longint[2]; - integer v_integer[2]; - time v_time[2]; - chandle v_chandle[2]; - bit v_bit[2]; - logic v_logic[2]; - reg v_reg[2]; - real v_real[2]; - realtime v_realtime[2]; + byte v_byte[2]; + shortint v_shortint[2]; + int v_int[2]; + longint v_longint[2]; + integer v_integer[2]; + time v_time[2]; + chandle v_chandle[2]; + bit v_bit[2]; + logic v_logic[2]; + reg v_reg[2]; + real v_real[2]; + realtime v_realtime[2]; - // We do this in two steps so we can check that initialization inside functions works properly - // verilator lint_off WIDTH - function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction - function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction - function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction - function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction - function int f_int; int lv_int; f_int = lv_int; endfunction - function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction - function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction - function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction - function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction - function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction - function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction - function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction - function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction - function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction - function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction - function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction - function time f_time; time lv_time; f_time = lv_time; endfunction - function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction - // verilator lint_on WIDTH + // We do this in two steps so we can check that initialization inside functions works properly + // verilator lint_off WIDTH + function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction + function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction + function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction + function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction + function int f_int; int lv_int; f_int = lv_int; endfunction + function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction + function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction + function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction + function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction + function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction + function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction + function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction + function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction + function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction + function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction + function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction + function time f_time; time lv_time; f_time = lv_time; endfunction + function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction + // verilator lint_on WIDTH `ifdef verilator - // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! + // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! `define XINIT 1'b1 `define ALL_TWOSTATE 1'b1 `else @@ -100,128 +100,128 @@ module t; `endif `define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ - if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ - begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ - name = {96{1'b1}}; \ - if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ - if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ - name = {96{1'bx}}; \ - if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ - begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ + if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ + begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ + name = {96{1'b1}}; \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ + name = {96{1'bx}}; \ + if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ + begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ - initial begin - // verilator lint_off WIDTH - // verilator lint_off UNSIGNED - // name b sign twost 0init - `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); - `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); - `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); - `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); - `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); - `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); - `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); - `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); - `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); - // verilator lint_on WIDTH - // verilator lint_on UNSIGNED + initial begin + // verilator lint_off WIDTH + // verilator lint_off UNSIGNED + // name b sign twost 0init + `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); + `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); + `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); + `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); + `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); + `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); + // verilator lint_on WIDTH + // verilator lint_on UNSIGNED - // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles + // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles `ifdef VERILATOR // else indeterminate - if ($bits(d_chandle) !== 64) $stop; + if ($bits(d_chandle) !== 64) $stop; `endif `define CHECK_P(name,nbits) \ - if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ - // name b - `CHECK_P(p_implicit ,96); - `CHECK_P(p_implicit[0] ,1 ); - `CHECK_P(p_explicit ,90); - `CHECK_P(p_explicit[0] ,1 ); - `CHECK_P(p_byte ,8 ); - `CHECK_P(p_byte[0] ,1 ); - `CHECK_P(p_shortint ,16); - `CHECK_P(p_shortint[0] ,1 ); - `CHECK_P(p_int ,32); - `CHECK_P(p_int[0] ,1 ); - `CHECK_P(p_longint ,64); - `CHECK_P(p_longint[0] ,1 ); - `CHECK_P(p_integer ,32); - `CHECK_P(p_integer[0] ,1 ); - `CHECK_P(p_bit ,1 ); - `CHECK_P(p_logic ,1 ); - `CHECK_P(p_reg ,1 ); - `CHECK_P(p_bit1 ,1 ); - `CHECK_P(p_logic1 ,1 ); - `CHECK_P(p_reg1 ,1 ); - `CHECK_P(p_bit1[0] ,1 ); - `CHECK_P(p_logic1[0] ,1 ); - `CHECK_P(p_reg1[0] ,1 ); - `CHECK_P(p_bit2 ,2 ); - `CHECK_P(p_logic2 ,2 ); - `CHECK_P(p_reg2 ,2 ); + // name b + `CHECK_P(p_implicit ,96); + `CHECK_P(p_implicit[0] ,1 ); + `CHECK_P(p_explicit ,90); + `CHECK_P(p_explicit[0] ,1 ); + `CHECK_P(p_byte ,8 ); + `CHECK_P(p_byte[0] ,1 ); + `CHECK_P(p_shortint ,16); + `CHECK_P(p_shortint[0] ,1 ); + `CHECK_P(p_int ,32); + `CHECK_P(p_int[0] ,1 ); + `CHECK_P(p_longint ,64); + `CHECK_P(p_longint[0] ,1 ); + `CHECK_P(p_integer ,32); + `CHECK_P(p_integer[0] ,1 ); + `CHECK_P(p_bit ,1 ); + `CHECK_P(p_logic ,1 ); + `CHECK_P(p_reg ,1 ); + `CHECK_P(p_bit1 ,1 ); + `CHECK_P(p_logic1 ,1 ); + `CHECK_P(p_reg1 ,1 ); + `CHECK_P(p_bit1[0] ,1 ); + `CHECK_P(p_logic1[0] ,1 ); + `CHECK_P(p_reg1[0] ,1 ); + `CHECK_P(p_bit2 ,2 ); + `CHECK_P(p_logic2 ,2 ); + `CHECK_P(p_reg2 ,2 ); `define CHECK_B(varname,nbits) \ - if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ + if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ - `CHECK_B(v_byte[1] ,8 ); - `CHECK_B(v_shortint[1] ,16); - `CHECK_B(v_int[1] ,32); - `CHECK_B(v_longint[1] ,64); - `CHECK_B(v_integer[1] ,32); - `CHECK_B(v_time[1] ,64); - //`CHECK_B(v_chandle[1] - `CHECK_B(v_bit[1] ,1 ); - `CHECK_B(v_logic[1] ,1 ); - `CHECK_B(v_reg[1] ,1 ); - //`CHECK_B(v_real[1] ,64); // $bits not allowed - //`CHECK_B(v_realtime[1] ,64); // $bits not allowed + `CHECK_B(v_byte[1] ,8 ); + `CHECK_B(v_shortint[1] ,16); + `CHECK_B(v_int[1] ,32); + `CHECK_B(v_longint[1] ,64); + `CHECK_B(v_integer[1] ,32); + `CHECK_B(v_time[1] ,64); + //`CHECK_B(v_chandle[1] + `CHECK_B(v_bit[1] ,1 ); + `CHECK_B(v_logic[1] ,1 ); + `CHECK_B(v_reg[1] ,1 ); + //`CHECK_B(v_real[1] ,64); // $bits not allowed + //`CHECK_B(v_realtime[1] ,64); // $bits not allowed `define CHECK_F(fname,nbits,zeroinit) \ - if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ + if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ - // name b 0init - `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 - `CHECK_F(f_explicit ,90,1'b0); - `CHECK_F(f_byte ,8 ,1'b1); - `CHECK_F(f_shortint ,16,1'b1); - `CHECK_F(f_int ,32,1'b1); - `CHECK_F(f_longint ,64,1'b1); - `CHECK_F(f_integer ,32,1'b0); - `CHECK_F(f_time ,64,1'b0); + // name b 0init + `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 + `CHECK_F(f_explicit ,90,1'b0); + `CHECK_F(f_byte ,8 ,1'b1); + `CHECK_F(f_shortint ,16,1'b1); + `CHECK_F(f_int ,32,1'b1); + `CHECK_F(f_longint ,64,1'b1); + `CHECK_F(f_integer ,32,1'b0); + `CHECK_F(f_time ,64,1'b0); `ifdef VERILATOR // else indeterminate - `CHECK_F(f_chandle ,64,1'b0); + `CHECK_F(f_chandle ,64,1'b0); `endif - `CHECK_F(f_bit ,1 ,1'b1); - `CHECK_F(f_logic ,1 ,1'b0); - `CHECK_F(f_reg ,1 ,1'b0); - `CHECK_F(f_bit1 ,1 ,1'b1); - `CHECK_F(f_logic1 ,1 ,1'b0); - `CHECK_F(f_reg1 ,1 ,1'b0); - `CHECK_F(f_bit2 ,2 ,1'b1); - `CHECK_F(f_logic2 ,2 ,1'b0); - `CHECK_F(f_reg2 ,2 ,1'b0); + `CHECK_F(f_bit ,1 ,1'b1); + `CHECK_F(f_logic ,1 ,1'b0); + `CHECK_F(f_reg ,1 ,1'b0); + `CHECK_F(f_bit1 ,1 ,1'b1); + `CHECK_F(f_logic1 ,1 ,1'b0); + `CHECK_F(f_reg1 ,1 ,1'b0); + `CHECK_F(f_bit2 ,2 ,1'b1); + `CHECK_F(f_logic2 ,2 ,1'b0); + `CHECK_F(f_reg2 ,2 ,1'b0); - // For unpacked types we don't want width warnings for unsized numbers that fit - d_byte = 2; - d_shortint= 2; - d_int = 2; - d_longint = 2; - d_integer = 2; + // For unpacked types we don't want width warnings for unsized numbers that fit + d_byte = 2; + d_shortint= 2; + d_int = 2; + d_longint = 2; + d_integer = 2; - // Special check - d_time = $time; - if ($time !== d_time) $stop; + // Special check + d_time = $time; + if ($time !== d_time) $stop; - // Null checks - d_chandle = null; - if (d_chandle != null) $stop; - if (d_chandle) $stop; + // Null checks + d_chandle = null; + if (d_chandle != null) $stop; + if (d_chandle) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_types_bad.out b/test_regress/t/t_var_types_bad.out index 89cb32d5e..bccf89dcc 100644 --- a/test_regress/t/t_var_types_bad.out +++ b/test_regress/t/t_var_types_bad.out @@ -1,32 +1,32 @@ -%Error: t/t_var_types_bad.v:39:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' +%Error: t/t_var_types_bad.v:40:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' : ... note: In instance 't' - 39 | d_bitz[0] = 1'b1; - | ^ + 40 | d_bitz[0] = 1'b1; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_types_bad.v:40:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... note: In instance 't' - 40 | d_logicz[0] = 1'b1; - | ^ %Error: t/t_var_types_bad.v:41:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 41 | d_regz[0] = 1'b1; + 41 | d_logicz[0] = 1'b1; | ^ -%Error: t/t_var_types_bad.v:46:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' +%Error: t/t_var_types_bad.v:42:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 46 | d_real[0] = 1'b1; - | ^ -%Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer; expected integral input to SEL + 42 | d_regz[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:47:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' + : ... note: In instance 't' + 47 | d_real[0] = 1'b1; + | ^ +%Warning-REALCVT: t/t_var_types_bad.v:47:5: Implicit conversion of real to integer; expected integral input to SEL : ... note: In instance 't' - 46 | d_real[0] = 1'b1; - | ^~~~~~ + 47 | d_real[0] = 1'b1; + | ^~~~~~ ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. -%Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' +%Error: t/t_var_types_bad.v:48:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... note: In instance 't' - 47 | d_realtime[0] = 1'b1; - | ^ -%Warning-REALCVT: t/t_var_types_bad.v:47:7: Implicit conversion of real to integer; expected integral input to SEL + 48 | d_realtime[0] = 1'b1; + | ^ +%Warning-REALCVT: t/t_var_types_bad.v:48:5: Implicit conversion of real to integer; expected integral input to SEL : ... note: In instance 't' - 47 | d_realtime[0] = 1'b1; - | ^~~~~~~~~~ + 48 | d_realtime[0] = 1'b1; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_types_bad.v b/test_regress/t/t_var_types_bad.v index ccd9a587f..b624d4f27 100644 --- a/test_regress/t/t_var_types_bad.v +++ b/test_regress/t/t_var_types_bad.v @@ -4,58 +4,59 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; - // IEEE: integer_atom_type - byte d_byte; - shortint d_shortint; - int d_int; - longint d_longint; - integer d_integer; - time d_time; - chandle d_chandle; + // IEEE: integer_atom_type + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; - // IEEE: integer_atom_type - bit d_bit; - logic d_logic; - reg d_reg; + // IEEE: integer_atom_type + bit d_bit; + logic d_logic; + reg d_reg; - bit [0:0] d_bit1; - logic [0:0] d_logic1; - reg [0:0] d_reg1; + bit [0:0] d_bit1; + logic [0:0] d_logic1; + reg [0:0] d_reg1; - bit d_bitz; - logic d_logicz; - reg d_regz; + bit d_bitz; + logic d_logicz; + reg d_regz; - // IEEE: non_integer_type - //UNSUP shortreal d_shortreal; - real d_real; - realtime d_realtime; + // IEEE: non_integer_type + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; - initial begin - // below errors might cause spurious warnings - // verilator lint_off WIDTH - d_bitz[0] = 1'b1; // Illegal range - d_logicz[0] = 1'b1; // Illegal range - d_regz[0] = 1'b1; // Illegal range + initial begin + // below errors might cause spurious warnings + // verilator lint_off WIDTH + d_bitz[0] = 1'b1; // Illegal range + d_logicz[0] = 1'b1; // Illegal range + d_regz[0] = 1'b1; // Illegal range `ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now - d_chandle[0] = 1'b1; // Illegal + d_chandle[0] = 1'b1; // Illegal `endif - d_real[0] = 1'b1; // Illegal - d_realtime[0] = 1'b1; // Illegal - // verilator lint_on WIDTH + d_real[0] = 1'b1; // Illegal + d_realtime[0] = 1'b1; // Illegal + // verilator lint_on WIDTH - d_byte[0] = 1'b1; // OK - d_shortint[0] = 1'b1; // OK - d_int[0] = 1'b1; // OK - d_longint[0] = 1'b1; // OK - d_integer[0] = 1'b1; // OK - d_time[0] = 1'b1; // OK + d_byte[0] = 1'b1; // OK + d_shortint[0] = 1'b1; // OK + d_int[0] = 1'b1; // OK + d_longint[0] = 1'b1; // OK + d_integer[0] = 1'b1; // OK + d_time[0] = 1'b1; // OK - d_bit1[0] = 1'b1; // OK - d_logic1[0] = 1'b1; // OK - d_reg1[0] = 1'b1; // OK - end + d_bit1[0] = 1'b1; // OK + d_logic1[0] = 1'b1; // OK + d_reg1[0] = 1'b1; // OK + end endmodule diff --git a/test_regress/t/t_var_vec_sel.v b/test_regress/t/t_var_vec_sel.v index b7ac89c82..99ce12c2f 100644 --- a/test_regress/t/t_var_vec_sel.v +++ b/test_regress/t/t_var_vec_sel.v @@ -7,21 +7,21 @@ // bug601 module t ( - input clk, - input [3:0] in3, // worky - input [0:0] in2 [3:0], // worky - input in1 [3:0], // no worky - input [1:0] sel, - output reg out1, - output reg out2, - output reg out3 - ); + input clk, + input [3:0] in3, // worky + input [0:0] in2[3:0], // worky + input in1[3:0], // no worky + input [1:0] sel, + output reg out1, + output reg out2, + output reg out3 +); - always @(posedge clk) begin - out3 <= in3[sel] ? in3[sel] : out3; - out2 <= in2[sel] ? in2[sel] : out2; - out1 <= in1[sel] ? in1[sel] : out1; // breaks - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + out3 <= in3[sel] ? in3[sel] : out3; + out2 <= in2[sel] ? in2[sel] : out2; + out1 <= in1[sel] ? in1[sel] : out1; // breaks + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_var_xref_bad.out b/test_regress/t/t_var_xref_bad.out index c050583b3..36b8a9fef 100644 --- a/test_regress/t/t_var_xref_bad.out +++ b/test_regress/t/t_var_xref_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_var_xref_bad.v:11:12: Found definition of 'tsk' as a TASK but expected a scope/variable - 11 | initial tsk.bad_missing_ref = 0; - | ^~~ +%Error: t/t_var_xref_bad.v:11:11: Found definition of 'tsk' as a TASK but expected a scope/variable + 11 | initial tsk.bad_missing_ref = 0; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_var_xref_bad.v b/test_regress/t/t_var_xref_bad.v index c7b00fb81..75edccfe2 100644 --- a/test_regress/t/t_var_xref_bad.v +++ b/test_regress/t/t_var_xref_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - task tsk; - endtask + task tsk; + endtask - initial tsk.bad_missing_ref = 0; + initial tsk.bad_missing_ref = 0; endmodule diff --git a/test_regress/t/t_var_xref_gen.v b/test_regress/t/t_var_xref_gen.v index 39a3faf1e..a9c480593 100644 --- a/test_regress/t/t_var_xref_gen.v +++ b/test_regress/t/t_var_xref_gen.v @@ -7,38 +7,45 @@ // SPDX-FileCopyrightText: 2015 Jie Xu and Roland Kruse // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, addr, res - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + addr, + res +); - input clk; + input clk; - input [31:0] addr; - output [15:0] res; + input [31:0] addr; + output [15:0] res; - memory i_mem(.addr(addr),.dout(res)); + memory i_mem ( + .addr(addr), + .dout(res) + ); - assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; + assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; endmodule -module memory(addr, dout); - parameter CM_XROWSIZE = 256; - parameter CM_NUMXROWS = 2; +module memory ( + addr, + dout +); + parameter CM_XROWSIZE = 256; + parameter CM_NUMXROWS = 2; - input [31:0] addr; - output [15:0] dout; + input [31:0] addr; + output [15:0] dout; - generate - genvar g_cx; - for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) - begin: cxrow_inst - reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; - end - endgenerate + generate + genvar g_cx; + for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) begin : cxrow_inst + reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; + end + endgenerate - assign dout = cxrow_inst[0].cmem_xrow[addr]; + assign dout = cxrow_inst[0].cmem_xrow[addr]; endmodule diff --git a/test_regress/t/t_varref_scope_in_interface.v b/test_regress/t/t_varref_scope_in_interface.v index d598f35e6..14df8a43b 100644 --- a/test_regress/t/t_varref_scope_in_interface.v +++ b/test_regress/t/t_varref_scope_in_interface.v @@ -4,11 +4,13 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface iface #(parameter DWIDTH = 32)(); +interface iface #( + parameter DWIDTH = 32 +) (); localparam TOTAL_PACKED_WIDTH = DWIDTH + 1; modport Tx(output sop, data, import unpack); logic sop; - logic [DWIDTH - 1:0] data = '0; + logic [DWIDTH - 1:0] data = '0; task static unpack(input logic [TOTAL_PACKED_WIDTH-1:0] packed_in, input logic sop_i); logic sop_nc; @@ -18,5 +20,5 @@ interface iface #(parameter DWIDTH = 32)(); endinterface module t; -iface ifc(); + iface ifc (); endmodule diff --git a/test_regress/t/t_verilated_all.v b/test_regress/t/t_verilated_all.v index f34361b2c..2d706bdd6 100644 --- a/test_regress/t/t_verilated_all.v +++ b/test_regress/t/t_verilated_all.v @@ -5,40 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 class Rnd; - rand bit x; + rand bit x; endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); - Rnd c; +module t ( + input clk +); - input clk; + Rnd c; - int cyc; - integer rand_result; - integer seed = 123; + int cyc; + integer rand_result; + integer seed = 123; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc != 0) begin - if (cyc == 10) begin - #5; - $display("dist: %f ", $dist_poisson(seed, 12)); // Get verilated_probdist.cpp - c = new; - rand_result = c.randomize(); - $display("rand: %x x: %x ", rand_result, c.x); // Get verilated_random.cpp - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc != 0) begin + if (cyc == 10) begin + #5; + $display("dist: %f ", $dist_poisson(seed, 12)); // Get verilated_probdist.cpp + c = new; + rand_result = c.randomize(); + $display("rand: %x x: %x ", rand_result, c.x); // Get verilated_random.cpp + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end - cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + cyc_eq_5 : + cover property (@(posedge clk) cyc == 5) $display("*COVER: Cyc==5"); - export "DPI-C" function dpix_f_int; - function int dpix_f_int (); - return cyc; - endfunction + export "DPI-C" function dpix_f_int; + function int dpix_f_int(); + return cyc; + endfunction endmodule diff --git a/test_regress/t/t_verilated_debug.v b/test_regress/t/t_verilated_debug.v index 7795281e6..0250b3907 100644 --- a/test_regress/t/t_verilated_debug.v +++ b/test_regress/t/t_verilated_debug.v @@ -4,25 +4,22 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [95:0] wide; - reg [95:0] wide; + initial begin + // internal code coverage for _vl_debug_print_w + wide = {32'haa, 32'hbb, 32'hcc}; + $c("_vl_debug_print_w(", $bits(wide), ", ", wide, ");"); + end - initial begin - // internal code coverage for _vl_debug_print_w - wide = {32'haa, 32'hbb, 32'hcc}; - $c("_vl_debug_print_w(", $bits(wide), ", ", wide, ");"); - end - - // Test loop - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_verilated_header.v b/test_regress/t/t_verilated_header.v index 6a41aac7c..aada9f6b4 100644 --- a/test_regress/t/t_verilated_header.v +++ b/test_regress/t/t_verilated_header.v @@ -8,12 +8,12 @@ module t; - initial begin - `verilator_file_descriptor i; - `coverage_block_off - i = $fopen("/dev/null", "r"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + `verilator_file_descriptor i; + `coverage_block_off + i = $fopen("/dev/null", "r"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_virtual_interface_delayed.v b/test_regress/t/t_virtual_interface_delayed.v index 3c7126751..42fea41ba 100644 --- a/test_regress/t/t_virtual_interface_delayed.v +++ b/test_regress/t/t_virtual_interface_delayed.v @@ -10,37 +10,39 @@ // verilog_format: on interface Ifc; - bit [7:0] rdata; + bit [7:0] rdata; endinterface class drv_c; - virtual Ifc vif; + virtual Ifc vif; - virtual task run(); - #100; - `checkh(vif.rdata, 8'haa); - #100; - `checkh(vif.rdata, 8'haa); - #100; - endtask + virtual task run(); + #100; + `checkh(vif.rdata, 8'haa); + #100; + `checkh(vif.rdata, 8'haa); + #100; + endtask endclass -module dut (output wire [7:0] rd_val); - assign rd_val = 8'haa; +module dut ( + output wire [7:0] rd_val +); + assign rd_val = 8'haa; endmodule module m; - drv_c d_0; + drv_c d_0; - Ifc u_Ifc (); - dut u_dut (.rd_val (u_Ifc.rdata)); + Ifc u_Ifc (); + dut u_dut (.rd_val(u_Ifc.rdata)); - initial begin - d_0 = new(); - d_0.vif = u_Ifc; - //u_Ifc.rdata = 10; - d_0.run(); - $write("*-* All Finished *-*\n"); - $finish(2); - end + initial begin + d_0 = new(); + d_0.vif = u_Ifc; + //u_Ifc.rdata = 10; + d_0.run(); + $write("*-* All Finished *-*\n"); + $finish(2); + end endmodule diff --git a/test_regress/t/t_virtual_interface_member_trigger.v b/test_regress/t/t_virtual_interface_member_trigger.v index 391075ae1..91f49885a 100644 --- a/test_regress/t/t_virtual_interface_member_trigger.v +++ b/test_regress/t/t_virtual_interface_member_trigger.v @@ -4,76 +4,76 @@ // SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ps +`timescale 1ns / 1ps interface INTF; - logic x; - logic y; - logic z; - logic [7:0] data; + logic x; + logic y; + logic z; + logic [7:0] data; endinterface class Dummy; - virtual INTF vif; - function new(virtual INTF vif); - this.vif = vif; - endfunction - task write_data(logic [7:0] d); - vif.data = d; - endtask + virtual INTF vif; + function new(virtual INTF vif); + this.vif = vif; + endfunction + task write_data(logic [7:0] d); + vif.data = d; + endtask endclass -module t_virtual_interface_member_trigger(); - // === Part 1: logic trigger false loop test === - logic s1, s2, src_val; - INTF intf_loop(); - virtual INTF vif_loop; - assign intf_loop.x = s1; - assign intf_loop.y = src_val; - assign intf_loop.z = !intf_loop.y; - assign s2 = intf_loop.z; - assign s1 = s2; +module t_virtual_interface_member_trigger (); + // === Part 1: logic trigger false loop test === + logic s1, s2, src_val; + INTF intf_loop (); + virtual INTF vif_loop; + assign intf_loop.x = s1; + assign intf_loop.y = src_val; + assign intf_loop.z = !intf_loop.y; + assign s2 = intf_loop.z; + assign s1 = s2; - // === Part 2: data transfer chain test === - logic [7:0] data; - INTF intf_read(); - INTF intf_write(); - assign intf_read.data = data; - assign data = intf_write.data; - virtual INTF vif_read, vif_write; + // === Part 2: data transfer chain test === + logic [7:0] data; + INTF intf_read (); + INTF intf_write (); + assign intf_read.data = data; + assign data = intf_write.data; + virtual INTF vif_read, vif_write; - Dummy cl_1, cl_2; + Dummy cl_1, cl_2; - initial begin + initial begin - // Test 1: no false loop with member-level trigger - #1ns; - vif_loop = intf_loop; - cl_1 = new(vif_loop); - #1ns; - src_val = 0; - #1ns; - if (!(cl_1.vif.x == 1 && cl_1.vif.y == 0 && cl_1.vif.z == 1 && s1 == 1 && s2 == 1)) $stop; + // Test 1: no false loop with member-level trigger + #1ns; + vif_loop = intf_loop; + cl_1 = new(vif_loop); + #1ns; + src_val = 0; + #1ns; + if (!(cl_1.vif.x == 1 && cl_1.vif.y == 0 && cl_1.vif.z == 1 && s1 == 1 && s2 == 1)) $stop; - // Test 2: write from module - #1ns; - vif_read = intf_read; - vif_write = intf_write; - #1ns; - vif_write.data = 8'hA5; - #1ns; - if (vif_read.data !== 8'hA5) $stop; + // Test 2: write from module + #1ns; + vif_read = intf_read; + vif_write = intf_write; + #1ns; + vif_write.data = 8'hA5; + #1ns; + if (vif_read.data !== 8'hA5) $stop; - // Test 3: write from class - #1ns; - cl_2 = new(vif_write); - #1ns; - cl_2.write_data(8'hB7); - #1ns; - if (vif_read.data !== 8'hB7) $stop; + // Test 3: write from class + #1ns; + cl_2 = new(vif_write); + #1ns; + cl_2.write_data(8'hB7); + #1ns; + if (vif_read.data !== 8'hB7) $stop; - #5ns; - $write("*-* All Finished *-*\n"); - $finish; - end + #5ns; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_virtual_interface_member_trigger_real.v b/test_regress/t/t_virtual_interface_member_trigger_real.v index 11eef5026..846425afe 100644 --- a/test_regress/t/t_virtual_interface_member_trigger_real.v +++ b/test_regress/t/t_virtual_interface_member_trigger_real.v @@ -4,135 +4,141 @@ // SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ps +`timescale 1ns / 1ps -interface INTF(); - logic clk; - logic [7:0] data; - logic valid; - logic ready; +interface INTF (); + logic clk; + logic [7:0] data; + logic valid; + logic ready; endinterface time TA = 5ns; class intf_driver; - virtual INTF intf; - function new(virtual INTF intf); - this.intf = intf; - endfunction + virtual INTF intf; + function new(virtual INTF intf); + this.intf = intf; + endfunction - task cycle_start(); - #TA; - endtask + task cycle_start(); + #TA; + endtask - task cycle_end(); - @(posedge intf.clk); - endtask + task cycle_end(); + @(posedge intf.clk); + endtask - task init_master(); - intf.data = '0; - intf.valid = 0; - endtask + task init_master(); + intf.data = '0; + intf.valid = 0; + endtask - task init_slave(); - intf.ready = 0; - endtask + task init_slave(); + intf.ready = 0; + endtask - task recv_data(output logic [7:0] data); - intf.ready <= #TA 1; - cycle_start(); - while (!(intf.valid && intf.ready)) begin cycle_end(); cycle_start(); end - cycle_end(); - data = intf.data; - intf.ready <= #TA 0; - endtask + task recv_data(output logic [7:0] data); + intf.ready <= #TA 1; + cycle_start(); + while (!(intf.valid && intf.ready)) begin + cycle_end(); + cycle_start(); + end + cycle_end(); + data = intf.data; + intf.ready <= #TA 0; + endtask - task send_data(input logic [7:0] data); - intf.data <= #TA data; - intf.valid <= #TA 1; - cycle_start(); - while (!(intf.valid && intf.ready)) begin cycle_end(); cycle_start(); end - cycle_end(); - intf.valid <= #TA 0; - endtask + task send_data(input logic [7:0] data); + intf.data <= #TA data; + intf.valid <= #TA 1; + cycle_start(); + while (!(intf.valid && intf.ready)) begin + cycle_end(); + cycle_start(); + end + cycle_end(); + intf.valid <= #TA 0; + endtask endclass module t; - logic clk; - logic [7:0] data; - logic valid; - logic ready; - logic [7:0] recv_data; + logic clk; + logic [7:0] data; + logic valid; + logic ready; + logic [7:0] recv_data; - INTF read_intf(); - assign read_intf.clk = clk; - assign read_intf.data = data; - assign read_intf.valid = valid; - assign ready = read_intf.ready; + INTF read_intf (); + assign read_intf.clk = clk; + assign read_intf.data = data; + assign read_intf.valid = valid; + assign ready = read_intf.ready; - INTF write_intf(); - assign write_intf.clk = clk; - assign data = write_intf.data; - assign valid = write_intf.valid; - assign write_intf.ready = ready; + INTF write_intf (); + assign write_intf.clk = clk; + assign data = write_intf.data; + assign valid = write_intf.valid; + assign write_intf.ready = ready; - intf_driver driver_master; - intf_driver driver_slave; + intf_driver driver_master; + intf_driver driver_slave; - virtual INTF vif_read = read_intf; - virtual INTF vif_write = write_intf; + virtual INTF vif_read = read_intf; + virtual INTF vif_write = write_intf; - initial begin - repeat(1000) begin - clk = '1; - #10ns; - clk = '0; - #10ns; - end + initial begin + repeat (1000) begin + clk = '1; + #10ns; + clk = '0; + #10ns; end + end - initial begin - driver_master = new(vif_write); - driver_slave = new(vif_read); + initial begin + driver_master = new(vif_write); + driver_slave = new(vif_read); - driver_master.init_master(); - driver_slave.init_slave(); - fork - begin - #35ns; - driver_master.send_data(8'h42); - // $display("[%0d]: Write data: %02x", $time, write_intf.data); - #10ns; - driver_master.send_data(8'h43); - // $display("[%0d]: Write data: %02x", $time, write_intf.data); - #10ns; - driver_master.send_data(8'h44); - // $display("[%0d]: Write data: %02x", $time, write_intf.data); - end - begin - #10ns; - driver_slave.recv_data(recv_data); - // $display("[%0d]: Got data: %02x", $time, recv_data); - if (recv_data !== 8'h42) $stop; - #5ns; - driver_slave.recv_data(recv_data); - // $display("[%0d]: Got data: %02x", $time, recv_data); - if (recv_data !== 8'h43) $stop; - #15ns; - driver_slave.recv_data(recv_data); - // $display("[%0d]: Got data: %02x", $time, recv_data); - if (recv_data !== 8'h44) $stop; - end - join + driver_master.init_master(); + driver_slave.init_slave(); + fork + begin + #35ns; + driver_master.send_data(8'h42); + // $display("[%0d]: Write data: %02x", $time, write_intf.data); + #10ns; + driver_master.send_data(8'h43); + // $display("[%0d]: Write data: %02x", $time, write_intf.data); + #10ns; + driver_master.send_data(8'h44); + // $display("[%0d]: Write data: %02x", $time, write_intf.data); + end + begin + #10ns; + driver_slave.recv_data(recv_data); + // $display("[%0d]: Got data: %02x", $time, recv_data); + if (recv_data !== 8'h42) $stop; + #5ns; + driver_slave.recv_data(recv_data); + // $display("[%0d]: Got data: %02x", $time, recv_data); + if (recv_data !== 8'h43) $stop; + #15ns; + driver_slave.recv_data(recv_data); + // $display("[%0d]: Got data: %02x", $time, recv_data); + if (recv_data !== 8'h44) $stop; + end + join - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end - // Dump waveforms - // initial begin - // $dumpfile("t_virtual_interface_member_trigger.vcd"); - // $dumpvars(0, t_virtual_interface_member_trigger); - // end + // Dump waveforms + // initial begin + // $dumpfile("t_virtual_interface_member_trigger.vcd"); + // $dumpvars(0, t_virtual_interface_member_trigger); + // end endmodule diff --git a/test_regress/t/t_virtual_interface_pkg.v b/test_regress/t/t_virtual_interface_pkg.v index 8d94418b4..22ffeba12 100644 --- a/test_regress/t/t_virtual_interface_pkg.v +++ b/test_regress/t/t_virtual_interface_pkg.v @@ -6,59 +6,58 @@ package my_pkg; - virtual class CallBackBase; - pure virtual function void add(int a, int b); - endclass + virtual class CallBackBase; + pure virtual function void add(int a, int b); + endclass - class my_class extends CallBackBase; - virtual my_interface vif; + class my_class extends CallBackBase; + virtual my_interface vif; - function new(virtual my_interface vif); - this.vif = vif; - $display("my_class::new"); - vif.register_callback(this); - endfunction + function new(virtual my_interface vif); + this.vif = vif; + $display("my_class::new"); + vif.register_callback(this); + endfunction - function void add(int a, int b); - // $display("a + b = %0d", a + b); - endfunction - endclass + function void add(int a, int b); + // $display("a + b = %0d", a + b); + endfunction + endclass endpackage interface my_interface; - import my_pkg::*; - CallBackBase callback_obj; + import my_pkg::*; + CallBackBase callback_obj; - function void register_callback(CallBackBase obj); - callback_obj = obj; - endfunction + function void register_callback(CallBackBase obj); + callback_obj = obj; + endfunction - logic clk; - always @(posedge clk) begin - if (callback_obj != null) - callback_obj.add(1, 2); - else $display("callback_obj is null"); - end + logic clk; + always @(posedge clk) begin + if (callback_obj != null) callback_obj.add(1, 2); + else $display("callback_obj is null"); + end endinterface module t; - import my_pkg::*; - logic clk = 0; - my_interface vif(); - my_class cl; + import my_pkg::*; + logic clk = 0; + my_interface vif (); + my_class cl; - assign vif.clk = clk; + assign vif.clk = clk; - initial begin - forever #5 clk = ~clk; - end + initial begin + forever #5 clk = ~clk; + end - initial begin - #10; - cl = new(vif); - #100; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + cl = new(vif); + #100; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vlt_match_contents.out b/test_regress/t/t_vlt_match_contents.out index 4867ea0bc..1e0fc5160 100644 --- a/test_regress/t/t_vlt_match_contents.out +++ b/test_regress/t/t_vlt_match_contents.out @@ -1,7 +1,7 @@ -%Warning-UNUSEDSIGNAL: t/t_vlt_match_contents.v:11:10: Signal is not driven, nor used: 'usignal_contents_mismatch' - : ... note: In instance 't' - 11 | logic usignal_contents_mismatch; - | ^~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-UNUSEDSIGNAL: t/t_vlt_match_contents.v:11:9: Signal is not driven, nor used: 'usignal_contents_mismatch' + : ... note: In instance 't' + 11 | logic usignal_contents_mismatch; + | ^~~~~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_match_contents.v b/test_regress/t/t_vlt_match_contents.v index 7991f2d90..3666c4487 100644 --- a/test_regress/t/t_vlt_match_contents.v +++ b/test_regress/t/t_vlt_match_contents.v @@ -7,6 +7,6 @@ string MATCH_VERSION = "10.20"; module t; - logic usignal_contents_suppress; // Suppressed with -contents - logic usignal_contents_mismatch; // Doesn't match -contents + logic usignal_contents_suppress; // Suppressed with -contents + logic usignal_contents_mismatch; // Doesn't match -contents endmodule diff --git a/test_regress/t/t_vlt_match_error.v b/test_regress/t/t_vlt_match_error.v index a6a7f0447..59a8844e5 100644 --- a/test_regress/t/t_vlt_match_error.v +++ b/test_regress/t/t_vlt_match_error.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 module DECLFILENAME; - logic UNUSEDSIGNAL; - logic [0:1] ASCRANGE_UNDRIVEN; - always_comb begin - case (ASCRANGE_UNDRIVEN) - 2'b0x: UNUSEDSIGNAL = 1; - endcase - end + logic UNUSEDSIGNAL; + logic [0:1] ASCRANGE_UNDRIVEN; + always_comb begin + case (ASCRANGE_UNDRIVEN) + 2'b0x: UNUSEDSIGNAL = 1; + endcase + end `ifdef T_VLT_MATCH_ERROR_1 - import hi::*; + import hi::*; `elsif T_VLT_MATCH_ERROR_2 - initial $readmemh("", EC_ERROR); + initial $readmemh("", EC_ERROR); `elsif T_VLT_MATCH_ERROR_3 - initial #1; + initial #1; `endif endmodule diff --git a/test_regress/t/t_vlt_match_error_1.out b/test_regress/t/t_vlt_match_error_1.out index c57c35126..dcf82c95a 100644 --- a/test_regress/t/t_vlt_match_error_1.out +++ b/test_regress/t/t_vlt_match_error_1.out @@ -1,5 +1,5 @@ -%Error: t/t_vlt_match_error.v:17:12: Import package not found: 'hi' - 17 | import hi::*; - | ^~ +%Error: t/t_vlt_match_error.v:17:10: Import package not found: 'hi' + 17 | import hi::*; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_match_error_2.out b/test_regress/t/t_vlt_match_error_2.out index 2eff72b9f..627dea18e 100644 --- a/test_regress/t/t_vlt_match_error_2.out +++ b/test_regress/t/t_vlt_match_error_2.out @@ -1,5 +1,5 @@ -%Error: t/t_vlt_match_error.v:19:27: Can't find definition of variable: 'EC_ERROR' - 19 | initial $readmemh("", EC_ERROR); - | ^~~~~~~~ +%Error: t/t_vlt_match_error.v:19:25: Can't find definition of variable: 'EC_ERROR' + 19 | initial $readmemh("", EC_ERROR); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_match_error_3.out b/test_regress/t/t_vlt_match_error_3.out index 057fb9412..bffebc7e4 100644 --- a/test_regress/t/t_vlt_match_error_3.out +++ b/test_regress/t/t_vlt_match_error_3.out @@ -1,6 +1,6 @@ -%Error-NEEDTIMINGOPT: t/t_vlt_match_error.v:21:13: Use --timing or --no-timing to specify how delays should be handled +%Error-NEEDTIMINGOPT: t/t_vlt_match_error.v:21:11: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 'DECLFILENAME' - 21 | initial #1; - | ^ + 21 | initial #1; + | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn.v b/test_regress/t/t_vlt_warn.v index 99285a4ab..d8bb16f45 100644 --- a/test_regress/t/t_vlt_warn.v +++ b/test_regress/t/t_vlt_warn.v @@ -7,7 +7,7 @@ // Try inline config `ifdef verilator `verilator_config - lint_off -rule CASEX -file "t/t_vlt_warn.v" + lint_off -rule CASEX -file "t/t_vlt_warn.v" `verilog `endif @@ -15,20 +15,20 @@ module t; - reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 - reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 - reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 + reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 + reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 + reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 - // Must not turn back on warning disabled via control file - // verilator lint_on CASEINCOMPLETE - // verilator lint_on CASEX + // Must not turn back on warning disabled via control file + // verilator lint_on CASEINCOMPLETE + // verilator lint_on CASEX - initial begin - casex (1'b1) - 1'b0: $stop; - endcase + initial begin + casex (1'b1) + 1'b0: $stop; + endcase - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vlt_warn_bad.out b/test_regress/t/t_vlt_warn_bad.out index b39ee1db1..00654f259 100644 --- a/test_regress/t/t_vlt_warn_bad.out +++ b/test_regress/t/t_vlt_warn_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTHTRUNC: t/t_vlt_warn.v:20:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. +%Warning-WIDTHTRUNC: t/t_vlt_warn.v:20:32: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... note: In instance 't' - 20 | reg width_warn3_var_line20 = 2'b11; - | ^~~~~ + 20 | reg width_warn3_var_line20 = 2'b11; + | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn_file_bad.out b/test_regress/t/t_vlt_warn_file_bad.out index 77804160c..f43c9dfd0 100644 --- a/test_regress/t/t_vlt_warn_file_bad.out +++ b/test_regress/t/t_vlt_warn_file_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTHTRUNC: t/t_vlt_warn_file_bad.v:11:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. +%Warning-WIDTHTRUNC: t/t_vlt_warn_file_bad.v:11:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' - 11 | int warn_t = 64'h1; - | ^~~~~ + 11 | int warn_t = 64'h1; + | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn_file_bad.v b/test_regress/t/t_vlt_warn_file_bad.v index 47dcc0ad1..cd49667b3 100644 --- a/test_regress/t/t_vlt_warn_file_bad.v +++ b/test_regress/t/t_vlt_warn_file_bad.v @@ -7,6 +7,6 @@ `include "t_vlt_warn_file_bad_b.vh" module t; - sub sub(); - int warn_t = 64'h1; + sub sub (); + int warn_t = 64'h1; endmodule diff --git a/test_regress/t/t_vpi_cb_iter.v b/test_regress/t/t_vpi_cb_iter.v index c29aa6eb7..4a5f51807 100644 --- a/test_regress/t/t_vpi_cb_iter.v +++ b/test_regress/t/t_vpi_cb_iter.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - input clk - ); +module t ( /*AUTOARG*/ + // Inputs + input clk +); - reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] count /*verilator public_flat_rd */; - // Test loop - initial begin - count = 0; - end + // Test loop + initial begin + count = 0; + end - always @(posedge clk) begin - count <= count + 2; + always @(posedge clk) begin + count <= count + 2; - if (count == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (count == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule : t diff --git a/test_regress/t/t_vpi_const_type.v b/test_regress/t/t_vpi_const_type.v index df13f23f4..544570d12 100644 --- a/test_regress/t/t_vpi_const_type.v +++ b/test_regress/t/t_vpi_const_type.v @@ -8,27 +8,27 @@ import "DPI-C" context function int mon_check(); -module t (/*AUTOARG*/ - ); /*verilator public_module*/ +module t ( /*AUTOARG*/ +); /*verilator public_module*/ - parameter int intParam /*verilator public_flat_rd*/ = 5; - parameter real realParam /*verilator public_flat_rd*/ = 2.3; - parameter time timeParam /*verilator public_flat_rd*/ = 0; - parameter string strParam /*verilator public_flat_rd*/ = "abc"; + parameter int intParam /*verilator public_flat_rd*/ = 5; + parameter real realParam /*verilator public_flat_rd*/ = 2.3; + parameter time timeParam /*verilator public_flat_rd*/ = 0; + parameter string strParam /*verilator public_flat_rd*/ = "abc"; - logic [31:0] signal_rw /*verilator public_flat_rw*/; - logic [31:0] signal_rd /*verilator public_flat_rd*/; + logic [31:0] signal_rw /*verilator public_flat_rw*/; + logic [31:0] signal_rd /*verilator public_flat_rd*/; - int status; + int status; - initial begin - status = mon_check(); - if (status!=0) begin - $write("%%Error: t_vpi_const_type.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + status = mon_check(); + if (status != 0) begin + $write("%%Error: t_vpi_const_type.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_dump.v b/test_regress/t/t_vpi_dump.v index 81ea91a8d..3d69324c6 100644 --- a/test_regress/t/t_vpi_dump.v +++ b/test_regress/t/t_vpi_dump.v @@ -9,15 +9,15 @@ /* verilator public_on */ typedef struct packed { - logic [3:0][7:0] adr; // address - logic [3:0][7:0] dat; // data - int sel; // select + logic [3:0][7:0] adr; // address + logic [3:0][7:0] dat; // data + int sel; // select } t_bus; -interface TestInterface(); +interface TestInterface (); - logic [31:0] addr; - modport source (input addr); + logic [31:0] addr; + modport source(input addr); endinterface @@ -31,120 +31,121 @@ module t ( /*AUTOARG*/ ); - parameter int DO_GENERATE = 1; - parameter longint LONG_INT = 64'h123456789abcdef; + parameter int DO_GENERATE = 1; + parameter longint LONG_INT = 64'h123456789abcdef; - input clk; + input clk; - input [7:0] a; - output reg [7:0] x; + input [7:0] a; + output reg [7:0] x; - reg onebit; - reg [2:1] twoone; - reg [2:1] fourthreetwoone[4:3]; - reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND ; + reg onebit; + reg [2:1] twoone; + reg [2:1] fourthreetwoone[4:3]; + reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND ; - // verilator lint_off ASCRANGE - reg [0:61] quads[2:3]; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + reg [0:61] quads[2:3]; + // verilator lint_on ASCRANGE - reg [31:0] count; - reg [31:0] half_count; + reg [31:0] count; + reg [31:0] half_count; - reg [7:0] text_byte; - reg [15:0] text_half; - reg [31:0] text_word; - reg [63:0] text_long; - reg [511:0] text; + reg [7:0] text_byte; + reg [15:0] text_half; + reg [31:0] text_word; + reg [63:0] text_long; + reg [511:0] text; - integer status; + integer status; - real real1; - string str1; + real real1; + string str1; - t_bus bus1; + t_bus bus1; - ModSub sub (); + ModSub sub (); - TestInterface intf_arr[2](); + TestInterface intf_arr[2] (); - initial begin + initial begin - $write("*-* All Finished *-*\n"); - $finish(); - end + $write("*-* All Finished *-*\n"); + $finish(); + end - genvar i; - generate - for (i = 1; i <= 2; i = i + 1) begin : arr - ModArr #(.LENGTH(i)) arr (); + genvar i; + generate + for (i = 1; i <= 2; i = i + 1) begin : arr + ModArr #(.LENGTH(i)) arr (); + end + + for (i = 1; i <= 3; i = i + 1) begin : outer_scope + + parameter int scoped_param = i * 2; + + genvar j; + for (j = 1; j <= 3; j = j + 1) begin : inner_scope + parameter int scoped_param_inner = scoped_param + 1; + ModArr #(.LENGTH(scoped_param_inner)) arr (); + end + end + endgenerate - for (i = 1; i <= 3; i = i + 1) begin : outer_scope - - parameter int scoped_param = i * 2; - - genvar j; - for (j = 1; j <= 3; j = j + 1) begin : inner_scope - parameter int scoped_param_inner = scoped_param + 1; - ModArr #(.LENGTH(scoped_param_inner)) arr (); - - end - end - endgenerate - - ModSubWrapper sub_wrap (); + ModSubWrapper sub_wrap (); - generate - if (DO_GENERATE == 1) begin : cond_scope - ModSub scoped_sub (); - parameter int scoped_wire = 1; + generate + if (DO_GENERATE == 1) begin : cond_scope + ModSub scoped_sub (); + parameter int scoped_wire = 1; - ModSubWrapper sub_wrap_gen (); - end else begin : cond_scope_else - ModSub scoped_sub_else (); - end - endgenerate + ModSubWrapper sub_wrap_gen (); + end + else begin : cond_scope_else + ModSub scoped_sub_else (); + end + endgenerate endmodule : t module ModSub; - reg subsig1; - reg subsig2; + reg subsig1; + reg subsig2; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = subsig1 | subsig2; + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; `endif endmodule : ModSub module ModArr; - parameter LENGTH = 1; + parameter LENGTH = 1; - reg [LENGTH-1:0] sig; - reg [LENGTH-1:0] rfr; + reg [LENGTH-1:0] sig; + reg [LENGTH-1:0] rfr; - reg check; - reg verbose; + reg check; + reg verbose; - initial begin - sig = {LENGTH{1'b0}}; - rfr = {LENGTH{1'b0}}; - end + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + end - always @(posedge check) begin - if (verbose) $display("%m : %x %x", sig, rfr); - if (check && sig != rfr) $stop; - check <= 0; - end + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end endmodule : ModArr module ModSubWrapper; - ModSub my_sub (); + ModSub my_sub (); endmodule diff --git a/test_regress/t/t_vpi_dump_missing_scopes.v b/test_regress/t/t_vpi_dump_missing_scopes.v index c97803e7e..a993e6ff0 100644 --- a/test_regress/t/t_vpi_dump_missing_scopes.v +++ b/test_regress/t/t_vpi_dump_missing_scopes.v @@ -12,35 +12,33 @@ /* verilator public_on */ -module t ( /*AUTOARG*/ -); +module t; + + initial begin + $write("*-* All Finished *-*\n"); + $finish(); + end - initial begin - $write("*-* All Finished *-*\n"); - $finish(); - end - - - gen_wrapper top_wrap_1 (); - gen_wrapper top_wrap_2 (); + gen_wrapper top_wrap_1 (); + gen_wrapper top_wrap_2 (); endmodule : t module sub; - reg subsig1; + reg subsig1; endmodule : sub module gen_wrapper; - genvar i; - generate - for (i = 0; i < 1; i++) begin : gen_loop + genvar i; + generate + for (i = 0; i < 1; i++) begin : gen_loop - // This fixes the scope - // localparam int x = 2; + // This fixes the scope + // localparam int x = 2; - sub after_gen_loop (); - end - endgenerate + sub after_gen_loop (); + end + endgenerate endmodule diff --git a/test_regress/t/t_vpi_escape.v b/test_regress/t/t_vpi_escape.v index 8d02fee8c..6f82b878b 100644 --- a/test_regress/t/t_vpi_escape.v +++ b/test_regress/t/t_vpi_escape.v @@ -26,100 +26,100 @@ extern "C" int mon_check(); `verilog `endif - input clk; - input [7:0] a /*verilator public_flat_rw*/; - input \b.c /*verilator public_flat_rw*/; + input clk; + input [7:0] a /*verilator public_flat_rw*/; + input \b.c /*verilator public_flat_rw*/; - int cyc /*verilator public_flat_rd*/; + int cyc /*verilator public_flat_rd*/; - output \escaped_normal /*verilator public_flat_rd*/; - wire \escaped_normal = cyc[0]; + output \escaped_normal /*verilator public_flat_rd*/; + wire \escaped_normal = cyc[0]; - output double__underscore /*verilator public_flat_rd*/; - wire double__underscore = cyc[0]; - output double__underscore__vlt; // public in .vlt - wire double__underscore__vlt = cyc[0]; + output double__underscore /*verilator public_flat_rd*/; + wire double__underscore = cyc[0]; + output double__underscore__vlt; // public in .vlt + wire double__underscore__vlt = cyc[0]; - // C doesn't allow leading non-alpha, so must escape - output \9num ; - wire \9num = cyc[0]; + // C doesn't allow leading non-alpha, so must escape + output \9num ; + wire \9num = cyc[0]; - output \bra[ket]slash/dash-colon:9backslash\done ; - wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; + output \bra[ket]slash/dash-colon:9backslash\done ; + wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; - output \x.y /*verilator public_flat_rd*/; - wire \x.y = cyc[0]; + output \x.y /*verilator public_flat_rd*/; + wire \x.y = cyc[0]; - wire \wire = cyc[0]; + wire \wire = cyc[0]; - wire \check_alias /*verilator public_flat_rd*/ = cyc[0]; - wire \check:alias /*verilator public_flat_rd*/ = cyc[0]; - wire \check;alias /*verilator public_flat_rd*/ = !cyc[0]; + wire \check_alias /*verilator public_flat_rd*/ = cyc[0]; + wire \check:alias /*verilator public_flat_rd*/ = cyc[0]; + wire \check;alias /*verilator public_flat_rd*/ = !cyc[0]; - // These are *different entities*, bug83 - wire [31:0] \a0.cyc = ~a0.cyc; - wire [31:0] \other.cyc = ~a0.cyc; + // These are *different entities*, bug83 + wire [31:0] \a0.cyc = ~a0.cyc; + wire [31:0] \other.cyc = ~a0.cyc; - integer status; + integer status; - sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name a0 (.cyc(cyc)); + sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name a0 (.cyc(cyc)); - sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name \mod.with_dot (.cyc(cyc)); + sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name \mod.with_dot (.cyc(cyc)); - // Check if scope names are not decoded twice - sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0F_ (.cyc(cyc)); - sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0_ (.cyc(cyc)); + // Check if scope names are not decoded twice + sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0F_ (.cyc(cyc)); + sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0_ (.cyc(cyc)); - initial begin + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status != 0) begin - $write("%%Error: C Test failed with %0d error(s)\n", status); - $stop; - end - $write("%%Info: Checking results\n"); - end + if (status != 0) begin + $write("%%Error: C Test failed with %0d error(s)\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + end - always @ (posedge clk) begin - cyc <= cyc + 1; - if (escaped_normal != cyc[0]) $stop; - if (\escaped_normal != cyc[0]) $stop; - if (double__underscore != cyc[0]) $stop; - if (\9num != cyc[0]) $stop; - if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; - if (\x.y != cyc[0]) $stop; - if (\wire != cyc[0]) $stop; - if (\check_alias != cyc[0]) $stop; - if (\check:alias != cyc[0]) $stop; - if (\check;alias != !cyc[0]) $stop; - if (\a0.cyc != ~cyc) $stop; - if (\other.cyc != ~cyc) $stop; - if (cyc==10) begin - if (a != 2) $stop; - if (\b.c != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 1; + if (escaped_normal != cyc[0]) $stop; + if (\escaped_normal != cyc[0]) $stop; + if (double__underscore != cyc[0]) $stop; + if (\9num != cyc[0]) $stop; + if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; + if (\x.y != cyc[0]) $stop; + if (\wire != cyc[0]) $stop; + if (\check_alias != cyc[0]) $stop; + if (\check:alias != cyc[0]) $stop; + if (\check;alias != !cyc[0]) $stop; + if (\a0.cyc != ~cyc) $stop; + if (\other.cyc != ~cyc) $stop; + if (cyc==10) begin + if (a != 2) $stop; + if (\b.c != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ( - input [31:0] cyc /*verilator public_flat_rd*/ - ); - reg \b.c /*verilator public_flat_rw*/; - reg subsig1 /*verilator public_flat_rd*/; - reg subsig2; // public in .vlt + input [31:0] cyc /*verilator public_flat_rd*/ + ); + reg \b.c /*verilator public_flat_rw*/; + reg subsig1 /*verilator public_flat_rd*/; + reg subsig2; // public in .vlt `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = subsig1 | subsig2 | \b.c ; + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2 | \b.c ; `endif endmodule diff --git a/test_regress/t/t_vpi_finish.v b/test_regress/t/t_vpi_finish.v index e626020b4..60d55309b 100644 --- a/test_regress/t/t_vpi_finish.v +++ b/test_regress/t/t_vpi_finish.v @@ -8,10 +8,10 @@ module t; - import "DPI-C" function void dpii_test(); + import "DPI-C" function void dpii_test(); - initial begin - $write("*-* All Finished *-*\n"); - dpii_test(); // $finish - end + initial begin + $write("*-* All Finished *-*\n"); + dpii_test(); // $finish + end endmodule diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index 0a673a05e..140adc410 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -23,19 +23,19 @@ import "DPI-C" function void dpi_print(input string somestring); `endif interface intf #(parameter int param `PUBLIC_FLAT_RD = 7); - localparam int lparam `PUBLIC_FLAT_RD = param + 1; - logic [7:0] bytesig `PUBLIC_FLAT_RD; + localparam int lparam `PUBLIC_FLAT_RD = param + 1; + logic [7:0] bytesig `PUBLIC_FLAT_RD; endinterface module t (/*AUTOARG*/ - // Inputs - input clk `PUBLIC_FLAT_RD, + // Inputs + input clk `PUBLIC_FLAT_RD, - // test ports - input [15:0] testin `PUBLIC_FLAT_RD, - output [23:0] testout `PUBLIC_FLAT_RW + // test ports + input [15:0] testin `PUBLIC_FLAT_RD, + output [23:0] testout `PUBLIC_FLAT_RW - ); + ); `ifdef VERILATOR `systemc_header @@ -43,51 +43,51 @@ extern "C" int mon_check(); `verilog `endif - reg onebit `PUBLIC_FLAT_RW; - reg [2:1] twoone `PUBLIC_FLAT_RW; - reg onetwo [1:2] `PUBLIC_FLAT_RW; - reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; - reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW; - int theint `PUBLIC_FLAT_RW; + reg onebit `PUBLIC_FLAT_RW; + reg [2:1] twoone `PUBLIC_FLAT_RW; + reg onetwo [1:2] `PUBLIC_FLAT_RW; + reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; + reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW; + int theint `PUBLIC_FLAT_RW; - integer status; + integer status; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; + // stop icarus optimizing signals away + wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; `endif - wire subin `PUBLIC_FLAT_RD; - wire subout `PUBLIC_FLAT_RD; - sub sub(.*); + wire subin `PUBLIC_FLAT_RD; + wire subout `PUBLIC_FLAT_RD; + sub sub(.*); - // Test loop - initial begin - dpi_print("foo"); + // Test loop + initial begin + dpi_print("foo"); `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status!=0) begin + $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t module sub #( - parameter int subparam `PUBLIC_FLAT_RD = 2 + parameter int subparam `PUBLIC_FLAT_RD = 2 ) ( - input subin `PUBLIC_FLAT_RD, - output subout `PUBLIC_FLAT_RD + input subin `PUBLIC_FLAT_RD, + output subout `PUBLIC_FLAT_RD ); - intf the_intf(); + intf the_intf(); endmodule : sub diff --git a/test_regress/t/t_vpi_get_value_array.v b/test_regress/t/t_vpi_get_value_array.v index 522141003..8c603e8d0 100644 --- a/test_regress/t/t_vpi_get_value_array.v +++ b/test_regress/t/t_vpi_get_value_array.v @@ -22,84 +22,84 @@ extern "C" int mon_check(); `verilog `endif - reg [7:0] read_bytes [0:3] `PUBLIC_FLAT_RD; - reg [7:0] read_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RD; - reg [7:0] read_bytes_rl [3:0] `PUBLIC_FLAT_RD; + reg [7:0] read_bytes [0:3] `PUBLIC_FLAT_RD; + reg [7:0] read_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RD; + reg [7:0] read_bytes_rl [3:0] `PUBLIC_FLAT_RD; - reg [15:0] read_shorts [0:3] `PUBLIC_FLAT_RD; - reg [31:0] read_words [0:3] `PUBLIC_FLAT_RD; - reg [31:0] read_words_rl [3:0] `PUBLIC_FLAT_RD; - reg [63:0] read_longs [0:3] `PUBLIC_FLAT_RD; - integer read_integers [0:3] `PUBLIC_FLAT_RD; - reg [68:0] read_customs [0:3] `PUBLIC_FLAT_RD; - reg [68:0] read_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RD; + reg [15:0] read_shorts [0:3] `PUBLIC_FLAT_RD; + reg [31:0] read_words [0:3] `PUBLIC_FLAT_RD; + reg [31:0] read_words_rl [3:0] `PUBLIC_FLAT_RD; + reg [63:0] read_longs [0:3] `PUBLIC_FLAT_RD; + integer read_integers [0:3] `PUBLIC_FLAT_RD; + reg [68:0] read_customs [0:3] `PUBLIC_FLAT_RD; + reg [68:0] read_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RD; - reg [7:0] read_scalar `PUBLIC_FLAT_RD; - reg [7:0] read_bounds [1:3] `PUBLIC_FLAT_RD; + reg [7:0] read_scalar `PUBLIC_FLAT_RD; + reg [7:0] read_bounds [1:3] `PUBLIC_FLAT_RD; - integer status; + integer status; - initial begin - read_bytes[0] = 8'had; - read_bytes[1] = 8'hde; - read_bytes[2] = 8'hef; - read_bytes[3] = 8'hbe; + initial begin + read_bytes[0] = 8'had; + read_bytes[1] = 8'hde; + read_bytes[2] = 8'hef; + read_bytes[3] = 8'hbe; - read_bytes_rl[3] = 8'had; - read_bytes_rl[2] = 8'hde; - read_bytes_rl[1] = 8'hef; - read_bytes_rl[0] = 8'hbe; + read_bytes_rl[3] = 8'had; + read_bytes_rl[2] = 8'hde; + read_bytes_rl[1] = 8'hef; + read_bytes_rl[0] = 8'hbe; - read_bytes_nonzero_index[1] = 8'had; - read_bytes_nonzero_index[2] = 8'hde; - read_bytes_nonzero_index[3] = 8'hef; - read_bytes_nonzero_index[4] = 8'hbe; + read_bytes_nonzero_index[1] = 8'had; + read_bytes_nonzero_index[2] = 8'hde; + read_bytes_nonzero_index[3] = 8'hef; + read_bytes_nonzero_index[4] = 8'hbe; - read_shorts[0] = 16'hdead; - read_shorts[1] = 16'hbeef; - read_shorts[2] = 16'hcafe; - read_shorts[3] = 16'hf00d; + read_shorts[0] = 16'hdead; + read_shorts[1] = 16'hbeef; + read_shorts[2] = 16'hcafe; + read_shorts[3] = 16'hf00d; - read_words[0] = 32'hdeadbeef; - read_words[1] = 32'hcafef00d; - read_words[2] = 32'h00010203; - read_words[3] = 32'h04050607; + read_words[0] = 32'hdeadbeef; + read_words[1] = 32'hcafef00d; + read_words[2] = 32'h00010203; + read_words[3] = 32'h04050607; - read_integers[0] = 32'hdeadbeef; - read_integers[1] = 32'hcafef00d; - read_integers[2] = 32'h00010203; - read_integers[3] = 32'h04050607; + read_integers[0] = 32'hdeadbeef; + read_integers[1] = 32'hcafef00d; + read_integers[2] = 32'h00010203; + read_integers[3] = 32'h04050607; - read_longs[0] = 64'hdeadbeefcafef00d; - read_longs[1] = 64'h0001020304050607; - read_longs[2] = 64'h08090a0b0c0d0e0f; - read_longs[3] = 64'h1011121314151617; + read_longs[0] = 64'hdeadbeefcafef00d; + read_longs[1] = 64'h0001020304050607; + read_longs[2] = 64'h08090a0b0c0d0e0f; + read_longs[3] = 64'h1011121314151617; - read_customs[0] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF - read_customs[1] = 69'hF50001020304050607; - read_customs[2] = 69'h0A08090a0b0c0d0e0f; - read_customs[3] = 69'h051011121314151617; + read_customs[0] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF + read_customs[1] = 69'hF50001020304050607; + read_customs[2] = 69'h0A08090a0b0c0d0e0f; + read_customs[3] = 69'h051011121314151617; - read_customs_nonzero_index_rl[4] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF - read_customs_nonzero_index_rl[3] = 69'hF50001020304050607; - read_customs_nonzero_index_rl[2] = 69'h0A08090a0b0c0d0e0f; - read_customs_nonzero_index_rl[1] = 69'h051011121314151617; + read_customs_nonzero_index_rl[4] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF + read_customs_nonzero_index_rl[3] = 69'hF50001020304050607; + read_customs_nonzero_index_rl[2] = 69'h0A08090a0b0c0d0e0f; + read_customs_nonzero_index_rl[1] = 69'h051011121314151617; `ifdef IVERILOG - status = $mon_check; + status = $mon_check; `endif `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif - if (status != 0) begin - $write("%%Error: t_vpi_get_value_array.cpp:%0d: C Test failed\n", status); - $stop; - end + if (status != 0) begin + $write("%%Error: t_vpi_get_value_array.cpp:%0d: C Test failed\n", status); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vpi_memory.v b/test_regress/t/t_vpi_memory.v index 26d873254..f4f5288b4 100644 --- a/test_regress/t/t_vpi_memory.v +++ b/test_regress/t/t_vpi_memory.v @@ -13,9 +13,9 @@ import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `ifdef VERILATOR `systemc_header @@ -23,48 +23,48 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - typedef logic [31:0] word_t; - reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */; - reg [16:1] [31:0] memp32 /*verilator public_flat_rw @(posedge clk) */; - reg [16:1] [30:0] memp31 /*verilator public_flat_rw @(posedge clk) */; - reg [15:1] [32:0] memp33 /*verilator public_flat_rw @(posedge clk) */; - word_t [16:1] memw /*verilator public_flat_rw @(posedge clk) */; - integer i, status; + typedef logic [31:0] word_t; + reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */; + reg [16:1] [31:0] memp32 /*verilator public_flat_rw @(posedge clk) */; + reg [16:1] [30:0] memp31 /*verilator public_flat_rw @(posedge clk) */; + reg [15:1] [32:0] memp33 /*verilator public_flat_rw @(posedge clk) */; + word_t [16:1] memw /*verilator public_flat_rw @(posedge clk) */; + integer i, status; `define CHECK_MEM(mem, words) \ - for (i = words; i > 0; i--) \ - if (integer'(mem[i]) !== i) begin \ - $write("%%Error: %s[%d] : GOT = %d EXP = %d\n", `"mem`", i, mem[i], i); \ - status = -1; \ - end + for (i = words; i > 0; i--) \ + if (integer'(mem[i]) !== i) begin \ + $write("%%Error: %s[%d] : GOT = %d EXP = %d\n", `"mem`", i, mem[i], i); \ + status = -1; \ + end - // Test loop - initial begin + // Test loop + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `else - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status); - $stop; - end - `CHECK_MEM(mem0, 16) - `CHECK_MEM(memp32, 16) - `CHECK_MEM(memp31, 16) - `CHECK_MEM(memp33, 15) - `CHECK_MEM(memw, 16) - if (status!=0) begin - $write("%%Error: Verilog memory checks failed\n"); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status!=0) begin + $write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status); + $stop; + end + `CHECK_MEM(mem0, 16) + `CHECK_MEM(memp32, 16) + `CHECK_MEM(memp31, 16) + `CHECK_MEM(memp33, 15) + `CHECK_MEM(memw, 16) + if (status!=0) begin + $write("%%Error: Verilog memory checks failed\n"); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_module.v b/test_regress/t/t_vpi_module.v index aa6c6a8bd..dfb651df6 100644 --- a/test_regress/t/t_vpi_module.v +++ b/test_regress/t/t_vpi_module.v @@ -11,13 +11,13 @@ import "DPI-C" context function int mon_check(); `endif package somepackage; - int someint /*verilator public_flat_rw*/; + int someint /*verilator public_flat_rw*/; endpackage module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `ifdef USE_DOLLAR_C32 `systemc_header @@ -25,101 +25,101 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - integer status; + integer status; - wire a, b, x; + wire a, b, x; - A \mod.a (/*AUTOINST*/ - // Outputs - .x (x), - // Inputs - .clk (clk), - .a (a), - .b (b)); + A \mod.a (/*AUTOINST*/ + // Outputs + .x (x), + // Inputs + .clk (clk), + .a (a), + .b (b)); - // Test loop - initial begin + // Test loop + initial begin `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `elsif USE_DOLLAR_C32 - status = $c32("mon_check()"); + status = $c32("mon_check()"); `else - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status!=0) begin + $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t module A(/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a, b - ); + // Outputs + x, + // Inputs + clk, a, b + ); - input clk; + input clk; - input a, b; - output x; + input a, b; + output x; - wire y, c; + wire y, c; - B \mod_b$ (/*AUTOINST*/ - // Outputs - .y (y), - // Inputs - .b (b), - .c (c)); + B \mod_b$ (/*AUTOINST*/ + // Outputs + .y (y), + // Inputs + .b (b), + .c (c)); - C \mod\c$ (/*AUTOINST*/ - // Outputs - .x (x), - // Inputs - .clk (clk), - .a (a), - .y (y)); + C \mod\c$ (/*AUTOINST*/ + // Outputs + .x (x), + // Inputs + .clk (clk), + .a (a), + .y (y)); endmodule : A module B(/*AUTOARG*/ - // Outputs - y, - // Inputs - b, c - ); /*verilator public_module*/ - input b, c; + // Outputs + y, + // Inputs + b, c + ); /*verilator public_module*/ + input b, c; - output reg y; + output reg y; - always @(*) begin : myproc - y = b ^ c; - end + always @(*) begin : myproc + y = b ^ c; + end endmodule module C(/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a, y - ); + // Outputs + x, + // Inputs + clk, a, y + ); - input clk; + input clk; - input a, y; + input a, y; - output reg x /* verilator public_flat_rw */; + output reg x /* verilator public_flat_rw */; - always @(posedge clk) begin - x <= a & y; - end + always @(posedge clk) begin + x <= a & y; + end endmodule diff --git a/test_regress/t/t_vpi_module_empty.v b/test_regress/t/t_vpi_module_empty.v index dd193f7f2..f990f135d 100644 --- a/test_regress/t/t_vpi_module_empty.v +++ b/test_regress/t/t_vpi_module_empty.v @@ -6,20 +6,20 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -interface sv_if(); - logic a /*verilator public_flat_rw*/; +interface sv_if (); + logic a /*verilator public_flat_rw*/; endinterface module top (); - sv_if sv_if_i(); + sv_if sv_if_i (); - // Workaround for bug3937: - // logic d /*verilator public_flat_rw*/; + // Workaround for bug3937: + // logic d /*verilator public_flat_rw*/; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vpi_multidim.v b/test_regress/t/t_vpi_multidim.v index d4f6d9f32..23a01dd05 100644 --- a/test_regress/t/t_vpi_multidim.v +++ b/test_regress/t/t_vpi_multidim.v @@ -7,9 +7,9 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ - // Inputs - clk - ); /*verilator public_module*/ + // Inputs + clk + ); /*verilator public_module*/ `ifdef VERILATOR `systemc_header @@ -17,28 +17,28 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - logic [3:2][5:3] arr_cdata [1:0][2:1]; // 2x3 (6) bit words - logic [7:6][12:7] arr_sdata [5:4][6:5]; // 2x6 (12) bit words - logic [11:10][25:11] arr_idata [9:8][10:9]; // 2x15 (30) bit words - logic [15:14][44:15] arr_qdata [13:12][14:13]; // 2x30 (60) bit words - logic [19:18][81:19] arr_wdata [17:16][18:17]; // 2x63 (126) bit words + logic [3:2][5:3] arr_cdata [1:0][2:1]; // 2x3 (6) bit words + logic [7:6][12:7] arr_sdata [5:4][6:5]; // 2x6 (12) bit words + logic [11:10][25:11] arr_idata [9:8][10:9]; // 2x15 (30) bit words + logic [15:14][44:15] arr_qdata [13:12][14:13]; // 2x30 (60) bit words + logic [19:18][81:19] arr_wdata [17:16][18:17]; // 2x63 (126) bit words - int status; + int status; - initial begin + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `else - status = $mon_check(); + status = $mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_multidim.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status!=0) begin + $write("%%Error: t_vpi_multidim.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_package.v b/test_regress/t/t_vpi_package.v index 4d51d187a..054834dca 100644 --- a/test_regress/t/t_vpi_package.v +++ b/test_regress/t/t_vpi_package.v @@ -11,32 +11,31 @@ import "DPI-C" context function int mon_check(); parameter int dollarUnitInt = 3; package somepackage; - parameter int someInt = 5; - parameter int anotherInt = 6; + parameter int someInt = 5; + parameter int anotherInt = 6; endpackage -module t (/*AUTOARG*/ - ); +module t; - parameter int someOtherInt = 7; - parameter int yetAnotherInt = 9; - parameter int stillAnotherInt = 17; - parameter int register = 0; - parameter int n_str = 2; - // Edge case with pvi code generation - parameter string someString [n_str] = '{default: ""}; - logic reference; + parameter int someOtherInt = 7; + parameter int yetAnotherInt = 9; + parameter int stillAnotherInt = 17; + parameter int register = 0; + parameter int n_str = 2; + // Edge case with pvi code generation + parameter string someString[n_str] = '{default: ""}; + logic reference; - integer status; + integer status; - initial begin - status = mon_check(); - if (status!=0) begin - $write("%%Error: t_vpi_package.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + status = mon_check(); + if (status != 0) begin + $write("%%Error: t_vpi_package.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_param.v b/test_regress/t/t_vpi_param.v index 8e90125d8..2ec74ec0d 100644 --- a/test_regress/t/t_vpi_param.v +++ b/test_regress/t/t_vpi_param.v @@ -14,11 +14,11 @@ import "DPI-C" context function int mon_check(); module t #( - parameter int WIDTH /* verilator public_flat_rd */ = 32 + parameter int WIDTH /* verilator public_flat_rd */ = 32 ) (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `ifdef VERILATOR `systemc_header @@ -26,25 +26,25 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - localparam int DEPTH /* verilator public_flat_rd */ = 16; - localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210; - localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'"; + localparam int DEPTH /* verilator public_flat_rd */ = 16; + localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210; + localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'"; - reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */; - integer i, status; + reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */; + integer i, status; - // Test loop - initial begin + // Test loop + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif if (status!=0) begin @@ -53,6 +53,6 @@ extern "C" int mon_check(); end $write("*-* All Finished *-*\n"); $finish; - end + end endmodule : t diff --git a/test_regress/t/t_vpi_public_depth.v b/test_regress/t/t_vpi_public_depth.v index a0ccafb40..1226655b9 100644 --- a/test_regress/t/t_vpi_public_depth.v +++ b/test_regress/t/t_vpi_public_depth.v @@ -11,13 +11,13 @@ import "DPI-C" context function int mon_check(); `endif package somepackage; - int someint; + int someint; endpackage module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `ifdef USE_DOLLAR_C32 `systemc_header @@ -25,102 +25,102 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - integer status; + integer status; - wire a, b, x; + wire a, b, x; - A \mod.a (/*AUTOINST*/ - // Outputs - .x (x), - // Inputs - .clk (clk), - .a (a), - .b (b)); + A \mod.a (/*AUTOINST*/ + // Outputs + .x (x), + // Inputs + .clk (clk), + .a (a), + .b (b)); - // Test loop - initial begin + // Test loop + initial begin `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `elsif USE_DOLLAR_C32 - status = $c32("mon_check()"); + status = $c32("mon_check()"); `else - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status!=0) begin + $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t module A(/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a, b - ); + // Outputs + x, + // Inputs + clk, a, b + ); - // this comment should get ignored for public-ignore - input clk /* verilator public_flat_rw */; + // this comment should get ignored for public-ignore + input clk /* verilator public_flat_rw */; - input a, b; - output x; + input a, b; + output x; - wire y, c; + wire y, c; - B \mod_b$ (/*AUTOINST*/ - // Outputs - .y (y), - // Inputs - .b (b), - .c (c)); + B \mod_b$ (/*AUTOINST*/ + // Outputs + .y (y), + // Inputs + .b (b), + .c (c)); - C \mod\c$ (/*AUTOINST*/ - // Outputs - .x (x), - // Inputs - .clk (clk), - .a (a), - .y (y)); + C \mod\c$ (/*AUTOINST*/ + // Outputs + .x (x), + // Inputs + .clk (clk), + .a (a), + .y (y)); endmodule : A module B(/*AUTOARG*/ - // Outputs - y, - // Inputs - b, c - ); - input b, c; + // Outputs + y, + // Inputs + b, c + ); + input b, c; - output reg y; + output reg y; - always @(*) begin : myproc - y = b ^ c; - end + always @(*) begin : myproc + y = b ^ c; + end endmodule module C(/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a, y - ); + // Outputs + x, + // Inputs + clk, a, y + ); - input clk; + input clk; - input a, y; + input a, y; - output reg x; + output reg x; - always @(posedge clk) begin - x <= a & y; - end + always @(posedge clk) begin + x <= a & y; + end endmodule diff --git a/test_regress/t/t_vpi_public_params.v b/test_regress/t/t_vpi_public_params.v index 8be64a20e..7113e5554 100644 --- a/test_regress/t/t_vpi_public_params.v +++ b/test_regress/t/t_vpi_public_params.v @@ -14,11 +14,11 @@ import "DPI-C" context function int mon_check(); // Copy of t_vpi_public_params.v but with the inline public taken out module t #( - parameter int WIDTH = 32 + parameter int WIDTH = 32 ) (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); `ifdef VERILATOR `systemc_header @@ -26,25 +26,25 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - localparam int DEPTH = 16; - localparam longint PARAM_LONG = 64'hFEDCBA9876543210; - localparam string PARAM_STR = "'some string value'"; + localparam int DEPTH = 16; + localparam longint PARAM_LONG = 64'hFEDCBA9876543210; + localparam string PARAM_STR = "'some string value'"; - reg [WIDTH-1:0] mem0 [DEPTH:1]; - integer i, status; + reg [WIDTH-1:0] mem0 [DEPTH:1]; + integer i, status; - // Test loop - initial begin + // Test loop + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif if (status!=0) begin @@ -53,6 +53,6 @@ extern "C" int mon_check(); end $write("*-* All Finished *-*\n"); $finish; - end + end endmodule : t diff --git a/test_regress/t/t_vpi_put_value_array.v b/test_regress/t/t_vpi_put_value_array.v index c9c04397c..f8ff0df8a 100644 --- a/test_regress/t/t_vpi_put_value_array.v +++ b/test_regress/t/t_vpi_put_value_array.v @@ -22,55 +22,55 @@ extern "C" int mon_check(); `verilog `endif - reg [7:0] write_bytes [0:3] `PUBLIC_FLAT_RW; - reg [7:0] write_bytes_rl [3:0] `PUBLIC_FLAT_RW; - reg [7:0] write_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RW; + reg [7:0] write_bytes [0:3] `PUBLIC_FLAT_RW; + reg [7:0] write_bytes_rl [3:0] `PUBLIC_FLAT_RW; + reg [7:0] write_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RW; - reg [15:0] write_shorts [0:3] `PUBLIC_FLAT_RW; - reg [31:0] write_words [0:3] `PUBLIC_FLAT_RW; - reg [63:0] write_longs [0:3] `PUBLIC_FLAT_RW; - reg [68:0] write_customs [0:3] `PUBLIC_FLAT_RW; - reg [68:0] write_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RW; + reg [15:0] write_shorts [0:3] `PUBLIC_FLAT_RW; + reg [31:0] write_words [0:3] `PUBLIC_FLAT_RW; + reg [63:0] write_longs [0:3] `PUBLIC_FLAT_RW; + reg [68:0] write_customs [0:3] `PUBLIC_FLAT_RW; + reg [68:0] write_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RW; - integer write_integers [0:3] `PUBLIC_FLAT_RW; + integer write_integers [0:3] `PUBLIC_FLAT_RW; - reg [7:0] write_scalar `PUBLIC_FLAT_RW; - reg [7:0] write_bounds [1:3] `PUBLIC_FLAT_RW; - reg [7:0] write_inaccessible [0:3] `PUBLIC_FLAT_RD; + reg [7:0] write_scalar `PUBLIC_FLAT_RW; + reg [7:0] write_bounds [1:3] `PUBLIC_FLAT_RW; + reg [7:0] write_inaccessible [0:3] `PUBLIC_FLAT_RD; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = write_bytes[0][0] | - write_bytes[0][0] | - write_bytes_rl[0][0] | - write_bytes_nonzero_index[1][0] | - write_shorts[0][0] | - write_words[0][0] | - write_longs[0][0] | - write_customs[0][0] | - write_customs_nonzero_index_rl[1][0] | - write_integers[0][0] | - write_scalar[0] | - write_bounds[1][0] | - write_inaccessible[0][0]; + // stop icarus optimizing signals away + wire redundant = write_bytes[0][0] | + write_bytes[0][0] | + write_bytes_rl[0][0] | + write_bytes_nonzero_index[1][0] | + write_shorts[0][0] | + write_words[0][0] | + write_longs[0][0] | + write_customs[0][0] | + write_customs_nonzero_index_rl[1][0] | + write_integers[0][0] | + write_scalar[0] | + write_bounds[1][0] | + write_inaccessible[0][0]; `endif - integer status; + integer status; - initial begin + initial begin `ifdef IVERILOG - status = $mon_check; + status = $mon_check; `endif `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif - if (status != 0) begin - $write("%%Error: t_vpi_put_value_array.cpp:%0d: C Test failed\n", status); - $stop; - end + if (status != 0) begin + $write("%%Error: t_vpi_put_value_array.cpp:%0d: C Test failed\n", status); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vpi_release_dup_bad.v b/test_regress/t/t_vpi_release_dup_bad.v index 605660bd2..bb71e90b2 100644 --- a/test_regress/t/t_vpi_release_dup_bad.v +++ b/test_regress/t/t_vpi_release_dup_bad.v @@ -7,9 +7,9 @@ import "DPI-C" context function void dpii_check(); module t; - initial begin - dpii_check(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + dpii_check(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vpi_repetitive_cbs.v b/test_regress/t/t_vpi_repetitive_cbs.v index 33ca974e1..4d5aaaf73 100644 --- a/test_regress/t/t_vpi_repetitive_cbs.v +++ b/test_regress/t/t_vpi_repetitive_cbs.v @@ -5,20 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - input clk - ); +module t ( + input clk +); - reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] count /*verilator public_flat_rd */; - // Test loop - initial begin - count = 0; - end + // Test loop + initial begin + count = 0; + end - always @(posedge clk) begin - count <= count + 2; - end + always @(posedge clk) begin + count <= count + 2; + end endmodule : t diff --git a/test_regress/t/t_vpi_sc.v b/test_regress/t/t_vpi_sc.v index 2453b4841..6fb1dbc11 100644 --- a/test_regress/t/t_vpi_sc.v +++ b/test_regress/t/t_vpi_sc.v @@ -8,12 +8,12 @@ module t; - // bug1081 - We don't use VPI, just need SC with VPI + // bug1081 - We don't use VPI, just need SC with VPI - initial begin - $write("%0t: Hello\n", $time); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("%0t: Hello\n", $time); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_stop_bad.v b/test_regress/t/t_vpi_stop_bad.v index 87dfe5dd0..85a69095f 100644 --- a/test_regress/t/t_vpi_stop_bad.v +++ b/test_regress/t/t_vpi_stop_bad.v @@ -8,12 +8,12 @@ module t; - import "DPI-C" function void dpii_test(); + import "DPI-C" function void dpii_test(); - initial begin - dpii_test(); - $display("Should have stopped above"); - //$write("*-* All Finished *-*\n"); - $finish; - end + initial begin + dpii_test(); + $display("Should have stopped above"); + //$write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_vpi_time_cb.v b/test_regress/t/t_vpi_time_cb.v index e6659e5e8..c92b46234 100644 --- a/test_regress/t/t_vpi_time_cb.v +++ b/test_regress/t/t_vpi_time_cb.v @@ -9,33 +9,31 @@ import "DPI-C" function void dpii_init(); import "DPI-C" function void dpii_final(); -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] count /*verilator public_flat_rd */; - integer status; + integer status; - // Test loop - initial begin - count = 0; - dpii_init(); - end + // Test loop + initial begin + count = 0; + dpii_init(); + end - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("[%0t] clk @ count %0d", $time, count); + $display("[%0t] clk @ count %0d", $time, count); `endif - count <= count + 2; - if (count == 200) begin - $display("Final section"); - // See C++ code: $write("*-* All Finished *-*\n"); - dpii_final(); - $finish; - end - end + count <= count + 2; + if (count == 200) begin + $display("Final section"); + // See C++ code: $write("*-* All Finished *-*\n"); + dpii_final(); + $finish; + end + end endmodule : t diff --git a/test_regress/t/t_vpi_unimpl.v b/test_regress/t/t_vpi_unimpl.v index 924be11be..6e7cdd61c 100644 --- a/test_regress/t/t_vpi_unimpl.v +++ b/test_regress/t/t_vpi_unimpl.v @@ -12,10 +12,9 @@ import "DPI-C" context function int mon_check(); `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); `ifdef VERILATOR `systemc_header @@ -23,25 +22,23 @@ extern "C" int mon_check(); `verilog `endif - input clk; + reg onebit /*verilator public_flat_rw @(posedge clk) */; - reg onebit /*verilator public_flat_rw @(posedge clk) */; + integer status; - integer status; - - // Test loop - initial begin + // Test loop + initial begin `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `else - status = mon_check(); + status = mon_check(); `endif - if (status != 0) begin - $write("%%Error: t_vpi_unimpl.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if (status != 0) begin + $write("%%Error: t_vpi_unimpl.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : t diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index df522a3dc..553371661 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -13,11 +13,11 @@ import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a - ); + // Outputs + x, + // Inputs + clk, a + ); `ifdef VERILATOR `systemc_header @@ -25,197 +25,197 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - input [7:0] a; - output reg [7:0] x; + input [7:0] a; + output reg [7:0] x; - reg onebit /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; - reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/; + reg onebit /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; + reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/; - // verilator lint_off ASCRANGE - reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; - reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; + // verilator lint_on ASCRANGE - reg [31:0] count /*verilator public_flat */; - reg [31:0] half_count /*verilator public_flat_rd */ = 0; - reg [31:0] delayed /*verilator public_flat_rw */; - reg [31:0] delayed_mem [16] /*verilator public_flat_rw */; - reg [7:0] \escaped_with_brackets[3] /*verilator public_flat_rw */; - reg [7:0] mem_2d[3:0][7:0] /*verilator public_flat_rw */; // Descending indices - // verilator lint_off ASCRANGE - reg [0:95] mem_3d[0:1][1:0][0:1] /*verilator public_flat_rw */; // Mixed: asc, desc, asc - // verilator lint_on ASCRANGE + reg [31:0] count /*verilator public_flat */; + reg [31:0] half_count /*verilator public_flat_rd */ = 0; + reg [31:0] delayed /*verilator public_flat_rw */; + reg [31:0] delayed_mem [16] /*verilator public_flat_rw */; + reg [7:0] \escaped_with_brackets[3] /*verilator public_flat_rw */; + reg [7:0] mem_2d[3:0][7:0] /*verilator public_flat_rw */; // Descending indices + // verilator lint_off ASCRANGE + reg [0:95] mem_3d[0:1][1:0][0:1] /*verilator public_flat_rw */; // Mixed: asc, desc, asc + // verilator lint_on ASCRANGE - reg [3:0] [7:0] multi_packed[2:0] /*verilator public_flat_rw */; - reg unpacked_only[7:0]; + reg [3:0] [7:0] multi_packed[2:0] /*verilator public_flat_rw */; + reg unpacked_only[7:0]; - reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; - reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; - reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; - reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; - reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; - reg [2047:0] too_big /*verilator public_flat_rw @(posedge clk) */; + reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; + reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; + reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; + reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; + reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; + reg [2047:0] too_big /*verilator public_flat_rw @(posedge clk) */; - integer status; + integer status; - bit bit1 /*verilator public_flat_rw */; - integer integer1 /*verilator public_flat_rw */; - byte byte1 /*verilator public_flat_rw */; - shortint short1 /*verilator public_flat_rw */; - int int1 /*verilator public_flat_rw */; - longint long1 /*verilator public_flat_rw */; - real real1 /*verilator public_flat_rw */; - string str1 /*verilator public_flat_rw */; - // specifically public and not public_flat_rw here so as to induce the C++ - // keyword collision - localparam int nullptr /*verilator public */ = 123; + bit bit1 /*verilator public_flat_rw */; + integer integer1 /*verilator public_flat_rw */; + byte byte1 /*verilator public_flat_rw */; + shortint short1 /*verilator public_flat_rw */; + int int1 /*verilator public_flat_rw */; + longint long1 /*verilator public_flat_rw */; + real real1 /*verilator public_flat_rw */; + string str1 /*verilator public_flat_rw */; + // specifically public and not public_flat_rw here so as to induce the C++ + // keyword collision + localparam int nullptr /*verilator public */ = 123; - logic [31:0] some_mem [4] /* verilator public_flat_rd */ = {0, 0, 0, 432}; + logic [31:0] some_mem [4] /* verilator public_flat_rd */ = {0, 0, 0, 432}; - generate - for (genvar i = 0; i < 1; i++) begin : gen - wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; - end - endgenerate + generate + for (genvar i = 0; i < 1; i++) begin : gen + wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; + end + endgenerate - sub sub(); + sub sub(); - // Test loop - initial begin - count = 0; - delayed = 0; - onebit = 1'b0; - fourthreetwoone[3] = 0; // stop icarus optimizing away - text_byte = "B"; - text_half = "Hf"; - text_word = "Word"; - text_long = "Long64b"; - text = "Verilog Test module"; - too_big = "some text"; + // Test loop + initial begin + count = 0; + delayed = 0; + onebit = 1'b0; + fourthreetwoone[3] = 0; // stop icarus optimizing away + text_byte = "B"; + text_half = "Hf"; + text_word = "Word"; + text_long = "Long64b"; + text = "Verilog Test module"; + too_big = "some text"; - bit1 = 1; - integer1 = 123; - byte1 = 123; - short1 = 123; - int1 = 123; - long1 = 123; - real1 = 1.0; - str1 = "hello"; - \escaped_with_brackets[3] = 8'h5a; + bit1 = 1; + integer1 = 123; + byte1 = 123; + short1 = 123; + int1 = 123; + long1 = 123; + real1 = 1.0; + str1 = "hello"; + \escaped_with_brackets[3] = 8'h5a; - rev = 12'habc; + rev = 12'habc; - for (int i = 0; i < 4; i++) begin - for (int j = 0; j < 8; j++) begin - mem_2d[i][j] = 8'(((i * 8) + j)); - end + for (int i = 0; i < 4; i++) begin + for (int j = 0; j < 8; j++) begin + mem_2d[i][j] = 8'(((i * 8) + j)); end + end - for (int i = 0; i < 2; i++) begin - for (int j = 0; j < 2; j++) begin - for (int k = 0; k < 2; k++) begin - mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); - end - end + for (int i = 0; i < 2; i++) begin + for (int j = 0; j < 2; j++) begin + for (int k = 0; k < 2; k++) begin + mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); + end end + end - for (int i = 0; i < 3; i++) begin - for (int j = 0; j < 4; j++) begin - multi_packed[i][j] = 8'((i * 4) + j); - end + for (int i = 0; i < 3; i++) begin + for (int j = 0; j < 4; j++) begin + multi_packed[i][j] = 8'((i * 4) + j); end + end `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("%%Info: Checking results\n"); - if (onebit != 1'b1) $stop; - if (quads[2] != 62'h12819213_abd31a1c) $stop; - if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; - if (text_byte != "A") $stop; - if (text_half != "T2") $stop; - if (text_word != "Tree") $stop; - if (text_long != "44Four44") $stop; - if (text != "lorem ipsum") $stop; - if (str1 != "something a lot longer than hello") $stop; - if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; - end + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + if (onebit != 1'b1) $stop; + if (quads[2] != 62'h12819213_abd31a1c) $stop; + if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; + if (text_byte != "A") $stop; + if (text_half != "T2") $stop; + if (text_word != "Tree") $stop; + if (text_long != "44Four44") $stop; + if (text != "lorem ipsum") $stop; + if (str1 != "something a lot longer than hello") $stop; + if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; + end - always @(posedge clk) begin - count <= count + 2; - if (count[1]) - half_count <= half_count + 2; + always @(posedge clk) begin + count <= count + 2; + if (count[1]) + half_count <= half_count + 2; - if (count == 1000) begin - if (delayed != 123) $stop; - if (delayed_mem[7] != 456) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (count == 1000) begin + if (delayed != 123) $stop; + if (delayed_mem[7] != 456) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - genvar i; - generate - for (i=1; i<=6; i=i+1) begin : arr - arr #(.LENGTH(i)) arr(); - end - endgenerate + genvar i; + generate + for (i=1; i<=6; i=i+1) begin : arr + arr #(.LENGTH(i)) arr(); + end + endgenerate - genvar k; - generate - for (k=1; k<=6; k=k+1) begin : subs - sub subsub(); - end - endgenerate + genvar k; + generate + for (k=1; k<=6; k=k+1) begin : subs + sub subsub(); + end + endgenerate - arr #(.LENGTH(8)) \escaped.inst[0] (); + arr #(.LENGTH(8)) \escaped.inst[0] (); endmodule : t module sub; - reg subsig1 /*verilator public_flat_rw*/; - reg subsig2 /*verilator public_flat_rd*/; + reg subsig1 /*verilator public_flat_rw*/; + reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = subsig1 | subsig2; + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; - parameter LENGTH = 1; + parameter LENGTH = 1; - reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; - reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; - reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; + reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; + reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; + reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; - reg check /*verilator public_flat_rw*/; - reg verbose /*verilator public_flat_rw*/; + reg check /*verilator public_flat_rw*/; + reg verbose /*verilator public_flat_rw*/; - initial begin - sig = {LENGTH{1'b0}}; - rfr = {LENGTH{1'b0}}; - \escaped_sig[1] = {LENGTH{1'b0}}; - end + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + \escaped_sig[1] = {LENGTH{1'b0}}; + end - always @(posedge check) begin - if (verbose) $display("%m : %x %x", sig, rfr); - if (check && sig != rfr) $stop; - check <= 0; - end + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end endmodule : arr diff --git a/test_regress/t/t_vpi_var2.v b/test_regress/t/t_vpi_var2.v index d4dd09164..5d1d0136d 100644 --- a/test_regress/t/t_vpi_var2.v +++ b/test_regress/t/t_vpi_var2.v @@ -15,19 +15,19 @@ import "DPI-C" context function int mon_check(); module t /* verilator public_flat_on */ #( - parameter int visibleParam1 = 0, + parameter int visibleParam1 = 0, /* verilator public_off */ - parameter int invisibleParam1 = 1, + parameter int invisibleParam1 = 1, /* verilator public_on */ - parameter int visibleParam2 = 2 + parameter int visibleParam2 = 2 /* verilator public_off */ ) (/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a - ); + // Outputs + x, + // Inputs + clk, a + ); `ifdef VERILATOR `systemc_header @@ -35,206 +35,206 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - input [7:0] a /* verilator public_flat_rw */; - output reg [7:0] x /* verilator public_flat_rw */; + input [7:0] a /* verilator public_flat_rw */; + output reg [7:0] x /* verilator public_flat_rw */; /*verilator public_flat_rw_on @(posedge clk)*/ - reg onebit; - reg [2:1] twoone; - reg [2:1] fourthreetwoone[4:3]; - reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; - // verilator lint_off ASCRANGE - reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; - reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; + reg onebit; + reg [2:1] twoone; + reg [2:1] fourthreetwoone[4:3]; + reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; + // verilator lint_off ASCRANGE + reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; /*verilator public_off*/ - reg invisible1; - // verilator lint_on ASCRANGE + reg invisible1; + // verilator lint_on ASCRANGE /*verilator public_flat_on*/ - reg [31:0] count; - reg [31:0] half_count = 0; + reg [31:0] count; + reg [31:0] half_count = 0; /*verilator public_off*/ /*verilator public_flat_rw_on*/ - reg [31:0] delayed; - reg [31:0] delayed_mem [16]; - reg [7:0] \escaped_with_brackets[3] ; - reg [7:0] mem_2d[3:0][7:0]; // Descending indices - // verilator lint_off ASCRANGE - reg [0:95] mem_3d[0:1][1:0][0:1]; // Mixed: asc, desc, asc - // verilator lint_on ASCRANGE + reg [31:0] delayed; + reg [31:0] delayed_mem [16]; + reg [7:0] \escaped_with_brackets[3] ; + reg [7:0] mem_2d[3:0][7:0]; // Descending indices + // verilator lint_off ASCRANGE + reg [0:95] mem_3d[0:1][1:0][0:1]; // Mixed: asc, desc, asc + // verilator lint_on ASCRANGE - // Signal with multiple packed dimensions - reg [3:0] [7:0] multi_packed[2:0]; - reg unpacked_only[7:0]; + // Signal with multiple packed dimensions + reg [3:0] [7:0] multi_packed[2:0]; + reg unpacked_only[7:0]; /*verilator public_off*/ - reg invisible2; + reg invisible2; /*verilator public_flat_rw_on @(posedge clk)*/ - reg [7:0] text_byte; - reg [15:0] text_half; - reg [31:0] text_word; - reg [63:0] text_long; - reg [511:0] text; - reg [2047:0] too_big; + reg [7:0] text_byte; + reg [15:0] text_half; + reg [31:0] text_word; + reg [63:0] text_long; + reg [511:0] text; + reg [2047:0] too_big; /*verilator public_off*/ - integer status; + integer status; /*verilator public_flat_rw_on*/ - bit bit1; - integer integer1; - byte byte1; - shortint short1; - int int1; - longint long1; - real real1; - string str1; - localparam int nullptr = 123; - logic [31:0] some_mem [4] = {0, 0, 0, 432}; + bit bit1; + integer integer1; + byte byte1; + shortint short1; + int int1; + longint long1; + real real1; + string str1; + localparam int nullptr = 123; + logic [31:0] some_mem [4] = {0, 0, 0, 432}; /*verilator public_off*/ - generate - for (genvar i = 0; i < 1; i++) begin : gen - wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; - end - endgenerate + generate + for (genvar i = 0; i < 1; i++) begin : gen + wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; + end + endgenerate - sub sub(); + sub sub(); - // Test loop - initial begin - count = 0; - delayed = 0; - onebit = 1'b0; - fourthreetwoone[3] = 0; // stop icarus optimizing away - text_byte = "B"; - text_half = "Hf"; - text_word = "Word"; - text_long = "Long64b"; - text = "Verilog Test module"; - too_big = "some text"; + // Test loop + initial begin + count = 0; + delayed = 0; + onebit = 1'b0; + fourthreetwoone[3] = 0; // stop icarus optimizing away + text_byte = "B"; + text_half = "Hf"; + text_word = "Word"; + text_long = "Long64b"; + text = "Verilog Test module"; + too_big = "some text"; - bit1 = 1; - integer1 = 123; - byte1 = 123; - short1 = 123; - int1 = 123; - long1 = 123; - real1 = 1.0; - str1 = "hello"; - \escaped_with_brackets[3] = 8'h5a; + bit1 = 1; + integer1 = 123; + byte1 = 123; + short1 = 123; + int1 = 123; + long1 = 123; + real1 = 1.0; + str1 = "hello"; + \escaped_with_brackets[3] = 8'h5a; - rev = 12'habc; + rev = 12'habc; - for (int i = 0; i < 4; i++) begin - for (int j = 0; j < 8; j++) begin - mem_2d[i][j] = 8'(((i * 8) + j)); - end + for (int i = 0; i < 4; i++) begin + for (int j = 0; j < 8; j++) begin + mem_2d[i][j] = 8'(((i * 8) + j)); end + end - for (int i = 0; i < 2; i++) begin - for (int j = 0; j < 2; j++) begin - for (int k = 0; k < 2; k++) begin - mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); - end - end + for (int i = 0; i < 2; i++) begin + for (int j = 0; j < 2; j++) begin + for (int k = 0; k < 2; k++) begin + mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); + end end + end - for (int i = 0; i < 3; i++) begin - for (int j = 0; j < 4; j++) begin - multi_packed[i][j] = 8'((i * 4) + j); - end + for (int i = 0; i < 3; i++) begin + for (int j = 0; j < 4; j++) begin + multi_packed[i][j] = 8'((i * 4) + j); end + end `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("%%Info: Checking results\n"); - if (onebit != 1'b1) $stop; - if (quads[2] != 62'h12819213_abd31a1c) $stop; - if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; - if (text_byte != "A") $stop; - if (text_half != "T2") $stop; - if (text_word != "Tree") $stop; - if (text_long != "44Four44") $stop; - if (text != "lorem ipsum") $stop; - if (str1 != "something a lot longer than hello") $stop; - if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; - end + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + if (onebit != 1'b1) $stop; + if (quads[2] != 62'h12819213_abd31a1c) $stop; + if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; + if (text_byte != "A") $stop; + if (text_half != "T2") $stop; + if (text_word != "Tree") $stop; + if (text_long != "44Four44") $stop; + if (text != "lorem ipsum") $stop; + if (str1 != "something a lot longer than hello") $stop; + if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; + end - always @(posedge clk) begin - count <= count + 2; - if (count[1]) - half_count <= half_count + 2; + always @(posedge clk) begin + count <= count + 2; + if (count[1]) + half_count <= half_count + 2; - if (count == 1000) begin - if (delayed != 123) $stop; - if (delayed_mem[7] != 456) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (count == 1000) begin + if (delayed != 123) $stop; + if (delayed_mem[7] != 456) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - genvar i; - generate - for (i=1; i<=6; i=i+1) begin : arr - arr #(.LENGTH(i)) arr(); - end - endgenerate + genvar i; + generate + for (i=1; i<=6; i=i+1) begin : arr + arr #(.LENGTH(i)) arr(); + end + endgenerate - genvar k; - generate - for (k=1; k<=6; k=k+1) begin : subs - sub subsub(); - end - endgenerate + genvar k; + generate + for (k=1; k<=6; k=k+1) begin : subs + sub subsub(); + end + endgenerate - arr #(.LENGTH(8)) \escaped.inst[0] (); + arr #(.LENGTH(8)) \escaped.inst[0] (); endmodule : t module sub; - reg subsig1 /*verilator public_flat_rw*/; - reg subsig2 /*verilator public_flat_rd*/; + reg subsig1 /*verilator public_flat_rw*/; + reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = subsig1 | subsig2; + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; - parameter LENGTH = 1; + parameter LENGTH = 1; /*verilator public_flat_rw_on*/ - reg [LENGTH-1:0] sig; - reg [LENGTH-1:0] rfr; - reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; + reg [LENGTH-1:0] sig; + reg [LENGTH-1:0] rfr; + reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; - reg check; - reg verbose; + reg check; + reg verbose; /*verilator public_off*/ - initial begin - sig = {LENGTH{1'b0}}; - rfr = {LENGTH{1'b0}}; - end + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + end - always @(posedge check) begin - if (verbose) $display("%m : %x %x", sig, rfr); - if (check && sig != rfr) $stop; - check <= 0; - end + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end endmodule : arr diff --git a/test_regress/t/t_vpi_var3.v b/test_regress/t/t_vpi_var3.v index 34434ee40..930c6c14e 100644 --- a/test_regress/t/t_vpi_var3.v +++ b/test_regress/t/t_vpi_var3.v @@ -13,11 +13,11 @@ import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ - // Outputs - x, - // Inputs - clk, a - ); + // Outputs + x, + // Inputs + clk, a + ); `ifdef VERILATOR `systemc_header @@ -25,194 +25,194 @@ extern "C" int mon_check(); `verilog `endif - input clk; + input clk; - input [7:0] a; - output reg [7:0] x; + input [7:0] a; + output reg [7:0] x; - reg onebit; - reg [2:1] twoone; - reg [2:1] fourthreetwoone[4:3]; - reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; + reg onebit; + reg [2:1] twoone; + reg [2:1] fourthreetwoone[4:3]; + reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; - // verilator lint_off ASCRANGE - reg [0:61] quads[2:3]; - reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + reg [0:61] quads[2:3]; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; + // verilator lint_on ASCRANGE - reg [31:0] count; - reg [31:0] half_count; - reg [31:0] delayed; - reg [31:0] delayed_mem [16]; - reg [7:0] \escaped_with_brackets[3] ; - reg [7:0] mem_2d[3:0][7:0]; // Descending indices - // verilator lint_off ASCRANGE - reg [0:95] mem_3d[0:1][1:0][0:1]; // Mixed: asc, desc, asc - // verilator lint_on ASCRANGE + reg [31:0] count; + reg [31:0] half_count; + reg [31:0] delayed; + reg [31:0] delayed_mem [16]; + reg [7:0] \escaped_with_brackets[3] ; + reg [7:0] mem_2d[3:0][7:0]; // Descending indices + // verilator lint_off ASCRANGE + reg [0:95] mem_3d[0:1][1:0][0:1]; // Mixed: asc, desc, asc + // verilator lint_on ASCRANGE - // Signal with multiple packed dimensions - reg [3:0] [7:0] multi_packed[2:0]; - reg unpacked_only[7:0]; + // Signal with multiple packed dimensions + reg [3:0] [7:0] multi_packed[2:0]; + reg unpacked_only[7:0]; - reg [7:0] text_byte; - reg [15:0] text_half; - reg [31:0] text_word; - reg [63:0] text_long; - reg [511:0] text; - reg [2047:0] too_big; + reg [7:0] text_byte; + reg [15:0] text_half; + reg [31:0] text_word; + reg [63:0] text_long; + reg [511:0] text; + reg [2047:0] too_big; - integer status; + integer status; - bit bit1; - integer integer1; - byte byte1; - shortint short1; - int int1; - longint long1; - real real1; - string str1; - localparam int nullptr = 123; - logic [31:0] some_mem [4] = {0, 0, 0, 432}; + bit bit1; + integer integer1; + byte byte1; + shortint short1; + int int1; + longint long1; + real real1; + string str1; + localparam int nullptr = 123; + logic [31:0] some_mem [4] = {0, 0, 0, 432}; - generate - for (genvar i = 0; i < 1; i++) begin : gen - wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; - end - endgenerate + generate + for (genvar i = 0; i < 1; i++) begin : gen + wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB; + end + endgenerate - sub sub(); + sub sub(); - // Test loop - initial begin - count = 0; - delayed = 0; - onebit = 1'b0; - fourthreetwoone[3] = 0; // stop icarus optimizing away - text_byte = "B"; - text_half = "Hf"; - text_word = "Word"; - text_long = "Long64b"; - text = "Verilog Test module"; - too_big = "some text"; + // Test loop + initial begin + count = 0; + delayed = 0; + onebit = 1'b0; + fourthreetwoone[3] = 0; // stop icarus optimizing away + text_byte = "B"; + text_half = "Hf"; + text_word = "Word"; + text_long = "Long64b"; + text = "Verilog Test module"; + too_big = "some text"; - bit1 = 1; - integer1 = 123; - byte1 = 123; - short1 = 123; - int1 = 123; - long1 = 123; - real1 = 1.0; - str1 = "hello"; - \escaped_with_brackets[3] = 8'h5a; + bit1 = 1; + integer1 = 123; + byte1 = 123; + short1 = 123; + int1 = 123; + long1 = 123; + real1 = 1.0; + str1 = "hello"; + \escaped_with_brackets[3] = 8'h5a; - rev = 12'habc; + rev = 12'habc; - for (int i = 0; i < 4; i++) begin - for (int j = 0; j < 8; j++) begin - mem_2d[i][j] = 8'(((i * 8) + j)); - end + for (int i = 0; i < 4; i++) begin + for (int j = 0; j < 8; j++) begin + mem_2d[i][j] = 8'(((i * 8) + j)); end + end - for (int i = 0; i < 2; i++) begin - for (int j = 0; j < 2; j++) begin - for (int k = 0; k < 2; k++) begin - mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); - end - end + for (int i = 0; i < 2; i++) begin + for (int j = 0; j < 2; j++) begin + for (int k = 0; k < 2; k++) begin + mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k)); + end end + end - for (int i = 0; i < 3; i++) begin - for (int j = 0; j < 4; j++) begin - multi_packed[i][j] = 8'((i * 4) + j); - end + for (int i = 0; i < 3; i++) begin + for (int j = 0; j < 4; j++) begin + multi_packed[i][j] = 8'((i * 4) + j); end + end `ifdef VERILATOR - status = $c32("mon_check()"); + status = $c32("mon_check()"); `endif `ifdef IVERILOG - status = $mon_check(); + status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI - status = mon_check(); + status = mon_check(); `endif - if (status!=0) begin - $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); - $stop; - end - $write("%%Info: Checking results\n"); - if (onebit != 1'b1) $stop; - if (quads[2] != 62'h12819213_abd31a1c) $stop; - if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; - if (text_byte != "A") $stop; - if (text_half != "T2") $stop; - if (text_word != "Tree") $stop; - if (text_long != "44Four44") $stop; - if (text != "lorem ipsum") $stop; - if (str1 != "something a lot longer than hello") $stop; - if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; - end + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + if (onebit != 1'b1) $stop; + if (quads[2] != 62'h12819213_abd31a1c) $stop; + if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; + if (text_byte != "A") $stop; + if (text_half != "T2") $stop; + if (text_word != "Tree") $stop; + if (text_long != "44Four44") $stop; + if (text != "lorem ipsum") $stop; + if (str1 != "something a lot longer than hello") $stop; + if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; + end - always @(posedge clk) begin - count <= count + 2; - if (count[1]) - half_count <= half_count + 2; + always @(posedge clk) begin + count <= count + 2; + if (count[1]) + half_count <= half_count + 2; - if (count == 1000) begin - if (delayed != 123) $stop; - if (delayed_mem[7] != 456) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (count == 1000) begin + if (delayed != 123) $stop; + if (delayed_mem[7] != 456) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - genvar i; - generate - for (i=1; i<=6; i=i+1) begin : arr - arr #(.LENGTH(i)) arr(); - end - endgenerate + genvar i; + generate + for (i=1; i<=6; i=i+1) begin : arr + arr #(.LENGTH(i)) arr(); + end + endgenerate - genvar k; - generate - for (k=1; k<=6; k=k+1) begin : subs - sub subsub(); - end - endgenerate + genvar k; + generate + for (k=1; k<=6; k=k+1) begin : subs + sub subsub(); + end + endgenerate - arr #(.LENGTH(8)) \escaped.inst[0] (); + arr #(.LENGTH(8)) \escaped.inst[0] (); endmodule : t module sub; - reg subsig1; - reg subsig2; + reg subsig1; + reg subsig2; `ifdef IVERILOG - // stop icarus optimizing signals away - wire redundant = subsig1 | subsig2; + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; - parameter LENGTH = 1; + parameter LENGTH = 1; - reg [LENGTH-1:0] sig; - reg [LENGTH-1:0] rfr; - reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; + reg [LENGTH-1:0] sig; + reg [LENGTH-1:0] rfr; + reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/; - reg check; - reg verbose; + reg check; + reg verbose; - initial begin - sig = {LENGTH{1'b0}}; - rfr = {LENGTH{1'b0}}; - end + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + end - always @(posedge check) begin - if (verbose) $display("%m : %x %x", sig, rfr); - if (check && sig != rfr) $stop; - check <= 0; - end + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end endmodule : arr diff --git a/test_regress/t/t_vpi_zero_time_cb.v b/test_regress/t/t_vpi_zero_time_cb.v index 153e29b61..3ca57ab91 100644 --- a/test_regress/t/t_vpi_zero_time_cb.v +++ b/test_regress/t/t_vpi_zero_time_cb.v @@ -6,30 +6,28 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] count /*verilator public_flat_rd */; - integer status; + integer status; - // Test loop - initial begin - count = 0; - end + // Test loop + initial begin + count = 0; + end - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("[%0t] clk", $time); + $display("[%0t] clk", $time); `endif - count <= count + 2; - if (count == 1000) begin - // See C++ code: $write("*-* All Finished *-*\n"); - $finish; - end - end + count <= count + 2; + if (count == 1000) begin + // See C++ code: $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule : t