Make refs illegal inside static tasks
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
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@ -304,6 +304,9 @@ class BeginVisitor final : public VNVisitor {
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const std::string newName
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= m_ftaskp->name() + "__Vstatic__" + dot(m_unnamedScope, nodep->name());
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if (nodep->isIO()) {
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if (nodep->direction().isRef()) {
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nodep->v3error("It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)");
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}
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// Create a port that is used for passing value between argument and static
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// variable
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AstVar* const portp = nodep->cloneTreePure(false);
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@ -0,0 +1,6 @@
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%Error: t/t_fork_write_after_timing_bad.v:12:19: It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)
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: ... note: In instance 't'
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12 | task t1(ref int x);
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2024 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,17 @@
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int x1;
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initial begin
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t1(x1);
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$finish;
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end
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task t1(ref int x);
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fork
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x = #1 2;
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join_none
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endtask
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endmodule
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