Make refs illegal inside static tasks

Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
This commit is contained in:
Kamil Danecki 2026-03-31 12:21:45 +02:00
parent fbf110cd06
commit 1e581ba5fa
4 changed files with 42 additions and 0 deletions

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@ -304,6 +304,9 @@ class BeginVisitor final : public VNVisitor {
const std::string newName
= m_ftaskp->name() + "__Vstatic__" + dot(m_unnamedScope, nodep->name());
if (nodep->isIO()) {
if (nodep->direction().isRef()) {
nodep->v3error("It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)");
}
// Create a port that is used for passing value between argument and static
// variable
AstVar* const portp = nodep->cloneTreePure(false);

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@ -0,0 +1,6 @@
%Error: t/t_fork_write_after_timing_bad.v:12:19: It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)
: ... note: In instance 't'
12 | task t1(ref int x);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename)
test.passes()

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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t;
int x1;
initial begin
t1(x1);
$finish;
end
task t1(ref int x);
fork
x = #1 2;
join_none
endtask
endmodule