From 1e581ba5fa16f207f376acd7cb26da92b9cd6dbe Mon Sep 17 00:00:00 2001
From: Kamil Danecki <kdanecki@internships.antmicro.com>
Date: Tue, 31 Mar 2026 12:21:45 +0200
Subject: [PATCH] Make refs illegal inside static tasks

Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
---
 src/V3Begin.cpp                                 |  3 +++
 .../t/t_fork_write_after_timing_bad.out         |  6 ++++++
 test_regress/t/t_fork_write_after_timing_bad.py | 16 ++++++++++++++++
 test_regress/t/t_fork_write_after_timing_bad.v  | 17 +++++++++++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 test_regress/t/t_fork_write_after_timing_bad.out
 create mode 100755 test_regress/t/t_fork_write_after_timing_bad.py
 create mode 100644 test_regress/t/t_fork_write_after_timing_bad.v

diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index fa339c062..d296bb70f 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -304,6 +304,9 @@ class BeginVisitor final : public VNVisitor {
             const std::string newName
                 = m_ftaskp->name() + "__Vstatic__" + dot(m_unnamedScope, nodep->name());
             if (nodep->isIO()) {
+                if (nodep->direction().isRef()) {
+                    nodep->v3error("It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)");
+                }
                 // Create a port that is used for passing value between argument and static
                 // variable
                 AstVar* const portp = nodep->cloneTreePure(false);
diff --git a/test_regress/t/t_fork_write_after_timing_bad.out b/test_regress/t/t_fork_write_after_timing_bad.out
new file mode 100644
index 000000000..99c600148
--- /dev/null
+++ b/test_regress/t/t_fork_write_after_timing_bad.out
@@ -0,0 +1,6 @@
+%Error: t/t_fork_write_after_timing_bad.v:12:19: It is illegal to use argument passing by reference for subroutines with a lifetime of static (IEEE 1800-2023 13.5.2)
+                                               : ... note: In instance 't'
+   12 |   task t1(ref int x);
+      |                   ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_fork_write_after_timing_bad.py b/test_regress/t/t_fork_write_after_timing_bad.py
new file mode 100755
index 000000000..d77726df8
--- /dev/null
+++ b/test_regress/t/t_fork_write_after_timing_bad.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_fork_write_after_timing_bad.v b/test_regress/t/t_fork_write_after_timing_bad.v
new file mode 100644
index 000000000..27c133140
--- /dev/null
+++ b/test_regress/t/t_fork_write_after_timing_bad.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int x1;
+  initial begin
+    t1(x1);
+    $finish;
+  end
+  task t1(ref int x);
+    fork
+      x = #1 2;
+    join_none
+  endtask
+endmodule