Add `--quiet-build` to suppress make/compiler informationals.
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@ -24,9 +24,10 @@ Verilator 5.043 devel
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* Add `-param`/`-port` options to `public_flat*` control directives (#6685). [Geza Lore, Fractile Ltd.]
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* Add `--top` specifying `config` name (#6710). [Dan Ruelas-Petrisko]
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* Add `sc_biguint` pragma (#6712). [Jakub Wasilewski, Antmicro Ltd.]
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* Add 'make venv' target (#6775). [Geza Lore]
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* Add `make venv` target (#6775). [Geza Lore]
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* Add SUPERNFIRST error on super.new on non-first statement (#6784). [Artur Bieniek]
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* Add fargs for reusability of `--dump-inputs` output (#6812). [Geza Lore]
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* Add `--quiet-build` to suppress make/compiler informationals.
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* Support `std::randomize(){...}` (#4706) (#6573). [Yilou Wang]
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* Support force assignments to unpacked array elements (partial #4735) (#6787). [Ryszard Rozak, Antmicro Ltd.]
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* Support `config' (#5891) (#6714) (#6717) (#6745) (#6764). [Dan Ruelas-Petrisko]
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@ -476,6 +476,7 @@ detailed descriptions of these arguments.
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--public-params Mark all parameters as public_flat
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-pvalue+<name>=<value> Overwrite toplevel parameter
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--quiet Minimize additional printing
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--quiet-build Don't print build progress
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--quiet-exit Don't print the command on failure
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--quiet-stats Don't print statistics
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--relative-includes Resolve includes relative to current file
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@ -1475,7 +1475,13 @@ Summary:
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.. option:: --quiet
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Alias for :vlopt:`--quiet-exit` :vlopt:`--quiet-stats`.
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Alias for :vlopt:`--quiet-build` :vlopt:`--quiet-exit`
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:vlopt:`--quiet-stats`.
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.. option:: --quiet-build
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Disable printing build progress such as compiler command lines, when
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using :vlopt:`--build`.
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.. option:: --quiet-exit
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@ -1690,9 +1690,11 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
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[this](const char* varp) { addParameter(varp, false); });
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DECL_OPTION("-quiet", CbOnOff, [this](bool flag) {
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m_quietBuild = flag;
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m_quietExit = flag;
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m_quietStats = flag;
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});
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DECL_OPTION("-quiet-build", OnOff, &m_quietBuild);
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DECL_OPTION("-quiet-exit", OnOff, &m_quietExit);
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DECL_OPTION("-quiet-stats", OnOff, &m_quietStats);
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@ -279,6 +279,7 @@ private:
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bool m_publicFlatRW = false; // main switch: --public-flat-rw
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bool m_publicIgnore = false; // main switch: --public-ignore
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bool m_publicParams = false; // main switch: --public-params
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bool m_quietBuild = false; // main switch: --quiet-build
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bool m_quietExit = false; // main switch: --quiet-exit
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bool m_quietStats = false; // main switch: --quiet-stats
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bool m_relativeIncludes = false; // main switch: --relative-includes
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@ -578,6 +579,7 @@ public:
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bool anyPublicFlat() const { return m_publicParams || m_publicFlatRW || m_publicDepth; }
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bool lintOnly() const VL_MT_SAFE { return m_lintOnly; }
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bool ignc() const { return m_ignc; }
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bool quietBuild() const VL_MT_SAFE { return m_quietBuild; }
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bool quietExit() const VL_MT_SAFE { return m_quietExit; }
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bool quietStats() const VL_MT_SAFE { return m_quietStats; }
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bool reportUnoptflat() const { return m_reportUnoptflat; }
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@ -818,6 +818,7 @@ static string buildMakeCmd(const string& makefile, const string& target) {
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cmd << " -C " << v3Global.opt.makeDir();
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cmd << " -f " << makefile;
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// Unless using make's jobserver, do a -j
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if (v3Global.opt.quietBuild()) cmd << " -s --no-print-directory";
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if (v3Global.opt.getenvMAKEFLAGS().find("-jobserver-auth") == string::npos) {
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if (jobs > 0) cmd << " -j " << jobs;
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}
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@ -841,7 +842,7 @@ static void execBuildJob() {
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V3Stats::addStatPerf(V3Stats::STAT_WALLTIME_BUILD, buildWallTime.deltaTime());
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if (exit_code != 0) {
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v3error(cmdStr << " exited with " << exit_code << std::endl);
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v3error("'" << cmdStr << "' exited with " << exit_code << std::endl);
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v3Global.vlExit(exit_code);
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}
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}
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile(verilator_flags2=["--binary", "--quiet-build"])
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test.file_grep_not(test.compile_log_filename, r'ccache')
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test.file_grep_not(test.compile_log_filename, r'make:')
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test.file_grep_not(test.compile_log_filename, r'/include')
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test.passes()
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@ -0,0 +1,9 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial $finish;
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endmodule
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