From 1b93033690ca3c2bd70e3683add3e0254ffdc244 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 23 Dec 2025 19:21:42 -0500 Subject: [PATCH] Add `--quiet-build` to suppress make/compiler informationals. --- Changes | 3 ++- bin/verilator | 1 + docs/guide/exe_verilator.rst | 8 +++++++- src/V3Options.cpp | 2 ++ src/V3Options.h | 2 ++ src/Verilator.cpp | 3 ++- test_regress/t/t_flag_quiet_build.py | 20 ++++++++++++++++++++ test_regress/t/t_flag_quiet_build.v | 9 +++++++++ 8 files changed, 45 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_flag_quiet_build.py create mode 100644 test_regress/t/t_flag_quiet_build.v diff --git a/Changes b/Changes index 7fe4b1ca5..273c0537f 100644 --- a/Changes +++ b/Changes @@ -24,9 +24,10 @@ Verilator 5.043 devel * Add `-param`/`-port` options to `public_flat*` control directives (#6685). [Geza Lore, Fractile Ltd.] * Add `--top` specifying `config` name (#6710). [Dan Ruelas-Petrisko] * Add `sc_biguint` pragma (#6712). [Jakub Wasilewski, Antmicro Ltd.] -* Add 'make venv' target (#6775). [Geza Lore] +* Add `make venv` target (#6775). [Geza Lore] * Add SUPERNFIRST error on super.new on non-first statement (#6784). [Artur Bieniek] * Add fargs for reusability of `--dump-inputs` output (#6812). [Geza Lore] +* Add `--quiet-build` to suppress make/compiler informationals. * Support `std::randomize(){...}` (#4706) (#6573). [Yilou Wang] * Support force assignments to unpacked array elements (partial #4735) (#6787). [Ryszard Rozak, Antmicro Ltd.] * Support `config' (#5891) (#6714) (#6717) (#6745) (#6764). [Dan Ruelas-Petrisko] diff --git a/bin/verilator b/bin/verilator index 730148ed8..721356ea1 100755 --- a/bin/verilator +++ b/bin/verilator @@ -476,6 +476,7 @@ detailed descriptions of these arguments. --public-params Mark all parameters as public_flat -pvalue+= Overwrite toplevel parameter --quiet Minimize additional printing + --quiet-build Don't print build progress --quiet-exit Don't print the command on failure --quiet-stats Don't print statistics --relative-includes Resolve includes relative to current file diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 1c08323dc..19cb17896 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1475,7 +1475,13 @@ Summary: .. option:: --quiet - Alias for :vlopt:`--quiet-exit` :vlopt:`--quiet-stats`. + Alias for :vlopt:`--quiet-build` :vlopt:`--quiet-exit` + :vlopt:`--quiet-stats`. + +.. option:: --quiet-build + + Disable printing build progress such as compiler command lines, when + using :vlopt:`--build`. .. option:: --quiet-exit diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 9e775a96d..5e3558321 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1690,9 +1690,11 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, [this](const char* varp) { addParameter(varp, false); }); DECL_OPTION("-quiet", CbOnOff, [this](bool flag) { + m_quietBuild = flag; m_quietExit = flag; m_quietStats = flag; }); + DECL_OPTION("-quiet-build", OnOff, &m_quietBuild); DECL_OPTION("-quiet-exit", OnOff, &m_quietExit); DECL_OPTION("-quiet-stats", OnOff, &m_quietStats); diff --git a/src/V3Options.h b/src/V3Options.h index 13ebcf726..0c2960383 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -279,6 +279,7 @@ private: bool m_publicFlatRW = false; // main switch: --public-flat-rw bool m_publicIgnore = false; // main switch: --public-ignore bool m_publicParams = false; // main switch: --public-params + bool m_quietBuild = false; // main switch: --quiet-build bool m_quietExit = false; // main switch: --quiet-exit bool m_quietStats = false; // main switch: --quiet-stats bool m_relativeIncludes = false; // main switch: --relative-includes @@ -578,6 +579,7 @@ public: bool anyPublicFlat() const { return m_publicParams || m_publicFlatRW || m_publicDepth; } bool lintOnly() const VL_MT_SAFE { return m_lintOnly; } bool ignc() const { return m_ignc; } + bool quietBuild() const VL_MT_SAFE { return m_quietBuild; } bool quietExit() const VL_MT_SAFE { return m_quietExit; } bool quietStats() const VL_MT_SAFE { return m_quietStats; } bool reportUnoptflat() const { return m_reportUnoptflat; } diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 38229cdef..1a559bba4 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -818,6 +818,7 @@ static string buildMakeCmd(const string& makefile, const string& target) { cmd << " -C " << v3Global.opt.makeDir(); cmd << " -f " << makefile; // Unless using make's jobserver, do a -j + if (v3Global.opt.quietBuild()) cmd << " -s --no-print-directory"; if (v3Global.opt.getenvMAKEFLAGS().find("-jobserver-auth") == string::npos) { if (jobs > 0) cmd << " -j " << jobs; } @@ -841,7 +842,7 @@ static void execBuildJob() { V3Stats::addStatPerf(V3Stats::STAT_WALLTIME_BUILD, buildWallTime.deltaTime()); if (exit_code != 0) { - v3error(cmdStr << " exited with " << exit_code << std::endl); + v3error("'" << cmdStr << "' exited with " << exit_code << std::endl); v3Global.vlExit(exit_code); } } diff --git a/test_regress/t/t_flag_quiet_build.py b/test_regress/t/t_flag_quiet_build.py new file mode 100755 index 000000000..558747e45 --- /dev/null +++ b/test_regress/t/t_flag_quiet_build.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary", "--quiet-build"]) + +test.file_grep_not(test.compile_log_filename, r'ccache') +test.file_grep_not(test.compile_log_filename, r'make:') +test.file_grep_not(test.compile_log_filename, r'/include') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_build.v b/test_regress/t/t_flag_quiet_build.v new file mode 100644 index 000000000..fbcbd7ce9 --- /dev/null +++ b/test_regress/t/t_flag_quiet_build.v @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial $finish; +endmodule