luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix large array initialization (#6669)

This commit is contained in:
Artur Bieniek 2025-11-10 15:19:08 +01:00 committed by GitHub
parent 6e05361318
commit 19bbeb24a6
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/V3Slice.cpp
View File

@ -254,6 +254,7 @@ class SliceVisitor final : public VNVisitor {
const int elementLimit = v3Global.opt.fSliceElementLimit(); const int elementLimit = v3Global.opt.fSliceElementLimit();
if (elements > elementLimit && elementLimit > 0) { if (elements > elementLimit && elementLimit > 0) {
++m_statSliceElementSkips; ++m_statSliceElementSkips;
m_okInitArray = true; // VL_RESTORER in visit(AstNodeAssign)
return false; return false;
} }

4
test_regress/t/t_mem.v
View File

@ -12,6 +12,9 @@ module t (/*AUTOARG*/
input clk; input clk;
integer cyc; initial cyc=1; integer cyc; initial cyc=1;
logic hugemem [257];
initial hugemem = '{default:1'b0};
// [16] is SV syntax for [0:15] // [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16]; reg [7:0] memory8_16 [16];
@ -41,6 +44,7 @@ module t (/*AUTOARG*/
if (cyc!=0) begin if (cyc!=0) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc==1) begin if (cyc==1) begin
$display(hugemem);
m_we <= 1'b1; m_we <= 1'b1;
m_addr <= 3'd2; m_addr <= 3'd2;
m_data <= 16'h55_44; m_data <= 16'h55_44;