From 19bbeb24a6ec0ba2f09aa9822a970ef01821c16d Mon Sep 17 00:00:00 2001
From: Artur Bieniek <abieniek@internships.antmicro.com>
Date: Mon, 10 Nov 2025 15:19:08 +0100
Subject: [PATCH] Fix large array initialization (#6669)

---
 src/V3Slice.cpp        | 1 +
 test_regress/t/t_mem.v | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 37ac8ae98..5c0aac526 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -254,6 +254,7 @@ class SliceVisitor final : public VNVisitor {
         const int elementLimit = v3Global.opt.fSliceElementLimit();
         if (elements > elementLimit && elementLimit > 0) {
             ++m_statSliceElementSkips;
+            m_okInitArray = true;  // VL_RESTORER in visit(AstNodeAssign)
             return false;
         }
 
diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v
index ea9d7dfce..5baa226a0 100644
--- a/test_regress/t/t_mem.v
+++ b/test_regress/t/t_mem.v
@@ -12,6 +12,9 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
+   logic hugemem [257];
+   initial hugemem = '{default:1'b0};
+
    // [16] is SV syntax for [0:15]
    reg [7:0] memory8_16 [16];
 
@@ -41,6 +44,7 @@ module t (/*AUTOARG*/
       if (cyc!=0) begin
          cyc <= cyc + 1;
          if (cyc==1) begin
+            $display(hugemem);
             m_we <= 1'b1;
             m_addr <= 3'd2;
             m_data <= 16'h55_44;