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remove timescale arg, update .v, 5ns -> 5

This commit is contained in:
Yilou Wang 2026-03-30 14:47:44 +02:00
parent ebbc54409c
commit 190d64c3cf
2 changed files with 2 additions and 2 deletions
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2
test_regress/t/t_wait_iface_vif.py
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@ -11,7 +11,7 @@ import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--binary', '--timescale 1ns/1ps'])
test.compile(verilator_flags2=['--binary'])
test.execute()

2
test_regress/t/t_wait_iface_vif.v
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@ -45,7 +45,7 @@ class Driver;
virtual my_if vif;
task run();
vif.set_period(5ns);
vif.set_period(5);
#10;
vif.start_clk();
endtask