From 190d64c3cf88552dbeba390e462a83e068c526e0 Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Mon, 30 Mar 2026 14:47:44 +0200 Subject: [PATCH] remove timescale arg, update .v, 5ns -> 5 --- test_regress/t/t_wait_iface_vif.py | 2 +- test_regress/t/t_wait_iface_vif.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/test_regress/t/t_wait_iface_vif.py b/test_regress/t/t_wait_iface_vif.py index 3f6cb54fd..46d1fe4c0 100755 --- a/test_regress/t/t_wait_iface_vif.py +++ b/test_regress/t/t_wait_iface_vif.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--binary', '--timescale 1ns/1ps']) +test.compile(verilator_flags2=['--binary']) test.execute() diff --git a/test_regress/t/t_wait_iface_vif.v b/test_regress/t/t_wait_iface_vif.v index a91fc8445..7d697e8fe 100644 --- a/test_regress/t/t_wait_iface_vif.v +++ b/test_regress/t/t_wait_iface_vif.v @@ -45,7 +45,7 @@ class Driver; virtual my_if vif; task run(); - vif.set_period(5ns); + vif.set_period(5); #10; vif.start_clk(); endtask