From 1856cad816e47ad75d0d82657b0b0948fda59076 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 17 Jan 2013 23:21:07 -0500 Subject: [PATCH] Maintain little endian indication for multidimensional arrays --- src/V3Width.cpp | 13 +++---------- test_regress/t/t_func_lib_sub.v | 2 +- test_regress/t/t_lint_blksync_loop.v | 2 +- test_regress/t/t_mem_fifo.v | 2 ++ test_regress/t/t_mem_first.v | 2 ++ test_regress/t/t_mem_multidim.v | 2 ++ test_regress/t/t_mem_multiwire.v | 2 ++ test_regress/t/t_mem_slot.v | 2 +- test_regress/t/t_param_repl.v | 2 ++ test_regress/t/t_sys_readmem.v | 2 ++ test_regress/t/t_sys_readmem_bad_addr.v | 2 +- test_regress/t/t_sys_readmem_bad_digit.v | 2 +- test_regress/t/t_sys_readmem_bad_end.v | 2 +- test_regress/t/t_sys_readmem_bad_notfound.v | 2 +- 14 files changed, 22 insertions(+), 17 deletions(-) diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 6f1c2c5ff..890539afd 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -370,16 +370,9 @@ private: int msb = nodep->msbConst(); int lsb = nodep->lsbConst(); if (msbbackp()->castRange()) huntbackp=huntbackp->backp(); - if (huntbackp->backp()->castNodeArrayDType()) { - } else { - // Little endian bits are legal, just remember to swap - // Warning is in V3Width to avoid false warnings when in "off" generate if's - nodep->littleEndian(!nodep->littleEndian()); - } + // Little endian bits are legal, just remember to swap + // Warning is in V3Width to avoid false warnings when in "off" generate if's + nodep->littleEndian(!nodep->littleEndian()); // Internally we'll always have msb() be the greater number // We only need to correct when doing [] AstSel extraction, // and when tracing the vector. diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index 8804a94f5..fcc8cc766 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -17,7 +17,7 @@ reg covfok; reg [15:0] xwieqw; reg [2:0] ofnjjt; -reg [37:0] hdsejo[0:1]; +reg [37:0] hdsejo[1:0]; reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; reg vrqrih, ryyjxy; diff --git a/test_regress/t/t_lint_blksync_loop.v b/test_regress/t/t_lint_blksync_loop.v index 15826e414..c7977a2bc 100644 --- a/test_regress/t/t_lint_blksync_loop.v +++ b/test_regress/t/t_lint_blksync_loop.v @@ -65,7 +65,7 @@ module reg_1r1w output [WIDTH-1:0] data_out; - reg [WIDTH-1:0] array [0:DEPTH-1]; + reg [WIDTH-1:0] array [DEPTH-1:0]; reg [ADRWID-1:0] ra_r, wa_r; reg [WIDTH-1:0] data_in_r; reg wr_r; diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index df378260d..12beb0664 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -88,7 +88,9 @@ module fifo (/*AUTOARG*/ reg [65:0] outData; // verilator lint_off VARHIDDEN + // verilator lint_off LITENDIAN reg [65:0] fifo[0:fifoDepth-1]; + // verilator lint_on LITENDIAN // verilator lint_on VARHIDDEN //reg [65:0] temp; diff --git a/test_regress/t/t_mem_first.v b/test_regress/t/t_mem_first.v index de95f7f1c..7c4ec342d 100644 --- a/test_regress/t/t_mem_first.v +++ b/test_regress/t/t_mem_first.v @@ -11,11 +11,13 @@ module t (/*AUTOARG*/ input clk; integer _mode; initial _mode = 0; + // verilator lint_off LITENDIAN reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [34:0] vec_wide; + // verilator lint_on LITENDIAN reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index daa8fc856..4cdbf8003 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -10,6 +10,7 @@ module t (/*AUTOARG*/ input clk; + // verilator lint_off LITENDIAN // verilator lint_off BLKANDNBLK // 3 3 4 reg [71:0] memw [2:0][1:3][5:2]; @@ -27,6 +28,7 @@ module t (/*AUTOARG*/ integer imem[2:0][1:3]; reg [2:0] cstyle[2]; + // verilator lint_on LITENDIAN initial begin for (i0=0; i0<3; i0=i0+1) begin diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index c9cfcb90a..89b36608d 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -10,7 +10,9 @@ module t (/*AUTOARG*/ input clk; + // verilator lint_off LITENDIAN wire [7:0] array [2:0][1:3]; + // verilator lint_on LITENDIAN integer cyc; initial cyc=0; integer i0,i1,i2; diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index 94a6db4bb..8fcf5ed18 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -14,7 +14,7 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); input [1:0] SlotToReturn; output [1:0] OutputVal; - reg [1:0] Array[0:2]; + reg [1:0] Array[2:0]; always @(posedge Clk) begin diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 4e71b3127..2043bceff 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -20,7 +20,9 @@ module t (/*AUTOARG*/ parameter DWORDS_LOG2 = 7; parameter DWORDS = (1<