Support expression coverage on assign statements (#7543)
This commit is contained in:
parent
e485dfe48c
commit
1c3ee7ce4c
|
|
@ -263,6 +263,7 @@ Szymon Gizler
|
|||
Sören Tempel
|
||||
Teng Huang
|
||||
Thomas Aldrian
|
||||
Thomas Brown
|
||||
Thomas Dybdahl Ahle
|
||||
Tim Hutt
|
||||
Tim Snyder
|
||||
|
|
|
|||
|
|
@ -290,8 +290,15 @@ class CoverageVisitor final : public VNVisitor {
|
|||
}
|
||||
void visit(AstAlways* nodep) override {
|
||||
if (nodep->keyword() == VAlwaysKwd::CONT_ASSIGN) {
|
||||
// Don't want line coverage for it, iterate for expression/toggle coverage only
|
||||
// Handle continuous assigns for expression coverage (but not line coverage)
|
||||
VL_RESTORER(m_state);
|
||||
VL_RESTORER(m_exprStmtsp);
|
||||
VL_RESTORER(m_inToggleOff);
|
||||
m_exprStmtsp = nodep;
|
||||
m_inToggleOff = true;
|
||||
createHandle(nodep);
|
||||
iterateChildren(nodep);
|
||||
// Note: No line coverage for continuous assigns
|
||||
return;
|
||||
}
|
||||
iterateProcedure(nodep);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
integer some_int;
|
||||
integer other_int;
|
||||
logic some_bool;
|
||||
logic [1:0] assign_lhs;
|
||||
|
||||
wire t1 = cyc[0];
|
||||
wire t2 = cyc[1];
|
||||
|
|
@ -283,6 +284,18 @@
|
|||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
end
|
||||
|
||||
%000005 assign assign_lhs[0] = t1 && t2;
|
||||
-000005 point: type=expr comment=(t1==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
%000003 assign assign_lhs[1] = (t1 && t2) || (t3 && t4);
|
||||
-000003 point: type=expr comment=(t1==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t
|
||||
-000000 point: type=expr comment=(t3==1 && t4==1) => 1 hier=top.t
|
||||
|
||||
logic ta, tb, tc;
|
||||
initial begin
|
||||
automatic cls obj = new;
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ module t (
|
|||
integer some_int;
|
||||
integer other_int;
|
||||
logic some_bool;
|
||||
logic [1:0] assign_lhs;
|
||||
|
||||
wire t1 = cyc[0];
|
||||
wire t2 = cyc[1];
|
||||
|
|
@ -120,6 +121,9 @@ module t (
|
|||
if (t1 && t2) $write("");
|
||||
end
|
||||
|
||||
assign assign_lhs[0] = t1 && t2;
|
||||
assign assign_lhs[1] = (t1 && t2) || (t3 && t4);
|
||||
|
||||
logic ta, tb, tc;
|
||||
initial begin
|
||||
automatic cls obj = new;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
integer some_int;
|
||||
integer other_int;
|
||||
logic some_bool;
|
||||
logic [1:0] assign_lhs;
|
||||
|
||||
wire t1 = cyc[0];
|
||||
wire t2 = cyc[1];
|
||||
|
|
@ -411,6 +412,18 @@
|
|||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
end
|
||||
|
||||
%000005 assign assign_lhs[0] = t1 && t2;
|
||||
-000005 point: type=expr comment=(t1==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
%000003 assign assign_lhs[1] = (t1 && t2) || (t3 && t4);
|
||||
-000003 point: type=expr comment=(t1==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t
|
||||
-000000 point: type=expr comment=(t3==1 && t4==1) => 1 hier=top.t
|
||||
|
||||
logic ta, tb, tc;
|
||||
initial begin
|
||||
automatic cls obj = new;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
integer some_int;
|
||||
integer other_int;
|
||||
logic some_bool;
|
||||
logic [1:0] assign_lhs;
|
||||
|
||||
wire t1 = cyc[0];
|
||||
wire t2 = cyc[1];
|
||||
|
|
@ -283,6 +284,18 @@
|
|||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
end
|
||||
|
||||
%000005 assign assign_lhs[0] = t1 && t2;
|
||||
-000005 point: type=expr comment=(t1==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
%000003 assign assign_lhs[1] = (t1 && t2) || (t3 && t4);
|
||||
-000003 point: type=expr comment=(t1==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t
|
||||
-000000 point: type=expr comment=(t3==1 && t4==1) => 1 hier=top.t
|
||||
|
||||
logic ta, tb, tc;
|
||||
initial begin
|
||||
automatic cls obj = new;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
integer some_int;
|
||||
integer other_int;
|
||||
logic some_bool;
|
||||
logic [1:0] assign_lhs;
|
||||
|
||||
wire t1 = cyc[0];
|
||||
wire t2 = cyc[1];
|
||||
|
|
@ -393,6 +394,18 @@
|
|||
-000008 point: type=branch comment=else hier=top.t
|
||||
end
|
||||
|
||||
%000005 assign assign_lhs[0] = t1 && t2;
|
||||
-000005 point: type=expr comment=(t1==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000005 point: type=expr comment=(t2==0) => 0 hier=top.t
|
||||
%000003 assign assign_lhs[1] = (t1 && t2) || (t3 && t4);
|
||||
-000003 point: type=expr comment=(t1==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t
|
||||
-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t
|
||||
-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t
|
||||
-000000 point: type=expr comment=(t3==1 && t4==1) => 1 hier=top.t
|
||||
|
||||
logic ta, tb, tc;
|
||||
%000001 initial begin
|
||||
-000001 point: type=line comment=block hier=top.t
|
||||
|
|
|
|||
Loading…
Reference in New Issue