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[#73220] remove t_trace_counter_saif test

This commit is contained in:
Mateusz Gancarz 2025-02-25 15:30:39 +01:00
parent a0d574e784
commit 0e4e616050
2 changed files with 0 additions and 75 deletions
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53
test_regress/t/t_trace_counter_saif.out
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@ -1,53 +0,0 @@
(SAIFILE
(SAIFVERSION "2.0")
(DIRECTION "backward")
(DESIGN "t")
(DIVIDER / )
(TIMESCALE 1 ps)
(DURATION 1000)
(INSTANCE top
(NET
(clk (T0 505) (T1 495) (TX 0) (TC 199) (IG 0))
(state\[0\] (T0 510) (T1 490) (TX 0) (TC 98) (IG 0))
(state\[1\] (T0 510) (T1 490) (TX 0) (TC 50) (IG 0))
(state\[2\] (T0 520) (T1 480) (TX 0) (TC 24) (IG 0))
(state\[3\] (T0 570) (T1 430) (TX 0) (TC 13) (IG 0))
(state\[4\] (T0 600) (T1 400) (TX 0) (TC 5) (IG 0))
(state\[5\] (T0 680) (T1 320) (TX 0) (TC 2) (IG 0))
(state\[6\] (T0 760) (T1 240) (TX 0) (TC 1) (IG 0))
)
(INSTANCE t
(NET
(clk (T0 505) (T1 495) (TX 0) (TC 199) (IG 0))
(rst (T0 20) (T1 980) (TX 0) (TC 3) (IG 0))
(state\[0\] (T0 510) (T1 490) (TX 0) (TC 98) (IG 0))
(state\[1\] (T0 510) (T1 490) (TX 0) (TC 50) (IG 0))
(state\[2\] (T0 520) (T1 480) (TX 0) (TC 24) (IG 0))
(state\[3\] (T0 570) (T1 430) (TX 0) (TC 13) (IG 0))
(state\[4\] (T0 600) (T1 400) (TX 0) (TC 5) (IG 0))
(state\[5\] (T0 680) (T1 320) (TX 0) (TC 2) (IG 0))
(state\[6\] (T0 760) (T1 240) (TX 0) (TC 1) (IG 0))
(cyc\[0\] (T0 500) (T1 500) (TX 0) (TC 100) (IG 0))
(cyc\[1\] (T0 500) (T1 500) (TX 0) (TC 50) (IG 0))
(cyc\[2\] (T0 520) (T1 480) (TX 0) (TC 25) (IG 0))
(cyc\[3\] (T0 520) (T1 480) (TX 0) (TC 12) (IG 0))
(cyc\[4\] (T0 520) (T1 480) (TX 0) (TC 6) (IG 0))
(cyc\[5\] (T0 640) (T1 360) (TX 0) (TC 3) (IG 0))
(cyc\[6\] (T0 640) (T1 360) (TX 0) (TC 1) (IG 0))
)
(INSTANCE c0
(NET
(clk (T0 505) (T1 495) (TX 0) (TC 199) (IG 0))
(rst (T0 20) (T1 980) (TX 0) (TC 3) (IG 0))
(out\[0\] (T0 510) (T1 490) (TX 0) (TC 98) (IG 0))
(out\[1\] (T0 510) (T1 490) (TX 0) (TC 50) (IG 0))
(out\[2\] (T0 520) (T1 480) (TX 0) (TC 24) (IG 0))
(out\[3\] (T0 570) (T1 430) (TX 0) (TC 13) (IG 0))
(out\[4\] (T0 600) (T1 400) (TX 0) (TC 5) (IG 0))
(out\[5\] (T0 680) (T1 320) (TX 0) (TC 2) (IG 0))
(out\[6\] (T0 760) (T1 240) (TX 0) (TC 1) (IG 0))
)
)
)
)
)

22
test_regress/t/t_trace_counter_saif.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test module
#
# Copyright 2025 by Antmicro. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_counter.v"
test.golden_filename = "t/t_trace_counter_saif.out"
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()