Support "program".

Changes

@@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Support "reg [1:0][1:0][1:0]", bug176.  [Byron Bradley]
 
+***  Support "program".
+
 * Verilator 3.720 2009/10/26
 
 **   Support little endian bit vectors ("reg [0:2] x;").

src/verilog.l

@@ -365,6 +365,7 @@ escid	\\[^ \t\f\r\n]+
   "clocking"		{ FL; return yCLOCKING; }
   "do"			{ FL; return yDO; }
   "endclocking"		{ FL; return yENDCLOCKING; }
+  "endprogram"		{ FL; return yENDPROGRAM; }
   "endproperty"		{ FL; return yENDPROPERTY; }
   "final"		{ FL; return yFINAL; }
   "iff"			{ FL; return yIFF; }
@@ -372,6 +373,7 @@ escid	\\[^ \t\f\r\n]+
   "logic"		{ FL; return yLOGIC; }
   "longint"		{ FL; return yLONGINT; }
   "priority"		{ FL; return yPRIORITY; }
+  "program"		{ FL; return yPROGRAM; }
   "shortint"		{ FL; return ySHORTINT; }
   "static"		{ FL; return ySTATIC; }
   "timeprecision"	{ FL; return yTIMEPRECISION; }
@@ -400,7 +402,6 @@ escid	\\[^ \t\f\r\n]+
   "endgroup"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "endinterface"	{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "endpackage"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "endprogram"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "endsequence"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "enum"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "expect"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
@@ -425,7 +426,6 @@ escid	\\[^ \t\f\r\n]+
   "null"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "package"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "packed"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "program"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "protected"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "pure"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "rand"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

src/verilog.y

@@ -245,6 +245,7 @@ class AstSenTree;
 %token<fl>		yENDFUNCTION	"endfunction"
 %token<fl>		yENDGENERATE	"endgenerate"
 %token<fl>		yENDMODULE	"endmodule"
+%token<fl>		yENDPROGRAM	"endprogram"
 %token<fl>		yENDPROPERTY	"endproperty"
 %token<fl>		yENDSPECIFY	"endspecify"
 %token<fl>		yENDTASK	"endtask"
@@ -276,6 +277,7 @@ class AstSenTree;
 %token<fl>		yPARAMETER	"parameter"
 %token<fl>		yPOSEDGE	"posedge"
 %token<fl>		yPRIORITY	"priority"
+%token<fl>		yPROGRAM	"program"
 %token<fl>		yPROPERTY	"property"
 %token<fl>		yPULLDOWN	"pulldown"
 %token<fl>		yPULLUP		"pullup"
@@ -502,7 +504,7 @@ descriptionList:		// IEEE: part of source_text
 description:			// ==IEEE: description
 		module_declaration			{ }
 	//UNSUP	interface_declaration			{ }
-	//UNSUP	program_declaration			{ }
+	|	program_declaration			{ }
 	//UNSUP	package_declaration			{ }
 	//UNSUP	package_item				{ }
 	//UNSUP	bind_directive				{ }
@@ -685,6 +687,57 @@ portSig<nodep>:
 //**********************************************************************
 // Program headers
 
+program_declaration:		// IEEE: program_declaration + program_nonansi_header + program_ansi_header:
+	//			// timeunits_delcarationE is instead in program_item
+		pgmFront parameter_port_listE portsStarE ';'
+			program_itemListE yENDPROGRAM endLabelE
+			{ $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn());  // Stash for implicit wires, etc
+			  if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3);
+			  if ($5) $1->addStmtp($5);
+			  SYMP->popScope($1); }
+	//UNSUP	yEXTERN	pgmFront parameter_port_listE portsStarE ';'
+	//UNSUP		{ PARSEP->symPopScope(VAstType::PROGRAM); }
+	;
+
+pgmFront<modulep>:
+		yPROGRAM lifetimeE idAny/*new_program*/
+			{ $$ = new AstModule($1,*$3); $$->inLibrary(PARSEP->inLibrary()||PARSEP->inCellDefine());
+			  $$->modTrace(v3Global.opt.trace());
+			  PARSEP->rootp()->addModulep($$);
+			  SYMP->pushNew($$); }
+	;
+
+program_itemListE<nodep>:	// ==IEEE: [{ program_item }]
+		/* empty */				{ $$ = NULL; }
+	|	program_itemList			{ $$ = $1; }
+	;
+
+program_itemList<nodep>:	// ==IEEE: { program_item }
+		program_item				{ $$ = $1; }
+	|	program_itemList program_item		{ $$ = $1->addNextNull($2); }
+	;
+
+program_item<nodep>:		// ==IEEE: program_item
+		port_declaration ';'			{ $$ = $1; }
+	|	non_port_program_item			{ $$ = $1; }
+	;
+
+non_port_program_item<nodep>:	// ==IEEE: non_port_program_item
+		continuous_assign			{ $$ = $1; }
+	|	module_or_generate_item_declaration	{ $$ = $1; }
+	|	initial_construct			{ $$ = $1; }
+	|	final_construct				{ $$ = $1; }
+	|	concurrent_assertion_item		{ $$ = $1; }
+	//UNSUP	timeunits_declaration			{ $$ = $1; }
+	|	program_generate_item			{ $$ = $1; }
+	;
+
+program_generate_item<nodep>:		// ==IEEE: program_generate_item
+		loop_generate_construct			{ $$ = $1; }
+	|	conditional_generate_construct		{ $$ = $1; }
+	|	generate_region				{ $$ = $1; }
+	;
+
 //************************************************
 // Variable Declarations
 

test_regress/t/t_program.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_program.v

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+program t;
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endprogram