From 0d65f08b1dd2496ab7d4b7917e06554c1b6b671b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 5 Nov 2009 19:09:45 -0500 Subject: [PATCH] Support "program". --- Changes | 2 ++ src/verilog.l | 4 +-- src/verilog.y | 55 ++++++++++++++++++++++++++++++++++++- test_regress/t/t_program.pl | 18 ++++++++++++ test_regress/t/t_program.v | 11 ++++++++ 5 files changed, 87 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_program.pl create mode 100644 test_regress/t/t_program.v diff --git a/Changes b/Changes index 7da71d744..c93aa5136 100644 --- a/Changes +++ b/Changes @@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks! *** Support "reg [1:0][1:0][1:0]", bug176. [Byron Bradley] +*** Support "program". + * Verilator 3.720 2009/10/26 ** Support little endian bit vectors ("reg [0:2] x;"). diff --git a/src/verilog.l b/src/verilog.l index b9f478071..f39fd4708 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -365,6 +365,7 @@ escid \\[^ \t\f\r\n]+ "clocking" { FL; return yCLOCKING; } "do" { FL; return yDO; } "endclocking" { FL; return yENDCLOCKING; } + "endprogram" { FL; return yENDPROGRAM; } "endproperty" { FL; return yENDPROPERTY; } "final" { FL; return yFINAL; } "iff" { FL; return yIFF; } @@ -372,6 +373,7 @@ escid \\[^ \t\f\r\n]+ "logic" { FL; return yLOGIC; } "longint" { FL; return yLONGINT; } "priority" { FL; return yPRIORITY; } + "program" { FL; return yPROGRAM; } "shortint" { FL; return ySHORTINT; } "static" { FL; return ySTATIC; } "timeprecision" { FL; return yTIMEPRECISION; } @@ -400,7 +402,6 @@ escid \\[^ \t\f\r\n]+ "endgroup" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "endinterface" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "endpackage" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "endprogram" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "endsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "enum" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "expect" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } @@ -425,7 +426,6 @@ escid \\[^ \t\f\r\n]+ "null" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "package" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "packed" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "program" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "protected" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "pure" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "rand" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } diff --git a/src/verilog.y b/src/verilog.y index 2f6ecb893..0872f2ebb 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -245,6 +245,7 @@ class AstSenTree; %token yENDFUNCTION "endfunction" %token yENDGENERATE "endgenerate" %token yENDMODULE "endmodule" +%token yENDPROGRAM "endprogram" %token yENDPROPERTY "endproperty" %token yENDSPECIFY "endspecify" %token yENDTASK "endtask" @@ -276,6 +277,7 @@ class AstSenTree; %token yPARAMETER "parameter" %token yPOSEDGE "posedge" %token yPRIORITY "priority" +%token yPROGRAM "program" %token yPROPERTY "property" %token yPULLDOWN "pulldown" %token yPULLUP "pullup" @@ -502,7 +504,7 @@ descriptionList: // IEEE: part of source_text description: // ==IEEE: description module_declaration { } //UNSUP interface_declaration { } - //UNSUP program_declaration { } + | program_declaration { } //UNSUP package_declaration { } //UNSUP package_item { } //UNSUP bind_directive { } @@ -685,6 +687,57 @@ portSig: //********************************************************************** // Program headers +program_declaration: // IEEE: program_declaration + program_nonansi_header + program_ansi_header: + // // timeunits_delcarationE is instead in program_item + pgmFront parameter_port_listE portsStarE ';' + program_itemListE yENDPROGRAM endLabelE + { $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc + if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); + if ($5) $1->addStmtp($5); + SYMP->popScope($1); } + //UNSUP yEXTERN pgmFront parameter_port_listE portsStarE ';' + //UNSUP { PARSEP->symPopScope(VAstType::PROGRAM); } + ; + +pgmFront: + yPROGRAM lifetimeE idAny/*new_program*/ + { $$ = new AstModule($1,*$3); $$->inLibrary(PARSEP->inLibrary()||PARSEP->inCellDefine()); + $$->modTrace(v3Global.opt.trace()); + PARSEP->rootp()->addModulep($$); + SYMP->pushNew($$); } + ; + +program_itemListE: // ==IEEE: [{ program_item }] + /* empty */ { $$ = NULL; } + | program_itemList { $$ = $1; } + ; + +program_itemList: // ==IEEE: { program_item } + program_item { $$ = $1; } + | program_itemList program_item { $$ = $1->addNextNull($2); } + ; + +program_item: // ==IEEE: program_item + port_declaration ';' { $$ = $1; } + | non_port_program_item { $$ = $1; } + ; + +non_port_program_item: // ==IEEE: non_port_program_item + continuous_assign { $$ = $1; } + | module_or_generate_item_declaration { $$ = $1; } + | initial_construct { $$ = $1; } + | final_construct { $$ = $1; } + | concurrent_assertion_item { $$ = $1; } + //UNSUP timeunits_declaration { $$ = $1; } + | program_generate_item { $$ = $1; } + ; + +program_generate_item: // ==IEEE: program_generate_item + loop_generate_construct { $$ = $1; } + | conditional_generate_construct { $$ = $1; } + | generate_region { $$ = $1; } + ; + //************************************************ // Variable Declarations diff --git a/test_regress/t/t_program.pl b/test_regress/t/t_program.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_program.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_program.v b/test_regress/t/t_program.v new file mode 100644 index 000000000..4f2436f99 --- /dev/null +++ b/test_regress/t/t_program.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +program t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endprogram