[#72179] wip: add t_trace_complex_saif test
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER .)
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(TIMESCALE 1ps)
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(DURATION 60)
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(INSTANCE foo (NET
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(a[0] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(a[2] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(b[0] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(b[2] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(PARAM[0] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(PARAM[1] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(PARAM[1] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(PARAM[2] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_arrp_strp[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_strp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_strp[2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_strp[3] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_arrp[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_arrp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_arrp[2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_arrp[3] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp[2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc[1] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_unip_strp[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_unip_strp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_strp_strp[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp_strp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp_strp[2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp_strp[3] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
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(v_arru_arrp[3][1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_arrp[3][2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_arrp[4][1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_arrp[4][2] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[3][0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[3][1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[4][0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[4][1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_str32x2[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
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(v_str32x2[1] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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(v_str32x2[2] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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(v_str32x2[3] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_str32x2[4] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_str32x2[5] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_str32x2[6] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_str32x2[7] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_str32x2[32] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_str32x2[33] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_str32x2[34] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_enumed[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_enumed[1] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_enumed[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_enumed2[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_enumed2[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_enumed2[3] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(v_enumb[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_enumb[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_enumb[2] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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(v_enumb2_str[0] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
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(v_enumb2_str[1] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_enumb2_str[2] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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(v_enumb2_str[3] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
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(v_enumb2_str[4] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(v_enumb2_str[5] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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)))
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_trace_complex.v"
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test.compile(verilator_flags2=['--cc --trace'])
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test.execute()
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test.saif_identical(test.trace_filename, test.golden_filename)
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test.passes()
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