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Fix supporting begin_keywords 1364-2001-noconfig

This commit is contained in:
Wilson Snyder 2020-12-16 18:40:45 -05:00
parent 6adda241c9
commit 0abf18f618
2 changed files with 32 additions and 16 deletions
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32
src/verilog.l
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@ -78,7 +78,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
%a 15000 %a 15000
%o 25000 %o 25000
%s V95 V01 V05 S05 S09 S12 S17 %s V95 V01NC V01C V05 S05 S09 S12 S17
%s STRING ATTRMODE TABLE %s STRING ATTRMODE TABLE
%s VA5 SAX VLT %s VA5 SAX VLT
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
@ -155,7 +155,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Verilog 1995 */ /* Verilog 1995 */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */ {ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
{crnl} { FL_FWD; FL_BRK; } /* Count line numbers */ {crnl} { FL_FWD; FL_BRK; } /* Count line numbers */
/* Extensions to Verilog set, some specified by PSL */ /* Extensions to Verilog set, some specified by PSL */
@ -395,7 +395,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2001 */ /* Verilog 2001 */
<V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
/* System Tasks */ /* System Tasks */
"$signed" { FL; return yD_SIGNED; } "$signed" { FL; return yD_SIGNED; }
"$unsigned" { FL; return yD_UNSIGNED; } "$unsigned" { FL; return yD_UNSIGNED; }
@ -412,6 +412,10 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"showcancelled" { FL; return yaTIMINGSPEC; } "showcancelled" { FL; return yaTIMINGSPEC; }
"signed" { FL; return ySIGNED; } "signed" { FL; return ySIGNED; }
"unsigned" { FL; return yUNSIGNED; } "unsigned" { FL; return yUNSIGNED; }
}
/* Verilog 2001 Config */
<V01C,V05,VA5,S05,S09,S12,S17,SAX>{
/* Generic unsupported keywords */ /* Generic unsupported keywords */
"cell" { ERROR_RSVD_WORD("Verilog 2001-config"); } "cell" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"config" { ERROR_RSVD_WORD("Verilog 2001-config"); } "config" { ERROR_RSVD_WORD("Verilog 2001-config"); }
@ -606,7 +610,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* No new keywords */ /* No new keywords */
/* Default PLI rule */ /* Default PLI rule */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext, yyleng); "$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext, yyleng);
yylval.strp = PARSEP->newString(AstNode::encodeName(str)); yylval.strp = PARSEP->newString(AstNode::encodeName(str));
FL; return yaD_PLI; FL; return yaD_PLI;
@ -710,7 +714,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Meta comments */ /* Meta comments */
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */ "/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */
"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
"/*verilator clocker*/" { FL; return yVL_CLOCKER; } "/*verilator clocker*/" { FL; return yVL_CLOCKER; }
@ -750,7 +754,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Single character operator thingies */ /* Single character operator thingies */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"{" { FL; return yytext[0]; } "{" { FL; return yytext[0]; }
"}" { FL; return yytext[0]; } "}" { FL; return yytext[0]; }
"!" { FL; return yytext[0]; } "!" { FL; return yytext[0]; }
@ -784,7 +788,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Operators and multi-character symbols */ /* Operators and multi-character symbols */
/* Verilog 1995 Operators */ /* Verilog 1995 Operators */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"&&" { FL; return yP_ANDAND; } "&&" { FL; return yP_ANDAND; }
"||" { FL; return yP_OROR; } "||" { FL; return yP_OROR; }
"<=" { FL; return yP_LTE; } "<=" { FL; return yP_LTE; }
@ -806,7 +810,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2001 Operators */ /* Verilog 2001 Operators */
<V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"<<<" { FL; return yP_SLEFT; } "<<<" { FL; return yP_SLEFT; }
">>>" { FL; return yP_SSRIGHT; } ">>>" { FL; return yP_SSRIGHT; }
"**" { FL; return yP_POW; } "**" { FL; return yP_POW; }
@ -858,7 +862,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Identifiers and numbers */ /* Identifiers and numbers */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
{escid} { FL; yylval.strp = PARSEP->newString {escid} { FL; yylval.strp = PARSEP->newString
(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash (AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
return yaID__LEX; return yaID__LEX;
@ -936,7 +940,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Attributes */ /* Attributes */
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
} }
@ -956,7 +960,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Common for all SYSC header states */ /* Common for all SYSC header states */
/* OPTIMIZE: we return one per line, make it one for the entire block */ /* OPTIMIZE: we return one per line, make it one for the entire block */
/* If add to this list also add to V3LanguageWords.h */ /* If add to this list also add to V3LanguageWords.h */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
"`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; } "`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; }
@ -1004,8 +1008,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* See also setLanguage below */ /* See also setLanguage below */
"`begin_keywords"[ \t]*\"1364-1995\" { FL_FWD; yy_push_state(V95); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1364-1995\" { FL_FWD; yy_push_state(V95); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01C); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01NC); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1364-2005\" { FL_FWD; yy_push_state(V05); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1364-2005\" { FL_FWD; yy_push_state(V05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { FL_FWD; yy_push_state(VA5); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { FL_FWD; yy_push_state(VA5); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800-2005\" { FL_FWD; yy_push_state(S05); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2005\" { FL_FWD; yy_push_state(S05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
@ -1052,7 +1056,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Default rules - leave last */ /* Default rules - leave last */
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
"`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; } "`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; }
"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ "//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
. { FL; return yytext[0]; } /* return single char ops. */ . { FL; return yytext[0]; } /* return single char ops. */

16
test_regress/t/t_preproc_kwd.v
View File

@ -11,7 +11,8 @@ module t (/*AUTOARG*/
input clk; input clk;
v95 v95 (); v95 v95 ();
v01 v01 (); v01nc v01nc ();
v01c v01c ();
v05 v05 (); v05 v05 ();
s05 s05 (); s05 s05 ();
s09 s09 (); s09 s09 ();
@ -31,26 +32,37 @@ module v95;
endmodule endmodule
`end_keywords `end_keywords
`begin_keywords "1364-2001-noconfig"
module v01nc;
localparam g = 0;
integer instance; initial instance = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001" `begin_keywords "1364-2001"
module v01; module v01c;
localparam g = 0;
integer bit; initial bit = 1; integer bit; initial bit = 1;
endmodule endmodule
`end_keywords `end_keywords
`begin_keywords "1364-2005" `begin_keywords "1364-2005"
module v05; module v05;
uwire w;
integer final; initial final = 1; integer final; initial final = 1;
endmodule endmodule
`end_keywords `end_keywords
`begin_keywords "1800-2005" `begin_keywords "1800-2005"
module s05; module s05;
bit b;
integer global; initial global = 1; integer global; initial global = 1;
endmodule endmodule
`end_keywords `end_keywords
`begin_keywords "1800-2009" `begin_keywords "1800-2009"
module s09; module s09;
bit b;
integer soft; initial soft = 1; integer soft; initial soft = 1;
endmodule endmodule
`end_keywords `end_keywords