diff --git a/src/verilog.l b/src/verilog.l
index 422af9538..b322394f3 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -78,7 +78,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
 %a 15000
 %o 25000
 
-%s V95 V01 V05 S05 S09 S12 S17
+%s V95 V01NC V01C V05 S05 S09 S12 S17
 %s STRING ATTRMODE TABLE
 %s VA5 SAX VLT
 %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
@@ -155,7 +155,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 
   /************************************************************************/
   /* Verilog 1995 */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   {ws}                  { FL_FWD; FL_BRK; }  /* otherwise ignore white-space */
   {crnl}                { FL_FWD; FL_BRK; }  /* Count line numbers */
   /*     Extensions to Verilog set, some specified by PSL */
@@ -395,7 +395,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Verilog 2001 */
-<V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   /*     System Tasks */
   "$signed"             { FL; return yD_SIGNED; }
   "$unsigned"           { FL; return yD_UNSIGNED; }
@@ -412,6 +412,10 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "showcancelled"       { FL; return yaTIMINGSPEC; }
   "signed"              { FL; return ySIGNED; }
   "unsigned"            { FL; return yUNSIGNED; }
+}
+
+  /* Verilog 2001 Config */
+<V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   /*     Generic unsupported keywords */
   "cell"                { ERROR_RSVD_WORD("Verilog 2001-config"); }
   "config"              { ERROR_RSVD_WORD("Verilog 2001-config"); }
@@ -606,7 +610,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* No new keywords */
 
   /* Default PLI rule */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   "$"[a-zA-Z_$][a-zA-Z0-9_$]*   { string str (yytext, yyleng);
                                   yylval.strp = PARSEP->newString(AstNode::encodeName(str));
                                   FL; return yaD_PLI;
@@ -710,7 +714,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Meta comments */
 
   /* Converted from //{cmt}verilator ...{cmt} by preprocessor */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   "/*verilator"{ws}*"*/"                { FL_FWD; FL_BRK; }  /* Ignore empty comments, may be `endif // verilator */
   "/*verilator clock_enable*/"          { FL; return yVL_CLOCK_ENABLE; }
   "/*verilator clocker*/"               { FL; return yVL_CLOCKER; }
@@ -750,7 +754,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /************************************************************************/
 
   /* Single character operator thingies */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   "{"                   { FL; return yytext[0]; }
   "}"                   { FL; return yytext[0]; }
   "!"                   { FL; return yytext[0]; }
@@ -784,7 +788,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Operators and multi-character symbols */
 
   /* Verilog 1995 Operators */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   "&&"                  { FL; return yP_ANDAND; }
   "||"                  { FL; return yP_OROR; }
   "<="                  { FL; return yP_LTE; }
@@ -806,7 +810,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Verilog 2001 Operators */
-<V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
   "<<<"                 { FL; return yP_SLEFT; }
   ">>>"                 { FL; return yP_SSRIGHT; }
   "**"                  { FL; return yP_POW; }
@@ -858,7 +862,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Identifiers and numbers */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
   {escid}               { FL; yylval.strp = PARSEP->newString
                                 (AstNode::encodeName(string(yytext+1)));  // +1 to skip the backslash
                           return yaID__LEX;
@@ -936,7 +940,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /************************************************************************/
   /* Attributes */
   /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
     "(*"({ws}|{crnl})*({id}|{escid})    { yymore(); yy_push_state(ATTRMODE); }  /* Doesn't match (*), but (* attr_spec */
 }
 
@@ -956,7 +960,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Common for all SYSC header states */
   /* OPTIMIZE: we return one per line, make it one for the entire block */
   /* If add to this list also add to V3LanguageWords.h */
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
   "`accelerate"                         { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`autoexpand_vectornets"              { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`celldefine"                         { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; }
@@ -1004,8 +1008,8 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 
   /* See also setLanguage below */
   "`begin_keywords"[ \t]*\"1364-1995\"          { FL_FWD; yy_push_state(V95); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
-  "`begin_keywords"[ \t]*\"1364-2001\"          { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
-  "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
+  "`begin_keywords"[ \t]*\"1364-2001\"          { FL_FWD; yy_push_state(V01C); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
+  "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01NC); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
   "`begin_keywords"[ \t]*\"1364-2005\"          { FL_FWD; yy_push_state(V05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
   "`begin_keywords"[ \t]*\"VAMS[-0-9.]*\"       { FL_FWD; yy_push_state(VA5); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
   "`begin_keywords"[ \t]*\"1800-2005\"          { FL_FWD; yy_push_state(S05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
@@ -1052,7 +1056,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /************************************************************************/
   /* Default rules - leave last */
 
-<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
+<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
   "`"[a-zA-Z_0-9]+      { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; }
   "//"[^\n]*            { FL_FWD; FL_BRK; }  /* throw away single line comments */
   .                     { FL; return yytext[0]; }       /* return single char ops. */
diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v
index ab22e2983..bee3632e0 100644
--- a/test_regress/t/t_preproc_kwd.v
+++ b/test_regress/t/t_preproc_kwd.v
@@ -11,7 +11,8 @@ module t (/*AUTOARG*/
    input clk;
 
    v95 v95 ();
-   v01 v01 ();
+   v01nc v01nc ();
+   v01c v01c ();
    v05 v05 ();
    s05 s05 ();
    s09 s09 ();
@@ -31,26 +32,37 @@ module v95;
 endmodule
 `end_keywords
 
+`begin_keywords "1364-2001-noconfig"
+module v01nc;
+  localparam g = 0;
+  integer instance; initial instance = 1;
+endmodule
+`end_keywords
+
 `begin_keywords "1364-2001"
-module v01;
+module v01c;
+  localparam g = 0;
   integer bit; initial bit = 1;
 endmodule
 `end_keywords
 
 `begin_keywords "1364-2005"
 module v05;
+  uwire w;
   integer final; initial final = 1;
 endmodule
 `end_keywords
 
 `begin_keywords "1800-2005"
 module s05;
+  bit b;
   integer global; initial global = 1;
 endmodule
 `end_keywords
 
 `begin_keywords "1800-2009"
 module s09;
+   bit b;
    integer soft; initial soft = 1;
 endmodule
 `end_keywords