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Add FSM state coverage to verilator_coverage .info output (#7973)

This commit is contained in:
Igor Zaworski 2026-07-22 18:24:02 +02:00 committed by GitHub
parent f149dd304c
commit 0a855fce47
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4 changed files with 43 additions and 1 deletions
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2
src/VlcTop.cpp
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@ -264,7 +264,7 @@ void VlcTop::writeInfo(const string& filename) {
for (const auto& point : sc.points()) { for (const auto& point : sc.points()) {
if (point->isFsmArc()) continue; if (point->isFsmArc()) continue;
daCount = std::max(daCount, point->count()); daCount = std::max(daCount, point->count());
if (!point->isFsmState()) infoPoints.push_back(point); infoPoints.push_back(point);
} }
os << "DA:" << sc.lineno() << "," << daCount << "\n"; os << "DA:" << sc.lineno() << "," << daCount << "\n";
if (infoPoints.size() <= 1) continue; if (infoPoints.size() <= 1) continue;

10
test_regress/t/t_vlcov_data_g.dat Normal file
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@ -0,0 +1,10 @@
# SystemC::Coverage-3
C 'ft/t_cover_fsm_basic.vl45n7tfsm_arcpagev_fsm_arc/$rootot.state::ANY->S_IDLE[reset_include]Fvt.stateFfANYFtS_IDLEFgreset_includehtop.TOP' 1
C 'ft/t_cover_fsm_basic.vl45n7tfsm_arcpagev_fsm_arc/$rootot.state::S_DONE->S_DONEFvt.stateFfS_DONEFtS_DONEhtop.TOP' 4
C 'ft/t_cover_fsm_basic.vl45n7tfsm_arcpagev_fsm_arc/$rootot.state::S_IDLE->S_IDLEFvt.stateFfS_IDLEFtS_IDLEhtop.TOP' 3
C 'ft/t_cover_fsm_basic.vl45n7tfsm_arcpagev_fsm_arc/$rootot.state::S_IDLE->S_RUNFvt.stateFfS_IDLEFtS_RUNhtop.TOP' 1
C 'ft/t_cover_fsm_basic.vl45n7tfsm_arcpagev_fsm_arc/$rootot.state::S_RUN->S_DONEFvt.stateFfS_RUNFtS_DONEhtop.TOP' 1
C 'ft/t_cover_fsm_basic.vl45n7tfsm_statepagev_fsm_state/$rootot.state::S_DONEFvt.stateFtS_DONEhtop.TOP' 1
C 'ft/t_cover_fsm_basic.vl45n7tfsm_statepagev_fsm_state/$rootot.state::S_ERRFvt.stateFtS_ERRhtop.TOP' 0
C 'ft/t_cover_fsm_basic.vl45n7tfsm_statepagev_fsm_state/$rootot.state::S_IDLEFvt.stateFtS_IDLEhtop.TOP' 0
C 'ft/t_cover_fsm_basic.vl45n7tfsm_statepagev_fsm_state/$rootot.state::S_RUNFvt.stateFtS_RUNhtop.TOP' 1

10
test_regress/t/t_vlcov_opt_fsm_state.info.out Normal file
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@ -0,0 +1,10 @@
TN:verilator_coverage
SF:t/t_cover_fsm_basic.v
DA:45,1
BRDA:45,0,t.state::S_DONE,1
BRDA:45,0,t.state::S_ERR,0
BRDA:45,0,t.state::S_IDLE,0
BRDA:45,0,t.state::S_RUN,1
BRF:4
BRH:0
end_of_record

22
test_regress/t/t_vlcov_opt_fsm_state.py Executable file
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@ -0,0 +1,22 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('dist')
test.run(cmd=[
os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info",
test.obj_dir + "/coverage.info", "--filter-type fsm_state", "t/t_vlcov_data_g.dat"
],
verilator_run=True)
test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out")
test.passes()