diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp
index de5160c2d..70a0a7f7d 100644
--- a/src/VlcTop.cpp
+++ b/src/VlcTop.cpp
@@ -264,7 +264,7 @@ void VlcTop::writeInfo(const string& filename) {
             for (const auto& point : sc.points()) {
                 if (point->isFsmArc()) continue;
                 daCount = std::max(daCount, point->count());
-                if (!point->isFsmState()) infoPoints.push_back(point);
+                infoPoints.push_back(point);
             }
             os << "DA:" << sc.lineno() << "," << daCount << "\n";
             if (infoPoints.size() <= 1) continue;
diff --git a/test_regress/t/t_vlcov_data_g.dat b/test_regress/t/t_vlcov_data_g.dat
new file mode 100644
index 000000000..0148fab6b
--- /dev/null
+++ b/test_regress/t/t_vlcov_data_g.dat
@@ -0,0 +1,10 @@
+# SystemC::Coverage-3
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_arc
pagev_fsm_arc/$root
ot.state::ANY->S_IDLE[reset_include]
Fvt.state
FfANY
FtS_IDLE
Fgreset_include
htop.TOP' 1
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_arc
pagev_fsm_arc/$root
ot.state::S_DONE->S_DONE
Fvt.state
FfS_DONE
FtS_DONE
htop.TOP' 4
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_arc
pagev_fsm_arc/$root
ot.state::S_IDLE->S_IDLE
Fvt.state
FfS_IDLE
FtS_IDLE
htop.TOP' 3
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_arc
pagev_fsm_arc/$root
ot.state::S_IDLE->S_RUN
Fvt.state
FfS_IDLE
FtS_RUN
htop.TOP' 1
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_arc
pagev_fsm_arc/$root
ot.state::S_RUN->S_DONE
Fvt.state
FfS_RUN
FtS_DONE
htop.TOP' 1
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_state
pagev_fsm_state/$root
ot.state::S_DONE
Fvt.state
FtS_DONE
htop.TOP' 1
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_state
pagev_fsm_state/$root
ot.state::S_ERR
Fvt.state
FtS_ERR
htop.TOP' 0
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_state
pagev_fsm_state/$root
ot.state::S_IDLE
Fvt.state
FtS_IDLE
htop.TOP' 0
+C '
ft/t_cover_fsm_basic.v
l45
n7
tfsm_state
pagev_fsm_state/$root
ot.state::S_RUN
Fvt.state
FtS_RUN
htop.TOP' 1
diff --git a/test_regress/t/t_vlcov_opt_fsm_state.info.out b/test_regress/t/t_vlcov_opt_fsm_state.info.out
new file mode 100644
index 000000000..639a2811b
--- /dev/null
+++ b/test_regress/t/t_vlcov_opt_fsm_state.info.out
@@ -0,0 +1,10 @@
+TN:verilator_coverage
+SF:t/t_cover_fsm_basic.v
+DA:45,1
+BRDA:45,0,t.state::S_DONE,1
+BRDA:45,0,t.state::S_ERR,0
+BRDA:45,0,t.state::S_IDLE,0
+BRDA:45,0,t.state::S_RUN,1
+BRF:4
+BRH:0
+end_of_record
diff --git a/test_regress/t/t_vlcov_opt_fsm_state.py b/test_regress/t/t_vlcov_opt_fsm_state.py
new file mode 100755
index 000000000..facd60aba
--- /dev/null
+++ b/test_regress/t/t_vlcov_opt_fsm_state.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('dist')
+
+test.run(cmd=[
+    os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info",
+    test.obj_dir + "/coverage.info", "--filter-type fsm_state", "t/t_vlcov_data_g.dat"
+],
+         verilator_run=True)
+
+test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out")
+
+test.passes()