Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.

nodist/verilog_format

@@ -12,6 +12,8 @@
 # SPDX-FileCopyrightText: 2026 Wilson Snyder
 # SPDX-License-Identifier: CC0-1.0
 
+# These flags tested against verible-v0.0-4080-ga0a8d8eb
+
 verible-verilog-format \
     --inplace \
     --wrap_end_else_clauses  \

test_regress/t/t_class_imp2.v

@@ -26,7 +26,9 @@ module t;
     virtual function void deliver();
       $display("fast delivery");
     endfunction
-    virtual function int seats(); return 4; endfunction
+    virtual function int seats();
+      return 4;
+    endfunction
   endclass
 
   class MetaCar extends Car;

test_regress/t/t_class_type_param_upcast.v

@@ -6,7 +6,9 @@
 
 // Output arg of class type-parameter accepts a base handle (upcast).
 
-class Fifo #(type T = int);
+class Fifo #(
+    type T = int
+);
   T m_val;
   task get(output T t);
     t = m_val;

test_regress/t/t_constraint_unpacked_array.v

@@ -40,7 +40,8 @@ class con_rand_1d_array_test;
       `check_rand(this, data[i])
       if (data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}) begin
         $display("data[%0d] = %h is valid", i, data[i]);
-      end else begin
+      end
+      else begin
         $display("Error: data[%0d] = %h is out of bounds", i, data[i]);
         $stop;
       end
@@ -70,7 +71,8 @@ class con_rand_2d_array_test;
       `check_rand(this, data[i][j])
       if (data[i][j] >= 8'h10 && data[i][j] <= 8'h50) begin
         $display("data[%0d][%0d] = %h is valid", i, j, data[i][j]);
-      end else begin
+      end
+      else begin
         $display("Error: data[%0d][%0d] = %h is out of bounds", i, j, data[i][j]);
         $stop;
       end

test_regress/t/t_flag_build_jobs_and_j.py

@@ -18,6 +18,6 @@ test.compile(verilator_flags2=[
 
 test.execute()
 
-test.file_grep(test.stats, r'Build jobs: 2')
+test.file_grep(test.stats, r'Build jobs: (\d+)', 2)
 
 test.passes()

test_regress/t/t_for_assign.v

@@ -4,10 +4,10 @@
 // SPDX-FileCopyrightText: 2023 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-// verilog_format: on
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-// verilog_format: off
+// verilog_format: on
 
 module t;
 

test_regress/t/t_opt_gate_blow_up.py

@@ -18,6 +18,6 @@ memUsageMB = int(test.file_grep(test.stats, r'Peak Memory Usage \(MB\) +(\d+)')[
 if memUsageMB > 128 and not test.have_dev_asan:
     test.error("Consumed over 128MB memory")
 
-test.file_grep(test.stats, r'Verilate jobs: 2')
+test.file_grep(test.stats, r'Verilate jobs: (\d+)', 2)
 
 test.passes()

test_regress/t/t_rand_undefined_var.v

@@ -10,9 +10,7 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-typedef struct{
+typedef struct {rand bit [31:0] x;} Bar;
-  rand bit [31:0] x;
-} Bar;
 
 class Foo;
   rand Bar bar0[];

test_regress/t/t_sequence_bool_ops.v

@@ -27,8 +27,7 @@ module t (
 
   always_ff @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
-           $time, cyc, crc, a, b, c, d);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@@ -37,9 +36,11 @@ module t (
     if (cyc == 0) begin
       crc <= 64'h5aef0c8d_d70a4497;
       sum <= '0;
-    end else if (cyc < 10) begin
+    end
+    else if (cyc < 10) begin
       sum <= '0;
-    end else if (cyc == 99) begin
+    end
+    else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkh(sum, 64'hdb7bc8bfe61f987e);
       $write("*-* All Finished *-*\n");

test_regress/t/t_sequence_intersect.v

@@ -26,8 +26,7 @@ module t (
 
   always_ff @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
-           $time, cyc, crc, a, b, c, d);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@@ -36,9 +35,11 @@ module t (
     if (cyc == 0) begin
       crc <= 64'h5aef0c8d_d70a4497;
       sum <= '0;
-    end else if (cyc < 10) begin
+    end
+    else if (cyc < 10) begin
       sum <= '0;
-    end else if (cyc == 99) begin
+    end
+    else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkh(sum, 64'hdb7bc8bfe61f987e);
       $write("*-* All Finished *-*\n");

test_regress/t/t_subclass_nonconstrained_enum.v

@@ -11,18 +11,17 @@
 
 class Sub;
   typedef enum bit [1:0] {
-    one,
+    ONE,
-    two,
+    TWO,
-    three,
+    THREE,
-    four
+    FOUR
   } enum_t;
 
   rand bit num;
   rand enum_t en;
 
-  constraint c {
+  constraint c {num == 0;}
-    num == 0;
+
-  };
 endclass
 
 class Top;

test_regress/t/t_vthread.py

@@ -46,6 +46,6 @@ test.compile(
 
 test.execute()
 
-test.file_grep(test.stats, r'Verilate jobs: 2')
+test.file_grep(test.stats, r'Verilate jobs: (\d+)', 2)
 
 test.passes()