Commentary: Changes update
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Changes
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@ -42,6 +42,7 @@ Verilator 5.047 devel
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* Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
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* Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
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* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
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* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
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* Support property-local variables and sequence match items (#7286). [Yilou Wang]
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* Support property-local variables and sequence match items (#7286). [Yilou Wang]
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* Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
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* Support `##[M:N]` range cycle delay in SVA sequences (#7312). [Yilou Wang]
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* Support `##[M:N]` range cycle delay in SVA sequences (#7312). [Yilou Wang]
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* Support array map() method (#7307) (#7316). [Wei-Lun Chiu]
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* Support array map() method (#7307) (#7316). [Wei-Lun Chiu]
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* Add VPI callback support to --main (#7145).
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* Add VPI callback support to --main (#7145).
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@ -58,9 +59,11 @@ Verilator 5.047 devel
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* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
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* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
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* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
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* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
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* Optimize reuse of existing associative terms in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
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* Optimize reuse of existing associative terms in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
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* Optimize duplicate vertices in DfgPeephole (#7305). [Geza Lore, Testorrent USA, Inc.]
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* Optimize duplicate vertices and multiplexers in DfgPeephole (#7305). [Geza Lore, Testorrent USA, Inc.]
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* Optimize commutative vertex operands in DFG for better combining. [Geza Lore, Testorrent USA, Inc.]
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* Optimize commutative vertex operands in DFG for better combining. [Geza Lore, Testorrent USA, Inc.]
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* Optimize DFG peephole until a fixed point (#7309). [Geza Lore, Testorrent USA, Inc.]
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* Optimize DFG peephole until a fixed point (#7309). [Geza Lore, Testorrent USA, Inc.]
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* Optimize comparisons with identical operands and $countones in DFG. [Geza Lore, Testorrent USA, Inc.]
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* Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.]
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* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
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* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
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* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
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* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
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* Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
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* Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
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@ -102,6 +105,8 @@ Verilator 5.047 devel
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* Fix linking shared library with its dependencies (#7320). [Artur Bieniek, Antmicro Ltd.]
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* Fix linking shared library with its dependencies (#7320). [Artur Bieniek, Antmicro Ltd.]
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* Fix modport selection of virtual interface handle (#7321). [Yilou Wang]
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* Fix modport selection of virtual interface handle (#7321). [Yilou Wang]
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* Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
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* Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
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* Fix static initialization order for packages with class hierarchies (#7324). [Yilou Wang]
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* Fix `disable iff` imply-delay statement linking (#7337). [Nick Brereton]
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Verilator 5.046 2026-02-28
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Verilator 5.046 2026-02-28
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@ -834,6 +834,7 @@ glibc
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gmake
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gmake
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gmon
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gmon
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gotFinish
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gotFinish
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goto
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gprof
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gprof
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gtkwave
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gtkwave
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hdr
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hdr
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@ -4,17 +4,20 @@
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// SPDX-FileCopyrightText: 2026 Eunseo Song
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// SPDX-FileCopyrightText: 2026 Eunseo Song
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// SPDX-License-Identifier: CC0-1.0
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// SPDX-License-Identifier: CC0-1.0
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module top(input clk, input rst, output reg [7:0] count);
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module top (
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always @(posedge clk) begin
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input clk,
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if (rst)
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input rst,
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count <= 0;
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output reg [7:0] count
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else
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);
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count <= count + 1;
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end
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initial begin
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always @(posedge clk) begin
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$display("Hello from t_flag_csplit_pch");
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if (rst) count <= 0;
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$write("*-* All Coverage-Coverage = 1\n");
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else count <= count + 1;
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$finish;
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end
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end
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initial begin
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$display("Hello from t_flag_csplit_pch");
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$write("*-* All Coverage-Coverage = 1\n");
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$finish;
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end
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endmodule
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endmodule
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@ -15,8 +15,8 @@
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package pkg_a;
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package pkg_a;
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typedef enum int {
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typedef enum int {
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STATE_UNINIT = 0,
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STATE_UNINIT = 0,
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STATE_INIT = 1,
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STATE_INIT = 1,
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STATE_DONE = 2
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STATE_DONE = 2
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} state_e;
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} state_e;
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state_e g_state = STATE_UNINIT;
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state_e g_state = STATE_UNINIT;
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