diff --git a/test_regress/t/t_case_66bits.v b/test_regress/t/t_case_66bits.v index 47adab54b..4d29c8425 100644 --- a/test_regress/t/t_case_66bits.v +++ b/test_regress/t/t_case_66bits.v @@ -4,24 +4,22 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [65:0] idx /*verilator public*/; + initial idx = 1; - reg [65:0] idx /*verilator public*/; initial idx = 1; - - always @(posedge clk) begin - case(idx) - 1: idx = 100; - 100: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: $stop; - endcase - end + always @(posedge clk) begin + case (idx) + 1: idx = 100; + 100: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_auto1.v b/test_regress/t/t_case_auto1.v index 4c3350259..1494e693d 100644 --- a/test_regress/t/t_case_auto1.v +++ b/test_regress/t/t_case_auto1.v @@ -4,73 +4,73 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilog_format: off + localparam // synopsys enum En_State + EP_State_IDLE = {3'b000,5'd00}, + EP_State_CMDSHIFT0 = {3'b001,5'd00}, + EP_State_CMDSHIFT13 = {3'b001,5'd13}, + EP_State_CMDSHIFT14 = {3'b001,5'd14}, + EP_State_CMDSHIFT15 = {3'b001,5'd15}, + EP_State_CMDSHIFT16 = {3'b001,5'd16}, + EP_State_DWAIT = {3'b010,5'd00}, + EP_State_DSHIFT0 = {3'b100,5'd00}, + EP_State_DSHIFT1 = {3'b100,5'd01}, + EP_State_DSHIFT15 = {3'b100,5'd15}; - localparam // synopsys enum En_State - EP_State_IDLE = {3'b000,5'd00}, - EP_State_CMDSHIFT0 = {3'b001,5'd00}, - EP_State_CMDSHIFT13 = {3'b001,5'd13}, - EP_State_CMDSHIFT14 = {3'b001,5'd14}, - EP_State_CMDSHIFT15 = {3'b001,5'd15}, - EP_State_CMDSHIFT16 = {3'b001,5'd16}, - EP_State_DWAIT = {3'b010,5'd00}, - EP_State_DSHIFT0 = {3'b100,5'd00}, - EP_State_DSHIFT1 = {3'b100,5'd01}, - EP_State_DSHIFT15 = {3'b100,5'd15}; + reg [7:0] /* synopsys enum En_State */ + m_state_xr; // Last command, for debugging + /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ + // Beginning of automatic ASCII enum decoding + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + always @(m_state_xr) begin + case ({m_state_xr}) + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; + endcase + end + // End of automatics + // verilog_format: on - reg [7:0] /* synopsys enum En_State */ - m_state_xr; // Last command, for debugging - /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ - // Beginning of automatic ASCII enum decoding - reg [79:0] m_stateAscii_xr; // Decode of m_state_xr - always @(m_state_xr) begin - case ({m_state_xr}) - EP_State_IDLE: m_stateAscii_xr = "idle "; - EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; - EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; - EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; - EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; - EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; - EP_State_DWAIT: m_stateAscii_xr = "dwait "; - EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; - EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; - EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; - default: m_stateAscii_xr = "%Error "; - endcase - end - // End of automatics - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - m_state_xr <= EP_State_IDLE; - end - if (cyc==2) begin - if (m_stateAscii_xr != "idle ") $stop; - m_state_xr <= EP_State_CMDSHIFT13; - end - if (cyc==3) begin - if (m_stateAscii_xr != "cmdshift13") $stop; - m_state_xr <= EP_State_CMDSHIFT16; - end - if (cyc==4) begin - if (m_stateAscii_xr != "cmdshift16") $stop; - m_state_xr <= EP_State_DWAIT; - end - if (cyc==9) begin - if (m_stateAscii_xr != "dwait ") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc == 1) begin + m_state_xr <= EP_State_IDLE; end - end + if (cyc == 2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + end + if (cyc == 3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + end + if (cyc == 4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + end + if (cyc == 9) begin + if (m_stateAscii_xr != "dwait ") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_case_call_count.v b/test_regress/t/t_case_call_count.v index 529596992..dc6a896da 100644 --- a/test_regress/t/t_case_call_count.v +++ b/test_regress/t/t_case_call_count.v @@ -8,12 +8,12 @@ class Cls; int callCount = 0; int callCount2 = 0; int value = 6; - bit[5:0] value2 = 6; + bit [5:0] value2 = 6; function int get(); callCount += 1; return value; endfunction - function bit[5:0] get2(); + function bit [5:0] get2(); callCount2 += 1; return value2; endfunction @@ -45,7 +45,7 @@ module t; default: $stop; endcase case (c.getPure()) - 1:; + 1: ; default: $stop; endcase if (!called) $stop; diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v index b844e1d14..cabd1e9bc 100644 --- a/test_regress/t/t_case_deep.v +++ b/test_regress/t/t_case_deep.v @@ -4,90 +4,92 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [33:0] in = crc[33:0]; + // Take CRC data and apply to testblock inputs + wire [33:0] in = crc[33:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] code; // From test of Test.v - wire [4:0] len; // From test of Test.v - wire next; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] code; // From test of Test.v + wire [4:0] len; // From test of Test.v + wire next; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .next (next), - .code (code[31:0]), - .len (len[4:0]), - // Inputs - .clk (clk), - .in (in[33:0])); + Test test ( /*AUTOINST*/ + // Outputs + .next(next), + .code(code[31:0]), + .len(len[4:0]), + // Inputs + .clk(clk), + .in(in[33:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {26'h0, next, len, code}; + // Aggregate outputs into a single result vector + wire [63:0] result = {26'h0, next, len, code}; - // What checksum will we end up with -`define EXPECTED_SUM 64'h5537fa30d49bf865 + // What checksum will we end up with + `define EXPECTED_SUM 64'h5537fa30d49bf865 - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - next, code, len, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + next, + code, + len, + // Inputs + clk, + in +); - input clk; - input [33:0] in; - output next; - output [31:0] code; - output [4:0] len; + input clk; + input [33:0] in; + output next; + output [31:0] code; + output [4:0] len; - /*AUTOREG*/ - // Beginning of automatic regs (for this module's undeclared outputs) - reg [31:0] code; - reg [4:0] len; - reg next; - // End of automatics + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [31:0] code; + reg [4:0] len; + reg next; + // End of automatics -/* + /* #!/usr/bin/env perl use warnings; srand(5); @@ -128,216 +130,216 @@ pat: } */ - always @* begin - next = 1'b0; - code = 32'd0; - len = 5'b11111; - casez (in[31:8]) - 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; - 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; - 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; - 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; - 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; - 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; - 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; - 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; - 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; - 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; - 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; - 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; - 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; - 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; - 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; - 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; - 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; - 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; - 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; - 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; - 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; - 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; - 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; - 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; - 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; - 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; - 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; - 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; - 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; - 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; - 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; - 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; - 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; - 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; - 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; - 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; - 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; - 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; - 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; - 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; - 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; - 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; - 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; - 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; - 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; - 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; - 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; - 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; - 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; - 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; - 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; - 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; - 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; - 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; - 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; - 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; - 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; - 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; - 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; - 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; - 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; - 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; - 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; - 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; - 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; - 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; - 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; - 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; - 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; - 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; - 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; - 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; - 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; - 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; - 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; - 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; - 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; - 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; - 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; - 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; - 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; - 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; - 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; - 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; - 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; - 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; - 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; - 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; - 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; - 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; - 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; - 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; - 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; - 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; - 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; - 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; - 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; - 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; - 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; - 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; - 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; - 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; - 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; - 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; - 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; - 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; - 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; - 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; - 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; - 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; - 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; - 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; - 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; - 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; - 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; - 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; - 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; - 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; - 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; - 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; - 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; - 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; - 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; - 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; - 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; - 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; - 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; - 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; - 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; - 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; - 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; - 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; - 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; - 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; - 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; - 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; - 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; - 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; - 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; - 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; - 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; - 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; - 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; - 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; - 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; - 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; - 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; - 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; - 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; - 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; - 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; - 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; - 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; - 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; - 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; - 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; - 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; - 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; - 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; - 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; - 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; - 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; - 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; - 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; - 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; - 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; - 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; - 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; - 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; - 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; - 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; - 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; - 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; - 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; - 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; - 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; - 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; - 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; - 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; - 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; - 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; - 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; - 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; - 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; - 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; - 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; - 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; - 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; - 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; - 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; - 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; - 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; - 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; - 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; - 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; - 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; - 24'b000000??????????????????: begin - casez (in[33:32]) - 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; - 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; - 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; - default: ; - endcase - end - default: ; - endcase - end + always @* begin + next = 1'b0; + code = 32'd0; + len = 5'b11111; + casez (in[31:8]) + 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; + 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; + 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; + 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; + 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; + 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; + 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; + 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; + 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; + 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; + 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; + 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; + 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; + 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; + 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; + 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; + 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; + 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; + 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; + 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; + 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; + 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; + 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; + 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; + 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; + 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; + 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; + 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; + 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; + 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; + 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; + 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; + 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; + 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; + 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; + 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; + 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; + 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; + 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; + 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; + 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; + 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; + 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; + 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; + 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; + 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; + 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; + 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; + 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; + 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; + 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; + 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; + 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; + 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; + 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; + 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; + 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; + 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; + 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; + 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; + 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; + 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; + 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; + 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; + 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; + 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; + 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; + 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; + 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; + 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; + 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; + 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; + 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; + 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; + 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; + 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; + 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; + 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; + 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; + 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; + 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; + 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; + 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; + 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; + 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; + 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; + 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; + 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; + 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; + 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; + 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; + 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; + 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; + 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; + 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; + 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; + 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; + 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; + 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; + 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; + 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; + 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; + 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; + 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; + 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; + 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; + 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; + 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; + 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; + 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; + 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; + 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; + 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; + 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; + 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; + 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; + 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; + 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; + 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; + 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; + 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; + 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; + 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; + 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; + 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; + 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; + 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; + 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; + 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; + 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; + 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; + 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; + 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; + 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; + 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; + 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; + 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; + 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; + 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; + 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; + 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; + 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; + 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; + 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; + 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; + 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; + 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; + 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; + 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; + 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; + 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; + 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; + 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; + 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; + 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; + 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; + 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; + 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; + 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; + 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; + 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; + 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; + 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; + 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; + 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; + 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; + 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; + 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; + 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; + 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; + 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; + 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; + 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; + 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; + 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; + 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; + 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; + 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; + 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; + 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; + 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; + 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; + 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; + 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; + 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; + 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; + 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; + 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; + 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; + 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; + 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; + 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; + 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; + 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; + 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; + 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; + 24'b000000??????????????????: begin + casez (in[33:32]) + 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; + 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; + 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; + default: ; + endcase + end + default: ; + endcase + end endmodule diff --git a/test_regress/t/t_case_default_bad.out b/test_regress/t/t_case_default_bad.out index 63cb3e614..f50d710a7 100644 --- a/test_regress/t/t_case_default_bad.out +++ b/test_regress/t/t_case_default_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement. - 16 | default: $stop; - | ^~~~~~~ +%Error: t/t_case_default_bad.v:16:7: Multiple default statements in case statement. + 16 | default: $stop; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_case_default_bad.v b/test_regress/t/t_case_default_bad.v index fabed01c3..9bb885465 100644 --- a/test_regress/t/t_case_default_bad.v +++ b/test_regress/t/t_case_default_bad.v @@ -4,16 +4,16 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - value - ); - input [3:0] value; - always @ (/*AS*/value) begin - case (value) - default: $stop; - 4'd0000: $stop; - default: $stop; - endcase - end +module t ( /*AUTOARG*/ + // Inputs + value +); + input [3:0] value; + always @( /*AS*/ value) begin + case (value) + default: $stop; + 4'd0000: $stop; + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v index c608fb470..0eeb2d61e 100644 --- a/test_regress/t/t_case_dupitems.v +++ b/test_regress/t/t_case_dupitems.v @@ -4,78 +4,77 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [1:0] in = crc[1:0]; + // Take CRC data and apply to testblock inputs + wire [1:0] in = crc[1:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[1:0]), - // Inputs - .in (in[1:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[1:0]), + // Inputs + .in(in[1:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {62'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {62'h0, out}; - // What checksum will we end up with -`define EXPECTED_SUM 64'hbb2d9709592f64bd + // What checksum will we end up with + `define EXPECTED_SUM 64'hbb2d9709592f64bd - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); - input [1:0] in; - output reg [1:0] out; - always @* begin - // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? - case (in[1:0]) - 2'd0, 2'd1, 2'd2, 2'd3: begin - out = in; - end - endcase - end +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); + input [1:0] in; + output reg [1:0] out; + always @* begin + // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? + case (in[1:0]) + 2'd0, 2'd1, 2'd2, 2'd3: begin + out = in; + end + endcase + end endmodule diff --git a/test_regress/t/t_case_enum_complete.v b/test_regress/t/t_case_enum_complete.v index 2eb4e94f3..1ab96c131 100644 --- a/test_regress/t/t_case_enum_complete.v +++ b/test_regress/t/t_case_enum_complete.v @@ -6,20 +6,24 @@ module t; - enum logic [2:0] {S0, S1, S2} state; + enum logic [2:0] { + S0, + S1, + S2 + } state; - int v = 0; + int v = 0; - initial begin - state = S1; + initial begin + state = S1; - unique case (state) - S0, S2: $stop; - S1: v++; - endcase - unique case (state) - S2: $stop; - default: v++; - endcase - end + unique case (state) + S0, S2: $stop; + S1: v++; + endcase + unique case (state) + S2: $stop; + default: v++; + endcase + end endmodule diff --git a/test_regress/t/t_case_enum_complete_wildcard.v b/test_regress/t/t_case_enum_complete_wildcard.v index 3cadee7bf..1241241f0 100644 --- a/test_regress/t/t_case_enum_complete_wildcard.v +++ b/test_regress/t/t_case_enum_complete_wildcard.v @@ -8,67 +8,67 @@ module t; - enum logic [1:0] { - S00 = 'b00, - S01 = 'b01, - S10 = 'b10, + enum logic [1:0] { + S00 = 'b00, + S01 = 'b01, + S10 = 'b10, - S0X = 2'b0?, - SX0 = 2'b?0 - } state; + S0X = 2'b0?, + SX0 = 2'b?0 + } state; - int v = 0; + int v = 0; - initial begin - state = S01; - unique case (state) - S00: $stop; - S01: v++; - S10: $stop; - endcase - unique case (state) - S00: $stop; - default: v++; // default - endcase - unique case (state) - 2'd0: $stop; - 2'd1: v++; - 2'd2: $stop; - endcase - unique case (state) - 2'd0: $stop; - 2'd1: v++; - 2'd2: $stop; - 2'd3: $stop; // extra case - endcase + initial begin + state = S01; + unique case (state) + S00: $stop; + S01: v++; + S10: $stop; + endcase + unique case (state) + S00: $stop; + default: v++; // default + endcase + unique case (state) + 2'd0: $stop; + 2'd1: v++; + 2'd2: $stop; + endcase + unique case (state) + 2'd0: $stop; + 2'd1: v++; + 2'd2: $stop; + 2'd3: $stop; // extra case + endcase - unique case (state) inside - 2'd0: $stop; - 2'd1: v++; - [2'd2:2'd3]: $stop; - endcase - unique case (state) inside - [S00:S10]: v++; - endcase + unique case (state) inside + 2'd0: $stop; + 2'd1: v++; + [2'd2 : 2'd3]: $stop; + endcase + unique case (state) inside + [S00 : S10]: v++; + endcase - unique casez (state) - S10: $stop; - S0X: v++; // fully covered - endcase - unique casez (state) - S10: $stop; - S0X: v++; - 2'b11: $stop; // extra case - endcase - unique casez (state) - S0X: v++; - default: $stop; - endcase + unique casez (state) + S10: $stop; + S0X: v++; // fully covered + endcase + unique casez (state) + S10: $stop; + S0X: v++; + 2'b11: $stop; // extra case + endcase + unique casez (state) + S0X: v++; + default: $stop; + endcase - case (state) - S00: $stop; - S01: v++; - S10, 2'b11: $stop; - endcase - end + case (state) + S00: $stop; + S01: v++; + S10, 2'b11: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_enum_emptyish.v b/test_regress/t/t_case_enum_emptyish.v index f637a6b33..e4c1628ef 100644 --- a/test_regress/t/t_case_enum_emptyish.v +++ b/test_regress/t/t_case_enum_emptyish.v @@ -6,24 +6,24 @@ module t; - enum logic [2:0] { - e0, - e1, - e2, - e3 - } EN; + enum logic [2:0] { + e0, + e1, + e2, + e3 + } EN; - initial begin + initial begin - unique case (EN) - e0 :; - e1 :; - e2 :; - e3 :; - endcase + unique case (EN) + e0: ; + e1: ; + e2: ; + e3: ; + endcase - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_case_enum_incomplete_bad.out b/test_regress/t/t_case_enum_incomplete_bad.out index f7713d73b..6fa08e122 100644 --- a/test_regress/t/t_case_enum_incomplete_bad.out +++ b/test_regress/t/t_case_enum_incomplete_bad.out @@ -1,6 +1,6 @@ -%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:14:14: Enum item 'S1' not covered by case - 14 | unique case (state) - | ^~~~ +%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:18:12: Enum item 'S1' not covered by case + 18 | unique case (state) + | ^~~~ ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_case_enum_incomplete_bad.v b/test_regress/t/t_case_enum_incomplete_bad.v index 9c8e8395f..d5d4dabab 100644 --- a/test_regress/t/t_case_enum_incomplete_bad.v +++ b/test_regress/t/t_case_enum_incomplete_bad.v @@ -6,14 +6,18 @@ module t; - enum logic [2:0] {S0, S1, S2} state; + enum logic [2:0] { + S0, + S1, + S2 + } state; - initial begin - state = S1; + initial begin + state = S1; - unique case (state) - S0: $stop; - S2: $stop; - endcase - end + unique case (state) + S0: $stop; + S2: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.out b/test_regress/t/t_case_enum_incomplete_wildcard_bad.out index 18337e745..289933112 100644 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.out +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.out @@ -1,15 +1,15 @@ -%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:26:16: Enum item 'S10' not covered by case - 26 | unique case (state) - | ^~~~ +%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:26:12: Enum item 'S10' not covered by case + 26 | unique case (state) + | ^~~~ ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. -%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:30:16: Enum item 'S00' not covered by case - 30 | unique case (state) - | ^~~~ -%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:35:16: Enum item 'S10' not covered by case - 35 | unique casez (state) - | ^~~~~ -%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:40:9: Case values incompletely covered (example pattern 0x3) - 40 | case (state) - | ^~~~ +%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:30:12: Enum item 'S00' not covered by case + 30 | unique case (state) + | ^~~~ +%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:35:12: Enum item 'S10' not covered by case + 35 | unique casez (state) + | ^~~~~ +%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:40:5: Case values incompletely covered (example pattern 0x3) + 40 | case (state) + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.v b/test_regress/t/t_case_enum_incomplete_wildcard_bad.v index 874eb2fa8..2c66010f9 100644 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.v +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.v @@ -5,42 +5,42 @@ // SPDX-License-Identifier: CC0-1.0 module t; - t1 i_t1(); + t1 i_t1 (); endmodule module t1; - enum logic [1:0] { - S00 = 'b00, - S01 = 'b01, - S10 = 'b10, + enum logic [1:0] { + S00 = 'b00, + S01 = 'b01, + S10 = 'b10, - SX0 = 2'b?0, - S0X = 'b0? - } state; + SX0 = 2'b?0, + S0X = 'b0? + } state; - int v = 0; + int v = 0; - initial begin - state = S10; - unique case (state) - S00: $stop; - 2'b01: $stop; - endcase - unique case (state) - 2'd2: v++; - 2'd1: $stop; - endcase + initial begin + state = S10; + unique case (state) + S00: $stop; + 2'b01: $stop; + endcase + unique case (state) + 2'd2: v++; + 2'd1: $stop; + endcase - unique casez (state) - S0X: $stop; - 2'b11: $stop; - endcase + unique casez (state) + S0X: $stop; + 2'b11: $stop; + endcase - case (state) - S00: $stop; - S01: $stop; - S10: v++; - endcase - end + case (state) + S00: $stop; + S01: $stop; + S10: v++; + endcase + end endmodule diff --git a/test_regress/t/t_case_group.v b/test_regress/t/t_case_group.v index e69495511..255600f6b 100644 --- a/test_regress/t/t_case_group.v +++ b/test_regress/t/t_case_group.v @@ -4,23 +4,21 @@ // SPDX-FileCopyrightText: 2014 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 -module t - ( - input i_clk, - input [6:0] i_input, - output logic o_output - ); +module t ( + input i_clk, + input [6:0] i_input, + output logic o_output +); - always_ff @(posedge i_clk) - // verilator lint_off CASEINCOMPLETE - case (i_input) - 7'(92+2), - 7'(92+3): o_output <= 1'b1; - endcase + always_ff @(posedge i_clk) + // verilator lint_off CASEINCOMPLETE + case (i_input) + 7'(92 + 2), 7'(92 + 3): o_output <= 1'b1; + endcase - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_case_huge.v b/test_regress/t/t_case_huge.v index cbdc93964..0a0922f76 100644 --- a/test_regress/t/t_case_huge.v +++ b/test_regress/t/t_case_huge.v @@ -4,207 +4,208 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk + ); - input clk; + input clk; - reg [9:0] index; - wire [7:0] index0 = index[7:0] + 8'h0; - wire [7:0] index1 = index[7:0] + 8'h1; - wire [7:0] index2 = index[7:0] + 8'h2; - wire [7:0] index3 = index[7:0] + 8'h3; - wire [7:0] index4 = index[7:0] + 8'h4; - wire [7:0] index5 = index[7:0] + 8'h5; - wire [7:0] index6 = index[7:0] + 8'h6; - wire [7:0] index7 = index[7:0] + 8'h7; + reg [9:0] index; + wire [7:0] index0 = index[7:0] + 8'h0; + wire [7:0] index1 = index[7:0] + 8'h1; + wire [7:0] index2 = index[7:0] + 8'h2; + wire [7:0] index3 = index[7:0] + 8'h3; + wire [7:0] index4 = index[7:0] + 8'h4; + wire [7:0] index5 = index[7:0] + 8'h5; + wire [7:0] index6 = index[7:0] + 8'h6; + wire [7:0] index7 = index[7:0] + 8'h7; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [9:0] outa0; // From s0 of t_case_huge_sub.v - wire [9:0] outa1; // From s1 of t_case_huge_sub.v - wire [9:0] outa2; // From s2 of t_case_huge_sub.v - wire [9:0] outa3; // From s3 of t_case_huge_sub.v - wire [9:0] outa4; // From s4 of t_case_huge_sub.v - wire [9:0] outa5; // From s5 of t_case_huge_sub.v - wire [9:0] outa6; // From s6 of t_case_huge_sub.v - wire [9:0] outa7; // From s7 of t_case_huge_sub.v - wire [1:0] outb0; // From s0 of t_case_huge_sub.v - wire [1:0] outb1; // From s1 of t_case_huge_sub.v - wire [1:0] outb2; // From s2 of t_case_huge_sub.v - wire [1:0] outb3; // From s3 of t_case_huge_sub.v - wire [1:0] outb4; // From s4 of t_case_huge_sub.v - wire [1:0] outb5; // From s5 of t_case_huge_sub.v - wire [1:0] outb6; // From s6 of t_case_huge_sub.v - wire [1:0] outb7; // From s7 of t_case_huge_sub.v - wire outc0; // From s0 of t_case_huge_sub.v - wire outc1; // From s1 of t_case_huge_sub.v - wire outc2; // From s2 of t_case_huge_sub.v - wire outc3; // From s3 of t_case_huge_sub.v - wire outc4; // From s4 of t_case_huge_sub.v - wire outc5; // From s5 of t_case_huge_sub.v - wire outc6; // From s6 of t_case_huge_sub.v - wire outc7; // From s7 of t_case_huge_sub.v - wire [9:0] outq; // From q of t_case_huge_sub4.v - wire [3:0] outr; // From sub3 of t_case_huge_sub3.v - wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [9:0] outa0; // From s0 of t_case_huge_sub.v + logic [9:0] outa1; // From s1 of t_case_huge_sub.v + logic [9:0] outa2; // From s2 of t_case_huge_sub.v + logic [9:0] outa3; // From s3 of t_case_huge_sub.v + logic [9:0] outa4; // From s4 of t_case_huge_sub.v + logic [9:0] outa5; // From s5 of t_case_huge_sub.v + logic [9:0] outa6; // From s6 of t_case_huge_sub.v + logic [9:0] outa7; // From s7 of t_case_huge_sub.v + logic [1:0] outb0; // From s0 of t_case_huge_sub.v + logic [1:0] outb1; // From s1 of t_case_huge_sub.v + logic [1:0] outb2; // From s2 of t_case_huge_sub.v + logic [1:0] outb3; // From s3 of t_case_huge_sub.v + logic [1:0] outb4; // From s4 of t_case_huge_sub.v + logic [1:0] outb5; // From s5 of t_case_huge_sub.v + logic [1:0] outb6; // From s6 of t_case_huge_sub.v + logic [1:0] outb7; // From s7 of t_case_huge_sub.v + logic outc0; // From s0 of t_case_huge_sub.v + logic outc1; // From s1 of t_case_huge_sub.v + logic outc2; // From s2 of t_case_huge_sub.v + logic outc3; // From s3 of t_case_huge_sub.v + logic outc4; // From s4 of t_case_huge_sub.v + logic outc5; // From s5 of t_case_huge_sub.v + logic outc6; // From s6 of t_case_huge_sub.v + logic outc7; // From s7 of t_case_huge_sub.v + logic [9:0] outq; // From q of t_case_huge_sub4.v + logic [3:0] outr; // From sub3 of t_case_huge_sub3.v + logic [9:0] outsmall; // From sub2 of t_case_huge_sub2.v + // End of automatics - t_case_huge_sub2 sub2 ( - // Outputs - .outa (outsmall[9:0]), - /*AUTOINST*/ - // Inputs - .index (index[9:0])); + t_case_huge_sub2 sub2 ( + // Outputs + .outa(outsmall[9:0]), + /*AUTOINST*/ + // Inputs + .index (index[9:0])); - t_case_huge_sub3 sub3 (/*AUTOINST*/ - // Outputs - .outr (outr[3:0]), - // Inputs - .clk (clk), - .index (index[9:0])); + t_case_huge_sub3 sub3 ( /*AUTOINST*/ + // Outputs + .outr (outr[3:0]), + // Inputs + .clk (clk), + .index (index[9:0])); - /* t_case_huge_sub AUTO_TEMPLATE ( + /* t_case_huge_sub AUTO_TEMPLATE ( .outa (outa@[]), .outb (outb@[]), .outc (outc@[]), .index (index@[])); */ - t_case_huge_sub s0 (/*AUTOINST*/ - // Outputs - .outa (outa0[9:0]), // Templated - .outb (outb0[1:0]), // Templated - .outc (outc0), // Templated - // Inputs - .index (index0[7:0])); // Templated - t_case_huge_sub s1 (/*AUTOINST*/ - // Outputs - .outa (outa1[9:0]), // Templated - .outb (outb1[1:0]), // Templated - .outc (outc1), // Templated - // Inputs - .index (index1[7:0])); // Templated - t_case_huge_sub s2 (/*AUTOINST*/ - // Outputs - .outa (outa2[9:0]), // Templated - .outb (outb2[1:0]), // Templated - .outc (outc2), // Templated - // Inputs - .index (index2[7:0])); // Templated - t_case_huge_sub s3 (/*AUTOINST*/ - // Outputs - .outa (outa3[9:0]), // Templated - .outb (outb3[1:0]), // Templated - .outc (outc3), // Templated - // Inputs - .index (index3[7:0])); // Templated - t_case_huge_sub s4 (/*AUTOINST*/ - // Outputs - .outa (outa4[9:0]), // Templated - .outb (outb4[1:0]), // Templated - .outc (outc4), // Templated - // Inputs - .index (index4[7:0])); // Templated - t_case_huge_sub s5 (/*AUTOINST*/ - // Outputs - .outa (outa5[9:0]), // Templated - .outb (outb5[1:0]), // Templated - .outc (outc5), // Templated - // Inputs - .index (index5[7:0])); // Templated - t_case_huge_sub s6 (/*AUTOINST*/ - // Outputs - .outa (outa6[9:0]), // Templated - .outb (outb6[1:0]), // Templated - .outc (outc6), // Templated - // Inputs - .index (index6[7:0])); // Templated - t_case_huge_sub s7 (/*AUTOINST*/ - // Outputs - .outa (outa7[9:0]), // Templated - .outb (outb7[1:0]), // Templated - .outc (outc7), // Templated - // Inputs - .index (index7[7:0])); // Templated + t_case_huge_sub s0 ( /*AUTOINST*/ + // Outputs + .outa (outa0[9:0]), // Templated + .outb (outb0[1:0]), // Templated + .outc (outc0), // Templated + // Inputs + .index (index0[7:0])); // Templated + t_case_huge_sub s1 ( /*AUTOINST*/ + // Outputs + .outa (outa1[9:0]), // Templated + .outb (outb1[1:0]), // Templated + .outc (outc1), // Templated + // Inputs + .index (index1[7:0])); // Templated + t_case_huge_sub s2 ( /*AUTOINST*/ + // Outputs + .outa (outa2[9:0]), // Templated + .outb (outb2[1:0]), // Templated + .outc (outc2), // Templated + // Inputs + .index (index2[7:0])); // Templated + t_case_huge_sub s3 ( /*AUTOINST*/ + // Outputs + .outa (outa3[9:0]), // Templated + .outb (outb3[1:0]), // Templated + .outc (outc3), // Templated + // Inputs + .index (index3[7:0])); // Templated + t_case_huge_sub s4 ( /*AUTOINST*/ + // Outputs + .outa (outa4[9:0]), // Templated + .outb (outb4[1:0]), // Templated + .outc (outc4), // Templated + // Inputs + .index (index4[7:0])); // Templated + t_case_huge_sub s5 ( /*AUTOINST*/ + // Outputs + .outa (outa5[9:0]), // Templated + .outb (outb5[1:0]), // Templated + .outc (outc5), // Templated + // Inputs + .index (index5[7:0])); // Templated + t_case_huge_sub s6 ( /*AUTOINST*/ + // Outputs + .outa (outa6[9:0]), // Templated + .outb (outb6[1:0]), // Templated + .outc (outc6), // Templated + // Inputs + .index (index6[7:0])); // Templated + t_case_huge_sub s7 ( /*AUTOINST*/ + // Outputs + .outa (outa7[9:0]), // Templated + .outb (outb7[1:0]), // Templated + .outc (outc7), // Templated + // Inputs + .index (index7[7:0])); // Templated - t_case_huge_sub4 q (/*AUTOINST*/ - // Outputs - .outq (outq[9:0]), - // Inputs - .index (index[7:0])); + t_case_huge_sub4 q ( /*AUTOINST*/ + // Outputs + .outq (outq[9:0]), + // Inputs + .index (index[7:0])); - integer cyc; initial cyc=1; - initial index = 10'h0; + integer cyc; + initial cyc = 1; + initial index = 10'h0; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%x: %x\n",cyc,outr); - //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); - if (cyc==1) begin - index <= 10'h236; - end - if (cyc==2) begin - index <= 10'h022; - if (outsmall != 10'h282) $stop; - if (outr != 4'b0) $stop; - if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; - if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; - if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; - if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; - if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; - if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==3) begin - index <= 10'h165; - if (outsmall != 10'h191) $stop; - if (outr != 4'h5) $stop; - if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; - if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; - if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; - if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; - if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==4) begin - index <= 10'h201; - if (outsmall != 10'h268) $stop; - if (outr != 4'h2) $stop; - if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; - if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; - if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; - if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; - if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==5) begin - index <= 10'h3ff; - if (outr != 4'hd) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==6) begin - index <= 10'h0; - if (outr != 4'hd) $stop; - if (outq != 10'h114) $stop; - end - if (cyc==7) begin - if (outr != 4'h4) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%x: %x\n",cyc,outr); + //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); + if (cyc == 1) begin + index <= 10'h236; end - end + if (cyc == 2) begin + index <= 10'h022; + if (outsmall != 10'h282) $stop; + if (outr != 4'b0) $stop; + if ({outa0, outb0, outc0} != {10'h282, 2'd3, 1'b0}) $stop; + if ({outa1, outb1, outc1} != {10'h21c, 2'd3, 1'b1}) $stop; + if ({outa2, outb2, outc2} != {10'h148, 2'd0, 1'b1}) $stop; + if ({outa3, outb3, outc3} != {10'h3c0, 2'd2, 1'b0}) $stop; + if ({outa4, outb4, outc4} != {10'h176, 2'd1, 1'b1}) $stop; + if ({outa5, outb5, outc5} != {10'h3fc, 2'd2, 1'b1}) $stop; + if ({outa6, outb6, outc6} != {10'h295, 2'd3, 1'b1}) $stop; + if ({outa7, outb7, outc7} != {10'h113, 2'd2, 1'b1}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc == 3) begin + index <= 10'h165; + if (outsmall != 10'h191) $stop; + if (outr != 4'h5) $stop; + if ({outa1, outb1, outc1} != {10'h379, 2'd1, 1'b0}) $stop; + if ({outa2, outb2, outc2} != {10'h073, 2'd0, 1'b0}) $stop; + if ({outa3, outb3, outc3} != {10'h2fd, 2'd3, 1'b1}) $stop; + if ({outa4, outb4, outc4} != {10'h2e0, 2'd3, 1'b1}) $stop; + if ({outa5, outb5, outc5} != {10'h337, 2'd1, 1'b1}) $stop; + if ({outa6, outb6, outc6} != {10'h2c7, 2'd3, 1'b1}) $stop; + if ({outa7, outb7, outc7} != {10'h19e, 2'd3, 1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc == 4) begin + index <= 10'h201; + if (outsmall != 10'h268) $stop; + if (outr != 4'h2) $stop; + if ({outa1, outb1, outc1} != {10'h111, 2'd1, 1'b0}) $stop; + if ({outa2, outb2, outc2} != {10'h1f9, 2'd0, 1'b0}) $stop; + if ({outa3, outb3, outc3} != {10'h232, 2'd0, 1'b1}) $stop; + if ({outa4, outb4, outc4} != {10'h255, 2'd3, 1'b0}) $stop; + if ({outa5, outb5, outc5} != {10'h34c, 2'd1, 1'b1}) $stop; + if ({outa6, outb6, outc6} != {10'h049, 2'd1, 1'b1}) $stop; + if ({outa7, outb7, outc7} != {10'h197, 2'd3, 1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc == 5) begin + index <= 10'h3ff; + if (outr != 4'hd) $stop; + if (outq != 10'h001) $stop; + end + if (cyc == 6) begin + index <= 10'h0; + if (outr != 4'hd) $stop; + if (outq != 10'h114) $stop; + end + if (cyc == 7) begin + if (outr != 4'h4) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index 2d95aeb1a..2c7c98237 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -4,12 +4,14 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_case_huge_sub (/*AUTOARG*/ - // Outputs - outa, outb, outc, - // Inputs - index - ); +module t_case_huge_sub ( /*AUTOARG*/ + // Outputs + outa, + outb, + outc, + // Inputs + index +); input [7:0] index; output logic [9:0] outa; diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v index bb6305ce3..2cf62c212 100644 --- a/test_regress/t/t_case_inside.v +++ b/test_regress/t/t_case_inside.v @@ -4,64 +4,71 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - reg out1; - reg [4:0] out2; - sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); + reg out1; + reg [4:0] out2; + sub sub ( + .in(crc[23:0]), + .out1(out1), + .out2(out2) + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2); + $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], + out1, out2); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; - if (cyc==0) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); -`define EXPECTED_SUM 64'h10204fa5567c8a4b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {58'h0, out1, out2}; + if (cyc == 0) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + `define EXPECTED_SUM 64'h10204fa5567c8a4b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub (/*AUTOARG*/ - // Outputs - out1, out2, - // Inputs - in - ); +module sub ( /*AUTOARG*/ + // Outputs + out1, + out2, + // Inputs + in +); - input [23:0] in; - output reg out1; - output reg [4:0] out2; + input [23:0] in; + output reg out1; + output reg [4:0] out2; - always @* begin - case (in[3:0]) inside - default {out1,out2} = {1'b0,5'h0F}; // Note not last item, no : to cover parser - 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; - 4'h4: {out1,out2} = {1'b1,5'h04}; - [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match - 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; - [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; - endcase - end + always @* begin + case (in[3:0]) inside + default {out1, out2} = {1'b0, 5'h0F}; // Note not last item, no : to cover parser + 4'h1, 4'h2, 4'h3: {out1, out2} = {1'b1, 5'h01}; + 4'h4: {out1, out2} = {1'b1, 5'h04}; + [4'h6 : 4'h5]: {out1, out2} = {1'b1, 5'h05}; // order backwards, will not match + 4'b100?: /*8,9*/{out1, out2} = {1'b1, 5'h08}; + [4'hc : 4'hf]: {out1, out2} = {1'b1, 5'h0C}; + endcase + end endmodule diff --git a/test_regress/t/t_case_inside_bad.out b/test_regress/t/t_case_inside_bad.out index f124f4689..7af227082 100644 --- a/test_regress/t/t_case_inside_bad.out +++ b/test_regress/t/t_case_inside_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_case_inside_bad.v:9:20: Illegal to have inside on a casex/casez - 9 | casex (1'bx) inside - | ^~~~~~ +%Error: t/t_case_inside_bad.v:9:18: Illegal to have inside on a casex/casez + 9 | casex (1'bx) inside + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_case_inside_bad.v b/test_regress/t/t_case_inside_bad.v index f653c84e1..e21d0272f 100644 --- a/test_regress/t/t_case_inside_bad.v +++ b/test_regress/t/t_case_inside_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - casex (1'bx) inside - default: $stop; - endcase - end + initial begin + casex (1'bx) inside + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_itemwidth.v b/test_regress/t/t_case_itemwidth.v index 0c0f16451..4c2b5575a 100644 --- a/test_regress/t/t_case_itemwidth.v +++ b/test_regress/t/t_case_itemwidth.v @@ -4,117 +4,117 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // Some inputs we'll set to random values + reg [6:0] addr; + reg [6:0] e0; + reg [5:0] e1; + reg [5:0] e2; - // Some inputs we'll set to random values - reg [6:0] addr; - reg [6:0] e0; - reg [5:0] e1; - reg [5:0] e2; + wire [7:0] data; + reg [2:0] wrapcheck_a; + reg [2:0] wrapcheck_b; - wire [7:0] data; - reg [2:0] wrapcheck_a; - reg [2:0] wrapcheck_b; + test test ( /*AUTOINST*/ + // Outputs + .data(data[7:0]), + // Inputs + .addr(addr[6:0]), + .e0(e0[6:0]), + .e1(e1[5:0]), + .e2(e2[5:0]) + ); - test test (/*AUTOINST*/ - // Outputs - .data (data[7:0]), - // Inputs - .addr (addr[6:0]), - .e0 (e0[6:0]), - .e1 (e1[5:0]), - .e2 (e2[5:0])); + always @( /*AS*/ addr) begin + case (addr[2:0]) + 3'd0 + 3'd0: wrapcheck_a = 3'h0; + 3'd0 + 3'd1: wrapcheck_a = 3'h1; + 3'd0 + 3'd2: wrapcheck_a = 3'h2; + 3'd0 + 3'd3: wrapcheck_a = 3'h3; + default: wrapcheck_a = 3'h4; + endcase - always @(/*AS*/addr) begin - case(addr[2:0]) - 3'd0+3'd0: wrapcheck_a = 3'h0; - 3'd0+3'd1: wrapcheck_a = 3'h1; - 3'd0+3'd2: wrapcheck_a = 3'h2; - 3'd0+3'd3: wrapcheck_a = 3'h3; - default: wrapcheck_a = 3'h4; - endcase + case (addr[2:0]) + 3'd0 + 0: wrapcheck_b = 3'h0; + 3'd1 + 1: wrapcheck_b = 3'h1; + 3'd2 + 2: wrapcheck_b = 3'h2; + 3'd3 + 3: wrapcheck_b = 3'h3; + default: wrapcheck_b = 3'h4; + endcase + end - case(addr[2:0]) - 3'd0+0: wrapcheck_b = 3'h0; - 3'd1+1: wrapcheck_b = 3'h1; - 3'd2+2: wrapcheck_b = 3'h2; - 3'd3+3: wrapcheck_b = 3'h3; - default: wrapcheck_b = 3'h4; - endcase - end - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - addr <= 7'h28; - e0 <= 7'h11; - e1 <= 6'h02; - e2 <= 6'h03; - end - if (cyc==2) begin - addr <= 7'h2b; - if (data != 8'h11) $stop; - end - if (cyc==3) begin - addr <= 7'h2c; - if (data != 8'h03) $stop; - if (wrapcheck_a != 3'h3) $stop; - if (wrapcheck_b != 3'h4) $stop; - end - if (cyc==4) begin - addr <= 7'h0; - if (data != 8'h00) $stop; - if (wrapcheck_a != 3'h4) $stop; - if (wrapcheck_b != 3'h2) $stop; - end - if (cyc==5) begin - if (data != 8'h00) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc == 1) begin + addr <= 7'h28; + e0 <= 7'h11; + e1 <= 6'h02; + e2 <= 6'h03; end - end + if (cyc == 2) begin + addr <= 7'h2b; + if (data != 8'h11) $stop; + end + if (cyc == 3) begin + addr <= 7'h2c; + if (data != 8'h03) $stop; + if (wrapcheck_a != 3'h3) $stop; + if (wrapcheck_b != 3'h4) $stop; + end + if (cyc == 4) begin + addr <= 7'h0; + if (data != 8'h00) $stop; + if (wrapcheck_a != 3'h4) $stop; + if (wrapcheck_b != 3'h2) $stop; + end + if (cyc == 5) begin + if (data != 8'h00) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule /* verilator lint_off WIDTH */ -`define AI 7'h28 +`define AI 7'h28 -module test (/*AUTOARG*/ - // Outputs - data, - // Inputs - addr, e0, e1, e2 - ); +module test ( /*AUTOARG*/ + // Outputs + data, + // Inputs + addr, + e0, + e1, + e2 +); - output [7:0] data; + output [7:0] data; - input [6:0] addr; - input [6:0] e0; - input [5:0] e1, e2; + input [6:0] addr; + input [6:0] e0; + input [5:0] e1, e2; - reg [7:0] data; + reg [7:0] data; - always @(/*AS*/addr or e0 or e1 or e2) - begin - case (addr) - `AI: data = {e0[6], 1'b0, e0[5:0]}; - `AI+1: data = e1; - `AI+2, - `AI+3: data = e2; - default: data = 0; - endcase - end + always @( /*AS*/ addr or e0 or e1 or e2) begin + case (addr) + `AI: data = {e0[6], 1'b0, e0[5:0]}; + `AI + 1: data = e1; + `AI + 2, `AI + 3: data = e2; + default: data = 0; + endcase + end endmodule diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v index 55d6d2171..905b39d61 100644 --- a/test_regress/t/t_case_nest.v +++ b/test_regress/t/t_case_nest.v @@ -4,108 +4,114 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + reg out1; + sub sub ( + .in(crc[23:0]), + .out1(out1) + ); - reg out1; - sub sub (.in(crc[23:0]), .out1(out1)); - - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1); + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; - if (cyc==1) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; - end - else if (cyc==90) begin - if (sum !== 64'h2e5cb972eb02b8a0) $stop; - end - else if (cyc==91) begin - end - else if (cyc==92) begin - end - else if (cyc==93) begin - end - else if (cyc==94) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {63'h0, out1}; + if (cyc == 1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc == 90) begin + if (sum !== 64'h2e5cb972eb02b8a0) $stop; + end + else if (cyc == 91) begin + end + else if (cyc == 92) begin + end + else if (cyc == 93) begin + end + else if (cyc == 94) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub (/*AUTOARG*/ - // Outputs - out1, - // Inputs - in - ); +module sub ( /*AUTOARG*/ + // Outputs + out1, + // Inputs + in +); - input [23:0] in; - output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal + input [23:0] in; + output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal - parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; + parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; - always @* begin - casez (in[17:16]) - 2'b00: casez (in[2:0]) - 3'h0: out1[0] = in[0]^RANDOM[0]; - 3'h1: out1[0] = in[0]^RANDOM[1]; - 3'h2: out1[0] = in[0]^RANDOM[2]; - 3'h3: out1[0] = in[0]^RANDOM[3]; - 3'h4: out1[0] = in[0]^RANDOM[4]; - 3'h5: out1[0] = in[0]^RANDOM[5]; - 3'h6: out1[0] = in[0]^RANDOM[6]; - 3'h7: out1[0] = in[0]^RANDOM[7]; - endcase - 2'b01: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[10]; - 3'h1: out1[0] = RANDOM[11]; - 3'h2: out1[0] = RANDOM[12]; - 3'h3: out1[0] = RANDOM[13]; - 3'h4: out1[0] = RANDOM[14]; - 3'h5: out1[0] = RANDOM[15]; - 3'h6: out1[0] = RANDOM[16]; - 3'h7: out1[0] = RANDOM[17]; - endcase - 2'b1?: casez (in[4]) - 1'b1: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[20]; - 3'h1: out1[0] = RANDOM[21]; - 3'h2: out1[0] = RANDOM[22]; - 3'h3: out1[0] = RANDOM[23]; - 3'h4: out1[0] = RANDOM[24]; - 3'h5: out1[0] = RANDOM[25]; - 3'h6: out1[0] = RANDOM[26]; - 3'h7: out1[0] = RANDOM[27]; - endcase - 1'b0: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[30]; - 3'h1: out1[0] = RANDOM[31]; - 3'h2: out1[0] = RANDOM[32]; - 3'h3: out1[0] = RANDOM[33]; - 3'h4: out1[0] = RANDOM[34]; - 3'h5: out1[0] = RANDOM[35]; - 3'h6: out1[0] = RANDOM[36]; - 3'h7: out1[0] = RANDOM[37]; - endcase - endcase + always @* begin + casez (in[17:16]) + 2'b00: + casez (in[2:0]) + 3'h0: out1[0] = in[0] ^ RANDOM[0]; + 3'h1: out1[0] = in[0] ^ RANDOM[1]; + 3'h2: out1[0] = in[0] ^ RANDOM[2]; + 3'h3: out1[0] = in[0] ^ RANDOM[3]; + 3'h4: out1[0] = in[0] ^ RANDOM[4]; + 3'h5: out1[0] = in[0] ^ RANDOM[5]; + 3'h6: out1[0] = in[0] ^ RANDOM[6]; + 3'h7: out1[0] = in[0] ^ RANDOM[7]; endcase - end + 2'b01: + casez (in[2:0]) + 3'h0: out1[0] = RANDOM[10]; + 3'h1: out1[0] = RANDOM[11]; + 3'h2: out1[0] = RANDOM[12]; + 3'h3: out1[0] = RANDOM[13]; + 3'h4: out1[0] = RANDOM[14]; + 3'h5: out1[0] = RANDOM[15]; + 3'h6: out1[0] = RANDOM[16]; + 3'h7: out1[0] = RANDOM[17]; + endcase + 2'b1?: + casez (in[4]) + 1'b1: + casez (in[2:0]) + 3'h0: out1[0] = RANDOM[20]; + 3'h1: out1[0] = RANDOM[21]; + 3'h2: out1[0] = RANDOM[22]; + 3'h3: out1[0] = RANDOM[23]; + 3'h4: out1[0] = RANDOM[24]; + 3'h5: out1[0] = RANDOM[25]; + 3'h6: out1[0] = RANDOM[26]; + 3'h7: out1[0] = RANDOM[27]; + endcase + 1'b0: + casez (in[2:0]) + 3'h0: out1[0] = RANDOM[30]; + 3'h1: out1[0] = RANDOM[31]; + 3'h2: out1[0] = RANDOM[32]; + 3'h3: out1[0] = RANDOM[33]; + 3'h4: out1[0] = RANDOM[34]; + 3'h5: out1[0] = RANDOM[35]; + 3'h6: out1[0] = RANDOM[36]; + 3'h7: out1[0] = RANDOM[37]; + endcase + endcase + endcase + end endmodule diff --git a/test_regress/t/t_case_onehot.v b/test_regress/t/t_case_onehot.v index 817e1eb8f..3a27f248e 100644 --- a/test_regress/t/t_case_onehot.v +++ b/test_regress/t/t_case_onehot.v @@ -4,93 +4,91 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [2:0] in = (crc[1:0]==0 ? 3'd0 - : crc[1:0]==0 ? 3'd1 - : crc[1:0]==0 ? 3'd2 : 3'd4); + // Take CRC data and apply to testblock inputs + wire [2:0] in = (crc[1:0] == 0 ? 3'd0 : crc[1:0] == 0 ? 3'd1 : crc[1:0] == 0 ? 3'd2 : 3'd4); - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[2:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[31:0]), + // Inputs + .clk(clk), + .in(in[2:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h704ca23e2a83e1c5 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h704ca23e2a83e1c5 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - // Replace this module with the device under test. - // - // Change the code in the t module to apply values to the inputs and - // merge the output values into the result vector. + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. - input clk; - input [2:0] in; - output reg [31:0] out; + input clk; + input [2:0] in; + output reg [31:0] out; - localparam ST_0 = 0; - localparam ST_1 = 1; - localparam ST_2 = 2; + localparam ST_0 = 0; + localparam ST_1 = 1; + localparam ST_2 = 2; - always @(posedge clk) begin - case (1'b1) // synopsys parallel_case - in[ST_0]: out <= 32'h1234; - in[ST_1]: out <= 32'h4356; - in[ST_2]: out <= 32'h9874; - default: out <= 32'h1; - endcase - end + always @(posedge clk) begin + case (1'b1) // synopsys parallel_case + in[ST_0]: out <= 32'h1234; + in[ST_1]: out <= 32'h4356; + in[ST_2]: out <= 32'h9874; + default: out <= 32'h1; + endcase + end endmodule diff --git a/test_regress/t/t_case_orig.v b/test_regress/t/t_case_orig.v index bbf1c84f5..2eebc50f7 100644 --- a/test_regress/t/t_case_orig.v +++ b/test_regress/t/t_case_orig.v @@ -4,184 +4,188 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg _ranit; + reg _ranit; - reg rnd; - reg [2:0] a; - reg [2:0] b; - reg [31:0] wide; + reg rnd; + reg [2:0] a; + reg [2:0] b; + reg [31:0] wide; - // surefire lint_off STMINI - initial _ranit = 0; + // surefire lint_off STMINI + initial _ranit = 0; - wire sigone1 = 1'b1; - wire sigone2 = 1'b1; - reg ok; + wire sigone1 = 1'b1; + wire sigone2 = 1'b1; + reg ok; - parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b?? + parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b?? - // Large case statements should be well optimizable. - reg [2:0] anot; - always @ (/*AS*/a) begin - casez (a) - default: anot = 3'b001; - 3'd0: anot = 3'b111; - 3'd1: anot = 3'b110; - 3'd2: anot = 3'b101; - 3'd3: anot = 3'b101; - 3'd4: anot = 3'b011; - 3'd5: anot = 3'b010; - 3'd6: anot = 3'b001; // Same so folds with 7 - endcase - end + // Large case statements should be well optimizable. + reg [2:0] anot; + always @( /*AS*/ a) begin + casez (a) + default: anot = 3'b001; + 3'd0: anot = 3'b111; + 3'd1: anot = 3'b110; + 3'd2: anot = 3'b101; + 3'd3: anot = 3'b101; + 3'd4: anot = 3'b011; + 3'd5: anot = 3'b010; + 3'd6: anot = 3'b001; // Same so folds with 7 + endcase + end - always @ (posedge clk) begin - if (!_ranit) begin - _ranit <= 1; - rnd <= 1; - $write("[%0t] t_case: Running\n", $time); - // - a = 3'b101; - b = 3'b111; - // verilator lint_off CASEX - casex (a) - default: $stop; - 3'bx1x: $stop; - 3'b100: $stop; - 3'bx01: ; - endcase - casez (a) - default: $stop; - 3'b?1?: $stop; - 3'b100: $stop; - 3'b?01: ; - endcase - casez (a) - default: $stop; - {1'b0, TWOUNKN}: $stop; - {1'b1, TWOUNKN}: ; - endcase - casez (b) - default: $stop; - {1'b0, TWOUNKN}: $stop; - {1'b1, TWOUNKN}: ; -// {1'b0, 2'b??}: $stop; -// {1'b1, 2'b??}: ; - endcase - case(a[0]) - default: ; - endcase - casex(a) - default: ; - 3'b?0?: ; - endcase - // verilator lint_off CASEX - //This is illegal, the default occurs before the statements. - //case(a[0]) - // default: $stop; - // 1'b1: ; - //endcase - // - wide = 32'h12345678; - casez (wide) - default: $stop; - 32'h12345677, - 32'h12345678, - 32'h12345679: ; - endcase - // - ok = 0; - casez ({sigone1,sigone2}) - //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... - 2'b10, 2'b01: ; - 2'b00: ; - default: ok=1'b1; - endcase - if (ok !== 1'b1) $stop; - // - - if (rnd) begin - $write(""); - end - // - $write("*-* All Finished *-*\n"); - $finish; - end - end - - // Check parameters in case statements - parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. - parameter DSP_REGISTER_V = 6'h03; - - reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl - reg [5:0] reg_addr_2s; // Delayed version of reg_addr - reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases - reg [15:10] f_tmp_2s; // Delayed copy of F - reg p00_2s; - - initial begin - alu_ctl_2s = 3'h1; - reg_addr_2s = 6'h3; - ir_slave_2s= 0; - f_tmp_2s= 0; - casex ({alu_ctl_2s,reg_addr_2s, - ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], - f_tmp_2s[11:10]}) - default: p00_2s = 1'b0; - {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; - endcase - if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused + always @(posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + rnd <= 1; + $write("[%0t] t_case: Running\n", $time); // - case ({1'b1, 1'b1}) + a = 3'b101; + b = 3'b111; + // verilator lint_off CASEX + casex (a) default: $stop; - {1'b1, p00_2s}: ; + 3'bx1x: $stop; + 3'b100: $stop; + 3'bx01: ; endcase - end + casez (a) + default: $stop; + 3'b?1?: $stop; + 3'b100: $stop; + 3'b?01: ; + endcase + casez (a) + default: $stop; + {1'b0, TWOUNKN} : $stop; + {1'b1, TWOUNKN} : ; + endcase + casez (b) + default: $stop; + {1'b0, TWOUNKN} : $stop; + {1'b1, TWOUNKN} : ; + // {1'b0, 2'b??}: $stop; + // {1'b1, 2'b??}: ; + endcase + case (a[0]) + default: ; + endcase + casex (a) + default: ; + 3'b?0?: ; + endcase + // verilator lint_off CASEX + //This is illegal, the default occurs before the statements. + //case(a[0]) + // default: $stop; + // 1'b1: ; + //endcase + // + wide = 32'h12345678; + casez (wide) + default: $stop; + 32'h12345677, 32'h12345678, 32'h12345679: ; + endcase + // + ok = 0; + casez ({ + sigone1, sigone2 + }) + //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... + 2'b10, 2'b01: ; + 2'b00: ; + default: ok = 1'b1; + endcase + if (ok !== 1'b1) $stop; + // - // Check wide overlapping cases - // surefire lint_off CSEOVR - parameter ANY_STATE = 7'h??; - reg [19:0] foo; - initial begin - foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; - casez (foo) - default: $stop; - {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; - {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; - endcase - end - initial begin - foo = 20'b1010; - casex (foo[3:0]) - default: $stop; - 4'b0xxx, - 4'b100x, - 4'b11xx: $stop; - 4'b1010: ; - endcase - end - initial begin - foo = 20'b1010; - ok = 1'b0; - // Test of RANGE(CONCAT reductions... - casex ({foo[3:2],foo[1:0],foo[3]}) - 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions - 5'bxx00x: $stop; - 5'bxx01x: $stop; - 5'bxx11x: $stop; - endcase - if (!ok) $stop; - end + if (rnd) begin + $write(""); + end + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // Check parameters in case statements + parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. + parameter DSP_REGISTER_V = 6'h03; + + reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl + reg [5:0] reg_addr_2s; // Delayed version of reg_addr + reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases + reg [15:10] f_tmp_2s; // Delayed copy of F + reg p00_2s; + + initial begin + alu_ctl_2s = 3'h1; + reg_addr_2s = 6'h3; + ir_slave_2s = 0; + f_tmp_2s = 0; + casex ({ + alu_ctl_2s, reg_addr_2s, ir_slave_2s[7], ir_slave_2s[5:4], ir_slave_2s[1:0], f_tmp_2s[11:10] + }) + default: p00_2s = 1'b0; + {ALU_DO_REGISTER, DSP_REGISTER_V, 1'bx, 2'bx, 2'bx, 2'bx} : p00_2s = 1'b1; + endcase + if (1'b0) $display("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused + // + case ({ + 1'b1, 1'b1 + }) + default: $stop; + {1'b1, p00_2s} : ; + endcase + end + + // Check wide overlapping cases + // surefire lint_off CSEOVR + parameter ANY_STATE = 7'h??; + reg [19:0] foo; + initial begin + foo = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 7'h04, 8'b0}; + casez (foo) + default: $stop; + {1'b1, 1'b?, 1'b?, 1'b?, 1'b?, ANY_STATE, 8'b?} : $stop; + {1'b?, 1'b1, 1'b?, 1'b?, 1'b?, 7'h00, 8'b?} : $stop; + {1'b?, 1'b?, 1'b1, 1'b?, 1'b?, 7'h00, 8'b?} : $stop; + {1'b?, 1'b?, 1'b?, 1'b1, 1'b?, 7'h00, 8'b?} : $stop; + {1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h04, 8'b?} : ; + {1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h06, 8'hdf} : $stop; + {1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h06, 8'h00} : $stop; + endcase + end + initial begin + foo = 20'b1010; + casex (foo[3:0]) + default: $stop; + 4'b0xxx, 4'b100x, 4'b11xx: $stop; + 4'b1010: ; + endcase + end + initial begin + foo = 20'b1010; + ok = 1'b0; + // Test of RANGE(CONCAT reductions... + casex ({ + foo[3:2], foo[1:0], foo[3] + }) + 5'bxx10x: begin + ok = 1'b0; + foo = 20'd1; + ok = 1'b1; + end // Check multiple expressions + 5'bxx00x: $stop; + 5'bxx01x: $stop; + 5'bxx11x: $stop; + endcase + if (!ok) $stop; + end endmodule diff --git a/test_regress/t/t_case_overlap_bad.out b/test_regress/t/t_case_overlap_bad.out index f53a2e97d..c904c98e4 100644 --- a/test_regress/t/t_case_overlap_bad.out +++ b/test_regress/t/t_case_overlap_bad.out @@ -1,27 +1,27 @@ -%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:13: Case conditions overlap - 25 | 3'b001, 3'b000: $stop; - | ^~~~~~ - t/t_case_overlap_bad.v:24:13: ... Location of overlapping condition - 24 | 3'b00?: $stop; - | ^~~~~~ +%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:7: Case conditions overlap + 25 | 3'b001, 3'b000: $stop; + | ^~~~~~ + t/t_case_overlap_bad.v:24:7: ... Location of overlapping condition + 24 | 3'b00?: $stop; + | ^~~~~~ ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. -%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:13: Case conditions overlap (example pattern 0x7) - 30 | 3'b11?: $stop; - | ^~~~~~ - t/t_case_overlap_bad.v:29:13: ... Location of overlapping condition - 29 | 3'b111, 3'b0??: v++; - | ^~~~~~ -%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:35:13: Case conditions overlap - 35 | 3'b001: $stop; - | ^~~~~~ - t/t_case_overlap_bad.v:34:21: ... Location of overlapping condition - 34 | 3'b000, 3'b001, 3'b010, 3'b011: v++; - | ^~~~~~ -%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:40:13: Case conditions overlap - 40 | 3'b011: $stop; - | ^~~~~~ - t/t_case_overlap_bad.v:39:37: ... Location of overlapping condition - 39 | 3'b000, 3'b001, 3'b010, 3'b011: v++; - | ^~~~~~ +%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:7: Case conditions overlap (example pattern 0x7) + 30 | 3'b11?: $stop; + | ^~~~~~ + t/t_case_overlap_bad.v:29:7: ... Location of overlapping condition + 29 | 3'b111, 3'b0??: v++; + | ^~~~~~ +%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:35:7: Case conditions overlap + 35 | 3'b001: $stop; + | ^~~~~~ + t/t_case_overlap_bad.v:34:15: ... Location of overlapping condition + 34 | 3'b000, 3'b001, 3'b010, 3'b011: v++; + | ^~~~~~ +%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:40:7: Case conditions overlap + 40 | 3'b011: $stop; + | ^~~~~~ + t/t_case_overlap_bad.v:39:31: ... Location of overlapping condition + 39 | 3'b000, 3'b001, 3'b010, 3'b011: v++; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_overlap_bad.v b/test_regress/t/t_case_overlap_bad.v index 1b30da2fe..845a0f436 100644 --- a/test_regress/t/t_case_overlap_bad.v +++ b/test_regress/t/t_case_overlap_bad.v @@ -5,40 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 module t; - t1 i_t1(); + t1 i_t1 (); endmodule module t1; - int v = 0; + int v = 0; - logic [2:0] state; + logic [2:0] state; - initial begin - state = 2; - casez (state) - 3'b11?, 3'b???: v++; - default; - endcase - casez (state) - 3'b00?: $stop; - 3'b001, 3'b000: $stop; - default; - endcase - casez (state) - 3'b111, 3'b0??: v++; - 3'b11?: $stop; - default; - endcase - casez (state) - 3'b000, 3'b001, 3'b010, 3'b011: v++; - 3'b001: $stop; - default; - endcase - casez (state) - 3'b000, 3'b001, 3'b010, 3'b011: v++; - 3'b011: $stop; - default; - endcase - end + initial begin + state = 2; + casez (state) + 3'b11?, 3'b???: v++; + default; + endcase + casez (state) + 3'b00?: $stop; + 3'b001, 3'b000: $stop; + default; + endcase + casez (state) + 3'b111, 3'b0??: v++; + 3'b11?: $stop; + default; + endcase + casez (state) + 3'b000, 3'b001, 3'b010, 3'b011: v++; + 3'b001: $stop; + default; + endcase + casez (state) + 3'b000, 3'b001, 3'b010, 3'b011: v++; + 3'b011: $stop; + default; + endcase + end endmodule diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v index 02e398d01..406555b25 100644 --- a/test_regress/t/t_case_reducer.v +++ b/test_regress/t/t_case_reducer.v @@ -4,100 +4,98 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] operand_a = crc[7:0]; - wire [7:0] operand_b = crc[15:8]; + // Take CRC data and apply to testblock inputs + wire [7:0] operand_a = crc[7:0]; + wire [7:0] operand_b = crc[15:8]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [6:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[6:0]), - // Inputs - .clk (clk), - .operand_a (operand_a[7:0]), - .operand_b (operand_b[7:0])); - - // Aggregate outputs into a single result vector - wire [63:0] result = {57'h0, out}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h8a78c2ec4946ac38 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module Test - ( - // Inputs - input wire clk, - input wire [7:0] operand_a, // operand a - input wire [7:0] operand_b, // operand b - // Outputs - output wire [6:0] out - ); - - wire [6:0] clz_a; - wire [6:0] clz_b; - - clz u_clz_a - ( + Test test ( /*AUTOINST*/ + // Outputs + .out(out[6:0]), // Inputs - .data_i (operand_a), - .out (clz_a)); + .clk(clk), + .operand_a(operand_a[7:0]), + .operand_b(operand_b[7:0]) + ); - clz u_clz_b - ( - // Inputs - .data_i (operand_b), - .out (clz_b)); + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, out}; - assign out = clz_a - clz_b; + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - always @(posedge clk) - $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h8a78c2ec4946ac38 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + // Inputs + input wire clk, + input wire [7:0] operand_a, // operand a + input wire [7:0] operand_b, // operand b + // Outputs + output wire [6:0] out +); + + wire [6:0] clz_a; + wire [6:0] clz_b; + + clz u_clz_a ( + // Inputs + .data_i(operand_a), + .out(clz_a) + ); + + clz u_clz_b ( + // Inputs + .data_i(operand_b), + .out(clz_b) + ); + + assign out = clz_a - clz_b; +`ifdef TEST_VERBOSE + always @(posedge clk) $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); `endif endmodule +// verilog_format: off `define def_0000_001x 8'b0000_0010, 8'b0000_0011 `define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 @@ -204,7 +202,6 @@ endmodule `define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx - module clz( input wire [7:0] data_i, output wire [6:0] out @@ -276,4 +273,4 @@ module clz( assign out = {4'b0000, clz_byte1}; -endmodule // clz +endmodule diff --git a/test_regress/t/t_case_string.v b/test_regress/t/t_case_string.v index 46de15a86..cf93a6f4e 100644 --- a/test_regress/t/t_case_string.v +++ b/test_regress/t/t_case_string.v @@ -4,36 +4,35 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - string mystr; - reg [2:0] cyc; initial cyc = 0; + string mystr; + reg [2:0] cyc; + initial cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) if (mystr != "case-1") $stop; - if (cyc == 4) if (mystr != "case-4") $stop; - if (cyc == 6) if (mystr != "bad-default") $stop; - if (cyc == 7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) if (mystr != "case-1") $stop; + if (cyc == 4) if (mystr != "case-4") $stop; + if (cyc == 6) if (mystr != "bad-default") $stop; + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @ (cyc) begin - // verilator lint_off CASEINCOMPLETE - case (cyc) - 3'b000: mystr = "case-0"; - 3'b001: mystr = "case-1"; - 3'b010: mystr = "case-2"; - 3'b100: mystr = "case-4"; - 3'b101: mystr = "case-5"; - default: mystr = "bad-default"; - endcase - //$display("with_case: %d = %s", cyc, mystr); - end + always @(cyc) begin + // verilator lint_off CASEINCOMPLETE + case (cyc) + 3'b000: mystr = "case-0"; + 3'b001: mystr = "case-1"; + 3'b010: mystr = "case-2"; + 3'b100: mystr = "case-4"; + 3'b101: mystr = "case-5"; + default: mystr = "bad-default"; + endcase + //$display("with_case: %d = %s", cyc, mystr); + end endmodule diff --git a/test_regress/t/t_case_string2.v b/test_regress/t/t_case_string2.v index 01a5cb0f1..b0e44639d 100644 --- a/test_regress/t/t_case_string2.v +++ b/test_regress/t/t_case_string2.v @@ -6,16 +6,16 @@ module t; -function automatic string broken_case(input string some_string); - case(some_string) - "alpha": return "alpha"; - default: return "beta"; + function automatic string broken_case(input string some_string); + case (some_string) + "alpha": return "alpha"; + default: return "beta"; endcase -endfunction + endfunction - initial begin - $display(broken_case("gamma")); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display(broken_case("gamma")); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index 80f08b488..472259af3 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -4,90 +4,93 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + reg out1; + reg [4:0] out2; + sub sub ( + .in(crc[23:0]), + .out1(out1), + .out2(out2) + ); - reg out1; - reg [4:0] out2; - sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; - if (cyc==0) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; - end - else if (cyc==90) begin - if (sum !== 64'hf0afc2bfa78277c5) $stop; - end - else if (cyc==91) begin - end - else if (cyc==92) begin - end - else if (cyc==93) begin - end - else if (cyc==94) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {58'h0, out1, out2}; + if (cyc == 0) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc == 90) begin + if (sum !== 64'hf0afc2bfa78277c5) $stop; + end + else if (cyc == 91) begin + end + else if (cyc == 92) begin + end + else if (cyc == 93) begin + end + else if (cyc == 94) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub (/*AUTOARG*/ - // Outputs - out1, out2, - // Inputs - in - ); +module sub ( /*AUTOARG*/ + // Outputs + out1, + out2, + // Inputs + in +); - input [23:0] in; - output reg out1; - output reg [4:0] out2; + input [23:0] in; + output reg out1; + output reg [4:0] out2; - always @* begin - casez (in) - 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; - 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; - 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; - 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; - 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; - 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; - 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; - 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; - 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; - // Same pattern, but reversed to test we work OK. - 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; - 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; - 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; - 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; - 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; - 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; - 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; - 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; - 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; - 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; - 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; - 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; - 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; - 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; - 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; - 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; - endcase - end + always @* begin + casez (in) + 24'b0000_0000_0000_0000_0000_0000: {out1, out2} = {1'b0, 5'h00}; + 24'b????_????_????_????_????_???1: {out1, out2} = {1'b1, 5'h00}; + 24'b????_????_????_????_????_??10: {out1, out2} = {1'b1, 5'h01}; + 24'b????_????_????_????_????_?100: {out1, out2} = {1'b1, 5'h02}; + 24'b????_????_????_????_????_1000: {out1, out2} = {1'b1, 5'h03}; + 24'b????_????_????_????_???1_0000: {out1, out2} = {1'b1, 5'h04}; + 24'b????_????_????_????_??10_0000: {out1, out2} = {1'b1, 5'h05}; + 24'b????_????_????_????_?100_0000: {out1, out2} = {1'b1, 5'h06}; + 24'b????_????_????_????_1000_0000: {out1, out2} = {1'b1, 5'h07}; + // Same pattern, but reversed to test we work OK. + 24'b1000_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h17}; + 24'b?100_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h16}; + 24'b??10_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h15}; + 24'b???1_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h14}; + 24'b????_1000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h13}; + 24'b????_?100_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h12}; + 24'b????_??10_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h11}; + 24'b????_???1_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h10}; + 24'b????_????_1000_0000_0000_0000: {out1, out2} = {1'b1, 5'h0f}; + 24'b????_????_?100_0000_0000_0000: {out1, out2} = {1'b1, 5'h0e}; + 24'b????_????_??10_0000_0000_0000: {out1, out2} = {1'b1, 5'h0d}; + 24'b????_????_???1_0000_0000_0000: {out1, out2} = {1'b1, 5'h0c}; + 24'b????_????_????_1000_0000_0000: {out1, out2} = {1'b1, 5'h0b}; + 24'b????_????_????_?100_0000_0000: {out1, out2} = {1'b1, 5'h0a}; + 24'b????_????_????_??10_0000_0000: {out1, out2} = {1'b1, 5'h09}; + 24'b????_????_????_???1_0000_0000: {out1, out2} = {1'b1, 5'h08}; + endcase + end endmodule diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v index 901f8e5e8..8476b2792 100644 --- a/test_regress/t/t_case_write1.v +++ b/test_regress/t/t_case_write1.v @@ -6,41 +6,39 @@ `define STRINGIFY(x) `"x`" -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [63:0] crc; + integer fd; + integer fdtmp; - reg [63:0] crc; - integer fd; - integer fdtmp; + t_case_write1_tasks tasks (); - t_case_write1_tasks tasks (); + integer cyc; + initial cyc = 0; - integer cyc; initial cyc = 0; + always @(posedge clk) begin + $fwrite(fd, "[%0d] crc=%x ", cyc, crc); + tasks.big_case(fd, crc[31:0]); + $fwrite(fd, "\n"); + end - always @ (posedge clk) begin - $fwrite(fd, "[%0d] crc=%x ", cyc, crc); - tasks.big_case(fd, crc[31:0]); - $fwrite(fd, "\n"); - end - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==1) begin - crc <= 64'h00000000_00000097; - $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); - fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); - fd <= fdtmp; - end - if (cyc==90) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 1) begin + crc <= 64'h00000000_00000097; + $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); + fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); + fd <= fdtmp; + end + if (cyc == 90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_case_write1_tasks.v b/test_regress/t/t_case_write1_tasks.v index 5b4998938..d99728e69 100644 --- a/test_regress/t/t_case_write1_tasks.v +++ b/test_regress/t/t_case_write1_tasks.v @@ -6,3788 +6,3257 @@ module t_case_write1_tasks (); - // verilator lint_off WIDTH - // verilator lint_off CASEINCOMPLETE + // verilator lint_off WIDTH + // verilator lint_off CASEINCOMPLETE - parameter STRLEN = 78; - task ozonerab; - input [6:0] rab; - inout [STRLEN*8:1] foobar; - // verilator no_inline_task - begin - case (rab[6:0]) - 7'h00 : foobar = {foobar, " 0"}; - 7'h01 : foobar = {foobar, " 1"}; - 7'h02 : foobar = {foobar, " 2"}; - 7'h03 : foobar = {foobar, " 3"}; - 7'h04 : foobar = {foobar, " 4"}; - 7'h05 : foobar = {foobar, " 5"}; - 7'h06 : foobar = {foobar, " 6"}; - 7'h07 : foobar = {foobar, " 7"}; - 7'h08 : foobar = {foobar, " 8"}; - 7'h09 : foobar = {foobar, " 9"}; - 7'h0a : foobar = {foobar, " 10"}; - 7'h0b : foobar = {foobar, " 11"}; - 7'h0c : foobar = {foobar, " 12"}; - 7'h0d : foobar = {foobar, " 13"}; - 7'h0e : foobar = {foobar, " 14"}; - 7'h0f : foobar = {foobar, " 15"}; - 7'h10 : foobar = {foobar, " 16"}; - 7'h11 : foobar = {foobar, " 17"}; - 7'h12 : foobar = {foobar, " 18"}; - 7'h13 : foobar = {foobar, " 19"}; - 7'h14 : foobar = {foobar, " 20"}; - 7'h15 : foobar = {foobar, " 21"}; - 7'h16 : foobar = {foobar, " 22"}; - 7'h17 : foobar = {foobar, " 23"}; - 7'h18 : foobar = {foobar, " 24"}; - 7'h19 : foobar = {foobar, " 25"}; - 7'h1a : foobar = {foobar, " 26"}; - 7'h1b : foobar = {foobar, " 27"}; - 7'h1c : foobar = {foobar, " 28"}; - 7'h1d : foobar = {foobar, " 29"}; - 7'h1e : foobar = {foobar, " 30"}; - 7'h1f : foobar = {foobar, " 31"}; - 7'h20 : foobar = {foobar, " 32"}; - 7'h21 : foobar = {foobar, " 33"}; - 7'h22 : foobar = {foobar, " 34"}; - 7'h23 : foobar = {foobar, " 35"}; - 7'h24 : foobar = {foobar, " 36"}; - 7'h25 : foobar = {foobar, " 37"}; - 7'h26 : foobar = {foobar, " 38"}; - 7'h27 : foobar = {foobar, " 39"}; - 7'h28 : foobar = {foobar, " 40"}; - 7'h29 : foobar = {foobar, " 41"}; - 7'h2a : foobar = {foobar, " 42"}; - 7'h2b : foobar = {foobar, " 43"}; - 7'h2c : foobar = {foobar, " 44"}; - 7'h2d : foobar = {foobar, " 45"}; - 7'h2e : foobar = {foobar, " 46"}; - 7'h2f : foobar = {foobar, " 47"}; - 7'h30 : foobar = {foobar, " 48"}; - 7'h31 : foobar = {foobar, " 49"}; - 7'h32 : foobar = {foobar, " 50"}; - 7'h33 : foobar = {foobar, " 51"}; - 7'h34 : foobar = {foobar, " 52"}; - 7'h35 : foobar = {foobar, " 53"}; - 7'h36 : foobar = {foobar, " 54"}; - 7'h37 : foobar = {foobar, " 55"}; - 7'h38 : foobar = {foobar, " 56"}; - 7'h39 : foobar = {foobar, " 57"}; - 7'h3a : foobar = {foobar, " 58"}; - 7'h3b : foobar = {foobar, " 59"}; - 7'h3c : foobar = {foobar, " 60"}; - 7'h3d : foobar = {foobar, " 61"}; - 7'h3e : foobar = {foobar, " 62"}; - 7'h3f : foobar = {foobar, " 63"}; - 7'h40 : foobar = {foobar, " 64"}; - 7'h41 : foobar = {foobar, " 65"}; - 7'h42 : foobar = {foobar, " 66"}; - 7'h43 : foobar = {foobar, " 67"}; - 7'h44 : foobar = {foobar, " 68"}; - 7'h45 : foobar = {foobar, " 69"}; - 7'h46 : foobar = {foobar, " 70"}; - 7'h47 : foobar = {foobar, " 71"}; - 7'h48 : foobar = {foobar, " 72"}; - 7'h49 : foobar = {foobar, " 73"}; - 7'h4a : foobar = {foobar, " 74"}; - 7'h4b : foobar = {foobar, " 75"}; - 7'h4c : foobar = {foobar, " 76"}; - 7'h4d : foobar = {foobar, " 77"}; - 7'h4e : foobar = {foobar, " 78"}; - 7'h4f : foobar = {foobar, " 79"}; - 7'h50 : foobar = {foobar, " 80"}; - 7'h51 : foobar = {foobar, " 81"}; - 7'h52 : foobar = {foobar, " 82"}; - 7'h53 : foobar = {foobar, " 83"}; - 7'h54 : foobar = {foobar, " 84"}; - 7'h55 : foobar = {foobar, " 85"}; - 7'h56 : foobar = {foobar, " 86"}; - 7'h57 : foobar = {foobar, " 87"}; - 7'h58 : foobar = {foobar, " 88"}; - 7'h59 : foobar = {foobar, " 89"}; - 7'h5a : foobar = {foobar, " 90"}; - 7'h5b : foobar = {foobar, " 91"}; - 7'h5c : foobar = {foobar, " 92"}; - 7'h5d : foobar = {foobar, " 93"}; - 7'h5e : foobar = {foobar, " 94"}; - 7'h5f : foobar = {foobar, " 95"}; - 7'h60 : foobar = {foobar, " 96"}; - 7'h61 : foobar = {foobar, " 97"}; - 7'h62 : foobar = {foobar, " 98"}; - 7'h63 : foobar = {foobar, " 99"}; - 7'h64 : foobar = {foobar, " 100"}; - 7'h65 : foobar = {foobar, " 101"}; - 7'h66 : foobar = {foobar, " 102"}; - 7'h67 : foobar = {foobar, " 103"}; - 7'h68 : foobar = {foobar, " 104"}; - 7'h69 : foobar = {foobar, " 105"}; - 7'h6a : foobar = {foobar, " 106"}; - 7'h6b : foobar = {foobar, " 107"}; - 7'h6c : foobar = {foobar, " 108"}; - 7'h6d : foobar = {foobar, " 109"}; - 7'h6e : foobar = {foobar, " 110"}; - 7'h6f : foobar = {foobar, " 111"}; - 7'h70 : foobar = {foobar, " 112"}; - 7'h71 : foobar = {foobar, " 113"}; - 7'h72 : foobar = {foobar, " 114"}; - 7'h73 : foobar = {foobar, " 115"}; - 7'h74 : foobar = {foobar, " 116"}; - 7'h75 : foobar = {foobar, " 117"}; - 7'h76 : foobar = {foobar, " 118"}; - 7'h77 : foobar = {foobar, " 119"}; - 7'h78 : foobar = {foobar, " 120"}; - 7'h79 : foobar = {foobar, " 121"}; - 7'h7a : foobar = {foobar, " 122"}; - 7'h7b : foobar = {foobar, " 123"}; - 7'h7c : foobar = {foobar, " 124"}; - 7'h7d : foobar = {foobar, " 125"}; - 7'h7e : foobar = {foobar, " 126"}; - 7'h7f : foobar = {foobar, " 127"}; - default:foobar = {foobar, " 128"}; - endcase - end + parameter STRLEN = 78; + task ozonerab; + input [6:0] rab; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (rab[6:0]) + 7'h00: foobar = {foobar, " 0"}; + 7'h01: foobar = {foobar, " 1"}; + 7'h02: foobar = {foobar, " 2"}; + 7'h03: foobar = {foobar, " 3"}; + 7'h04: foobar = {foobar, " 4"}; + 7'h05: foobar = {foobar, " 5"}; + 7'h06: foobar = {foobar, " 6"}; + 7'h07: foobar = {foobar, " 7"}; + 7'h08: foobar = {foobar, " 8"}; + 7'h09: foobar = {foobar, " 9"}; + 7'h0a: foobar = {foobar, " 10"}; + 7'h0b: foobar = {foobar, " 11"}; + 7'h0c: foobar = {foobar, " 12"}; + 7'h0d: foobar = {foobar, " 13"}; + 7'h0e: foobar = {foobar, " 14"}; + 7'h0f: foobar = {foobar, " 15"}; + 7'h10: foobar = {foobar, " 16"}; + 7'h11: foobar = {foobar, " 17"}; + 7'h12: foobar = {foobar, " 18"}; + 7'h13: foobar = {foobar, " 19"}; + 7'h14: foobar = {foobar, " 20"}; + 7'h15: foobar = {foobar, " 21"}; + 7'h16: foobar = {foobar, " 22"}; + 7'h17: foobar = {foobar, " 23"}; + 7'h18: foobar = {foobar, " 24"}; + 7'h19: foobar = {foobar, " 25"}; + 7'h1a: foobar = {foobar, " 26"}; + 7'h1b: foobar = {foobar, " 27"}; + 7'h1c: foobar = {foobar, " 28"}; + 7'h1d: foobar = {foobar, " 29"}; + 7'h1e: foobar = {foobar, " 30"}; + 7'h1f: foobar = {foobar, " 31"}; + 7'h20: foobar = {foobar, " 32"}; + 7'h21: foobar = {foobar, " 33"}; + 7'h22: foobar = {foobar, " 34"}; + 7'h23: foobar = {foobar, " 35"}; + 7'h24: foobar = {foobar, " 36"}; + 7'h25: foobar = {foobar, " 37"}; + 7'h26: foobar = {foobar, " 38"}; + 7'h27: foobar = {foobar, " 39"}; + 7'h28: foobar = {foobar, " 40"}; + 7'h29: foobar = {foobar, " 41"}; + 7'h2a: foobar = {foobar, " 42"}; + 7'h2b: foobar = {foobar, " 43"}; + 7'h2c: foobar = {foobar, " 44"}; + 7'h2d: foobar = {foobar, " 45"}; + 7'h2e: foobar = {foobar, " 46"}; + 7'h2f: foobar = {foobar, " 47"}; + 7'h30: foobar = {foobar, " 48"}; + 7'h31: foobar = {foobar, " 49"}; + 7'h32: foobar = {foobar, " 50"}; + 7'h33: foobar = {foobar, " 51"}; + 7'h34: foobar = {foobar, " 52"}; + 7'h35: foobar = {foobar, " 53"}; + 7'h36: foobar = {foobar, " 54"}; + 7'h37: foobar = {foobar, " 55"}; + 7'h38: foobar = {foobar, " 56"}; + 7'h39: foobar = {foobar, " 57"}; + 7'h3a: foobar = {foobar, " 58"}; + 7'h3b: foobar = {foobar, " 59"}; + 7'h3c: foobar = {foobar, " 60"}; + 7'h3d: foobar = {foobar, " 61"}; + 7'h3e: foobar = {foobar, " 62"}; + 7'h3f: foobar = {foobar, " 63"}; + 7'h40: foobar = {foobar, " 64"}; + 7'h41: foobar = {foobar, " 65"}; + 7'h42: foobar = {foobar, " 66"}; + 7'h43: foobar = {foobar, " 67"}; + 7'h44: foobar = {foobar, " 68"}; + 7'h45: foobar = {foobar, " 69"}; + 7'h46: foobar = {foobar, " 70"}; + 7'h47: foobar = {foobar, " 71"}; + 7'h48: foobar = {foobar, " 72"}; + 7'h49: foobar = {foobar, " 73"}; + 7'h4a: foobar = {foobar, " 74"}; + 7'h4b: foobar = {foobar, " 75"}; + 7'h4c: foobar = {foobar, " 76"}; + 7'h4d: foobar = {foobar, " 77"}; + 7'h4e: foobar = {foobar, " 78"}; + 7'h4f: foobar = {foobar, " 79"}; + 7'h50: foobar = {foobar, " 80"}; + 7'h51: foobar = {foobar, " 81"}; + 7'h52: foobar = {foobar, " 82"}; + 7'h53: foobar = {foobar, " 83"}; + 7'h54: foobar = {foobar, " 84"}; + 7'h55: foobar = {foobar, " 85"}; + 7'h56: foobar = {foobar, " 86"}; + 7'h57: foobar = {foobar, " 87"}; + 7'h58: foobar = {foobar, " 88"}; + 7'h59: foobar = {foobar, " 89"}; + 7'h5a: foobar = {foobar, " 90"}; + 7'h5b: foobar = {foobar, " 91"}; + 7'h5c: foobar = {foobar, " 92"}; + 7'h5d: foobar = {foobar, " 93"}; + 7'h5e: foobar = {foobar, " 94"}; + 7'h5f: foobar = {foobar, " 95"}; + 7'h60: foobar = {foobar, " 96"}; + 7'h61: foobar = {foobar, " 97"}; + 7'h62: foobar = {foobar, " 98"}; + 7'h63: foobar = {foobar, " 99"}; + 7'h64: foobar = {foobar, " 100"}; + 7'h65: foobar = {foobar, " 101"}; + 7'h66: foobar = {foobar, " 102"}; + 7'h67: foobar = {foobar, " 103"}; + 7'h68: foobar = {foobar, " 104"}; + 7'h69: foobar = {foobar, " 105"}; + 7'h6a: foobar = {foobar, " 106"}; + 7'h6b: foobar = {foobar, " 107"}; + 7'h6c: foobar = {foobar, " 108"}; + 7'h6d: foobar = {foobar, " 109"}; + 7'h6e: foobar = {foobar, " 110"}; + 7'h6f: foobar = {foobar, " 111"}; + 7'h70: foobar = {foobar, " 112"}; + 7'h71: foobar = {foobar, " 113"}; + 7'h72: foobar = {foobar, " 114"}; + 7'h73: foobar = {foobar, " 115"}; + 7'h74: foobar = {foobar, " 116"}; + 7'h75: foobar = {foobar, " 117"}; + 7'h76: foobar = {foobar, " 118"}; + 7'h77: foobar = {foobar, " 119"}; + 7'h78: foobar = {foobar, " 120"}; + 7'h79: foobar = {foobar, " 121"}; + 7'h7a: foobar = {foobar, " 122"}; + 7'h7b: foobar = {foobar, " 123"}; + 7'h7c: foobar = {foobar, " 124"}; + 7'h7d: foobar = {foobar, " 125"}; + 7'h7e: foobar = {foobar, " 126"}; + 7'h7f: foobar = {foobar, " 127"}; + default: foobar = {foobar, " 128"}; + endcase + end - endtask + endtask - task ozonerb; - input [5:0] rb; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (rb[5:0]) - 6'h10, - 6'h17, - 6'h1e, - 6'h1f: foobar = {foobar, " 129"}; - default: ozonerab({1'b1, rb}, foobar); - endcase - end - endtask + task ozonerb; + input [5:0] rb; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (rb[5:0]) + 6'h10, 6'h17, 6'h1e, 6'h1f: foobar = {foobar, " 129"}; + default: ozonerab({1'b1, rb}, foobar); + endcase + end + endtask - task ozonef3f4_iext; - input [1:0] foo; - input [15:0] im16; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo) - 2'h0 : - begin - skyway({4{im16[15]}}, foobar); - skyway({4{im16[15]}}, foobar); - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - foobar = {foobar, " 130"}; - end - 2'h1 : - begin - foobar = {foobar, " 131"}; - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - end - 2'h2 : - begin - skyway({4{im16[15]}}, foobar); - skyway({4{im16[15]}}, foobar); - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - foobar = {foobar, " 132"}; - end - 2'h3 : - begin - foobar = {foobar, " 133"}; - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - end - endcase - end - endtask + task ozonef3f4_iext; + input [1:0] foo; + input [15:0] im16; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0: begin + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11:8], foobar); + skyway(im16[7:4], foobar); + skyway(im16[3:0], foobar); + foobar = {foobar, " 130"}; + end + 2'h1: begin + foobar = {foobar, " 131"}; + skyway(im16[15:12], foobar); + skyway(im16[11:8], foobar); + skyway(im16[7:4], foobar); + skyway(im16[3:0], foobar); + end + 2'h2: begin + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11:8], foobar); + skyway(im16[7:4], foobar); + skyway(im16[3:0], foobar); + foobar = {foobar, " 132"}; + end + 2'h3: begin + foobar = {foobar, " 133"}; + skyway(im16[15:12], foobar); + skyway(im16[11:8], foobar); + skyway(im16[7:4], foobar); + skyway(im16[3:0], foobar); + end + endcase + end + endtask - task skyway; - input [ 3:0] hex; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (hex) - 4'h0 : foobar = {foobar, " 134"}; - 4'h1 : foobar = {foobar, " 135"}; - 4'h2 : foobar = {foobar, " 136"}; - 4'h3 : foobar = {foobar, " 137"}; - 4'h4 : foobar = {foobar, " 138"}; - 4'h5 : foobar = {foobar, " 139"}; - 4'h6 : foobar = {foobar, " 140"}; - 4'h7 : foobar = {foobar, " 141"}; - 4'h8 : foobar = {foobar, " 142"}; - 4'h9 : foobar = {foobar, " 143"}; - 4'ha : foobar = {foobar, " 144"}; - 4'hb : foobar = {foobar, " 145"}; - 4'hc : foobar = {foobar, " 146"}; - 4'hd : foobar = {foobar, " 147"}; - 4'he : foobar = {foobar, " 148"}; - 4'hf : foobar = {foobar, " 149"}; - endcase - end - endtask + task skyway; + input [3:0] hex; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (hex) + 4'h0: foobar = {foobar, " 134"}; + 4'h1: foobar = {foobar, " 135"}; + 4'h2: foobar = {foobar, " 136"}; + 4'h3: foobar = {foobar, " 137"}; + 4'h4: foobar = {foobar, " 138"}; + 4'h5: foobar = {foobar, " 139"}; + 4'h6: foobar = {foobar, " 140"}; + 4'h7: foobar = {foobar, " 141"}; + 4'h8: foobar = {foobar, " 142"}; + 4'h9: foobar = {foobar, " 143"}; + 4'ha: foobar = {foobar, " 144"}; + 4'hb: foobar = {foobar, " 145"}; + 4'hc: foobar = {foobar, " 146"}; + 4'hd: foobar = {foobar, " 147"}; + 4'he: foobar = {foobar, " 148"}; + 4'hf: foobar = {foobar, " 149"}; + endcase + end + endtask - task ozonesr; - input [ 15:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[11: 9]) - 3'h0 : foobar = {foobar, " 158"}; - 3'h1 : foobar = {foobar, " 159"}; - 3'h2 : foobar = {foobar, " 160"}; - 3'h3 : foobar = {foobar, " 161"}; - 3'h4 : foobar = {foobar, " 162"}; - 3'h5 : foobar = {foobar, " 163"}; - 3'h6 : foobar = {foobar, " 164"}; - 3'h7 : foobar = {foobar, " 165"}; - endcase - end - endtask + task ozonesr; + input [15:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[11:9]) + 3'h0: foobar = {foobar, " 158"}; + 3'h1: foobar = {foobar, " 159"}; + 3'h2: foobar = {foobar, " 160"}; + 3'h3: foobar = {foobar, " 161"}; + 3'h4: foobar = {foobar, " 162"}; + 3'h5: foobar = {foobar, " 163"}; + 3'h6: foobar = {foobar, " 164"}; + 3'h7: foobar = {foobar, " 165"}; + endcase + end + endtask - task ozonejk; - input k; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - if (k) - foobar = {foobar, " 166"}; - else - foobar = {foobar, " 167"}; - end - endtask + task ozonejk; + input k; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + if (k) foobar = {foobar, " 166"}; + else foobar = {foobar, " 167"}; + end + endtask - task ozoneae; - input [ 2:0] ae; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (ae) - 3'b000 : foobar = {foobar, " 168"}; - 3'b001 : foobar = {foobar, " 169"}; - 3'b010 : foobar = {foobar, " 170"}; - 3'b011 : foobar = {foobar, " 171"}; - 3'b100 : foobar = {foobar, " 172"}; - 3'b101 : foobar = {foobar, " 173"}; - 3'b110 : foobar = {foobar, " 174"}; - 3'b111 : foobar = {foobar, " 175"}; - endcase - end - endtask + task ozoneae; + input [2:0] ae; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (ae) + 3'b000: foobar = {foobar, " 168"}; + 3'b001: foobar = {foobar, " 169"}; + 3'b010: foobar = {foobar, " 170"}; + 3'b011: foobar = {foobar, " 171"}; + 3'b100: foobar = {foobar, " 172"}; + 3'b101: foobar = {foobar, " 173"}; + 3'b110: foobar = {foobar, " 174"}; + 3'b111: foobar = {foobar, " 175"}; + endcase + end + endtask - task ozoneaee; - input [ 2:0] aee; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (aee) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : foobar = {foobar, " 176"}; - 3'b000 : foobar = {foobar, " 177"}; - 3'b010 : foobar = {foobar, " 178"}; - 3'b100 : foobar = {foobar, " 179"}; - 3'b110 : foobar = {foobar, " 180"}; - endcase - end - endtask + task ozoneaee; + input [2:0] aee; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (aee) + 3'b001, 3'b011, 3'b101, 3'b111: foobar = {foobar, " 176"}; + 3'b000: foobar = {foobar, " 177"}; + 3'b010: foobar = {foobar, " 178"}; + 3'b100: foobar = {foobar, " 179"}; + 3'b110: foobar = {foobar, " 180"}; + endcase + end + endtask - task ozoneape; - input [ 2:0] ape; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (ape) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : foobar = {foobar, " 181"}; - 3'b000 : foobar = {foobar, " 182"}; - 3'b010 : foobar = {foobar, " 183"}; - 3'b100 : foobar = {foobar, " 184"}; - 3'b110 : foobar = {foobar, " 185"}; - endcase - end - endtask + task ozoneape; + input [2:0] ape; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (ape) + 3'b001, 3'b011, 3'b101, 3'b111: foobar = {foobar, " 181"}; + 3'b000: foobar = {foobar, " 182"}; + 3'b010: foobar = {foobar, " 183"}; + 3'b100: foobar = {foobar, " 184"}; + 3'b110: foobar = {foobar, " 185"}; + endcase + end + endtask - task ozonef1; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[24:21]) - 4'h0 : - if (foo[26]) - foobar = {foobar, " 186"}; - else - foobar = {foobar, " 187"}; - 4'h1 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 188"}; - 2'b01 : foobar = {foobar, " 189"}; - 2'b10 : foobar = {foobar, " 190"}; - 2'b11 : foobar = {foobar, " 191"}; - endcase - 4'h2 : foobar = {foobar, " 192"}; - 4'h3 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 193"}; - 2'b01 : foobar = {foobar, " 194"}; - 2'b10 : foobar = {foobar, " 195"}; - 2'b11 : foobar = {foobar, " 196"}; - endcase - 4'h4 : - if (foo[26]) - foobar = {foobar, " 197"}; - else - foobar = {foobar, " 198"}; - 4'h5 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 199"}; - 2'b01 : foobar = {foobar, " 200"}; - 2'b10 : foobar = {foobar, " 201"}; - 2'b11 : foobar = {foobar, " 202"}; - endcase - 4'h6 : foobar = {foobar, " 203"}; - 4'h7 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 204"}; - 2'b01 : foobar = {foobar, " 205"}; - 2'b10 : foobar = {foobar, " 206"}; - 2'b11 : foobar = {foobar, " 207"}; - endcase - 4'h8 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 208"}; - 2'b01 : foobar = {foobar, " 209"}; - 2'b10 : foobar = {foobar, " 210"}; - 2'b11 : foobar = {foobar, " 211"}; - endcase - 4'h9 : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 212"}; - 2'b01 : foobar = {foobar, " 213"}; - 2'b10 : foobar = {foobar, " 214"}; - 2'b11 : foobar = {foobar, " 215"}; - endcase - 4'ha : - if (foo[25]) - foobar = {foobar, " 216"}; - else - foobar = {foobar, " 217"}; - 4'hb : - if (foo[25]) - foobar = {foobar, " 218"}; - else - foobar = {foobar, " 219"}; - 4'hc : - if (foo[26]) - foobar = {foobar, " 220"}; - else - foobar = {foobar, " 221"}; - 4'hd : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 222"}; - 2'b01 : foobar = {foobar, " 223"}; - 2'b10 : foobar = {foobar, " 224"}; - 2'b11 : foobar = {foobar, " 225"}; - endcase - 4'he : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 226"}; - 2'b01 : foobar = {foobar, " 227"}; - 2'b10 : foobar = {foobar, " 228"}; - 2'b11 : foobar = {foobar, " 229"}; - endcase - 4'hf : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 230"}; - 2'b01 : foobar = {foobar, " 231"}; - 2'b10 : foobar = {foobar, " 232"}; - 2'b11 : foobar = {foobar, " 233"}; - endcase - endcase - end - endtask + task ozonef1; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0: + if (foo[26]) foobar = {foobar, " 186"}; + else foobar = {foobar, " 187"}; + 4'h1: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 188"}; + 2'b01: foobar = {foobar, " 189"}; + 2'b10: foobar = {foobar, " 190"}; + 2'b11: foobar = {foobar, " 191"}; + endcase + 4'h2: foobar = {foobar, " 192"}; + 4'h3: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 193"}; + 2'b01: foobar = {foobar, " 194"}; + 2'b10: foobar = {foobar, " 195"}; + 2'b11: foobar = {foobar, " 196"}; + endcase + 4'h4: + if (foo[26]) foobar = {foobar, " 197"}; + else foobar = {foobar, " 198"}; + 4'h5: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 199"}; + 2'b01: foobar = {foobar, " 200"}; + 2'b10: foobar = {foobar, " 201"}; + 2'b11: foobar = {foobar, " 202"}; + endcase + 4'h6: foobar = {foobar, " 203"}; + 4'h7: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 204"}; + 2'b01: foobar = {foobar, " 205"}; + 2'b10: foobar = {foobar, " 206"}; + 2'b11: foobar = {foobar, " 207"}; + endcase + 4'h8: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 208"}; + 2'b01: foobar = {foobar, " 209"}; + 2'b10: foobar = {foobar, " 210"}; + 2'b11: foobar = {foobar, " 211"}; + endcase + 4'h9: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 212"}; + 2'b01: foobar = {foobar, " 213"}; + 2'b10: foobar = {foobar, " 214"}; + 2'b11: foobar = {foobar, " 215"}; + endcase + 4'ha: + if (foo[25]) foobar = {foobar, " 216"}; + else foobar = {foobar, " 217"}; + 4'hb: + if (foo[25]) foobar = {foobar, " 218"}; + else foobar = {foobar, " 219"}; + 4'hc: + if (foo[26]) foobar = {foobar, " 220"}; + else foobar = {foobar, " 221"}; + 4'hd: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 222"}; + 2'b01: foobar = {foobar, " 223"}; + 2'b10: foobar = {foobar, " 224"}; + 2'b11: foobar = {foobar, " 225"}; + endcase + 4'he: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 226"}; + 2'b01: foobar = {foobar, " 227"}; + 2'b10: foobar = {foobar, " 228"}; + 2'b11: foobar = {foobar, " 229"}; + endcase + 4'hf: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 230"}; + 2'b01: foobar = {foobar, " 231"}; + 2'b10: foobar = {foobar, " 232"}; + 2'b11: foobar = {foobar, " 233"}; + endcase + endcase + end + endtask - task ozonef1e; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[27:21]) - 7'h00: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 234"}; - foobar = {foobar, " 235"}; - end - 7'h01: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 236"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 237"}; - foobar = {foobar, " 238"}; - end - 7'h02: - foobar = {foobar, " 239"}; - 7'h03: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 240"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 241"}; - foobar = {foobar, " 242"}; - end - 7'h04: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 243"}; - foobar = {foobar," 244"}; - end - 7'h05: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 245"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 246"}; - end - 7'h06: - foobar = {foobar, " 247"}; - 7'h07: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 248"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 249"}; - end - 7'h08: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 250"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 251"}; - end - 7'h09: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 252"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 253"}; - end - 7'h0a: - begin - ozoneae(foo[17:15], foobar); - foobar = {foobar," 254"}; - end - 7'h0b: - begin - ozoneae(foo[17:15], foobar); - foobar = {foobar," 255"}; - end - 7'h0c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 256"}; - end - 7'h0d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 257"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 258"}; - end - 7'h0e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 259"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 260"}; - end - 7'h0f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 261"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 262"}; - end - 7'h10: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 263"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 264"}; - foobar = {foobar, " 265"}; - foobar = {foobar, " 266"}; - end - 7'h11: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 267"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 268"}; - foobar = {foobar, " 269"}; - foobar = {foobar, " 270"}; - end - 7'h12: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 271"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 272"}; - foobar = {foobar, " 273"}; - foobar = {foobar, " 274"}; - end - 7'h13: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 275"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 276"}; - foobar = {foobar, " 277"}; - foobar = {foobar, " 278"}; - end - 7'h14: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 279"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 280"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 281"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 282"}; - foobar = {foobar, " 283"}; - foobar = {foobar, " 284"}; - end - 7'h15: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 285"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 286"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 287"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 288"}; - foobar = {foobar, " 289"}; - foobar = {foobar, " 290"}; - end - 7'h16: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 291"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 292"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 293"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 294"}; - foobar = {foobar, " 295"}; - foobar = {foobar, " 296"}; - end - 7'h17: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 297"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 298"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 299"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 300"}; - foobar = {foobar, " 301"}; - foobar = {foobar, " 302"}; - end - 7'h18: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 303"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 304"}; - foobar = {foobar, " 305"}; - foobar = {foobar, " 306"}; - end - 7'h19: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 307"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 308"}; - foobar = {foobar, " 309"}; - foobar = {foobar, " 310"}; - end - 7'h1a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 311"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 312"}; - foobar = {foobar, " 313"}; - foobar = {foobar, " 314"}; - end - 7'h1b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 315"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 316"}; - foobar = {foobar, " 317"}; - foobar = {foobar, " 318"}; - end - 7'h1c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 319"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 320"}; - foobar = {foobar, " 321"}; - foobar = {foobar, " 322"}; - end - 7'h1d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 323"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 324"}; - foobar = {foobar, " 325"}; - foobar = {foobar, " 326"}; - end - 7'h1e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 327"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 328"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 329"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 330"}; - foobar = {foobar, " 331"}; - foobar = {foobar, " 332"}; - end - 7'h1f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 333"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 334"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 335"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 336"}; - foobar = {foobar, " 337"}; - foobar = {foobar, " 338"}; - end - 7'h20: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 339"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 340"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 341"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 342"}; - foobar = {foobar, " 343"}; - foobar = {foobar, " 344"}; - end - 7'h21: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 345"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 346"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 347"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 348"}; - foobar = {foobar, " 349"}; - foobar = {foobar, " 350"}; - end - 7'h22: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 351"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 352"}; - foobar = {foobar, " 353"}; - foobar = {foobar, " 354"}; - end - 7'h23: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 355"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 356"}; - foobar = {foobar, " 357"}; - foobar = {foobar, " 358"}; - end - 7'h24: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 359"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 360"}; - foobar = {foobar, " 361"}; - foobar = {foobar, " 362"}; - end - 7'h25: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 363"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 364"}; - foobar = {foobar, " 365"}; - foobar = {foobar, " 366"}; - end - 7'h26: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 367"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 368"}; - foobar = {foobar, " 369"}; - foobar = {foobar, " 370"}; - end - 7'h27: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 371"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 372"}; - foobar = {foobar, " 373"}; - foobar = {foobar, " 374"}; - end - 7'h28: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 375"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 376"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 377"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 378"}; - foobar = {foobar, " 379"}; - foobar = {foobar, " 380"}; - end - 7'h29: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 381"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 382"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 383"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 384"}; - foobar = {foobar, " 385"}; - foobar = {foobar, " 386"}; - end - 7'h2a: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 387"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 388"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 389"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 390"}; - foobar = {foobar, " 391"}; - foobar = {foobar, " 392"}; - end - 7'h2b: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 393"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 394"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 395"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 396"}; - foobar = {foobar, " 397"}; - foobar = {foobar, " 398"}; - end - 7'h2c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 399"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 400"}; - foobar = {foobar, " 401"}; - foobar = {foobar, " 402"}; - end - 7'h2d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 403"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 404"}; - foobar = {foobar, " 405"}; - foobar = {foobar, " 406"}; - end - 7'h2e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 407"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 408"}; - foobar = {foobar, " 409"}; - foobar = {foobar, " 410"}; - end - 7'h2f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 411"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 412"}; - foobar = {foobar, " 413"}; - foobar = {foobar, " 414"}; - end - 7'h30: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 415"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 416"}; - foobar = {foobar, " 417"}; - foobar = {foobar, " 418"}; - end - 7'h31: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 419"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 420"}; - foobar = {foobar, " 421"}; - foobar = {foobar, " 422"}; - end - 7'h32: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 423"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 424"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 425"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 426"}; - foobar = {foobar, " 427"}; - foobar = {foobar, " 428"}; - end - 7'h33: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 429"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 430"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 431"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 432"}; - foobar = {foobar, " 433"}; - foobar = {foobar, " 434"}; - end - 7'h34: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 435"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 436"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 437"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 438"}; - foobar = {foobar, " 439"}; - foobar = {foobar, " 440"}; - end - 7'h35: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 441"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 442"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 443"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 444"}; - foobar = {foobar, " 445"}; - foobar = {foobar, " 446"}; - end - 7'h36: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 447"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 448"}; - foobar = {foobar, " 449"}; - foobar = {foobar, " 450"}; - end - 7'h37: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 451"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 452"}; - foobar = {foobar, " 453"}; - foobar = {foobar, " 454"}; - end - 7'h38: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 455"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 456"}; - foobar = {foobar, " 457"}; - end - 7'h39: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 458"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 459"}; - foobar = {foobar, " 460"}; - end - 7'h3a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 461"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 462"}; - foobar = {foobar, " 463"}; - end - 7'h3b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 464"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 465"}; - foobar = {foobar, " 466"}; - end - 7'h3c: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 467"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 468"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 469"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 470"}; - foobar = {foobar, " 471"}; - end - 7'h3d: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 472"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 473"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 474"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 475"}; - foobar = {foobar, " 476"}; - end - 7'h3e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 477"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 478"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 479"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 480"}; - foobar = {foobar, " 481"}; - end - 7'h3f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 482"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 483"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 484"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 485"}; - foobar = {foobar, " 486"}; - end - 7'h40: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 487"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 488"}; - foobar = {foobar, " 489"}; - foobar = {foobar, " 490"}; - end - 7'h41: - begin - foobar = {foobar, " 491"}; - foobar = {foobar, " 492"}; - end - 7'h42: - begin - foobar = {foobar, " 493"}; - foobar = {foobar, " 494"}; - end - 7'h43: - begin - foobar = {foobar, " 495"}; - foobar = {foobar, " 496"}; - end - 7'h44: - begin - foobar = {foobar, " 497"}; - foobar = {foobar, " 498"}; - end - 7'h45: - foobar = {foobar, " 499"}; - 7'h46: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 500"}; - foobar = {foobar, " 501"}; - foobar = {foobar, " 502"}; - end - 7'h47: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 503"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 504"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 505"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 506"}; - foobar = {foobar, " 507"}; - foobar = {foobar, " 508"}; - end - 7'h48: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 509"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 510"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 511"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 512"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 513"}; - end - 7'h49: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 514"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 515"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 516"}; - end - 7'h4a: - foobar = {foobar," 517"}; - 7'h4b: - foobar = {foobar, " 518"}; - 7'h4c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 519"}; - foobar = {foobar, " 520"}; - foobar = {foobar, " 521"}; - end - 7'h4d: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 522"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 523"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 524"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 525"}; - foobar = {foobar, " 526"}; - foobar = {foobar, " 527"}; - end - 7'h4e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 528"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 529"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 530"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 531"}; - end - 7'h4f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 532"}; - end - 7'h50: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 533"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 534"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 535"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 536"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 537"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 538"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 539"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 540"}; - end - 7'h51: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 541"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 542"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 543"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 544"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 545"}; - end - 7'h52: - foobar = {foobar, " 546"}; - 7'h53: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 547"}; - end - 7'h54: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 548"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 549"}; - end - 7'h55: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 550"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 551"}; - end - 7'h56: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 552"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 553"}; - foobar = {foobar, " 554"}; - end - 7'h57: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 555"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 556"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 557"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 558"}; - end - 7'h58: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 559"}; - end - 7'h59: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 560"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 561"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 562"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 563"}; - end - 7'h5a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 564"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 565"}; - end - 7'h5b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 566"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 567"}; - end - 7'h5c: - begin - foobar = {foobar," 568"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 569"}; - foobar = {foobar," 570"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 571"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 572"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar, " 573"}; - end - 7'h5d: - begin - foobar = {foobar," 574"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 575"}; - foobar = {foobar," 576"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 577"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 578"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar, " 579"}; - end - 7'h5e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 580"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 581"}; - end - 7'h5f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 582"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 583"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 584"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 585"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 586"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 587"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 588"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 589"}; - end - 7'h60: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 590"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 591"}; - end - 7'h61: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 592"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 593"}; - end - 7'h62: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 594"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 595"}; - end - 7'h63: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 596"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 597"}; - end - 7'h64: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 598"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 599"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 600"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 601"}; - end - 7'h65: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 602"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 603"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 604"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 605"}; - end - 7'h66: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 606"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 607"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 608"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 609"}; - end - 7'h67: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 610"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 611"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 612"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 613"}; - end - 7'h68: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 614"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 615"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 616"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 617"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 618"}; - ozoneape(foo[17:15], foobar); - end - 7'h69: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 619"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 620"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 621"}; - end - 7'h6a: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 622"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 623"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 624"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 625"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 626"}; - ozoneae(foo[17:15], foobar); - end - 7'h6b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 627"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 628"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 629"}; - end - 7'h6c: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 630"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 631"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 632"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 633"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 634"}; - ozoneae(foo[17:15], foobar); - end - 7'h6d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 635"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 636"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 637"}; - end - 7'h6e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 638"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 639"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 640"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 641"}; - end - 7'h6f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 642"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 643"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 644"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 645"}; - end - 7'h70: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 646"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 647"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 648"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 649"}; - end - 7'h71: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 650"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 651"}; - end - 7'h72: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 652"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 653"}; - end - 7'h73: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 654"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 655"}; - ozoneae(foo[17:15], foobar); - end - 7'h74: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 656"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 657"}; - ozoneae(foo[17:15], foobar); - end - 7'h75: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 658"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 659"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 660"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 661"}; - foobar = {foobar, " 662"}; - foobar = {foobar, " 663"}; - end - 7'h76: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 664"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 665"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 666"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 667"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 668"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 669"}; - end - 7'h77: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 670"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 671"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 672"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 673"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 674"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 675"}; - end - 7'h78, - 7'h79, - 7'h7a, - 7'h7b, - 7'h7c, - 7'h7d, - 7'h7e, - 7'h7f: - foobar = {foobar," 676"}; - endcase - end - endtask + task ozonef1e; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[27:21]) + 7'h00: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 234"}; + foobar = {foobar, " 235"}; + end + 7'h01: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 236"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 237"}; + foobar = {foobar, " 238"}; + end + 7'h02: foobar = {foobar, " 239"}; + 7'h03: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 240"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 241"}; + foobar = {foobar, " 242"}; + end + 7'h04: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 243"}; + foobar = {foobar, " 244"}; + end + 7'h05: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 245"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 246"}; + end + 7'h06: foobar = {foobar, " 247"}; + 7'h07: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 248"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 249"}; + end + 7'h08: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 250"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 251"}; + end + 7'h09: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 252"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 253"}; + end + 7'h0a: begin + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 254"}; + end + 7'h0b: begin + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 255"}; + end + 7'h0c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 256"}; + end + 7'h0d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 257"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 258"}; + end + 7'h0e: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 259"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 260"}; + end + 7'h0f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 261"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 262"}; + end + 7'h10: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 263"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 264"}; + foobar = {foobar, " 265"}; + foobar = {foobar, " 266"}; + end + 7'h11: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 267"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 268"}; + foobar = {foobar, " 269"}; + foobar = {foobar, " 270"}; + end + 7'h12: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 271"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 272"}; + foobar = {foobar, " 273"}; + foobar = {foobar, " 274"}; + end + 7'h13: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 275"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 276"}; + foobar = {foobar, " 277"}; + foobar = {foobar, " 278"}; + end + 7'h14: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 279"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 280"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 281"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 282"}; + foobar = {foobar, " 283"}; + foobar = {foobar, " 284"}; + end + 7'h15: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 285"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 286"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 287"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 288"}; + foobar = {foobar, " 289"}; + foobar = {foobar, " 290"}; + end + 7'h16: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 291"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 292"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 293"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 294"}; + foobar = {foobar, " 295"}; + foobar = {foobar, " 296"}; + end + 7'h17: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 297"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 298"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 299"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 300"}; + foobar = {foobar, " 301"}; + foobar = {foobar, " 302"}; + end + 7'h18: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 303"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 304"}; + foobar = {foobar, " 305"}; + foobar = {foobar, " 306"}; + end + 7'h19: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 307"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 308"}; + foobar = {foobar, " 309"}; + foobar = {foobar, " 310"}; + end + 7'h1a: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 311"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 312"}; + foobar = {foobar, " 313"}; + foobar = {foobar, " 314"}; + end + 7'h1b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 315"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 316"}; + foobar = {foobar, " 317"}; + foobar = {foobar, " 318"}; + end + 7'h1c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 319"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 320"}; + foobar = {foobar, " 321"}; + foobar = {foobar, " 322"}; + end + 7'h1d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 323"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 324"}; + foobar = {foobar, " 325"}; + foobar = {foobar, " 326"}; + end + 7'h1e: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 327"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 328"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 329"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 330"}; + foobar = {foobar, " 331"}; + foobar = {foobar, " 332"}; + end + 7'h1f: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 333"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 334"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 335"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 336"}; + foobar = {foobar, " 337"}; + foobar = {foobar, " 338"}; + end + 7'h20: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 339"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 340"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 341"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 342"}; + foobar = {foobar, " 343"}; + foobar = {foobar, " 344"}; + end + 7'h21: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 345"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 346"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 347"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 348"}; + foobar = {foobar, " 349"}; + foobar = {foobar, " 350"}; + end + 7'h22: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 351"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 352"}; + foobar = {foobar, " 353"}; + foobar = {foobar, " 354"}; + end + 7'h23: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 355"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 356"}; + foobar = {foobar, " 357"}; + foobar = {foobar, " 358"}; + end + 7'h24: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 359"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 360"}; + foobar = {foobar, " 361"}; + foobar = {foobar, " 362"}; + end + 7'h25: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 363"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 364"}; + foobar = {foobar, " 365"}; + foobar = {foobar, " 366"}; + end + 7'h26: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 367"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 368"}; + foobar = {foobar, " 369"}; + foobar = {foobar, " 370"}; + end + 7'h27: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 371"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 372"}; + foobar = {foobar, " 373"}; + foobar = {foobar, " 374"}; + end + 7'h28: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 375"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 376"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 377"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 378"}; + foobar = {foobar, " 379"}; + foobar = {foobar, " 380"}; + end + 7'h29: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 381"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 382"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 383"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 384"}; + foobar = {foobar, " 385"}; + foobar = {foobar, " 386"}; + end + 7'h2a: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 387"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 388"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 389"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 390"}; + foobar = {foobar, " 391"}; + foobar = {foobar, " 392"}; + end + 7'h2b: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 393"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 394"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 395"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 396"}; + foobar = {foobar, " 397"}; + foobar = {foobar, " 398"}; + end + 7'h2c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 399"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 400"}; + foobar = {foobar, " 401"}; + foobar = {foobar, " 402"}; + end + 7'h2d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 403"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 404"}; + foobar = {foobar, " 405"}; + foobar = {foobar, " 406"}; + end + 7'h2e: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 407"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 408"}; + foobar = {foobar, " 409"}; + foobar = {foobar, " 410"}; + end + 7'h2f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 411"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 412"}; + foobar = {foobar, " 413"}; + foobar = {foobar, " 414"}; + end + 7'h30: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 415"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 416"}; + foobar = {foobar, " 417"}; + foobar = {foobar, " 418"}; + end + 7'h31: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 419"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 420"}; + foobar = {foobar, " 421"}; + foobar = {foobar, " 422"}; + end + 7'h32: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 423"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 424"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 425"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 426"}; + foobar = {foobar, " 427"}; + foobar = {foobar, " 428"}; + end + 7'h33: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 429"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 430"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 431"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 432"}; + foobar = {foobar, " 433"}; + foobar = {foobar, " 434"}; + end + 7'h34: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 435"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 436"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 437"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 438"}; + foobar = {foobar, " 439"}; + foobar = {foobar, " 440"}; + end + 7'h35: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 441"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 442"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 443"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 444"}; + foobar = {foobar, " 445"}; + foobar = {foobar, " 446"}; + end + 7'h36: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 447"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 448"}; + foobar = {foobar, " 449"}; + foobar = {foobar, " 450"}; + end + 7'h37: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 451"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 452"}; + foobar = {foobar, " 453"}; + foobar = {foobar, " 454"}; + end + 7'h38: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 455"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 456"}; + foobar = {foobar, " 457"}; + end + 7'h39: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 458"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 459"}; + foobar = {foobar, " 460"}; + end + 7'h3a: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 461"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 462"}; + foobar = {foobar, " 463"}; + end + 7'h3b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 464"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 465"}; + foobar = {foobar, " 466"}; + end + 7'h3c: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 467"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 468"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 469"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 470"}; + foobar = {foobar, " 471"}; + end + 7'h3d: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 472"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 473"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 474"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 475"}; + foobar = {foobar, " 476"}; + end + 7'h3e: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 477"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 478"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 479"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 480"}; + foobar = {foobar, " 481"}; + end + 7'h3f: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 482"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 483"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 484"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 485"}; + foobar = {foobar, " 486"}; + end + 7'h40: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 487"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 488"}; + foobar = {foobar, " 489"}; + foobar = {foobar, " 490"}; + end + 7'h41: begin + foobar = {foobar, " 491"}; + foobar = {foobar, " 492"}; + end + 7'h42: begin + foobar = {foobar, " 493"}; + foobar = {foobar, " 494"}; + end + 7'h43: begin + foobar = {foobar, " 495"}; + foobar = {foobar, " 496"}; + end + 7'h44: begin + foobar = {foobar, " 497"}; + foobar = {foobar, " 498"}; + end + 7'h45: foobar = {foobar, " 499"}; + 7'h46: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 500"}; + foobar = {foobar, " 501"}; + foobar = {foobar, " 502"}; + end + 7'h47: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 503"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 504"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 505"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 506"}; + foobar = {foobar, " 507"}; + foobar = {foobar, " 508"}; + end + 7'h48: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 509"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 510"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 511"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 512"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 513"}; + end + 7'h49: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 514"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 515"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 516"}; + end + 7'h4a: foobar = {foobar, " 517"}; + 7'h4b: foobar = {foobar, " 518"}; + 7'h4c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 519"}; + foobar = {foobar, " 520"}; + foobar = {foobar, " 521"}; + end + 7'h4d: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 522"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 523"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 524"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 525"}; + foobar = {foobar, " 526"}; + foobar = {foobar, " 527"}; + end + 7'h4e: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 528"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 529"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 530"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 531"}; + end + 7'h4f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 532"}; + end + 7'h50: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 533"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 534"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 535"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 536"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 537"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 538"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 539"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 540"}; + end + 7'h51: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 541"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 542"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 543"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 544"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 545"}; + end + 7'h52: foobar = {foobar, " 546"}; + 7'h53: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 547"}; + end + 7'h54: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 548"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 549"}; + end + 7'h55: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 550"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 551"}; + end + 7'h56: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 552"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 553"}; + foobar = {foobar, " 554"}; + end + 7'h57: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 555"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 556"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 557"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 558"}; + end + 7'h58: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 559"}; + end + 7'h59: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 560"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 561"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 562"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 563"}; + end + 7'h5a: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 564"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 565"}; + end + 7'h5b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 566"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 567"}; + end + 7'h5c: begin + foobar = {foobar, " 568"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 569"}; + foobar = {foobar, " 570"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 571"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 572"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 573"}; + end + 7'h5d: begin + foobar = {foobar, " 574"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 575"}; + foobar = {foobar, " 576"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 577"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 578"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 579"}; + end + 7'h5e: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 580"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 581"}; + end + 7'h5f: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 582"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 583"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 584"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 585"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 586"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 587"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 588"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 589"}; + end + 7'h60: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 590"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 591"}; + end + 7'h61: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 592"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 593"}; + end + 7'h62: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 594"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 595"}; + end + 7'h63: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 596"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 597"}; + end + 7'h64: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 598"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 599"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 600"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 601"}; + end + 7'h65: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 602"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 603"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 604"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 605"}; + end + 7'h66: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 606"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 607"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 608"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 609"}; + end + 7'h67: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 610"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 611"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 612"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 613"}; + end + 7'h68: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 614"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 615"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 616"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 617"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 618"}; + ozoneape(foo[17:15], foobar); + end + 7'h69: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 619"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 620"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 621"}; + end + 7'h6a: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 622"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 623"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 624"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 625"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 626"}; + ozoneae(foo[17:15], foobar); + end + 7'h6b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 627"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 628"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 629"}; + end + 7'h6c: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 630"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 631"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 632"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 633"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 634"}; + ozoneae(foo[17:15], foobar); + end + 7'h6d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 635"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 636"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 637"}; + end + 7'h6e: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 638"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 639"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 640"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 641"}; + end + 7'h6f: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 642"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 643"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 644"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 645"}; + end + 7'h70: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 646"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 647"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 648"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 649"}; + end + 7'h71: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 650"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 651"}; + end + 7'h72: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 652"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 653"}; + end + 7'h73: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 654"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 655"}; + ozoneae(foo[17:15], foobar); + end + 7'h74: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 656"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 657"}; + ozoneae(foo[17:15], foobar); + end + 7'h75: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 658"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 659"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 660"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 661"}; + foobar = {foobar, " 662"}; + foobar = {foobar, " 663"}; + end + 7'h76: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 664"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 665"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 666"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 667"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 668"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 669"}; + end + 7'h77: begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar, " 670"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 671"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 672"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar, " 673"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 674"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar, " 675"}; + end + 7'h78, 7'h79, 7'h7a, 7'h7b, 7'h7c, 7'h7d, 7'h7e, 7'h7f: foobar = {foobar, " 676"}; + endcase + end + endtask - task ozonef2; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[24:21]) - 4'h0 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 677"}; - 2'b01 : foobar = {foobar," 678"}; - 2'b10 : foobar = {foobar," 679"}; - 2'b11 : foobar = {foobar," 680"}; - endcase - 4'h1 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 681"}; - 2'b01 : foobar = {foobar," 682"}; - 2'b10 : foobar = {foobar," 683"}; - 2'b11 : foobar = {foobar," 684"}; - endcase - 4'h2 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 685"}; - 2'b01 : foobar = {foobar," 686"}; - 2'b10 : foobar = {foobar," 687"}; - 2'b11 : foobar = {foobar," 688"}; - endcase - 4'h3 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 689"}; - 2'b01 : foobar = {foobar," 690"}; - 2'b10 : foobar = {foobar," 691"}; - 2'b11 : foobar = {foobar," 692"}; - endcase - 4'h4 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 693"}; - 2'b01 : foobar = {foobar," 694"}; - 2'b10 : foobar = {foobar," 695"}; - 2'b11 : foobar = {foobar," 696"}; - endcase - 4'h5 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 697"}; - 2'b01 : foobar = {foobar," 698"}; - 2'b10 : foobar = {foobar," 699"}; - 2'b11 : foobar = {foobar," 700"}; - endcase - 4'h6 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 701"}; - 2'b01 : foobar = {foobar," 702"}; - 2'b10 : foobar = {foobar," 703"}; - 2'b11 : foobar = {foobar," 704"}; - endcase - 4'h7 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 705"}; - 2'b01 : foobar = {foobar," 706"}; - 2'b10 : foobar = {foobar," 707"}; - 2'b11 : foobar = {foobar," 708"}; - endcase - 4'h8 : - if (foo[26]) - foobar = {foobar," 709"}; - else - foobar = {foobar," 710"}; - 4'h9 : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 711"}; - 2'b01 : foobar = {foobar," 712"}; - 2'b10 : foobar = {foobar," 713"}; - 2'b11 : foobar = {foobar," 714"}; - endcase - 4'ha : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 715"}; - 2'b01 : foobar = {foobar," 716"}; - 2'b10 : foobar = {foobar," 717"}; - 2'b11 : foobar = {foobar," 718"}; - endcase - 4'hb : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 719"}; - 2'b01 : foobar = {foobar," 720"}; - 2'b10 : foobar = {foobar," 721"}; - 2'b11 : foobar = {foobar," 722"}; - endcase - 4'hc : - if (foo[26]) - foobar = {foobar," 723"}; - else - foobar = {foobar," 724"}; - 4'hd : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 725"}; - 2'b01 : foobar = {foobar," 726"}; - 2'b10 : foobar = {foobar," 727"}; - 2'b11 : foobar = {foobar," 728"}; - endcase - 4'he : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 729"}; - 2'b01 : foobar = {foobar," 730"}; - 2'b10 : foobar = {foobar," 731"}; - 2'b11 : foobar = {foobar," 732"}; - endcase - 4'hf : - case (foo[26:25]) - 2'b00 : foobar = {foobar," 733"}; - 2'b01 : foobar = {foobar," 734"}; - 2'b10 : foobar = {foobar," 735"}; - 2'b11 : foobar = {foobar," 736"}; - endcase - endcase - end - endtask + task ozonef2; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 677"}; + 2'b01: foobar = {foobar, " 678"}; + 2'b10: foobar = {foobar, " 679"}; + 2'b11: foobar = {foobar, " 680"}; + endcase + 4'h1: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 681"}; + 2'b01: foobar = {foobar, " 682"}; + 2'b10: foobar = {foobar, " 683"}; + 2'b11: foobar = {foobar, " 684"}; + endcase + 4'h2: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 685"}; + 2'b01: foobar = {foobar, " 686"}; + 2'b10: foobar = {foobar, " 687"}; + 2'b11: foobar = {foobar, " 688"}; + endcase + 4'h3: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 689"}; + 2'b01: foobar = {foobar, " 690"}; + 2'b10: foobar = {foobar, " 691"}; + 2'b11: foobar = {foobar, " 692"}; + endcase + 4'h4: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 693"}; + 2'b01: foobar = {foobar, " 694"}; + 2'b10: foobar = {foobar, " 695"}; + 2'b11: foobar = {foobar, " 696"}; + endcase + 4'h5: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 697"}; + 2'b01: foobar = {foobar, " 698"}; + 2'b10: foobar = {foobar, " 699"}; + 2'b11: foobar = {foobar, " 700"}; + endcase + 4'h6: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 701"}; + 2'b01: foobar = {foobar, " 702"}; + 2'b10: foobar = {foobar, " 703"}; + 2'b11: foobar = {foobar, " 704"}; + endcase + 4'h7: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 705"}; + 2'b01: foobar = {foobar, " 706"}; + 2'b10: foobar = {foobar, " 707"}; + 2'b11: foobar = {foobar, " 708"}; + endcase + 4'h8: + if (foo[26]) foobar = {foobar, " 709"}; + else foobar = {foobar, " 710"}; + 4'h9: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 711"}; + 2'b01: foobar = {foobar, " 712"}; + 2'b10: foobar = {foobar, " 713"}; + 2'b11: foobar = {foobar, " 714"}; + endcase + 4'ha: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 715"}; + 2'b01: foobar = {foobar, " 716"}; + 2'b10: foobar = {foobar, " 717"}; + 2'b11: foobar = {foobar, " 718"}; + endcase + 4'hb: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 719"}; + 2'b01: foobar = {foobar, " 720"}; + 2'b10: foobar = {foobar, " 721"}; + 2'b11: foobar = {foobar, " 722"}; + endcase + 4'hc: + if (foo[26]) foobar = {foobar, " 723"}; + else foobar = {foobar, " 724"}; + 4'hd: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 725"}; + 2'b01: foobar = {foobar, " 726"}; + 2'b10: foobar = {foobar, " 727"}; + 2'b11: foobar = {foobar, " 728"}; + endcase + 4'he: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 729"}; + 2'b01: foobar = {foobar, " 730"}; + 2'b10: foobar = {foobar, " 731"}; + 2'b11: foobar = {foobar, " 732"}; + endcase + 4'hf: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 733"}; + 2'b01: foobar = {foobar, " 734"}; + 2'b10: foobar = {foobar, " 735"}; + 2'b11: foobar = {foobar, " 736"}; + endcase + endcase + end + endtask - task ozonef2e; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - casez (foo[25:21]) - 5'h00 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 737"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 738"}; - end - 5'h01 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 739"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 740"}; - end - 5'h02 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 741"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 742"}; - end - 5'h03 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 743"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 744"}; - end - 5'h04 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 745"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 746"}; - end - 5'h05 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 747"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 748"}; - end - 5'h06 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 749"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 750"}; - end - 5'h07 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 751"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 752"}; - end - 5'h08 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 753"}; - if (foo[ 6]) - foobar = {foobar," 754"}; - else - foobar = {foobar," 755"}; - end - 5'h09 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 756"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 757"}; - end - 5'h0a : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 758"}; - ozoneae(foo[17:15], foobar); - end - 5'h0b : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 759"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 760"}; - end - 5'h0c : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 761"}; - end - 5'h0d : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 762"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 763"}; - end - 5'h0e : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 764"}; - ozoneae(foo[17:15], foobar); - end - 5'h0f : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 765"}; - ozoneae(foo[17:15], foobar); - end - 5'h10 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 766"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 767"}; - end - 5'h11 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 768"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 769"}; - end - 5'h18 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 770"}; - if (foo[ 6]) - foobar = {foobar," 771"}; - else - foobar = {foobar," 772"}; - end - 5'h1a : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 773"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 774"}; - end - 5'h1b : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 775"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 776"}; - if (foo[ 6]) - foobar = {foobar," 777"}; - else - foobar = {foobar," 778"}; - foobar = {foobar," 779"}; - end - 5'h1c : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 780"}; - end - 5'h1d : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 781"}; - if (foo[ 6]) - foobar = {foobar," 782"}; - else - foobar = {foobar," 783"}; - foobar = {foobar," 784"}; - end - 5'h1e : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 785"}; - if (foo[ 6]) - foobar = {foobar," 786"}; - else - foobar = {foobar," 787"}; - foobar = {foobar," 788"}; - end - 5'h1f : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 789"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 790"}; - if (foo[ 6]) - foobar = {foobar," 791"}; - else - foobar = {foobar," 792"}; - foobar = {foobar," 793"}; - end - default : - foobar = {foobar," 794"}; - endcase - end - endtask + task ozonef2e; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + casez (foo[25:21]) + 5'h00: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 737"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 738"}; + end + 5'h01: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 739"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 740"}; + end + 5'h02: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 741"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 742"}; + end + 5'h03: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 743"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 744"}; + end + 5'h04: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 745"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 746"}; + end + 5'h05: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 747"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 748"}; + end + 5'h06: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 749"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 750"}; + end + 5'h07: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 751"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 752"}; + end + 5'h08: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 753"}; + if (foo[6]) foobar = {foobar, " 754"}; + else foobar = {foobar, " 755"}; + end + 5'h09: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 756"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 757"}; + end + 5'h0a: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 758"}; + ozoneae(foo[17:15], foobar); + end + 5'h0b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 759"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 760"}; + end + 5'h0c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 761"}; + end + 5'h0d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 762"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 763"}; + end + 5'h0e: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 764"}; + ozoneae(foo[17:15], foobar); + end + 5'h0f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 765"}; + ozoneae(foo[17:15], foobar); + end + 5'h10: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 766"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 767"}; + end + 5'h11: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 768"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 769"}; + end + 5'h18: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 770"}; + if (foo[6]) foobar = {foobar, " 771"}; + else foobar = {foobar, " 772"}; + end + 5'h1a: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 773"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 774"}; + end + 5'h1b: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 775"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 776"}; + if (foo[6]) foobar = {foobar, " 777"}; + else foobar = {foobar, " 778"}; + foobar = {foobar, " 779"}; + end + 5'h1c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 780"}; + end + 5'h1d: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 781"}; + if (foo[6]) foobar = {foobar, " 782"}; + else foobar = {foobar, " 783"}; + foobar = {foobar, " 784"}; + end + 5'h1e: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 785"}; + if (foo[6]) foobar = {foobar, " 786"}; + else foobar = {foobar, " 787"}; + foobar = {foobar, " 788"}; + end + 5'h1f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 789"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 790"}; + if (foo[6]) foobar = {foobar, " 791"}; + else foobar = {foobar, " 792"}; + foobar = {foobar, " 793"}; + end + default: foobar = {foobar, " 794"}; + endcase + end + endtask - task ozonef3e; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[25:21]) - 5'h00, - 5'h01, - 5'h02: - begin - ozoneae(foo[20:18], foobar); - case (foo[22:21]) - 2'h0: foobar = {foobar," 795"}; - 2'h1: foobar = {foobar," 796"}; - 2'h2: foobar = {foobar," 797"}; - endcase - ozoneae(foo[17:15], foobar); - foobar = {foobar," 798"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - foobar = {foobar," 799"}; - end - 5'h08, - 5'h09, - 5'h0d, - 5'h0e, - 5'h0f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 800"}; - ozoneae(foo[17:15], foobar); - case (foo[23:21]) - 3'h0: foobar = {foobar," 801"}; - 3'h1: foobar = {foobar," 802"}; - 3'h5: foobar = {foobar," 803"}; - 3'h6: foobar = {foobar," 804"}; - 3'h7: foobar = {foobar," 805"}; - endcase - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - end - 5'h0a, - 5'h0b: - begin - ozoneae(foo[17:15], foobar); - if (foo[21]) - foobar = {foobar," 806"}; - else - foobar = {foobar," 807"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - end - 5'h0c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 808"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - foobar = {foobar," 809"}; - ozoneae(foo[17:15], foobar); - end - 5'h10, - 5'h11, - 5'h12, - 5'h13: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 810"}; - ozoneae(foo[17:15], foobar); - case (foo[22:21]) - 2'h0, - 2'h2: - foobar = {foobar," 811"}; - 2'h1, - 2'h3: - foobar = {foobar," 812"}; - endcase - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar," 813"}; - ozoneae((foo[20:18]+1), foobar); - foobar = {foobar," 814"}; - ozoneae((foo[17:15]+1), foobar); - case (foo[22:21]) - 2'h0, - 2'h3: - foobar = {foobar," 815"}; - 2'h1, - 2'h2: - foobar = {foobar," 816"}; - endcase - ozoneae((foo[ 8: 6]+1), foobar); - end - 5'h18: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 817"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 818"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar," 819"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 820"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 821"}; - ozoneae(foo[ 8: 6], foobar); - end - default : - foobar = {foobar," 822"}; - endcase + task ozonef3e; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[25:21]) + 5'h00, 5'h01, 5'h02: begin + ozoneae(foo[20:18], foobar); + case (foo[22:21]) + 2'h0: foobar = {foobar, " 795"}; + 2'h1: foobar = {foobar, " 796"}; + 2'h2: foobar = {foobar, " 797"}; + endcase + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 798"}; + if (foo[9]) ozoneae(foo[8:6], foobar); + else ozonef3e_te(foo[8:6], foobar); + foobar = {foobar, " 799"}; + end + 5'h08, 5'h09, 5'h0d, 5'h0e, 5'h0f: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 800"}; + ozoneae(foo[17:15], foobar); + case (foo[23:21]) + 3'h0: foobar = {foobar, " 801"}; + 3'h1: foobar = {foobar, " 802"}; + 3'h5: foobar = {foobar, " 803"}; + 3'h6: foobar = {foobar, " 804"}; + 3'h7: foobar = {foobar, " 805"}; + endcase + if (foo[9]) ozoneae(foo[8:6], foobar); + else ozonef3e_te(foo[8:6], foobar); + end + 5'h0a, 5'h0b: begin + ozoneae(foo[17:15], foobar); + if (foo[21]) foobar = {foobar, " 806"}; + else foobar = {foobar, " 807"}; + if (foo[9]) ozoneae(foo[8:6], foobar); + else ozonef3e_te(foo[8:6], foobar); + end + 5'h0c: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 808"}; + if (foo[9]) ozoneae(foo[8:6], foobar); + else ozonef3e_te(foo[8:6], foobar); + foobar = {foobar, " 809"}; + ozoneae(foo[17:15], foobar); + end + 5'h10, 5'h11, 5'h12, 5'h13: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 810"}; + ozoneae(foo[17:15], foobar); + case (foo[22:21]) + 2'h0, 2'h2: foobar = {foobar, " 811"}; + 2'h1, 2'h3: foobar = {foobar, " 812"}; + endcase + ozoneae(foo[8:6], foobar); + foobar = {foobar, " 813"}; + ozoneae((foo[20:18] + 1), foobar); + foobar = {foobar, " 814"}; + ozoneae((foo[17:15] + 1), foobar); + case (foo[22:21]) + 2'h0, 2'h3: foobar = {foobar, " 815"}; + 2'h1, 2'h2: foobar = {foobar, " 816"}; + endcase + ozoneae((foo[8:6] + 1), foobar); + end + 5'h18: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 817"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 818"}; + ozoneae(foo[8:6], foobar); + foobar = {foobar, " 819"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 820"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 821"}; + ozoneae(foo[8:6], foobar); + end + default: foobar = {foobar, " 822"}; + endcase + end + endtask + task ozonef3e_te; + input [2:0] te; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (te) + 3'b100: foobar = {foobar, " 823"}; + 3'b101: foobar = {foobar, " 824"}; + 3'b110: foobar = {foobar, " 825"}; + default: foobar = {foobar, " 826"}; + endcase + end + endtask + task ozonearm; + input [2:0] ate; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (ate) + 3'b000: foobar = {foobar, " 827"}; + 3'b001: foobar = {foobar, " 828"}; + 3'b010: foobar = {foobar, " 829"}; + 3'b011: foobar = {foobar, " 830"}; + 3'b100: foobar = {foobar, " 831"}; + 3'b101: foobar = {foobar, " 832"}; + 3'b110: foobar = {foobar, " 833"}; + 3'b111: foobar = {foobar, " 834"}; + endcase + end + endtask + task ozonebmuop; + input [4:0] f4; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (f4[4:0]) + 5'h00, 5'h04: foobar = {foobar, " 835"}; + 5'h01, 5'h05: foobar = {foobar, " 836"}; + 5'h02, 5'h06: foobar = {foobar, " 837"}; + 5'h03, 5'h07: foobar = {foobar, " 838"}; + 5'h08, 5'h18: foobar = {foobar, " 839"}; + 5'h09, 5'h19: foobar = {foobar, " 840"}; + 5'h0a, 5'h1a: foobar = {foobar, " 841"}; + 5'h0b: foobar = {foobar, " 842"}; + 5'h1b: foobar = {foobar, " 843"}; + 5'h0c, 5'h1c: foobar = {foobar, " 844"}; + 5'h0d, 5'h1d: foobar = {foobar, " 845"}; + 5'h1e: foobar = {foobar, " 846"}; + endcase + end + endtask + task automatic ozonef3; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + reg nacho; + // verilator no_inline_task + begin : f3_body + nacho = 1'b0; + case (foo[24:21]) + 4'h0: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 847"}; + 2'b01: foobar = {foobar, " 848"}; + 2'b10: foobar = {foobar, " 849"}; + 2'b11: foobar = {foobar, " 850"}; + endcase + 4'h1: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 851"}; + 2'b01: foobar = {foobar, " 852"}; + 2'b10: foobar = {foobar, " 853"}; + 2'b11: foobar = {foobar, " 854"}; + endcase + 4'h2: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 855"}; + 2'b01: foobar = {foobar, " 856"}; + 2'b10: foobar = {foobar, " 857"}; + 2'b11: foobar = {foobar, " 858"}; + endcase + 4'h8, 4'h9, 4'hd, 4'he, 4'hf: + case (foo[26:25]) + 2'b00: foobar = {foobar, " 859"}; + 2'b01: foobar = {foobar, " 860"}; + 2'b10: foobar = {foobar, " 861"}; + 2'b11: foobar = {foobar, " 862"}; + endcase + 4'ha, 4'hb: + if (foo[25]) foobar = {foobar, " 863"}; + else foobar = {foobar, " 864"}; + 4'hc: + if (foo[26]) foobar = {foobar, " 865"}; + else foobar = {foobar, " 866"}; + default: begin + foobar = {foobar, " 867"}; + nacho = 1'b1; + end + endcase + if (~nacho) begin + case (foo[24:21]) + 4'h8: foobar = {foobar, " 868"}; + 4'h9: foobar = {foobar, " 869"}; + 4'ha, 4'he: foobar = {foobar, " 870"}; + 4'hb, 4'hf: foobar = {foobar, " 871"}; + 4'hd: foobar = {foobar, " 872"}; + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000: foobar = {foobar, " 873"}; + 3'b100: foobar = {foobar, " 874"}; + default: foobar = {foobar, " 875"}; + endcase + else ozoneae(foo[18:16], foobar); + if (foo[24:21] === 4'hc) + if (foo[25]) foobar = {foobar, " 876"}; + else foobar = {foobar, " 877"}; + case (foo[24:21]) + 4'h0, 4'h1, 4'h2: foobar = {foobar, " 878"}; + endcase end - endtask - task ozonef3e_te; - input [ 2:0] te; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (te) - 3'b100 : foobar = {foobar, " 823"}; - 3'b101 : foobar = {foobar, " 824"}; - 3'b110 : foobar = {foobar, " 825"}; - default: foobar = {foobar, " 826"}; - endcase + end + endtask + task ozonerx; + input [31:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[19:18]) + 2'h0: foobar = {foobar, " 879"}; + 2'h1: foobar = {foobar, " 880"}; + 2'h2: foobar = {foobar, " 881"}; + 2'h3: foobar = {foobar, " 882"}; + endcase + case (foo[17:16]) + 2'h1: foobar = {foobar, " 883"}; + 2'h2: foobar = {foobar, " 884"}; + 2'h3: foobar = {foobar, " 885"}; + endcase + end + endtask + task ozonerme; + input [2:0] rme; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (rme) + 3'h0: foobar = {foobar, " 886"}; + 3'h1: foobar = {foobar, " 887"}; + 3'h2: foobar = {foobar, " 888"}; + 3'h3: foobar = {foobar, " 889"}; + 3'h4: foobar = {foobar, " 890"}; + 3'h5: foobar = {foobar, " 891"}; + 3'h6: foobar = {foobar, " 892"}; + 3'h7: foobar = {foobar, " 893"}; + endcase + end + endtask + task ozoneye; + input [5:0] ye; + input l; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + foobar = {foobar, " 894"}; + ozonerme(ye[5:3], foobar); + case ({ + ye[2:0], l + }) + 4'h2, 4'ha: foobar = {foobar, " 895"}; + 4'h4, 4'hb: foobar = {foobar, " 896"}; + 4'h6, 4'he: foobar = {foobar, " 897"}; + 4'h8, 4'hc: foobar = {foobar, " 898"}; + endcase + end + endtask + task ozonef1e_ye; + input [5:0] ye; + input l; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + foobar = {foobar, " 899"}; + ozonerme(ye[5:3], foobar); + ozonef1e_inc_dec(ye[5:0], l, foobar); + end + endtask + task ozonef1e_h; + input [2:0] e; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + if (e[2:0] <= 3'h4) foobar = {foobar, " 900"}; + end + endtask + task ozonef1e_inc_dec; + input [5:0] ye; + input l; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case ({ + ye[2:0], l + }) + 4'h2, 4'h3, 4'ha: foobar = {foobar, " 901"}; + 4'h4, 4'h5, 4'hb: foobar = {foobar, " 902"}; + 4'h6, 4'h7, 4'he: foobar = {foobar, " 903"}; + 4'h8, 4'h9, 4'hc: foobar = {foobar, " 904"}; + 4'hf: foobar = {foobar, " 905"}; + endcase + end + endtask + task ozonef1e_hl; + input [2:0] e; + input l; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case ({ + e[2:0], l + }) + 4'h0, 4'h2, 4'h4, 4'h6, 4'h8: foobar = {foobar, " 906"}; + 4'h1, 4'h3, 4'h5, 4'h7, 4'h9: foobar = {foobar, " 907"}; + endcase + end + endtask + task ozonexe; + input [3:0] xe; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (xe[3]) + 1'b0: foobar = {foobar, " 908"}; + 1'b1: foobar = {foobar, " 909"}; + endcase + case (xe[2:0]) + 3'h1, 3'h5: foobar = {foobar, " 910"}; + 3'h2, 3'h6: foobar = {foobar, " 911"}; + 3'h3, 3'h7: foobar = {foobar, " 912"}; + 3'h4: foobar = {foobar, " 913"}; + endcase + end + endtask + task ozonerp; + input [2:0] rp; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (rp) + 3'h0: foobar = {foobar, " 914"}; + 3'h1: foobar = {foobar, " 915"}; + 3'h2: foobar = {foobar, " 916"}; + 3'h3: foobar = {foobar, " 917"}; + 3'h4: foobar = {foobar, " 918"}; + 3'h5: foobar = {foobar, " 919"}; + 3'h6: foobar = {foobar, " 920"}; + 3'h7: foobar = {foobar, " 921"}; + endcase + end + endtask + task ozonery; + input [3:0] ry; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (ry) + 4'h0: foobar = {foobar, " 922"}; + 4'h1: foobar = {foobar, " 923"}; + 4'h2: foobar = {foobar, " 924"}; + 4'h3: foobar = {foobar, " 925"}; + 4'h4: foobar = {foobar, " 926"}; + 4'h5: foobar = {foobar, " 927"}; + 4'h6: foobar = {foobar, " 928"}; + 4'h7: foobar = {foobar, " 929"}; + 4'h8: foobar = {foobar, " 930"}; + 4'h9: foobar = {foobar, " 931"}; + 4'ha: foobar = {foobar, " 932"}; + 4'hb: foobar = {foobar, " 933"}; + 4'hc: foobar = {foobar, " 934"}; + 4'hd: foobar = {foobar, " 935"}; + 4'he: foobar = {foobar, " 936"}; + 4'hf: foobar = {foobar, " 937"}; + endcase + end + endtask + task ozonearx; + input [15:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[1:0]) + 2'h0: foobar = {foobar, " 938"}; + 2'h1: foobar = {foobar, " 939"}; + 2'h2: foobar = {foobar, " 940"}; + 2'h3: foobar = {foobar, " 941"}; + endcase + end + endtask + task ozonef3f4imop; + input [4:0] f3f4iml; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + casez (f3f4iml) + 5'b000??: foobar = {foobar, " 942"}; + 5'b001??: foobar = {foobar, " 943"}; + 5'b?10??: foobar = {foobar, " 944"}; + 5'b0110?: foobar = {foobar, " 945"}; + 5'b01110: foobar = {foobar, " 946"}; + 5'b01111: foobar = {foobar, " 947"}; + 5'b10???: foobar = {foobar, " 948"}; + 5'b11100: foobar = {foobar, " 949"}; + 5'b11101: foobar = {foobar, " 950"}; + 5'b11110: foobar = {foobar, " 951"}; + 5'b11111: foobar = {foobar, " 952"}; + endcase + end + endtask + task ozonecon; + input [4:0] con; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (con) + 5'h00: foobar = {foobar, " 953"}; + 5'h01: foobar = {foobar, " 954"}; + 5'h02: foobar = {foobar, " 955"}; + 5'h03: foobar = {foobar, " 956"}; + 5'h04: foobar = {foobar, " 957"}; + 5'h05: foobar = {foobar, " 958"}; + 5'h06: foobar = {foobar, " 959"}; + 5'h07: foobar = {foobar, " 960"}; + 5'h08: foobar = {foobar, " 961"}; + 5'h09: foobar = {foobar, " 962"}; + 5'h0a: foobar = {foobar, " 963"}; + 5'h0b: foobar = {foobar, " 964"}; + 5'h0c: foobar = {foobar, " 965"}; + 5'h0d: foobar = {foobar, " 966"}; + 5'h0e: foobar = {foobar, " 967"}; + 5'h0f: foobar = {foobar, " 968"}; + 5'h10: foobar = {foobar, " 969"}; + 5'h11: foobar = {foobar, " 970"}; + 5'h12: foobar = {foobar, " 971"}; + 5'h13: foobar = {foobar, " 972"}; + 5'h14: foobar = {foobar, " 973"}; + 5'h15: foobar = {foobar, " 974"}; + 5'h16: foobar = {foobar, " 975"}; + 5'h17: foobar = {foobar, " 976"}; + 5'h18: foobar = {foobar, " 977"}; + 5'h19: foobar = {foobar, " 978"}; + 5'h1a: foobar = {foobar, " 979"}; + 5'h1b: foobar = {foobar, " 980"}; + 5'h1c: foobar = {foobar, " 981"}; + 5'h1d: foobar = {foobar, " 982"}; + 5'h1e: foobar = {foobar, " 983"}; + 5'h1f: foobar = {foobar, " 984"}; + endcase + end + endtask + task ozonedr; + input [15:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[9:6]) + 4'h0: foobar = {foobar, " 985"}; + 4'h1: foobar = {foobar, " 986"}; + 4'h2: foobar = {foobar, " 987"}; + 4'h3: foobar = {foobar, " 988"}; + 4'h4: foobar = {foobar, " 989"}; + 4'h5: foobar = {foobar, " 990"}; + 4'h6: foobar = {foobar, " 991"}; + 4'h7: foobar = {foobar, " 992"}; + 4'h8: foobar = {foobar, " 993"}; + 4'h9: foobar = {foobar, " 994"}; + 4'ha: foobar = {foobar, " 995"}; + 4'hb: foobar = {foobar, " 996"}; + 4'hc: foobar = {foobar, " 997"}; + 4'hd: foobar = {foobar, " 998"}; + 4'he: foobar = {foobar, " 999"}; + 4'hf: foobar = {foobar, " 1000"}; + endcase + end + endtask + task ozoneshift; + input [15:0] foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo[4:3]) + 2'h0: foobar = {foobar, " 1001"}; + 2'h1: foobar = {foobar, " 1002"}; + 2'h2: foobar = {foobar, " 1003"}; + 2'h3: foobar = {foobar, " 1004"}; + endcase + end + endtask + task ozoneacc; + input foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0: foobar = {foobar, " 1005"}; + 2'h1: foobar = {foobar, " 1006"}; + endcase + end + endtask + task ozonehl; + input foo; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0: foobar = {foobar, " 1007"}; + 2'h1: foobar = {foobar, " 1008"}; + endcase + end + endtask + task automatic dude; + inout [STRLEN*8:1] foobar; + reg [7:0] temp; + integer i; + reg nacho; + // verilator no_inline_task + begin : justify_block + nacho = 1'b0; + for (i = STRLEN - 1; i > 1; i = i - 1) begin + temp = foobar >> ((STRLEN - 1) * 8); + if (temp || nacho) nacho = 1'b1; + else begin + foobar = foobar << 8; + foobar[8:1] = 32; + end end - endtask - task ozonearm; - input [ 2:0] ate; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (ate) - 3'b000 : foobar = {foobar, " 827"}; - 3'b001 : foobar = {foobar, " 828"}; - 3'b010 : foobar = {foobar, " 829"}; - 3'b011 : foobar = {foobar, " 830"}; - 3'b100 : foobar = {foobar, " 831"}; - 3'b101 : foobar = {foobar, " 832"}; - 3'b110 : foobar = {foobar, " 833"}; - 3'b111 : foobar = {foobar, " 834"}; - endcase - end - endtask - task ozonebmuop; - input [ 4:0] f4; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (f4[ 4:0]) - 5'h00, - 5'h04 : - foobar = {foobar, " 835"}; - 5'h01, - 5'h05 : - foobar = {foobar, " 836"}; - 5'h02, - 5'h06 : - foobar = {foobar, " 837"}; - 5'h03, - 5'h07 : - foobar = {foobar, " 838"}; - 5'h08, - 5'h18 : - foobar = {foobar, " 839"}; - 5'h09, - 5'h19 : - foobar = {foobar, " 840"}; - 5'h0a, - 5'h1a : - foobar = {foobar, " 841"}; - 5'h0b : - foobar = {foobar, " 842"}; - 5'h1b : - foobar = {foobar, " 843"}; - 5'h0c, - 5'h1c : - foobar = {foobar, " 844"}; - 5'h0d, - 5'h1d : - foobar = {foobar, " 845"}; - 5'h1e : - foobar = {foobar, " 846"}; - endcase - end - endtask - task automatic ozonef3; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - reg nacho; - // verilator no_inline_task - begin : f3_body - nacho = 1'b0; - case (foo[24:21]) - 4'h0: - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 847"}; - 2'b01 : foobar = {foobar, " 848"}; - 2'b10 : foobar = {foobar, " 849"}; - 2'b11 : foobar = {foobar, " 850"}; - endcase - 4'h1: - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 851"}; - 2'b01 : foobar = {foobar, " 852"}; - 2'b10 : foobar = {foobar, " 853"}; - 2'b11 : foobar = {foobar, " 854"}; - endcase - 4'h2: - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 855"}; - 2'b01 : foobar = {foobar, " 856"}; - 2'b10 : foobar = {foobar, " 857"}; - 2'b11 : foobar = {foobar, " 858"}; - endcase - 4'h8, - 4'h9, - 4'hd, - 4'he, - 4'hf : - case (foo[26:25]) - 2'b00 : foobar = {foobar, " 859"}; - 2'b01 : foobar = {foobar, " 860"}; - 2'b10 : foobar = {foobar, " 861"}; - 2'b11 : foobar = {foobar, " 862"}; - endcase - 4'ha, - 4'hb : - if (foo[25]) - foobar = {foobar, " 863"}; - else - foobar = {foobar, " 864"}; - 4'hc : - if (foo[26]) - foobar = {foobar, " 865"}; - else - foobar = {foobar, " 866"}; - default : - begin - foobar = {foobar, " 867"}; - nacho = 1'b1; - end - endcase - if (~nacho) - begin - case (foo[24:21]) - 4'h8 : - foobar = {foobar, " 868"}; - 4'h9 : - foobar = {foobar, " 869"}; - 4'ha, - 4'he : - foobar = {foobar, " 870"}; - 4'hb, - 4'hf : - foobar = {foobar, " 871"}; - 4'hd : - foobar = {foobar, " 872"}; - endcase - if (foo[20]) - case (foo[18:16]) - 3'b000 : foobar = {foobar, " 873"}; - 3'b100 : foobar = {foobar, " 874"}; - default: foobar = {foobar, " 875"}; - endcase - else - ozoneae(foo[18:16], foobar); - if (foo[24:21] === 4'hc) - if (foo[25]) - foobar = {foobar, " 876"}; - else - foobar = {foobar, " 877"}; - case (foo[24:21]) - 4'h0, - 4'h1, - 4'h2: - foobar = {foobar, " 878"}; - endcase - end - end - endtask - task ozonerx; - input [ 31:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[19:18]) - 2'h0 : foobar = {foobar, " 879"}; - 2'h1 : foobar = {foobar, " 880"}; - 2'h2 : foobar = {foobar, " 881"}; - 2'h3 : foobar = {foobar, " 882"}; - endcase - case (foo[17:16]) - 2'h1 : foobar = {foobar, " 883"}; - 2'h2 : foobar = {foobar, " 884"}; - 2'h3 : foobar = {foobar, " 885"}; - endcase - end - endtask - task ozonerme; - input [ 2:0] rme; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (rme) - 3'h0 : foobar = {foobar, " 886"}; - 3'h1 : foobar = {foobar, " 887"}; - 3'h2 : foobar = {foobar, " 888"}; - 3'h3 : foobar = {foobar, " 889"}; - 3'h4 : foobar = {foobar, " 890"}; - 3'h5 : foobar = {foobar, " 891"}; - 3'h6 : foobar = {foobar, " 892"}; - 3'h7 : foobar = {foobar, " 893"}; - endcase - end - endtask - task ozoneye; - input [5:0] ye; - input l; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - foobar = {foobar, " 894"}; - ozonerme(ye[5:3],foobar); - case ({ye[ 2:0], l}) - 4'h2, - 4'ha: foobar = {foobar, " 895"}; - 4'h4, - 4'hb: foobar = {foobar, " 896"}; - 4'h6, - 4'he: foobar = {foobar, " 897"}; - 4'h8, - 4'hc: foobar = {foobar, " 898"}; - endcase - end - endtask - task ozonef1e_ye; - input [5:0] ye; - input l; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - foobar = {foobar, " 899"}; - ozonerme(ye[5:3],foobar); - ozonef1e_inc_dec(ye[5:0], l ,foobar); - end - endtask - task ozonef1e_h; - input [ 2:0] e; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - if (e[ 2:0] <= 3'h4) - foobar = {foobar, " 900"}; - end - endtask - task ozonef1e_inc_dec; - input [5:0] ye; - input l; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case ({ye[ 2:0], l}) - 4'h2, - 4'h3, - 4'ha: foobar = {foobar, " 901"}; - 4'h4, - 4'h5, - 4'hb: foobar = {foobar, " 902"}; - 4'h6, - 4'h7, - 4'he: foobar = {foobar, " 903"}; - 4'h8, - 4'h9, - 4'hc: foobar = {foobar, " 904"}; - 4'hf: foobar = {foobar, " 905"}; - endcase - end - endtask - task ozonef1e_hl; - input [ 2:0] e; - input l; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case ({e[ 2:0], l}) - 4'h0, - 4'h2, - 4'h4, - 4'h6, - 4'h8: foobar = {foobar, " 906"}; - 4'h1, - 4'h3, - 4'h5, - 4'h7, - 4'h9: foobar = {foobar, " 907"}; - endcase - end - endtask - task ozonexe; - input [ 3:0] xe; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (xe[3]) - 1'b0 : foobar = {foobar, " 908"}; - 1'b1 : foobar = {foobar, " 909"}; - endcase - case (xe[ 2:0]) - 3'h1, - 3'h5: foobar = {foobar, " 910"}; - 3'h2, - 3'h6: foobar = {foobar, " 911"}; - 3'h3, - 3'h7: foobar = {foobar, " 912"}; - 3'h4: foobar = {foobar, " 913"}; - endcase - end - endtask - task ozonerp; - input [ 2:0] rp; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (rp) - 3'h0 : foobar = {foobar, " 914"}; - 3'h1 : foobar = {foobar, " 915"}; - 3'h2 : foobar = {foobar, " 916"}; - 3'h3 : foobar = {foobar, " 917"}; - 3'h4 : foobar = {foobar, " 918"}; - 3'h5 : foobar = {foobar, " 919"}; - 3'h6 : foobar = {foobar, " 920"}; - 3'h7 : foobar = {foobar, " 921"}; - endcase - end - endtask - task ozonery; - input [ 3:0] ry; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (ry) - 4'h0 : foobar = {foobar, " 922"}; - 4'h1 : foobar = {foobar, " 923"}; - 4'h2 : foobar = {foobar, " 924"}; - 4'h3 : foobar = {foobar, " 925"}; - 4'h4 : foobar = {foobar, " 926"}; - 4'h5 : foobar = {foobar, " 927"}; - 4'h6 : foobar = {foobar, " 928"}; - 4'h7 : foobar = {foobar, " 929"}; - 4'h8 : foobar = {foobar, " 930"}; - 4'h9 : foobar = {foobar, " 931"}; - 4'ha : foobar = {foobar, " 932"}; - 4'hb : foobar = {foobar, " 933"}; - 4'hc : foobar = {foobar, " 934"}; - 4'hd : foobar = {foobar, " 935"}; - 4'he : foobar = {foobar, " 936"}; - 4'hf : foobar = {foobar, " 937"}; - endcase - end - endtask - task ozonearx; - input [ 15:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[1:0]) - 2'h0 : foobar = {foobar, " 938"}; - 2'h1 : foobar = {foobar, " 939"}; - 2'h2 : foobar = {foobar, " 940"}; - 2'h3 : foobar = {foobar, " 941"}; - endcase - end - endtask - task ozonef3f4imop; - input [ 4:0] f3f4iml; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - casez (f3f4iml) - 5'b000??: foobar = {foobar, " 942"}; - 5'b001??: foobar = {foobar, " 943"}; - 5'b?10??: foobar = {foobar, " 944"}; - 5'b0110?: foobar = {foobar, " 945"}; - 5'b01110: foobar = {foobar, " 946"}; - 5'b01111: foobar = {foobar, " 947"}; - 5'b10???: foobar = {foobar, " 948"}; - 5'b11100: foobar = {foobar, " 949"}; - 5'b11101: foobar = {foobar, " 950"}; - 5'b11110: foobar = {foobar, " 951"}; - 5'b11111: foobar = {foobar, " 952"}; - endcase - end - endtask - task ozonecon; - input [ 4:0] con; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (con) - 5'h00 : foobar = {foobar, " 953"}; - 5'h01 : foobar = {foobar, " 954"}; - 5'h02 : foobar = {foobar, " 955"}; - 5'h03 : foobar = {foobar, " 956"}; - 5'h04 : foobar = {foobar, " 957"}; - 5'h05 : foobar = {foobar, " 958"}; - 5'h06 : foobar = {foobar, " 959"}; - 5'h07 : foobar = {foobar, " 960"}; - 5'h08 : foobar = {foobar, " 961"}; - 5'h09 : foobar = {foobar, " 962"}; - 5'h0a : foobar = {foobar, " 963"}; - 5'h0b : foobar = {foobar, " 964"}; - 5'h0c : foobar = {foobar, " 965"}; - 5'h0d : foobar = {foobar, " 966"}; - 5'h0e : foobar = {foobar, " 967"}; - 5'h0f : foobar = {foobar, " 968"}; - 5'h10 : foobar = {foobar, " 969"}; - 5'h11 : foobar = {foobar, " 970"}; - 5'h12 : foobar = {foobar, " 971"}; - 5'h13 : foobar = {foobar, " 972"}; - 5'h14 : foobar = {foobar, " 973"}; - 5'h15 : foobar = {foobar, " 974"}; - 5'h16 : foobar = {foobar, " 975"}; - 5'h17 : foobar = {foobar, " 976"}; - 5'h18 : foobar = {foobar, " 977"}; - 5'h19 : foobar = {foobar, " 978"}; - 5'h1a : foobar = {foobar, " 979"}; - 5'h1b : foobar = {foobar, " 980"}; - 5'h1c : foobar = {foobar, " 981"}; - 5'h1d : foobar = {foobar, " 982"}; - 5'h1e : foobar = {foobar, " 983"}; - 5'h1f : foobar = {foobar, " 984"}; - endcase - end - endtask - task ozonedr; - input [ 15:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[ 9: 6]) - 4'h0 : foobar = {foobar, " 985"}; - 4'h1 : foobar = {foobar, " 986"}; - 4'h2 : foobar = {foobar, " 987"}; - 4'h3 : foobar = {foobar, " 988"}; - 4'h4 : foobar = {foobar, " 989"}; - 4'h5 : foobar = {foobar, " 990"}; - 4'h6 : foobar = {foobar, " 991"}; - 4'h7 : foobar = {foobar, " 992"}; - 4'h8 : foobar = {foobar, " 993"}; - 4'h9 : foobar = {foobar, " 994"}; - 4'ha : foobar = {foobar, " 995"}; - 4'hb : foobar = {foobar, " 996"}; - 4'hc : foobar = {foobar, " 997"}; - 4'hd : foobar = {foobar, " 998"}; - 4'he : foobar = {foobar, " 999"}; - 4'hf : foobar = {foobar, " 1000"}; - endcase - end - endtask - task ozoneshift; - input [ 15:0] foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo[ 4: 3]) - 2'h0 : foobar = {foobar, " 1001"}; - 2'h1 : foobar = {foobar, " 1002"}; - 2'h2 : foobar = {foobar, " 1003"}; - 2'h3 : foobar = {foobar, " 1004"}; - endcase - end - endtask - task ozoneacc; - input foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo) - 2'h0 : foobar = {foobar, " 1005"}; - 2'h1 : foobar = {foobar, " 1006"}; - endcase - end - endtask - task ozonehl; - input foo; - inout [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - case (foo) - 2'h0 : foobar = {foobar, " 1007"}; - 2'h1 : foobar = {foobar, " 1008"}; - endcase - end - endtask - task automatic dude; - inout [STRLEN*8: 1] foobar; - reg [ 7:0] temp; - integer i; - reg nacho; - // verilator no_inline_task - begin : justify_block - nacho = 1'b0; - for (i=STRLEN-1; i>1; i=i-1) - begin - temp = foobar>>((STRLEN-1)*8); - if (temp || nacho) - nacho = 1'b1; - else - begin - foobar = foobar<<8; - foobar[8:1] = 32; + end + endtask + + task automatic big_case; + input [31:0] fd; + input [31:0] foo; + reg [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + foobar = " 1009"; + if (&foo === 1'bx) $fwrite(fd, " 1010"); + else + casez ({ + foo[31:26], foo[19:15], foo[5:0] + }) + 17'b00_111?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1011"}; + ozoneacc(~foo[26], foobar); + ozonehl(foo[20], foobar); + foobar = {foobar, " 1012"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite(fd, " 1013:%s", foobar); + end + 17'b01_001?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1014"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1015"}; + foobar = {foobar, " 1016"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite(fd, " 1017:%s", foobar); + end + 17'b10_100?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1018"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1019"}; + foobar = {foobar, " 1020"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite(fd, " 1021:%s", foobar); + end + 17'b10_101?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1022"}; + if (foo[20]) begin + foobar = {foobar, " 1023"}; + ozoneacc(foo[18], foobar); + foobar = {foobar, " 1024"}; + foobar = {foobar, " 1025"}; + if (foo[19]) foobar = {foobar, " 1026"}; + else foobar = {foobar, " 1027"}; + end + else ozonerx(foo, foobar); + dude(foobar); + $fwrite(fd, " 1028:%s", foobar); + end + 17'b10_110?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1029"}; + foobar = {foobar, " 1030"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1031"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite(fd, " 1032:%s", foobar); + end + 17'b10_111?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1033"}; + foobar = {foobar, " 1034"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1035"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite(fd, " 1036:%s", foobar); + end + 17'b11_001?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1037"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1038"}; + foobar = {foobar, " 1039"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite(fd, " 1040:%s", foobar); + end + 17'b11_111?_?_????_??_????: begin + ozonef1(foo, foobar); + foobar = {foobar, " 1041"}; + foobar = {foobar, " 1042"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1043"}; + if (foo[20]) foobar = {foobar, " 1044"}; + else foobar = {foobar, " 1045"}; + dude(foobar); + $fwrite(fd, " 1046:%s", foobar); + end + 17'b00_10??_?_????_?1_1111: + casez (foo[11:5]) + 7'b??_0_010_0: begin + foobar = " 1047"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1048"}; + ozonef1e(foo, foobar); + dude(foobar); + $fwrite(fd, " 1049:%s", foobar); + end + 7'b00_?_110_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1050"}; + case ({ + foo[9], foo[5] + }) + 2'b00: begin + foobar = {foobar, " 1051"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[5], foobar); end - end - end - endtask + 2'b01: begin + foobar = {foobar, " 1052"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[5], foobar); + end + 2'b10: begin + foobar = {foobar, " 1053"}; + ozoneae(foo[14:12], foobar); + end + 2'b11: foobar = {foobar, " 1054"}; + endcase + dude(foobar); + $fwrite(fd, " 1055:%s", foobar); + end + 7'b01_?_110_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1056"}; + case ({ + foo[9], foo[5] + }) + 2'b00: begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[5], foobar); + foobar = {foobar, " 1057"}; + end + 2'b01: begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[5], foobar); + foobar = {foobar, " 1058"}; + end + 2'b10: begin + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1059"}; + end + 2'b11: foobar = {foobar, " 1060"}; + endcase + dude(foobar); + $fwrite(fd, " 1061:%s", foobar); + end + 7'b10_0_110_0: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1062"}; + foobar = {foobar, " 1063"}; + if (foo[12]) foobar = {foobar, " 1064"}; + else ozonerab({4'b1001, foo[14:12]}, foobar); + dude(foobar); + $fwrite(fd, " 1065:%s", foobar); + end + 7'b10_0_110_1: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1066"}; + if (foo[12]) foobar = {foobar, " 1067"}; + else ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1068"}; + dude(foobar); + $fwrite(fd, " 1069:%s", foobar); + end + 7'b??_?_000_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1070"}; + foobar = {foobar, " 1071"}; + ozonef1e_hl(foo[11:9], foo[5], foobar); + foobar = {foobar, " 1072"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1073:%s", foobar); + end + 7'b??_?_100_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1074"}; + foobar = {foobar, " 1075"}; + ozonef1e_hl(foo[11:9], foo[5], foobar); + foobar = {foobar, " 1076"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1077:%s", foobar); + end + 7'b??_?_001_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1078"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + foobar = {foobar, " 1079"}; + foobar = {foobar, " 1080"}; + ozonef1e_hl(foo[11:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1081:%s", foobar); + end + 7'b??_?_011_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1082"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + foobar = {foobar, " 1083"}; + foobar = {foobar, " 1084"}; + ozonef1e_hl(foo[11:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1085:%s", foobar); + end + 7'b??_?_101_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1086"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1087:%s", foobar); + end + endcase + 17'b00_10??_?_????_?0_0110: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1088"}; + ozoneae(foo[8:6], foobar); + ozonef1e_hl(foo[11:9], foo[5], foobar); + foobar = {foobar, " 1089"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1090:%s", foobar); + end + 17'b00_10??_?_????_00_0111: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1091"}; + if (foo[6]) foobar = {foobar, " 1092"}; + else ozonerab({4'b1001, foo[8:6]}, foobar); + foobar = {foobar, " 1093"}; + foobar = {foobar, " 1094"}; + ozonerme(foo[14:12], foobar); + case (foo[11:9]) + 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9], 1'b0, foobar); + 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1095"}; + endcase + dude(foobar); + $fwrite(fd, " 1096:%s", foobar); + end + 17'b00_10??_?_????_?0_0100: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1097"}; + ozonef1e_ye(foo[14:9], foo[5], foobar); + foobar = {foobar, " 1098"}; + ozoneae(foo[8:6], foobar); + ozonef1e_hl(foo[11:9], foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1099:%s", foobar); + end + 17'b00_10??_?_????_10_0111: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1100"}; + foobar = {foobar, " 1101"}; + ozonerme(foo[14:12], foobar); + case (foo[11:9]) + 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9], 1'b0, foobar); + 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1102"}; + endcase + foobar = {foobar, " 1103"}; + if (foo[6]) foobar = {foobar, " 1104"}; + else ozonerab({4'b1001, foo[8:6]}, foobar); + dude(foobar); + $fwrite(fd, " 1105:%s", foobar); + end + 17'b00_10??_?_????_?0_1110: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1106"}; + case (foo[11:9]) + 3'h2: begin + foobar = {foobar, " 1107"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1108"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1109"}; + end + 3'h6: begin + foobar = {foobar, " 1110"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1111"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1112"}; + end + 3'h0: begin + foobar = {foobar, " 1113"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1114"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1115"}; + if (foo[7:5] >= 3'h5) foobar = {foobar, " 1116"}; + else ozonexe(foo[8:5], foobar); + end + 3'h1: begin + foobar = {foobar, " 1117"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1118"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1119"}; + if (foo[7:5] >= 3'h5) foobar = {foobar, " 1120"}; + else ozonexe(foo[8:5], foobar); + end + 3'h4: begin + foobar = {foobar, " 1121"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1122"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1123"}; + if (foo[7:5] >= 3'h5) foobar = {foobar, " 1124"}; + else ozonexe(foo[8:5], foobar); + end + 3'h5: begin + foobar = {foobar, " 1125"}; + if (foo[14:12] == 3'h0) foobar = {foobar, " 1126"}; + else ozonerme(foo[14:12], foobar); + foobar = {foobar, " 1127"}; + if (foo[7:5] >= 3'h5) foobar = {foobar, " 1128"}; + else ozonexe(foo[8:5], foobar); + end + endcase + dude(foobar); + $fwrite(fd, " 1129:%s", foobar); + end + 17'b00_10??_?_????_?0_1111: + casez (foo[14:9]) + 6'b001_10_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1130"}; + foobar = {foobar, " 1131"}; + ozonef1e_hl(foo[7:5], foo[9], foobar); + foobar = {foobar, " 1132"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1133:%s", foobar); + end + 6'b???_11_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1134"}; + ozoneae(foo[14:12], foobar); + ozonef1e_hl(foo[7:5], foo[9], foobar); + foobar = {foobar, " 1135"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1136:%s", foobar); + end + 6'b000_10_1, 6'b010_10_1, 6'b100_10_1, 6'b110_10_1: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1137"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1138"}; + if ((foo[7:5] >= 3'h1) & (foo[7:5] <= 3'h3)) foobar = {foobar, " 1139"}; + else ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1140:%s", foobar); + end + 6'b000_10_0, 6'b010_10_0, 6'b100_10_0, 6'b110_10_0: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1141"}; + foobar = {foobar, " 1142"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1143"}; + foobar = {foobar, " 1144"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1145"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1146:%s", foobar); + end + 6'b???_00_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1147"}; + if (foo[9]) begin + foobar = {foobar, " 1148"}; + ozoneae(foo[14:12], foobar); + end + else begin + foobar = {foobar, " 1149"}; + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1150"}; + end + foobar = {foobar, " 1151"}; + foobar = {foobar, " 1152"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1153"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1154:%s", foobar); + end + 6'b???_01_?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1155"}; + ozoneae(foo[14:12], foobar); + if (foo[9]) foobar = {foobar, " 1156"}; + else foobar = {foobar, " 1157"}; + foobar = {foobar, " 1158"}; + foobar = {foobar, " 1159"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1160"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1161:%s", foobar); + end + 6'b011_10_0: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1162"}; + case (foo[8:5]) + 4'h0: foobar = {foobar, " 1163"}; + 4'h1: foobar = {foobar, " 1164"}; + 4'h2: foobar = {foobar, " 1165"}; + 4'h3: foobar = {foobar, " 1166"}; + 4'h4: foobar = {foobar, " 1167"}; + 4'h5: foobar = {foobar, " 1168"}; + 4'h8: foobar = {foobar, " 1169"}; + 4'h9: foobar = {foobar, " 1170"}; + 4'ha: foobar = {foobar, " 1171"}; + 4'hb: foobar = {foobar, " 1172"}; + 4'hc: foobar = {foobar, " 1173"}; + 4'hd: foobar = {foobar, " 1174"}; + default: foobar = {foobar, " 1175"}; + endcase + dude(foobar); + $fwrite(fd, " 1176:%s", foobar); + end + default: foobar = {foobar, " 1177"}; + endcase + 17'b00_10??_?_????_?0_110?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1178"}; + foobar = {foobar, " 1179"}; + ozonef1e_hl(foo[11:9], foo[0], foobar); + foobar = {foobar, " 1180"}; + ozonef1e_ye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1181"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1182"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1183:%s", foobar); + end + 17'b00_10??_?_????_?1_110?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1184"}; + foobar = {foobar, " 1185"}; + ozonef1e_hl(foo[11:9], foo[0], foobar); + foobar = {foobar, " 1186"}; + ozonef1e_ye(foo[14:9], foo[0], foobar); + foobar = {foobar, " 1187"}; + foobar = {foobar, " 1188"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1189"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1190:%s", foobar); + end + 17'b00_10??_?_????_?0_101?: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1191"}; + ozonef1e_ye(foo[14:9], foo[0], foobar); + foobar = {foobar, " 1192"}; + foobar = {foobar, " 1193"}; + ozonef1e_hl(foo[11:9], foo[0], foobar); + foobar = {foobar, " 1194"}; + foobar = {foobar, " 1195"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1196"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1197:%s", foobar); + end + 17'b00_10??_?_????_?0_1001: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1198"}; + foobar = {foobar, " 1199"}; + ozonef1e_h(foo[11:9], foobar); + foobar = {foobar, " 1200"}; + ozonef1e_ye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1201"}; + case (foo[7:5]) + 3'h1, 3'h2, 3'h3: foobar = {foobar, " 1202"}; + default: begin + foobar = {foobar, " 1203"}; + foobar = {foobar, " 1204"}; + ozonexe(foo[8:5], foobar); + end + endcase + dude(foobar); + $fwrite(fd, " 1205:%s", foobar); + end + 17'b00_10??_?_????_?0_0101: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1206"}; + case (foo[11:9]) + 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1207"}; + default: begin + ozonef1e_ye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1208"}; + foobar = {foobar, " 1209"}; + end + endcase + foobar = {foobar, " 1210"}; + foobar = {foobar, " 1211"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1212"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1213:%s", foobar); + end + 17'b00_10??_?_????_?1_1110: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1214"}; + ozonef1e_ye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1215"}; + foobar = {foobar, " 1216"}; + ozonef1e_h(foo[11:9], foobar); + foobar = {foobar, " 1217"}; + foobar = {foobar, " 1218"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1219"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1220:%s", foobar); + end + 17'b00_10??_?_????_?0_1000: begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1221"}; + ozonef1e_ye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1222"}; + foobar = {foobar, " 1223"}; + ozonef1e_h(foo[11:9], foobar); + foobar = {foobar, " 1224"}; + foobar = {foobar, " 1225"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1226"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1227:%s", foobar); + end + 17'b10_01??_?_????_??_????: begin + if (foo[27]) foobar = " 1228"; + else foobar = " 1229"; + ozonecon(foo[20:16], foobar); + foobar = {foobar, " 1230"}; + ozonef2(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1231:%s", foobar); + end + 17'b00_1000_?_????_01_0011: + if (~|foo[9:8]) begin + if (foo[7]) foobar = " 1232"; + else foobar = " 1233"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1234"}; + ozonef2e(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1235:%s", foobar); + end + else begin + foobar = " 1236"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1237"}; + ozonef3e(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1238:%s", foobar); + end + 17'b11_110?_1_????_??_????: begin + ozonef3(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1239:%s", foobar); + end + 17'b11_110?_0_????_??_????: begin : f4_body + casez (foo[24:20]) + 5'b0_1110, 5'b1_0???, 5'b1_1111: begin + $fwrite(fd, " 1240"); + end + 5'b0_00??: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1241"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1242"}; + dude(foobar); + $fwrite(fd, " 1243:%s", foobar); + end + 5'b0_01??: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1244"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozonearm(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1245:%s", foobar); + end + 5'b0_1011: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1246"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1247"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1248"}; + dude(foobar); + $fwrite(fd, " 1249:%s", foobar); + end + 5'b0_100?, 5'b0_1010, 5'b0_110?: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1250"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1251"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1252"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1253"}; + dude(foobar); + $fwrite(fd, " 1254:%s", foobar); + end + 5'b0_1111: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1255"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1256"}; + ozoneae(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1257:%s", foobar); + end + 5'b1_10??, 5'b1_110?, 5'b1_1110: begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1258"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1259"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1260"}; + ozonearm(foo[18:16], foobar); + foobar = {foobar, " 1261"}; + dude(foobar); + $fwrite(fd, " 1262:%s", foobar); + end + endcase + end + 17'b11_100?_?_????_??_????: + casez (foo[23:19]) + 5'b111??, 5'b0111?: begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1263"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1264"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1265"}; + skyway(foo[15:12], foobar); + skyway(foo[11:8], foobar); + skyway(foo[7:4], foobar); + skyway(foo[3:0], foobar); + foobar = {foobar, " 1266"}; + dude(foobar); + $fwrite(fd, " 1267:%s", foobar); + end + 5'b?0???, 5'b110??: begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1268"}; + if (foo[23:21] == 3'b100) foobar = {foobar, " 1269"}; + ozoneae(foo[18:16], foobar); + if (foo[19]) foobar = {foobar, " 1270"}; + else foobar = {foobar, " 1271"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1272"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1273:%s", foobar); + end + 5'b010??, 5'b0110?: begin + ozoneae(foo[18:16], foobar); + if (foo[19]) foobar = {foobar, " 1274"}; + else foobar = {foobar, " 1275"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1276"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1277:%s", foobar); + end + endcase + 17'b00_1000_?_????_11_0011: begin + foobar = " 1278"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1279"}; + casez (foo[25:21]) + 5'b0_1110, 5'b1_0???, 5'b1_1111: begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1281"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozoneae(foo[8:6], foobar); + foobar = {foobar, " 1282"}; + dude(foobar); + $fwrite(fd, " 1283:%s", foobar); + end + 5'b0_01??: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1284"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozonearm(foo[8:6], foobar); + dude(foobar); + $fwrite(fd, " 1285:%s", foobar); + end + 5'b0_1011: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1286"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1287"}; + ozoneae(foo[8:6], foobar); + foobar = {foobar, " 1288"}; + dude(foobar); + $fwrite(fd, " 1289:%s", foobar); + end + 5'b0_100?, 5'b0_1010, 5'b0_110?: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1290"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1291"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1292"}; + ozoneae(foo[8:6], foobar); + foobar = {foobar, " 1293"}; + dude(foobar); + $fwrite(fd, " 1294:%s", foobar); + end + 5'b0_1111: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1295"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1296"}; + ozoneae(foo[8:6], foobar); + dude(foobar); + $fwrite(fd, " 1297:%s", foobar); + end + 5'b1_10??, 5'b1_110?, 5'b1_1110: begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1298"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1299"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1300"}; + ozonearm(foo[8:6], foobar); + foobar = {foobar, " 1301"}; + dude(foobar); + $fwrite(fd, " 1302:%s", foobar); + end + endcase + end + 17'b00_0010_?_????_??_????: begin + $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); + ozonerab({1'b0, foo[25:20]}, foobar); + $fwrite(fd, " 1304b:%x", foobar); + foobar = {foobar, " 1303"}; + $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); + skyway(foo[19:16], foobar); + $fwrite(fd, " 1304d:%x", foobar); + dude(foobar); + $fwrite(fd, " 1304e:%x", foobar); + $fwrite(fd, " 1304:%s", foobar); + end + 17'b00_01??_?_????_??_????: begin + if (foo[27]) begin + foobar = {foobar, " 1305"}; + if (foo[26]) foobar = {foobar, " 1306"}; + else foobar = {foobar, " 1307"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1308"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + else begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1309"}; + if (foo[26]) foobar = {foobar, " 1310"}; + else foobar = {foobar, " 1311"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1312"}; + end + dude(foobar); + $fwrite(fd, " 1313:%s", foobar); + end + 17'b01_000?_?_????_??_????: begin + if (foo[26]) begin + ozonerb(foo[25:20], foobar); + foobar = {foobar, " 1314"}; + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + end + else begin + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + foobar = {foobar, " 1315"}; + ozonerb(foo[25:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1316:%s", foobar); + end + 17'b01_10??_?_????_??_????: begin + if (foo[27]) begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1317"}; + ozonerx(foo, foobar); + end + else begin + ozonerx(foo, foobar); + foobar = {foobar, " 1318"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + dude(foobar); + $fwrite(fd, " 1319:%s", foobar); + end + 17'b11_101?_?_????_??_????: begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1320"}; + skyway(foo[19:16], foobar); + skyway(foo[15:12], foobar); + skyway(foo[11:8], foobar); + skyway(foo[7:4], foobar); + skyway(foo[3:0], foobar); + dude(foobar); + $fwrite(fd, " 1321:%s", foobar); + end + 17'b11_0000_?_????_??_????: begin + casez (foo[25:23]) + 3'b00?: begin + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1322"}; + end + 3'b01?: begin + foobar = {foobar, " 1323"}; + if (foo[22:16] >= 7'h60) foobar = {foobar, " 1324"}; + else ozonerab(foo[22:16], foobar); + end + 3'b110: foobar = {foobar, " 1325"}; + 3'b10?: begin + foobar = {foobar, " 1326"}; + if (foo[22:16] >= 7'h60) foobar = {foobar, " 1327"}; + else ozonerab(foo[22:16], foobar); + end + 3'b111: begin + foobar = {foobar, " 1328"}; + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1329"}; + end + endcase + dude(foobar); + $fwrite(fd, " 1330:%s", foobar); + end + 17'b00_10??_?_????_?1_0000: begin + if (foo[27]) begin + foobar = {foobar, " 1331"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1332"}; + skyway(foo[19:16], foobar); + skyway({foo[15], foo[11:9]}, foobar); + skyway(foo[8:5], foobar); + foobar = {foobar, " 1333"}; + if (foo[26:20] >= 7'h60) foobar = {foobar, " 1334"}; + else ozonerab(foo[26:20], foobar); + end + else begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1335"}; + foobar = {foobar, " 1336"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1337"}; + skyway(foo[19:16], foobar); + skyway({foo[15], foo[11:9]}, foobar); + skyway(foo[8:5], foobar); + foobar = {foobar, " 1338"}; + end + dude(foobar); + $fwrite(fd, " 1339:%s", foobar); + end + 17'b00_101?_1_0000_?1_0010: + if (~|foo[11:7]) begin + if (foo[6]) begin + foobar = {foobar, " 1340"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1341"}; + ozonejk(foo[5], foobar); + foobar = {foobar, " 1342"}; + if (foo[26:20] >= 7'h60) foobar = {foobar, " 1343"}; + else ozonerab(foo[26:20], foobar); + end + else begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1344"}; + foobar = {foobar, " 1345"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1346"}; + ozonejk(foo[5], foobar); + foobar = {foobar, " 1347"}; + end + dude(foobar); + $fwrite(fd, " 1348:%s", foobar); + end + else $fwrite(fd, " 1349"); + 17'b00_100?_0_0011_?1_0101: + if (~|foo[8:7]) begin + if (foo[6]) begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1350"}; + ozoneye(foo[14:9], foo[5], foobar); + end + else begin + ozoneye(foo[14:9], foo[5], foobar); + foobar = {foobar, " 1351"}; + if (foo[26:20] >= 7'h60) foobar = {foobar, " 1352"}; + else ozonerab(foo[26:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1353:%s", foobar); + end + else $fwrite(fd, " 1354"); + 17'b00_1001_0_0000_?1_0010: + if (~|foo[25:20]) begin + ozoneye(foo[14:9], 1'b0, foobar); + foobar = {foobar, " 1355"}; + ozonef1e_h(foo[11:9], foobar); + foobar = {foobar, " 1356"}; + ozonef1e_h(foo[7:5], foobar); + foobar = {foobar, " 1357"}; + ozonexe(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1358:%s", foobar); + end + else $fwrite(fd, " 1359"); + 17'b00_101?_0_????_?1_0010: + if (~foo[13]) begin + if (foo[12]) begin + foobar = {foobar, " 1360"}; + if (foo[26:20] >= 7'h60) foobar = {foobar, " 1361"}; + else ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1362"}; + foobar = {foobar, " 1363"}; + skyway({1'b0, foo[18:16]}, foobar); + skyway({foo[15], foo[11:9]}, foobar); + skyway(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1364:%s", foobar); + end + else begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1365"}; + foobar = {foobar, " 1366"}; + skyway({1'b0, foo[18:16]}, foobar); + skyway({foo[15], foo[11:9]}, foobar); + skyway(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1367:%s", foobar); + end + end + else $fwrite(fd, " 1368"); + 17'b01_01??_?_????_??_????: begin + ozonerab({1'b0, foo[27:26], foo[19:16]}, foobar); + foobar = {foobar, " 1369"}; + ozonerab({1'b0, foo[25:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1370:%s", foobar); + end + 17'b00_100?_?_???0_11_0101: + if (~foo[6]) begin + foobar = " 1371"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1372"}; + ozonerab({foo[9:7], foo[19:16]}, foobar); + foobar = {foobar, " 1373"}; + ozonerab({foo[26:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1374:%s", foobar); + end + else $fwrite(fd, " 1375"); + 17'b00_1000_?_????_?1_0010: + if (~|foo[25:24]) begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1376"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1377"}; + skyway(foo[19:16], foobar); + skyway({foo[15], foo[11:9]}, foobar); + skyway(foo[8:5], foobar); + dude(foobar); + $fwrite(fd, " 1378:%s", foobar); + end + else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11:6]) begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1379"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1380"}; + ozonejk(foo[5], foobar); + dude(foobar); + $fwrite(fd, " 1381:%s", foobar); + end + else $fwrite(fd, " 1382"); + 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_????: + if (foo[30]) $fwrite(fd, " 1383:%s", foo[27:16]); + else $fwrite(fd, " 1384:%s", foo[27:16]); + 17'b00_10??_?_????_01_1000: + if (~foo[6]) begin + if (foo[7]) $fwrite(fd, " 1385:%s", foo[27:8]); + else $fwrite(fd, " 1386:%s", foo[27:8]); + end + else $fwrite(fd, " 1387"); + 17'b00_10??_?_????_11_1000: begin + foobar = " 1388"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1389"}; + if (foo[15]) foobar = {foobar, " 1390"}; + else foobar = {foobar, " 1391"}; + skyway(foo[27:24], foobar); + skyway(foo[23:20], foobar); + skyway(foo[19:16], foobar); + skyway(foo[9:6], foobar); + dude(foobar); + $fwrite(fd, " 1392:%s", foobar); + end + 17'b11_0001_?_????_??_????: + casez (foo[25:22]) + 4'b01??: begin + foobar = " 1393"; + ozonecon(foo[20:16], foobar); + case (foo[23:21]) + 3'h0: foobar = {foobar, " 1394"}; + 3'h1: foobar = {foobar, " 1395"}; + 3'h2: foobar = {foobar, " 1396"}; + 3'h3: foobar = {foobar, " 1397"}; + 3'h4: foobar = {foobar, " 1398"}; + 3'h5: foobar = {foobar, " 1399"}; + 3'h6: foobar = {foobar, " 1400"}; + 3'h7: foobar = {foobar, " 1401"}; + endcase + dude(foobar); + $fwrite(fd, " 1402:%s", foobar); + end + 4'b0000: $fwrite(fd, " 1403:%s", foo[21:16]); + 4'b0010: if (~|foo[21:16]) $fwrite(fd, " 1404"); + 4'b1010: + if (~|foo[21:17]) begin + if (foo[16]) $fwrite(fd, " 1405"); + else $fwrite(fd, " 1406"); + end + default: $fwrite(fd, " 1407"); + endcase + 17'b01_11??_?_????_??_????: + if (foo[27:23] === 5'h00) $fwrite(fd, " 1408:%s", foo[22:16]); + else $fwrite(fd, " 1409:%s", foo[22:16]); + default: $fwrite(fd, " 1410"); + endcase + end + endtask - task automatic big_case; - input [ 31:0] fd; - input [ 31:0] foo; - reg [STRLEN*8: 1] foobar; - // verilator no_inline_task - begin - foobar = " 1009"; - if (&foo === 1'bx) - $fwrite(fd, " 1010"); - else - casez ( {foo[31:26], foo[19:15], foo[5:0]} ) - 17'b00_111?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1011"}; - ozoneacc(~foo[26], foobar); - ozonehl(foo[20], foobar); - foobar = {foobar, " 1012"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1013:%s", foobar); - end - 17'b01_001?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1014"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1015"}; - foobar = {foobar, " 1016"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1017:%s", foobar); - end - 17'b10_100?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1018"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1019"}; - foobar = {foobar, " 1020"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1021:%s", foobar); - end - 17'b10_101?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1022"}; - if (foo[20]) - begin - foobar = {foobar, " 1023"}; - ozoneacc(foo[18], foobar); - foobar = {foobar, " 1024"}; - foobar = {foobar, " 1025"}; - if (foo[19]) - foobar = {foobar, " 1026"}; - else - foobar = {foobar, " 1027"}; - end - else - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1028:%s", foobar); - end - 17'b10_110?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1029"}; - foobar = {foobar, " 1030"}; - ozonehl(foo[20], foobar); - foobar = {foobar, " 1031"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1032:%s", foobar); - end - 17'b10_111?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1033"}; - foobar = {foobar, " 1034"}; - ozonehl(foo[20], foobar); - foobar = {foobar, " 1035"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1036:%s", foobar); - end - 17'b11_001?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1037"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1038"}; - foobar = {foobar, " 1039"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1040:%s", foobar); - end - 17'b11_111?_?_????_??_???? : - begin - ozonef1(foo, foobar); - foobar = {foobar, " 1041"}; - foobar = {foobar, " 1042"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1043"}; - if (foo[20]) - foobar = {foobar, " 1044"}; - else - foobar = {foobar, " 1045"}; - dude(foobar); - $fwrite (fd, " 1046:%s", foobar); - end - 17'b00_10??_?_????_?1_1111 : - casez (foo[11: 5]) - 7'b??_0_010_0: - begin - foobar = " 1047"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1048"}; - ozonef1e(foo, foobar); - dude(foobar); - $fwrite (fd, " 1049:%s", foobar); - end - 7'b00_?_110_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1050"}; - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - foobar = {foobar, " 1051"}; - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - end - 2'b01: - begin - foobar = {foobar, " 1052"}; - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - end - 2'b10: - begin - foobar = {foobar, " 1053"}; - ozoneae(foo[14:12], foobar); - end - 2'b11: foobar = {foobar, " 1054"}; - endcase - dude(foobar); - $fwrite (fd, " 1055:%s", foobar); - end - 7'b01_?_110_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1056"}; - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - foobar = {foobar, " 1057"}; - end - 2'b01: - begin - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - foobar = {foobar, " 1058"}; - end - 2'b10: - begin - ozoneae(foo[14:12], foobar); - foobar = {foobar, " 1059"}; - end - 2'b11: foobar = {foobar, " 1060"}; - endcase - dude(foobar); - $fwrite (fd, " 1061:%s", foobar); - end - 7'b10_0_110_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1062"}; - foobar = {foobar, " 1063"}; - if (foo[12]) - foobar = {foobar, " 1064"}; - else - ozonerab({4'b1001, foo[14:12]}, foobar); - dude(foobar); - $fwrite (fd, " 1065:%s", foobar); - end - 7'b10_0_110_1: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1066"}; - if (foo[12]) - foobar = {foobar, " 1067"}; - else - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1068"}; - dude(foobar); - $fwrite (fd, " 1069:%s", foobar); - end - 7'b??_?_000_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1070"}; - foobar = {foobar, " 1071"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1072"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1073:%s", foobar); - end - 7'b??_?_100_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1074"}; - foobar = {foobar, " 1075"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1076"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1077:%s", foobar); - end - 7'b??_?_001_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1078"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1079"}; - foobar = {foobar, " 1080"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1081:%s", foobar); - end - 7'b??_?_011_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1082"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1083"}; - foobar = {foobar, " 1084"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1085:%s", foobar); - end - 7'b??_?_101_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1086"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1087:%s", foobar); - end - endcase - 17'b00_10??_?_????_?0_0110 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1088"}; - ozoneae(foo[ 8: 6], foobar); - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1089"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1090:%s", foobar); - end - 17'b00_10??_?_????_00_0111 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1091"}; - if (foo[ 6]) - foobar = {foobar, " 1092"}; - else - ozonerab({4'b1001, foo[ 8: 6]}, foobar); - foobar = {foobar, " 1093"}; - foobar = {foobar, " 1094"}; - ozonerme(foo[14:12],foobar); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0,foobar); - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1095"}; - endcase - dude(foobar); - $fwrite (fd, " 1096:%s", foobar); - end - 17'b00_10??_?_????_?0_0100 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1097"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1098"}; - ozoneae(foo[ 8: 6], foobar); - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1099:%s", foobar); - end - 17'b00_10??_?_????_10_0111 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1100"}; - foobar = {foobar, " 1101"}; - ozonerme(foo[14:12],foobar); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0,foobar); - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1102"}; - endcase - foobar = {foobar, " 1103"}; - if (foo[ 6]) - foobar = {foobar, " 1104"}; - else - ozonerab({4'b1001, foo[ 8: 6]}, foobar); - dude(foobar); - $fwrite (fd, " 1105:%s", foobar); - end - 17'b00_10??_?_????_?0_1110 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1106"}; - case (foo[11:9]) - 3'h2: - begin - foobar = {foobar, " 1107"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1108"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1109"}; - end - 3'h6: - begin - foobar = {foobar, " 1110"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1111"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1112"}; - end - 3'h0: - begin - foobar = {foobar, " 1113"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1114"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1115"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1116"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h1: - begin - foobar = {foobar, " 1117"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1118"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1119"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1120"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h4: - begin - foobar = {foobar, " 1121"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1122"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1123"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1124"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h5: - begin - foobar = {foobar, " 1125"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1126"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1127"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1128"}; - else - ozonexe(foo[ 8: 5], foobar); - end - endcase - dude(foobar); - $fwrite (fd, " 1129:%s", foobar); - end - 17'b00_10??_?_????_?0_1111 : - casez (foo[14: 9]) - 6'b001_10_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1130"}; - foobar = {foobar, " 1131"}; - ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); - foobar = {foobar, " 1132"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1133:%s", foobar); - end - 6'b???_11_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1134"}; - ozoneae(foo[14:12], foobar); - ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); - foobar = {foobar, " 1135"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1136:%s", foobar); - end - 6'b000_10_1, - 6'b010_10_1, - 6'b100_10_1, - 6'b110_10_1: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1137"}; - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1138"}; - if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) - foobar = {foobar, " 1139"}; - else - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1140:%s", foobar); - end - 6'b000_10_0, - 6'b010_10_0, - 6'b100_10_0, - 6'b110_10_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1141"}; - foobar = {foobar, " 1142"}; - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1143"}; - foobar = {foobar, " 1144"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1145"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1146:%s", foobar); - end - 6'b???_00_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1147"}; - if (foo[ 9]) - begin - foobar = {foobar, " 1148"}; - ozoneae(foo[14:12], foobar); - end - else - begin - foobar = {foobar, " 1149"}; - ozoneae(foo[14:12], foobar); - foobar = {foobar, " 1150"}; - end - foobar = {foobar, " 1151"}; - foobar = {foobar, " 1152"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1153"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1154:%s", foobar); - end - 6'b???_01_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1155"}; - ozoneae(foo[14:12], foobar); - if (foo[ 9]) - foobar = {foobar, " 1156"}; - else - foobar = {foobar, " 1157"}; - foobar = {foobar, " 1158"}; - foobar = {foobar, " 1159"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1160"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1161:%s", foobar); - end - 6'b011_10_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1162"}; - case (foo[ 8: 5]) - 4'h0: foobar = {foobar, " 1163"}; - 4'h1: foobar = {foobar, " 1164"}; - 4'h2: foobar = {foobar, " 1165"}; - 4'h3: foobar = {foobar, " 1166"}; - 4'h4: foobar = {foobar, " 1167"}; - 4'h5: foobar = {foobar, " 1168"}; - 4'h8: foobar = {foobar, " 1169"}; - 4'h9: foobar = {foobar, " 1170"}; - 4'ha: foobar = {foobar, " 1171"}; - 4'hb: foobar = {foobar, " 1172"}; - 4'hc: foobar = {foobar, " 1173"}; - 4'hd: foobar = {foobar, " 1174"}; - default: foobar = {foobar, " 1175"}; - endcase - dude(foobar); - $fwrite (fd, " 1176:%s", foobar); - end - default: foobar = {foobar, " 1177"}; - endcase - 17'b00_10??_?_????_?0_110? : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1178"}; - foobar = {foobar, " 1179"}; - ozonef1e_hl(foo[11:9], foo[0], foobar); - foobar = {foobar, " 1180"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1181"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1182"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1183:%s", foobar); - end - 17'b00_10??_?_????_?1_110? : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1184"}; - foobar = {foobar, " 1185"}; - ozonef1e_hl(foo[11:9],foo[0],foobar); - foobar = {foobar, " 1186"}; - ozonef1e_ye(foo[14:9],foo[ 0],foobar); - foobar = {foobar, " 1187"}; - foobar = {foobar, " 1188"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1189"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1190:%s", foobar); - end - 17'b00_10??_?_????_?0_101? : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1191"}; - ozonef1e_ye(foo[14:9],foo[ 0],foobar); - foobar = {foobar, " 1192"}; - foobar = {foobar, " 1193"}; - ozonef1e_hl(foo[11:9],foo[0],foobar); - foobar = {foobar, " 1194"}; - foobar = {foobar, " 1195"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1196"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1197:%s", foobar); - end - 17'b00_10??_?_????_?0_1001 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1198"}; - foobar = {foobar, " 1199"}; - ozonef1e_h(foo[11:9],foobar); - foobar = {foobar, " 1200"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1201"}; - case (foo[ 7: 5]) - 3'h1, - 3'h2, - 3'h3: - foobar = {foobar, " 1202"}; - default: - begin - foobar = {foobar, " 1203"}; - foobar = {foobar, " 1204"}; - ozonexe(foo[ 8: 5], foobar); - end - endcase - dude(foobar); - $fwrite (fd, " 1205:%s", foobar); - end - 17'b00_10??_?_????_?0_0101 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1206"}; - case (foo[11: 9]) - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1207"}; - default: - begin - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1208"}; - foobar = {foobar, " 1209"}; - end - endcase - foobar = {foobar, " 1210"}; - foobar = {foobar, " 1211"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1212"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1213:%s", foobar); - end - 17'b00_10??_?_????_?1_1110 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1214"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1215"}; - foobar = {foobar, " 1216"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1217"}; - foobar = {foobar, " 1218"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1219"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1220:%s", foobar); - end - 17'b00_10??_?_????_?0_1000 : - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1221"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1222"}; - foobar = {foobar, " 1223"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1224"}; - foobar = {foobar, " 1225"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1226"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1227:%s", foobar); - end - 17'b10_01??_?_????_??_???? : - begin - if (foo[27]) - foobar = " 1228"; - else - foobar = " 1229"; - ozonecon(foo[20:16], foobar); - foobar = {foobar, " 1230"}; - ozonef2(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1231:%s", foobar); - end - 17'b00_1000_?_????_01_0011 : - if (~|foo[ 9: 8]) - begin - if (foo[ 7]) - foobar = " 1232"; - else - foobar = " 1233"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1234"}; - ozonef2e(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1235:%s", foobar); - end - else - begin - foobar = " 1236"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1237"}; - ozonef3e(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1238:%s", foobar); - end - 17'b11_110?_1_????_??_???? : - begin - ozonef3(foo[31:0], foobar); - dude(foobar); - $fwrite(fd, " 1239:%s", foobar); - end - 17'b11_110?_0_????_??_???? : - begin : f4_body - casez (foo[24:20]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite (fd, " 1240"); - end - 5'b0_00??: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1241"}; - ozoneacc(foo[25], foobar); - ozonebmuop(foo[24:20], foobar); - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1242"}; - dude(foobar); - $fwrite(fd, " 1243:%s", foobar); - end - 5'b0_01??: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1244"}; - ozoneacc(foo[25], foobar); - ozonebmuop(foo[24:20], foobar); - ozonearm(foo[18:16], foobar); - dude(foobar); - $fwrite(fd, " 1245:%s", foobar); - end - 5'b0_1011: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1246"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1247"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1248"}; - dude(foobar); - $fwrite(fd, " 1249:%s", foobar); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1250"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1251"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1252"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1253"}; - dude(foobar); - $fwrite(fd, " 1254:%s", foobar); - end - 5'b0_1111 : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1255"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1256"}; - ozoneae(foo[18:16], foobar); - dude(foobar); - $fwrite(fd, " 1257:%s", foobar); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1258"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1259"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1260"}; - ozonearm(foo[18:16], foobar); - foobar = {foobar, " 1261"}; - dude(foobar); - $fwrite(fd, " 1262:%s", foobar); - end - endcase - end - 17'b11_100?_?_????_??_???? : - casez (foo[23:19]) - 5'b111??, - 5'b0111?: - begin - ozoneae(foo[26:24], foobar); - foobar = {foobar, " 1263"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1264"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1265"}; - skyway(foo[15:12], foobar); - skyway(foo[11: 8], foobar); - skyway(foo[ 7: 4], foobar); - skyway(foo[ 3:0], foobar); - foobar = {foobar, " 1266"}; - dude(foobar); - $fwrite(fd, " 1267:%s", foobar); - end - 5'b?0???, - 5'b110??: - begin - ozoneae(foo[26:24], foobar); - foobar = {foobar, " 1268"}; - if (foo[23:21] == 3'b100) - foobar = {foobar, " 1269"}; - ozoneae(foo[18:16], foobar); - if (foo[19]) - foobar = {foobar, " 1270"}; - else - foobar = {foobar, " 1271"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1272"}; - ozonef3f4_iext(foo[20:19], foo[15:0], foobar); - dude(foobar); - $fwrite(fd, " 1273:%s", foobar); - end - 5'b010??, - 5'b0110?: - begin - ozoneae(foo[18:16], foobar); - if (foo[19]) - foobar = {foobar, " 1274"}; - else - foobar = {foobar, " 1275"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1276"}; - ozonef3f4_iext(foo[20:19], foo[15:0], foobar); - dude(foobar); - $fwrite(fd, " 1277:%s", foobar); - end - endcase - 17'b00_1000_?_????_11_0011 : - begin - foobar = " 1278"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1279"}; - casez (foo[25:21]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite(fd, " 1280"); - end - 5'b0_00??: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1281"}; - ozoneae(foo[17:15], foobar); - ozonebmuop(foo[25:21], foobar); - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1282"}; - dude(foobar); - $fwrite(fd, " 1283:%s", foobar); - end - 5'b0_01??: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1284"}; - ozoneae(foo[17:15], foobar); - ozonebmuop(foo[25:21], foobar); - ozonearm(foo[ 8: 6], foobar); - dude(foobar); - $fwrite(fd, " 1285:%s", foobar); - end - 5'b0_1011: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1286"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1287"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1288"}; - dude(foobar); - $fwrite(fd, " 1289:%s", foobar); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1290"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1291"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1292"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1293"}; - dude(foobar); - $fwrite(fd, " 1294:%s", foobar); - end - 5'b0_1111 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1295"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1296"}; - ozoneae(foo[ 8: 6], foobar); - dude(foobar); - $fwrite(fd, " 1297:%s", foobar); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1298"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1299"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1300"}; - ozonearm(foo[ 8: 6], foobar); - foobar = {foobar, " 1301"}; - dude(foobar); - $fwrite(fd, " 1302:%s", foobar); - end - endcase - end - 17'b00_0010_?_????_??_???? : - begin - $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); - ozonerab({1'b0, foo[25:20]}, foobar); - $fwrite(fd, " 1304b:%x", foobar); - foobar = {foobar, " 1303"}; - $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); - skyway(foo[19:16], foobar); - $fwrite(fd, " 1304d:%x", foobar); - dude(foobar); - $fwrite(fd, " 1304e:%x", foobar); - $fwrite(fd, " 1304:%s", foobar); - end - 17'b00_01??_?_????_??_???? : - begin - if (foo[27]) - begin - foobar = {foobar, " 1305"}; - if (foo[26]) - foobar = {foobar, " 1306"}; - else - foobar = {foobar, " 1307"}; - skyway(foo[19:16], foobar); - foobar = {foobar, " 1308"}; - ozonerab({1'b0, foo[25:20]}, foobar); - end - else - begin - ozonerab({1'b0, foo[25:20]}, foobar); - foobar = {foobar, " 1309"}; - if (foo[26]) - foobar = {foobar, " 1310"}; - else - foobar = {foobar, " 1311"}; - skyway(foo[19:16], foobar); - foobar = {foobar, " 1312"}; - end - dude(foobar); - $fwrite(fd, " 1313:%s", foobar); - end - 17'b01_000?_?_????_??_???? : - begin - if (foo[26]) - begin - ozonerb(foo[25:20], foobar); - foobar = {foobar, " 1314"}; - ozoneae(foo[18:16], foobar); - ozonehl(foo[19], foobar); - end - else - begin - ozoneae(foo[18:16], foobar); - ozonehl(foo[19], foobar); - foobar = {foobar, " 1315"}; - ozonerb(foo[25:20], foobar); - end - dude(foobar); - $fwrite(fd, " 1316:%s", foobar); - end - 17'b01_10??_?_????_??_???? : - begin - if (foo[27]) - begin - ozonerab({1'b0, foo[25:20]}, foobar); - foobar = {foobar, " 1317"}; - ozonerx(foo, foobar); - end - else - begin - ozonerx(foo, foobar); - foobar = {foobar, " 1318"}; - ozonerab({1'b0, foo[25:20]}, foobar); - end - dude(foobar); - $fwrite(fd, " 1319:%s", foobar); - end - 17'b11_101?_?_????_??_???? : - begin - ozonerab (foo[26:20], foobar); - foobar = {foobar, " 1320"}; - skyway(foo[19:16], foobar); - skyway(foo[15:12], foobar); - skyway(foo[11: 8], foobar); - skyway(foo[ 7: 4], foobar); - skyway(foo[ 3: 0], foobar); - dude(foobar); - $fwrite(fd, " 1321:%s", foobar); - end - 17'b11_0000_?_????_??_???? : - begin - casez (foo[25:23]) - 3'b00?: - begin - ozonerab(foo[22:16], foobar); - foobar = {foobar, " 1322"}; - end - 3'b01?: - begin - foobar = {foobar, " 1323"}; - if (foo[22:16]>=7'h60) - foobar = {foobar, " 1324"}; - else - ozonerab(foo[22:16], foobar); - end - 3'b110: - foobar = {foobar, " 1325"}; - 3'b10?: - begin - foobar = {foobar, " 1326"}; - if (foo[22:16]>=7'h60) - foobar = {foobar, " 1327"}; - else - ozonerab(foo[22:16], foobar); - end - 3'b111: - begin - foobar = {foobar, " 1328"}; - ozonerab(foo[22:16], foobar); - foobar = {foobar, " 1329"}; - end - endcase - dude(foobar); - $fwrite(fd, " 1330:%s", foobar); - end - 17'b00_10??_?_????_?1_0000 : - begin - if (foo[27]) - begin - foobar = {foobar, " 1331"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1332"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - foobar = {foobar, " 1333"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1334"}; - else - ozonerab(foo[26:20], foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1335"}; - foobar = {foobar, " 1336"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1337"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - foobar = {foobar, " 1338"}; - end - dude(foobar); - $fwrite(fd, " 1339:%s", foobar); - end - 17'b00_101?_1_0000_?1_0010 : - if (~|foo[11: 7]) - begin - if (foo[ 6]) - begin - foobar = {foobar, " 1340"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1341"}; - ozonejk(foo[ 5], foobar); - foobar = {foobar, " 1342"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1343"}; - else - ozonerab(foo[26:20], foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1344"}; - foobar = {foobar, " 1345"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1346"}; - ozonejk(foo[ 5], foobar); - foobar = {foobar, " 1347"}; - end - dude(foobar); - $fwrite(fd, " 1348:%s", foobar); - end - else - $fwrite(fd, " 1349"); - 17'b00_100?_0_0011_?1_0101 : - if (~|foo[ 8: 7]) - begin - if (foo[6]) - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1350"}; - ozoneye(foo[14: 9],foo[ 5], foobar); - end - else - begin - ozoneye(foo[14: 9],foo[ 5], foobar); - foobar = {foobar, " 1351"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1352"}; - else - ozonerab(foo[26:20], foobar); - end - dude(foobar); - $fwrite(fd, " 1353:%s", foobar); - end - else - $fwrite(fd, " 1354"); - 17'b00_1001_0_0000_?1_0010 : - if (~|foo[25:20]) - begin - ozoneye(foo[14: 9],1'b0, foobar); - foobar = {foobar, " 1355"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1356"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1357"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1358:%s", foobar); - end - else - $fwrite(fd, " 1359"); - 17'b00_101?_0_????_?1_0010 : - if (~foo[13]) - begin - if (foo[12]) - begin - foobar = {foobar, " 1360"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1361"}; - else - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1362"}; - foobar = {foobar, " 1363"}; - skyway({1'b0,foo[18:16]}, foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1364:%s", foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1365"}; - foobar = {foobar, " 1366"}; - skyway({1'b0,foo[18:16]}, foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1367:%s", foobar); - end - end - else - $fwrite(fd, " 1368"); - 17'b01_01??_?_????_??_???? : - begin - ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); - foobar = {foobar, " 1369"}; - ozonerab({1'b0,foo[25:20]}, foobar); - dude(foobar); - $fwrite(fd, " 1370:%s", foobar); - end - 17'b00_100?_?_???0_11_0101 : - if (~foo[6]) - begin - foobar = " 1371"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1372"}; - ozonerab({foo[ 9: 7],foo[19:16]}, foobar); - foobar = {foobar, " 1373"}; - ozonerab({foo[26:20]}, foobar); - dude(foobar); - $fwrite(fd, " 1374:%s", foobar); - end - else - $fwrite(fd, " 1375"); - 17'b00_1000_?_????_?1_0010 : - if (~|foo[25:24]) - begin - ozonery(foo[23:20], foobar); - foobar = {foobar, " 1376"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1377"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1378:%s", foobar); - end - else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) - begin - ozonery(foo[23:20], foobar); - foobar = {foobar, " 1379"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1380"}; - ozonejk(foo[ 5], foobar); - dude(foobar); - $fwrite(fd, " 1381:%s", foobar); - end - else - $fwrite(fd, " 1382"); - 17'b11_01??_?_????_??_????, - 17'b10_00??_?_????_??_???? : - if (foo[30]) - $fwrite(fd, " 1383:%s", foo[27:16]); - else - $fwrite(fd, " 1384:%s", foo[27:16]); - 17'b00_10??_?_????_01_1000 : - if (~foo[6]) - begin - if (foo[7]) - $fwrite(fd, " 1385:%s", foo[27: 8]); - else - $fwrite(fd, " 1386:%s", foo[27: 8]); - end - else - $fwrite(fd, " 1387"); - 17'b00_10??_?_????_11_1000 : - begin - foobar = " 1388"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1389"}; - if (foo[15]) - foobar = {foobar, " 1390"}; - else - foobar = {foobar, " 1391"}; - skyway(foo[27:24], foobar); - skyway(foo[23:20], foobar); - skyway(foo[19:16], foobar); - skyway(foo[ 9: 6], foobar); - dude(foobar); - $fwrite(fd, " 1392:%s", foobar); - end - 17'b11_0001_?_????_??_???? : - casez (foo[25:22]) - 4'b01?? : - begin - foobar = " 1393"; - ozonecon(foo[20:16], foobar); - case (foo[23:21]) - 3'h0 : foobar = {foobar, " 1394"}; - 3'h1 : foobar = {foobar, " 1395"}; - 3'h2 : foobar = {foobar, " 1396"}; - 3'h3 : foobar = {foobar, " 1397"}; - 3'h4 : foobar = {foobar, " 1398"}; - 3'h5 : foobar = {foobar, " 1399"}; - 3'h6 : foobar = {foobar, " 1400"}; - 3'h7 : foobar = {foobar, " 1401"}; - endcase - dude(foobar); - $fwrite(fd, " 1402:%s", foobar); - end - 4'b0000 : - $fwrite(fd, " 1403:%s", foo[21:16]); - 4'b0010 : - if (~|foo[21:16]) - $fwrite(fd, " 1404"); - 4'b1010 : - if (~|foo[21:17]) - begin - if (foo[16]) - $fwrite(fd, " 1405"); - else - $fwrite(fd, " 1406"); - end - default : - $fwrite(fd, " 1407"); - endcase - 17'b01_11??_?_????_??_???? : - if (foo[27:23] === 5'h00) - $fwrite(fd, " 1408:%s", foo[22:16]); - else - $fwrite(fd, " 1409:%s", foo[22:16]); - default: $fwrite(fd, " 1410"); - endcase - end - endtask - - //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) - //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v index 4123415ee..c00496a14 100644 --- a/test_regress/t/t_case_write2.v +++ b/test_regress/t/t_case_write2.v @@ -6,41 +6,39 @@ `define STRINGIFY(x) `"x`" -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [63:0] crc; + integer fd; + integer fdtmp; - reg [63:0] crc; - integer fd; - integer fdtmp; + t_case_write2_tasks tasks (); - t_case_write2_tasks tasks (); + integer cyc; + initial cyc = 0; - integer cyc; initial cyc = 0; + always @(posedge clk) begin + $fwrite(fd, "[%0d] crc=%x ", cyc, crc); + tasks.big_case(fd, crc[31:0]); + $fwrite(fd, "\n"); + end - always @ (posedge clk) begin - $fwrite(fd, "[%0d] crc=%x ", cyc, crc); - tasks.big_case(fd, crc[31:0]); - $fwrite(fd, "\n"); - end - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==1) begin - crc <= 64'h00000000_00000097; - $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); - fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); - fd <= fdtmp; - end - if (cyc==90) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 1) begin + crc <= 64'h00000000_00000097; + $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); + fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); + fd <= fdtmp; + end + if (cyc == 90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_case_write2_tasks.v b/test_regress/t/t_case_write2_tasks.v index 6298dbadf..764f1119d 100644 --- a/test_regress/t/t_case_write2_tasks.v +++ b/test_regress/t/t_case_write2_tasks.v @@ -4,3769 +4,3770 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t_case_write2_tasks (); - // verilator lint_off WIDTH - // verilator lint_off CASEINCOMPLETE + // verilator lint_off WIDTH + // verilator lint_off CASEINCOMPLETE `define FD_BITS 31:0 - parameter STRLEN = 78; - task ozonerab; - input [6:0] rab; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (rab[6:0]) - 7'h00 : $fwrite (fd, " 0"); - 7'h01 : $fwrite (fd, " 1"); - 7'h02 : $fwrite (fd, " 2"); - 7'h03 : $fwrite (fd, " 3"); - 7'h04 : $fwrite (fd, " 4"); - 7'h05 : $fwrite (fd, " 5"); - 7'h06 : $fwrite (fd, " 6"); - 7'h07 : $fwrite (fd, " 7"); - 7'h08 : $fwrite (fd, " 8"); - 7'h09 : $fwrite (fd, " 9"); - 7'h0a : $fwrite (fd, " 10"); - 7'h0b : $fwrite (fd, " 11"); - 7'h0c : $fwrite (fd, " 12"); - 7'h0d : $fwrite (fd, " 13"); - 7'h0e : $fwrite (fd, " 14"); - 7'h0f : $fwrite (fd, " 15"); - 7'h10 : $fwrite (fd, " 16"); - 7'h11 : $fwrite (fd, " 17"); - 7'h12 : $fwrite (fd, " 18"); - 7'h13 : $fwrite (fd, " 19"); - 7'h14 : $fwrite (fd, " 20"); - 7'h15 : $fwrite (fd, " 21"); - 7'h16 : $fwrite (fd, " 22"); - 7'h17 : $fwrite (fd, " 23"); - 7'h18 : $fwrite (fd, " 24"); - 7'h19 : $fwrite (fd, " 25"); - 7'h1a : $fwrite (fd, " 26"); - 7'h1b : $fwrite (fd, " 27"); - 7'h1c : $fwrite (fd, " 28"); - 7'h1d : $fwrite (fd, " 29"); - 7'h1e : $fwrite (fd, " 30"); - 7'h1f : $fwrite (fd, " 31"); - 7'h20 : $fwrite (fd, " 32"); - 7'h21 : $fwrite (fd, " 33"); - 7'h22 : $fwrite (fd, " 34"); - 7'h23 : $fwrite (fd, " 35"); - 7'h24 : $fwrite (fd, " 36"); - 7'h25 : $fwrite (fd, " 37"); - 7'h26 : $fwrite (fd, " 38"); - 7'h27 : $fwrite (fd, " 39"); - 7'h28 : $fwrite (fd, " 40"); - 7'h29 : $fwrite (fd, " 41"); - 7'h2a : $fwrite (fd, " 42"); - 7'h2b : $fwrite (fd, " 43"); - 7'h2c : $fwrite (fd, " 44"); - 7'h2d : $fwrite (fd, " 45"); - 7'h2e : $fwrite (fd, " 46"); - 7'h2f : $fwrite (fd, " 47"); - 7'h30 : $fwrite (fd, " 48"); - 7'h31 : $fwrite (fd, " 49"); - 7'h32 : $fwrite (fd, " 50"); - 7'h33 : $fwrite (fd, " 51"); - 7'h34 : $fwrite (fd, " 52"); - 7'h35 : $fwrite (fd, " 53"); - 7'h36 : $fwrite (fd, " 54"); - 7'h37 : $fwrite (fd, " 55"); - 7'h38 : $fwrite (fd, " 56"); - 7'h39 : $fwrite (fd, " 57"); - 7'h3a : $fwrite (fd, " 58"); - 7'h3b : $fwrite (fd, " 59"); - 7'h3c : $fwrite (fd, " 60"); - 7'h3d : $fwrite (fd, " 61"); - 7'h3e : $fwrite (fd, " 62"); - 7'h3f : $fwrite (fd, " 63"); - 7'h40 : $fwrite (fd, " 64"); - 7'h41 : $fwrite (fd, " 65"); - 7'h42 : $fwrite (fd, " 66"); - 7'h43 : $fwrite (fd, " 67"); - 7'h44 : $fwrite (fd, " 68"); - 7'h45 : $fwrite (fd, " 69"); - 7'h46 : $fwrite (fd, " 70"); - 7'h47 : $fwrite (fd, " 71"); - 7'h48 : $fwrite (fd, " 72"); - 7'h49 : $fwrite (fd, " 73"); - 7'h4a : $fwrite (fd, " 74"); - 7'h4b : $fwrite (fd, " 75"); - 7'h4c : $fwrite (fd, " 76"); - 7'h4d : $fwrite (fd, " 77"); - 7'h4e : $fwrite (fd, " 78"); - 7'h4f : $fwrite (fd, " 79"); - 7'h50 : $fwrite (fd, " 80"); - 7'h51 : $fwrite (fd, " 81"); - 7'h52 : $fwrite (fd, " 82"); - 7'h53 : $fwrite (fd, " 83"); - 7'h54 : $fwrite (fd, " 84"); - 7'h55 : $fwrite (fd, " 85"); - 7'h56 : $fwrite (fd, " 86"); - 7'h57 : $fwrite (fd, " 87"); - 7'h58 : $fwrite (fd, " 88"); - 7'h59 : $fwrite (fd, " 89"); - 7'h5a : $fwrite (fd, " 90"); - 7'h5b : $fwrite (fd, " 91"); - 7'h5c : $fwrite (fd, " 92"); - 7'h5d : $fwrite (fd, " 93"); - 7'h5e : $fwrite (fd, " 94"); - 7'h5f : $fwrite (fd, " 95"); - 7'h60 : $fwrite (fd, " 96"); - 7'h61 : $fwrite (fd, " 97"); - 7'h62 : $fwrite (fd, " 98"); - 7'h63 : $fwrite (fd, " 99"); - 7'h64 : $fwrite (fd, " 100"); - 7'h65 : $fwrite (fd, " 101"); - 7'h66 : $fwrite (fd, " 102"); - 7'h67 : $fwrite (fd, " 103"); - 7'h68 : $fwrite (fd, " 104"); - 7'h69 : $fwrite (fd, " 105"); - 7'h6a : $fwrite (fd, " 106"); - 7'h6b : $fwrite (fd, " 107"); - 7'h6c : $fwrite (fd, " 108"); - 7'h6d : $fwrite (fd, " 109"); - 7'h6e : $fwrite (fd, " 110"); - 7'h6f : $fwrite (fd, " 111"); - 7'h70 : $fwrite (fd, " 112"); - 7'h71 : $fwrite (fd, " 113"); - 7'h72 : $fwrite (fd, " 114"); - 7'h73 : $fwrite (fd, " 115"); - 7'h74 : $fwrite (fd, " 116"); - 7'h75 : $fwrite (fd, " 117"); - 7'h76 : $fwrite (fd, " 118"); - 7'h77 : $fwrite (fd, " 119"); - 7'h78 : $fwrite (fd, " 120"); - 7'h79 : $fwrite (fd, " 121"); - 7'h7a : $fwrite (fd, " 122"); - 7'h7b : $fwrite (fd, " 123"); - 7'h7c : $fwrite (fd, " 124"); - 7'h7d : $fwrite (fd, " 125"); - 7'h7e : $fwrite (fd, " 126"); - 7'h7f : $fwrite (fd, " 127"); - default:$fwrite (fd, " 128"); - endcase - end - endtask + parameter STRLEN = 78; + task ozonerab; + input [6:0] rab; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rab[6:0]) + 7'h00 : $fwrite (fd, " 0"); + 7'h01 : $fwrite (fd, " 1"); + 7'h02 : $fwrite (fd, " 2"); + 7'h03 : $fwrite (fd, " 3"); + 7'h04 : $fwrite (fd, " 4"); + 7'h05 : $fwrite (fd, " 5"); + 7'h06 : $fwrite (fd, " 6"); + 7'h07 : $fwrite (fd, " 7"); + 7'h08 : $fwrite (fd, " 8"); + 7'h09 : $fwrite (fd, " 9"); + 7'h0a : $fwrite (fd, " 10"); + 7'h0b : $fwrite (fd, " 11"); + 7'h0c : $fwrite (fd, " 12"); + 7'h0d : $fwrite (fd, " 13"); + 7'h0e : $fwrite (fd, " 14"); + 7'h0f : $fwrite (fd, " 15"); + 7'h10 : $fwrite (fd, " 16"); + 7'h11 : $fwrite (fd, " 17"); + 7'h12 : $fwrite (fd, " 18"); + 7'h13 : $fwrite (fd, " 19"); + 7'h14 : $fwrite (fd, " 20"); + 7'h15 : $fwrite (fd, " 21"); + 7'h16 : $fwrite (fd, " 22"); + 7'h17 : $fwrite (fd, " 23"); + 7'h18 : $fwrite (fd, " 24"); + 7'h19 : $fwrite (fd, " 25"); + 7'h1a : $fwrite (fd, " 26"); + 7'h1b : $fwrite (fd, " 27"); + 7'h1c : $fwrite (fd, " 28"); + 7'h1d : $fwrite (fd, " 29"); + 7'h1e : $fwrite (fd, " 30"); + 7'h1f : $fwrite (fd, " 31"); + 7'h20 : $fwrite (fd, " 32"); + 7'h21 : $fwrite (fd, " 33"); + 7'h22 : $fwrite (fd, " 34"); + 7'h23 : $fwrite (fd, " 35"); + 7'h24 : $fwrite (fd, " 36"); + 7'h25 : $fwrite (fd, " 37"); + 7'h26 : $fwrite (fd, " 38"); + 7'h27 : $fwrite (fd, " 39"); + 7'h28 : $fwrite (fd, " 40"); + 7'h29 : $fwrite (fd, " 41"); + 7'h2a : $fwrite (fd, " 42"); + 7'h2b : $fwrite (fd, " 43"); + 7'h2c : $fwrite (fd, " 44"); + 7'h2d : $fwrite (fd, " 45"); + 7'h2e : $fwrite (fd, " 46"); + 7'h2f : $fwrite (fd, " 47"); + 7'h30 : $fwrite (fd, " 48"); + 7'h31 : $fwrite (fd, " 49"); + 7'h32 : $fwrite (fd, " 50"); + 7'h33 : $fwrite (fd, " 51"); + 7'h34 : $fwrite (fd, " 52"); + 7'h35 : $fwrite (fd, " 53"); + 7'h36 : $fwrite (fd, " 54"); + 7'h37 : $fwrite (fd, " 55"); + 7'h38 : $fwrite (fd, " 56"); + 7'h39 : $fwrite (fd, " 57"); + 7'h3a : $fwrite (fd, " 58"); + 7'h3b : $fwrite (fd, " 59"); + 7'h3c : $fwrite (fd, " 60"); + 7'h3d : $fwrite (fd, " 61"); + 7'h3e : $fwrite (fd, " 62"); + 7'h3f : $fwrite (fd, " 63"); + 7'h40 : $fwrite (fd, " 64"); + 7'h41 : $fwrite (fd, " 65"); + 7'h42 : $fwrite (fd, " 66"); + 7'h43 : $fwrite (fd, " 67"); + 7'h44 : $fwrite (fd, " 68"); + 7'h45 : $fwrite (fd, " 69"); + 7'h46 : $fwrite (fd, " 70"); + 7'h47 : $fwrite (fd, " 71"); + 7'h48 : $fwrite (fd, " 72"); + 7'h49 : $fwrite (fd, " 73"); + 7'h4a : $fwrite (fd, " 74"); + 7'h4b : $fwrite (fd, " 75"); + 7'h4c : $fwrite (fd, " 76"); + 7'h4d : $fwrite (fd, " 77"); + 7'h4e : $fwrite (fd, " 78"); + 7'h4f : $fwrite (fd, " 79"); + 7'h50 : $fwrite (fd, " 80"); + 7'h51 : $fwrite (fd, " 81"); + 7'h52 : $fwrite (fd, " 82"); + 7'h53 : $fwrite (fd, " 83"); + 7'h54 : $fwrite (fd, " 84"); + 7'h55 : $fwrite (fd, " 85"); + 7'h56 : $fwrite (fd, " 86"); + 7'h57 : $fwrite (fd, " 87"); + 7'h58 : $fwrite (fd, " 88"); + 7'h59 : $fwrite (fd, " 89"); + 7'h5a : $fwrite (fd, " 90"); + 7'h5b : $fwrite (fd, " 91"); + 7'h5c : $fwrite (fd, " 92"); + 7'h5d : $fwrite (fd, " 93"); + 7'h5e : $fwrite (fd, " 94"); + 7'h5f : $fwrite (fd, " 95"); + 7'h60 : $fwrite (fd, " 96"); + 7'h61 : $fwrite (fd, " 97"); + 7'h62 : $fwrite (fd, " 98"); + 7'h63 : $fwrite (fd, " 99"); + 7'h64 : $fwrite (fd, " 100"); + 7'h65 : $fwrite (fd, " 101"); + 7'h66 : $fwrite (fd, " 102"); + 7'h67 : $fwrite (fd, " 103"); + 7'h68 : $fwrite (fd, " 104"); + 7'h69 : $fwrite (fd, " 105"); + 7'h6a : $fwrite (fd, " 106"); + 7'h6b : $fwrite (fd, " 107"); + 7'h6c : $fwrite (fd, " 108"); + 7'h6d : $fwrite (fd, " 109"); + 7'h6e : $fwrite (fd, " 110"); + 7'h6f : $fwrite (fd, " 111"); + 7'h70 : $fwrite (fd, " 112"); + 7'h71 : $fwrite (fd, " 113"); + 7'h72 : $fwrite (fd, " 114"); + 7'h73 : $fwrite (fd, " 115"); + 7'h74 : $fwrite (fd, " 116"); + 7'h75 : $fwrite (fd, " 117"); + 7'h76 : $fwrite (fd, " 118"); + 7'h77 : $fwrite (fd, " 119"); + 7'h78 : $fwrite (fd, " 120"); + 7'h79 : $fwrite (fd, " 121"); + 7'h7a : $fwrite (fd, " 122"); + 7'h7b : $fwrite (fd, " 123"); + 7'h7c : $fwrite (fd, " 124"); + 7'h7d : $fwrite (fd, " 125"); + 7'h7e : $fwrite (fd, " 126"); + 7'h7f : $fwrite (fd, " 127"); + default:$fwrite (fd, " 128"); + endcase + end + endtask - task ozonerb; - input [5:0] rb; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (rb[5:0]) - 6'h10, - 6'h17, - 6'h1e, - 6'h1f: $fwrite (fd, " 129"); - default: ozonerab({1'b1, rb}, fd); - endcase - end - endtask + task ozonerb; + input [5:0] rb; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rb[5:0]) + 6'h10, + 6'h17, + 6'h1e, + 6'h1f: $fwrite (fd, " 129"); + default: ozonerab({1'b1, rb}, fd); + endcase + end + endtask - task ozonef3f4_iext; - input [1:0] foo; - input [15:0] im16; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo) - 2'h0 : - begin - skyway({4{im16[15]}}, fd); - skyway({4{im16[15]}}, fd); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - $fwrite (fd, " 130"); - end - 2'h1 : - begin - $fwrite (fd, " 131"); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - end - 2'h2 : - begin - skyway({4{im16[15]}}, fd); - skyway({4{im16[15]}}, fd); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - $fwrite (fd, " 132"); - end - 2'h3 : - begin - $fwrite (fd, " 133"); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - end - endcase - end - endtask + task ozonef3f4_iext; + input [1:0] foo; + input [15:0] im16; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : + begin + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 130"); + end + 2'h1 : + begin + $fwrite (fd, " 131"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + end + 2'h2 : + begin + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 132"); + end + 2'h3 : + begin + $fwrite (fd, " 133"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + end + endcase + end + endtask - task skyway; - input [ 3:0] hex; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (hex) - 4'h0 : $fwrite (fd, " 134"); - 4'h1 : $fwrite (fd, " 135"); - 4'h2 : $fwrite (fd, " 136"); - 4'h3 : $fwrite (fd, " 137"); - 4'h4 : $fwrite (fd, " 138"); - 4'h5 : $fwrite (fd, " 139"); - 4'h6 : $fwrite (fd, " 140"); - 4'h7 : $fwrite (fd, " 141"); - 4'h8 : $fwrite (fd, " 142"); - 4'h9 : $fwrite (fd, " 143"); - 4'ha : $fwrite (fd, " 144"); - 4'hb : $fwrite (fd, " 145"); - 4'hc : $fwrite (fd, " 146"); - 4'hd : $fwrite (fd, " 147"); - 4'he : $fwrite (fd, " 148"); - 4'hf : $fwrite (fd, " 149"); - endcase - end - endtask + task skyway; + input [ 3:0] hex; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (hex) + 4'h0 : $fwrite (fd, " 134"); + 4'h1 : $fwrite (fd, " 135"); + 4'h2 : $fwrite (fd, " 136"); + 4'h3 : $fwrite (fd, " 137"); + 4'h4 : $fwrite (fd, " 138"); + 4'h5 : $fwrite (fd, " 139"); + 4'h6 : $fwrite (fd, " 140"); + 4'h7 : $fwrite (fd, " 141"); + 4'h8 : $fwrite (fd, " 142"); + 4'h9 : $fwrite (fd, " 143"); + 4'ha : $fwrite (fd, " 144"); + 4'hb : $fwrite (fd, " 145"); + 4'hc : $fwrite (fd, " 146"); + 4'hd : $fwrite (fd, " 147"); + 4'he : $fwrite (fd, " 148"); + 4'hf : $fwrite (fd, " 149"); + endcase + end + endtask - task ozonesr; - input [ 15:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[11: 9]) - 3'h0 : $fwrite (fd, " 158"); - 3'h1 : $fwrite (fd, " 159"); - 3'h2 : $fwrite (fd, " 160"); - 3'h3 : $fwrite (fd, " 161"); - 3'h4 : $fwrite (fd, " 162"); - 3'h5 : $fwrite (fd, " 163"); - 3'h6 : $fwrite (fd, " 164"); - 3'h7 : $fwrite (fd, " 165"); - endcase - end - endtask + task ozonesr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[11: 9]) + 3'h0 : $fwrite (fd, " 158"); + 3'h1 : $fwrite (fd, " 159"); + 3'h2 : $fwrite (fd, " 160"); + 3'h3 : $fwrite (fd, " 161"); + 3'h4 : $fwrite (fd, " 162"); + 3'h5 : $fwrite (fd, " 163"); + 3'h6 : $fwrite (fd, " 164"); + 3'h7 : $fwrite (fd, " 165"); + endcase + end + endtask - task ozonejk; - input k; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - if (k) - $fwrite (fd, " 166"); + task ozonejk; + input k; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + if (k) + $fwrite (fd, " 166"); + else + $fwrite (fd, " 167"); + end + endtask + + task ozoneae; + input [ 2:0] ae; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ae) + 3'b000 : $fwrite (fd, " 168"); + 3'b001 : $fwrite (fd, " 169"); + 3'b010 : $fwrite (fd, " 170"); + 3'b011 : $fwrite (fd, " 171"); + 3'b100 : $fwrite (fd, " 172"); + 3'b101 : $fwrite (fd, " 173"); + 3'b110 : $fwrite (fd, " 174"); + 3'b111 : $fwrite (fd, " 175"); + endcase + end + endtask + + task ozoneaee; + input [ 2:0] aee; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (aee) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 176"); + 3'b000 : $fwrite (fd, " 177"); + 3'b010 : $fwrite (fd, " 178"); + 3'b100 : $fwrite (fd, " 179"); + 3'b110 : $fwrite (fd, " 180"); + endcase + end + endtask + + task ozoneape; + input [ 2:0] ape; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ape) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 181"); + 3'b000 : $fwrite (fd, " 182"); + 3'b010 : $fwrite (fd, " 183"); + 3'b100 : $fwrite (fd, " 184"); + 3'b110 : $fwrite (fd, " 185"); + endcase + end + endtask + + task ozonef1; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + if (foo[26]) + $fwrite (fd, " 186"); else - $fwrite (fd, " 167"); - end - endtask - - task ozoneae; - input [ 2:0] ae; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (ae) - 3'b000 : $fwrite (fd, " 168"); - 3'b001 : $fwrite (fd, " 169"); - 3'b010 : $fwrite (fd, " 170"); - 3'b011 : $fwrite (fd, " 171"); - 3'b100 : $fwrite (fd, " 172"); - 3'b101 : $fwrite (fd, " 173"); - 3'b110 : $fwrite (fd, " 174"); - 3'b111 : $fwrite (fd, " 175"); + $fwrite (fd, " 187"); + 4'h1 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 188"); + 2'b01 : $fwrite (fd, " 189"); + 2'b10 : $fwrite (fd, " 190"); + 2'b11 : $fwrite (fd, " 191"); endcase - end - endtask - - task ozoneaee; - input [ 2:0] aee; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (aee) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : $fwrite (fd, " 176"); - 3'b000 : $fwrite (fd, " 177"); - 3'b010 : $fwrite (fd, " 178"); - 3'b100 : $fwrite (fd, " 179"); - 3'b110 : $fwrite (fd, " 180"); + 4'h2 : $fwrite (fd, " 192"); + 4'h3 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 193"); + 2'b01 : $fwrite (fd, " 194"); + 2'b10 : $fwrite (fd, " 195"); + 2'b11 : $fwrite (fd, " 196"); endcase - end - endtask - - task ozoneape; - input [ 2:0] ape; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (ape) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : $fwrite (fd, " 181"); - 3'b000 : $fwrite (fd, " 182"); - 3'b010 : $fwrite (fd, " 183"); - 3'b100 : $fwrite (fd, " 184"); - 3'b110 : $fwrite (fd, " 185"); + 4'h4 : + if (foo[26]) + $fwrite (fd, " 197"); + else + $fwrite (fd, " 198"); + 4'h5 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 199"); + 2'b01 : $fwrite (fd, " 200"); + 2'b10 : $fwrite (fd, " 201"); + 2'b11 : $fwrite (fd, " 202"); endcase - end - endtask + 4'h6 : $fwrite (fd, " 203"); + 4'h7 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 204"); + 2'b01 : $fwrite (fd, " 205"); + 2'b10 : $fwrite (fd, " 206"); + 2'b11 : $fwrite (fd, " 207"); + endcase + 4'h8 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 208"); + 2'b01 : $fwrite (fd, " 209"); + 2'b10 : $fwrite (fd, " 210"); + 2'b11 : $fwrite (fd, " 211"); + endcase + 4'h9 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 212"); + 2'b01 : $fwrite (fd, " 213"); + 2'b10 : $fwrite (fd, " 214"); + 2'b11 : $fwrite (fd, " 215"); + endcase + 4'ha : + if (foo[25]) + $fwrite (fd, " 216"); + else + $fwrite (fd, " 217"); + 4'hb : + if (foo[25]) + $fwrite (fd, " 218"); + else + $fwrite (fd, " 219"); + 4'hc : + if (foo[26]) + $fwrite (fd, " 220"); + else + $fwrite (fd, " 221"); + 4'hd : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 222"); + 2'b01 : $fwrite (fd, " 223"); + 2'b10 : $fwrite (fd, " 224"); + 2'b11 : $fwrite (fd, " 225"); + endcase + 4'he : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 226"); + 2'b01 : $fwrite (fd, " 227"); + 2'b10 : $fwrite (fd, " 228"); + 2'b11 : $fwrite (fd, " 229"); + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 230"); + 2'b01 : $fwrite (fd, " 231"); + 2'b10 : $fwrite (fd, " 232"); + 2'b11 : $fwrite (fd, " 233"); + endcase + endcase + end + endtask - task ozonef1; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[24:21]) - 4'h0 : - if (foo[26]) - $fwrite (fd, " 186"); - else - $fwrite (fd, " 187"); - 4'h1 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 188"); - 2'b01 : $fwrite (fd, " 189"); - 2'b10 : $fwrite (fd, " 190"); - 2'b11 : $fwrite (fd, " 191"); - endcase - 4'h2 : $fwrite (fd, " 192"); - 4'h3 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 193"); - 2'b01 : $fwrite (fd, " 194"); - 2'b10 : $fwrite (fd, " 195"); - 2'b11 : $fwrite (fd, " 196"); - endcase - 4'h4 : - if (foo[26]) - $fwrite (fd, " 197"); - else - $fwrite (fd, " 198"); - 4'h5 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 199"); - 2'b01 : $fwrite (fd, " 200"); - 2'b10 : $fwrite (fd, " 201"); - 2'b11 : $fwrite (fd, " 202"); - endcase - 4'h6 : $fwrite (fd, " 203"); - 4'h7 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 204"); - 2'b01 : $fwrite (fd, " 205"); - 2'b10 : $fwrite (fd, " 206"); - 2'b11 : $fwrite (fd, " 207"); - endcase + task ozonef1e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[27:21]) + 7'h00: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 234"); + $fwrite (fd, " 235"); + end + 7'h01: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 236"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 237"); + $fwrite (fd, " 238"); + end + 7'h02: + $fwrite (fd, " 239"); + 7'h03: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 240"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 241"); + $fwrite (fd, " 242"); + end + 7'h04: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 243"); + $fwrite (fd," 244"); + end + 7'h05: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 245"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 246"); + end + 7'h06: + $fwrite (fd, " 247"); + 7'h07: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 248"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 249"); + end + 7'h08: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 250"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 251"); + end + 7'h09: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 252"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 253"); + end + 7'h0a: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 254"); + end + 7'h0b: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 255"); + end + 7'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 256"); + end + 7'h0d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 257"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 258"); + end + 7'h0e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 259"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 260"); + end + 7'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 261"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 262"); + end + 7'h10: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 263"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 264"); + $fwrite (fd, " 265"); + $fwrite (fd, " 266"); + end + 7'h11: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 267"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 268"); + $fwrite (fd, " 269"); + $fwrite (fd, " 270"); + end + 7'h12: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 271"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 272"); + $fwrite (fd, " 273"); + $fwrite (fd, " 274"); + end + 7'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 275"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 276"); + $fwrite (fd, " 277"); + $fwrite (fd, " 278"); + end + 7'h14: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 279"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 280"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 281"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 282"); + $fwrite (fd, " 283"); + $fwrite (fd, " 284"); + end + 7'h15: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 285"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 286"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 287"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 288"); + $fwrite (fd, " 289"); + $fwrite (fd, " 290"); + end + 7'h16: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 291"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 292"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 293"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 294"); + $fwrite (fd, " 295"); + $fwrite (fd, " 296"); + end + 7'h17: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 297"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 298"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 299"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 300"); + $fwrite (fd, " 301"); + $fwrite (fd, " 302"); + end + 7'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 303"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 304"); + $fwrite (fd, " 305"); + $fwrite (fd, " 306"); + end + 7'h19: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 307"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 308"); + $fwrite (fd, " 309"); + $fwrite (fd, " 310"); + end + 7'h1a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 311"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 312"); + $fwrite (fd, " 313"); + $fwrite (fd, " 314"); + end + 7'h1b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 315"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 316"); + $fwrite (fd, " 317"); + $fwrite (fd, " 318"); + end + 7'h1c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 319"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 320"); + $fwrite (fd, " 321"); + $fwrite (fd, " 322"); + end + 7'h1d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 323"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 324"); + $fwrite (fd, " 325"); + $fwrite (fd, " 326"); + end + 7'h1e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 327"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 328"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 329"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 330"); + $fwrite (fd, " 331"); + $fwrite (fd, " 332"); + end + 7'h1f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 333"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 334"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 335"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 336"); + $fwrite (fd, " 337"); + $fwrite (fd, " 338"); + end + 7'h20: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 339"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 340"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 341"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 342"); + $fwrite (fd, " 343"); + $fwrite (fd, " 344"); + end + 7'h21: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 345"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 346"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 347"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 348"); + $fwrite (fd, " 349"); + $fwrite (fd, " 350"); + end + 7'h22: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 351"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 352"); + $fwrite (fd, " 353"); + $fwrite (fd, " 354"); + end + 7'h23: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 355"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 356"); + $fwrite (fd, " 357"); + $fwrite (fd, " 358"); + end + 7'h24: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 359"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 360"); + $fwrite (fd, " 361"); + $fwrite (fd, " 362"); + end + 7'h25: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 363"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 364"); + $fwrite (fd, " 365"); + $fwrite (fd, " 366"); + end + 7'h26: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 367"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 368"); + $fwrite (fd, " 369"); + $fwrite (fd, " 370"); + end + 7'h27: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 371"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 372"); + $fwrite (fd, " 373"); + $fwrite (fd, " 374"); + end + 7'h28: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 375"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 376"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 377"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 378"); + $fwrite (fd, " 379"); + $fwrite (fd, " 380"); + end + 7'h29: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 381"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 382"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 383"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 384"); + $fwrite (fd, " 385"); + $fwrite (fd, " 386"); + end + 7'h2a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 387"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 388"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 389"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 390"); + $fwrite (fd, " 391"); + $fwrite (fd, " 392"); + end + 7'h2b: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 393"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 394"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 395"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 396"); + $fwrite (fd, " 397"); + $fwrite (fd, " 398"); + end + 7'h2c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 399"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 400"); + $fwrite (fd, " 401"); + $fwrite (fd, " 402"); + end + 7'h2d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 403"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 404"); + $fwrite (fd, " 405"); + $fwrite (fd, " 406"); + end + 7'h2e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 407"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 408"); + $fwrite (fd, " 409"); + $fwrite (fd, " 410"); + end + 7'h2f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 411"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 412"); + $fwrite (fd, " 413"); + $fwrite (fd, " 414"); + end + 7'h30: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 415"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 416"); + $fwrite (fd, " 417"); + $fwrite (fd, " 418"); + end + 7'h31: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 419"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 420"); + $fwrite (fd, " 421"); + $fwrite (fd, " 422"); + end + 7'h32: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 423"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 424"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 425"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 426"); + $fwrite (fd, " 427"); + $fwrite (fd, " 428"); + end + 7'h33: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 429"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 430"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 431"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 432"); + $fwrite (fd, " 433"); + $fwrite (fd, " 434"); + end + 7'h34: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 435"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 436"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 437"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 438"); + $fwrite (fd, " 439"); + $fwrite (fd, " 440"); + end + 7'h35: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 441"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 442"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 443"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 444"); + $fwrite (fd, " 445"); + $fwrite (fd, " 446"); + end + 7'h36: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 447"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 448"); + $fwrite (fd, " 449"); + $fwrite (fd, " 450"); + end + 7'h37: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 451"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 452"); + $fwrite (fd, " 453"); + $fwrite (fd, " 454"); + end + 7'h38: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 455"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 456"); + $fwrite (fd, " 457"); + end + 7'h39: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 458"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 459"); + $fwrite (fd, " 460"); + end + 7'h3a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 461"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 462"); + $fwrite (fd, " 463"); + end + 7'h3b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 464"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 465"); + $fwrite (fd, " 466"); + end + 7'h3c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 467"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 468"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 469"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 470"); + $fwrite (fd, " 471"); + end + 7'h3d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 472"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 473"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 474"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 475"); + $fwrite (fd, " 476"); + end + 7'h3e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 477"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 478"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 479"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 480"); + $fwrite (fd, " 481"); + end + 7'h3f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 482"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 483"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 484"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 485"); + $fwrite (fd, " 486"); + end + 7'h40: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 487"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 488"); + $fwrite (fd, " 489"); + $fwrite (fd, " 490"); + end + 7'h41: + begin + $fwrite (fd, " 491"); + $fwrite (fd, " 492"); + end + 7'h42: + begin + $fwrite (fd, " 493"); + $fwrite (fd, " 494"); + end + 7'h43: + begin + $fwrite (fd, " 495"); + $fwrite (fd, " 496"); + end + 7'h44: + begin + $fwrite (fd, " 497"); + $fwrite (fd, " 498"); + end + 7'h45: + $fwrite (fd, " 499"); + 7'h46: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 500"); + $fwrite (fd, " 501"); + $fwrite (fd, " 502"); + end + 7'h47: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 503"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 504"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 505"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 506"); + $fwrite (fd, " 507"); + $fwrite (fd, " 508"); + end + 7'h48: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 509"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 510"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 511"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 512"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 513"); + end + 7'h49: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 514"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 515"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 516"); + end + 7'h4a: + $fwrite (fd," 517"); + 7'h4b: + $fwrite (fd, " 518"); + 7'h4c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 519"); + $fwrite (fd, " 520"); + $fwrite (fd, " 521"); + end + 7'h4d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 522"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 523"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 524"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 525"); + $fwrite (fd, " 526"); + $fwrite (fd, " 527"); + end + 7'h4e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 528"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 529"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 530"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 531"); + end + 7'h4f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 532"); + end + 7'h50: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 533"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 534"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 535"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 536"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 537"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 538"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 539"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 540"); + end + 7'h51: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 541"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 542"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 543"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 544"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 545"); + end + 7'h52: + $fwrite (fd, " 546"); + 7'h53: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 547"); + end + 7'h54: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 548"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 549"); + end + 7'h55: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 550"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 551"); + end + 7'h56: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 552"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 553"); + $fwrite (fd, " 554"); + end + 7'h57: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 555"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 556"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 557"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 558"); + end + 7'h58: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 559"); + end + 7'h59: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 560"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 561"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 562"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 563"); + end + 7'h5a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 564"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 565"); + end + 7'h5b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 566"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 567"); + end + 7'h5c: + begin + $fwrite (fd," 568"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 569"); + $fwrite (fd," 570"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 571"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 572"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 573"); + end + 7'h5d: + begin + $fwrite (fd," 574"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 575"); + $fwrite (fd," 576"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 577"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 578"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 579"); + end + 7'h5e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 580"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 581"); + end + 7'h5f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 582"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 583"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 584"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 585"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 586"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 587"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 588"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 589"); + end + 7'h60: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 590"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 591"); + end + 7'h61: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 592"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 593"); + end + 7'h62: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 594"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 595"); + end + 7'h63: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 596"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 597"); + end + 7'h64: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 598"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 599"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 600"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 601"); + end + 7'h65: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 602"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 603"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 604"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 605"); + end + 7'h66: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 606"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 607"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 608"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 609"); + end + 7'h67: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 610"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 611"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 612"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 613"); + end + 7'h68: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 614"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 615"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 616"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 617"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 618"); + ozoneape(foo[17:15], fd); + end + 7'h69: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 619"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 620"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 621"); + end + 7'h6a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 622"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 623"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 624"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 625"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 626"); + ozoneae(foo[17:15], fd); + end + 7'h6b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 627"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 628"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 629"); + end + 7'h6c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 630"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 631"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 632"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 633"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 634"); + ozoneae(foo[17:15], fd); + end + 7'h6d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 635"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 636"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 637"); + end + 7'h6e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 638"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 639"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 640"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 641"); + end + 7'h6f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 642"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 643"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 644"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 645"); + end + 7'h70: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 646"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 647"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 648"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 649"); + end + 7'h71: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 650"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 651"); + end + 7'h72: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 652"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 653"); + end + 7'h73: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 654"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 655"); + ozoneae(foo[17:15], fd); + end + 7'h74: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 656"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 657"); + ozoneae(foo[17:15], fd); + end + 7'h75: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 658"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 659"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 660"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 661"); + $fwrite (fd, " 662"); + $fwrite (fd, " 663"); + end + 7'h76: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 664"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 665"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 666"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 667"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 668"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 669"); + end + 7'h77: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 670"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 671"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 672"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 673"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 674"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 675"); + end + 7'h78, + 7'h79, + 7'h7a, + 7'h7b, + 7'h7c, + 7'h7d, + 7'h7e, + 7'h7f: + $fwrite (fd," 676"); + endcase + end + endtask + + task ozonef2; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 677"); + 2'b01 : $fwrite (fd," 678"); + 2'b10 : $fwrite (fd," 679"); + 2'b11 : $fwrite (fd," 680"); + endcase + 4'h1 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 681"); + 2'b01 : $fwrite (fd," 682"); + 2'b10 : $fwrite (fd," 683"); + 2'b11 : $fwrite (fd," 684"); + endcase + 4'h2 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 685"); + 2'b01 : $fwrite (fd," 686"); + 2'b10 : $fwrite (fd," 687"); + 2'b11 : $fwrite (fd," 688"); + endcase + 4'h3 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 689"); + 2'b01 : $fwrite (fd," 690"); + 2'b10 : $fwrite (fd," 691"); + 2'b11 : $fwrite (fd," 692"); + endcase + 4'h4 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 693"); + 2'b01 : $fwrite (fd," 694"); + 2'b10 : $fwrite (fd," 695"); + 2'b11 : $fwrite (fd," 696"); + endcase + 4'h5 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 697"); + 2'b01 : $fwrite (fd," 698"); + 2'b10 : $fwrite (fd," 699"); + 2'b11 : $fwrite (fd," 700"); + endcase + 4'h6 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 701"); + 2'b01 : $fwrite (fd," 702"); + 2'b10 : $fwrite (fd," 703"); + 2'b11 : $fwrite (fd," 704"); + endcase + 4'h7 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 705"); + 2'b01 : $fwrite (fd," 706"); + 2'b10 : $fwrite (fd," 707"); + 2'b11 : $fwrite (fd," 708"); + endcase + 4'h8 : + if (foo[26]) + $fwrite (fd," 709"); + else + $fwrite (fd," 710"); + 4'h9 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 711"); + 2'b01 : $fwrite (fd," 712"); + 2'b10 : $fwrite (fd," 713"); + 2'b11 : $fwrite (fd," 714"); + endcase + 4'ha : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 715"); + 2'b01 : $fwrite (fd," 716"); + 2'b10 : $fwrite (fd," 717"); + 2'b11 : $fwrite (fd," 718"); + endcase + 4'hb : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 719"); + 2'b01 : $fwrite (fd," 720"); + 2'b10 : $fwrite (fd," 721"); + 2'b11 : $fwrite (fd," 722"); + endcase + 4'hc : + if (foo[26]) + $fwrite (fd," 723"); + else + $fwrite (fd," 724"); + 4'hd : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 725"); + 2'b01 : $fwrite (fd," 726"); + 2'b10 : $fwrite (fd," 727"); + 2'b11 : $fwrite (fd," 728"); + endcase + 4'he : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 729"); + 2'b01 : $fwrite (fd," 730"); + 2'b10 : $fwrite (fd," 731"); + 2'b11 : $fwrite (fd," 732"); + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 733"); + 2'b01 : $fwrite (fd," 734"); + 2'b10 : $fwrite (fd," 735"); + 2'b11 : $fwrite (fd," 736"); + endcase + endcase + end + endtask + + task ozonef2e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + casez (foo[25:21]) + 5'h00 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 737"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 738"); + end + 5'h01 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 739"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 740"); + end + 5'h02 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 741"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 742"); + end + 5'h03 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 743"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 744"); + end + 5'h04 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 745"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 746"); + end + 5'h05 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 747"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 748"); + end + 5'h06 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 749"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 750"); + end + 5'h07 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 751"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 752"); + end + 5'h08 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 753"); + if (foo[ 6]) + $fwrite (fd," 754"); + else + $fwrite (fd," 755"); + end + 5'h09 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 756"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 757"); + end + 5'h0a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 758"); + ozoneae(foo[17:15], fd); + end + 5'h0b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 759"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 760"); + end + 5'h0c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 761"); + end + 5'h0d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 762"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 763"); + end + 5'h0e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 764"); + ozoneae(foo[17:15], fd); + end + 5'h0f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 765"); + ozoneae(foo[17:15], fd); + end + 5'h10 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 766"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 767"); + end + 5'h11 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 768"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 769"); + end + 5'h18 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 770"); + if (foo[ 6]) + $fwrite (fd," 771"); + else + $fwrite (fd," 772"); + end + 5'h1a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 773"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 774"); + end + 5'h1b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 775"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 776"); + if (foo[ 6]) + $fwrite (fd," 777"); + else + $fwrite (fd," 778"); + $fwrite (fd," 779"); + end + 5'h1c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 780"); + end + 5'h1d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 781"); + if (foo[ 6]) + $fwrite (fd," 782"); + else + $fwrite (fd," 783"); + $fwrite (fd," 784"); + end + 5'h1e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 785"); + if (foo[ 6]) + $fwrite (fd," 786"); + else + $fwrite (fd," 787"); + $fwrite (fd," 788"); + end + 5'h1f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 789"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 790"); + if (foo[ 6]) + $fwrite (fd," 791"); + else + $fwrite (fd," 792"); + $fwrite (fd," 793"); + end + default : + $fwrite (fd," 794"); + endcase + end + endtask + + task ozonef3e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[25:21]) + 5'h00, + 5'h01, + 5'h02: + begin + ozoneae(foo[20:18], fd); + case (foo[22:21]) + 2'h0: $fwrite (fd," 795"); + 2'h1: $fwrite (fd," 796"); + 2'h2: $fwrite (fd," 797"); + endcase + ozoneae(foo[17:15], fd); + $fwrite (fd," 798"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 799"); + end + 5'h08, + 5'h09, + 5'h0d, + 5'h0e, + 5'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 800"); + ozoneae(foo[17:15], fd); + case (foo[23:21]) + 3'h0: $fwrite (fd," 801"); + 3'h1: $fwrite (fd," 802"); + 3'h5: $fwrite (fd," 803"); + 3'h6: $fwrite (fd," 804"); + 3'h7: $fwrite (fd," 805"); + endcase + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0a, + 5'h0b: + begin + ozoneae(foo[17:15], fd); + if (foo[21]) + $fwrite (fd," 806"); + else + $fwrite (fd," 807"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 808"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 809"); + ozoneae(foo[17:15], fd); + end + 5'h10, + 5'h11, + 5'h12, + 5'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 810"); + ozoneae(foo[17:15], fd); + case (foo[22:21]) + 2'h0, + 2'h2: + $fwrite (fd," 811"); + 2'h1, + 2'h3: + $fwrite (fd," 812"); + endcase + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 813"); + ozoneae((foo[20:18]+1), fd); + $fwrite (fd," 814"); + ozoneae((foo[17:15]+1), fd); + case (foo[22:21]) + 2'h0, + 2'h3: + $fwrite (fd," 815"); + 2'h1, + 2'h2: + $fwrite (fd," 816"); + endcase + ozoneae((foo[ 8: 6]+1), fd); + end + 5'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 817"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 818"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 819"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 820"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 821"); + ozoneae(foo[ 8: 6], fd); + end + default : + $fwrite (fd," 822"); + endcase + end + endtask + task ozonef3e_te; + input [ 2:0] te; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (te) + 3'b100 : $fwrite (fd, " 823"); + 3'b101 : $fwrite (fd, " 824"); + 3'b110 : $fwrite (fd, " 825"); + default: $fwrite (fd, " 826"); + endcase + end + endtask + task ozonearm; + input [ 2:0] ate; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ate) + 3'b000 : $fwrite (fd, " 827"); + 3'b001 : $fwrite (fd, " 828"); + 3'b010 : $fwrite (fd, " 829"); + 3'b011 : $fwrite (fd, " 830"); + 3'b100 : $fwrite (fd, " 831"); + 3'b101 : $fwrite (fd, " 832"); + 3'b110 : $fwrite (fd, " 833"); + 3'b111 : $fwrite (fd, " 834"); + endcase + end + endtask + task ozonebmuop; + input [ 4:0] f4; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (f4[ 4:0]) + 5'h00, + 5'h04 : + $fwrite (fd, " 835"); + 5'h01, + 5'h05 : + $fwrite (fd, " 836"); + 5'h02, + 5'h06 : + $fwrite (fd, " 837"); + 5'h03, + 5'h07 : + $fwrite (fd, " 838"); + 5'h08, + 5'h18 : + $fwrite (fd, " 839"); + 5'h09, + 5'h19 : + $fwrite (fd, " 840"); + 5'h0a, + 5'h1a : + $fwrite (fd, " 841"); + 5'h0b : + $fwrite (fd, " 842"); + 5'h1b : + $fwrite (fd, " 843"); + 5'h0c, + 5'h1c : + $fwrite (fd, " 844"); + 5'h0d, + 5'h1d : + $fwrite (fd, " 845"); + 5'h1e : + $fwrite (fd, " 846"); + endcase + end + endtask + task automatic ozonef3; + input [ 31:0] foo; + input [`FD_BITS] fd; + reg nacho; + // verilator no_inline_task + begin : f3_body + nacho = 1'b0; + case (foo[24:21]) + 4'h0: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 847"); + 2'b01 : $fwrite (fd, " 848"); + 2'b10 : $fwrite (fd, " 849"); + 2'b11 : $fwrite (fd, " 850"); + endcase + 4'h1: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 851"); + 2'b01 : $fwrite (fd, " 852"); + 2'b10 : $fwrite (fd, " 853"); + 2'b11 : $fwrite (fd, " 854"); + endcase + 4'h2: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 855"); + 2'b01 : $fwrite (fd, " 856"); + 2'b10 : $fwrite (fd, " 857"); + 2'b11 : $fwrite (fd, " 858"); + endcase + 4'h8, + 4'h9, + 4'hd, + 4'he, + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 859"); + 2'b01 : $fwrite (fd, " 860"); + 2'b10 : $fwrite (fd, " 861"); + 2'b11 : $fwrite (fd, " 862"); + endcase + 4'ha, + 4'hb : + if (foo[25]) + $fwrite (fd, " 863"); + else + $fwrite (fd, " 864"); + 4'hc : + if (foo[26]) + $fwrite (fd, " 865"); + else + $fwrite (fd, " 866"); + default : + begin + $fwrite (fd, " 867"); + nacho = 1'b1; + end + endcase + if (~nacho) + begin + case (foo[24:21]) 4'h8 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 208"); - 2'b01 : $fwrite (fd, " 209"); - 2'b10 : $fwrite (fd, " 210"); - 2'b11 : $fwrite (fd, " 211"); - endcase + $fwrite (fd, " 868"); 4'h9 : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 212"); - 2'b01 : $fwrite (fd, " 213"); - 2'b10 : $fwrite (fd, " 214"); - 2'b11 : $fwrite (fd, " 215"); - endcase - 4'ha : - if (foo[25]) - $fwrite (fd, " 216"); - else - $fwrite (fd, " 217"); - 4'hb : - if (foo[25]) - $fwrite (fd, " 218"); - else - $fwrite (fd, " 219"); - 4'hc : - if (foo[26]) - $fwrite (fd, " 220"); - else - $fwrite (fd, " 221"); - 4'hd : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 222"); - 2'b01 : $fwrite (fd, " 223"); - 2'b10 : $fwrite (fd, " 224"); - 2'b11 : $fwrite (fd, " 225"); - endcase - 4'he : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 226"); - 2'b01 : $fwrite (fd, " 227"); - 2'b10 : $fwrite (fd, " 228"); - 2'b11 : $fwrite (fd, " 229"); - endcase - 4'hf : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 230"); - 2'b01 : $fwrite (fd, " 231"); - 2'b10 : $fwrite (fd, " 232"); - 2'b11 : $fwrite (fd, " 233"); - endcase - endcase - end - endtask - - task ozonef1e; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[27:21]) - 7'h00: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 234"); - $fwrite (fd, " 235"); - end - 7'h01: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 236"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 237"); - $fwrite (fd, " 238"); - end - 7'h02: - $fwrite (fd, " 239"); - 7'h03: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 240"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 241"); - $fwrite (fd, " 242"); - end - 7'h04: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 243"); - $fwrite (fd," 244"); - end - 7'h05: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 245"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 246"); - end - 7'h06: - $fwrite (fd, " 247"); - 7'h07: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 248"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 249"); - end - 7'h08: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 250"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 251"); - end - 7'h09: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 252"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 253"); - end - 7'h0a: - begin - ozoneae(foo[17:15], fd); - $fwrite (fd," 254"); - end - 7'h0b: - begin - ozoneae(foo[17:15], fd); - $fwrite (fd," 255"); - end - 7'h0c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 256"); - end - 7'h0d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 257"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 258"); - end - 7'h0e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 259"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 260"); - end - 7'h0f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 261"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 262"); - end - 7'h10: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 263"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 264"); - $fwrite (fd, " 265"); - $fwrite (fd, " 266"); - end - 7'h11: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 267"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 268"); - $fwrite (fd, " 269"); - $fwrite (fd, " 270"); - end - 7'h12: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 271"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 272"); - $fwrite (fd, " 273"); - $fwrite (fd, " 274"); - end - 7'h13: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 275"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 276"); - $fwrite (fd, " 277"); - $fwrite (fd, " 278"); - end - 7'h14: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 279"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 280"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 281"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 282"); - $fwrite (fd, " 283"); - $fwrite (fd, " 284"); - end - 7'h15: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 285"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 286"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 287"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 288"); - $fwrite (fd, " 289"); - $fwrite (fd, " 290"); - end - 7'h16: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 291"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 292"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 293"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 294"); - $fwrite (fd, " 295"); - $fwrite (fd, " 296"); - end - 7'h17: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 297"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 298"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 299"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 300"); - $fwrite (fd, " 301"); - $fwrite (fd, " 302"); - end - 7'h18: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 303"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 304"); - $fwrite (fd, " 305"); - $fwrite (fd, " 306"); - end - 7'h19: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 307"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 308"); - $fwrite (fd, " 309"); - $fwrite (fd, " 310"); - end - 7'h1a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 311"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 312"); - $fwrite (fd, " 313"); - $fwrite (fd, " 314"); - end - 7'h1b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 315"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 316"); - $fwrite (fd, " 317"); - $fwrite (fd, " 318"); - end - 7'h1c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 319"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 320"); - $fwrite (fd, " 321"); - $fwrite (fd, " 322"); - end - 7'h1d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 323"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 324"); - $fwrite (fd, " 325"); - $fwrite (fd, " 326"); - end - 7'h1e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 327"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 328"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 329"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 330"); - $fwrite (fd, " 331"); - $fwrite (fd, " 332"); - end - 7'h1f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 333"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 334"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 335"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 336"); - $fwrite (fd, " 337"); - $fwrite (fd, " 338"); - end - 7'h20: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 339"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 340"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 341"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 342"); - $fwrite (fd, " 343"); - $fwrite (fd, " 344"); - end - 7'h21: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 345"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 346"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 347"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 348"); - $fwrite (fd, " 349"); - $fwrite (fd, " 350"); - end - 7'h22: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 351"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 352"); - $fwrite (fd, " 353"); - $fwrite (fd, " 354"); - end - 7'h23: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 355"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 356"); - $fwrite (fd, " 357"); - $fwrite (fd, " 358"); - end - 7'h24: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 359"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 360"); - $fwrite (fd, " 361"); - $fwrite (fd, " 362"); - end - 7'h25: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 363"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 364"); - $fwrite (fd, " 365"); - $fwrite (fd, " 366"); - end - 7'h26: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 367"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 368"); - $fwrite (fd, " 369"); - $fwrite (fd, " 370"); - end - 7'h27: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 371"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 372"); - $fwrite (fd, " 373"); - $fwrite (fd, " 374"); - end - 7'h28: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 375"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 376"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 377"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 378"); - $fwrite (fd, " 379"); - $fwrite (fd, " 380"); - end - 7'h29: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 381"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 382"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 383"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 384"); - $fwrite (fd, " 385"); - $fwrite (fd, " 386"); - end - 7'h2a: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 387"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 388"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 389"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 390"); - $fwrite (fd, " 391"); - $fwrite (fd, " 392"); - end - 7'h2b: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 393"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 394"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 395"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 396"); - $fwrite (fd, " 397"); - $fwrite (fd, " 398"); - end - 7'h2c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 399"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 400"); - $fwrite (fd, " 401"); - $fwrite (fd, " 402"); - end - 7'h2d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 403"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 404"); - $fwrite (fd, " 405"); - $fwrite (fd, " 406"); - end - 7'h2e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 407"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 408"); - $fwrite (fd, " 409"); - $fwrite (fd, " 410"); - end - 7'h2f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 411"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 412"); - $fwrite (fd, " 413"); - $fwrite (fd, " 414"); - end - 7'h30: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 415"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 416"); - $fwrite (fd, " 417"); - $fwrite (fd, " 418"); - end - 7'h31: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 419"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 420"); - $fwrite (fd, " 421"); - $fwrite (fd, " 422"); - end - 7'h32: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 423"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 424"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 425"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 426"); - $fwrite (fd, " 427"); - $fwrite (fd, " 428"); - end - 7'h33: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 429"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 430"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 431"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 432"); - $fwrite (fd, " 433"); - $fwrite (fd, " 434"); - end - 7'h34: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 435"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 436"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 437"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 438"); - $fwrite (fd, " 439"); - $fwrite (fd, " 440"); - end - 7'h35: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 441"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 442"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 443"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 444"); - $fwrite (fd, " 445"); - $fwrite (fd, " 446"); - end - 7'h36: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 447"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 448"); - $fwrite (fd, " 449"); - $fwrite (fd, " 450"); - end - 7'h37: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 451"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 452"); - $fwrite (fd, " 453"); - $fwrite (fd, " 454"); - end - 7'h38: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 455"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 456"); - $fwrite (fd, " 457"); - end - 7'h39: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 458"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 459"); - $fwrite (fd, " 460"); - end - 7'h3a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 461"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 462"); - $fwrite (fd, " 463"); - end - 7'h3b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 464"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 465"); - $fwrite (fd, " 466"); - end - 7'h3c: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 467"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 468"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 469"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 470"); - $fwrite (fd, " 471"); - end - 7'h3d: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 472"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 473"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 474"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 475"); - $fwrite (fd, " 476"); - end - 7'h3e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 477"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 478"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 479"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 480"); - $fwrite (fd, " 481"); - end - 7'h3f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 482"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 483"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 484"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 485"); - $fwrite (fd, " 486"); - end - 7'h40: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 487"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 488"); - $fwrite (fd, " 489"); - $fwrite (fd, " 490"); - end - 7'h41: - begin - $fwrite (fd, " 491"); - $fwrite (fd, " 492"); - end - 7'h42: - begin - $fwrite (fd, " 493"); - $fwrite (fd, " 494"); - end - 7'h43: - begin - $fwrite (fd, " 495"); - $fwrite (fd, " 496"); - end - 7'h44: - begin - $fwrite (fd, " 497"); - $fwrite (fd, " 498"); - end - 7'h45: - $fwrite (fd, " 499"); - 7'h46: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 500"); - $fwrite (fd, " 501"); - $fwrite (fd, " 502"); - end - 7'h47: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 503"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 504"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 505"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 506"); - $fwrite (fd, " 507"); - $fwrite (fd, " 508"); - end - 7'h48: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 509"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 510"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 511"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 512"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 513"); - end - 7'h49: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 514"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 515"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 516"); - end - 7'h4a: - $fwrite (fd," 517"); - 7'h4b: - $fwrite (fd, " 518"); - 7'h4c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 519"); - $fwrite (fd, " 520"); - $fwrite (fd, " 521"); - end - 7'h4d: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 522"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 523"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 524"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 525"); - $fwrite (fd, " 526"); - $fwrite (fd, " 527"); - end - 7'h4e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 528"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 529"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 530"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 531"); - end - 7'h4f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 532"); - end - 7'h50: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 533"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 534"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 535"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 536"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 537"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 538"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 539"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 540"); - end - 7'h51: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 541"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 542"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 543"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 544"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 545"); - end - 7'h52: - $fwrite (fd, " 546"); - 7'h53: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 547"); - end - 7'h54: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 548"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 549"); - end - 7'h55: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 550"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 551"); - end - 7'h56: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 552"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 553"); - $fwrite (fd, " 554"); - end - 7'h57: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 555"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 556"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 557"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 558"); - end - 7'h58: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 559"); - end - 7'h59: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 560"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 561"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 562"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 563"); - end - 7'h5a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 564"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 565"); - end - 7'h5b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 566"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 567"); - end - 7'h5c: - begin - $fwrite (fd," 568"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 569"); - $fwrite (fd," 570"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 571"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 572"); - ozoneaee(foo[17:15], fd); - $fwrite (fd, " 573"); - end - 7'h5d: - begin - $fwrite (fd," 574"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 575"); - $fwrite (fd," 576"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 577"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 578"); - ozoneaee(foo[17:15], fd); - $fwrite (fd, " 579"); - end - 7'h5e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 580"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 581"); - end - 7'h5f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 582"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 583"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 584"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 585"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 586"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 587"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 588"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 589"); - end - 7'h60: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 590"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 591"); - end - 7'h61: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 592"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 593"); - end - 7'h62: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 594"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 595"); - end - 7'h63: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 596"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 597"); - end - 7'h64: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 598"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 599"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 600"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 601"); - end - 7'h65: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 602"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 603"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 604"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 605"); - end - 7'h66: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 606"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 607"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 608"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 609"); - end - 7'h67: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 610"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 611"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 612"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 613"); - end - 7'h68: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 614"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 615"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 616"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 617"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 618"); - ozoneape(foo[17:15], fd); - end - 7'h69: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 619"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 620"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 621"); - end - 7'h6a: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 622"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 623"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 624"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 625"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 626"); - ozoneae(foo[17:15], fd); - end - 7'h6b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 627"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 628"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 629"); - end - 7'h6c: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 630"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 631"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 632"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 633"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 634"); - ozoneae(foo[17:15], fd); - end - 7'h6d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 635"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 636"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 637"); - end - 7'h6e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 638"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 639"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 640"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 641"); - end - 7'h6f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 642"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 643"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 644"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 645"); - end - 7'h70: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 646"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 647"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 648"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 649"); - end - 7'h71: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 650"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 651"); - end - 7'h72: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 652"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 653"); - end - 7'h73: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 654"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 655"); - ozoneae(foo[17:15], fd); - end - 7'h74: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 656"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 657"); - ozoneae(foo[17:15], fd); - end - 7'h75: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 658"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 659"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 660"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 661"); - $fwrite (fd, " 662"); - $fwrite (fd, " 663"); - end - 7'h76: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 664"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 665"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 666"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 667"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 668"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 669"); - end - 7'h77: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 670"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 671"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 672"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 673"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 674"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 675"); - end - 7'h78, - 7'h79, - 7'h7a, - 7'h7b, - 7'h7c, - 7'h7d, - 7'h7e, - 7'h7f: - $fwrite (fd," 676"); - endcase - end - endtask - - task ozonef2; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[24:21]) - 4'h0 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 677"); - 2'b01 : $fwrite (fd," 678"); - 2'b10 : $fwrite (fd," 679"); - 2'b11 : $fwrite (fd," 680"); - endcase - 4'h1 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 681"); - 2'b01 : $fwrite (fd," 682"); - 2'b10 : $fwrite (fd," 683"); - 2'b11 : $fwrite (fd," 684"); - endcase - 4'h2 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 685"); - 2'b01 : $fwrite (fd," 686"); - 2'b10 : $fwrite (fd," 687"); - 2'b11 : $fwrite (fd," 688"); - endcase - 4'h3 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 689"); - 2'b01 : $fwrite (fd," 690"); - 2'b10 : $fwrite (fd," 691"); - 2'b11 : $fwrite (fd," 692"); - endcase - 4'h4 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 693"); - 2'b01 : $fwrite (fd," 694"); - 2'b10 : $fwrite (fd," 695"); - 2'b11 : $fwrite (fd," 696"); - endcase - 4'h5 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 697"); - 2'b01 : $fwrite (fd," 698"); - 2'b10 : $fwrite (fd," 699"); - 2'b11 : $fwrite (fd," 700"); - endcase - 4'h6 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 701"); - 2'b01 : $fwrite (fd," 702"); - 2'b10 : $fwrite (fd," 703"); - 2'b11 : $fwrite (fd," 704"); - endcase - 4'h7 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 705"); - 2'b01 : $fwrite (fd," 706"); - 2'b10 : $fwrite (fd," 707"); - 2'b11 : $fwrite (fd," 708"); - endcase - 4'h8 : - if (foo[26]) - $fwrite (fd," 709"); - else - $fwrite (fd," 710"); - 4'h9 : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 711"); - 2'b01 : $fwrite (fd," 712"); - 2'b10 : $fwrite (fd," 713"); - 2'b11 : $fwrite (fd," 714"); - endcase - 4'ha : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 715"); - 2'b01 : $fwrite (fd," 716"); - 2'b10 : $fwrite (fd," 717"); - 2'b11 : $fwrite (fd," 718"); - endcase - 4'hb : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 719"); - 2'b01 : $fwrite (fd," 720"); - 2'b10 : $fwrite (fd," 721"); - 2'b11 : $fwrite (fd," 722"); - endcase - 4'hc : - if (foo[26]) - $fwrite (fd," 723"); - else - $fwrite (fd," 724"); - 4'hd : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 725"); - 2'b01 : $fwrite (fd," 726"); - 2'b10 : $fwrite (fd," 727"); - 2'b11 : $fwrite (fd," 728"); - endcase - 4'he : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 729"); - 2'b01 : $fwrite (fd," 730"); - 2'b10 : $fwrite (fd," 731"); - 2'b11 : $fwrite (fd," 732"); - endcase - 4'hf : - case (foo[26:25]) - 2'b00 : $fwrite (fd," 733"); - 2'b01 : $fwrite (fd," 734"); - 2'b10 : $fwrite (fd," 735"); - 2'b11 : $fwrite (fd," 736"); - endcase - endcase - end - endtask - - task ozonef2e; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - casez (foo[25:21]) - 5'h00 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 737"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 738"); - end - 5'h01 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 739"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 740"); - end - 5'h02 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 741"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 742"); - end - 5'h03 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 743"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 744"); - end - 5'h04 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 745"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 746"); - end - 5'h05 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 747"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 748"); - end - 5'h06 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 749"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 750"); - end - 5'h07 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 751"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 752"); - end - 5'h08 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 753"); - if (foo[ 6]) - $fwrite (fd," 754"); - else - $fwrite (fd," 755"); - end - 5'h09 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 756"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 757"); - end - 5'h0a : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 758"); - ozoneae(foo[17:15], fd); - end - 5'h0b : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 759"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 760"); - end - 5'h0c : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 761"); - end - 5'h0d : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 762"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 763"); - end - 5'h0e : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 764"); - ozoneae(foo[17:15], fd); - end - 5'h0f : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 765"); - ozoneae(foo[17:15], fd); - end - 5'h10 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 766"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 767"); - end - 5'h11 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 768"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 769"); - end - 5'h18 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 770"); - if (foo[ 6]) - $fwrite (fd," 771"); - else - $fwrite (fd," 772"); - end - 5'h1a : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 773"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 774"); - end - 5'h1b : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 775"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 776"); - if (foo[ 6]) - $fwrite (fd," 777"); - else - $fwrite (fd," 778"); - $fwrite (fd," 779"); - end - 5'h1c : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 780"); - end - 5'h1d : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 781"); - if (foo[ 6]) - $fwrite (fd," 782"); - else - $fwrite (fd," 783"); - $fwrite (fd," 784"); - end - 5'h1e : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 785"); - if (foo[ 6]) - $fwrite (fd," 786"); - else - $fwrite (fd," 787"); - $fwrite (fd," 788"); - end - 5'h1f : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 789"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 790"); - if (foo[ 6]) - $fwrite (fd," 791"); - else - $fwrite (fd," 792"); - $fwrite (fd," 793"); - end - default : - $fwrite (fd," 794"); - endcase - end - endtask - - task ozonef3e; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[25:21]) - 5'h00, - 5'h01, - 5'h02: - begin - ozoneae(foo[20:18], fd); - case (foo[22:21]) - 2'h0: $fwrite (fd," 795"); - 2'h1: $fwrite (fd," 796"); - 2'h2: $fwrite (fd," 797"); - endcase - ozoneae(foo[17:15], fd); - $fwrite (fd," 798"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - $fwrite (fd," 799"); - end - 5'h08, - 5'h09, - 5'h0d, - 5'h0e, - 5'h0f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 800"); - ozoneae(foo[17:15], fd); - case (foo[23:21]) - 3'h0: $fwrite (fd," 801"); - 3'h1: $fwrite (fd," 802"); - 3'h5: $fwrite (fd," 803"); - 3'h6: $fwrite (fd," 804"); - 3'h7: $fwrite (fd," 805"); - endcase - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - end - 5'h0a, - 5'h0b: - begin - ozoneae(foo[17:15], fd); - if (foo[21]) - $fwrite (fd," 806"); - else - $fwrite (fd," 807"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - end - 5'h0c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 808"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - $fwrite (fd," 809"); - ozoneae(foo[17:15], fd); - end - 5'h10, - 5'h11, - 5'h12, - 5'h13: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 810"); - ozoneae(foo[17:15], fd); - case (foo[22:21]) - 2'h0, - 2'h2: - $fwrite (fd," 811"); - 2'h1, - 2'h3: - $fwrite (fd," 812"); - endcase - ozoneae(foo[ 8: 6], fd); - $fwrite (fd," 813"); - ozoneae((foo[20:18]+1), fd); - $fwrite (fd," 814"); - ozoneae((foo[17:15]+1), fd); - case (foo[22:21]) - 2'h0, - 2'h3: - $fwrite (fd," 815"); - 2'h1, - 2'h2: - $fwrite (fd," 816"); - endcase - ozoneae((foo[ 8: 6]+1), fd); - end - 5'h18: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 817"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 818"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd," 819"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 820"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 821"); - ozoneae(foo[ 8: 6], fd); - end - default : - $fwrite (fd," 822"); - endcase - end - endtask - task ozonef3e_te; - input [ 2:0] te; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (te) - 3'b100 : $fwrite (fd, " 823"); - 3'b101 : $fwrite (fd, " 824"); - 3'b110 : $fwrite (fd, " 825"); - default: $fwrite (fd, " 826"); - endcase - end - endtask - task ozonearm; - input [ 2:0] ate; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (ate) - 3'b000 : $fwrite (fd, " 827"); - 3'b001 : $fwrite (fd, " 828"); - 3'b010 : $fwrite (fd, " 829"); - 3'b011 : $fwrite (fd, " 830"); - 3'b100 : $fwrite (fd, " 831"); - 3'b101 : $fwrite (fd, " 832"); - 3'b110 : $fwrite (fd, " 833"); - 3'b111 : $fwrite (fd, " 834"); - endcase - end - endtask - task ozonebmuop; - input [ 4:0] f4; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (f4[ 4:0]) - 5'h00, - 5'h04 : - $fwrite (fd, " 835"); - 5'h01, - 5'h05 : - $fwrite (fd, " 836"); - 5'h02, - 5'h06 : - $fwrite (fd, " 837"); - 5'h03, - 5'h07 : - $fwrite (fd, " 838"); - 5'h08, - 5'h18 : - $fwrite (fd, " 839"); - 5'h09, - 5'h19 : - $fwrite (fd, " 840"); - 5'h0a, - 5'h1a : - $fwrite (fd, " 841"); - 5'h0b : - $fwrite (fd, " 842"); - 5'h1b : - $fwrite (fd, " 843"); - 5'h0c, - 5'h1c : - $fwrite (fd, " 844"); - 5'h0d, - 5'h1d : - $fwrite (fd, " 845"); - 5'h1e : - $fwrite (fd, " 846"); - endcase - end - endtask - task automatic ozonef3; - input [ 31:0] foo; - input [`FD_BITS] fd; - reg nacho; - // verilator no_inline_task - begin : f3_body - nacho = 1'b0; - case (foo[24:21]) - 4'h0: - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 847"); - 2'b01 : $fwrite (fd, " 848"); - 2'b10 : $fwrite (fd, " 849"); - 2'b11 : $fwrite (fd, " 850"); - endcase - 4'h1: - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 851"); - 2'b01 : $fwrite (fd, " 852"); - 2'b10 : $fwrite (fd, " 853"); - 2'b11 : $fwrite (fd, " 854"); - endcase - 4'h2: - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 855"); - 2'b01 : $fwrite (fd, " 856"); - 2'b10 : $fwrite (fd, " 857"); - 2'b11 : $fwrite (fd, " 858"); - endcase - 4'h8, - 4'h9, - 4'hd, - 4'he, - 4'hf : - case (foo[26:25]) - 2'b00 : $fwrite (fd, " 859"); - 2'b01 : $fwrite (fd, " 860"); - 2'b10 : $fwrite (fd, " 861"); - 2'b11 : $fwrite (fd, " 862"); - endcase + $fwrite (fd, " 869"); 4'ha, - 4'hb : - if (foo[25]) - $fwrite (fd, " 863"); - else - $fwrite (fd, " 864"); - 4'hc : - if (foo[26]) - $fwrite (fd, " 865"); - else - $fwrite (fd, " 866"); - default : - begin - $fwrite (fd, " 867"); - nacho = 1'b1; - end - endcase - if (~nacho) - begin - case (foo[24:21]) - 4'h8 : - $fwrite (fd, " 868"); - 4'h9 : - $fwrite (fd, " 869"); - 4'ha, - 4'he : - $fwrite (fd, " 870"); - 4'hb, - 4'hf : - $fwrite (fd, " 871"); - 4'hd : - $fwrite (fd, " 872"); - endcase - if (foo[20]) - case (foo[18:16]) - 3'b000 : $fwrite (fd, " 873"); - 3'b100 : $fwrite (fd, " 874"); - default: $fwrite (fd, " 875"); - endcase - else - ozoneae(foo[18:16], fd); - if (foo[24:21] === 4'hc) - if (foo[25]) - $fwrite (fd, " 876"); - else - $fwrite (fd, " 877"); - case (foo[24:21]) - 4'h0, - 4'h1, - 4'h2: - $fwrite (fd, " 878"); - endcase - end - end - endtask - task ozonerx; - input [ 31:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[19:18]) - 2'h0 : $fwrite (fd, " 879"); - 2'h1 : $fwrite (fd, " 880"); - 2'h2 : $fwrite (fd, " 881"); - 2'h3 : $fwrite (fd, " 882"); - endcase - case (foo[17:16]) - 2'h1 : $fwrite (fd, " 883"); - 2'h2 : $fwrite (fd, " 884"); - 2'h3 : $fwrite (fd, " 885"); - endcase - end - endtask - task ozonerme; - input [ 2:0] rme; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (rme) - 3'h0 : $fwrite (fd, " 886"); - 3'h1 : $fwrite (fd, " 887"); - 3'h2 : $fwrite (fd, " 888"); - 3'h3 : $fwrite (fd, " 889"); - 3'h4 : $fwrite (fd, " 890"); - 3'h5 : $fwrite (fd, " 891"); - 3'h6 : $fwrite (fd, " 892"); - 3'h7 : $fwrite (fd, " 893"); - endcase - end - endtask - task ozoneye; - input [5:0] ye; - input l; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - $fwrite (fd, " 894"); - ozonerme(ye[5:3], fd); - case ({ye[ 2:0], l}) - 4'h2, - 4'ha: $fwrite (fd, " 895"); - 4'h4, - 4'hb: $fwrite (fd, " 896"); - 4'h6, - 4'he: $fwrite (fd, " 897"); - 4'h8, - 4'hc: $fwrite (fd, " 898"); - endcase - end - endtask - task ozonef1e_ye; - input [5:0] ye; - input l; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - $fwrite (fd, " 899"); - ozonerme(ye[5:3], fd); - ozonef1e_inc_dec(ye[5:0], l , fd); - end - endtask - task ozonef1e_h; - input [ 2:0] e; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - if (e[ 2:0] <= 3'h4) - $fwrite (fd, " 900"); - end - endtask - task ozonef1e_inc_dec; - input [5:0] ye; - input l; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case ({ye[ 2:0], l}) - 4'h2, - 4'h3, - 4'ha: $fwrite (fd, " 901"); - 4'h4, - 4'h5, - 4'hb: $fwrite (fd, " 902"); - 4'h6, - 4'h7, - 4'he: $fwrite (fd, " 903"); - 4'h8, - 4'h9, - 4'hc: $fwrite (fd, " 904"); - 4'hf: $fwrite (fd, " 905"); - endcase - end - endtask - task ozonef1e_hl; - input [ 2:0] e; - input l; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case ({e[ 2:0], l}) + 4'he : + $fwrite (fd, " 870"); + 4'hb, + 4'hf : + $fwrite (fd, " 871"); + 4'hd : + $fwrite (fd, " 872"); + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000 : $fwrite (fd, " 873"); + 3'b100 : $fwrite (fd, " 874"); + default: $fwrite (fd, " 875"); + endcase + else + ozoneae(foo[18:16], fd); + if (foo[24:21] === 4'hc) + if (foo[25]) + $fwrite (fd, " 876"); + else + $fwrite (fd, " 877"); + case (foo[24:21]) 4'h0, - 4'h2, - 4'h4, - 4'h6, - 4'h8: $fwrite (fd, " 906"); - 4'h1, - 4'h3, - 4'h5, - 4'h7, - 4'h9: $fwrite (fd, " 907"); - endcase - end - endtask - task ozonexe; - input [ 3:0] xe; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (xe[3]) - 1'b0 : $fwrite (fd, " 908"); - 1'b1 : $fwrite (fd, " 909"); - endcase - case (xe[ 2:0]) - 3'h1, - 3'h5: $fwrite (fd, " 910"); - 3'h2, - 3'h6: $fwrite (fd, " 911"); - 3'h3, - 3'h7: $fwrite (fd, " 912"); - 3'h4: $fwrite (fd, " 913"); - endcase - end - endtask - task ozonerp; - input [ 2:0] rp; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (rp) - 3'h0 : $fwrite (fd, " 914"); - 3'h1 : $fwrite (fd, " 915"); - 3'h2 : $fwrite (fd, " 916"); - 3'h3 : $fwrite (fd, " 917"); - 3'h4 : $fwrite (fd, " 918"); - 3'h5 : $fwrite (fd, " 919"); - 3'h6 : $fwrite (fd, " 920"); - 3'h7 : $fwrite (fd, " 921"); - endcase - end - endtask - task ozonery; - input [ 3:0] ry; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (ry) - 4'h0 : $fwrite (fd, " 922"); - 4'h1 : $fwrite (fd, " 923"); - 4'h2 : $fwrite (fd, " 924"); - 4'h3 : $fwrite (fd, " 925"); - 4'h4 : $fwrite (fd, " 926"); - 4'h5 : $fwrite (fd, " 927"); - 4'h6 : $fwrite (fd, " 928"); - 4'h7 : $fwrite (fd, " 929"); - 4'h8 : $fwrite (fd, " 930"); - 4'h9 : $fwrite (fd, " 931"); - 4'ha : $fwrite (fd, " 932"); - 4'hb : $fwrite (fd, " 933"); - 4'hc : $fwrite (fd, " 934"); - 4'hd : $fwrite (fd, " 935"); - 4'he : $fwrite (fd, " 936"); - 4'hf : $fwrite (fd, " 937"); - endcase - end - endtask - task ozonearx; - input [ 15:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[1:0]) - 2'h0 : $fwrite (fd, " 938"); - 2'h1 : $fwrite (fd, " 939"); - 2'h2 : $fwrite (fd, " 940"); - 2'h3 : $fwrite (fd, " 941"); - endcase - end - endtask - task ozonef3f4imop; - input [ 4:0] f3f4iml; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - casez (f3f4iml) - 5'b000??: $fwrite (fd, " 942"); - 5'b001??: $fwrite (fd, " 943"); - 5'b?10??: $fwrite (fd, " 944"); - 5'b0110?: $fwrite (fd, " 945"); - 5'b01110: $fwrite (fd, " 946"); - 5'b01111: $fwrite (fd, " 947"); - 5'b10???: $fwrite (fd, " 948"); - 5'b11100: $fwrite (fd, " 949"); - 5'b11101: $fwrite (fd, " 950"); - 5'b11110: $fwrite (fd, " 951"); - 5'b11111: $fwrite (fd, " 952"); - endcase - end - endtask - task ozonecon; - input [ 4:0] con; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (con) - 5'h00 : $fwrite (fd, " 953"); - 5'h01 : $fwrite (fd, " 954"); - 5'h02 : $fwrite (fd, " 955"); - 5'h03 : $fwrite (fd, " 956"); - 5'h04 : $fwrite (fd, " 957"); - 5'h05 : $fwrite (fd, " 958"); - 5'h06 : $fwrite (fd, " 959"); - 5'h07 : $fwrite (fd, " 960"); - 5'h08 : $fwrite (fd, " 961"); - 5'h09 : $fwrite (fd, " 962"); - 5'h0a : $fwrite (fd, " 963"); - 5'h0b : $fwrite (fd, " 964"); - 5'h0c : $fwrite (fd, " 965"); - 5'h0d : $fwrite (fd, " 966"); - 5'h0e : $fwrite (fd, " 967"); - 5'h0f : $fwrite (fd, " 968"); - 5'h10 : $fwrite (fd, " 969"); - 5'h11 : $fwrite (fd, " 970"); - 5'h12 : $fwrite (fd, " 971"); - 5'h13 : $fwrite (fd, " 972"); - 5'h14 : $fwrite (fd, " 973"); - 5'h15 : $fwrite (fd, " 974"); - 5'h16 : $fwrite (fd, " 975"); - 5'h17 : $fwrite (fd, " 976"); - 5'h18 : $fwrite (fd, " 977"); - 5'h19 : $fwrite (fd, " 978"); - 5'h1a : $fwrite (fd, " 979"); - 5'h1b : $fwrite (fd, " 980"); - 5'h1c : $fwrite (fd, " 981"); - 5'h1d : $fwrite (fd, " 982"); - 5'h1e : $fwrite (fd, " 983"); - 5'h1f : $fwrite (fd, " 984"); - endcase - end - endtask - task ozonedr; - input [ 15:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[ 9: 6]) - 4'h0 : $fwrite (fd, " 985"); - 4'h1 : $fwrite (fd, " 986"); - 4'h2 : $fwrite (fd, " 987"); - 4'h3 : $fwrite (fd, " 988"); - 4'h4 : $fwrite (fd, " 989"); - 4'h5 : $fwrite (fd, " 990"); - 4'h6 : $fwrite (fd, " 991"); - 4'h7 : $fwrite (fd, " 992"); - 4'h8 : $fwrite (fd, " 993"); - 4'h9 : $fwrite (fd, " 994"); - 4'ha : $fwrite (fd, " 995"); - 4'hb : $fwrite (fd, " 996"); - 4'hc : $fwrite (fd, " 997"); - 4'hd : $fwrite (fd, " 998"); - 4'he : $fwrite (fd, " 999"); - 4'hf : $fwrite (fd, " 1000"); - endcase - end - endtask - task ozoneshift; - input [ 15:0] foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo[ 4: 3]) - 2'h0 : $fwrite (fd, " 1001"); - 2'h1 : $fwrite (fd, " 1002"); - 2'h2 : $fwrite (fd, " 1003"); - 2'h3 : $fwrite (fd, " 1004"); - endcase - end - endtask - task ozoneacc; - input foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo) - 2'h0 : $fwrite (fd, " 1005"); - 2'h1 : $fwrite (fd, " 1006"); - endcase - end - endtask - task ozonehl; - input foo; - input [`FD_BITS] fd; - // verilator no_inline_task - begin - case (foo) - 2'h0 : $fwrite (fd, " 1007"); - 2'h1 : $fwrite (fd, " 1008"); - endcase - end - endtask - task dude; - input [`FD_BITS] fd; - // verilator no_inline_task - $fwrite(fd," dude"); - endtask + 4'h1, + 4'h2: + $fwrite (fd, " 878"); + endcase + end + end + endtask + task ozonerx; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[19:18]) + 2'h0 : $fwrite (fd, " 879"); + 2'h1 : $fwrite (fd, " 880"); + 2'h2 : $fwrite (fd, " 881"); + 2'h3 : $fwrite (fd, " 882"); + endcase + case (foo[17:16]) + 2'h1 : $fwrite (fd, " 883"); + 2'h2 : $fwrite (fd, " 884"); + 2'h3 : $fwrite (fd, " 885"); + endcase + end + endtask + task ozonerme; + input [ 2:0] rme; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rme) + 3'h0 : $fwrite (fd, " 886"); + 3'h1 : $fwrite (fd, " 887"); + 3'h2 : $fwrite (fd, " 888"); + 3'h3 : $fwrite (fd, " 889"); + 3'h4 : $fwrite (fd, " 890"); + 3'h5 : $fwrite (fd, " 891"); + 3'h6 : $fwrite (fd, " 892"); + 3'h7 : $fwrite (fd, " 893"); + endcase + end + endtask + task ozoneye; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + $fwrite (fd, " 894"); + ozonerme(ye[5:3], fd); + case ({ye[ 2:0], l}) + 4'h2, + 4'ha: $fwrite (fd, " 895"); + 4'h4, + 4'hb: $fwrite (fd, " 896"); + 4'h6, + 4'he: $fwrite (fd, " 897"); + 4'h8, + 4'hc: $fwrite (fd, " 898"); + endcase + end + endtask + task ozonef1e_ye; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + $fwrite (fd, " 899"); + ozonerme(ye[5:3], fd); + ozonef1e_inc_dec(ye[5:0], l , fd); + end + endtask + task ozonef1e_h; + input [ 2:0] e; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + if (e[ 2:0] <= 3'h4) + $fwrite (fd, " 900"); + end + endtask + task ozonef1e_inc_dec; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case ({ye[ 2:0], l}) + 4'h2, + 4'h3, + 4'ha: $fwrite (fd, " 901"); + 4'h4, + 4'h5, + 4'hb: $fwrite (fd, " 902"); + 4'h6, + 4'h7, + 4'he: $fwrite (fd, " 903"); + 4'h8, + 4'h9, + 4'hc: $fwrite (fd, " 904"); + 4'hf: $fwrite (fd, " 905"); + endcase + end + endtask + task ozonef1e_hl; + input [ 2:0] e; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case ({e[ 2:0], l}) + 4'h0, + 4'h2, + 4'h4, + 4'h6, + 4'h8: $fwrite (fd, " 906"); + 4'h1, + 4'h3, + 4'h5, + 4'h7, + 4'h9: $fwrite (fd, " 907"); + endcase + end + endtask + task ozonexe; + input [ 3:0] xe; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (xe[3]) + 1'b0 : $fwrite (fd, " 908"); + 1'b1 : $fwrite (fd, " 909"); + endcase + case (xe[ 2:0]) + 3'h1, + 3'h5: $fwrite (fd, " 910"); + 3'h2, + 3'h6: $fwrite (fd, " 911"); + 3'h3, + 3'h7: $fwrite (fd, " 912"); + 3'h4: $fwrite (fd, " 913"); + endcase + end + endtask + task ozonerp; + input [ 2:0] rp; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rp) + 3'h0 : $fwrite (fd, " 914"); + 3'h1 : $fwrite (fd, " 915"); + 3'h2 : $fwrite (fd, " 916"); + 3'h3 : $fwrite (fd, " 917"); + 3'h4 : $fwrite (fd, " 918"); + 3'h5 : $fwrite (fd, " 919"); + 3'h6 : $fwrite (fd, " 920"); + 3'h7 : $fwrite (fd, " 921"); + endcase + end + endtask + task ozonery; + input [ 3:0] ry; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ry) + 4'h0 : $fwrite (fd, " 922"); + 4'h1 : $fwrite (fd, " 923"); + 4'h2 : $fwrite (fd, " 924"); + 4'h3 : $fwrite (fd, " 925"); + 4'h4 : $fwrite (fd, " 926"); + 4'h5 : $fwrite (fd, " 927"); + 4'h6 : $fwrite (fd, " 928"); + 4'h7 : $fwrite (fd, " 929"); + 4'h8 : $fwrite (fd, " 930"); + 4'h9 : $fwrite (fd, " 931"); + 4'ha : $fwrite (fd, " 932"); + 4'hb : $fwrite (fd, " 933"); + 4'hc : $fwrite (fd, " 934"); + 4'hd : $fwrite (fd, " 935"); + 4'he : $fwrite (fd, " 936"); + 4'hf : $fwrite (fd, " 937"); + endcase + end + endtask + task ozonearx; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[1:0]) + 2'h0 : $fwrite (fd, " 938"); + 2'h1 : $fwrite (fd, " 939"); + 2'h2 : $fwrite (fd, " 940"); + 2'h3 : $fwrite (fd, " 941"); + endcase + end + endtask + task ozonef3f4imop; + input [ 4:0] f3f4iml; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + casez (f3f4iml) + 5'b000??: $fwrite (fd, " 942"); + 5'b001??: $fwrite (fd, " 943"); + 5'b?10??: $fwrite (fd, " 944"); + 5'b0110?: $fwrite (fd, " 945"); + 5'b01110: $fwrite (fd, " 946"); + 5'b01111: $fwrite (fd, " 947"); + 5'b10???: $fwrite (fd, " 948"); + 5'b11100: $fwrite (fd, " 949"); + 5'b11101: $fwrite (fd, " 950"); + 5'b11110: $fwrite (fd, " 951"); + 5'b11111: $fwrite (fd, " 952"); + endcase + end + endtask + task ozonecon; + input [ 4:0] con; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (con) + 5'h00 : $fwrite (fd, " 953"); + 5'h01 : $fwrite (fd, " 954"); + 5'h02 : $fwrite (fd, " 955"); + 5'h03 : $fwrite (fd, " 956"); + 5'h04 : $fwrite (fd, " 957"); + 5'h05 : $fwrite (fd, " 958"); + 5'h06 : $fwrite (fd, " 959"); + 5'h07 : $fwrite (fd, " 960"); + 5'h08 : $fwrite (fd, " 961"); + 5'h09 : $fwrite (fd, " 962"); + 5'h0a : $fwrite (fd, " 963"); + 5'h0b : $fwrite (fd, " 964"); + 5'h0c : $fwrite (fd, " 965"); + 5'h0d : $fwrite (fd, " 966"); + 5'h0e : $fwrite (fd, " 967"); + 5'h0f : $fwrite (fd, " 968"); + 5'h10 : $fwrite (fd, " 969"); + 5'h11 : $fwrite (fd, " 970"); + 5'h12 : $fwrite (fd, " 971"); + 5'h13 : $fwrite (fd, " 972"); + 5'h14 : $fwrite (fd, " 973"); + 5'h15 : $fwrite (fd, " 974"); + 5'h16 : $fwrite (fd, " 975"); + 5'h17 : $fwrite (fd, " 976"); + 5'h18 : $fwrite (fd, " 977"); + 5'h19 : $fwrite (fd, " 978"); + 5'h1a : $fwrite (fd, " 979"); + 5'h1b : $fwrite (fd, " 980"); + 5'h1c : $fwrite (fd, " 981"); + 5'h1d : $fwrite (fd, " 982"); + 5'h1e : $fwrite (fd, " 983"); + 5'h1f : $fwrite (fd, " 984"); + endcase + end + endtask + task ozonedr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[ 9: 6]) + 4'h0 : $fwrite (fd, " 985"); + 4'h1 : $fwrite (fd, " 986"); + 4'h2 : $fwrite (fd, " 987"); + 4'h3 : $fwrite (fd, " 988"); + 4'h4 : $fwrite (fd, " 989"); + 4'h5 : $fwrite (fd, " 990"); + 4'h6 : $fwrite (fd, " 991"); + 4'h7 : $fwrite (fd, " 992"); + 4'h8 : $fwrite (fd, " 993"); + 4'h9 : $fwrite (fd, " 994"); + 4'ha : $fwrite (fd, " 995"); + 4'hb : $fwrite (fd, " 996"); + 4'hc : $fwrite (fd, " 997"); + 4'hd : $fwrite (fd, " 998"); + 4'he : $fwrite (fd, " 999"); + 4'hf : $fwrite (fd, " 1000"); + endcase + end + endtask + task ozoneshift; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[ 4: 3]) + 2'h0 : $fwrite (fd, " 1001"); + 2'h1 : $fwrite (fd, " 1002"); + 2'h2 : $fwrite (fd, " 1003"); + 2'h3 : $fwrite (fd, " 1004"); + endcase + end + endtask + task ozoneacc; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : $fwrite (fd, " 1005"); + 2'h1 : $fwrite (fd, " 1006"); + endcase + end + endtask + task ozonehl; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : $fwrite (fd, " 1007"); + 2'h1 : $fwrite (fd, " 1008"); + endcase + end + endtask + task dude; + input [`FD_BITS] fd; + // verilator no_inline_task + $fwrite(fd," dude"); + endtask - task automatic big_case; - input [ `FD_BITS] fd; - input [ 31:0] foo; - // verilator no_inline_task - begin - $fwrite(fd," 1009"); - if (&foo === 1'bx) - $fwrite(fd, " 1010"); - else - casez ( {foo[31:26], foo[19:15], foo[5:0]} ) - 17'b00_111?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1011"); - ozoneacc(~foo[26], fd); - ozonehl(foo[20], fd); - $fwrite (fd, " 1012"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1013"); - end - 17'b01_001?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1014"); - ozonerx(foo, fd); - $fwrite (fd, " 1015"); - $fwrite (fd, " 1016:%x", foo[20]); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1017"); - end - 17'b10_100?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1018"); - ozonerx(foo, fd); - $fwrite (fd, " 1019"); - $fwrite (fd, " 1020"); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1021"); - end - 17'b10_101?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1022"); - if (foo[20]) + task automatic big_case; + input [ `FD_BITS] fd; + input [ 31:0] foo; + // verilator no_inline_task + begin + $fwrite(fd," 1009"); + if (&foo === 1'bx) + $fwrite(fd, " 1010"); + else + casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + 17'b00_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1011"); + ozoneacc(~foo[26], fd); + ozonehl(foo[20], fd); + $fwrite (fd, " 1012"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1013"); + end + 17'b01_001?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1014"); + ozonerx(foo, fd); + $fwrite (fd, " 1015"); + $fwrite (fd, " 1016:%x", foo[20]); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1017"); + end + 17'b10_100?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1018"); + ozonerx(foo, fd); + $fwrite (fd, " 1019"); + $fwrite (fd, " 1020"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1021"); + end + 17'b10_101?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1022"); + if (foo[20]) + begin + $fwrite (fd, " 1023"); + ozoneacc(foo[18], fd); + $fwrite (fd, " 1024"); + $fwrite (fd, " 1025"); + if (foo[19]) + $fwrite (fd, " 1026"); + else + $fwrite (fd, " 1027"); + end + else + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1028"); + end + 17'b10_110?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1029"); + $fwrite (fd, " 1030"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1031"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1032"); + end + 17'b10_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1033"); + $fwrite (fd, " 1034"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1035"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1036"); + end + 17'b11_001?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1037"); + ozonerx(foo, fd); + $fwrite (fd, " 1038"); + $fwrite (fd, " 1039"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1040"); + end + 17'b11_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1041"); + $fwrite (fd, " 1042"); + ozonerx(foo, fd); + $fwrite (fd, " 1043"); + if (foo[20]) + $fwrite (fd, " 1044"); + else + $fwrite (fd, " 1045"); + dude(fd); + $fwrite (fd, " 1046"); + end + 17'b00_10??_?_????_?1_1111 : + casez (foo[11: 5]) + 7'b??_0_010_0: + begin + $fwrite (fd, " 1047"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1048"); + ozonef1e(foo, fd); + dude(fd); + $fwrite (fd, " 1049"); + end + 7'b00_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1050"); + case ({foo[ 9],foo[ 5]}) + 2'b00: begin - $fwrite (fd, " 1023"); - ozoneacc(foo[18], fd); - $fwrite (fd, " 1024"); - $fwrite (fd, " 1025"); - if (foo[19]) - $fwrite (fd, " 1026"); - else - $fwrite (fd, " 1027"); + $fwrite (fd, " 1051"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); end + 2'b01: + begin + $fwrite (fd, " 1052"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + end + 2'b10: + begin + $fwrite (fd, " 1053"); + ozoneae(foo[14:12], fd); + end + 2'b11: $fwrite (fd, " 1054"); + endcase + dude(fd); + $fwrite (fd, " 1055"); + end + 7'b01_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1056"); + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1057"); + end + 2'b01: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1058"); + end + 2'b10: + begin + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1059"); + end + 2'b11: $fwrite (fd, " 1060"); + endcase + dude(fd); + $fwrite (fd, " 1061"); + end + 7'b10_0_110_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1062"); + $fwrite (fd, " 1063"); + if (foo[12]) + $fwrite (fd, " 1064"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + dude(fd); + $fwrite (fd, " 1065"); + end + 7'b10_0_110_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1066"); + if (foo[12]) + $fwrite (fd, " 1067"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1068"); + dude(fd); + $fwrite (fd, " 1069"); + end + 7'b??_?_000_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1070"); + $fwrite (fd, " 1071"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1072"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1073"); + end + 7'b??_?_100_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1074"); + $fwrite (fd, " 1075"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1076"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1077"); + end + 7'b??_?_001_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1078"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1079"); + $fwrite (fd, " 1080"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1081"); + end + 7'b??_?_011_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1082"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1083"); + $fwrite (fd, " 1084"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1085"); + end + 7'b??_?_101_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1086"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1087"); + end + endcase + 17'b00_10??_?_????_?0_0110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1088"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1089"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1090"); + end + 17'b00_10??_?_????_00_0111 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1091"); + if (foo[ 6]) + $fwrite (fd, " 1092"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + $fwrite (fd, " 1093"); + $fwrite (fd, " 1094"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1095"); + endcase + dude(fd); + $fwrite (fd, " 1096"); + end + 17'b00_10??_?_????_?0_0100 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1097"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1098"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1099"); + end + 17'b00_10??_?_????_10_0111 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1100"); + $fwrite (fd, " 1101"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1102"); + endcase + $fwrite (fd, " 1103"); + if (foo[ 6]) + $fwrite (fd, " 1104"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + dude(fd); + $fwrite (fd, " 1105"); + end + 17'b00_10??_?_????_?0_1110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1106"); + case (foo[11:9]) + 3'h2: + begin + $fwrite (fd, " 1107"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1108"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1109"); + end + 3'h6: + begin + $fwrite (fd, " 1110"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1111"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1112"); + end + 3'h0: + begin + $fwrite (fd, " 1113"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1114"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1115"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1116"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h1: + begin + $fwrite (fd, " 1117"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1118"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1119"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1120"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h4: + begin + $fwrite (fd, " 1121"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1122"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1123"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1124"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h5: + begin + $fwrite (fd, " 1125"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1126"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1127"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1128"); + else + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1129"); + end + 17'b00_10??_?_????_?0_1111 : + casez (foo[14: 9]) + 6'b001_10_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1130"); + $fwrite (fd, " 1131"); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1132"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1133"); + end + 6'b???_11_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1134"); + ozoneae(foo[14:12], fd); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1135"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1136"); + end + 6'b000_10_1, + 6'b010_10_1, + 6'b100_10_1, + 6'b110_10_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1137"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1138"); + if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) + $fwrite (fd, " 1139"); else - ozonerx(foo, fd); + ozonexe(foo[ 8: 5], fd); dude(fd); - $fwrite (fd, " 1028"); + $fwrite (fd, " 1140"); end - 17'b10_110?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1029"); - $fwrite (fd, " 1030"); - ozonehl(foo[20], fd); - $fwrite (fd, " 1031"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1032"); - end - 17'b10_111?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1033"); - $fwrite (fd, " 1034"); - ozonehl(foo[20], fd); - $fwrite (fd, " 1035"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1036"); - end - 17'b11_001?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1037"); - ozonerx(foo, fd); - $fwrite (fd, " 1038"); - $fwrite (fd, " 1039"); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1040"); - end - 17'b11_111?_?_????_??_???? : - begin - ozonef1(foo, fd); - $fwrite (fd, " 1041"); - $fwrite (fd, " 1042"); - ozonerx(foo, fd); - $fwrite (fd, " 1043"); - if (foo[20]) - $fwrite (fd, " 1044"); - else - $fwrite (fd, " 1045"); - dude(fd); - $fwrite (fd, " 1046"); - end - 17'b00_10??_?_????_?1_1111 : - casez (foo[11: 5]) - 7'b??_0_010_0: - begin - $fwrite (fd, " 1047"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1048"); - ozonef1e(foo, fd); - dude(fd); - $fwrite (fd, " 1049"); - end - 7'b00_?_110_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1050"); - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - $fwrite (fd, " 1051"); - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - end - 2'b01: - begin - $fwrite (fd, " 1052"); - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - end - 2'b10: - begin - $fwrite (fd, " 1053"); - ozoneae(foo[14:12], fd); - end - 2'b11: $fwrite (fd, " 1054"); - endcase - dude(fd); - $fwrite (fd, " 1055"); - end - 7'b01_?_110_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1056"); - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - $fwrite (fd, " 1057"); - end - 2'b01: - begin - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - $fwrite (fd, " 1058"); - end - 2'b10: - begin - ozoneae(foo[14:12], fd); - $fwrite (fd, " 1059"); - end - 2'b11: $fwrite (fd, " 1060"); - endcase - dude(fd); - $fwrite (fd, " 1061"); - end - 7'b10_0_110_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1062"); - $fwrite (fd, " 1063"); - if (foo[12]) - $fwrite (fd, " 1064"); - else - ozonerab({4'b1001, foo[14:12]}, fd); - dude(fd); - $fwrite (fd, " 1065"); - end - 7'b10_0_110_1: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1066"); - if (foo[12]) - $fwrite (fd, " 1067"); - else - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1068"); - dude(fd); - $fwrite (fd, " 1069"); - end - 7'b??_?_000_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1070"); - $fwrite (fd, " 1071"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1072"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1073"); - end - 7'b??_?_100_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1074"); - $fwrite (fd, " 1075"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1076"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1077"); - end - 7'b??_?_001_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1078"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1079"); - $fwrite (fd, " 1080"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1081"); - end - 7'b??_?_011_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1082"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1083"); - $fwrite (fd, " 1084"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1085"); - end - 7'b??_?_101_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1086"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1087"); - end - endcase - 17'b00_10??_?_????_?0_0110 : + 6'b000_10_0, + 6'b010_10_0, + 6'b100_10_0, + 6'b110_10_0: begin ozonef1e(foo, fd); - $fwrite (fd, " 1088"); - ozoneae(foo[ 8: 6], fd); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1089"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1090"); - end - 17'b00_10??_?_????_00_0111 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1091"); - if (foo[ 6]) - $fwrite (fd, " 1092"); - else - ozonerab({4'b1001, foo[ 8: 6]}, fd); - $fwrite (fd, " 1093"); - $fwrite (fd, " 1094"); - ozonerme(foo[14:12], fd); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0, fd); - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1095"); - endcase - dude(fd); - $fwrite (fd, " 1096"); - end - 17'b00_10??_?_????_?0_0100 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1097"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1098"); - ozoneae(foo[ 8: 6], fd); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1099"); - end - 17'b00_10??_?_????_10_0111 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1100"); - $fwrite (fd, " 1101"); - ozonerme(foo[14:12], fd); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0, fd); - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1102"); - endcase - $fwrite (fd, " 1103"); - if (foo[ 6]) - $fwrite (fd, " 1104"); - else - ozonerab({4'b1001, foo[ 8: 6]}, fd); - dude(fd); - $fwrite (fd, " 1105"); - end - 17'b00_10??_?_????_?0_1110 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1106"); - case (foo[11:9]) - 3'h2: - begin - $fwrite (fd, " 1107"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1108"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1109"); - end - 3'h6: - begin - $fwrite (fd, " 1110"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1111"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1112"); - end - 3'h0: - begin - $fwrite (fd, " 1113"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1114"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1115"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1116"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h1: - begin - $fwrite (fd, " 1117"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1118"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1119"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1120"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h4: - begin - $fwrite (fd, " 1121"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1122"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1123"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1124"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h5: - begin - $fwrite (fd, " 1125"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1126"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1127"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1128"); - else - ozonexe(foo[ 8: 5], fd); - end - endcase - dude(fd); - $fwrite (fd, " 1129"); - end - 17'b00_10??_?_????_?0_1111 : - casez (foo[14: 9]) - 6'b001_10_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1130"); - $fwrite (fd, " 1131"); - ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); - $fwrite (fd, " 1132"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1133"); - end - 6'b???_11_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1134"); - ozoneae(foo[14:12], fd); - ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); - $fwrite (fd, " 1135"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1136"); - end - 6'b000_10_1, - 6'b010_10_1, - 6'b100_10_1, - 6'b110_10_1: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1137"); - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1138"); - if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) - $fwrite (fd, " 1139"); - else - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1140"); - end - 6'b000_10_0, - 6'b010_10_0, - 6'b100_10_0, - 6'b110_10_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1141"); - $fwrite (fd, " 1142"); - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1143"); - $fwrite (fd, " 1144"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1145"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1146"); - end - 6'b???_00_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1147"); - if (foo[ 9]) - begin - $fwrite (fd, " 1148"); - ozoneae(foo[14:12], fd); - end - else - begin - $fwrite (fd, " 1149"); - ozoneae(foo[14:12], fd); - $fwrite (fd, " 1150"); - end - $fwrite (fd, " 1151"); - $fwrite (fd, " 1152"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1153"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1154"); - end - 6'b???_01_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1155"); - ozoneae(foo[14:12], fd); - if (foo[ 9]) - $fwrite (fd, " 1156"); - else - $fwrite (fd, " 1157"); - $fwrite (fd, " 1158"); - $fwrite (fd, " 1159"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1160"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1161"); - end - 6'b011_10_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1162"); - case (foo[ 8: 5]) - 4'h0: $fwrite (fd, " 1163"); - 4'h1: $fwrite (fd, " 1164"); - 4'h2: $fwrite (fd, " 1165"); - 4'h3: $fwrite (fd, " 1166"); - 4'h4: $fwrite (fd, " 1167"); - 4'h5: $fwrite (fd, " 1168"); - 4'h8: $fwrite (fd, " 1169"); - 4'h9: $fwrite (fd, " 1170"); - 4'ha: $fwrite (fd, " 1171"); - 4'hb: $fwrite (fd, " 1172"); - 4'hc: $fwrite (fd, " 1173"); - 4'hd: $fwrite (fd, " 1174"); - default: $fwrite (fd, " 1175"); - endcase - dude(fd); - $fwrite (fd, " 1176"); - end - default: $fwrite (fd, " 1177"); - endcase - 17'b00_10??_?_????_?0_110? : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1178"); - $fwrite (fd, " 1179"); - ozonef1e_hl(foo[11:9], foo[0], fd); - $fwrite (fd, " 1180"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1181"); + $fwrite (fd, " 1141"); + $fwrite (fd, " 1142"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1143"); + $fwrite (fd, " 1144"); ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1182"); + $fwrite (fd, " 1145"); ozonexe(foo[ 8: 5], fd); dude(fd); - $fwrite (fd, " 1183"); + $fwrite (fd, " 1146"); end - 17'b00_10??_?_????_?1_110? : + 6'b???_00_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1147"); + if (foo[ 9]) + begin + $fwrite (fd, " 1148"); + ozoneae(foo[14:12], fd); + end + else + begin + $fwrite (fd, " 1149"); + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1150"); + end + $fwrite (fd, " 1151"); + $fwrite (fd, " 1152"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1153"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1154"); + end + 6'b???_01_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1155"); + ozoneae(foo[14:12], fd); + if (foo[ 9]) + $fwrite (fd, " 1156"); + else + $fwrite (fd, " 1157"); + $fwrite (fd, " 1158"); + $fwrite (fd, " 1159"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1160"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1161"); + end + 6'b011_10_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1162"); + case (foo[ 8: 5]) + 4'h0: $fwrite (fd, " 1163"); + 4'h1: $fwrite (fd, " 1164"); + 4'h2: $fwrite (fd, " 1165"); + 4'h3: $fwrite (fd, " 1166"); + 4'h4: $fwrite (fd, " 1167"); + 4'h5: $fwrite (fd, " 1168"); + 4'h8: $fwrite (fd, " 1169"); + 4'h9: $fwrite (fd, " 1170"); + 4'ha: $fwrite (fd, " 1171"); + 4'hb: $fwrite (fd, " 1172"); + 4'hc: $fwrite (fd, " 1173"); + 4'hd: $fwrite (fd, " 1174"); + default: $fwrite (fd, " 1175"); + endcase + dude(fd); + $fwrite (fd, " 1176"); + end + default: $fwrite (fd, " 1177"); + endcase + 17'b00_10??_?_????_?0_110? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1178"); + $fwrite (fd, " 1179"); + ozonef1e_hl(foo[11:9], foo[0], fd); + $fwrite (fd, " 1180"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1181"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1182"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1183"); + end + 17'b00_10??_?_????_?1_110? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1184"); + $fwrite (fd, " 1185"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1186"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1187"); + $fwrite (fd, " 1188"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1189"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1190"); + end + 17'b00_10??_?_????_?0_101? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1191"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1192"); + $fwrite (fd, " 1193"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1194"); + $fwrite (fd, " 1195"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1196"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1197"); + end + 17'b00_10??_?_????_?0_1001 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1198"); + $fwrite (fd, " 1199"); + ozonef1e_h(foo[11:9], fd); + $fwrite (fd, " 1200"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1201"); + case (foo[ 7: 5]) + 3'h1, + 3'h2, + 3'h3: + $fwrite (fd, " 1202"); + default: + begin + $fwrite (fd, " 1203"); + $fwrite (fd, " 1204"); + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1205"); + end + 17'b00_10??_?_????_?0_0101 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1206"); + case (foo[11: 9]) + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1207"); + default: + begin + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1208"); + $fwrite (fd, " 1209"); + end + endcase + $fwrite (fd, " 1210"); + $fwrite (fd, " 1211"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1212"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1213"); + end + 17'b00_10??_?_????_?1_1110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1214"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1215"); + $fwrite (fd, " 1216"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1217"); + $fwrite (fd, " 1218"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1219"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1220"); + end + 17'b00_10??_?_????_?0_1000 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1221"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1222"); + $fwrite (fd, " 1223"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1224"); + $fwrite (fd, " 1225"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1226"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1227"); + end + 17'b10_01??_?_????_??_???? : + begin + if (foo[27]) + $fwrite (fd," 1228"); + else + $fwrite (fd," 1229"); + ozonecon(foo[20:16], fd); + $fwrite (fd, " 1230"); + ozonef2(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1231"); + end + 17'b00_1000_?_????_01_0011 : + if (~|foo[ 9: 8]) + begin + if (foo[ 7]) + $fwrite (fd," 1232"); + else + $fwrite (fd," 1233"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1234"); + ozonef2e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1235"); + end + else + begin + $fwrite (fd, " 1236"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1237"); + ozonef3e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1238"); + end + 17'b11_110?_1_????_??_???? : + begin + ozonef3(foo[31:0], fd); + dude(fd); + $fwrite(fd, " 1239"); + end + 17'b11_110?_0_????_??_???? : + begin : f4_body + casez (foo[24:20]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite (fd, " 1240"); + end + 5'b0_00??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1241"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1242"); + dude(fd); + $fwrite(fd, " 1243"); + end + 5'b0_01??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1244"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozonearm(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1245"); + end + 5'b0_1011: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1246"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1247"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1248"); + dude(fd); + $fwrite(fd, " 1249"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1250"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1251"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1252"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1253"); + dude(fd); + $fwrite(fd, " 1254"); + end + 5'b0_1111 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1255"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1256"); + ozoneae(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1257"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1258"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1259"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1260"); + ozonearm(foo[18:16], fd); + $fwrite (fd, " 1261"); + dude(fd); + $fwrite(fd, " 1262"); + end + endcase + end + 17'b11_100?_?_????_??_???? : + casez (foo[23:19]) + 5'b111??, + 5'b0111?: begin - ozonef1e(foo, fd); - $fwrite (fd, " 1184"); - $fwrite (fd, " 1185"); - ozonef1e_hl(foo[11:9],foo[0], fd); - $fwrite (fd, " 1186"); - ozonef1e_ye(foo[14:9],foo[ 0], fd); - $fwrite (fd, " 1187"); - $fwrite (fd, " 1188"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1189"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1190"); - end - 17'b00_10??_?_????_?0_101? : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1191"); - ozonef1e_ye(foo[14:9],foo[ 0], fd); - $fwrite (fd, " 1192"); - $fwrite (fd, " 1193"); - ozonef1e_hl(foo[11:9],foo[0], fd); - $fwrite (fd, " 1194"); - $fwrite (fd, " 1195"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1196"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1197"); - end - 17'b00_10??_?_????_?0_1001 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1198"); - $fwrite (fd, " 1199"); - ozonef1e_h(foo[11:9], fd); - $fwrite (fd, " 1200"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1201"); - case (foo[ 7: 5]) - 3'h1, - 3'h2, - 3'h3: - $fwrite (fd, " 1202"); - default: - begin - $fwrite (fd, " 1203"); - $fwrite (fd, " 1204"); - ozonexe(foo[ 8: 5], fd); - end - endcase - dude(fd); - $fwrite (fd, " 1205"); - end - 17'b00_10??_?_????_?0_0101 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1206"); - case (foo[11: 9]) - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1207"); - default: - begin - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1208"); - $fwrite (fd, " 1209"); - end - endcase - $fwrite (fd, " 1210"); - $fwrite (fd, " 1211"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1212"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1213"); - end - 17'b00_10??_?_????_?1_1110 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1214"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1215"); - $fwrite (fd, " 1216"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1217"); - $fwrite (fd, " 1218"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1219"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1220"); - end - 17'b00_10??_?_????_?0_1000 : - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1221"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1222"); - $fwrite (fd, " 1223"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1224"); - $fwrite (fd, " 1225"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1226"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1227"); - end - 17'b10_01??_?_????_??_???? : - begin - if (foo[27]) - $fwrite (fd," 1228"); - else - $fwrite (fd," 1229"); - ozonecon(foo[20:16], fd); - $fwrite (fd, " 1230"); - ozonef2(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1231"); - end - 17'b00_1000_?_????_01_0011 : - if (~|foo[ 9: 8]) - begin - if (foo[ 7]) - $fwrite (fd," 1232"); - else - $fwrite (fd," 1233"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1234"); - ozonef2e(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1235"); - end - else - begin - $fwrite (fd, " 1236"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1237"); - ozonef3e(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1238"); - end - 17'b11_110?_1_????_??_???? : - begin - ozonef3(foo[31:0], fd); - dude(fd); - $fwrite(fd, " 1239"); - end - 17'b11_110?_0_????_??_???? : - begin : f4_body - casez (foo[24:20]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite (fd, " 1240"); - end - 5'b0_00??: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1241"); - ozoneacc(foo[25], fd); - ozonebmuop(foo[24:20], fd); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1242"); - dude(fd); - $fwrite(fd, " 1243"); - end - 5'b0_01??: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1244"); - ozoneacc(foo[25], fd); - ozonebmuop(foo[24:20], fd); - ozonearm(foo[18:16], fd); - dude(fd); - $fwrite(fd, " 1245"); - end - 5'b0_1011: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1246"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1247"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1248"); - dude(fd); - $fwrite(fd, " 1249"); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1250"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1251"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1252"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1253"); - dude(fd); - $fwrite(fd, " 1254"); - end - 5'b0_1111 : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1255"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1256"); - ozoneae(foo[18:16], fd); - dude(fd); - $fwrite(fd, " 1257"); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1258"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1259"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1260"); - ozonearm(foo[18:16], fd); - $fwrite (fd, " 1261"); - dude(fd); - $fwrite(fd, " 1262"); - end - endcase - end - 17'b11_100?_?_????_??_???? : - casez (foo[23:19]) - 5'b111??, - 5'b0111?: - begin - ozoneae(foo[26:24], fd); - $fwrite (fd, " 1263"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1264"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1265"); - skyway(foo[15:12], fd); - skyway(foo[11: 8], fd); - skyway(foo[ 7: 4], fd); - skyway(foo[ 3:0], fd); - $fwrite (fd, " 1266"); - dude(fd); - $fwrite(fd, " 1267"); - end - 5'b?0???, - 5'b110??: - begin - ozoneae(foo[26:24], fd); - $fwrite (fd, " 1268"); - if (foo[23:21] == 3'b100) - $fwrite (fd, " 1269"); - ozoneae(foo[18:16], fd); - if (foo[19]) - $fwrite (fd, " 1270"); - else - $fwrite (fd, " 1271"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1272"); - ozonef3f4_iext(foo[20:19], foo[15:0], fd); - dude(fd); - $fwrite(fd, " 1273"); - end - 5'b010??, - 5'b0110?: - begin - ozoneae(foo[18:16], fd); - if (foo[19]) - $fwrite (fd, " 1274"); - else - $fwrite (fd, " 1275"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1276"); - ozonef3f4_iext(foo[20:19], foo[15:0], fd); - dude(fd); - $fwrite(fd, " 1277"); - end - endcase - 17'b00_1000_?_????_11_0011 : - begin - $fwrite (fd," 1278"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1279"); - casez (foo[25:21]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite(fd, " 1280"); - end - 5'b0_00??: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1281"); - ozoneae(foo[17:15], fd); - ozonebmuop(foo[25:21], fd); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1282"); - dude(fd); - $fwrite(fd, " 1283"); - end - 5'b0_01??: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1284"); - ozoneae(foo[17:15], fd); - ozonebmuop(foo[25:21], fd); - ozonearm(foo[ 8: 6], fd); - dude(fd); - $fwrite(fd, " 1285"); - end - 5'b0_1011: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1286"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1287"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1288"); - dude(fd); - $fwrite(fd, " 1289"); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1290"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1291"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1292"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1293"); - dude(fd); - $fwrite(fd, " 1294"); - end - 5'b0_1111 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1295"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1296"); - ozoneae(foo[ 8: 6], fd); - dude(fd); - $fwrite(fd, " 1297"); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1298"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1299"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1300"); - ozonearm(foo[ 8: 6], fd); - $fwrite (fd, " 1301"); - dude(fd); - $fwrite(fd, " 1302"); - end - endcase - end - 17'b00_0010_?_????_??_???? : - begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1303"); - skyway(foo[19:16], fd); - dude(fd); - $fwrite(fd, " 1304"); - end - 17'b00_01??_?_????_??_???? : - begin - if (foo[27]) - begin - $fwrite (fd, " 1305"); - if (foo[26]) - $fwrite (fd, " 1306"); - else - $fwrite (fd, " 1307"); - skyway(foo[19:16], fd); - $fwrite (fd, " 1308"); - ozonerab({1'b0, foo[25:20]}, fd); - end - else - begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1309"); - if (foo[26]) - $fwrite (fd, " 1310"); - else - $fwrite (fd, " 1311"); - skyway(foo[19:16], fd); - $fwrite (fd, " 1312"); - end - dude(fd); - $fwrite(fd, " 1313"); - end - 17'b01_000?_?_????_??_???? : - begin - if (foo[26]) - begin - ozonerb(foo[25:20], fd); - $fwrite (fd, " 1314"); - ozoneae(foo[18:16], fd); - ozonehl(foo[19], fd); - end - else - begin - ozoneae(foo[18:16], fd); - ozonehl(foo[19], fd); - $fwrite (fd, " 1315"); - ozonerb(foo[25:20], fd); - end - dude(fd); - $fwrite(fd, " 1316"); - end - 17'b01_10??_?_????_??_???? : - begin - if (foo[27]) - begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1317"); - ozonerx(foo, fd); - end - else - begin - ozonerx(foo, fd); - $fwrite (fd, " 1318"); - ozonerab({1'b0, foo[25:20]}, fd); - end - dude(fd); - $fwrite(fd, " 1319"); - end - 17'b11_101?_?_????_??_???? : - begin - ozonerab (foo[26:20], fd); - $fwrite (fd, " 1320"); - skyway(foo[19:16], fd); + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1263"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1264"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1265"); skyway(foo[15:12], fd); skyway(foo[11: 8], fd); skyway(foo[ 7: 4], fd); - skyway(foo[ 3: 0], fd); + skyway(foo[ 3:0], fd); + $fwrite (fd, " 1266"); dude(fd); - $fwrite(fd, " 1321"); + $fwrite(fd, " 1267"); end - 17'b11_0000_?_????_??_???? : + 5'b?0???, + 5'b110??: begin - casez (foo[25:23]) - 3'b00?: - begin - ozonerab(foo[22:16], fd); - $fwrite (fd, " 1322"); - end - 3'b01?: - begin - $fwrite (fd, " 1323"); - if (foo[22:16]>=7'h60) - $fwrite (fd, " 1324"); - else - ozonerab(foo[22:16], fd); - end - 3'b110: - $fwrite (fd, " 1325"); - 3'b10?: - begin - $fwrite (fd, " 1326"); - if (foo[22:16]>=7'h60) - $fwrite (fd, " 1327"); - else - ozonerab(foo[22:16], fd); - end - 3'b111: - begin - $fwrite (fd, " 1328"); - ozonerab(foo[22:16], fd); - $fwrite (fd, " 1329"); - end - endcase - dude(fd); - $fwrite(fd, " 1330"); - end - 17'b00_10??_?_????_?1_0000 : - begin - if (foo[27]) - begin - $fwrite (fd, " 1331"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1332"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - $fwrite (fd, " 1333"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1334"); - else - ozonerab(foo[26:20], fd); - end + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1268"); + if (foo[23:21] == 3'b100) + $fwrite (fd, " 1269"); + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1270"); else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1335"); - $fwrite (fd, " 1336"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1337"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - $fwrite (fd, " 1338"); - end + $fwrite (fd, " 1271"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1272"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); - $fwrite(fd, " 1339"); + $fwrite(fd, " 1273"); end - 17'b00_101?_1_0000_?1_0010 : - if (~|foo[11: 7]) - begin - if (foo[ 6]) - begin - $fwrite (fd, " 1340"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1341"); - ozonejk(foo[ 5], fd); - $fwrite (fd, " 1342"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1343"); - else - ozonerab(foo[26:20], fd); - end - else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1344"); - $fwrite (fd, " 1345"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1346"); - ozonejk(foo[ 5], fd); - $fwrite (fd, " 1347"); - end - dude(fd); - $fwrite(fd, " 1348"); - end - else - $fwrite(fd, " 1349"); - 17'b00_100?_0_0011_?1_0101 : - if (~|foo[ 8: 7]) - begin - if (foo[6]) - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1350"); - ozoneye(foo[14: 9],foo[ 5], fd); - end - else - begin - ozoneye(foo[14: 9],foo[ 5], fd); - $fwrite (fd, " 1351"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1352"); - else - ozonerab(foo[26:20], fd); - end - dude(fd); - $fwrite(fd, " 1353"); - end - else - $fwrite(fd, " 1354"); - 17'b00_1001_0_0000_?1_0010 : - if (~|foo[25:20]) - begin - ozoneye(foo[14: 9],1'b0, fd); - $fwrite (fd, " 1355"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1356"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1357"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1358"); - end - else - $fwrite(fd, " 1359"); - 17'b00_101?_0_????_?1_0010 : - if (~foo[13]) - begin - if (foo[12]) - begin - $fwrite (fd, " 1360"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1361"); - else - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1362"); - $fwrite (fd, " 1363"); - skyway({1'b0,foo[18:16]}, fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1364"); - end - else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1365"); - $fwrite (fd, " 1366"); - skyway({1'b0,foo[18:16]}, fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1367"); - end - end - else - $fwrite(fd, " 1368"); - 17'b01_01??_?_????_??_???? : + 5'b010??, + 5'b0110?: begin - ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); - $fwrite (fd, " 1369"); - ozonerab({1'b0,foo[25:20]}, fd); + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1274"); + else + $fwrite (fd, " 1275"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1276"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); - $fwrite(fd, " 1370"); + $fwrite(fd, " 1277"); end - 17'b00_100?_?_???0_11_0101 : - if (~foo[6]) - begin - $fwrite (fd," 1371"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1372"); - ozonerab({foo[ 9: 7],foo[19:16]}, fd); - $fwrite (fd, " 1373"); - ozonerab({foo[26:20]}, fd); - dude(fd); - $fwrite(fd, " 1374"); - end - else - $fwrite(fd, " 1375"); - 17'b00_1000_?_????_?1_0010 : - if (~|foo[25:24]) - begin - ozonery(foo[23:20], fd); - $fwrite (fd, " 1376"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1377"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1378"); - end - else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) - begin - ozonery(foo[23:20], fd); - $fwrite (fd, " 1379"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1380"); - ozonejk(foo[ 5], fd); - dude(fd); - $fwrite(fd, " 1381"); - end - else - $fwrite(fd, " 1382"); - 17'b11_01??_?_????_??_????, - 17'b10_00??_?_????_??_???? : - if (foo[30]) - $fwrite(fd, " 1383:%x", foo[27:16]); + endcase + 17'b00_1000_?_????_11_0011 : + begin + $fwrite (fd," 1278"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1279"); + casez (foo[25:21]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1281"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1282"); + dude(fd); + $fwrite(fd, " 1283"); + end + 5'b0_01??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1284"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozonearm(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1285"); + end + 5'b0_1011: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1286"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1287"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1288"); + dude(fd); + $fwrite(fd, " 1289"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1290"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1291"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1292"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1293"); + dude(fd); + $fwrite(fd, " 1294"); + end + 5'b0_1111 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1295"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1296"); + ozoneae(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1297"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1298"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1299"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1300"); + ozonearm(foo[ 8: 6], fd); + $fwrite (fd, " 1301"); + dude(fd); + $fwrite(fd, " 1302"); + end + endcase + end + 17'b00_0010_?_????_??_???? : + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1303"); + skyway(foo[19:16], fd); + dude(fd); + $fwrite(fd, " 1304"); + end + 17'b00_01??_?_????_??_???? : + begin + if (foo[27]) + begin + $fwrite (fd, " 1305"); + if (foo[26]) + $fwrite (fd, " 1306"); else - $fwrite(fd, " 1384:%x", foo[27:16]); - 17'b00_10??_?_????_01_1000 : - if (~foo[6]) - begin - if (foo[7]) - $fwrite(fd, " 1385:%x", foo[27: 8]); - else - $fwrite(fd, " 1386:%x", foo[27: 8]); - end - else - $fwrite(fd, " 1387"); - 17'b00_10??_?_????_11_1000 : + $fwrite (fd, " 1307"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1308"); + ozonerab({1'b0, foo[25:20]}, fd); + end + else + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1309"); + if (foo[26]) + $fwrite (fd, " 1310"); + else + $fwrite (fd, " 1311"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1312"); + end + dude(fd); + $fwrite(fd, " 1313"); + end + 17'b01_000?_?_????_??_???? : + begin + if (foo[26]) + begin + ozonerb(foo[25:20], fd); + $fwrite (fd, " 1314"); + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + end + else + begin + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + $fwrite (fd, " 1315"); + ozonerb(foo[25:20], fd); + end + dude(fd); + $fwrite(fd, " 1316"); + end + 17'b01_10??_?_????_??_???? : + begin + if (foo[27]) + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1317"); + ozonerx(foo, fd); + end + else + begin + ozonerx(foo, fd); + $fwrite (fd, " 1318"); + ozonerab({1'b0, foo[25:20]}, fd); + end + dude(fd); + $fwrite(fd, " 1319"); + end + 17'b11_101?_?_????_??_???? : + begin + ozonerab (foo[26:20], fd); + $fwrite (fd, " 1320"); + skyway(foo[19:16], fd); + skyway(foo[15:12], fd); + skyway(foo[11: 8], fd); + skyway(foo[ 7: 4], fd); + skyway(foo[ 3: 0], fd); + dude(fd); + $fwrite(fd, " 1321"); + end + 17'b11_0000_?_????_??_???? : + begin + casez (foo[25:23]) + 3'b00?: + begin + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1322"); + end + 3'b01?: + begin + $fwrite (fd, " 1323"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1324"); + else + ozonerab(foo[22:16], fd); + end + 3'b110: + $fwrite (fd, " 1325"); + 3'b10?: + begin + $fwrite (fd, " 1326"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1327"); + else + ozonerab(foo[22:16], fd); + end + 3'b111: + begin + $fwrite (fd, " 1328"); + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1329"); + end + endcase + dude(fd); + $fwrite(fd, " 1330"); + end + 17'b00_10??_?_????_?1_0000 : + begin + if (foo[27]) + begin + $fwrite (fd, " 1331"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1332"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1333"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1334"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1335"); + $fwrite (fd, " 1336"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1337"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1338"); + end + dude(fd); + $fwrite(fd, " 1339"); + end + 17'b00_101?_1_0000_?1_0010 : + if (~|foo[11: 7]) + begin + if (foo[ 6]) + begin + $fwrite (fd, " 1340"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1341"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1342"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1343"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1344"); + $fwrite (fd, " 1345"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1346"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1347"); + end + dude(fd); + $fwrite(fd, " 1348"); + end + else + $fwrite(fd, " 1349"); + 17'b00_100?_0_0011_?1_0101 : + if (~|foo[ 8: 7]) + begin + if (foo[6]) + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1350"); + ozoneye(foo[14: 9],foo[ 5], fd); + end + else + begin + ozoneye(foo[14: 9],foo[ 5], fd); + $fwrite (fd, " 1351"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1352"); + else + ozonerab(foo[26:20], fd); + end + dude(fd); + $fwrite(fd, " 1353"); + end + else + $fwrite(fd, " 1354"); + 17'b00_1001_0_0000_?1_0010 : + if (~|foo[25:20]) + begin + ozoneye(foo[14: 9],1'b0, fd); + $fwrite (fd, " 1355"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1356"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1357"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1358"); + end + else + $fwrite(fd, " 1359"); + 17'b00_101?_0_????_?1_0010 : + if (~foo[13]) + begin + if (foo[12]) + begin + $fwrite (fd, " 1360"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1361"); + else + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1362"); + $fwrite (fd, " 1363"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1364"); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1365"); + $fwrite (fd, " 1366"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1367"); + end + end + else + $fwrite(fd, " 1368"); + 17'b01_01??_?_????_??_???? : + begin + ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); + $fwrite (fd, " 1369"); + ozonerab({1'b0,foo[25:20]}, fd); + dude(fd); + $fwrite(fd, " 1370"); + end + 17'b00_100?_?_???0_11_0101 : + if (~foo[6]) + begin + $fwrite (fd," 1371"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1372"); + ozonerab({foo[ 9: 7],foo[19:16]}, fd); + $fwrite (fd, " 1373"); + ozonerab({foo[26:20]}, fd); + dude(fd); + $fwrite(fd, " 1374"); + end + else + $fwrite(fd, " 1375"); + 17'b00_1000_?_????_?1_0010 : + if (~|foo[25:24]) + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1376"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1377"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1378"); + end + else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1379"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1380"); + ozonejk(foo[ 5], fd); + dude(fd); + $fwrite(fd, " 1381"); + end + else + $fwrite(fd, " 1382"); + 17'b11_01??_?_????_??_????, + 17'b10_00??_?_????_??_???? : + if (foo[30]) + $fwrite(fd, " 1383:%x", foo[27:16]); + else + $fwrite(fd, " 1384:%x", foo[27:16]); + 17'b00_10??_?_????_01_1000 : + if (~foo[6]) + begin + if (foo[7]) + $fwrite(fd, " 1385:%x", foo[27: 8]); + else + $fwrite(fd, " 1386:%x", foo[27: 8]); + end + else + $fwrite(fd, " 1387"); + 17'b00_10??_?_????_11_1000 : + begin + $fwrite (fd," 1388"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1389"); + if (foo[15]) + $fwrite (fd, " 1390"); + else + $fwrite (fd, " 1391"); + skyway(foo[27:24], fd); + skyway(foo[23:20], fd); + skyway(foo[19:16], fd); + skyway(foo[ 9: 6], fd); + dude(fd); + $fwrite(fd, " 1392"); + end + 17'b11_0001_?_????_??_???? : + casez (foo[25:22]) + 4'b01?? : + begin + $fwrite (fd," 1393"); + ozonecon(foo[20:16], fd); + case (foo[23:21]) + 3'h0 : $fwrite (fd, " 1394"); + 3'h1 : $fwrite (fd, " 1395"); + 3'h2 : $fwrite (fd, " 1396"); + 3'h3 : $fwrite (fd, " 1397"); + 3'h4 : $fwrite (fd, " 1398"); + 3'h5 : $fwrite (fd, " 1399"); + 3'h6 : $fwrite (fd, " 1400"); + 3'h7 : $fwrite (fd, " 1401"); + endcase + dude(fd); + $fwrite(fd, " 1402"); + end + 4'b0000 : + $fwrite(fd, " 1403:%x", foo[21:16]); + 4'b0010 : + if (~|foo[21:16]) + $fwrite(fd, " 1404"); + 4'b1010 : + if (~|foo[21:17]) begin - $fwrite (fd," 1388"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1389"); - if (foo[15]) - $fwrite (fd, " 1390"); + if (foo[16]) + $fwrite(fd, " 1405"); else - $fwrite (fd, " 1391"); - skyway(foo[27:24], fd); - skyway(foo[23:20], fd); - skyway(foo[19:16], fd); - skyway(foo[ 9: 6], fd); - dude(fd); - $fwrite(fd, " 1392"); + $fwrite(fd, " 1406"); end - 17'b11_0001_?_????_??_???? : - casez (foo[25:22]) - 4'b01?? : - begin - $fwrite (fd," 1393"); - ozonecon(foo[20:16], fd); - case (foo[23:21]) - 3'h0 : $fwrite (fd, " 1394"); - 3'h1 : $fwrite (fd, " 1395"); - 3'h2 : $fwrite (fd, " 1396"); - 3'h3 : $fwrite (fd, " 1397"); - 3'h4 : $fwrite (fd, " 1398"); - 3'h5 : $fwrite (fd, " 1399"); - 3'h6 : $fwrite (fd, " 1400"); - 3'h7 : $fwrite (fd, " 1401"); - endcase - dude(fd); - $fwrite(fd, " 1402"); - end - 4'b0000 : - $fwrite(fd, " 1403:%x", foo[21:16]); - 4'b0010 : - if (~|foo[21:16]) - $fwrite(fd, " 1404"); - 4'b1010 : - if (~|foo[21:17]) - begin - if (foo[16]) - $fwrite(fd, " 1405"); - else - $fwrite(fd, " 1406"); - end - default : - $fwrite(fd, " 1407"); - endcase - 17'b01_11??_?_????_??_???? : - if (foo[27:23] === 5'h00) - $fwrite(fd, " 1408:%x", foo[22:16]); - else - $fwrite(fd, " 1409:%x", foo[22:16]); - default: $fwrite(fd, " 1410"); - endcase - end - endtask + default : + $fwrite(fd, " 1407"); + endcase + 17'b01_11??_?_????_??_???? : + if (foo[27:23] === 5'h00) + $fwrite(fd, " 1408:%x", foo[22:16]); + else + $fwrite(fd, " 1409:%x", foo[22:16]); + default: $fwrite(fd, " 1410"); + endcase + end + endtask - //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) - //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule diff --git a/test_regress/t/t_case_x.v b/test_regress/t/t_case_x.v index 58d3a16f7..aa8b5e0b1 100644 --- a/test_regress/t/t_case_x.v +++ b/test_regress/t/t_case_x.v @@ -6,61 +6,61 @@ module t; - reg [3:0] value; - reg [3:0] valuex; + reg [3:0] value; + reg [3:0] valuex; - // verilator lint_off CASEOVERLAP - // verilator lint_off CASEWITHX - // verilator lint_off CASEX + // verilator lint_off CASEOVERLAP + // verilator lint_off CASEWITHX + // verilator lint_off CASEX - // Note for Verilator Xs must become zeros, or the Xs may match. + // Note for Verilator Xs must become zeros, or the Xs may match. - initial begin - value = 4'b1001; - valuex = 4'b1xxx; - case (value) - 4'b1xxx: $stop; - 4'b1???: $stop; - 4'b1001: ; - default: $stop; - endcase - case (valuex) - 4'b1???: $stop; - 4'b1xxx: ; - 4'b1001: ; - 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 - default: $stop; - endcase - // - casex (value) - 4'b100x: ; - default: $stop; - endcase - casex (value) - 4'b100?: ; - default: $stop; - endcase - casex (valuex) - 4'b100x: ; - default: $stop; - endcase - casex (valuex) - 4'b100?: ; - default: $stop; - endcase - // - casez (value) - 4'bxxxx: $stop; - 4'b100?: ; - default: $stop; - endcase - casez (valuex) - 4'b1xx?: ; - 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 - default: $stop; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + value = 4'b1001; + valuex = 4'b1xxx; + case (value) + 4'b1xxx: $stop; + 4'b1???: $stop; + 4'b1001: ; + default: $stop; + endcase + case (valuex) + 4'b1???: $stop; + 4'b1xxx: ; + 4'b1001: ; + 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + // + casex (value) + 4'b100x: ; + default: $stop; + endcase + casex (value) + 4'b100?: ; + default: $stop; + endcase + casex (valuex) + 4'b100x: ; + default: $stop; + endcase + casex (valuex) + 4'b100?: ; + default: $stop; + endcase + // + casez (value) + 4'bxxxx: $stop; + 4'b100?: ; + default: $stop; + endcase + casez (valuex) + 4'b1xx?: ; + 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_case_x_bad.out b/test_regress/t/t_case_x_bad.out index 0f5729ed2..b1f8c1adb 100644 --- a/test_regress/t/t_case_x_bad.out +++ b/test_regress/t/t_case_x_bad.out @@ -1,11 +1,11 @@ -%Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) - 14 | casex (value) - | ^~~~~ +%Warning-CASEX: t/t_case_x_bad.v:14:5: Suggest casez (with ?'s) in place of casex (with X's) + 14 | casex (value) + | ^~~~~ ... For warning description see https://verilator.org/warn/CASEX?v=latest ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. -%Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) - 19 | 4'b1xxx: $stop; - | ^~~~~~~ +%Warning-CASEWITHX: t/t_case_x_bad.v:19:7: Use of x/? constant in case statement, (perhaps intended casex/casez) + 19 | 4'b1xxx: $stop; + | ^~~~~~~ ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_case_x_bad.v b/test_regress/t/t_case_x_bad.v index 761842c49..fd145e9d8 100644 --- a/test_regress/t/t_case_x_bad.v +++ b/test_regress/t/t_case_x_bad.v @@ -4,21 +4,21 @@ // SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - value - ); +module t ( /*AUTOARG*/ + // Inputs + value +); - input [3:0] value; - always @ (/*AS*/value) begin - casex (value) - default: $stop; - endcase - case (value) - 4'b0000: $stop; - 4'b1xxx: $stop; - default: $stop; - endcase - end + input [3:0] value; + always @( /*AS*/ value) begin + casex (value) + default: $stop; + endcase + case (value) + 4'b0000: $stop; + 4'b1xxx: $stop; + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_case_zx_bad.out b/test_regress/t/t_case_zx_bad.out index 70c6a855e..ef3b53d07 100644 --- a/test_regress/t/t_case_zx_bad.out +++ b/test_regress/t/t_case_zx_bad.out @@ -1,6 +1,6 @@ -%Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) - 16 | 4'b1xxx: $stop; - | ^~~~~~~ +%Warning-CASEWITHX: t/t_case_zx_bad.v:16:7: Use of x constant in casez statement, (perhaps intended ?/z in constant) + 16 | 4'b1xxx: $stop; + | ^~~~~~~ ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_case_zx_bad.v b/test_regress/t/t_case_zx_bad.v index 58bab2d14..e62f718f6 100644 --- a/test_regress/t/t_case_zx_bad.v +++ b/test_regress/t/t_case_zx_bad.v @@ -4,18 +4,18 @@ // SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - value - ); +module t ( /*AUTOARG*/ + // Inputs + value +); - input [3:0] value; - always @ (/*AS*/value) begin - casez (value) - 4'b0000: $stop; - 4'b1xxx: $stop; - default: $stop; - endcase - end + input [3:0] value; + always @( /*AS*/ value) begin + casez (value) + 4'b0000: $stop; + 4'b1xxx: $stop; + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_cast_class.v b/test_regress/t/t_cast_class.v index 28c31716b..41041f236 100644 --- a/test_regress/t/t_cast_class.v +++ b/test_regress/t/t_cast_class.v @@ -5,35 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 class Base; - int b; + int b; endclass class BaseExtended extends Base; - int e; + int e; endclass module t; - Base v_cls_a; - BaseExtended v_cls_ab; - BaseExtended v_cls_ab1; + Base v_cls_a; + BaseExtended v_cls_ab; + BaseExtended v_cls_ab1; - initial begin - v_cls_a = Base'(null); - if (v_cls_a != null) $stop; + initial begin + v_cls_a = Base'(null); + if (v_cls_a != null) $stop; - v_cls_ab = new; - v_cls_ab.b = 10; - v_cls_ab.e = 20; + v_cls_ab = new; + v_cls_ab.b = 10; + v_cls_ab.e = 20; - v_cls_ab1 = BaseExtended'(v_cls_ab); - if (v_cls_ab1.b != 10) $stop; - if (v_cls_ab1.e != 20) $stop; + v_cls_ab1 = BaseExtended'(v_cls_ab); + if (v_cls_ab1.b != 10) $stop; + if (v_cls_ab1.e != 20) $stop; - v_cls_a = Base'(v_cls_ab); - if (v_cls_a.b != 10) $stop; + v_cls_a = Base'(v_cls_ab); + if (v_cls_a.b != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cast_class_incompat_bad.out b/test_regress/t/t_cast_class_incompat_bad.out index ee8e7cb1c..edb93f6e7 100644 --- a/test_regress/t/t_cast_class_incompat_bad.out +++ b/test_regress/t/t_cast_class_incompat_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_cast_class_incompat_bad.v:26:28: Dynamic, not static cast, required to cast 'class{}BaseExtended' from 'class{}Base' +%Error: t/t_cast_class_incompat_bad.v:26:26: Dynamic, not static cast, required to cast 'class{}BaseExtended' from 'class{}Base' : ... note: In instance 't' : ... Suggest dynamic $cast - 26 | cls_ab = BaseExtended'(cls_a); - | ^ + 26 | cls_ab = BaseExtended'(cls_a); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_cast_class_incompat_bad.v:27:20: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended' +%Error: t/t_cast_class_incompat_bad.v:27:18: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended' : ... note: In instance 't' - 27 | other = Other'(cls_ab); - | ^ + 27 | other = Other'(cls_ab); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_cast_class_incompat_bad.v b/test_regress/t/t_cast_class_incompat_bad.v index ca46da69c..0660b30fe 100644 --- a/test_regress/t/t_cast_class_incompat_bad.v +++ b/test_regress/t/t_cast_class_incompat_bad.v @@ -17,14 +17,14 @@ typedef Other Other_t; module t; - Base_t cls_a; - BaseExtended_t cls_ab; - Other_t other; + Base_t cls_a; + BaseExtended_t cls_ab; + Other_t other; - initial begin - cls_a = new; - cls_ab = BaseExtended'(cls_a); // bad-need dyn - other = Other'(cls_ab); // bad-incompat - end + initial begin + cls_a = new; + cls_ab = BaseExtended'(cls_a); // bad-need dyn + other = Other'(cls_ab); // bad-incompat + end endmodule diff --git a/test_regress/t/t_cast_param_logic.v b/test_regress/t/t_cast_param_logic.v index aeb6b494e..7542451ef 100644 --- a/test_regress/t/t_cast_param_logic.v +++ b/test_regress/t/t_cast_param_logic.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - #( +module t #( parameter type data_t = logic - ) - ( - input data_t[7:0] in_data - ); +) ( + input data_t [7:0] in_data +); - typedef data_t[7:0] in_data_t; + typedef data_t [7:0] in_data_t; - in_data_t out_data; - always_comb out_data = in_data_t'(in_data); + in_data_t out_data; + always_comb out_data = in_data_t'(in_data); endmodule diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v index ca4814eaa..68378ab81 100644 --- a/test_regress/t/t_cast_param_type.v +++ b/test_regress/t/t_cast_param_type.v @@ -4,33 +4,37 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum logic [1:0] {A, B, C } letters_t; +typedef enum logic [1:0] { + A, + B, + C +} letters_t; -module SubA - #(parameter letters_t LETTER = A) - (); +module SubA #( + parameter letters_t LETTER = A +) (); endmodule -module SubB - #(parameter letters_t LETTER = letters_t'(0)) - (); +module SubB #( + parameter letters_t LETTER = letters_t'(0) +) (); endmodule function automatic letters_t lfunc(int a); - return letters_t'(1); + return letters_t'(1); endfunction module t; - localparam FMT = lfunc(1); + localparam FMT = lfunc(1); - SubA suba0 (); - SubA #(.LETTER(letters_t'(1))) suba1 (); - SubB #(.LETTER(letters_t'(1))) subb2 (); + SubA suba0 (); + SubA #(.LETTER(letters_t'(1))) suba1 (); + SubB #(.LETTER(letters_t'(1))) subb2 (); - initial begin - if (lfunc(1) != B) $stop; - if (FMT != B) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (lfunc(1) != B) $stop; + if (FMT != B) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cast_signed.v b/test_regress/t/t_cast_signed.v index 9a3832675..28aa9d473 100644 --- a/test_regress/t/t_cast_signed.v +++ b/test_regress/t/t_cast_signed.v @@ -6,18 +6,18 @@ module t; - logic [7:0] smaller; - logic [15:0] bigger; - typedef logic [15:0] bigger_t; + logic [7:0] smaller; + logic [15:0] bigger; + typedef logic [15:0] bigger_t; - initial begin - smaller = 8'hfa; - bigger = bigger_t'(signed'(smaller)); - $display("%x", bigger); // NOCOMMIT - if (bigger != 16'hfffa) $stop; + initial begin + smaller = 8'hfa; + bigger = bigger_t'(signed'(smaller)); + $display("%x", bigger); // NOCOMMIT + if (bigger != 16'hfffa) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cast_size_bad.out b/test_regress/t/t_cast_size_bad.out index 538b9d168..59bc68f3b 100644 --- a/test_regress/t/t_cast_size_bad.out +++ b/test_regress/t/t_cast_size_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_cast_size_bad.v:14:15: Size-changing cast to zero or negative size +%Error: t/t_cast_size_bad.v:14:13: Size-changing cast to zero or negative size : ... note: In instance 't' - 14 | b = (-1)'(a); - | ^ + 14 | b = (-1)'(a); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. +%Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:7: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 14 | b = (-1)'(a); - | ^ + 14 | b = (-1)'(a); + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_cast_size_bad.v b/test_regress/t/t_cast_size_bad.v index c0dc36b4f..5fb49102f 100644 --- a/test_regress/t/t_cast_size_bad.v +++ b/test_regress/t/t_cast_size_bad.v @@ -6,12 +6,12 @@ module t; - int a; - reg [3:0] b; + int a; + reg [3:0] b; - initial begin - a = 1; - b = (-1)'(a); // Bad - end + initial begin + a = 1; + b = (-1)'(a); // Bad + end endmodule diff --git a/test_regress/t/t_cast_stream.v b/test_regress/t/t_cast_stream.v index 703ced890..fb2c3831a 100644 --- a/test_regress/t/t_cast_stream.v +++ b/test_regress/t/t_cast_stream.v @@ -10,26 +10,26 @@ // verilog_format: on typedef enum { - UVM_TLM_READ_COMMAND, - UVM_TLM_WRITE_COMMAND, - UVM_TLM_IGNORE_COMMAND + UVM_TLM_READ_COMMAND, + UVM_TLM_WRITE_COMMAND, + UVM_TLM_IGNORE_COMMAND } uvm_tlm_command_e; module t; - initial begin - automatic bit array[] = new [8]; - automatic int unsigned m_length; - automatic uvm_tlm_command_e m_command; + initial begin + automatic bit array[] = new[8]; + automatic int unsigned m_length; + automatic uvm_tlm_command_e m_command; - m_length = 2; - array = '{0, 0, 0, 0, 0, 0, 1, 0}; - array = new [$bits(m_length)] (array); - m_command = uvm_tlm_command_e'({ << bit { array }}); + m_length = 2; + array = '{0, 0, 0, 0, 0, 0, 1, 0}; + array = new[$bits(m_length)] (array); + m_command = uvm_tlm_command_e'({<5.9 + // 6.22.3 + `COMPATIBLE(v_string, `STRING_LITERAL); + `COMPATIBLE(v_int, v_enum_a); + `COMPATIBLE(v_int, v_real); + `COMPATIBLE(v_real, v_int); + // 6.22.4->5.9 `ifndef NC - `CAST_COMPATIBLE(v_string, v_int); + `CAST_COMPATIBLE(v_string, v_int); `endif - // 6.22.4->6.19.3 + // 6.22.4->6.19.3 `ifndef NC - `CAST_COMPATIBLE_ENUM(v_enum_a, v_int); - `CAST_COMPATIBLE_ENUM(v_enum_a, v_enum_b); + `CAST_COMPATIBLE_ENUM(v_enum_a, v_int); + `CAST_COMPATIBLE_ENUM(v_enum_a, v_enum_b); `endif - `CAST_COMPATIBLE_DYNAMIC(v_cls_ab, v_cls_a); - // 6.22.5 incompatible - `INCOMPATIBLE(v_cls_ab, v_int); + `CAST_COMPATIBLE_DYNAMIC(v_cls_ab, v_cls_a); + // 6.22.5 incompatible + `INCOMPATIBLE(v_cls_ab, v_int); `ifndef VCS - `INCOMPATIBLE(v_real, v_assoc_a); - `INCOMPATIBLE(v_real, v_q_a); + `INCOMPATIBLE(v_real, v_assoc_a); + `INCOMPATIBLE(v_real, v_q_a); `endif `ifndef VCS - `ifndef VERILATOR - `INCOMPATIBLE(v_chandle, v_int); - `endif +`ifndef VERILATOR + `INCOMPATIBLE(v_chandle, v_int); +`endif `endif `ifndef NC - `INCOMPATIBLE(v_cls_a, v_cls_b); + `INCOMPATIBLE(v_cls_a, v_cls_b); `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_assign_bad.out b/test_regress/t/t_class_assign_bad.out index eeb7d4666..189dddddc 100644 --- a/test_regress/t/t_class_assign_bad.out +++ b/test_regress/t/t_class_assign_bad.out @@ -1,38 +1,38 @@ -%Error: t/t_class_assign_bad.v:28:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' +%Error: t/t_class_assign_bad.v:30:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' - 28 | c = 0; - | ^ + 30 | c = 0; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_assign_bad.v:29:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' +%Error: t/t_class_assign_bad.v:31:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' - 29 | c = 1; - | ^ -%Error: t/t_class_assign_bad.v:30:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' + 31 | c = 1; + | ^ +%Error: t/t_class_assign_bad.v:32:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' : ... note: In instance 't' - 30 | c = c2; - | ^ -%Error: t/t_class_assign_bad.v:31:13: Assign RHS expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' + 32 | c = c2; + | ^ +%Error: t/t_class_assign_bad.v:33:11: Assign RHS expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' : ... note: In instance 't' - 31 | c_ext = c; - | ^ -%Error: t/t_class_assign_bad.v:32:11: Assign RHS expects a CLASSREFDTYPE 'Cls2', got CLASSREFDTYPE 'Cls' - : ... note: In instance 't' - 32 | ct2 = c; + 33 | c_ext = c; | ^ -%Error: t/t_class_assign_bad.v:34:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' +%Error: t/t_class_assign_bad.v:34:9: Assign RHS expects a CLASSREFDTYPE 'Cls2', got CLASSREFDTYPE 'Cls' : ... note: In instance 't' - 34 | t(0); - | ^ -%Error: t/t_class_assign_bad.v:35:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' + 34 | ct2 = c; + | ^ +%Error: t/t_class_assign_bad.v:36:5: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' - 35 | t(1); - | ^ -%Error: t/t_class_assign_bad.v:36:7: Function Argument expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' + 36 | t(0); + | ^ +%Error: t/t_class_assign_bad.v:37:5: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' - 36 | t(c2); - | ^ -%Error: t/t_class_assign_bad.v:37:7: Function Argument expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' + 37 | t(1); + | ^ +%Error: t/t_class_assign_bad.v:38:5: Function Argument expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' : ... note: In instance 't' - 37 | f(c); - | ^ + 38 | t(c2); + | ^ +%Error: t/t_class_assign_bad.v:39:5: Function Argument expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' + : ... note: In instance 't' + 39 | f(c); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_assign_bad.v b/test_regress/t/t_class_assign_bad.v index afa52f3aa..29063a6a7 100644 --- a/test_regress/t/t_class_assign_bad.v +++ b/test_regress/t/t_class_assign_bad.v @@ -16,24 +16,26 @@ endclass typedef Cls2 cls2_t; module t; - Cls c; - Cls2 c2; - cls2_t ct2; - ClsExt c_ext; + Cls c; + Cls2 c2; + cls2_t ct2; + ClsExt c_ext; - task t(Cls c); endtask - function void f(ClsExt c); endfunction + task t(Cls c); + endtask + function void f(ClsExt c); + endfunction - initial begin - c = 0; - c = 1; - c = c2; - c_ext = c; - ct2 = c; + initial begin + c = 0; + c = 1; + c = c2; + c_ext = c; + ct2 = c; - t(0); - t(1); - t(c2); - f(c); - end + t(0); + t(1); + t(c2); + f(c); + end endmodule diff --git a/test_regress/t/t_class_assign_cond.v b/test_regress/t/t_class_assign_cond.v index c1a040e2b..47ae4f288 100644 --- a/test_regress/t/t_class_assign_cond.v +++ b/test_regress/t/t_class_assign_cond.v @@ -5,89 +5,89 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int f; - function new(int x); - f = x; - endfunction + int f; + function new(int x); + f = x; + endfunction endclass class ExtendCls extends Cls; - function new(int x); - super.new(x); - endfunction + function new(int x); + super.new(x); + endfunction endclass class AnotherExtendCls extends Cls; - function new(int x); - super.new(x); - endfunction + function new(int x); + super.new(x); + endfunction endclass class ExtendExtendCls extends ExtendCls; - function new(int x); - super.new(x); - endfunction + function new(int x); + super.new(x); + endfunction endclass module t; - typedef ExtendCls ExtendCls_t; + typedef ExtendCls ExtendCls_t; - initial begin - automatic Cls cls1 = null; - automatic Cls cls2 = null; - automatic ExtendCls_t ext_cls = null; - automatic AnotherExtendCls an_ext_cls = null; - automatic ExtendExtendCls ext_ext_cls = null; - int r; + initial begin + automatic Cls cls1 = null; + automatic Cls cls2 = null; + automatic ExtendCls_t ext_cls = null; + automatic AnotherExtendCls an_ext_cls = null; + automatic ExtendExtendCls ext_ext_cls = null; + int r; - cls1 = (cls1 == null) ? cls2 : cls1; - if (cls1 != null) $stop; + cls1 = (cls1 == null) ? cls2 : cls1; + if (cls1 != null) $stop; - cls1 = new(1); - cls1 = (cls1 == null) ? cls2 : cls1; - if (cls1.f != 1) $stop; + cls1 = new(1); + cls1 = (cls1 == null) ? cls2 : cls1; + if (cls1.f != 1) $stop; - cls1 = (cls1 != null) ? cls2 : cls1; - if (cls1 != null) $stop; + cls1 = (cls1 != null) ? cls2 : cls1; + if (cls1 != null) $stop; - cls1 = new(1); - cls2 = new(2); - cls1 = (cls1 != null) ? cls2 : cls1; - if (cls1.f != 2) $stop; + cls1 = new(1); + cls2 = new(2); + cls1 = (cls1 != null) ? cls2 : cls1; + if (cls1.f != 2) $stop; - cls1 = null; - cls1 = (ext_cls != null) ? ext_cls : cls2; - if (cls1.f != 2) $stop; + cls1 = null; + cls1 = (ext_cls != null) ? ext_cls : cls2; + if (cls1.f != 2) $stop; - ext_cls = new(3); - cls1 = (ext_cls != null) ? ext_cls : cls2; - if (cls1.f != 3) $stop; + ext_cls = new(3); + cls1 = (ext_cls != null) ? ext_cls : cls2; + if (cls1.f != 3) $stop; - ext_ext_cls = new(4); - an_ext_cls = new(5); - cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls; - if (cls1.f != 5) $stop; + ext_ext_cls = new(4); + an_ext_cls = new(5); + cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls; + if (cls1.f != 5) $stop; - ext_cls = new(3); - r = $random; - cls1 = r[0] ? ext_cls : null; - if (cls1 != null && cls1.f != 3) $stop; + ext_cls = new(3); + r = $random; + cls1 = r[0] ? ext_cls : null; + if (cls1 != null && cls1.f != 3) $stop; - ext_cls = new(3); - r = $random; - cls1 = r[0] ? null : ext_cls; - if (cls1 != null && cls1.f != 3) $stop; + ext_cls = new(3); + r = $random; + cls1 = r[0] ? null : ext_cls; + if (cls1 != null && cls1.f != 3) $stop; - ext_cls = new(3); - r = $random; - cls1 = r[0] ? null : null; - if (cls1 != null) $stop; + ext_cls = new(3); + r = $random; + cls1 = r[0] ? null : null; + if (cls1 != null) $stop; - ext_cls = new(3); - cls1 = (ext_cls == null) ? null : null; - if (cls1 != null) $stop; + ext_cls = new(3); + cls1 = (ext_cls == null) ? null : null; + if (cls1 != null) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_assign_cond_bad.out b/test_regress/t/t_class_assign_cond_bad.out index 6dbaf0b17..d2bc63410 100644 --- a/test_regress/t/t_class_assign_cond_bad.out +++ b/test_regress/t/t_class_assign_cond_bad.out @@ -1,22 +1,22 @@ -%Error: t/t_class_assign_cond_bad.v:22:25: Incompatible types of operands of condition operator: CLASSREFDTYPE 'Cls1' and CLASSREFDTYPE 'Cls2' +%Error: t/t_class_assign_cond_bad.v:22:23: Incompatible types of operands of condition operator: CLASSREFDTYPE 'Cls1' and CLASSREFDTYPE 'Cls2' : ... note: In instance 't' - 22 | c1 = (c1 != null) ? c1 : c2; - | ^ + 22 | c1 = (c1 != null) ? c1 : c2; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_assign_cond_bad.v:23:10: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2' +%Error: t/t_class_assign_cond_bad.v:23:8: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2' + : ... note: In instance 't' + 23 | c1 = (c1 != null) ? c2 : c2; + | ^ +%Error: t/t_class_assign_cond_bad.v:24:23: Incompatible types of operands of condition operator: BASICDTYPE 'logic' and CLASSREFDTYPE 'Cls2' : ... note: In instance 't' - 23 | c1 = (c1 != null) ? c2 : c2; - | ^ -%Error: t/t_class_assign_cond_bad.v:24:25: Incompatible types of operands of condition operator: BASICDTYPE 'logic' and CLASSREFDTYPE 'Cls2' + 24 | c2 = (c1 == null) ? 1'b1 : c2; + | ^ +%Error: t/t_class_assign_cond_bad.v:24:8: Assign RHS expects a CLASSREFDTYPE 'Cls2', got BASICDTYPE 'logic' + : ... note: In instance 't' + 24 | c2 = (c1 == null) ? 1'b1 : c2; + | ^ +%Error: t/t_class_assign_cond_bad.v:25:27: Incompatible types of operands of condition operator: CLASSREFDTYPE 'ExtCls1' and CLASSREFDTYPE 'Cls1' : ... note: In instance 't' - 24 | c2 = (c1 == null) ? 1'b1 : c2; - | ^ -%Error: t/t_class_assign_cond_bad.v:24:10: Assign RHS expects a CLASSREFDTYPE 'Cls2', got BASICDTYPE 'logic' - : ... note: In instance 't' - 24 | c2 = (c1 == null) ? 1'b1 : c2; - | ^ -%Error: t/t_class_assign_cond_bad.v:25:29: Incompatible types of operands of condition operator: CLASSREFDTYPE 'ExtCls1' and CLASSREFDTYPE 'Cls1' - : ... note: In instance 't' - 25 | ext_c1 = (c1 == null) ? ext_c1 : c1; - | ^ + 25 | ext_c1 = (c1 == null) ? ext_c1 : c1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_assign_cond_bad.v b/test_regress/t/t_class_assign_cond_bad.v index 8e51728e8..686fc40c5 100644 --- a/test_regress/t/t_class_assign_cond_bad.v +++ b/test_regress/t/t_class_assign_cond_bad.v @@ -14,14 +14,14 @@ class ExtCls1; endclass module t; - Cls1 c1; - Cls2 c2; - ExtCls1 ext_c1; + Cls1 c1; + Cls2 c2; + ExtCls1 ext_c1; - initial begin - c1 = (c1 != null) ? c1 : c2; - c1 = (c1 != null) ? c2 : c2; - c2 = (c1 == null) ? 1'b1 : c2; - ext_c1 = (c1 == null) ? ext_c1 : c1; - end + initial begin + c1 = (c1 != null) ? c1 : c2; + c1 = (c1 != null) ? c2 : c2; + c2 = (c1 == null) ? 1'b1 : c2; + ext_c1 = (c1 == null) ? ext_c1 : c1; + end endmodule diff --git a/test_regress/t/t_class_capitalization.v b/test_regress/t/t_class_capitalization.v index 5bbcf882e..0c7db99ea 100644 --- a/test_regress/t/t_class_capitalization.v +++ b/test_regress/t/t_class_capitalization.v @@ -6,59 +6,59 @@ // Test different uppercase/lowercase capitalization cases class ClsMixed; - int m; - int M; + int m; + int M; endclass class Clsmixed; - int m; - int M; + int m; + int M; endclass module ModMixed; - // verilator no_inline_module - int m; - int M; + // verilator no_inline_module + int m; + int M; endmodule module Modmixed; - // verilator no_inline_module - int m; - int M; + // verilator no_inline_module + int m; + int M; endmodule module t; - // verilator no_inline_module + // verilator no_inline_module - ModMixed modMixed(); - Modmixed modmixed(); + ModMixed modMixed (); + Modmixed modmixed (); - initial begin - ClsMixed clsMixed; - Clsmixed clsmixed; + initial begin + ClsMixed clsMixed; + Clsmixed clsmixed; - clsMixed = new; - clsMixed.m = 1; - clsMixed.M = 2; - clsmixed = new; - clsmixed.m = 3; - clsmixed.M = 4; - if (clsMixed.m != 1) $stop; - if (clsMixed.M != 2) $stop; - if (clsmixed.m != 3) $stop; - if (clsmixed.M != 4) $stop; + clsMixed = new; + clsMixed.m = 1; + clsMixed.M = 2; + clsmixed = new; + clsmixed.m = 3; + clsmixed.M = 4; + if (clsMixed.m != 1) $stop; + if (clsMixed.M != 2) $stop; + if (clsmixed.m != 3) $stop; + if (clsmixed.M != 4) $stop; - modMixed.m = 1; - modMixed.M = 2; - modmixed.m = 3; - modmixed.M = 4; - if (modMixed.m != 1) $stop; - if (modMixed.M != 2) $stop; - if (modmixed.m != 3) $stop; - if (modmixed.M != 4) $stop; + modMixed.m = 1; + modMixed.M = 2; + modmixed.m = 3; + modmixed.M = 4; + if (modMixed.m != 1) $stop; + if (modMixed.M != 2) $stop; + if (modmixed.m != 3) $stop; + if (modmixed.M != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_class.v b/test_regress/t/t_class_class.v index d04c31774..4f0a91faf 100644 --- a/test_regress/t/t_class_class.v +++ b/test_regress/t/t_class_class.v @@ -6,33 +6,35 @@ // Note UVM internals do not require classes-in-classes package P; -class Cls #(type STORE_T=string); - STORE_T imembera; - STORE_T imemberb; - class SubCls; + class Cls #( + type STORE_T = string + ); + STORE_T imembera; + STORE_T imemberb; + class SubCls; STORE_T smembera; STORE_T smemberb; // TODO put extern function here or in t_class_extern.v to check link - endclass : SubCls - SubCls sc; -endclass : Cls + endclass : SubCls + SubCls sc; + endclass : Cls endpackage : P module t; - P::Cls#(int) c; - initial begin - c = new; - c.imembera = 10; - c.imemberb = 20; - c.sc = new; - c.sc.smembera = 30; - c.sc.smemberb = 40; - if (c.imembera != 10) $stop; - if (c.imemberb != 20) $stop; - if (c.sc.smembera != 30) $stop; - if (c.sc.smemberb != 40) $stop; + P::Cls #(int) c; + initial begin + c = new; + c.imembera = 10; + c.imemberb = 20; + c.sc = new; + c.sc.smembera = 30; + c.sc.smemberb = 40; + if (c.imembera != 10) $stop; + if (c.imemberb != 20) $stop; + if (c.sc.smembera != 30) $stop; + if (c.sc.smemberb != 40) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_compare.v b/test_regress/t/t_class_compare.v index 22521ee02..d85fe70b6 100644 --- a/test_regress/t/t_class_compare.v +++ b/test_regress/t/t_class_compare.v @@ -4,47 +4,49 @@ // SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) +// verilog_format: on class Cls; - class InnerCls; - int j; - endclass - int i; + class InnerCls; + int j; + endclass + int i; endclass class ExtendCls extends Cls; endclass module t; - initial begin - automatic Cls a = new; - automatic Cls b = new; - automatic ExtendCls ext = new; - automatic Cls::InnerCls ia = new; - automatic Cls::InnerCls ib = new; - automatic ExtendCls::InnerCls iext = new; - `check_ne(a, b) - `check_ne(a, ext) - `check_ne(ext, a) - `check_ne(ia, ib) - `check_ne(ia, iext) - `check_ne(iext, ia) - a = b; - ia = ib; - `check_eq(a, b) - `check_eq(ia, ib) - a = ext; - ia = iext; - `check_eq(a, ext) - `check_eq(ext, a) - `check_eq(ia, iext) - `check_eq(iext, ia) - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic Cls a = new; + automatic Cls b = new; + automatic ExtendCls ext = new; + automatic Cls::InnerCls ia = new; + automatic Cls::InnerCls ib = new; + automatic ExtendCls::InnerCls iext = new; + `check_ne(a, b) + `check_ne(a, ext) + `check_ne(ext, a) + `check_ne(ia, ib) + `check_ne(ia, iext) + `check_ne(iext, ia) + a = b; + ia = ib; + `check_eq(a, b) + `check_eq(ia, ib) + a = ext; + ia = iext; + `check_eq(a, ext) + `check_eq(ext, a) + `check_eq(ia, iext) + `check_eq(iext, ia) + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_const.v b/test_regress/t/t_class_const.v index e0ab5aaac..633c56042 100644 --- a/test_regress/t/t_class_const.v +++ b/test_regress/t/t_class_const.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - const int aconst = 10; - static const int astatic = 20; + const int aconst = 10; + static const int astatic = 20; endclass module t; - initial begin - automatic Cls c = new; - if (c.aconst !== 10) $stop; - if (Cls::astatic !== 20) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic Cls c = new; + if (c.aconst !== 10) $stop; + if (Cls::astatic !== 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_copy.v b/test_regress/t/t_class_copy.v index b2cd08082..74ab7f75d 100644 --- a/test_regress/t/t_class_copy.v +++ b/test_regress/t/t_class_copy.v @@ -5,33 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int imembera; - function int inc_methoda; imembera += 1; return imembera; endfunction + int imembera; + function int inc_methoda; + imembera += 1; + return imembera; + endfunction endclass module t; - initial begin - Cls c1; - Cls c2; - Cls c3; - c1 = new; - c1.imembera = 10; - if (c1.inc_methoda() != 11) $stop; + initial begin + Cls c1; + Cls c2; + Cls c3; + c1 = new; + c1.imembera = 10; + if (c1.inc_methoda() != 11) $stop; - // Assignment - c2 = c1; - if (c1.inc_methoda() != 12) $stop; - if (c2.inc_methoda() != 13) $stop; - if (c1.inc_methoda() != 14) $stop; + // Assignment + c2 = c1; + if (c1.inc_methoda() != 12) $stop; + if (c2.inc_methoda() != 13) $stop; + if (c1.inc_methoda() != 14) $stop; - // Shallow copy - c3 = new c1; + // Shallow copy + c3 = new c1; - if (c1.inc_methoda() != 15) $stop; - if (c3.inc_methoda() != 15) $stop; - if (c1.inc_methoda() != 16) $stop; + if (c1.inc_methoda() != 15) $stop; + if (c3.inc_methoda() != 15) $stop; + if (c1.inc_methoda() != 16) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_copy2.v b/test_regress/t/t_class_copy2.v index a296497c6..02a9ef322 100644 --- a/test_regress/t/t_class_copy2.v +++ b/test_regress/t/t_class_copy2.v @@ -4,33 +4,35 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; - bit x = 1; + bit x = 1; endclass module t; - Cls obj1; - Cls obj2; + Cls obj1; + Cls obj2; - initial begin - obj1 = new; - `checkh(obj1.x, 1); + initial begin + obj1 = new; + `checkh(obj1.x, 1); - obj1.x = 0; - obj2 = new obj1; - `checkh(obj2.x, 0); + obj1.x = 0; + obj2 = new obj1; + `checkh(obj2.x, 0); - obj2.x = 1; - `checkh(obj1.x, 0); - `checkh(obj2.x, 1); + obj2.x = 1; + `checkh(obj1.x, 0); + `checkh(obj2.x, 1); - obj2.x = 0; - `checkh(obj2.x, 0); + obj2.x = 0; + `checkh(obj2.x, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_copy_bad.out b/test_regress/t/t_class_copy_bad.out index 217391ca2..1cb0f10f2 100644 --- a/test_regress/t/t_class_copy_bad.out +++ b/test_regress/t/t_class_copy_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_copy_bad.v:19:16: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' than expected 'CLASSREFDTYPE 'Other'' +%Error: t/t_class_copy_bad.v:22:14: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' than expected 'CLASSREFDTYPE 'Other'' : ... note: In instance 't' - 19 | c1 = new co; - | ^~ + 22 | c1 = new co; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_copy_bad.v b/test_regress/t/t_class_copy_bad.v index d69b81f9d..9eb608f71 100644 --- a/test_regress/t/t_class_copy_bad.v +++ b/test_regress/t/t_class_copy_bad.v @@ -8,14 +8,17 @@ class Other; endclass class Cls; - int imembera; - function int inc_methoda; imembera += 1; return imembera; endfunction + int imembera; + function int inc_methoda; + imembera += 1; + return imembera; + endfunction endclass module t; - initial begin - Cls c1; - Other co; - c1 = new co; // Bad, incompatible types - end + initial begin + Cls c1; + Other co; + c1 = new co; // Bad, incompatible types + end endmodule diff --git a/test_regress/t/t_class_defaultparams.v b/test_regress/t/t_class_defaultparams.v index f5c955929..bd73519fc 100644 --- a/test_regress/t/t_class_defaultparams.v +++ b/test_regress/t/t_class_defaultparams.v @@ -5,25 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 // verilator lint_off NORETURN -class c0 #(type T= real); +class c0 #( + type T = real +); static function T f(); endfunction endclass -class c2 #(type REQ=int, type RSP= int, type IMP=int); - function new (IMP imp); +class c2 #( + type REQ = int, + type RSP = int, + type IMP = int +); + function new(IMP imp); endfunction endclass -class c3 #(type REQ, type RSP, type IMP=RSP); - function new (IMP imp); +class c3 #( + type REQ, + type RSP, + type IMP = RSP +); + function new(IMP imp); endfunction endclass -class c1 #(type REQ= int, RSP=REQ); - typedef c1 #( REQ , RSP) this_type; - typedef c0 #(this_type) type_id; +class c1 #( + type REQ = int, + RSP = REQ +); + typedef c1#(REQ, RSP) this_type; + typedef c0#(this_type) type_id; c2 #(REQ, RSP, this_type) c2inst; - function new (string name, int parent); - c2inst = new (this); + function new(string name, int parent); + c2inst = new(this); endfunction c3 #(REQ, this_type) c3inst; @@ -42,18 +55,18 @@ interface interf; endinterface module t; // `test - interf interf_inst(); + interf interf_inst (); endmodule class topc; // `test endclass class paramcl; -endclass: paramcl +endclass : paramcl class c5; -c1 #(paramcl) seq; -function void f(); - seq = c1 #(paramcl)::type_id::f(); -endfunction: f + c1 #(paramcl) seq; + function void f(); + seq = c1#(paramcl)::type_id::f(); + endfunction : f endclass c5 c5inst; diff --git a/test_regress/t/t_class_diamond.v b/test_regress/t/t_class_diamond.v index a75bb27e9..30ec99401 100644 --- a/test_regress/t/t_class_diamond.v +++ b/test_regress/t/t_class_diamond.v @@ -6,54 +6,54 @@ module class_tb (); interface class Ibase; - pure virtual function int fn(); + pure virtual function int fn(); endclass interface class Ic1 extends Ibase; - pure virtual function int fn1(); + pure virtual function int fn1(); endclass interface class Ic2 extends Ibase; - pure virtual function int fn2(); + pure virtual function int fn2(); endclass interface class Ic3 extends Ic1, Ic2; endclass class Cls implements Ic3; - virtual function int fn(); - return 10; - endfunction - virtual function int fn1(); - return 1; - endfunction - virtual function int fn2(); - return 2; - endfunction + virtual function int fn(); + return 10; + endfunction + virtual function int fn1(); + return 1; + endfunction + virtual function int fn2(); + return 2; + endfunction endclass - initial begin - Cls cls; - Ibase ibase; - Ic1 ic1; - Ic2 ic2; - Ic3 ic3; - cls = new; - if (cls.fn() != 10) $stop; - if (cls.fn1() != 1) $stop; - if (cls.fn2() != 2) $stop; - ibase = cls; - ic1 = cls; - ic2 = cls; - ic3 = cls; - if (ibase.fn() != 10) $stop; - if (ic1.fn() != 10) $stop; - if (ic2.fn() != 10) $stop; - if (ic3.fn() != 10) $stop; - if (ic1.fn1() != 1) $stop; - if (ic2.fn2() != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls cls; + Ibase ibase; + Ic1 ic1; + Ic2 ic2; + Ic3 ic3; + cls = new; + if (cls.fn() != 10) $stop; + if (cls.fn1() != 1) $stop; + if (cls.fn2() != 2) $stop; + ibase = cls; + ic1 = cls; + ic2 = cls; + ic3 = cls; + if (ibase.fn() != 10) $stop; + if (ic1.fn() != 10) $stop; + if (ic2.fn() != 10) $stop; + if (ic3.fn() != 10) $stop; + if (ic1.fn1() != 1) $stop; + if (ic2.fn2() != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_dict.v b/test_regress/t/t_class_dict.v index bef95456d..06d2a75e4 100644 --- a/test_regress/t/t_class_dict.v +++ b/test_regress/t/t_class_dict.v @@ -4,27 +4,29 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; - int x; - function new(int a); - x = a; - endfunction + int x; + function new(int a); + x = a; + endfunction endclass module t; - initial begin - automatic int dict[Cls]; - automatic Cls c1 = new(1); - automatic Cls c2 = new(2); - dict[c1] = 1; - dict[c2] = 2; - `checkh(dict[c1], 1); - `checkh(dict[c2], 2); + initial begin + automatic int dict[Cls]; + automatic Cls c1 = new(1); + automatic Cls c2 = new(2); + dict[c1] = 1; + dict[c2] = 2; + `checkh(dict[c1], 1); + `checkh(dict[c2], 2); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_enum.v b/test_regress/t/t_class_enum.v index f4147a18a..bd30cd2f8 100644 --- a/test_regress/t/t_class_enum.v +++ b/test_regress/t/t_class_enum.v @@ -6,14 +6,18 @@ module t; -class Cls; - typedef enum {A = 10, B = 20, C = 30} en_t; -endclass + class Cls; + typedef enum { + A = 10, + B = 20, + C = 30 + } en_t; + endclass - initial begin - Cls c; - if (c.A != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + if (c.A != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_eq.v b/test_regress/t/t_class_eq.v index 8a17f094b..96b39e2aa 100644 --- a/test_regress/t/t_class_eq.v +++ b/test_regress/t/t_class_eq.v @@ -6,27 +6,27 @@ module t; -class A; - int num; - function new(int num); + class A; + int num; + function new(int num); this.num = num; - endfunction -endclass + endfunction + endclass -class B; - static A obj = new(2); -endclass + class B; + static A obj = new(2); + endclass -class C; - static A obj = new(5); -endclass + class C; + static A obj = new(5); + endclass - initial begin - #1; - $display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj)); - if (B::obj == C::obj) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #1; + $display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj)); + if (B::obj == C::obj) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends.v b/test_regress/t/t_class_extends.v index 85de6e686..11e670c56 100644 --- a/test_regress/t/t_class_extends.v +++ b/test_regress/t/t_class_extends.v @@ -7,55 +7,57 @@ typedef class Cls; class Base0; - // No members to check that to_string handles this + // No members to check that to_string handles this endclass class Base1 extends Base0; - int b1member; - typedef int T; + int b1member; + typedef int T; endclass class Base2 extends Base1; - int b2member; + int b2member; endclass class Cls extends Base2; - int imembera; - int imemberb; - T imemberc; + int imembera; + int imemberb; + T imemberc; endclass : Cls class uvm_object_wrapper; - function int create (); + function int create(); return 0; endfunction endclass -class uvm__registry #(type T=int) extends uvm_object_wrapper; +class uvm__registry #( + type T = int +) extends uvm_object_wrapper; // This override must be in the new symbol table, not // under the extend's symbol table - function int create (); + function int create(); T obj; return 0; endfunction endclass module t; - initial begin - Cls c; - c = new; - c.b1member = 10; - c.b2member = 30; - c.imembera = 100; - c.imemberb = 110; - c.imemberc = 120; - $display("Display: set = \"%p\"", c); // '{all 4 members} - if (c.b1member != 10) $stop; - if (c.b2member != 30) $stop; - if (c.imembera != 100) $stop; - if (c.imemberb != 110) $stop; - if (c.imemberc != 120) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c = new; + c.b1member = 10; + c.b2member = 30; + c.imembera = 100; + c.imemberb = 110; + c.imemberc = 120; + $display("Display: set = \"%p\"", c); // '{all 4 members} + if (c.b1member != 10) $stop; + if (c.b2member != 30) $stop; + if (c.imembera != 100) $stop; + if (c.imemberb != 110) $stop; + if (c.imemberc != 120) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends1.v b/test_regress/t/t_class_extends1.v index 021bacfb2..9accc891d 100644 --- a/test_regress/t/t_class_extends1.v +++ b/test_regress/t/t_class_extends1.v @@ -5,84 +5,88 @@ // SPDX-License-Identifier: CC0-1.0 class Base0; - class BaseInnerOnly; - int inneronly; - function new(); - inneronly = 10; - if (inneronly != 10) $stop; - endfunction - endclass + class BaseInnerOnly; + int inneronly; + function new(); + inneronly = 10; + if (inneronly != 10) $stop; + endfunction + endclass - class BaseInnerOver; - int innerover; - function new(); - innerover = 10; - if (innerover != 10) $stop; - endfunction - endclass + class BaseInnerOver; + int innerover; + function new(); + innerover = 10; + if (innerover != 10) $stop; + endfunction + endclass - int baseonly; - int baseover; - BaseInnerOnly inneronly = new; - BaseInnerOver innerover = new; + int baseonly; + int baseover; + BaseInnerOnly inneronly = new; + BaseInnerOver innerover = new; - function void b_set_bo(int v); baseover = v; endfunction - function int b_get_bo(); return baseover; endfunction - function int get_bo(); return baseover; endfunction - function void b_set_io(int v); innerover.innerover = v; endfunction - function int b_get_io(); return innerover.innerover; endfunction - function int get_io(); return innerover.innerover; endfunction + // verilog_format: off + function void b_set_bo(int v); baseover = v; endfunction + function int b_get_bo(); return baseover; endfunction + function int get_bo(); return baseover; endfunction + function void b_set_io(int v); innerover.innerover = v; endfunction + function int b_get_io(); return innerover.innerover; endfunction + function int get_io(); return innerover.innerover; endfunction + // verilog_format: on endclass class Ext extends Base0; - class BaseInnerOver; - int innerover; - function new(); - innerover = 20; - if (innerover != 20) $stop; - endfunction - endclass + class BaseInnerOver; + int innerover; + function new(); + innerover = 20; + if (innerover != 20) $stop; + endfunction + endclass - int baseover; - int extonly; - BaseInnerOnly inneronly = new; - BaseInnerOver innerover = new; + int baseover; + int extonly; + BaseInnerOnly inneronly = new; + BaseInnerOver innerover = new; - function void e_set_bo(int v); baseover = v; endfunction - function int e_get_bo(); return baseover; endfunction - function int get_bo(); return baseover; endfunction - function void e_set_io(int v); innerover.innerover = v; endfunction - function int e_get_io(); return innerover.innerover; endfunction - function int get_io(); return innerover.innerover; endfunction + // verilog_format: off + function void e_set_bo(int v); baseover = v; endfunction + function int e_get_bo(); return baseover; endfunction + function int get_bo(); return baseover; endfunction + function void e_set_io(int v); innerover.innerover = v; endfunction + function int e_get_io(); return innerover.innerover; endfunction + function int get_io(); return innerover.innerover; endfunction + // verilog_format: on endclass module t; - initial begin - Ext c; - c = new; - c.baseonly = 10; - c.baseover = 20; - c.extonly = 30; - c.inneronly.inneronly = 40; - c.innerover.innerover = 50; - if (c.baseonly != 10) $stop; - if (c.baseover != 20) $stop; - if (c.extonly != 30) $stop; - if (c.inneronly.inneronly != 40) $stop; - if (c.innerover.innerover != 50) $stop; + initial begin + Ext c; + c = new; + c.baseonly = 10; + c.baseover = 20; + c.extonly = 30; + c.inneronly.inneronly = 40; + c.innerover.innerover = 50; + if (c.baseonly != 10) $stop; + if (c.baseover != 20) $stop; + if (c.extonly != 30) $stop; + if (c.inneronly.inneronly != 40) $stop; + if (c.innerover.innerover != 50) $stop; - c.b_set_bo(100); - c.e_set_bo(200); - c.b_set_io(300); - c.e_set_io(400); - if (c.b_get_bo() != 100) $stop; - if (c.e_get_bo() != 200) $stop; - if (c.get_bo() != 200) $stop; - if (c.b_get_io() != 300) $stop; - if (c.e_get_io() != 400) $stop; - if (c.get_io() != 400) $stop; + c.b_set_bo(100); + c.e_set_bo(200); + c.b_set_io(300); + c.e_set_io(400); + if (c.b_get_bo() != 100) $stop; + if (c.e_get_bo() != 200) $stop; + if (c.get_bo() != 200) $stop; + if (c.b_get_io() != 300) $stop; + if (c.e_get_io() != 400) $stop; + if (c.get_io() != 400) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends2.v b/test_regress/t/t_class_extends2.v index 3595601ae..dcc8fbbda 100644 --- a/test_regress/t/t_class_extends2.v +++ b/test_regress/t/t_class_extends2.v @@ -5,35 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; -class Base0; - class BaseInnerOnly; - int inneronly; - function new(); - inneronly = 10; - if (inneronly != 10) $stop; - endfunction - endclass + class Base0; + class BaseInnerOnly; + int inneronly; + function new(); + inneronly = 10; + if (inneronly != 10) $stop; + endfunction + endclass - class BaseInnerOver; - int innerover; - function new(); - innerover = 10; - if (innerover != 10) $stop; - endfunction - endclass + class BaseInnerOver; + int innerover; + function new(); + innerover = 10; + if (innerover != 10) $stop; + endfunction + endclass - int baseonly; - int baseover; - BaseInnerOnly inneronly = new; - BaseInnerOver innerover = new; + int baseonly; + int baseover; + BaseInnerOnly inneronly = new; + BaseInnerOver innerover = new; - function void b_set_bo(int v); baseover = v; endfunction - function int b_get_bo(); return baseover; endfunction - function int get_bo(); return baseover; endfunction - function void b_set_io(int v); innerover.innerover = v; endfunction - function int b_get_io(); return innerover.innerover; endfunction - function int get_io(); return innerover.innerover; endfunction -endclass + // verilog_format: off + function void b_set_bo(int v); baseover = v; endfunction + function int b_get_bo(); return baseover; endfunction + function int get_bo(); return baseover; endfunction + function void b_set_io(int v); innerover.innerover = v; endfunction + function int b_get_io(); return innerover.innerover; endfunction + function int get_io(); return innerover.innerover; endfunction + // verilog_format: on + endclass endpackage // We need to import Base0, as verilator currently doesn't support @@ -41,53 +43,55 @@ endpackage // `BaseInnerOnly` class inside `Ext` class. import Pkg::Base0; class Ext extends Pkg::Base0; - class BaseInnerOver; - int innerover; - function new(); - innerover = 20; - if (innerover != 20) $stop; - endfunction - endclass - int baseover; - int extonly; - BaseInnerOnly inneronly = new; - BaseInnerOver innerover = new; + class BaseInnerOver; + int innerover; + function new(); + innerover = 20; + if (innerover != 20) $stop; + endfunction + endclass + int baseover; + int extonly; + BaseInnerOnly inneronly = new; + BaseInnerOver innerover = new; - function void e_set_bo(int v); baseover = v; endfunction - function int e_get_bo(); return baseover; endfunction - function int get_bo(); return baseover; endfunction - function void e_set_io(int v); innerover.innerover = v; endfunction - function int e_get_io(); return innerover.innerover; endfunction - function int get_io(); return innerover.innerover; endfunction + // verilog_format: off + function void e_set_bo(int v); baseover = v; endfunction + function int e_get_bo(); return baseover; endfunction + function int get_bo(); return baseover; endfunction + function void e_set_io(int v); innerover.innerover = v; endfunction + function int e_get_io(); return innerover.innerover; endfunction + function int get_io(); return innerover.innerover; endfunction + // verilog_format: on endclass module t; - initial begin - Ext c; - c = new; - c.baseonly = 10; - c.baseover = 20; - c.extonly = 30; - c.inneronly.inneronly = 40; - c.innerover.innerover = 50; - if (c.baseonly != 10) $stop; - if (c.baseover != 20) $stop; - if (c.extonly != 30) $stop; - if (c.inneronly.inneronly != 40) $stop; - if (c.innerover.innerover != 50) $stop; + initial begin + Ext c; + c = new; + c.baseonly = 10; + c.baseover = 20; + c.extonly = 30; + c.inneronly.inneronly = 40; + c.innerover.innerover = 50; + if (c.baseonly != 10) $stop; + if (c.baseover != 20) $stop; + if (c.extonly != 30) $stop; + if (c.inneronly.inneronly != 40) $stop; + if (c.innerover.innerover != 50) $stop; - c.b_set_bo(100); - c.e_set_bo(200); - c.b_set_io(300); - c.e_set_io(400); - if (c.b_get_bo() != 100) $stop; - if (c.e_get_bo() != 200) $stop; - if (c.get_bo() != 200) $stop; - if (c.b_get_io() != 300) $stop; - if (c.e_get_io() != 400) $stop; - if (c.get_io() != 400) $stop; + c.b_set_bo(100); + c.e_set_bo(200); + c.b_set_io(300); + c.e_set_io(400); + if (c.b_get_bo() != 100) $stop; + if (c.e_get_bo() != 200) $stop; + if (c.get_bo() != 200) $stop; + if (c.b_get_io() != 300) $stop; + if (c.e_get_io() != 400) $stop; + if (c.get_io() != 400) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_aliased_real_bad.out b/test_regress/t/t_class_extends_aliased_real_bad.out index 33d8191ed..e755e239b 100644 --- a/test_regress/t/t_class_extends_aliased_real_bad.out +++ b/test_regress/t/t_class_extends_aliased_real_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_extends_aliased_real_bad.v:14:10: Attempting to extend using non-class - : ... note: In instance 't' - 14 | bar #(real_t) bar_real_t; - | ^~~~~~ +%Error: t/t_class_extends_aliased_real_bad.v:16:9: Attempting to extend using non-class + : ... note: In instance 't' + 16 | bar #(real_t) bar_real_t; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_extends_aliased_real_bad.v b/test_regress/t/t_class_extends_aliased_real_bad.v index a60a9b8e8..8c52d1429 100644 --- a/test_regress/t/t_class_extends_aliased_real_bad.v +++ b/test_regress/t/t_class_extends_aliased_real_bad.v @@ -6,14 +6,16 @@ module t; - class bar #(type T) extends T; - endclass + class bar #( + type T + ) extends T; + endclass - typedef real real_t; + typedef real real_t; - bar #(real_t) bar_real_t; + bar #(real_t) bar_real_t; - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_class_extends_arg.v b/test_regress/t/t_class_extends_arg.v index 784a66c7d..097b7a455 100644 --- a/test_regress/t/t_class_extends_arg.v +++ b/test_regress/t/t_class_extends_arg.v @@ -4,41 +4,43 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on class Base; - int m_s = 2; - function new(int def = 3); - m_s = def; - endfunction + int m_s = 2; + function new(int def = 3); + m_s = def; + endfunction endclass class Cls5Exp extends Base(5); - int m_a = 11; - function new(int def = 42); // Explicit new - m_a = def; - endfunction + int m_a = 11; + function new(int def = 42); // Explicit new + m_a = def; + endfunction endclass class Cls5Imp extends Base(5); - int m_a = 12; - // Implicit new + int m_a = 12; + // Implicit new endclass module t; - Cls5Exp ce; - Cls5Imp ci; + Cls5Exp ce; + Cls5Imp ci; - initial begin - ce = new(37); - `checkh(ce.m_s, 5); - `checkh(ce.m_a, 37); - ci = new; - `checkh(ci.m_s, 5); - `checkh(ci.m_a, 12); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + ce = new(37); + `checkh(ce.m_s, 5); + `checkh(ce.m_a, 37); + ci = new; + `checkh(ci.m_s, 5); + `checkh(ci.m_a, 12); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_arg_super_bad.out b/test_regress/t/t_class_extends_arg_super_bad.out index 8b163b5e4..5a9099315 100644 --- a/test_regress/t/t_class_extends_arg_super_bad.out +++ b/test_regress/t/t_class_extends_arg_super_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_class_extends_arg_super_bad.v:17:13: Explicit super.new not allowed with class extends arguments (IEEE 1800-2023 8.17) +%Error: t/t_class_extends_arg_super_bad.v:17:11: Explicit super.new not allowed with class extends arguments (IEEE 1800-2023 8.17) : ... Suggest remove super.new - 17 | super.new(33); - | ^~~ + 17 | super.new(33); + | ^~~ t/t_class_extends_arg_super_bad.v:14:25: ... Location of extends argument(s) 14 | class Cls5 extends Base(5); | ^ diff --git a/test_regress/t/t_class_extends_arg_super_bad.v b/test_regress/t/t_class_extends_arg_super_bad.v index 6dfd94fcb..7355c8ca9 100644 --- a/test_regress/t/t_class_extends_arg_super_bad.v +++ b/test_regress/t/t_class_extends_arg_super_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Base; - int m_s = 2; - function new(int def = 3); - m_s = def; - endfunction + int m_s = 2; + function new(int def = 3); + m_s = def; + endfunction endclass class Cls5 extends Base(5); - int m_a; - function new(int def = 42); - super.new(33); // Bad, can't super.new with extends args - m_a = def; - endfunction + int m_a; + function new(int def = 42); + super.new(33); // Bad, can't super.new with extends args + m_a = def; + endfunction endclass diff --git a/test_regress/t/t_class_extends_colon.v b/test_regress/t/t_class_extends_colon.v index b1cd70a17..77cbb599f 100644 --- a/test_regress/t/t_class_extends_colon.v +++ b/test_regress/t/t_class_extends_colon.v @@ -8,12 +8,14 @@ interface class Icempty; endclass : Icempty package Pkg; -class Icls1 #(parameter PARAM = 12); - localparam LP1 = 1; - function int getParam(); + class Icls1 #( + parameter PARAM = 12 + ); + localparam LP1 = 1; + function int getParam(); return PARAM; - endfunction -endclass + endfunction + endclass endpackage @@ -22,14 +24,14 @@ endclass module t; - Cls12 cp12; + Cls12 cp12; - initial begin - cp12 = new; - if (cp12.getParam() != 12) $stop; + initial begin + cp12 = new; + if (cp12.getParam() != 12) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_default.v b/test_regress/t/t_class_extends_default.v index 2960054dd..07b1c627b 100644 --- a/test_regress/t/t_class_extends_default.v +++ b/test_regress/t/t_class_extends_default.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 class Base1; - int s = 2; - function new(int def = 3); - s = def; - endfunction + int s = 2; + function new(int def = 3); + s = def; + endfunction endclass class Cls1 extends Base1(default); - // Gets new(int def) + // Gets new(int def) endclass module t; - initial begin - Cls1 c1; - Cls1 c5; - c1 = new(57); - if (c1.s !== 57) $stop; + initial begin + Cls1 c1; + Cls1 c5; + c1 = new(57); + if (c1.s !== 57) $stop; - c5 = new; - if (c5.s !== 5) $stop; + c5 = new; + if (c5.s !== 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_int_param_bad.out b/test_regress/t/t_class_extends_int_param_bad.out index 041883e98..c28b5eb00 100644 --- a/test_regress/t/t_class_extends_int_param_bad.out +++ b/test_regress/t/t_class_extends_int_param_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_extends_int_param_bad.v:9:23: Attempting to extend using non-class - : ... note: In instance 't' - 9 | class Bar #(type T=int) extends T; - | ^~~ +%Error: t/t_class_extends_int_param_bad.v:10:16: Attempting to extend using non-class + : ... note: In instance 't' + 10 | type T = int + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_extends_int_param_bad.v b/test_regress/t/t_class_extends_int_param_bad.v index abaad9b40..ce4611006 100644 --- a/test_regress/t/t_class_extends_int_param_bad.v +++ b/test_regress/t/t_class_extends_int_param_bad.v @@ -6,11 +6,13 @@ module t; - class Bar #(type T=int) extends T; - endclass + class Bar #( + type T = int + ) extends T; + endclass - initial begin - Bar#() bar; - $stop; - end + initial begin + Bar #() bar; + $stop; + end endmodule diff --git a/test_regress/t/t_class_extends_param.v b/test_regress/t/t_class_extends_param.v index 60f879286..df1554aa5 100644 --- a/test_regress/t/t_class_extends_param.v +++ b/test_regress/t/t_class_extends_param.v @@ -4,145 +4,148 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - ); +module t; - class Foo; - class InnerFoo; - int y = 10; - function int get_y; - return y; - endfunction - function int get_30; - return 30; - endfunction - endclass - - int x = 1; - InnerFoo foo = new; - function int get_x; - return x; + class Foo; + class InnerFoo; + int y = 10; + function int get_y; + return y; endfunction - function int get_3; - return 3; + function int get_30; + return 30; endfunction - function InnerFoo get_foo; - return foo; + endclass + + int x = 1; + InnerFoo foo = new; + function int get_x; + return x; + endfunction + function int get_3; + return 3; + endfunction + function InnerFoo get_foo; + return foo; + endfunction + endclass + + class Bar #( + type T = Foo + ) extends T; + endclass + + class Baz; + class InnerFoo; + int y = 20; + function int get_y; + return y; endfunction - endclass - - class Bar #(type T=Foo) extends T; - endclass - - class Baz; - class InnerFoo; - int y = 20; - function int get_y; - return y; - endfunction - function int get_40; - return 40; - endfunction - endclass - int x = 2; - InnerFoo foo = new; - function int get_x; - return x; + function int get_40; + return 40; endfunction - function int get_4; - return 4; - endfunction - function InnerFoo get_foo; - return foo; - endfunction - endclass + endclass + int x = 2; + InnerFoo foo = new; + function int get_x; + return x; + endfunction + function int get_4; + return 4; + endfunction + function InnerFoo get_foo; + return foo; + endfunction + endclass - class ExtendBar extends Bar#(); - function int get_x; - return super.get_x(); - endfunction - function int get_6; - return 2 * get_3(); - endfunction - endclass + class ExtendBar extends Bar #(); + function int get_x; + return super.get_x(); + endfunction + function int get_6; + return 2 * get_3(); + endfunction + endclass - class ExtendBar1 extends Bar #(Foo); - function int get_x; - return super.get_x(); - endfunction - function int get_6; - return 2 * get_3(); - endfunction - endclass + class ExtendBar1 extends Bar #(Foo); + function int get_x; + return super.get_x(); + endfunction + function int get_6; + return 2 * get_3(); + endfunction + endclass - class ExtendBarBaz extends Bar #(Baz); - function int get_x; - return super.get_x(); - endfunction - function int get_8; - return 2 * get_4(); - endfunction - endclass + class ExtendBarBaz extends Bar #(Baz); + function int get_x; + return super.get_x(); + endfunction + function int get_8; + return 2 * get_4(); + endfunction + endclass - class ExtendExtendBar extends ExtendBar; - function int get_12; - return 4 * get_3(); - endfunction - endclass + class ExtendExtendBar extends ExtendBar; + function int get_12; + return 4 * get_3(); + endfunction + endclass - class FooDict; - Foo q[int]; - endclass + class FooDict; + Foo q[int]; + endclass - class ExtendFooDict#(type BASE=FooDict) extends BASE; - function int get_x_of_item(int i); - return q[i].x; - endfunction - function int get_y_of_item(int i); - return q[i].get_foo().get_y(); - endfunction - endclass + class ExtendFooDict #( + type BASE = FooDict + ) extends BASE; + function int get_x_of_item(int i); + return q[i].x; + endfunction + function int get_y_of_item(int i); + return q[i].get_foo().get_y(); + endfunction + endclass - Bar #() bar_foo_i; - Bar #(Baz) bar_baz_i; - ExtendBar extend_bar_i; - ExtendBar1 extend_bar1_i; - ExtendBarBaz extend_bar_baz_i; - ExtendExtendBar extend_extend_bar_i; - ExtendFooDict extend_foo_dict_i; + Bar #() bar_foo_i; + Bar #(Baz) bar_baz_i; + ExtendBar extend_bar_i; + ExtendBar1 extend_bar1_i; + ExtendBarBaz extend_bar_baz_i; + ExtendExtendBar extend_extend_bar_i; + ExtendFooDict extend_foo_dict_i; - initial begin - bar_foo_i = new; - bar_baz_i = new; - extend_bar_i = new; - extend_bar1_i = new; - extend_bar_baz_i = new; - extend_extend_bar_i = new; - extend_foo_dict_i = new; - extend_foo_dict_i.q[1] = new; + initial begin + bar_foo_i = new; + bar_baz_i = new; + extend_bar_i = new; + extend_bar1_i = new; + extend_bar_baz_i = new; + extend_extend_bar_i = new; + extend_foo_dict_i = new; + extend_foo_dict_i.q[1] = new; - if (bar_foo_i.get_x() != 1) $stop; - if (bar_foo_i.get_3() != 3) $stop; - if (bar_foo_i.get_foo().get_y() != 10) $stop; - if (bar_foo_i.get_foo().get_30() != 30) $stop; - if (bar_baz_i.get_x() != 2) $stop; - if (bar_baz_i.get_4() != 4) $stop; - if (bar_baz_i.get_foo().get_y() != 20) $stop; - if (bar_baz_i.get_foo().get_40() != 40) $stop; - if (extend_bar_i.get_x() != 1) $stop; - if (extend_bar_i.get_6() != 6) $stop; - if (extend_bar_i.get_x() != 1) $stop; - if (extend_bar_i.get_6() != 6) $stop; - if (extend_bar1_i.get_x() != 1) $stop; - if (extend_bar1_i.get_6() != 6) $stop; - if (extend_bar_baz_i.get_x() != 2) $stop; - if (extend_bar_baz_i.get_8() != 8) $stop; - if (extend_extend_bar_i.get_x() != 1) $stop; - if (extend_extend_bar_i.get_12() != 12) $stop; - if (extend_foo_dict_i.get_x_of_item(1) != 1) $stop; - if (extend_foo_dict_i.get_y_of_item(1) != 10) $stop; + if (bar_foo_i.get_x() != 1) $stop; + if (bar_foo_i.get_3() != 3) $stop; + if (bar_foo_i.get_foo().get_y() != 10) $stop; + if (bar_foo_i.get_foo().get_30() != 30) $stop; + if (bar_baz_i.get_x() != 2) $stop; + if (bar_baz_i.get_4() != 4) $stop; + if (bar_baz_i.get_foo().get_y() != 20) $stop; + if (bar_baz_i.get_foo().get_40() != 40) $stop; + if (extend_bar_i.get_x() != 1) $stop; + if (extend_bar_i.get_6() != 6) $stop; + if (extend_bar_i.get_x() != 1) $stop; + if (extend_bar_i.get_6() != 6) $stop; + if (extend_bar1_i.get_x() != 1) $stop; + if (extend_bar1_i.get_6() != 6) $stop; + if (extend_bar_baz_i.get_x() != 2) $stop; + if (extend_bar_baz_i.get_8() != 8) $stop; + if (extend_extend_bar_i.get_x() != 1) $stop; + if (extend_extend_bar_i.get_12() != 12) $stop; + if (extend_foo_dict_i.get_x_of_item(1) != 1) $stop; + if (extend_foo_dict_i.get_y_of_item(1) != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_param_unused.v b/test_regress/t/t_class_extends_param_unused.v index 6545002a0..3c1e9c7a6 100644 --- a/test_regress/t/t_class_extends_param_unused.v +++ b/test_regress/t/t_class_extends_param_unused.v @@ -4,12 +4,14 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Foo#(type T = logic) extends T; +class Foo #( + type T = logic +) extends T; endclass module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_rec_bad.v b/test_regress/t/t_class_extends_rec_bad.v index 10d916b50..1828078c1 100644 --- a/test_regress/t/t_class_extends_rec_bad.v +++ b/test_regress/t/t_class_extends_rec_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 class RecursiveExtCls extends RecursiveExtCls; - int i; + int i; endclass module t; - RecursiveExtCls cls = new; + RecursiveExtCls cls = new; endmodule diff --git a/test_regress/t/t_class_extends_this.v b/test_regress/t/t_class_extends_this.v index e36fe398a..df209699a 100644 --- a/test_regress/t/t_class_extends_this.v +++ b/test_regress/t/t_class_extends_this.v @@ -7,73 +7,73 @@ typedef class Cls; class Base; - class BaseInner; - int value = 10; - function void test; - if (value != 10) $stop; - if (this.value != 10) $stop; - value = 20; - if (value != 20) $stop; - this.value = 30; - if (value != 30) $stop; - endfunction - endclass + class BaseInner; + int value = 10; + function void test; + if (value != 10) $stop; + if (this.value != 10) $stop; + value = 20; + if (value != 20) $stop; + this.value = 30; + if (value != 30) $stop; + endfunction + endclass - int value = 1; - BaseInner inner = new; - function void test; - if (value != 1) $stop; - if (this.value != 1) $stop; - value = 2; - if (value != 2) $stop; - this.value = 3; - if (value != 3) $stop; - endfunction + int value = 1; + BaseInner inner = new; + function void test; + if (value != 1) $stop; + if (this.value != 1) $stop; + value = 2; + if (value != 2) $stop; + this.value = 3; + if (value != 3) $stop; + endfunction endclass class Cls extends Base; - class BaseInner extends Base::BaseInner; - int value = 100; - function void test; - if (value != 100) $stop; - if (this.value != 100) $stop; - if (super.value != 10) $stop; - super.test(); - if (value != 100) $stop; - if (this.value != 100) $stop; - if (super.value != 30) $stop; - value = 200; - if (value != 200) $stop; - this.value = 300; - if (value != 300) $stop; - endfunction - endclass - - int value = 20; - BaseInner inner = new; - function void test; - if (value != 20) $stop; - if (this.value != 20) $stop; - if (super.value != 1) $stop; - + class BaseInner extends Base::BaseInner; + int value = 100; + function void test; + if (value != 100) $stop; + if (this.value != 100) $stop; + if (super.value != 10) $stop; super.test(); - if (this.value != 20) $stop; + if (value != 100) $stop; + if (this.value != 100) $stop; + if (super.value != 30) $stop; + value = 200; + if (value != 200) $stop; + this.value = 300; + if (value != 300) $stop; + endfunction + endclass - super.value = 9; - this.value = 29; - if (super.value != 9) $stop; - if (value != 29) $stop; + int value = 20; + BaseInner inner = new; + function void test; + if (value != 20) $stop; + if (this.value != 20) $stop; + if (super.value != 1) $stop; - inner.test(); - endfunction + super.test(); + if (this.value != 20) $stop; + + super.value = 9; + this.value = 29; + if (super.value != 9) $stop; + if (value != 29) $stop; + + inner.test(); + endfunction endclass module t; - initial begin - Cls c; - c = new; - c.test(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c = new; + c.test(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_this3.v b/test_regress/t/t_class_extends_this3.v index e00f279a1..9860a24e0 100644 --- a/test_regress/t/t_class_extends_this3.v +++ b/test_regress/t/t_class_extends_this3.v @@ -7,35 +7,35 @@ typedef class Cls; class Base; - class Inner; - int value = 10; - function void testBaseInner; - if (value != 10) $stop; - endfunction - endclass - int value = 1; - Inner inner = new; - function void testBase; - if (value != 1) $stop; - if (inner.value != 10) $stop; - endfunction + class Inner; + int value = 10; + function void testBaseInner; + if (value != 10) $stop; + endfunction + endclass + int value = 1; + Inner inner = new; + function void testBase; + if (value != 1) $stop; + if (inner.value != 10) $stop; + endfunction endclass class Cls extends Base; - function void testDerived; - if (value != 1) $stop; - if (inner.value != 10) $stop; - endfunction + function void testDerived; + if (value != 1) $stop; + if (inner.value != 10) $stop; + endfunction endclass module t; - initial begin - Cls c; - c = new; - c.testBase(); - c.testDerived(); - c.inner.testBaseInner(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c = new; + c.testBase(); + c.testDerived(); + c.inner.testBaseInner(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_extends_vsyment.v b/test_regress/t/t_class_extends_vsyment.v index 343780d2e..b7303646f 100644 --- a/test_regress/t/t_class_extends_vsyment.v +++ b/test_regress/t/t_class_extends_vsyment.v @@ -8,8 +8,8 @@ class Foo; endclass class Bar extends Foo; - int m_field = get_1(); - function int get_1(); - return 1; - endfunction + int m_field = get_1(); + function int get_1(); + return 1; + endfunction endclass diff --git a/test_regress/t/t_class_extern.v b/test_regress/t/t_class_extern.v index 15ac405ac..506b91327 100644 --- a/test_regress/t/t_class_extern.v +++ b/test_regress/t/t_class_extern.v @@ -5,104 +5,104 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int value; - extern function int ext_f_np; - extern function int ext_f_p(); - extern function int ext_f_i(int in); - extern function ext_f_imp(in); - extern static function int get_1(); - extern task ext_t_np; - extern task ext_t_p(); - extern task ext_t_i(int in); - class SubCls; - int value; - extern function int ext_f_np; - extern function int ext_f_p(); - extern function int ext_f_i(int in); - extern static function int get_10(); - extern task ext_t_np; - extern task ext_t_p(); - extern task ext_t_i(int in); - endclass + int value; + extern function int ext_f_np; + extern function int ext_f_p(); + extern function int ext_f_i(int in); + extern function ext_f_imp(in); + extern static function int get_1(); + extern task ext_t_np; + extern task ext_t_p(); + extern task ext_t_i(int in); + class SubCls; + int value; + extern function int ext_f_np; + extern function int ext_f_p(); + extern function int ext_f_i(int in); + extern static function int get_10(); + extern task ext_t_np; + extern task ext_t_p(); + extern task ext_t_i(int in); + endclass endclass function int Cls::ext_f_np; - return 1; + return 1; endfunction function int Cls::ext_f_p(); - return value; + return value; endfunction function int Cls::ext_f_i(int in); - return in+1; + return in+1; endfunction function Cls::ext_f_imp(in); - return ~in; + return ~in; endfunction function int Cls::get_1(); - return 1; + return 1; endfunction task Cls::ext_t_np(); - $write("*-* All Finished *-*\n"); + $write("*-* All Finished *-*\n"); endtask task Cls::ext_t_p(); - $finish; + $finish; endtask task Cls::ext_t_i(int in); - if (in != 2) $stop; - value = in; + if (in != 2) $stop; + value = in; endtask function int Cls::SubCls::ext_f_np; - return 10; + return 10; endfunction function int Cls::SubCls::ext_f_p(); - return value; + return value; endfunction function int Cls::SubCls::ext_f_i(int in); - return in+10; + return in+10; endfunction function int Cls::SubCls::get_10(); - return 10; + return 10; endfunction task Cls::SubCls::ext_t_np(); - $write("Cls::SubCls::ext_t_np\n"); + $write("Cls::SubCls::ext_t_np\n"); endtask task Cls::SubCls::ext_t_p(); - $write("Cls::SubCls::ext_t_p\n"); + $write("Cls::SubCls::ext_t_p\n"); endtask task Cls::SubCls::ext_t_i(int in); - if (in != 20) $stop; - value = in; + if (in != 20) $stop; + value = in; endtask module t; - initial begin - automatic Cls c = new; - automatic Cls::SubCls subc = new; - c.ext_t_i(2); - if (c.ext_f_np() != 1) $stop; - if (c.ext_f_p() != 2) $stop; - if (c.ext_f_i(10) != 11) $stop; - if (c.ext_f_imp(1'b1) != 1'b0) $stop; - if (Cls::get_1() != 1) $stop; - subc.ext_t_i(20); - if (subc.ext_f_np() != 10) $stop; - if (subc.ext_f_p() != 20) $stop; - if (subc.ext_f_i(11) != 21) $stop; - if (Cls::SubCls::get_10() != 10) $stop; - subc.ext_t_np(); - subc.ext_t_p(); - c.ext_t_np(); - c.ext_t_p(); - end + initial begin + automatic Cls c = new; + automatic Cls::SubCls subc = new; + c.ext_t_i(2); + if (c.ext_f_np() != 1) $stop; + if (c.ext_f_p() != 2) $stop; + if (c.ext_f_i(10) != 11) $stop; + if (c.ext_f_imp(1'b1) != 1'b0) $stop; + if (Cls::get_1() != 1) $stop; + subc.ext_t_i(20); + if (subc.ext_f_np() != 10) $stop; + if (subc.ext_f_p() != 20) $stop; + if (subc.ext_f_i(11) != 21) $stop; + if (Cls::SubCls::get_10() != 10) $stop; + subc.ext_t_np(); + subc.ext_t_p(); + c.ext_t_np(); + c.ext_t_p(); + end endmodule diff --git a/test_regress/t/t_class_field_name.v b/test_regress/t/t_class_field_name.v index 96e575836..7a83f0c78 100644 --- a/test_regress/t/t_class_field_name.v +++ b/test_regress/t/t_class_field_name.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int queue; + int queue; endclass module t; - initial begin - automatic Cls cls = new; - cls.queue = 1; - if (cls.queue == 1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + automatic Cls cls = new; + cls.queue = 1; + if (cls.queue == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_class_forward.v b/test_regress/t/t_class_forward.v index 590187350..081f20229 100644 --- a/test_regress/t/t_class_forward.v +++ b/test_regress/t/t_class_forward.v @@ -5,36 +5,36 @@ // SPDX-License-Identifier: CC0-1.0 package P; - typedef class ClsB; -class ClsA; - int imembera; - ClsB b; -endclass -class ClsB; - int imemberb; - ClsA a; -endclass + typedef class ClsB; + class ClsA; + int imembera; + ClsB b; + endclass + class ClsB; + int imemberb; + ClsA a; + endclass endpackage module t; - P::ClsA ca; - P::ClsB cb; - initial begin - // Alternate between two versions to make sure we don't - // constant propagate between them. - ca = new; - cb = new; - ca.b = new; - cb.a = new; - ca.imembera = 100; - ca.b.imemberb = 111; - cb.imemberb = 200; - cb.a.imembera = 202; - if (ca.imembera != 100) $stop; - if (ca.b.imemberb != 111) $stop; - if (cb.imemberb != 200) $stop; - if (cb.a.imembera != 202) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + P::ClsA ca; + P::ClsB cb; + initial begin + // Alternate between two versions to make sure we don't + // constant propagate between them. + ca = new; + cb = new; + ca.b = new; + cb.a = new; + ca.imembera = 100; + ca.b.imemberb = 111; + cb.imemberb = 200; + cb.a.imembera = 202; + if (ca.imembera != 100) $stop; + if (ca.b.imemberb != 111) $stop; + if (cb.imemberb != 200) $stop; + if (cb.a.imembera != 202) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_func_arg_unused.v b/test_regress/t/t_class_func_arg_unused.v index 5a31df2d7..6ee0fad71 100644 --- a/test_regress/t/t_class_func_arg_unused.v +++ b/test_regress/t/t_class_func_arg_unused.v @@ -6,24 +6,24 @@ package uvm_pkg; -class uvm_reg_field; // extends uvm_object; - function void configure(bit overde, bit is_rand); + class uvm_reg_field; // extends uvm_object; + function void configure(bit overde, bit is_rand); if (overde) is_rand = 0; - if (!is_rand) ; // value.rand_mode(0); + if (!is_rand); // value.rand_mode(0); // See issue #4567 - endfunction -endclass + endfunction + endclass endpackage module t; - initial begin - automatic uvm_pkg::uvm_reg_field c = new; - c.configure(1, 0); - c.configure(0, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic uvm_pkg::uvm_reg_field c = new; + c.configure(1, 0); + c.configure(0, 0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_func_dot.v b/test_regress/t/t_class_func_dot.v index 8594b8d43..d355f29e3 100644 --- a/test_regress/t/t_class_func_dot.v +++ b/test_regress/t/t_class_func_dot.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 class Cls_report_object; - string m_msg; - function string get_msg; - return m_msg; - endfunction + string m_msg; + function string get_msg; + return m_msg; + endfunction endclass function Cls_report_object get_report_object; - Cls_report_object c; - c = new; - c.m_msg = "hello"; - return c; + Cls_report_object c; + c = new; + c.m_msg = "hello"; + return c; endfunction module t; - string s; + string s; - initial begin - Cls_report_object _local_report_object; - s = get_report_object().get_msg(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls_report_object _local_report_object; + s = get_report_object().get_msg(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_func_nvoid_bad.out b/test_regress/t/t_class_func_nvoid_bad.out index 3c2fa409b..25b8784d1 100644 --- a/test_regress/t/t_class_func_nvoid_bad.out +++ b/test_regress/t/t_class_func_nvoid_bad.out @@ -1,26 +1,26 @@ -%Error: t/t_class_func_nvoid_bad.v:47:11: Cannot call a task/void-function as a function: 'mod_fv' - : ... note: In instance 't' - 47 | if (mod_fv() == 10) $stop; - | ^~~~~~ +%Error: t/t_class_func_nvoid_bad.v:47:9: Cannot call a task/void-function as a function: 'mod_fv' + : ... note: In instance 't' + 47 | if (mod_fv() == 10) $stop; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_func_nvoid_bad.v:50:11: Cannot call a task/void-function as a function: 'mod_t' +%Error: t/t_class_func_nvoid_bad.v:50:9: Cannot call a task/void-function as a function: 'mod_t' + : ... note: In instance 't' + 50 | if (mod_t() == 10) $stop; + | ^~~~~ +%Error: t/t_class_func_nvoid_bad.v:58:11: Cannot call a task/void-function as a member function: 'fv' : ... note: In instance 't' - 50 | if (mod_t() == 10) $stop; - | ^~~~~ -%Error: t/t_class_func_nvoid_bad.v:58:13: Cannot call a task/void-function as a member function: 'fv' + 58 | if (c.fv() == 10) $stop; + | ^~ +%Error: t/t_class_func_nvoid_bad.v:61:11: Cannot call a task/void-function as a member function: 't' : ... note: In instance 't' - 58 | if (c.fv() == 10) $stop; - | ^~ -%Error: t/t_class_func_nvoid_bad.v:61:13: Cannot call a task/void-function as a member function: 't' + 61 | if (c.t() == 10) $stop; + | ^ +%Error: t/t_class_func_nvoid_bad.v:69:11: Cannot call a task/void-function as a function: 'sfv' : ... note: In instance 't' - 61 | if (c.t() == 10) $stop; - | ^ -%Error: t/t_class_func_nvoid_bad.v:69:13: Cannot call a task/void-function as a function: 'sfv' + 69 | if (c.sfv() == 10) $stop; + | ^~~ +%Error: t/t_class_func_nvoid_bad.v:72:11: Cannot call a task/void-function as a function: 'st' : ... note: In instance 't' - 69 | if (c.sfv() == 10) $stop; - | ^~~ -%Error: t/t_class_func_nvoid_bad.v:72:13: Cannot call a task/void-function as a function: 'st' - : ... note: In instance 't' - 72 | if (c.st() == 10) $stop; - | ^~ + 72 | if (c.st() == 10) $stop; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_class_func_nvoid_bad.v b/test_regress/t/t_class_func_nvoid_bad.v index b693c29b6..21c1aa01e 100644 --- a/test_regress/t/t_class_func_nvoid_bad.v +++ b/test_regress/t/t_class_func_nvoid_bad.v @@ -6,71 +6,71 @@ class Cls; - function int fi(); - return 10; - endfunction - function void fv(); - endfunction - task t(); - endtask - static function int sfi(); - return 10; - endfunction - static function void sfv(); - endfunction - static task st(); - endtask + function int fi(); + return 10; + endfunction + function void fv(); + endfunction + task t(); + endtask + static function int sfi(); + return 10; + endfunction + static function void sfv(); + endfunction + static task st(); + endtask endclass module t; - function int mod_fi(); - return 10; - endfunction - function void mod_fv(); - endfunction - task mod_t(); - endtask + function int mod_fi(); + return 10; + endfunction + function void mod_fv(); + endfunction + task mod_t(); + endtask - initial begin - Cls c; - c = new; + initial begin + Cls c; + c = new; - // For test of calling function in void context, see t_func_void_bad.v + // For test of calling function in void context, see t_func_void_bad.v - // Module - if (mod_fi() != 10) $stop; // OK - void'(mod_fi()); // OK + // Module + if (mod_fi() != 10) $stop; // OK + void'(mod_fi()); // OK - mod_fv(); // Warn IGNOREDRETURN - void'(mod_fv()); // OK - if (mod_fv() == 10) $stop; // Bad call of task as function + mod_fv(); // Warn IGNOREDRETURN + void'(mod_fv()); // OK + if (mod_fv() == 10) $stop; // Bad call of task as function - mod_t(); // OK - if (mod_t() == 10) $stop; // Bad call of task as function + mod_t(); // OK + if (mod_t() == 10) $stop; // Bad call of task as function - // Member functions - if (c.fi() != 10) $stop; // OK - void'(c.fi()); // OK + // Member functions + if (c.fi() != 10) $stop; // OK + void'(c.fi()); // OK - c.fv(); // Ok - void'(c.fv()); // OK - if (c.fv() == 10) $stop; // Bad + c.fv(); // Ok + void'(c.fv()); // OK + if (c.fv() == 10) $stop; // Bad - c.t(); // OK - if (c.t() == 10) $stop; // Bad + c.t(); // OK + if (c.t() == 10) $stop; // Bad - // Static member functions - if (c.sfi() != 10) $stop; // OK - void'(c.sfi()); // OK + // Static member functions + if (c.sfi() != 10) $stop; // OK + void'(c.sfi()); // OK - c.sfv(); // Ok - void'(c.sfv()); // OK - if (c.sfv() == 10) $stop; // Bad + c.sfv(); // Ok + void'(c.sfv()); // OK + if (c.sfv() == 10) $stop; // Bad - c.st(); // OK - if (c.st() == 10) $stop; // Bad + c.st(); // OK + if (c.st() == 10) $stop; // Bad - $stop; - end + $stop; + end endmodule diff --git a/test_regress/t/t_class_fwd_cc.v b/test_regress/t/t_class_fwd_cc.v index c5ed2db27..ad49cda2c 100644 --- a/test_regress/t/t_class_fwd_cc.v +++ b/test_regress/t/t_class_fwd_cc.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef class Fwd; - virtual class Virt; - pure virtual function Fwd get_root(); - endclass - class Ext extends Virt; - virtual function Fwd get_root(); - return Fwd::m_uvm_get_root(); - endfunction - endclass - class Fwd; - static function Fwd m_uvm_get_root(); - return null; - endfunction - endclass + typedef class Fwd; + virtual class Virt; + pure virtual function Fwd get_root(); + endclass + class Ext extends Virt; + virtual function Fwd get_root(); + return Fwd::m_uvm_get_root(); + endfunction + endclass + class Fwd; + static function Fwd m_uvm_get_root(); + return null; + endfunction + endclass endpackage diff --git a/test_regress/t/t_class_if_assign.v b/test_regress/t/t_class_if_assign.v index cfa9226d4..f6e64b96d 100644 --- a/test_regress/t/t_class_if_assign.v +++ b/test_regress/t/t_class_if_assign.v @@ -5,39 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int x; - function new; - x = 1; - endfunction + int x; + function new; + x = 1; + endfunction endclass class ExtendCls extends Cls; - function new; - x = 2; - endfunction + function new; + x = 2; + endfunction endclass class AnotherExtendCls extends Cls; - function new; - x = 3; - endfunction + function new; + x = 3; + endfunction endclass module t; - initial begin - automatic Cls cls = new; - automatic ExtendCls ext_cls = new; - automatic AnotherExtendCls an_ext_cls = new; + initial begin + automatic Cls cls = new; + automatic ExtendCls ext_cls = new; + automatic AnotherExtendCls an_ext_cls = new; - if (cls.x == 1) cls = ext_cls; - else cls = an_ext_cls; - if (cls.x != 2) $stop; + if (cls.x == 1) cls = ext_cls; + else cls = an_ext_cls; + if (cls.x != 2) $stop; - if (cls.x == 1) cls = ext_cls; - else cls = an_ext_cls; - if (cls.x != 3) $stop; + if (cls.x == 1) cls = ext_cls; + else cls = an_ext_cls; + if (cls.x != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_imp2.v b/test_regress/t/t_class_imp2.v index 92be1b878..2b49d681c 100644 --- a/test_regress/t/t_class_imp2.v +++ b/test_regress/t/t_class_imp2.v @@ -6,42 +6,42 @@ module t; - interface class Courier; - pure virtual function void deliver(); - endclass - class Person implements Courier; - virtual function void deliver(); - $display("slow delivery"); - endfunction - endclass + interface class Courier; + pure virtual function void deliver(); + endclass + class Person implements Courier; + virtual function void deliver(); + $display("slow delivery"); + endfunction + endclass - interface class Seats; - pure virtual function int seats(); - endclass + interface class Seats; + pure virtual function int seats(); + endclass - class Vehicle; - endclass + class Vehicle; + endclass - class Car extends Vehicle implements Courier, Seats; - virtual function void deliver(); - $display("fast delivery"); - endfunction - virtual function int seats(); return 4; endfunction - endclass + class Car extends Vehicle implements Courier, Seats; + virtual function void deliver(); + $display("fast delivery"); + endfunction + virtual function int seats(); return 4; endfunction + endclass - class MetaCar extends Car; - endclass + class MetaCar extends Car; + endclass - function void do_delivery(Courier courier); - courier.deliver(); - endfunction + function void do_delivery(Courier courier); + courier.deliver(); + endfunction - initial begin - MetaCar car; - car = new(); - do_delivery(car); - if (car.seats() != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + MetaCar car; + car = new(); + do_delivery(car); + if (car.seats() != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_inc.v b/test_regress/t/t_class_inc.v index 3c5a59c58..3420f428c 100644 --- a/test_regress/t/t_class_inc.v +++ b/test_regress/t/t_class_inc.v @@ -4,34 +4,38 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class Base #(type T = integer); - T m_count; +class Base #( + type T = integer +); + T m_count; - function void test1(); - if (this.m_count != 0) $stop; - if (this.m_count++ != 0) $stop; - if (this.m_count != 1) $stop; - if (m_count++ != 1) $stop; - if (this.m_count != 2) $stop; - endfunction + function void test1(); + if (this.m_count != 0) $stop; + if (this.m_count++ != 0) $stop; + if (this.m_count != 1) $stop; + if (m_count++ != 1) $stop; + if (this.m_count != 2) $stop; + endfunction endclass -class Cls #(type T = integer) extends Base #(T); +class Cls #( + type T = integer +) extends Base #(T); endclass module t; - Cls #(int) c; + Cls #(int) c; - initial begin - c = new; - c.test1(); + initial begin + c = new; + c.test1(); - c.m_count = 0; - if (c.m_count != 0) $stop; - if (c.m_count++ != 0) $stop; - if (c.m_count != 1) $stop; + c.m_count = 0; + if (c.m_count != 0) $stop; + if (c.m_count++ != 0) $stop; + if (c.m_count != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_link_delay.v b/test_regress/t/t_class_link_delay.v index 834031c92..92efb225c 100644 --- a/test_regress/t/t_class_link_delay.v +++ b/test_regress/t/t_class_link_delay.v @@ -4,49 +4,47 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - (/*AUTOARG*/ - // Outputs - someOutput, - // Inputs - clk, reset_l, InOne, InTwo - ); +module t ( /*AUTOARG*/ + // Outputs + someOutput, + // Inputs + clk, + reset_l, + InOne, + InTwo +); - input clk; - input reset_l; - input InOne, InTwo; - output logic someOutput; + input clk; + input reset_l; + input InOne, InTwo; + output logic someOutput; - typedef enum { - STATE_ONE, - STATE_TWO, - STATE_THREE, - STATE_FOUR - } some_state_t; + typedef enum { + STATE_ONE, + STATE_TWO, + STATE_THREE, + STATE_FOUR + } some_state_t; - some_state_t some_FSM; + some_state_t some_FSM; - always_ff @ (posedge clk or negedge reset_l) begin - if(!reset_l) - some_FSM <= some_FSM.first; - else begin - unique case (some_FSM) - STATE_ONE, STATE_TWO, STATE_THREE: begin - if(InOne & InTwo) - some_FSM <= some_FSM.next; - else if(InOne) - some_FSM <= some_FSM; - else - some_FSM <= some_FSM.first; - end - default: begin - some_FSM <= STATE_ONE; - end - endcase - end - end + always_ff @(posedge clk or negedge reset_l) begin + if (!reset_l) some_FSM <= some_FSM.first; + else begin + unique case (some_FSM) + STATE_ONE, STATE_TWO, STATE_THREE: begin + if (InOne & InTwo) some_FSM <= some_FSM.next; + else if (InOne) some_FSM <= some_FSM; + else some_FSM <= some_FSM.first; + end + default: begin + some_FSM <= STATE_ONE; + end + endcase + end + end - always_comb begin - someOutput = (some_FSM == STATE_FOUR); - end + always_comb begin + someOutput = (some_FSM == STATE_FOUR); + end endmodule diff --git a/test_regress/t/t_class_local.v b/test_regress/t/t_class_local.v index e9cb4ae9a..0785f5d78 100644 --- a/test_regress/t/t_class_local.v +++ b/test_regress/t/t_class_local.v @@ -5,18 +5,65 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - typedef enum {A = 10, B = 20, C = 30} en_t; + typedef enum { + A = 10, + B = 20, + C = 30 + } en_t; - int m_pub = 1; - local int m_loc = 2; - protected int m_prot = B; - task f_pub; endtask - local task f_loc; endtask - protected task f_prot; endtask - static task s_pub; endtask - static local task s_loc; endtask - static protected task s_prot; endtask - task check; + int m_pub = 1; + local int m_loc = 2; + protected int m_prot = B; + task f_pub; + endtask + local task f_loc; + endtask + protected task f_prot; + endtask + static task s_pub; + endtask + static local task s_loc; + endtask + static protected task s_prot; + endtask + task check; + Cls o; + if (m_pub != 1) $stop; + if (m_loc != 2) $stop; + if (m_prot != 20) $stop; + f_pub(); // Ok + f_loc(); // Ok + f_prot(); // Ok + s_pub(); // Ok + s_loc(); // Ok + s_prot(); // Ok + Cls::s_pub(); // Ok + Cls::s_loc(); // Ok + Cls::s_prot(); // Ok + endtask + class InnerCls; + typedef enum { + A = 10, + B = 20, + C = 30 + } en_t; + + int m_pub = 1; + local int m_loc = 2; + protected int m_prot = B; + task f_pub; + endtask + local task f_loc; + endtask + protected task f_prot; + endtask + static task s_pub; + endtask + static local task s_loc; + endtask + static protected task s_prot; + endtask + task check; Cls o; if (m_pub != 1) $stop; if (m_loc != 2) $stop; @@ -30,96 +77,69 @@ class Cls; Cls::s_pub(); // Ok Cls::s_loc(); // Ok Cls::s_prot(); // Ok - endtask - class InnerCls; - typedef enum {A = 10, B = 20, C = 30} en_t; - - int m_pub = 1; - local int m_loc = 2; - protected int m_prot = B; - task f_pub; endtask - local task f_loc; endtask - protected task f_prot; endtask - static task s_pub; endtask - static local task s_loc; endtask - static protected task s_prot; endtask - task check; - Cls o; - if (m_pub != 1) $stop; - if (m_loc != 2) $stop; - if (m_prot != 20) $stop; - f_pub(); // Ok - f_loc(); // Ok - f_prot(); // Ok - s_pub(); // Ok - s_loc(); // Ok - s_prot(); // Ok - Cls::s_pub(); // Ok - Cls::s_loc(); // Ok - Cls::s_prot(); // Ok - endtask - endclass + endtask + endclass endclass class Ext extends Cls; - task check; + task check; + if (m_pub != 1) $stop; + if (m_prot != 20) $stop; + f_pub(); // Ok + f_prot(); // Ok + s_pub(); // Ok + s_prot(); // Ok + Cls::s_pub(); // Ok + Cls::s_prot(); // Ok + endtask + class ExtInner extends Cls::InnerCls; + task check; if (m_pub != 1) $stop; if (m_prot != 20) $stop; f_pub(); // Ok f_prot(); // Ok s_pub(); // Ok s_prot(); // Ok - Cls::s_pub(); // Ok - Cls::s_prot(); // Ok - endtask - class ExtInner extends Cls::InnerCls; - task check; - if (m_pub != 1) $stop; - if (m_prot != 20) $stop; - f_pub(); // Ok - f_prot(); // Ok - s_pub(); // Ok - s_prot(); // Ok - Cls::InnerCls::s_pub(); // Ok - Cls::InnerCls::s_prot(); // Ok - endtask - endclass + Cls::InnerCls::s_pub(); // Ok + Cls::InnerCls::s_prot(); // Ok + endtask + endclass endclass module t; - const Cls mod_c = new; - const Cls::InnerCls imod_c = new; + const Cls mod_c = new; + const Cls::InnerCls imod_c = new; - initial begin - Cls c; - Cls::InnerCls i; - Ext e; - Ext::ExtInner ei; - if (c.A != 10) $stop; - if (i.A != 10) $stop; - c = new; - i = new; - e = new; - ei = new; - if (c.m_pub != 1) $stop; - if (i.m_pub != 1) $stop; - // - if (mod_c.A != 10) $stop; - if (imod_c.A != 10) $stop; - // - c.check(); - i.check(); - e.check(); - ei.check(); - // - Cls::s_pub(); // Ok - Cls::InnerCls::s_pub(); // Ok - c.s_pub(); // Ok - i.s_pub(); // Ok - e.s_pub(); // Ok - ei.s_pub(); // Ok - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + Cls::InnerCls i; + Ext e; + Ext::ExtInner ei; + if (c.A != 10) $stop; + if (i.A != 10) $stop; + c = new; + i = new; + e = new; + ei = new; + if (c.m_pub != 1) $stop; + if (i.m_pub != 1) $stop; + // + if (mod_c.A != 10) $stop; + if (imod_c.A != 10) $stop; + // + c.check(); + i.check(); + e.check(); + ei.check(); + // + Cls::s_pub(); // Ok + Cls::InnerCls::s_pub(); // Ok + c.s_pub(); // Ok + i.s_pub(); // Ok + e.s_pub(); // Ok + ei.s_pub(); // Ok + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_local_bad.out b/test_regress/t/t_class_local_bad.out index 672942d32..66b5663a0 100644 --- a/test_regress/t/t_class_local_bad.out +++ b/test_regress/t/t_class_local_bad.out @@ -1,107 +1,107 @@ -%Error-ENCAPSULATED: t/t_class_local_bad.v:71:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) +%Error-ENCAPSULATED: t/t_class_local_bad.v:72:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 71 | bad(); if (c.m_loc != 2) $stop; - | ^~~~~ - t/t_class_local_bad.v:71:20: ... Location of definition - 15 | local int m_loc = 2; - | ^~~~~ - ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest -%Error-ENCAPSULATED: t/t_class_local_bad.v:72:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 72 | bad(); if (c.m_prot != 20) $stop; - | ^~~~~~ - t/t_class_local_bad.v:72:20: ... Location of definition - 16 | protected int m_prot = 3; - | ^~~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:74:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 74 | bad(); if (e.m_loc != 2) $stop; - | ^~~~~ - t/t_class_local_bad.v:74:20: ... Location of definition - 15 | local int m_loc = 2; - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:75:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 75 | bad(); if (e.m_prot != 20) $stop; - | ^~~~~~ - t/t_class_local_bad.v:75:20: ... Location of definition - 16 | protected int m_prot = 3; - | ^~~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:77:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 77 | bad(); c.f_loc(); - | ^~~~~ - t/t_class_local_bad.v:77:16: ... Location of definition - 18 | local task f_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:78:16: 'f_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 78 | bad(); c.f_prot(); - | ^~~~~~ - t/t_class_local_bad.v:78:16: ... Location of definition - 19 | protected task f_prot; endtask - | ^~~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:80:16: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 80 | bad(); c.s_loc(); - | ^~~~~ - t/t_class_local_bad.v:80:16: ... Location of definition - 21 | static local task s_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:81:16: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 81 | bad(); c.s_prot(); - | ^~~~~~ - t/t_class_local_bad.v:81:16: ... Location of definition - 22 | static protected task s_prot; endtask - | ^~~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:83:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 83 | bad(); Cls::s_loc(); - | ^~~~~ - t/t_class_local_bad.v:83:19: ... Location of definition - 21 | static local task s_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:84:19: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 84 | bad(); Cls::s_prot(); - | ^~~~~~ - t/t_class_local_bad.v:84:19: ... Location of definition - 22 | static protected task s_prot; endtask - | ^~~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:47:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) - : ... note: In instance 't' - 47 | bad(); if (m_loc != 10) $stop; + 72 | bad(); if (c.m_loc != 2) $stop; | ^~~~~ - t/t_class_local_bad.v:47:18: ... Location of definition - 15 | local int m_loc = 2; - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:50:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + t/t_class_local_bad.v:72:18: ... Location of definition + 16 | local int m_loc = 2; + | ^~~~~ + ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest +%Error-ENCAPSULATED: t/t_class_local_bad.v:73:18: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 50 | bad(); f_loc(); - | ^~~~~ - t/t_class_local_bad.v:50:14: ... Location of definition - 18 | local task f_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:53:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + 73 | bad(); if (c.m_prot != 20) $stop; + | ^~~~~~ + t/t_class_local_bad.v:73:18: ... Location of definition + 17 | protected int m_prot = 3; + | ^~~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:75:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 53 | bad(); o.f_loc(); + 75 | bad(); if (e.m_loc != 2) $stop; + | ^~~~~ + t/t_class_local_bad.v:75:18: ... Location of definition + 16 | local int m_loc = 2; + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:76:18: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 76 | bad(); if (e.m_prot != 20) $stop; + | ^~~~~~ + t/t_class_local_bad.v:76:18: ... Location of definition + 17 | protected int m_prot = 3; + | ^~~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:78:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 78 | bad(); c.f_loc(); + | ^~~~~ + t/t_class_local_bad.v:78:14: ... Location of definition + 19 | local task f_loc; endtask + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:79:14: 'f_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 79 | bad(); c.f_prot(); + | ^~~~~~ + t/t_class_local_bad.v:79:14: ... Location of definition + 20 | protected task f_prot; endtask + | ^~~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:81:14: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 81 | bad(); c.s_loc(); + | ^~~~~ + t/t_class_local_bad.v:81:14: ... Location of definition + 22 | static local task s_loc; endtask + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:82:14: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 82 | bad(); c.s_prot(); + | ^~~~~~ + t/t_class_local_bad.v:82:14: ... Location of definition + 23 | static protected task s_prot; endtask + | ^~~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:84:17: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 84 | bad(); Cls::s_loc(); + | ^~~~~ + t/t_class_local_bad.v:84:17: ... Location of definition + 22 | static local task s_loc; endtask + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:85:17: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 85 | bad(); Cls::s_prot(); + | ^~~~~~ + t/t_class_local_bad.v:85:17: ... Location of definition + 23 | static protected task s_prot; endtask + | ^~~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:48:16: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 48 | bad(); if (m_loc != 10) $stop; | ^~~~~ - t/t_class_local_bad.v:53:16: ... Location of definition - 18 | local task f_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:56:14: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + t/t_class_local_bad.v:48:16: ... Location of definition + 16 | local int m_loc = 2; + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:51:12: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 56 | bad(); s_loc(); + 51 | bad(); f_loc(); + | ^~~~~ + t/t_class_local_bad.v:51:12: ... Location of definition + 19 | local task f_loc; endtask | ^~~~~ - t/t_class_local_bad.v:56:14: ... Location of definition - 21 | static local task s_loc; endtask - | ^~~~~ -%Error-ENCAPSULATED: t/t_class_local_bad.v:59:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) +%Error-ENCAPSULATED: t/t_class_local_bad.v:54:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 59 | bad(); Cls::s_loc(); - | ^~~~~ - t/t_class_local_bad.v:59:19: ... Location of definition - 21 | static local task s_loc; endtask - | ^~~~~ + 54 | bad(); o.f_loc(); + | ^~~~~ + t/t_class_local_bad.v:54:14: ... Location of definition + 19 | local task f_loc; endtask + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:57:12: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 57 | bad(); s_loc(); + | ^~~~~ + t/t_class_local_bad.v:57:12: ... Location of definition + 22 | static local task s_loc; endtask + | ^~~~~ +%Error-ENCAPSULATED: t/t_class_local_bad.v:60:17: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) + : ... note: In instance 't' + 60 | bad(); Cls::s_loc(); + | ^~~~~ + t/t_class_local_bad.v:60:17: ... Location of definition + 22 | static local task s_loc; endtask + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_local_bad.v b/test_regress/t/t_class_local_bad.v index 6af613062..b973ae515 100644 --- a/test_regress/t/t_class_local_bad.v +++ b/test_regress/t/t_class_local_bad.v @@ -10,80 +10,81 @@ endtask task bad; endtask +// verilog_format: off class Cls; - int m_pub = 1; - local int m_loc = 2; - protected int m_prot = 3; - task f_pub; endtask - local task f_loc; endtask - protected task f_prot; endtask - static task s_pub; endtask - static local task s_loc; endtask - static protected task s_prot; endtask - task check; - Cls o; - ok(); if (m_pub != 1) $stop; - ok(); if (m_loc != 10) $stop; - ok(); if (m_prot != 20) $stop; - ok(); f_pub(); - ok(); f_loc(); - ok(); f_prot(); - ok(); o.f_pub(); - ok(); o.f_loc(); - ok(); o.f_prot(); - ok(); s_pub(); - ok(); s_loc(); - ok(); s_prot(); - ok(); Cls::s_pub(); - ok(); Cls::s_loc(); - ok(); Cls::s_prot(); - endtask + int m_pub = 1; + local int m_loc = 2; + protected int m_prot = 3; + task f_pub; endtask + local task f_loc; endtask + protected task f_prot; endtask + static task s_pub; endtask + static local task s_loc; endtask + static protected task s_prot; endtask + task check; + Cls o; + ok(); if (m_pub != 1) $stop; + ok(); if (m_loc != 10) $stop; + ok(); if (m_prot != 20) $stop; + ok(); f_pub(); + ok(); f_loc(); + ok(); f_prot(); + ok(); o.f_pub(); + ok(); o.f_loc(); + ok(); o.f_prot(); + ok(); s_pub(); + ok(); s_loc(); + ok(); s_prot(); + ok(); Cls::s_pub(); + ok(); Cls::s_loc(); + ok(); Cls::s_prot(); + endtask endclass class Ext extends Cls; - task check; - Ext o; - ok(); if (m_pub != 1) $stop; - bad(); if (m_loc != 10) $stop; - ok(); if (m_prot != 20) $stop; - ok(); f_pub(); - bad(); f_loc(); - ok(); f_prot(); - ok(); o.f_pub(); - bad(); o.f_loc(); - ok(); o.f_prot(); - ok(); s_pub(); - bad(); s_loc(); - ok(); s_prot(); - ok(); Cls::s_pub(); - bad(); Cls::s_loc(); - ok(); Cls::s_prot(); - endtask + task check; + Ext o; + ok(); if (m_pub != 1) $stop; + bad(); if (m_loc != 10) $stop; + ok(); if (m_prot != 20) $stop; + ok(); f_pub(); + bad(); f_loc(); + ok(); f_prot(); + ok(); o.f_pub(); + bad(); o.f_loc(); + ok(); o.f_prot(); + ok(); s_pub(); + bad(); s_loc(); + ok(); s_prot(); + ok(); Cls::s_pub(); + bad(); Cls::s_loc(); + ok(); Cls::s_prot(); + endtask endclass module t; - initial begin - Cls c; - Ext e; - c = new; - e = new; - ok(); if (c.m_pub != 1) $stop; - bad(); if (c.m_loc != 2) $stop; - bad(); if (c.m_prot != 20) $stop; - ok(); if (e.m_pub != 1) $stop; - bad(); if (e.m_loc != 2) $stop; - bad(); if (e.m_prot != 20) $stop; - ok(); c.f_pub(); - bad(); c.f_loc(); - bad(); c.f_prot(); - ok(); c.s_pub(); - bad(); c.s_loc(); - bad(); c.s_prot(); - ok(); Cls::s_pub(); - bad(); Cls::s_loc(); - bad(); Cls::s_prot(); - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + Ext e; + c = new; + e = new; + ok(); if (c.m_pub != 1) $stop; + bad(); if (c.m_loc != 2) $stop; + bad(); if (c.m_prot != 20) $stop; + ok(); if (e.m_pub != 1) $stop; + bad(); if (e.m_loc != 2) $stop; + bad(); if (e.m_prot != 20) $stop; + ok(); c.f_pub(); + bad(); c.f_loc(); + bad(); c.f_prot(); + ok(); c.s_pub(); + bad(); c.s_loc(); + bad(); c.s_prot(); + ok(); Cls::s_pub(); + bad(); Cls::s_loc(); + bad(); Cls::s_prot(); + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_local_nested_bad.out b/test_regress/t/t_class_local_nested_bad.out index 8f4b39314..f5116d971 100644 --- a/test_regress/t/t_class_local_nested_bad.out +++ b/test_regress/t/t_class_local_nested_bad.out @@ -1,9 +1,9 @@ -%Error-ENCAPSULATED: t/t_class_local_nested_bad.v:14:22: 'name' is hidden as 'local' within this context (IEEE 1800-2023 8.18) +%Error-ENCAPSULATED: t/t_class_local_nested_bad.v:14:18: 'name' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' - 14 | name = Node::name; - | ^~~~ - t/t_class_local_nested_bad.v:14:22: ... Location of definition - 9 | static local string name; - | ^~~~ + 14 | name = Node::name; + | ^~~~ + t/t_class_local_nested_bad.v:14:18: ... Location of definition + 9 | static local string name; + | ^~~~ ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_local_nested_bad.v b/test_regress/t/t_class_local_nested_bad.v index 5adcc9b2c..2e3b46696 100644 --- a/test_regress/t/t_class_local_nested_bad.v +++ b/test_regress/t/t_class_local_nested_bad.v @@ -5,21 +5,21 @@ // SPDX-License-Identifier: CC0-1.0 class NodeList; - class Node; - static local string name; - endclass + class Node; + static local string name; + endclass - string name; - function new(); - name = Node::name; - endfunction + string name; + function new(); + name = Node::name; + endfunction endclass module t; - initial begin - automatic NodeList n = new; + initial begin + automatic NodeList n = new; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_member_bad.out b/test_regress/t/t_class_member_bad.out index ff345409a..6186ad8ba 100644 --- a/test_regress/t/t_class_member_bad.out +++ b/test_regress/t/t_class_member_bad.out @@ -1,13 +1,13 @@ -%Error: t/t_class_member_bad.v:18:9: Member 'memb3' not found in class 'Cls2' +%Error: t/t_class_member_bad.v:18:7: Member 'memb3' not found in class 'Cls2' : ... note: In instance 't' : ... Suggested alternative: 'memb2' - 18 | c.memb3 = 3; - | ^~~~~ + 18 | c.memb3 = 3; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits. +%Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:13: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits. : ... note: In instance 't' - 18 | c.memb3 = 3; - | ^ + 18 | c.memb3 = 3; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_class_member_bad.v b/test_regress/t/t_class_member_bad.v index c6e904ba8..00a71fd2a 100644 --- a/test_regress/t/t_class_member_bad.v +++ b/test_regress/t/t_class_member_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Base1; - int memb1; + int memb1; endclass class Cls2 extends Base1; - int memb2; + int memb2; endclass module t; - initial begin - Cls2 c; - c.memb3 = 3; // Not found - end + initial begin + Cls2 c; + c.memb3 = 3; // Not found + end endmodule diff --git a/test_regress/t/t_class_member_bad2.out b/test_regress/t/t_class_member_bad2.out index d84763811..14c56dd0f 100644 --- a/test_regress/t/t_class_member_bad2.out +++ b/test_regress/t/t_class_member_bad2.out @@ -1,26 +1,26 @@ -%Error: t/t_class_member_bad2.v:9:8: Duplicate declaration of signal: 'vardup' - 9 | int vardup; - | ^~~~~~ - t/t_class_member_bad2.v:8:8: ... Location of original declaration - 8 | int vardup; - | ^~~~~~ +%Error: t/t_class_member_bad2.v:9:7: Duplicate declaration of signal: 'vardup' + 9 | int vardup; + | ^~~~~~ + t/t_class_member_bad2.v:8:7: ... Location of original declaration + 8 | int vardup; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of task: 'memdup' - 12 | task memdup; - | ^~~~~~ - t/t_class_member_bad2.v:10:9: ... Location of original declaration - 10 | task memdup; - | ^~~~~~ -%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of task: 'funcdup' - 17 | function void funcdup; - | ^~~~~~~ - t/t_class_member_bad2.v:15:18: ... Location of original declaration - 15 | function void funcdup; - | ^~~~~~~ -%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of member name: 'memdup' - 12 | task memdup; - | ^~~~~~ -%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of member name: 'funcdup' - 17 | function void funcdup; - | ^~~~~~~ +%Error: t/t_class_member_bad2.v:12:8: Duplicate declaration of task: 'memdup' + 12 | task memdup; + | ^~~~~~ + t/t_class_member_bad2.v:10:8: ... Location of original declaration + 10 | task memdup; + | ^~~~~~ +%Error: t/t_class_member_bad2.v:17:17: Duplicate declaration of task: 'funcdup' + 17 | function void funcdup; + | ^~~~~~~ + t/t_class_member_bad2.v:15:17: ... Location of original declaration + 15 | function void funcdup; + | ^~~~~~~ +%Error: t/t_class_member_bad2.v:12:8: Duplicate declaration of member name: 'memdup' + 12 | task memdup; + | ^~~~~~ +%Error: t/t_class_member_bad2.v:17:17: Duplicate declaration of member name: 'funcdup' + 17 | function void funcdup; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_member_bad2.v b/test_regress/t/t_class_member_bad2.v index 2d1814d5d..6e57db7f1 100644 --- a/test_regress/t/t_class_member_bad2.v +++ b/test_regress/t/t_class_member_bad2.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 class ClsDup; - int vardup; - int vardup; - task memdup; - endtask - task memdup; - endtask + int vardup; + int vardup; + task memdup; + endtask + task memdup; + endtask - function void funcdup; - endfunction - function void funcdup; - endfunction + function void funcdup; + endfunction + function void funcdup; + endfunction endclass diff --git a/test_regress/t/t_class_member_sens.v b/test_regress/t/t_class_member_sens.v index 869967f99..890c339f9 100644 --- a/test_regress/t/t_class_member_sens.v +++ b/test_regress/t/t_class_member_sens.v @@ -4,27 +4,25 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - class EventClass; - event e; - endclass + class EventClass; + event e; + endclass - EventClass ec = new; - int cyc = 0; + EventClass ec = new; + int cyc = 0; - always @ec.e ec = new; + always @ec.e ec = new; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) ->ec.e; - else if (cyc == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1)->ec.e; + else if (cyc == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_class_member_var_virt_bad.out b/test_regress/t/t_class_member_var_virt_bad.out index df9f9185b..e47ff5487 100644 --- a/test_regress/t/t_class_member_var_virt_bad.out +++ b/test_regress/t/t_class_member_var_virt_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_member_var_virt_bad.v:8:16: Syntax error: 'virtual' not allowed before var declaration - 8 | virtual int member; - | ^~~~~~ +%Error: t/t_class_member_var_virt_bad.v:8:15: Syntax error: 'virtual' not allowed before var declaration + 8 | virtual int member; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_member_var_virt_bad.v b/test_regress/t/t_class_member_var_virt_bad.v index 8a7673452..44b80b43e 100644 --- a/test_regress/t/t_class_member_var_virt_bad.v +++ b/test_regress/t/t_class_member_var_virt_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - virtual int member; + virtual int member; endclass module t; diff --git a/test_regress/t/t_class_membersel_int.v b/test_regress/t/t_class_membersel_int.v index f321cd0ee..1fc79b131 100644 --- a/test_regress/t/t_class_membersel_int.v +++ b/test_regress/t/t_class_membersel_int.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int t; + int t; endclass module Sub; - Cls c; - initial begin - int i; - c = new; - i = c.t; - $write("*-* All Finished *-*\n"); - $finish; - end + Cls c; + initial begin + int i; + c = new; + i = c.t; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module t; - Sub foo(); + Sub foo (); endmodule diff --git a/test_regress/t/t_class_method.v b/test_regress/t/t_class_method.v index 53a35c1ec..59b9189c6 100644 --- a/test_regress/t/t_class_method.v +++ b/test_regress/t/t_class_method.v @@ -7,28 +7,34 @@ typedef class Cls; class Cls; - int imembera; - function int get_methoda; return imembera; endfunction - task set_methoda(input int val); imembera = val; endtask - function void setv_methoda(input int val); imembera = val; endfunction + int imembera; + function int get_methoda; + return imembera; + endfunction + task set_methoda(input int val); + imembera = val; + endtask + function void setv_methoda(input int val); + imembera = val; + endfunction endclass : Cls module t; - initial begin - int tmp_i; - Cls c; - if (c != null) $stop; - c = new; - c.imembera = 10; - if (c.get_methoda() != 10) $stop; - c.set_methoda(20); - if (c.get_methoda() != 20) $stop; - c.setv_methoda(30); - if (c.get_methoda() != 30) $stop; - c.setv_methoda(300); - tmp_i = c.get_methoda; - if (tmp_i != 300) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int tmp_i; + Cls c; + if (c != null) $stop; + c = new; + c.imembera = 10; + if (c.get_methoda() != 10) $stop; + c.set_methoda(20); + if (c.get_methoda() != 20) $stop; + c.setv_methoda(30); + if (c.get_methoda() != 30) $stop; + c.setv_methoda(300); + tmp_i = c.get_methoda; + if (tmp_i != 300) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_method_bad.out b/test_regress/t/t_class_method_bad.out index 4a68cefb5..5e1f72f60 100644 --- a/test_regress/t/t_class_method_bad.out +++ b/test_regress/t/t_class_method_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_class_method_bad.v:18:9: Class method 'meth3' not found in class 'Cls2' +%Error: t/t_class_method_bad.v:20:7: Class method 'meth3' not found in class 'Cls2' : ... note: In instance 't' : ... Suggested alternative: 'meth2' - 18 | c.meth3(); - | ^~~~~ + 20 | c.meth3(); + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_method_bad.v b/test_regress/t/t_class_method_bad.v index f8600d6c6..81145960e 100644 --- a/test_regress/t/t_class_method_bad.v +++ b/test_regress/t/t_class_method_bad.v @@ -5,16 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 class Base1; - task meth1; endtask + task meth1; + endtask endclass class Cls2 extends Base1; - task meth2; endtask + task meth2; + endtask endclass module t; - initial begin - Cls2 c; - c.meth3(); // Not found - end + initial begin + Cls2 c; + c.meth3(); // Not found + end endmodule diff --git a/test_regress/t/t_class_method_str_literal.v b/test_regress/t/t_class_method_str_literal.v index 688e6ff76..60c7ddb89 100644 --- a/test_regress/t/t_class_method_str_literal.v +++ b/test_regress/t/t_class_method_str_literal.v @@ -6,36 +6,37 @@ module t; -class uvm_reg; + class uvm_reg; function int get_1; - return 1; + return 1; endfunction function bit get_true; - return 1; + return 1; endfunction function string get_string; - if (get_1() == 1) begin - return get_true() ? "user backdoor" : "DPI backdoor"; - end else begin - return ""; - end + if (get_1() == 1) begin + return get_true() ? "user backdoor" : "DPI backdoor"; + end + else begin + return ""; + end endfunction -endclass + endclass -class T; + class T; function automatic string return_str(input string a_string); - return a_string; + return a_string; endfunction static function automatic string static_return_str(input string a_string); - return a_string; + return a_string; endfunction -endclass + endclass -initial begin + initial begin automatic T t_c = new; automatic uvm_reg u_r = new; if (u_r.get_string() != "user backdoor") $stop; @@ -44,5 +45,5 @@ initial begin if (T::static_return_str("C") != "C") $stop; $write("*-* All Finished *-*\n"); $finish; -end + end endmodule diff --git a/test_regress/t/t_class_method_struct.v b/test_regress/t/t_class_method_struct.v index 70c6a68b8..341323df4 100644 --- a/test_regress/t/t_class_method_struct.v +++ b/test_regress/t/t_class_method_struct.v @@ -5,30 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - int x; - int y; - int z; + int x; + int y; + int z; } my_struct; class Cls; - function my_struct get_struct; - my_struct s; - s.x = 1; - s.y = 2; - s.z = 3; - return s; - endfunction + function my_struct get_struct; + my_struct s; + s.x = 1; + s.y = 2; + s.z = 3; + return s; + endfunction endclass : Cls module t; - initial begin - automatic Cls c = new; - automatic my_struct s = c.get_struct; - if (s.x != 1) $stop; - if (s.y != 2) $stop; - if (s.z != 3) $stop; + initial begin + automatic Cls c = new; + automatic my_struct s = c.get_struct; + if (s.x != 1) $stop; + if (s.y != 2) $stop; + if (s.z != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_mispure_bad.out b/test_regress/t/t_class_mispure_bad.out index 185132b3f..96fc022a1 100644 --- a/test_regress/t/t_class_mispure_bad.out +++ b/test_regress/t/t_class_mispure_bad.out @@ -1,8 +1,8 @@ %Error: t/t_class_mispure_bad.v:11:1: Class 'Bar' extends 'Base' but is missing implementation for 'pvfunc' (IEEE 1800-2023 8.26) 11 | class Bar extends Base; | ^~~~~ - t/t_class_mispure_bad.v:8:31: ... Location of interface class's function - 8 | pure virtual function void pvfunc(); - | ^~~~~~ + t/t_class_mispure_bad.v:8:30: ... Location of interface class's function + 8 | pure virtual function void pvfunc(); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_mispure_bad.v b/test_regress/t/t_class_mispure_bad.v index 453b457f3..8e631d051 100644 --- a/test_regress/t/t_class_mispure_bad.v +++ b/test_regress/t/t_class_mispure_bad.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 virtual class Base; - pure virtual function void pvfunc(); + pure virtual function void pvfunc(); endclass class Bar extends Base; - // Bad, no implementation of pvfunc + // Bad, no implementation of pvfunc endclass module t; - initial begin - automatic Bar obj = new(); - obj.pvfunc(); - $stop; - end + initial begin + automatic Bar obj = new(); + obj.pvfunc(); + $stop; + end endmodule diff --git a/test_regress/t/t_class_mod_bad.out b/test_regress/t/t_class_mod_bad.out index f5bc65c0b..12bb045b4 100644 --- a/test_regress/t/t_class_mod_bad.out +++ b/test_regress/t/t_class_mod_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_class_mod_bad.v:21:7: Package/class for ':: reference' not found: 'M' - 21 | M::Cls p; - | ^ +%Error: t/t_class_mod_bad.v:21:5: Package/class for ':: reference' not found: 'M' + 21 | M::Cls p; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_mod_bad.v:21:7: Package/class for 'class/package reference' not found: 'M' - 21 | M::Cls p; - | ^ +%Error: t/t_class_mod_bad.v:21:5: Package/class for 'class/package reference' not found: 'M' + 21 | M::Cls p; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_mod_bad.v b/test_regress/t/t_class_mod_bad.v index 5ca4ebe28..73cbed367 100644 --- a/test_regress/t/t_class_mod_bad.v +++ b/test_regress/t/t_class_mod_bad.v @@ -7,19 +7,19 @@ // verilator lint_off MULTITOP module M; -class Cls; - function string name; + class Cls; + function string name; return $sformatf("m %m"); - endfunction -endclass + endfunction + endclass endmodule module t; - string s; + string s; - initial begin - M::Cls p; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + M::Cls p; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_module.v b/test_regress/t/t_class_module.v index 31bc9b284..2ff45def3 100644 --- a/test_regress/t/t_class_module.v +++ b/test_regress/t/t_class_module.v @@ -6,34 +6,34 @@ module t; -class Cls; - class Inner; + class Cls; + class Inner; int imemberinnera; int imemberinnerb; - endclass - int imembera; - int imemberb; - Inner innermemberc; -endclass : Cls + endclass + int imembera; + int imemberb; + Inner innermemberc; + endclass : Cls -class Dead; -endclass + class Dead; + endclass - initial begin - Cls c; - if (c != null) $stop; - c = new; - if (c.innermemberc != null) $stop; - c.innermemberc = new; - c.imembera = 10; - c.imemberb = 20; - c.innermemberc.imemberinnera = 30; - c.innermemberc.imemberinnerb = 40; - if (c.imembera != 10) $stop; - if (c.imemberb != 20) $stop; - if (c.innermemberc.imemberinnera != 30) $stop; - if (c.innermemberc.imemberinnerb != 40) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + if (c != null) $stop; + c = new; + if (c.innermemberc != null) $stop; + c.innermemberc = new; + c.imembera = 10; + c.imemberb = 20; + c.innermemberc.imemberinnera = 30; + c.innermemberc.imemberinnerb = 40; + if (c.imembera != 10) $stop; + if (c.imemberb != 20) $stop; + if (c.innermemberc.imemberinnera != 30) $stop; + if (c.innermemberc.imemberinnerb != 40) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_name.v b/test_regress/t/t_class_name.v index cc38300df..d6328e040 100644 --- a/test_regress/t/t_class_name.v +++ b/test_regress/t/t_class_name.v @@ -4,150 +4,152 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef verilator `define stop $stop `else `define stop `endif `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on function string unit_name; - return $sformatf("u %m"); + return $sformatf("u %m"); endfunction class Cls; - // We use the same name for all static_name's to check we resolve right - static function string static_name; - return $sformatf("c %m"); - endfunction - // Different for non_statis to make sure likewise - function string c_auto_name; - return $sformatf("c %m"); - endfunction + // We use the same name for all static_name's to check we resolve right + static function string static_name; + return $sformatf("c %m"); + endfunction + // Different for non_statis to make sure likewise + function string c_auto_name; + return $sformatf("c %m"); + endfunction endclass package P; -class Cls; - static function string static_name; + class Cls; + static function string static_name; return $sformatf("p %m"); - endfunction - function string p_auto_name; + endfunction + function string p_auto_name; return $sformatf("p %m"); - endfunction -endclass + endfunction + endclass endpackage module M; -class Cls; - static function string static_name; + class Cls; + static function string static_name; return $sformatf("m %m"); - endfunction - function string m_auto_name; + endfunction + function string m_auto_name; return $sformatf("m %m"); - endfunction -endclass - S sub(); - function string cls_static_name; - return Cls::static_name(); - endfunction - function string cls_auto_name; - Cls c; - c = new; - return c.m_auto_name(); - endfunction + endfunction + endclass + S sub (); + function string cls_static_name; + return Cls::static_name(); + endfunction + function string cls_auto_name; + Cls c; + c = new; + return c.m_auto_name(); + endfunction endmodule module S; -class Cls; - static function string static_name; + class Cls; + static function string static_name; return $sformatf("ms %m"); - endfunction - function string ms_auto_name; + endfunction + function string ms_auto_name; return $sformatf("ms %m"); - endfunction -endclass - function string cls_static_name; - return Cls::static_name(); - endfunction - function string cls_auto_name; - Cls c; - c = new; - return c.ms_auto_name(); - endfunction + endfunction + endclass + function string cls_static_name; + return Cls::static_name(); + endfunction + function string cls_auto_name; + Cls c; + c = new; + return c.ms_auto_name(); + endfunction endmodule module t; - string s; + string s; - M m(); + M m (); - function string mod_func_name; - return $sformatf("tmf %m"); - endfunction + function string mod_func_name; + return $sformatf("tmf %m"); + endfunction - initial begin - Cls c; - P::Cls p; - p = new; - c = new; + initial begin + Cls c; + P::Cls p; + p = new; + c = new; - s = mod_func_name(); - `checks(s, "tmf top.t.mod_func_name"); + s = mod_func_name(); + `checks(s, "tmf top.t.mod_func_name"); - s = unit_name(); - `checks(s, "u top.$unit.unit_name"); - // Others: "u $unit_????::unit_name - // Others: "u $unit::unit_name - // Others: "u \\package UnitScopePackage_1\ .UnitScopePackage_1.unit_name + s = unit_name(); + `checks(s, "u top.$unit.unit_name"); + // Others: "u $unit_????::unit_name + // Others: "u $unit::unit_name + // Others: "u \\package UnitScopePackage_1\ .UnitScopePackage_1.unit_name - // *** Below results vary with simulator. + // *** Below results vary with simulator. - s = Cls::static_name(); - `checks(s, "c top.$unit.Cls.static_name"); - // Others: "c $unit_????.Cls.static_name - // Others: "c $unit::\Cls::static_name - // Others: "c Cls.static_name - s = c.c_auto_name(); - `checks(s, "c top.$unit.Cls.c_auto_name"); - // Others: "c $unit_????.Cls.c_auto_name - // Others: "c $unit::\Cls::c_auto_name - // Others: "c Cls.c_auto_name + s = Cls::static_name(); + `checks(s, "c top.$unit.Cls.static_name"); + // Others: "c $unit_????.Cls.static_name + // Others: "c $unit::\Cls::static_name + // Others: "c Cls.static_name + s = c.c_auto_name(); + `checks(s, "c top.$unit.Cls.c_auto_name"); + // Others: "c $unit_????.Cls.c_auto_name + // Others: "c $unit::\Cls::c_auto_name + // Others: "c Cls.c_auto_name - //UNSUP s = P::Cls::static_name(); - //UNSUP `checks(s, "p top.P.Cls"); - // UNSUP `checks(s, "p top.P.Cls.static_name"); - // Others: "p P.Cls.static_name - // Others: "p P::Cls.static_name - // Others: "p P::\Cls::static_name - // Others: "p \\package P\ .Cls.static_name + //UNSUP s = P::Cls::static_name(); + //UNSUP `checks(s, "p top.P.Cls"); + // UNSUP `checks(s, "p top.P.Cls.static_name"); + // Others: "p P.Cls.static_name + // Others: "p P::Cls.static_name + // Others: "p P::\Cls::static_name + // Others: "p \\package P\ .Cls.static_name - s = p.p_auto_name(); - `checks(s, "p top.P.Cls.p_auto_name"); - // Others: "p P.Cls.p_auto_name - // Others: "p P::Cls.p_auto_name - // Others: "p P::\Cls::p_auto_name - // Others: "p \\package P\ .Cls.p_auto_name + s = p.p_auto_name(); + `checks(s, "p top.P.Cls.p_auto_name"); + // Others: "p P.Cls.p_auto_name + // Others: "p P::Cls.p_auto_name + // Others: "p P::\Cls::p_auto_name + // Others: "p \\package P\ .Cls.p_auto_name - s = m.cls_static_name(); - `checks(s, "m top.t.m.Cls.static_name"); - // Others: "m top.t.m.Cls.static_name - // Others: "m top.t.m.\Cls::static_name + s = m.cls_static_name(); + `checks(s, "m top.t.m.Cls.static_name"); + // Others: "m top.t.m.Cls.static_name + // Others: "m top.t.m.\Cls::static_name - s = m.cls_auto_name(); - `checks(s, "m top.t.m.Cls.m_auto_name"); - // Others: "m top.t.m.Cls.m_auto_name - // Others: "m top.t.m.\Cls::m_auto_name + s = m.cls_auto_name(); + `checks(s, "m top.t.m.Cls.m_auto_name"); + // Others: "m top.t.m.Cls.m_auto_name + // Others: "m top.t.m.\Cls::m_auto_name - s = m.sub.cls_static_name(); - `checks(s, "ms top.t.m.sub.Cls.static_name"); - // Others: "ms top.t.m.sub.Cls.static_name - // Others: "ms top.t.m.sub.\Cls::static_name - s = m.sub.cls_auto_name(); - `checks(s, "ms top.t.m.sub.Cls.ms_auto_name"); - // Others: "ms top.t.m.sub.Cls.ms_auto_name - // Others: "ms top.t.m.sub.\Cls::ms_auto_name + s = m.sub.cls_static_name(); + `checks(s, "ms top.t.m.sub.Cls.static_name"); + // Others: "ms top.t.m.sub.Cls.static_name + // Others: "ms top.t.m.sub.\Cls::static_name + s = m.sub.cls_auto_name(); + `checks(s, "ms top.t.m.sub.Cls.ms_auto_name"); + // Others: "ms top.t.m.sub.Cls.ms_auto_name + // Others: "ms top.t.m.sub.\Cls::ms_auto_name - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_nested.v b/test_regress/t/t_class_nested.v index 10c2f547d..7c87dc94c 100644 --- a/test_regress/t/t_class_nested.v +++ b/test_regress/t/t_class_nested.v @@ -5,86 +5,86 @@ // SPDX-License-Identifier: CC0-1.0 class NodeList; - class Node; - string name; - Node link; + class Node; + string name; + Node link; - function new(); - name = "node"; - endfunction - endclass + function new(); + name = "node"; + endfunction + endclass - Node head; + Node head; endclass class NodeTree; - class Node; - int id; - Node link; - endclass + class Node; + int id; + Node link; + endclass - Node root; + Node root; endclass // Based on IEEE 1800-2017 section 8.23 Nested classes class Outer; - int outerProp; - local int outerLocalProp; - static int outerStaticProp; - static local int outerLocalStaticProp; + int outerProp; + local int outerLocalProp; + static int outerStaticProp; + static local int outerLocalStaticProp; - class Inner; - function void innerMethod(Outer h); - outerStaticProp = 1; - outerLocalStaticProp = 1; - h.outerProp = 1; - h.outerLocalProp = 1; - endfunction - endclass + class Inner; + function void innerMethod(Outer h); + outerStaticProp = 1; + outerLocalStaticProp = 1; + h.outerProp = 1; + h.outerLocalProp = 1; + endfunction + endclass endclass module t; - initial begin - automatic NodeList n = new; - automatic NodeList::Node n1 = new; - automatic NodeList::Node n2 = new; - automatic NodeTree tr = new; - automatic NodeTree::Node t1 = new; - automatic NodeTree::Node t2 = new; - automatic Outer o = new; - automatic Outer::Inner i = new; + initial begin + automatic NodeList n = new; + automatic NodeList::Node n1 = new; + automatic NodeList::Node n2 = new; + automatic NodeTree tr = new; + automatic NodeTree::Node t1 = new; + automatic NodeTree::Node t2 = new; + automatic Outer o = new; + automatic Outer::Inner i = new; - i.innerMethod(o); + i.innerMethod(o); - if(o.outerProp != 1) $stop; - if(Outer::outerStaticProp != 1) $stop; + if (o.outerProp != 1) $stop; + if (Outer::outerStaticProp != 1) $stop; - if (n1.name != "node") $stop; + if (n1.name != "node") $stop; - n1.name = "n1"; - if (n1.name != "n1") $stop; + n1.name = "n1"; + if (n1.name != "n1") $stop; - n2.name = "n2"; - if (n2.name != "n2") $stop; + n2.name = "n2"; + if (n2.name != "n2") $stop; - n.head = n1; - n1.link = n2; - if (n.head.name != "n1") $stop; - if (n.head.link.name != "n2") $stop; + n.head = n1; + n1.link = n2; + if (n.head.name != "n1") $stop; + if (n.head.link.name != "n2") $stop; - t1.id = 1; - if (t1.id != 1) $stop; + t1.id = 1; + if (t1.id != 1) $stop; - t2.id = 2; - if (t2.id != 2) $stop; + t2.id = 2; + if (t2.id != 2) $stop; - tr.root = t1; - t1.link = t2; - if (tr.root.id != 1) $stop; - if (tr.root.link.id != 2) $stop; + tr.root = t1; + t1.link = t2; + if (tr.root.id != 1) $stop; + if (tr.root.link.id != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_nested_link.v b/test_regress/t/t_class_nested_link.v index f7bcc730a..27cb51fc9 100644 --- a/test_regress/t/t_class_nested_link.v +++ b/test_regress/t/t_class_nested_link.v @@ -12,34 +12,36 @@ int calls = 0; module t; - // int calls = 0; // TODO: Error: Internal Error: Can't locate varref scope + // int calls = 0; // TODO: Error: Internal Error: Can't locate varref scope + function void myfunc(); + calls |= 32'b10; + endfunction : myfunc + + class Cls #( + int A = 0 + ); + function new(); + calls |= 32'b1; + endfunction : new function void myfunc(); - calls |= 32'b10; + calls |= 32'b100; endfunction : myfunc + endclass - class Cls #(int A = 0); - function new(); - calls |= 32'b1; - endfunction : new - function void myfunc(); - calls |= 32'b100; - endfunction : myfunc - endclass + Cls #(100) cls; - Cls #(100) cls; + // this block is following the definition of Cls + initial begin + cls = new; + myfunc(); - // this block is following the definition of Cls - initial begin - cls = new; - myfunc(); - - if (calls != 32'b011) begin - $write("calls: %0b\n", calls); - $stop; - end - - $write("*-* All Finished *-*\n"); - $finish; + if (calls != 32'b011) begin + $write("calls: %0b\n", calls); + $stop; end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_new.v b/test_regress/t/t_class_new.v index 981033ecf..de1afe853 100644 --- a/test_regress/t/t_class_new.v +++ b/test_regress/t/t_class_new.v @@ -5,89 +5,89 @@ // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; - const int imembera; // Ok for new() to assign to a const - function new(); + const int imembera; // Ok for new() to assign to a const + function new(); + int other = other_func(); + imembera = 5; + if (other != 6) $stop; + endfunction : new + class InnerNoArg; + const int imembera; + function new(); int other = other_func(); imembera = 5; if (other != 6) $stop; - endfunction : new - class InnerNoArg; - const int imembera; - function new(); - int other = other_func(); - imembera = 5; - if (other != 6) $stop; - endfunction - function int other_func(); - return 6; - endfunction - endclass - function int other_func(); + endfunction + function int other_func(); return 6; - endfunction + endfunction + endclass + function int other_func(); + return 6; + endfunction endclass class ClsArg; - int imembera; - function new(int i); - imembera = i + 1; - endfunction - function int geta; - return imembera; - endfunction - static function ClsArg create6; - ClsArg obj; - obj = new(6 - 1); - return obj; - endfunction + int imembera; + function new(int i); + imembera = i + 1; + endfunction + function int geta; + return imembera; + endfunction + static function ClsArg create6; + ClsArg obj; + obj = new(6 - 1); + return obj; + endfunction endclass class Cls2Arg; - int imembera; - int imemberb; - function new(int i, int j); - imembera = i + 1; - imemberb = j + 2; - endfunction + int imembera; + int imemberb; + function new(int i, int j); + imembera = i + 1; + imemberb = j + 2; + endfunction - function Cls2Arg clone(); - Cls2Arg ret; - ret = new(imembera, imemberb); - return ret; - endfunction + function Cls2Arg clone(); + Cls2Arg ret; + ret = new(imembera, imemberb); + return ret; + endfunction endclass module t; - initial begin - ClsNoArg c1; - ClsArg c2; - Cls2Arg c3; - Cls2Arg c4; - automatic ClsNoArg::InnerNoArg c5 = new; + initial begin + ClsNoArg c1; + ClsArg c2; + Cls2Arg c3; + Cls2Arg c4; + automatic ClsNoArg::InnerNoArg c5 = new; - c1 = new; - if (c1.imembera != 5) $stop; + c1 = new; + if (c1.imembera != 5) $stop; - c2 = new(3 - 1); - if (c2.imembera != 3) $stop; - if (c2.geta() != 3) $stop; + c2 = new(3 - 1); + if (c2.imembera != 3) $stop; + if (c2.geta() != 3) $stop; - c2 = ClsArg::create6(); - if (c2.imembera != 6) $stop; - if (c2.geta() != 6) $stop; + c2 = ClsArg::create6(); + if (c2.imembera != 6) $stop; + if (c2.geta() != 6) $stop; - c3 = new(4, 5); - if (c3.imembera != 5) $stop; - if (c3.imemberb != 7) $stop; + c3 = new(4, 5); + if (c3.imembera != 5) $stop; + if (c3.imemberb != 7) $stop; - c4 = c3.clone(); - if (c4.imembera != 6) $stop; - if (c4.imemberb != 9) $stop; + c4 = c3.clone(); + if (c4.imembera != 6) $stop; + if (c4.imemberb != 9) $stop; - c5 = new; - if (c5.imembera != 5) $stop; + c5 = new; + if (c5.imembera != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_new_bad.out b/test_regress/t/t_class_new_bad.out index 441d1fc11..5707e4229 100644 --- a/test_regress/t/t_class_new_bad.out +++ b/test_regress/t/t_class_new_bad.out @@ -1,40 +1,40 @@ -%Error: t/t_class_new_bad.v:27:19: class 'new()' cannot be static (IEEE 1800-2023 18.3) +%Error: t/t_class_new_bad.v:28:12: class 'new()' cannot be static (IEEE 1800-2023 18.3) : ... note: In instance 't' - 27 | static function new(); - | ^~~ + 28 | function new(); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_new_bad.v:32:20: class 'new()' cannot be virual (IEEE 1800-2023 18.3) +%Error: t/t_class_new_bad.v:34:12: class 'new()' cannot be virual (IEEE 1800-2023 18.3) : ... note: In instance 't' - 32 | virtual function new(); - | ^~~ -%Error: t/t_class_new_bad.v:39:19: class 'new()' cannot be virual (IEEE 1800-2023 18.3) + 34 | function new(); + | ^~~ +%Error: t/t_class_new_bad.v:41:19: class 'new()' cannot be virual (IEEE 1800-2023 18.3) : ... note: In instance 't' - 39 | function ClsNew3::new(); + 41 | function ClsNew3::new(); | ^~~ -%Error: t/t_class_new_bad.v:47:16: Too many arguments in call to function 'new' +%Error: t/t_class_new_bad.v:49:14: Too many arguments in call to function 'new' : ... note: In instance 't' - 47 | c1 = new(3); - | ^~~ + 49 | c1 = new(3); + | ^~~ : ... Location of function 'new' declaration: - 10 | function new(); - | ^~~ -%Error: t/t_class_new_bad.v:48:16: Too many arguments in call to function 'new' - : ... note: In instance 't' - 48 | c2 = new(3); + 10 | function new(); | ^~~ +%Error: t/t_class_new_bad.v:50:14: Too many arguments in call to function 'new' + : ... note: In instance 't' + 50 | c2 = new(3); + | ^~~ : ... Location of function 'new' declaration: 15 | class ClsNoNew; | ^~~~~ -%Error: t/t_class_new_bad.v:49:12: Missing argument on non-defaulted argument 'i' in function call to FUNC 'new' +%Error: t/t_class_new_bad.v:51:10: Missing argument on non-defaulted argument 'i' in function call to FUNC 'new' : ... note: In instance 't' - 49 | c3 = new(); - | ^~~ -%Error: t/t_class_new_bad.v:50:12: dynamic new() not expected in this context (data type must be dynamic array) + 51 | c3 = new(); + | ^~~ +%Error: t/t_class_new_bad.v:52:10: dynamic new() not expected in this context (data type must be dynamic array) : ... note: In instance 't' - 50 | c1 = new[2]; - | ^~~ -%Error: Internal Error: t/t_class_new_bad.v:50:12: ../V3Width.cpp:#: Node has no type + 52 | c1 = new[2]; + | ^~~ +%Error: Internal Error: t/t_class_new_bad.v:52:10: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' - 50 | c1 = new[2]; - | ^~~ + 52 | c1 = new[2]; + | ^~~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_class_new_bad.v b/test_regress/t/t_class_new_bad.v index 1e9a3fb03..864d56793 100644 --- a/test_regress/t/t_class_new_bad.v +++ b/test_regress/t/t_class_new_bad.v @@ -6,30 +6,32 @@ class ClsNoArg; - int imembera; - function new(); - imembera = 5; - endfunction + int imembera; + function new(); + imembera = 5; + endfunction endclass class ClsNoNew; - int imembera; + int imembera; endclass class ClsArg; - int imembera; - function new(int i); - imembera = i + 1; - endfunction + int imembera; + function new(int i); + imembera = i + 1; + endfunction endclass class ClsNew1; - static function new(); // <--- Error: new can't be static + static + function new(); // <--- Error: new can't be static endfunction endclass class ClsNew2; - virtual function new(); // <--- Error: new can't be virtual + virtual + function new(); // <--- Error: new can't be virtual endfunction endclass @@ -40,14 +42,14 @@ function ClsNew3::new(); endfunction module t; - initial begin - ClsNoArg c1; - ClsNoNew c2; - ClsArg c3; - c1 = new(3); // Bad, called with arg - c2 = new(3); // Bad, called with arg - c3 = new(); // Bad, called without arg - c1 = new[2]; - $stop; - end + initial begin + ClsNoArg c1; + ClsNoNew c2; + ClsArg c3; + c1 = new(3); // Bad, called with arg + c2 = new(3); // Bad, called with arg + c3 = new(); // Bad, called without arg + c1 = new[2]; + $stop; + end endmodule diff --git a/test_regress/t/t_class_new_default.out b/test_regress/t/t_class_new_default.out index 1ddd26248..d01349eed 100644 --- a/test_regress/t/t_class_new_default.out +++ b/test_regress/t/t_class_new_default.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_class_new_default.v:10:17: Unsupported: new constructor 'default' argument - 10 | function new(default); - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_class_new_default.v:10:16: Unsupported: new constructor 'default' argument + 10 | function new(default); + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_class_new_default.v:17:24: Unsupported: new constructor 'default' argument - 17 | extern function new(default); - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_class_new_default.v:17:23: Unsupported: new constructor 'default' argument + 17 | extern function new(default); + | ^~~~~~~ %Error-UNSUPPORTED: t/t_class_new_default.v:20:25: Unsupported: new constructor 'default' argument 20 | function ClsDefFwd::new(default); | ^~~~~~~ diff --git a/test_regress/t/t_class_new_default.v b/test_regress/t/t_class_new_default.v index 213874f14..8767688c1 100644 --- a/test_regress/t/t_class_new_default.v +++ b/test_regress/t/t_class_new_default.v @@ -6,23 +6,23 @@ class ClsDef; - int imembera; - function new(default); - imembera = i + 1; - endfunction + int imembera; + function new(default); + imembera = i + 1; + endfunction endclass class ClsDefFwd; - int imembera; - extern function new(default); + int imembera; + extern function new(default); endclass function ClsDefFwd::new(default); endfunction module t; - initial begin - // TODO real test - $stop; - end + initial begin + // TODO real test + $stop; + end endmodule diff --git a/test_regress/t/t_class_new_noparen.v b/test_regress/t/t_class_new_noparen.v index 299faf90a..97f51f343 100644 --- a/test_regress/t/t_class_new_noparen.v +++ b/test_regress/t/t_class_new_noparen.v @@ -5,35 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 class u_object; - string m_name; - function new(string name); - m_name = name; - endfunction + string m_name; + function new(string name); + m_name = name; + endfunction endclass -class u_cache#(type KEY_T=int, type DATA_T=int) extends u_object; - typedef int unsigned size_t; - int m_max_size; +class u_cache #( + type KEY_T = int, + type DATA_T = int +) extends u_object; + typedef int unsigned size_t; + int m_max_size; - extern function new(string name="u_cache", size_t max_size = 256); + extern function new(string name = "u_cache", size_t max_size = 256); endclass // #() not required below, see IEEE 1800-2023 8.25.1 -function u_cache::new(string name="u_cache", u_cache::size_t max_size = 256); - super.new(name); - this.m_max_size = max_size; +function u_cache::new(string name = "u_cache", u_cache::size_t max_size = 256); + super.new(name); + this.m_max_size = max_size; endfunction module t; - u_cache #(real, real) obj; + u_cache #(real, real) obj; - initial begin - obj = new("fred", 62); - if (obj.m_name != "fred") $stop; - if (obj.m_max_size != 62) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + obj = new("fred", 62); + if (obj.m_name != "fred") $stop; + if (obj.m_max_size != 62) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_new_ref_bad.out b/test_regress/t/t_class_new_ref_bad.out index b949f859e..3448171b9 100644 --- a/test_regress/t/t_class_new_ref_bad.out +++ b/test_regress/t/t_class_new_ref_bad.out @@ -1,14 +1,14 @@ -%Error: t/t_class_new_ref_bad.v:16:24: new() assignment not legal to non-class data type 'int' +%Error: t/t_class_new_ref_bad.v:16:22: new() assignment not legal to non-class data type 'int' : ... note: In instance 't' - 16 | txn_type_t txn = new; - | ^~~ + 16 | txn_type_t txn = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_new_ref_bad.v:17:25: new() cannot copy from non-class data type 'int' +%Error: t/t_class_new_ref_bad.v:17:23: new() cannot copy from non-class data type 'int' : ... note: In instance 't' - 17 | txn_type_t copy = new txn; - | ^~~ -%Error: t/t_class_new_ref_bad.v:26:31: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' + 17 | txn_type_t copy = new txn; + | ^~~ +%Error: t/t_class_new_ref_bad.v:26:29: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' : ... note: In instance 't' - 26 | automatic Base b = Cls::generate_txn(); - | ^~~~~~~~~~~~ + 26 | automatic Base b = Cls::generate_txn(); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_new_ref_bad.v b/test_regress/t/t_class_new_ref_bad.v index fbab68617..7785eb81d 100644 --- a/test_regress/t/t_class_new_ref_bad.v +++ b/test_regress/t/t_class_new_ref_bad.v @@ -8,26 +8,26 @@ class Base; endclass class Cls extends Base; - typedef int txn_type_t; // Bad type + typedef int txn_type_t; // Bad type - rand txn_type_t req_txn_type; + rand txn_type_t req_txn_type; - static function txn_type_t generate_txn(); - txn_type_t txn = new; - txn_type_t copy = new txn; - return txn; - endfunction + static function txn_type_t generate_txn(); + txn_type_t txn = new; + txn_type_t copy = new txn; + return txn; + endfunction endclass module t; - initial begin - automatic Base b = Cls::generate_txn(); - $display("%p", b); + initial begin + automatic Base b = Cls::generate_txn(); + $display("%p", b); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_new_return.v b/test_regress/t/t_class_new_return.v index db38a2bfc..5533c2364 100644 --- a/test_regress/t/t_class_new_return.v +++ b/test_regress/t/t_class_new_return.v @@ -4,33 +4,30 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; + class foo; + int a; + function new; + a = 1; + return; + a = 2; + endfunction + function int get_a; + return a; + endfunction + endclass - class foo; - int a; - function new; - a = 1; - return; - a = 2; - endfunction - function int get_a; - return a; - endfunction - endclass + foo foo_i; + initial foo_i = new; - foo foo_i; - initial foo_i = new; - - always @(posedge clk) begin - if (foo_i.get_a() == 1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else - $stop; - end + always @(posedge clk) begin + if (foo_i.get_a() == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else $stop; + end endmodule diff --git a/test_regress/t/t_class_new_scoped_bad.out b/test_regress/t/t_class_new_scoped_bad.out index 12fc842e7..f3d65d214 100644 --- a/test_regress/t/t_class_new_scoped_bad.out +++ b/test_regress/t/t_class_new_scoped_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_new_scoped_bad.v:17:16: new() assignment not legal to non-class 'Pkg' +%Error: t/t_class_new_scoped_bad.v:17:14: new() assignment not legal to non-class 'Pkg' : ... note: In instance 't' - 17 | c = Pkg::new; - | ^~~ + 17 | c = Pkg::new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_new_scoped_bad.v b/test_regress/t/t_class_new_scoped_bad.v index 19f20889a..85a889559 100644 --- a/test_regress/t/t_class_new_scoped_bad.v +++ b/test_regress/t/t_class_new_scoped_bad.v @@ -12,8 +12,8 @@ class C; endclass module t; - C c; - initial begin - c = Pkg::new; // Bad - end + C c; + initial begin + c = Pkg::new; // Bad + end endmodule diff --git a/test_regress/t/t_class_new_this.v b/test_regress/t/t_class_new_this.v index 70211bb83..42375f101 100644 --- a/test_regress/t/t_class_new_this.v +++ b/test_regress/t/t_class_new_this.v @@ -4,45 +4,45 @@ // SPDX-License-Identifier: CC0-1.0 interface class ICls; - pure virtual function string get(); + pure virtual function string get(); endclass class Cls; - string name; - ICls icls; - function new(string name, ICls icls); - this.name = name; - this.icls = icls; - endfunction + string name; + ICls icls; + function new(string name, ICls icls); + this.name = name; + this.icls = icls; + endfunction endclass class Testcase implements ICls; - Cls cls = new("test_class", this); - virtual function string get(); - return "In ICls"; - endfunction - function Testcase clone(); - Testcase a = new this; - return a; - endfunction + Cls cls = new("test_class", this); + virtual function string get(); + return "In ICls"; + endfunction + function Testcase clone(); + Testcase a = new this; + return a; + endfunction endclass module t; - initial begin - Testcase test; - Testcase cloned; - test = new; - if (test.cls.name != "test_class") $stop; - if (test.cls.icls.get() != "In ICls") $stop; + initial begin + Testcase test; + Testcase cloned; + test = new; + if (test.cls.name != "test_class") $stop; + if (test.cls.icls.get() != "In ICls") $stop; - cloned = test.clone(); - if (cloned.cls.name != "test_class") $stop; + cloned = test.clone(); + if (cloned.cls.name != "test_class") $stop; - test.cls.icls = null; // Prevent leak + test.cls.icls = null; // Prevent leak - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_new_typed.v b/test_regress/t/t_class_new_typed.v index 76dedbf49..9779c4d35 100644 --- a/test_regress/t/t_class_new_typed.v +++ b/test_regress/t/t_class_new_typed.v @@ -5,26 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 module t; -class SuperCls; - int s = 2; - function new(int def = 3); + class SuperCls; + int s = 2; + function new(int def = 3); s = def; - endfunction -endclass + endfunction + endclass -class Cls extends SuperCls; - function new(int def = 42); + class Cls extends SuperCls; + function new(int def = 42); s = def; - endfunction -endclass + endfunction + endclass - SuperCls super_obj; + SuperCls super_obj; - initial begin - super_obj = Cls::new; - if (super_obj.s != 42) $stop; + initial begin + super_obj = Cls::new; + if (super_obj.s != 42) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_null_bad.v b/test_regress/t/t_class_null_bad.v index 75f06abe6..3ecd39fd6 100644 --- a/test_regress/t/t_class_null_bad.v +++ b/test_regress/t/t_class_null_bad.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int imembera; + int imembera; endclass : Cls module t; - Cls c; - initial begin - c = null; // Not really required as null is default - c.imembera = 10; // BAD IEEE 8.4 - $write("*-* All Finished *-*\n"); - $finish; - end + Cls c; + initial begin + c = null; // Not really required as null is default + c.imembera = 10; // BAD IEEE 8.4 + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_null_struct.v b/test_regress/t/t_class_null_struct.v index 172a3ad78..9848e6b9f 100644 --- a/test_regress/t/t_class_null_struct.v +++ b/test_regress/t/t_class_null_struct.v @@ -8,32 +8,32 @@ class Cls; endclass : Cls typedef struct { - Cls obj; - int number; + Cls obj; + int number; } str_t; module t; - function automatic str_t func_null(); - return '{null, 42}; - endfunction + function automatic str_t func_null(); + return '{null, 42}; + endfunction - function automatic str_t func_obj(); - Cls c; - c = new; - return '{c, 43}; - endfunction + function automatic str_t func_obj(); + Cls c; + c = new; + return '{c, 43}; + endfunction - initial begin - str_t result; - result = func_null(); - if (result.obj != null) $stop; - if (result.number != 42) $stop; + initial begin + str_t result; + result = func_null(); + if (result.obj != null) $stop; + if (result.number != 42) $stop; - result = func_obj(); - if (result.obj == null) $stop; - if (result.number != 43) $stop; + result = func_obj(); + if (result.obj == null) $stop; + if (result.number != 43) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_override.v b/test_regress/t/t_class_override.v index e2d7186f9..e6d76713b 100644 --- a/test_regress/t/t_class_override.v +++ b/test_regress/t/t_class_override.v @@ -6,87 +6,87 @@ // Function names correspond to how the function is declared in the base class, // then the extend class, with letters: -// Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) +// Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) class Base; - // _X = non-existant - // _n = None - function int get_n; return 1; endfunction - function int get_n_n; return 1; endfunction - function int get_n_e; return 1; endfunction - function int get_n_ef; return 1; endfunction - function int get_n_i; return 1; endfunction - function int get_n_if; return 1; endfunction - function int get_n_f; return 1; endfunction - // _e = :extends - // function :extends int get_e; return 1; endfunction // Bad - // _ef = :extends :final - // function :extends :final int get_ef; return 1; endfunction // Bad - // _i = :initial - function :initial int get_i; return 1; endfunction - function :initial int get_i_n; return 1; endfunction - function :initial int get_i_e; return 1; endfunction - function :initial int get_i_ef; return 1; endfunction - function :initial int get_i_i; return 1; endfunction - function :initial int get_i_if; return 1; endfunction - function :initial int get_i_f; return 1; endfunction - // _if = :initial :final - function :initial :final int get_if; return 1; endfunction - function :initial :final int get_if_n; return 1; endfunction - function :initial :final int get_if_e; return 1; endfunction - function :initial :final int get_if_ef; return 1; endfunction - function :initial :final int get_if_i; return 1; endfunction - function :initial :final int get_if_if; return 1; endfunction - function :initial :final int get_if_f; return 1; endfunction - // _f = :final - function :final int get_f; return 1; endfunction - function :final int get_f_n; return 1; endfunction - function :final int get_f_e; return 1; endfunction - function :final int get_f_ef; return 1; endfunction - function :final int get_f_i; return 1; endfunction - function :final int get_f_if; return 1; endfunction - function :final int get_f_f; return 1; endfunction + // _X = non-existant + // _n = None + function int get_n; return 1; endfunction + function int get_n_n; return 1; endfunction + function int get_n_e; return 1; endfunction + function int get_n_ef; return 1; endfunction + function int get_n_i; return 1; endfunction + function int get_n_if; return 1; endfunction + function int get_n_f; return 1; endfunction + // _e = :extends + // function :extends int get_e; return 1; endfunction // Bad + // _ef = :extends :final + // function :extends :final int get_ef; return 1; endfunction // Bad + // _i = :initial + function :initial int get_i; return 1; endfunction + function :initial int get_i_n; return 1; endfunction + function :initial int get_i_e; return 1; endfunction + function :initial int get_i_ef; return 1; endfunction + function :initial int get_i_i; return 1; endfunction + function :initial int get_i_if; return 1; endfunction + function :initial int get_i_f; return 1; endfunction + // _if = :initial :final + function :initial :final int get_if; return 1; endfunction + function :initial :final int get_if_n; return 1; endfunction + function :initial :final int get_if_e; return 1; endfunction + function :initial :final int get_if_ef; return 1; endfunction + function :initial :final int get_if_i; return 1; endfunction + function :initial :final int get_if_if; return 1; endfunction + function :initial :final int get_if_f; return 1; endfunction + // _f = :final + function :final int get_f; return 1; endfunction + function :final int get_f_n; return 1; endfunction + function :final int get_f_e; return 1; endfunction + function :final int get_f_ef; return 1; endfunction + function :final int get_f_i; return 1; endfunction + function :final int get_f_if; return 1; endfunction + function :final int get_f_f; return 1; endfunction endclass class Cls extends Base; - // _X = non-existant - function int get_x_n; return 1; endfunction - // function :extends int get_x_e; return 1; endfunction // Bad - // function :extends :final int get_x_ef; return 1; endfunction // Bad - function :initial int get_x_i; return 1; endfunction - function :initial :final int get_x_if; return 1; endfunction - function :final int get_x_f; return 1; endfunction - // _n = None - function int get_n_n; return 1; endfunction - function :extends int get_n_e; return 1; endfunction - function :extends :final int get_n_ef; return 1; endfunction - // function :initial int get_n_i; return 1; endfunction // Bad - // function :initial :final int get_n_if; return 1; endfunction // Bad - function :final int get_n_f; return 1; endfunction - // _e = :extends - // _ef = :extends :final - // _i = :initial - function int get_i_n; return 1; endfunction - function :extends int get_i_e; return 1; endfunction - function :extends :final int get_i_ef; return 1; endfunction - // function :initial int get_i_i; return 1; endfunction // Bad - // function :initial :final int get_i_if; return 1; endfunction // Bad - function :final int get_i_f; return 1; endfunction - // _if = :initial :final - // function int get_if_n; return 1; endfunction // Bad - // function :extends int get_if_e; return 1; endfunction // Bad - // function :extends :final int get_if_ef; return 1; endfunction // Bad - // function :initial int get_if_i; return 1; endfunction // Bad - // function :initial :final int get_if_if; return 1; endfunction // Bad - // function :final int get_if_f; return 1; endfunction // Bad - // _f = :final - // function int get_f_n; return 1; endfunction // Bad - // function :extends int get_f_e; return 1; endfunction // Bad - // function :extends :final int get_f_ef; return 1; endfunction // Bad - // function :initial int get_f_i; return 1; endfunction // Bad - // function :initial :final int get_f_if; return 1; endfunction // Bad - // function :final int get_f_f; return 1; endfunction // Bad + // _X = non-existant + function int get_x_n; return 1; endfunction + // function :extends int get_x_e; return 1; endfunction // Bad + // function :extends :final int get_x_ef; return 1; endfunction // Bad + function :initial int get_x_i; return 1; endfunction + function :initial :final int get_x_if; return 1; endfunction + function :final int get_x_f; return 1; endfunction + // _n = None + function int get_n_n; return 1; endfunction + function :extends int get_n_e; return 1; endfunction + function :extends :final int get_n_ef; return 1; endfunction + // function :initial int get_n_i; return 1; endfunction // Bad + // function :initial :final int get_n_if; return 1; endfunction // Bad + function :final int get_n_f; return 1; endfunction + // _e = :extends + // _ef = :extends :final + // _i = :initial + function int get_i_n; return 1; endfunction + function :extends int get_i_e; return 1; endfunction + function :extends :final int get_i_ef; return 1; endfunction + // function :initial int get_i_i; return 1; endfunction // Bad + // function :initial :final int get_i_if; return 1; endfunction // Bad + function :final int get_i_f; return 1; endfunction + // _if = :initial :final + // function int get_if_n; return 1; endfunction // Bad + // function :extends int get_if_e; return 1; endfunction // Bad + // function :extends :final int get_if_ef; return 1; endfunction // Bad + // function :initial int get_if_i; return 1; endfunction // Bad + // function :initial :final int get_if_if; return 1; endfunction // Bad + // function :final int get_if_f; return 1; endfunction // Bad + // _f = :final + // function int get_f_n; return 1; endfunction // Bad + // function :extends int get_f_e; return 1; endfunction // Bad + // function :extends :final int get_f_ef; return 1; endfunction // Bad + // function :initial int get_f_i; return 1; endfunction // Bad + // function :initial :final int get_f_if; return 1; endfunction // Bad + // function :final int get_f_f; return 1; endfunction // Bad endclass class CBase; @@ -99,15 +99,15 @@ class :final CClsF extends CBase; endclass module t; - initial begin - Cls c; - CClsF cc; + initial begin + Cls c; + CClsF cc; - if (c != null) $stop; - c = new; - cc = new; + if (c != null) $stop; + c = new; + cc = new; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_override_bad.out b/test_regress/t/t_class_override_bad.out index 801ceba7f..a8a142597 100644 --- a/test_regress/t/t_class_override_bad.out +++ b/test_regress/t/t_class_override_bad.out @@ -1,165 +1,165 @@ -%Error: t/t_class_override_bad.v:22:26: Member 'get_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) +%Error: t/t_class_override_bad.v:23:25: Member 'get_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' - 22 | function :extends int get_e; return 1; endfunction - | ^~~~~ + 23 | function :extends int get_e; return 1; endfunction + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_override_bad.v:24:33: Member 'get_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) +%Error: t/t_class_override_bad.v:25:32: Member 'get_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' - 24 | function :extends :final int get_ef; return 1; endfunction - | ^~~~~~ -%Error: t/t_class_override_bad.v:55:26: Member 'get_x_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) + 25 | function :extends :final int get_ef; return 1; endfunction + | ^~~~~~ +%Error: t/t_class_override_bad.v:56:25: Member 'get_x_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' - 55 | function :extends int get_x_e; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:56:33: Member 'get_x_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) + 56 | function :extends int get_x_e; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:57:32: Member 'get_x_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' - 56 | function :extends :final int get_x_ef; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:64:26: Member 'get_n_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 57 | function :extends :final int get_x_ef; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:65:25: Member 'get_n_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 64 | function :initial int get_n_i; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:18:17: ... Location of declaration being extended - 18 | function int get_n_i; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:65:33: Member 'get_n_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 65 | function :initial int get_n_i; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:19:16: ... Location of declaration being extended + 19 | function int get_n_i; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:66:32: Member 'get_n_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 65 | function :initial :final int get_n_if; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:19:17: ... Location of declaration being extended - 19 | function int get_n_if; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:73:26: Member 'get_i_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 66 | function :initial :final int get_n_if; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:20:16: ... Location of declaration being extended + 20 | function int get_n_if; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:74:25: Member 'get_i_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 73 | function :initial int get_i_i; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:30:26: ... Location of declaration being extended - 30 | function :initial int get_i_i; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:74:33: Member 'get_i_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 74 | function :initial int get_i_i; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:31:25: ... Location of declaration being extended + 31 | function :initial int get_i_i; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:75:32: Member 'get_i_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 74 | function :initial :final int get_i_if; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:31:26: ... Location of declaration being extended - 31 | function :initial int get_i_if; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:77:17: Member 'get_if_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 75 | function :initial :final int get_i_if; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:32:25: ... Location of declaration being extended + 32 | function :initial int get_i_if; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:78:16: Member 'get_if_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 77 | function int get_if_n; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:35:33: ... Location of ':final' declaration being extended - 35 | function :initial :final int get_if_n; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:78:26: Member 'get_if_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 78 | function int get_if_n; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:36:32: ... Location of ':final' declaration being extended + 36 | function :initial :final int get_if_n; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:79:25: Member 'get_if_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 78 | function :extends int get_if_e; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:36:33: ... Location of ':final' declaration being extended - 36 | function :initial :final int get_if_e; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:79:33: Member 'get_if_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 79 | function :extends int get_if_e; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:37:32: ... Location of ':final' declaration being extended + 37 | function :initial :final int get_if_e; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:80:32: Member 'get_if_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 79 | function :extends :final int get_if_ef; return 1; endfunction - | ^~~~~~~~~ - t/t_class_override_bad.v:37:33: ... Location of ':final' declaration being extended - 37 | function :initial :final int get_if_ef; return 1; endfunction - | ^~~~~~~~~ -%Error: t/t_class_override_bad.v:80:26: Member 'get_if_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 80 | function :extends :final int get_if_ef; return 1; endfunction + | ^~~~~~~~~ + t/t_class_override_bad.v:38:32: ... Location of ':final' declaration being extended + 38 | function :initial :final int get_if_ef; return 1; endfunction + | ^~~~~~~~~ +%Error: t/t_class_override_bad.v:81:25: Member 'get_if_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 80 | function :initial int get_if_i; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:38:33: ... Location of declaration being extended - 38 | function :initial :final int get_if_i; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:80:26: Member 'get_if_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 81 | function :initial int get_if_i; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:39:32: ... Location of declaration being extended + 39 | function :initial :final int get_if_i; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:81:25: Member 'get_if_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 80 | function :initial int get_if_i; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:38:33: ... Location of ':final' declaration being extended - 38 | function :initial :final int get_if_i; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:81:33: Member 'get_if_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 81 | function :initial int get_if_i; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:39:32: ... Location of ':final' declaration being extended + 39 | function :initial :final int get_if_i; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:82:32: Member 'get_if_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 81 | function :initial :final int get_if_if; return 1; endfunction - | ^~~~~~~~~ - t/t_class_override_bad.v:39:33: ... Location of declaration being extended - 39 | function :initial :final int get_if_if; return 1; endfunction - | ^~~~~~~~~ -%Error: t/t_class_override_bad.v:81:33: Member 'get_if_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 82 | function :initial :final int get_if_if; return 1; endfunction + | ^~~~~~~~~ + t/t_class_override_bad.v:40:32: ... Location of declaration being extended + 40 | function :initial :final int get_if_if; return 1; endfunction + | ^~~~~~~~~ +%Error: t/t_class_override_bad.v:82:32: Member 'get_if_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 81 | function :initial :final int get_if_if; return 1; endfunction - | ^~~~~~~~~ - t/t_class_override_bad.v:39:33: ... Location of ':final' declaration being extended - 39 | function :initial :final int get_if_if; return 1; endfunction - | ^~~~~~~~~ -%Error: t/t_class_override_bad.v:82:24: Member 'get_if_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 82 | function :initial :final int get_if_if; return 1; endfunction + | ^~~~~~~~~ + t/t_class_override_bad.v:40:32: ... Location of ':final' declaration being extended + 40 | function :initial :final int get_if_if; return 1; endfunction + | ^~~~~~~~~ +%Error: t/t_class_override_bad.v:83:23: Member 'get_if_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 82 | function :final int get_if_f; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:40:33: ... Location of ':final' declaration being extended - 40 | function :initial :final int get_if_f; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:84:17: Member 'get_f_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 83 | function :final int get_if_f; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:41:32: ... Location of ':final' declaration being extended + 41 | function :initial :final int get_if_f; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:85:16: Member 'get_f_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 84 | function int get_f_n; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:43:24: ... Location of ':final' declaration being extended - 43 | function :final int get_f_n; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:85:26: Member 'get_f_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 85 | function int get_f_n; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:44:23: ... Location of ':final' declaration being extended + 44 | function :final int get_f_n; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:86:25: Member 'get_f_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 85 | function :extends int get_f_e; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:44:24: ... Location of ':final' declaration being extended - 44 | function :final int get_f_e; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:86:33: Member 'get_f_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 86 | function :extends int get_f_e; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:45:23: ... Location of ':final' declaration being extended + 45 | function :final int get_f_e; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:87:32: Member 'get_f_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 86 | function :extends :final int get_f_ef; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:45:24: ... Location of ':final' declaration being extended - 45 | function :final int get_f_ef; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:87:26: Member 'get_f_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 87 | function :extends :final int get_f_ef; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:46:23: ... Location of ':final' declaration being extended + 46 | function :final int get_f_ef; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:88:25: Member 'get_f_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 87 | function :initial int get_f_i; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:46:24: ... Location of declaration being extended - 46 | function :final int get_f_i; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:87:26: Member 'get_f_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 88 | function :initial int get_f_i; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:47:23: ... Location of declaration being extended + 47 | function :final int get_f_i; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:88:25: Member 'get_f_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 87 | function :initial int get_f_i; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:46:24: ... Location of ':final' declaration being extended - 46 | function :final int get_f_i; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:88:33: Member 'get_f_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) + 88 | function :initial int get_f_i; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:47:23: ... Location of ':final' declaration being extended + 47 | function :final int get_f_i; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:89:32: Member 'get_f_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' - 88 | function :initial :final int get_f_if; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:47:24: ... Location of declaration being extended - 47 | function :final int get_f_if; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:88:33: Member 'get_f_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 89 | function :initial :final int get_f_if; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:48:23: ... Location of declaration being extended + 48 | function :final int get_f_if; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:89:32: Member 'get_f_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 88 | function :initial :final int get_f_if; return 1; endfunction - | ^~~~~~~~ - t/t_class_override_bad.v:47:24: ... Location of ':final' declaration being extended - 47 | function :final int get_f_if; return 1; endfunction - | ^~~~~~~~ -%Error: t/t_class_override_bad.v:89:24: Member 'get_f_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) + 89 | function :initial :final int get_f_if; return 1; endfunction + | ^~~~~~~~ + t/t_class_override_bad.v:48:23: ... Location of ':final' declaration being extended + 48 | function :final int get_f_if; return 1; endfunction + | ^~~~~~~~ +%Error: t/t_class_override_bad.v:90:23: Member 'get_f_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 89 | function :final int get_f_f; return 1; endfunction - | ^~~~~~~ - t/t_class_override_bad.v:48:24: ... Location of ':final' declaration being extended - 48 | function :final int get_f_f; return 1; endfunction - | ^~~~~~~ -%Error: t/t_class_override_bad.v:101:42: Class 'CClsBadExtendsFinal' is being extended from class marked ':final' (IEEE 1800-2023 8.20) + 90 | function :final int get_f_f; return 1; endfunction + | ^~~~~~~ + t/t_class_override_bad.v:49:23: ... Location of ':final' declaration being extended + 49 | function :final int get_f_f; return 1; endfunction + | ^~~~~~~ +%Error: t/t_class_override_bad.v:102:42: Class 'CClsBadExtendsFinal' is being extended from class marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' - 101 | class :final CClsBadExtendsFinal extends CClsF; + 102 | class :final CClsBadExtendsFinal extends CClsF; | ^~~~~ - t/t_class_override_bad.v:98:1: ... Location of ':final' class being extended - 98 | class :final CClsF extends CBase; + t/t_class_override_bad.v:99:1: ... Location of ':final' class being extended + 99 | class :final CClsF extends CBase; | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_override_bad.v b/test_regress/t/t_class_override_bad.v index b4e9f251a..90b4b62d4 100644 --- a/test_regress/t/t_class_override_bad.v +++ b/test_regress/t/t_class_override_bad.v @@ -6,87 +6,88 @@ // Function names correspond to how the function is declared in the base class, // then the extend class, with letters: -// Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) +// Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) +// verilog_format: off class Base; - // _X = non-existant - // _n = None - function int get_n; return 1; endfunction - function int get_n_n; return 1; endfunction - function int get_n_e; return 1; endfunction - function int get_n_ef; return 1; endfunction - function int get_n_i; return 1; endfunction - function int get_n_if; return 1; endfunction - function int get_n_f; return 1; endfunction - // _e = :extends - function :extends int get_e; return 1; endfunction // Bad - // _ef = :extends :final - function :extends :final int get_ef; return 1; endfunction // Bad - // _i = :initial - function :initial int get_i; return 1; endfunction - function :initial int get_i_n; return 1; endfunction - function :initial int get_i_e; return 1; endfunction - function :initial int get_i_ef; return 1; endfunction - function :initial int get_i_i; return 1; endfunction - function :initial int get_i_if; return 1; endfunction - function :initial int get_i_f; return 1; endfunction - // _if = :initial :final - function :initial :final int get_if; return 1; endfunction - function :initial :final int get_if_n; return 1; endfunction - function :initial :final int get_if_e; return 1; endfunction - function :initial :final int get_if_ef; return 1; endfunction - function :initial :final int get_if_i; return 1; endfunction - function :initial :final int get_if_if; return 1; endfunction - function :initial :final int get_if_f; return 1; endfunction - // _f = :final - function :final int get_f; return 1; endfunction - function :final int get_f_n; return 1; endfunction - function :final int get_f_e; return 1; endfunction - function :final int get_f_ef; return 1; endfunction - function :final int get_f_i; return 1; endfunction - function :final int get_f_if; return 1; endfunction - function :final int get_f_f; return 1; endfunction + // _X = non-existant + // _n = None + function int get_n; return 1; endfunction + function int get_n_n; return 1; endfunction + function int get_n_e; return 1; endfunction + function int get_n_ef; return 1; endfunction + function int get_n_i; return 1; endfunction + function int get_n_if; return 1; endfunction + function int get_n_f; return 1; endfunction + // _e = :extends + function :extends int get_e; return 1; endfunction // Bad + // _ef = :extends :final + function :extends :final int get_ef; return 1; endfunction // Bad + // _i = :initial + function :initial int get_i; return 1; endfunction + function :initial int get_i_n; return 1; endfunction + function :initial int get_i_e; return 1; endfunction + function :initial int get_i_ef; return 1; endfunction + function :initial int get_i_i; return 1; endfunction + function :initial int get_i_if; return 1; endfunction + function :initial int get_i_f; return 1; endfunction + // _if = :initial :final + function :initial :final int get_if; return 1; endfunction + function :initial :final int get_if_n; return 1; endfunction + function :initial :final int get_if_e; return 1; endfunction + function :initial :final int get_if_ef; return 1; endfunction + function :initial :final int get_if_i; return 1; endfunction + function :initial :final int get_if_if; return 1; endfunction + function :initial :final int get_if_f; return 1; endfunction + // _f = :final + function :final int get_f; return 1; endfunction + function :final int get_f_n; return 1; endfunction + function :final int get_f_e; return 1; endfunction + function :final int get_f_ef; return 1; endfunction + function :final int get_f_i; return 1; endfunction + function :final int get_f_if; return 1; endfunction + function :final int get_f_f; return 1; endfunction endclass class Cls extends Base; - // _X = non-existant - function int get_x_n; return 1; endfunction - function :extends int get_x_e; return 1; endfunction // Bad - function :extends :final int get_x_ef; return 1; endfunction // Bad - function :initial int get_x_i; return 1; endfunction - function :initial :final int get_x_if; return 1; endfunction - function :final int get_x_f; return 1; endfunction - // _n = None - function int get_n_n; return 1; endfunction - function :extends int get_n_e; return 1; endfunction - function :extends :final int get_n_ef; return 1; endfunction - function :initial int get_n_i; return 1; endfunction // Bad - function :initial :final int get_n_if; return 1; endfunction // Bad - function :final int get_n_f; return 1; endfunction - // _e = :extends - // _ef = :extends :final - // _i = :initial - function int get_i_n; return 1; endfunction - function :extends int get_i_e; return 1; endfunction - function :extends :final int get_i_ef; return 1; endfunction - function :initial int get_i_i; return 1; endfunction // Bad - function :initial :final int get_i_if; return 1; endfunction // Bad - function :final int get_i_f; return 1; endfunction - // _if = :initial :final - function int get_if_n; return 1; endfunction // Bad - function :extends int get_if_e; return 1; endfunction // Bad - function :extends :final int get_if_ef; return 1; endfunction // Bad - function :initial int get_if_i; return 1; endfunction // Bad - function :initial :final int get_if_if; return 1; endfunction // Bad - function :final int get_if_f; return 1; endfunction // Bad - // _f = :final - function int get_f_n; return 1; endfunction // Bad - function :extends int get_f_e; return 1; endfunction // Bad - function :extends :final int get_f_ef; return 1; endfunction // Bad - function :initial int get_f_i; return 1; endfunction // Bad - function :initial :final int get_f_if; return 1; endfunction // Bad - function :final int get_f_f; return 1; endfunction // Bad + // _X = non-existant + function int get_x_n; return 1; endfunction + function :extends int get_x_e; return 1; endfunction // Bad + function :extends :final int get_x_ef; return 1; endfunction // Bad + function :initial int get_x_i; return 1; endfunction + function :initial :final int get_x_if; return 1; endfunction + function :final int get_x_f; return 1; endfunction + // _n = None + function int get_n_n; return 1; endfunction + function :extends int get_n_e; return 1; endfunction + function :extends :final int get_n_ef; return 1; endfunction + function :initial int get_n_i; return 1; endfunction // Bad + function :initial :final int get_n_if; return 1; endfunction // Bad + function :final int get_n_f; return 1; endfunction + // _e = :extends + // _ef = :extends :final + // _i = :initial + function int get_i_n; return 1; endfunction + function :extends int get_i_e; return 1; endfunction + function :extends :final int get_i_ef; return 1; endfunction + function :initial int get_i_i; return 1; endfunction // Bad + function :initial :final int get_i_if; return 1; endfunction // Bad + function :final int get_i_f; return 1; endfunction + // _if = :initial :final + function int get_if_n; return 1; endfunction // Bad + function :extends int get_if_e; return 1; endfunction // Bad + function :extends :final int get_if_ef; return 1; endfunction // Bad + function :initial int get_if_i; return 1; endfunction // Bad + function :initial :final int get_if_if; return 1; endfunction // Bad + function :final int get_if_f; return 1; endfunction // Bad + // _f = :final + function int get_f_n; return 1; endfunction // Bad + function :extends int get_f_e; return 1; endfunction // Bad + function :extends :final int get_f_ef; return 1; endfunction // Bad + function :initial int get_f_i; return 1; endfunction // Bad + function :initial :final int get_f_if; return 1; endfunction // Bad + function :final int get_f_f; return 1; endfunction // Bad endclass class CBase; @@ -102,15 +103,15 @@ class :final CClsBadExtendsFinal extends CClsF; endclass module t; - initial begin - Cls c; - CClsF cc; + initial begin + Cls c; + CClsF cc; - if (c != null) $stop; - c = new; - cc = new; + if (c != null) $stop; + c = new; + cc = new; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_package.v b/test_regress/t/t_class_package.v index 20765e149..f7938b8d4 100644 --- a/test_regress/t/t_class_package.v +++ b/test_regress/t/t_class_package.v @@ -7,41 +7,47 @@ package pkga; int pvar; class MyClass; - int member; - function int getpvar(); return pvar; endfunction + int member; + function int getpvar(); + return pvar; + endfunction endclass endpackage package pkgb; int pvar; class MyClass; - int member; - function int getpvar(); return pvar; endfunction - function int getavar(); return pkga::pvar; endfunction + int member; + function int getpvar(); + return pvar; + endfunction + function int getavar(); + return pkga::pvar; + endfunction endclass endpackage module t; - initial begin - pkga::MyClass a; - pkgb::MyClass b; + initial begin + pkga::MyClass a; + pkgb::MyClass b; - pkga::pvar = 100; - pkgb::pvar = 200; - if (pkga::pvar != 100) $stop; - if (pkgb::pvar != 200) $stop; + pkga::pvar = 100; + pkgb::pvar = 200; + if (pkga::pvar != 100) $stop; + if (pkgb::pvar != 200) $stop; - a = new; - b = new; - a.member = 10; - b.member = 20; - if (a.member != 10) $stop; - if (b.member != 20) $stop; + a = new; + b = new; + a.member = 10; + b.member = 20; + if (a.member != 10) $stop; + if (b.member != 20) $stop; - if (a.getpvar() != 100) $stop; - if (b.getpvar() != 200) $stop; - if (b.getavar() != 100) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (a.getpvar() != 100) $stop; + if (b.getpvar() != 200) $stop; + if (b.getavar() != 100) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_packed.v b/test_regress/t/t_class_packed.v index 3c603879e..3749937ed 100644 --- a/test_regress/t/t_class_packed.v +++ b/test_regress/t/t_class_packed.v @@ -4,37 +4,33 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - //TODO sub #(.WIDTH(1)) w1(); - //TODO sub #(.WIDTH(2)) w2(); - //TODO sub #(.WIDTH(3)) w3(); - //TODO sub #(.WIDTH(4)) w4(); - sub #(.WIDTH(5)) w5(); + //TODO sub #(.WIDTH(1)) w1(); + //TODO sub #(.WIDTH(2)) w2(); + //TODO sub #(.WIDTH(3)) w3(); + //TODO sub #(.WIDTH(4)) w4(); + sub #(.WIDTH(5)) w5 (); - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub (); - parameter WIDTH=5; // WIDTH >= 5 fails. WIDTH <= 4 passes + parameter WIDTH = 5; // WIDTH >= 5 fails. WIDTH <= 4 passes - typedef struct packed { - logic [WIDTH-1:0] data; - } [15:0] w_t; + typedef struct packed {logic [WIDTH-1:0] data;} [15:0] w_t; - class WrReqQ; - w_t w; - endclass + class WrReqQ; + w_t w; + endclass - initial begin - if ($bits(w_t) != WIDTH * 16) $stop; - end + initial begin + if ($bits(w_t) != WIDTH * 16) $stop; + end endmodule diff --git a/test_regress/t/t_class_param.v b/test_regress/t/t_class_param.v index 8b00ad6d1..c73600566 100644 --- a/test_regress/t/t_class_param.v +++ b/test_regress/t/t_class_param.v @@ -4,131 +4,154 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on // See also t_class_param_mod.v typedef class Cls; -class Wrap #(parameter P = 13); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Cls#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last +class Wrap #( + parameter P = 13 +); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Cls #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last endclass -class Wrap2 #(parameter P = 35); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Wrap#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last +class Wrap2 #( + parameter P = 35 +); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Wrap #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last endclass -class Cls #(parameter PBASE = 12); - bit [PBASE-1:0] member; - function bit [PBASE-1:0] get_member; - return member; - endfunction - static function int get_p; - return PBASE; - endfunction - typedef enum { E_PBASE = PBASE } enum_t; - class ClsInner; - bit [PBASE-1:0] member; - endclass +class Cls #( + parameter PBASE = 12 +); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum {E_PBASE = PBASE} enum_t; + class ClsInner; + bit [PBASE-1:0] member; + endclass endclass typedef Cls#(8) Cls8_t; -class SelfRefClassTypeParam #(type T=logic); - typedef SelfRefClassTypeParam #(int) self_int_t; - T field; +class SelfRefClassTypeParam #( + type T = logic +); + typedef SelfRefClassTypeParam#(int) self_int_t; + T field; endclass -class SelfRefClassIntParam #(int P=1); - typedef SelfRefClassIntParam #(10) self_int_t; +class SelfRefClassIntParam #( + int P = 1 +); + typedef SelfRefClassIntParam#(10) self_int_t; endclass -class Sum #(type T); - static int sum; - static function void add(T element); - sum += int'(element); - endfunction +class Sum #( + type T +); + static int sum; + static function void add(T element); + sum += int'(element); + endfunction endclass class IntQueue; - int q[$]; - function int getSum(); - foreach(q[i]) - Sum#(int)::add(q[i]); - return Sum#(int)::sum; - endfunction + int q[$]; + function int getSum(); + foreach (q[i]) Sum#(int)::add(q[i]); + return Sum#(int)::sum; + endfunction endclass class ClsStatic; - static int x = 1; - static function int get_2; - return 2; - endfunction + static int x = 1; + static function int get_2; + return 2; + endfunction endclass -class ClsParam #(type T); - typedef T param_t; +class ClsParam #( + type T +); + typedef T param_t; endclass class ClsWithParamField; - int m_field = Sum#(int)::sum; - int m_queue[$]; + int m_field = Sum#(int)::sum; + int m_queue[$]; - function int get(int index); - return m_queue[index]; - endfunction + function int get(int index); + return m_queue[index]; + endfunction endclass class DictWrapper; - int m_dict[string]; + int m_dict[string]; endclass -class DictOperator #(type T) extends T; - function void set(string s, int x); - m_dict[s] = x; - endfunction +class DictOperator #( + type T +) extends T; + function void set(string s, int x); + m_dict[s] = x; + endfunction - function int get(string s); - return m_dict[s]; - endfunction + function int get(string s); + return m_dict[s]; + endfunction endclass -class Getter1 #(int T=0); - static function int get_1(); - return Getter1#(1)::T; - endfunction +class Getter1 #( + int T = 0 +); + static function int get_1(); + return Getter1#(1)::T; + endfunction endclass -class Getter2 #(int T=5); - static function int get_T(); - return T; - endfunction +class Getter2 #( + int T = 5 +); + static function int get_T(); + return T; + endfunction - static function int get_2(); - return Getter2#(2)::get_T(); - endfunction + static function int get_2(); + return Getter2#(2)::get_T(); + endfunction endclass -class ClsParamString #(string S="abcde"); - typedef ClsParamString#(S) this_type; - static this_type m_inst; - int x = 0; - string name = S; +class ClsParamString #( + string S = "abcde" +); + typedef ClsParamString#(S) this_type; + static this_type m_inst; + int x = 0; + string name = S; endclass typedef ClsParamString#("abcde") cls_param_string_def_t; @@ -136,127 +159,127 @@ typedef ClsParamString#("xyz") cls_param_string_not_def_t; module t; - Cls c12; - Cls #(.PBASE(4)) c4; - Cls8_t c8; - Cls#()::ClsInner ci; - Cls#(8)::ClsInner ci8; - Wrap #(.P(16)) w16; - Wrap2 #(.P(32)) w32; - SelfRefClassTypeParam src_logic; - SelfRefClassTypeParam#()::self_int_t src_int; - SelfRefClassIntParam src1; - SelfRefClassIntParam#()::self_int_t src10; - IntQueue qi; - ClsWithParamField cls_param_field; - DictOperator #(DictWrapper) dict_op; - Getter1 getter1; - Getter1 #(1) getter1_param_1; - Getter2 getter2; - cls_param_string_def_t cps_def; - cls_param_string_not_def_t cps_not_def; - int arr [1:0] = '{1, 2}; - initial begin - c12 = new; - c4 = new; - c8 = new; - ci = new; - ci8 = new; - w16 = new; - w32 = new; - src_int = new; - src_logic = new; - src1 = new; - src10 = new; - qi = new; - cls_param_field = new; - dict_op = new; - getter1 = new; - getter1_param_1 = new; - getter2 = new; + Cls c12; + Cls #(.PBASE(4)) c4; + Cls8_t c8; + Cls #()::ClsInner ci; + Cls #(8)::ClsInner ci8; + Wrap #(.P(16)) w16; + Wrap2 #(.P(32)) w32; + SelfRefClassTypeParam src_logic; + SelfRefClassTypeParam #()::self_int_t src_int; + SelfRefClassIntParam src1; + SelfRefClassIntParam #()::self_int_t src10; + IntQueue qi; + ClsWithParamField cls_param_field; + DictOperator #(DictWrapper) dict_op; + Getter1 getter1; + Getter1 #(1) getter1_param_1; + Getter2 getter2; + cls_param_string_def_t cps_def; + cls_param_string_not_def_t cps_not_def; + int arr[1:0] = '{1, 2}; + initial begin + c12 = new; + c4 = new; + c8 = new; + ci = new; + ci8 = new; + w16 = new; + w32 = new; + src_int = new; + src_logic = new; + src1 = new; + src10 = new; + qi = new; + cls_param_field = new; + dict_op = new; + getter1 = new; + getter1_param_1 = new; + getter2 = new; - if (Cls#()::PBASE != 12) $stop; - if (Cls#(4)::PBASE != 4) $stop; - if (Cls8_t::PBASE != 8) $stop; + if (Cls#()::PBASE != 12) $stop; + if (Cls#(4)::PBASE != 4) $stop; + if (Cls8_t::PBASE != 8) $stop; - if (Cls#()::E_PBASE != 12) $stop; - if (Cls#(4)::E_PBASE != 4) $stop; - if (Cls8_t::E_PBASE != 8) $stop; + if (Cls#()::E_PBASE != 12) $stop; + if (Cls#(4)::E_PBASE != 4) $stop; + if (Cls8_t::E_PBASE != 8) $stop; - if (c12.PBASE != 12) $stop; - if (c4.PBASE != 4) $stop; - if (c8.PBASE != 8) $stop; + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; - if (Cls#()::get_p() != 12) $stop; - if (Cls#(4)::get_p() != 4) $stop; - if (Cls8_t::get_p() != 8) $stop; + if (Cls#()::get_p() != 12) $stop; + if (Cls#(4)::get_p() != 4) $stop; + if (Cls8_t::get_p() != 8) $stop; - if (c12.get_p() != 12) $stop; - if (c4.get_p() != 4) $stop; - if (c8.get_p() != 8) $stop; - if (w16.get_p() != 16) $stop; - if (w32.get_p() != 32) $stop; + if (c12.get_p() != 12) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + if (w32.get_p() != 32) $stop; - // verilator lint_off WIDTH - c12.member = 32'haaaaaaaa; - c4.member = 32'haaaaaaaa; - c8.member = 32'haaaaaaaa; - // verilator lint_on WIDTH - ci.member = 12'haaa; - ci8.member = 8'hff; - if (ci.member != 12'haaa) $stop; - if (ci8.member != 8'hff) $stop; - if (c12.member != 12'haaa) $stop; - if (c4.member != 4'ha) $stop; - if (c12.get_member() != 12'haaa) $stop; - if (c4.get_member() != 4'ha) $stop; - `checkp(c12, "'{member:'haaa}"); - `checkp(c4, "'{member:'ha}"); + // verilator lint_off WIDTH + c12.member = 32'haaaaaaaa; + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + ci.member = 12'haaa; + ci8.member = 8'hff; + if (ci.member != 12'haaa) $stop; + if (ci8.member != 8'hff) $stop; + if (c12.member != 12'haaa) $stop; + if (c4.member != 4'ha) $stop; + if (c12.get_member() != 12'haaa) $stop; + if (c4.get_member() != 4'ha) $stop; + `checkp(c12, "'{member:'haaa}"); + `checkp(c4, "'{member:'ha}"); - if ($bits(src_logic.field) != 1) $stop; - if ($bits(src_int.field) != 32) $stop; - if (src1.P != 1) $stop; - if (src10.P != 10) $stop; + if ($bits(src_logic.field) != 1) $stop; + if ($bits(src_int.field) != 32) $stop; + if (src1.P != 1) $stop; + if (src10.P != 10) $stop; - qi.q = '{2, 4, 6, 0, 2}; - if (qi.getSum() != 14) $stop; - Sum#(int)::add(arr[0]); - if (Sum#(int)::sum != 16) $stop; + qi.q = '{2, 4, 6, 0, 2}; + if (qi.getSum() != 14) $stop; + Sum#(int)::add(arr[0]); + if (Sum#(int)::sum != 16) $stop; - if (Sum#(real)::sum != 0) $stop; - Sum#(real)::add(1.9); // rounds - if (Sum#(real)::sum != 2) $stop; + if (Sum#(real)::sum != 0) $stop; + Sum#(real)::add(1.9); // rounds + if (Sum#(real)::sum != 2) $stop; - if (ClsParam#(ClsStatic)::param_t::x != 1) $stop; - if (ClsParam#(ClsStatic)::param_t::get_2() != 2) $stop; + if (ClsParam#(ClsStatic)::param_t::x != 1) $stop; + if (ClsParam#(ClsStatic)::param_t::get_2() != 2) $stop; - cls_param_field.m_queue = '{1, 5, 7}; - if (cls_param_field.get(2) != 7) $stop; + cls_param_field.m_queue = '{1, 5, 7}; + if (cls_param_field.get(2) != 7) $stop; - dict_op.set("abcd", 1); - if (dict_op.get("abcd") != 1) $stop; + dict_op.set("abcd", 1); + if (dict_op.get("abcd") != 1) $stop; - if (getter1.get_1() != 1) $stop; - if (Getter1#()::get_1() != 1) $stop; - if (getter1_param_1.get_1() != 1) $stop; + if (getter1.get_1() != 1) $stop; + if (Getter1#()::get_1() != 1) $stop; + if (getter1_param_1.get_1() != 1) $stop; - if (getter2.get_2() != 2) $stop; - if (Getter2#()::get_2() != 2) $stop; - if (Getter2#(2)::get_2() != 2) $stop; + if (getter2.get_2() != 2) $stop; + if (Getter2#()::get_2() != 2) $stop; + if (Getter2#(2)::get_2() != 2) $stop; - cls_param_string_def_t::m_inst = new; - cls_param_string_def_t::m_inst.x = 1; - cps_def = cls_param_string_def_t::m_inst; - if (cps_def.x != 1) $stop; - if (cps_def.name != "abcde") $stop; + cls_param_string_def_t::m_inst = new; + cls_param_string_def_t::m_inst.x = 1; + cps_def = cls_param_string_def_t::m_inst; + if (cps_def.x != 1) $stop; + if (cps_def.name != "abcde") $stop; - cls_param_string_not_def_t::m_inst = new; - cls_param_string_not_def_t::m_inst.x = 2; - cps_not_def = cls_param_string_not_def_t::m_inst; - if (cps_not_def.x != 2) $stop; - if (cps_not_def.name != "xyz") $stop; + cls_param_string_not_def_t::m_inst = new; + cls_param_string_not_def_t::m_inst.x = 2; + cps_not_def = cls_param_string_not_def_t::m_inst; + if (cps_not_def.x != 2) $stop; + if (cps_not_def.name != "xyz") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_bad1.out b/test_regress/t/t_class_param_bad1.out index 55071fadd..ba6c8812c 100644 --- a/test_regress/t/t_class_param_bad1.out +++ b/test_regress/t/t_class_param_bad1.out @@ -1,9 +1,9 @@ -%Error-PINNOTFOUND: t/t_class_param_bad1.v:12:11: Parameter not found: 'PARAMBAD' +%Error-PINNOTFOUND: t/t_class_param_bad1.v:14:10: Parameter not found: 'PARAMBAD' : ... Suggested alternative: 'PARAMB' - 12 | Cls #(.PARAMBAD(1)) c; - | ^~~~~~~~ + 14 | Cls #(.PARAMBAD(1)) c; + | ^~~~~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest -%Error-PINNOTFOUND: t/t_class_param_bad1.v:13:14: Parameter not found: '__paramNumber2' - 13 | Cls #(13, 1) cd; - | ^ +%Error-PINNOTFOUND: t/t_class_param_bad1.v:15:13: Parameter not found: '__paramNumber2' + 15 | Cls #(13, 1) cd; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_bad1.v b/test_regress/t/t_class_param_bad1.v index 239c1bf8c..ff4ecd620 100644 --- a/test_regress/t/t_class_param_bad1.v +++ b/test_regress/t/t_class_param_bad1.v @@ -4,12 +4,14 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class Cls #(parameter PARAMB = 12); +class Cls #( + parameter PARAMB = 12 +); endclass module t; - Cls #(.PARAMBAD(1)) c; // Bad param name - Cls #(13, 1) cd; // Bad param number + Cls #(.PARAMBAD(1)) c; // Bad param name + Cls #(13, 1) cd; // Bad param number endmodule diff --git a/test_regress/t/t_class_param_bad2.out b/test_regress/t/t_class_param_bad2.out index 466fd5e5d..64ccff158 100644 --- a/test_regress/t/t_class_param_bad2.out +++ b/test_regress/t/t_class_param_bad2.out @@ -1,10 +1,10 @@ -%Error: t/t_class_param_bad2.v:12:4: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' +%Error: t/t_class_param_bad2.v:14:3: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' : ... note: In instance 't' - 12 | Cls c; - | ^~~ + 14 | Cls c; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_param_bad2.v:7:18: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' +%Error: t/t_class_param_bad2.v:8:10: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' : ... note: In instance 't' - 7 | class Cls #(type PARAMB); - | ^~~~~~ + 8 | type PARAMB + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_bad2.v b/test_regress/t/t_class_param_bad2.v index b46548e94..c3d416fa1 100644 --- a/test_regress/t/t_class_param_bad2.v +++ b/test_regress/t/t_class_param_bad2.v @@ -4,11 +4,13 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Cls #(type PARAMB); +class Cls #( + type PARAMB +); endclass module t; - Cls c; // Missing type param + Cls c; // Missing type param endmodule diff --git a/test_regress/t/t_class_param_circ_bad.out b/test_regress/t/t_class_param_circ_bad.out index dd1d3c695..cf34235f0 100644 --- a/test_regress/t/t_class_param_circ_bad.out +++ b/test_regress/t/t_class_param_circ_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_param_circ_bad.v:14:4: Exceeded maximum --module-recursion-depth of 100 +%Error: t/t_class_param_circ_bad.v:18:3: Exceeded maximum --module-recursion-depth of 100 : ... note: In instance 't' - 14 | ClsA #(PARAM+1) a; - | ^~~~ + 18 | ClsA #(PARAM + 1) a; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_param_circ_bad.v b/test_regress/t/t_class_param_circ_bad.v index 7f7622c1a..ac4a929ea 100644 --- a/test_regress/t/t_class_param_circ_bad.v +++ b/test_regress/t/t_class_param_circ_bad.v @@ -6,16 +6,20 @@ typedef class ClsB; -class ClsA #(parameter PARAM = 12); - ClsB #(PARAM+1) b; +class ClsA #( + parameter PARAM = 12 +); + ClsB #(PARAM + 1) b; endclass -class ClsB #(parameter PARAM = 12); - ClsA #(PARAM+1) a; +class ClsB #( + parameter PARAM = 12 +); + ClsA #(PARAM + 1) a; endclass module t; - ClsA #(.PARAM(15)) c; // Bad param name + ClsA #(.PARAM(15)) c; // Bad param name endmodule diff --git a/test_regress/t/t_class_param_comma_bad.out b/test_regress/t/t_class_param_comma_bad.out index 05bdbaff7..322dab93a 100644 --- a/test_regress/t/t_class_param_comma_bad.out +++ b/test_regress/t/t_class_param_comma_bad.out @@ -1,17 +1,17 @@ -%Error: t/t_class_param_comma_bad.v:16:22: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 16 | Cls #(.PARAMB(14),) ce; - | ^ +%Error: t/t_class_param_comma_bad.v:16:21: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 16 | Cls #(.PARAMB(14),) ce; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_param_comma_bad.v:17:13: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 17 | Cls #(14,) cf; +%Error: t/t_class_param_comma_bad.v:17:12: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 17 | Cls #(14,) cf; + | ^ +%Error: t/t_class_param_comma_bad.v:18:13: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 18 | Cls2 #(15,) cg; | ^ -%Error: t/t_class_param_comma_bad.v:18:14: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 18 | Cls2 #(15,) cg; - | ^ -%Error: t/t_class_param_comma_bad.v:19:23: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 19 | Cls2 #(.PARAMB(16),) ch; - | ^ -%Error: t/t_class_param_comma_bad.v:20:23: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 20 | Cls2 #(.PARAMC(17),) ci; - | ^ +%Error: t/t_class_param_comma_bad.v:19:22: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 19 | Cls2 #(.PARAMB(16),) ch; + | ^ +%Error: t/t_class_param_comma_bad.v:20:22: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 20 | Cls2 #(.PARAMC(17),) ci; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_comma_bad.v b/test_regress/t/t_class_param_comma_bad.v index 1c4c0a7e0..8309388f4 100644 --- a/test_regress/t/t_class_param_comma_bad.v +++ b/test_regress/t/t_class_param_comma_bad.v @@ -11,12 +11,12 @@ endclass module t; - Cls #(.PARAMBAD(1)) c; // Bad param name - Cls #(13, 1) cd; // Bad param number - Cls #(.PARAMB(14),) ce; // Bad superfluous comma - Cls #(14,) cf; // Bad superfluous comma - Cls2 #(15,) cg; // Bad superfluous comma - Cls2 #(.PARAMB(16),) ch; // Bad superfluous comma - Cls2 #(.PARAMC(17),) ci; // Bad superfluous comma + Cls #(.PARAMBAD(1)) c; // Bad param name + Cls #(13, 1) cd; // Bad param number + Cls #(.PARAMB(14),) ce; // Bad superfluous comma + Cls #(14,) cf; // Bad superfluous comma + Cls2 #(15,) cg; // Bad superfluous comma + Cls2 #(.PARAMB(16),) ch; // Bad superfluous comma + Cls2 #(.PARAMC(17),) ci; // Bad superfluous comma endmodule diff --git a/test_regress/t/t_class_param_enum.v b/test_regress/t/t_class_param_enum.v index 8a7821bc2..ed6c922d1 100644 --- a/test_regress/t/t_class_param_enum.v +++ b/test_regress/t/t_class_param_enum.v @@ -4,23 +4,28 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -typedef enum bit {A = 0, B = 1} enum_t; +typedef enum bit { + A = 0, + B = 1 +} enum_t; -class Converter #(type T); - function int toInt(T t); - return int'(t); - endfunction +class Converter #( + type T +); + function int toInt(T t); + return int'(t); + endfunction endclass module t; - initial begin - automatic Converter#(enum_t) conv1 = new; - automatic Converter#(bit) conv2 = new; + initial begin + automatic Converter #(enum_t) conv1 = new; + automatic Converter #(bit) conv2 = new; - if (conv1.toInt(A) != 0) $stop; - if (conv2.toInt(1) != 1) $stop; + if (conv1.toInt(A) != 0) $stop; + if (conv2.toInt(1) != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_enum_bad.out b/test_regress/t/t_class_param_enum_bad.out index 1367e3acb..27e909152 100644 --- a/test_regress/t/t_class_param_enum_bad.out +++ b/test_regress/t/t_class_param_enum_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_class_param_enum_bad.v:20:41: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1' +%Error: t/t_class_param_enum_bad.v:25:40: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1' : ... note: In instance 't' - 20 | automatic Converter#(bit) conv2 = conv1; - | ^~~~~ + 25 | automatic Converter #(bit) conv2 = conv1; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-ENUMVALUE: t/t_class_param_enum_bad.v:21:19: Implicit conversion to enum 'enum{}$unit::enum_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) +%Error-ENUMVALUE: t/t_class_param_enum_bad.v:26:17: Implicit conversion to enum 'enum{}$unit::enum_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast - 21 | conv1.toInt(0); - | ^ + 26 | conv1.toInt(0); + | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_param_enum_bad.v b/test_regress/t/t_class_param_enum_bad.v index b7215093e..9b4e7169e 100644 --- a/test_regress/t/t_class_param_enum_bad.v +++ b/test_regress/t/t_class_param_enum_bad.v @@ -4,21 +4,26 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -typedef enum bit {A = 0, B = 1} enum_t; +typedef enum bit { + A = 0, + B = 1 +} enum_t; -class Converter #(type T); - function int toInt(T t); - return int'(t); - endfunction +class Converter #( + type T +); + function int toInt(T t); + return int'(t); + endfunction endclass module t; - initial begin - automatic Converter#(enum_t) conv1 = new; - // enum types does not match with other types (IEEE 1800-2023 6.22.1 and 6.22.4) - // The assignment and the function call should throw an error. - automatic Converter#(bit) conv2 = conv1; - conv1.toInt(0); - $stop; - end + initial begin + automatic Converter #(enum_t) conv1 = new; + // enum types does not match with other types (IEEE 1800-2023 6.22.1 and 6.22.4) + // The assignment and the function call should throw an error. + automatic Converter #(bit) conv2 = conv1; + conv1.toInt(0); + $stop; + end endmodule diff --git a/test_regress/t/t_class_param_extends.v b/test_regress/t/t_class_param_extends.v index fce412cfa..2d515c882 100644 --- a/test_regress/t/t_class_param_extends.v +++ b/test_regress/t/t_class_param_extends.v @@ -6,90 +6,98 @@ // Code your testbench here // or browse Examples -class Base #(parameter PBASE = 12); - bit [PBASE-1:0] member; +class Base #( + parameter PBASE = 12 +); + bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; - return member; - endfunction - function int get_p; - return PBASE; - endfunction + return member; + endfunction + function int get_p; + return PBASE; + endfunction endclass -class Cls #(parameter P = 13) extends Base #(P); +class Cls #( + parameter P = 13 +) extends Base #(P); endclass typedef Cls#(8) Cls8_t; class Getter1; - function int get_int; - return 1; - endfunction + function int get_int; + return 1; + endfunction endclass class Getter2; - function int get_int; - return 2; - endfunction + function int get_int; + return 2; + endfunction endclass -class Foo #(type T=Getter1); - T foo_field; - int x; - function new(int y); - foo_field = new; - x = y; - endfunction +class Foo #( + type T = Getter1 +); + T foo_field; + int x; + function new(int y); + foo_field = new; + x = y; + endfunction endclass -class Bar #(type S=Getter2) extends Foo#(S); - T field; - function new(int y); - super.new(y); - field = new; - endfunction +class Bar #( + type S = Getter2 +) extends Foo #(S); + T field; + function new(int y); + super.new(y); + field = new; + endfunction - function int get_field_int; - return field.get_int(); - endfunction + function int get_field_int; + return field.get_int(); + endfunction - function int get_foo_field_int; - return foo_field.get_int(); - endfunction + function int get_foo_field_int; + return foo_field.get_int(); + endfunction endclass // See also t_class_param_mod.v module t; - Cls #(.P(4)) c4; - Cls8_t c8; - Bar b; + Cls #(.P(4)) c4; + Cls8_t c8; + Bar b; - initial begin - c4 = new; - c8 = new; - b = new(1); - if (c4.PBASE != 4) $stop; - if (c8.PBASE != 8) $stop; - if (c4.get_p() != 4) $stop; - if (c8.get_p() != 8) $stop; - // verilator lint_off WIDTH - c4.member = 32'haaaaaaaa; - c8.member = 32'haaaaaaaa; - // verilator lint_on WIDTH - if (c4.member != 4'ha) $stop; - if (c4.get_member() != 4'ha) $stop; - if (c8.member != 8'haa) $stop; - if (c8.get_member() != 8'haa) $stop; - $display("c4 = %s", $sformatf("%p", c4)); - if ($sformatf("%p", c4) != "'{member:'ha}") $stop; + initial begin + c4 = new; + c8 = new; + b = new(1); + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + // verilator lint_off WIDTH + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + if (c4.member != 4'ha) $stop; + if (c4.get_member() != 4'ha) $stop; + if (c8.member != 8'haa) $stop; + if (c8.get_member() != 8'haa) $stop; + $display("c4 = %s", $sformatf("%p", c4)); + if ($sformatf("%p", c4) != "'{member:'ha}") $stop; - if (b.x != 1) $stop; - if (b.get_field_int() != 2) $stop; - if (b.get_foo_field_int() != 2) $stop; + if (b.x != 1) $stop; + if (b.get_field_int() != 2) $stop; + if (b.get_foo_field_int() != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_extends2.v b/test_regress/t/t_class_param_extends2.v index 1158d689a..564ca6c05 100644 --- a/test_regress/t/t_class_param_extends2.v +++ b/test_regress/t/t_class_param_extends2.v @@ -4,35 +4,39 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Foo #(type T=bit); - int x = $bits(T); +class Foo #( + type T = bit +); + int x = $bits(T); endclass -class Bar #(type S=int) extends Foo#(S); +class Bar #( + type S = int +) extends Foo #(S); endclass typedef Bar#() bar_default_t; class Baz; - Bar#(logic[7:0]) bar_string; - int bar_x; - function new; - bar_string = new; - bar_x = bar_string.x; - endfunction + Bar #(logic [7:0]) bar_string; + int bar_x; + function new; + bar_string = new; + bar_x = bar_string.x; + endfunction endclass typedef Baz baz_t; module t; - initial begin - automatic bar_default_t bar_default = new; - automatic baz_t baz = new; + initial begin + automatic bar_default_t bar_default = new; + automatic baz_t baz = new; - if (bar_default.x != 32) $stop; - if (baz.bar_x != 8) $stop; + if (bar_default.x != 32) $stop; + if (baz.bar_x != 8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_extends3.v b/test_regress/t/t_class_param_extends3.v index f728316e7..ea86bd7d8 100644 --- a/test_regress/t/t_class_param_extends3.v +++ b/test_regress/t/t_class_param_extends3.v @@ -5,60 +5,68 @@ // SPDX-License-Identifier: CC0-1.0 package u_pkg; - typedef class u_report_object; - typedef class u_callback; + typedef class u_report_object; + typedef class u_callback; - virtual class u_object; - endclass + virtual class u_object; + endclass - class u_queue #(type T=int) extends u_object; - int m_value = 6; - endclass + class u_queue #( + type T = int + ) extends u_object; + int m_value = 6; + endclass - class u_callbacks_base extends u_object; - typedef u_callbacks_base this_type; - endclass + class u_callbacks_base extends u_object; + typedef u_callbacks_base this_type; + endclass - class u_typed_callbacks#(type T=u_object) extends u_callbacks_base; - typedef u_typed_callbacks#(T) this_type; - static this_type m_t_inst; - static u_queue#(u_callback) m_tw_cb_q; - endclass + class u_typed_callbacks #( + type T = u_object + ) extends u_callbacks_base; + typedef u_typed_callbacks#(T) this_type; + static this_type m_t_inst; + static u_queue #(u_callback) m_tw_cb_q; + endclass - class u_callbacks #(type T=u_object, type CB=u_callback) - extends u_typed_callbacks#(T); - static function bit m_register_pair(); - return 1'b0; - endfunction - static function void add(u_callback cb); - u_queue#(u_callback) qr; - qr = u_callbacks#(u_report_object,u_callback)::m_t_inst.m_tw_cb_q; //<<<< - if (qr.m_value != 6) $stop; - endfunction - endclass + class u_callbacks #( + type T = u_object, + type CB = u_callback + ) extends u_typed_callbacks #(T); + static function bit m_register_pair(); + return 1'b0; + endfunction + static function void add(u_callback cb); + u_queue #(u_callback) qr; + qr = u_callbacks#(u_report_object, u_callback)::m_t_inst.m_tw_cb_q; //<<<< + if (qr.m_value != 6) $stop; + endfunction + endclass - class u_callback extends u_object; - endclass + class u_callback extends u_object; + endclass - virtual class u_report_catcher extends u_callback; - static local bit m_register_cb_u_report_catcher = u_callbacks#(u_report_object,u_report_catcher)::m_register_pair(); - endclass + virtual class u_report_catcher extends u_callback; + static local + bit + m_register_cb_u_report_catcher = u_callbacks#(u_report_object,u_report_catcher)::m_register_pair(); + endclass - // Having this class (versus using #(u_object) is needed to hit the bug - class u_report_object extends u_object; - endclass + // Having this class (versus using #(u_object) is needed to hit the bug + class u_report_object extends u_object; + endclass endpackage module t; - u_pkg::u_callback cb; + u_pkg::u_callback cb; - initial begin - cb = new; + initial begin + cb = new; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_extra_bad.out b/test_regress/t/t_class_param_extra_bad.out index 65b1d443e..671e733fa 100644 --- a/test_regress/t/t_class_param_extra_bad.out +++ b/test_regress/t/t_class_param_extra_bad.out @@ -1,11 +1,11 @@ -%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:21: Parameter not found: '__paramNumber1' - 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; - | ^~~ +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:20: Parameter not found: '__paramNumber1' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest -%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:26: Parameter not found: '__paramNumber2' - 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; - | ^~~~~~~ -%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:35: Parameter not found: '__paramNumber3' - 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; - | ^~~~~~ +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:25: Parameter not found: '__paramNumber2' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~~~~~ +%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:34: Parameter not found: '__paramNumber3' + 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_extra_bad.v b/test_regress/t/t_class_param_extra_bad.v index 6548e5f74..be74a9e8a 100644 --- a/test_regress/t/t_class_param_extra_bad.v +++ b/test_regress/t/t_class_param_extra_bad.v @@ -6,10 +6,10 @@ module t; - class Cls1; - typedef bit bool_t; - endclass + class Cls1; + typedef bit bool_t; + endclass - localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; + localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; endmodule diff --git a/test_regress/t/t_class_param_func_return.v b/test_regress/t/t_class_param_func_return.v index 23f15377e..a9d1fe5cd 100644 --- a/test_regress/t/t_class_param_func_return.v +++ b/test_regress/t/t_class_param_func_return.v @@ -4,42 +4,44 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Foo #(type T=int); - typedef Foo default_type; - typedef Foo#(T) this_type; +class Foo #( + type T = int +); + typedef Foo default_type; + typedef Foo#(T) this_type; - T x; + T x; - function default_type get_default(); - default_type o = new; - return o; - endfunction + function default_type get_default(); + default_type o = new; + return o; + endfunction - function this_type get_this(); - this_type o = new; - return o; - endfunction + function this_type get_this(); + this_type o = new; + return o; + endfunction endclass module t; - Foo f_def1, f_def2; - Foo#(bit) f_bit1, f_bit2; - initial begin - f_def1 = new; - f_bit1 = new; + Foo f_def1, f_def2; + Foo #(bit) f_bit1, f_bit2; + initial begin + f_def1 = new; + f_bit1 = new; - f_def2 = f_def1.get_default(); - if ($bits(f_def2.x) != 32) $stop; - f_def2 = f_def1.get_this(); - if ($bits(f_def2.x) != 32) $stop; + f_def2 = f_def1.get_default(); + if ($bits(f_def2.x) != 32) $stop; + f_def2 = f_def1.get_this(); + if ($bits(f_def2.x) != 32) $stop; - f_def2 = f_bit1.get_default(); - if ($bits(f_def2.x) != 32) $stop; - f_bit2 = f_bit1.get_this(); - if ($bits(f_bit2.x) != 1) $stop; + f_def2 = f_bit1.get_default(); + if ($bits(f_def2.x) != 32) $stop; + f_bit2 = f_bit1.get_this(); + if ($bits(f_bit2.x) != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_lvalue.v b/test_regress/t/t_class_param_lvalue.v index b9af1b40f..a0a99c97c 100644 --- a/test_regress/t/t_class_param_lvalue.v +++ b/test_regress/t/t_class_param_lvalue.v @@ -7,7 +7,9 @@ class Foo; endclass -class Bar #(type BASE=Foo) extends BASE; +class Bar #( + type BASE = Foo +) extends BASE; task body(); int v = 0; v = 1; diff --git a/test_regress/t/t_class_param_mod.v b/test_regress/t/t_class_param_mod.v index dbd6a0620..17ca64fd2 100644 --- a/test_regress/t/t_class_param_mod.v +++ b/test_regress/t/t_class_param_mod.v @@ -4,116 +4,128 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on // See also t_class_param.v module t; -class Cls #(parameter PBASE = 12); - bit [PBASE-1:0] member; - function bit [PBASE-1:0] get_member; + class Cls #( + parameter PBASE = 12 + ); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; return member; - endfunction - static function int get_p; + endfunction + static function int get_p; return PBASE; - endfunction - typedef enum { E_PBASE = PBASE } enum_t; -endclass + endfunction + typedef enum {E_PBASE = PBASE} enum_t; + endclass -class Wrap #(parameter P = 13); - function int get_p; + class Wrap #( + parameter P = 13 + ); + function int get_p; return c1.get_p(); - endfunction - function new; + endfunction + function new; c1 = new; - endfunction - Cls#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last -endclass + endfunction + Cls #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last + endclass -class Wrap2 #(parameter P = 35); - function int get_p; + class Wrap2 #( + parameter P = 35 + ); + function int get_p; return c1.get_p(); - endfunction - function new; + endfunction + function new; c1 = new; - endfunction - Wrap#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last -endclass + endfunction + Wrap #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last + endclass - typedef Cls#(8) Cls8_t; + typedef Cls#(8) Cls8_t; -class SelfRefClassTypeParam #(type T=logic); - typedef SelfRefClassTypeParam #(int) self_int_t; - T field; -endclass + class SelfRefClassTypeParam #( + type T = logic + ); + typedef SelfRefClassTypeParam#(int) self_int_t; + T field; + endclass -class SelfRefClassIntParam #(int P=1); - typedef SelfRefClassIntParam #(10) self_int_t; -endclass + class SelfRefClassIntParam #( + int P = 1 + ); + typedef SelfRefClassIntParam#(10) self_int_t; + endclass - Cls c12; - Cls #(.PBASE(4)) c4; - Cls8_t c8; - Wrap #(.P(16)) w16; - Wrap2 #(.P(32)) w32; - SelfRefClassTypeParam src_logic; - SelfRefClassTypeParam#()::self_int_t src_int; - SelfRefClassIntParam src1; - SelfRefClassIntParam#()::self_int_t src10; - initial begin - c12 = new; - c4 = new; - c8 = new; - w16 = new; - w32 = new; - src_int = new; - src_logic = new; - src1 = new; - src10 = new; - if (Cls#()::PBASE != 12) $stop; - if (Cls#(4)::PBASE != 4) $stop; - if (Cls8_t::PBASE != 8) $stop; + Cls c12; + Cls #(.PBASE(4)) c4; + Cls8_t c8; + Wrap #(.P(16)) w16; + Wrap2 #(.P(32)) w32; + SelfRefClassTypeParam src_logic; + SelfRefClassTypeParam #()::self_int_t src_int; + SelfRefClassIntParam src1; + SelfRefClassIntParam #()::self_int_t src10; + initial begin + c12 = new; + c4 = new; + c8 = new; + w16 = new; + w32 = new; + src_int = new; + src_logic = new; + src1 = new; + src10 = new; + if (Cls#()::PBASE != 12) $stop; + if (Cls#(4)::PBASE != 4) $stop; + if (Cls8_t::PBASE != 8) $stop; - if (Cls#()::E_PBASE != 12) $stop; - if (Cls#(4)::E_PBASE != 4) $stop; - if (Cls8_t::E_PBASE != 8) $stop; + if (Cls#()::E_PBASE != 12) $stop; + if (Cls#(4)::E_PBASE != 4) $stop; + if (Cls8_t::E_PBASE != 8) $stop; - if (c12.PBASE != 12) $stop; - if (c4.PBASE != 4) $stop; - if (c8.PBASE != 8) $stop; + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; - if (Cls#()::get_p() != 12) $stop; - if (Cls#(4)::get_p() != 4) $stop; - if (Cls8_t::get_p() != 8) $stop; + if (Cls#()::get_p() != 12) $stop; + if (Cls#(4)::get_p() != 4) $stop; + if (Cls8_t::get_p() != 8) $stop; - if (c12.get_p() != 12) $stop; - if (c4.get_p() != 4) $stop; - if (c8.get_p() != 8) $stop; - if (w16.get_p() != 16) $stop; - if (w32.get_p() != 32) $stop; + if (c12.get_p() != 12) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + if (w32.get_p() != 32) $stop; - // verilator lint_off WIDTH - c12.member = 32'haaaaaaaa; - c4.member = 32'haaaaaaaa; - c8.member = 32'haaaaaaaa; - // verilator lint_on WIDTH - if (c12.member != 12'haaa) $stop; - if (c4.member != 4'ha) $stop; - if (c12.get_member() != 12'haaa) $stop; - if (c4.get_member() != 4'ha) $stop; - `checkp(c12, "'{member:'haaa}"); - `checkp(c4, "'{member:'ha}"); + // verilator lint_off WIDTH + c12.member = 32'haaaaaaaa; + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + if (c12.member != 12'haaa) $stop; + if (c4.member != 4'ha) $stop; + if (c12.get_member() != 12'haaa) $stop; + if (c4.get_member() != 4'ha) $stop; + `checkp(c12, "'{member:'haaa}"); + `checkp(c4, "'{member:'ha}"); - if ($bits(src_logic.field) != 1) $stop; - if ($bits(src_int.field) != 32) $stop; - if (src1.P != 1) $stop; - if (src10.P != 10) $stop; + if ($bits(src_logic.field) != 1) $stop; + if ($bits(src_int.field) != 32) $stop; + if (src1.P != 1) $stop; + if (src10.P != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_nconst_bad.out b/test_regress/t/t_class_param_nconst_bad.out index 45fe0e7de..8455daf98 100644 --- a/test_regress/t/t_class_param_nconst_bad.out +++ b/test_regress/t/t_class_param_nconst_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_class_param_nconst_bad.v:12:17: Expecting expression to be constant, but can't convert a RAND to constant. +%Error: t/t_class_param_nconst_bad.v:14:16: Expecting expression to be constant, but can't convert a RAND to constant. : ... note: In instance 't' - 12 | Cls #(.PARAM($random)) c; - | ^~~~~~~ + 14 | Cls #(.PARAM($random)) c; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_param_nconst_bad.v:12:11: Can't convert defparam value to constant: Param 'PARAM' of 'Cls' +%Error: t/t_class_param_nconst_bad.v:14:10: Can't convert defparam value to constant: Param 'PARAM' of 'Cls' : ... note: In instance 't' - 12 | Cls #(.PARAM($random)) c; - | ^~~~~ + 14 | Cls #(.PARAM($random)) c; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_nconst_bad.v b/test_regress/t/t_class_param_nconst_bad.v index ded86f95a..b797ff95d 100644 --- a/test_regress/t/t_class_param_nconst_bad.v +++ b/test_regress/t/t_class_param_nconst_bad.v @@ -4,11 +4,13 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class Cls #(parameter PARAM = 12); +class Cls #( + parameter PARAM = 12 +); endclass module t; - Cls #(.PARAM($random)) c; // Bad param name + Cls #(.PARAM($random)) c; // Bad param name endmodule diff --git a/test_regress/t/t_class_param_nested_bad.out b/test_regress/t/t_class_param_nested_bad.out index ec8a58f25..a3f0f32de 100644 --- a/test_regress/t/t_class_param_nested_bad.out +++ b/test_regress/t/t_class_param_nested_bad.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_class_param_nested_bad.v:51:23: dotted expressions in parameters +%Error-UNSUPPORTED: t/t_class_param_nested_bad.v:57:23: dotted expressions in parameters : ... note: In instance 't' : ... Suggest use a typedef - 51 | Wrap2 #(Wrap#(19)::PBASE * 2) w38; + 57 | Wrap2 #(Wrap #(19)::PBASE * 2) w38; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Internal Error: t/t_class_param_nested_bad.v:51:23: ../V3Width.cpp:#: Node has no type +%Error: Internal Error: t/t_class_param_nested_bad.v:57:23: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' - 51 | Wrap2 #(Wrap#(19)::PBASE * 2) w38; + 57 | Wrap2 #(Wrap #(19)::PBASE * 2) w38; | ^~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_class_param_nested_bad.v b/test_regress/t/t_class_param_nested_bad.v index e6d75cf4b..0aa2333b7 100644 --- a/test_regress/t/t_class_param_nested_bad.v +++ b/test_regress/t/t_class_param_nested_bad.v @@ -6,59 +6,65 @@ typedef class Cls; -class Wrap #(parameter P = 13); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Cls#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last +class Wrap #( + parameter P = 13 +); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Cls #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last endclass -class Wrap2 #(parameter P = 35); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Wrap#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last +class Wrap2 #( + parameter P = 35 +); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Wrap #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last endclass -class Cls #(parameter PBASE = 12); - bit [PBASE-1:0] member; - function bit [PBASE-1:0] get_member; - return member; - endfunction - static function int get_p; - return PBASE; - endfunction - typedef enum { E_PBASE = PBASE } enum_t; +class Cls #( + parameter PBASE = 12 +); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum {E_PBASE = PBASE} enum_t; endclass typedef Cls#(8) Cls8_t; module t; - Cls c12; - Cls #(.PBASE(4)) c4; - Cls8_t c8; - Wrap #(.P(16)) w16; - Wrap2 #(.P(32)) w32; - Wrap2 #(Wrap#(19)::PBASE * 2) w38; - initial begin - c12 = new; - c4 = new; - c8 = new; - w16 = new; - w32 = new; - w38 = new; - if (w38.get_p() != 38) $stop; + Cls c12; + Cls #(.PBASE(4)) c4; + Cls8_t c8; + Wrap #(.P(16)) w16; + Wrap2 #(.P(32)) w32; + Wrap2 #(Wrap #(19)::PBASE * 2) w38; + initial begin + c12 = new; + c4 = new; + c8 = new; + w16 = new; + w32 = new; + w38 = new; + if (w38.get_p() != 38) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_noinit.v b/test_regress/t/t_class_param_noinit.v index f17d5e9fb..f453887b3 100644 --- a/test_regress/t/t_class_param_noinit.v +++ b/test_regress/t/t_class_param_noinit.v @@ -5,13 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter -class Cls #(int A, int B); +class Cls #( + int A, + int B +); endclass module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_noinit_bad.out b/test_regress/t/t_class_param_noinit_bad.out index 6de7724b1..b2e6c32ec 100644 --- a/test_regress/t/t_class_param_noinit_bad.out +++ b/test_regress/t/t_class_param_noinit_bad.out @@ -1,14 +1,14 @@ -%Error: t/t_class_param_noinit_bad.v:13:7: Class parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'B' +%Error: t/t_class_param_noinit_bad.v:17:5: Class parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'B' : ... note: In instance 't' - 13 | Cls #(1) c; - | ^~~ + 17 | Cls #(1) c; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_param_noinit_bad.v:13:7: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' +%Error: t/t_class_param_noinit_bad.v:17:5: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' : ... note: In instance 't' - 13 | Cls #(1) c; - | ^~~ -%Error: t/t_class_param_noinit_bad.v:8:32: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' - : ... note: In instance 't' - 8 | class Cls #(int A, int B, type T); - | ^ + 17 | Cls #(1) c; + | ^~~ +%Error: t/t_class_param_noinit_bad.v:11:10: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' + : ... note: In instance 't' + 11 | type T + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_noinit_bad.v b/test_regress/t/t_class_param_noinit_bad.v index 1cf3b86c9..0ca86d1c1 100644 --- a/test_regress/t/t_class_param_noinit_bad.v +++ b/test_regress/t/t_class_param_noinit_bad.v @@ -5,14 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter -class Cls #(int A, int B, type T); +class Cls #( + int A, + int B, + type T +); endclass module t; - initial begin - Cls #(1) c; // Bad: missing B - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls #(1) c; // Bad: missing B + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_override_local_bad.out b/test_regress/t/t_class_param_override_local_bad.out index 37c671895..093ffe116 100644 --- a/test_regress/t/t_class_param_override_local_bad.out +++ b/test_regress/t/t_class_param_override_local_bad.out @@ -5,10 +5,10 @@ %Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:23:41: Parameter not found: '__paramNumber1' 23 | class Cls3 implements Icls1#(2), Icls2#(0); | ^ -%Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:29:23: Parameter not found: '__paramNumber1' - 29 | automatic Cls1#(bit) cls1 = new; - | ^~~ -%Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:30:23: Parameter not found: '__paramNumber1' - 30 | automatic Cls2#(1) cls2 = new; - | ^ +%Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:29:21: Parameter not found: '__paramNumber1' + 29 | automatic Cls1#(bit) cls1 = new; + | ^~~ +%Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:30:21: Parameter not found: '__paramNumber1' + 30 | automatic Cls2#(1) cls2 = new; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_override_local_bad.v b/test_regress/t/t_class_param_override_local_bad.v index 4ea6d1e62..b3b8887c6 100644 --- a/test_regress/t/t_class_param_override_local_bad.v +++ b/test_regress/t/t_class_param_override_local_bad.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - parameter type T = int; + parameter type T = int; endclass class Cls2; - localparam int P = 0; + localparam int P = 0; endclass interface class Icls1; - localparam LP1 = 1; + localparam LP1 = 1; endclass interface class Icls2; - parameter LP1 = 1; + parameter LP1 = 1; endclass class Cls3 implements Icls1#(2), Icls2#(0); @@ -25,10 +25,10 @@ endclass module t; - initial begin - automatic Cls1#(bit) cls1 = new; - automatic Cls2#(1) cls2 = new; - automatic Cls3 cls3 = new; - $stop; - end + initial begin + automatic Cls1#(bit) cls1 = new; + automatic Cls2#(1) cls2 = new; + automatic Cls3 cls3 = new; + $stop; + end endmodule diff --git a/test_regress/t/t_class_param_pkg.v b/test_regress/t/t_class_param_pkg.v index e0615df98..61d3e645e 100644 --- a/test_regress/t/t_class_param_pkg.v +++ b/test_regress/t/t_class_param_pkg.v @@ -4,99 +4,107 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on // See also t_class_param_mod.v package Pkg; - typedef class Cls; + typedef class Cls; - class Wrap #(parameter P = 13); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Cls#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last - endclass + class Wrap #( + parameter P = 13 + ); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Cls #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last + endclass - class Wrap2 #(parameter P = 35); - function int get_p; - return c1.get_p(); - endfunction - function new; - c1 = new; - endfunction - Wrap#(PMINUS1 + 1) c1; - localparam PMINUS1 = P - 1; // Checking works when last - endclass + class Wrap2 #( + parameter P = 35 + ); + function int get_p; + return c1.get_p(); + endfunction + function new; + c1 = new; + endfunction + Wrap #(PMINUS1 + 1) c1; + localparam PMINUS1 = P - 1; // Checking works when last + endclass - class Cls #(parameter PBASE = 12); - bit [PBASE-1:0] member; - function bit [PBASE-1:0] get_member; - return member; - endfunction - static function int get_p; - return PBASE; - endfunction - typedef enum { E_PBASE = PBASE } enum_t; - endclass + class Cls #( + parameter PBASE = 12 + ); + bit [PBASE-1:0] member; + function bit [PBASE-1:0] get_member; + return member; + endfunction + static function int get_p; + return PBASE; + endfunction + typedef enum {E_PBASE = PBASE} enum_t; + endclass - typedef Pkg::Cls#(8) Cls8_t; + typedef Pkg::Cls#(8) Cls8_t; endpackage module t; - Pkg::Cls c12; - Pkg::Cls #(.PBASE(4)) c4; - Pkg::Cls8_t c8; - Pkg::Wrap #(.P(16)) w16; - Pkg::Wrap2 #(.P(32)) w32; - initial begin - c12 = new; - c4 = new; - c8 = new; - w16 = new; - w32 = new; - if (Pkg::Cls#()::PBASE != 12) $stop; - if (Pkg::Cls#(4)::PBASE != 4) $stop; - if (Pkg::Cls8_t::PBASE != 8) $stop; + Pkg::Cls c12; + Pkg::Cls #(.PBASE(4)) c4; + Pkg::Cls8_t c8; + Pkg::Wrap #(.P(16)) w16; + Pkg::Wrap2 #(.P(32)) w32; + initial begin + c12 = new; + c4 = new; + c8 = new; + w16 = new; + w32 = new; + if (Pkg::Cls#()::PBASE != 12) $stop; + if (Pkg::Cls#(4)::PBASE != 4) $stop; + if (Pkg::Cls8_t::PBASE != 8) $stop; - if (Pkg::Cls#()::E_PBASE != 12) $stop; - if (Pkg::Cls#(4)::E_PBASE != 4) $stop; - if (Pkg::Cls8_t::E_PBASE != 8) $stop; + if (Pkg::Cls#()::E_PBASE != 12) $stop; + if (Pkg::Cls#(4)::E_PBASE != 4) $stop; + if (Pkg::Cls8_t::E_PBASE != 8) $stop; - if (c12.PBASE != 12) $stop; - if (c4.PBASE != 4) $stop; - if (c8.PBASE != 8) $stop; + if (c12.PBASE != 12) $stop; + if (c4.PBASE != 4) $stop; + if (c8.PBASE != 8) $stop; - if (Pkg::Cls#()::get_p() != 12) $stop; - if (Pkg::Cls#(4)::get_p() != 4) $stop; - if (Pkg::Cls8_t::get_p() != 8) $stop; + if (Pkg::Cls#()::get_p() != 12) $stop; + if (Pkg::Cls#(4)::get_p() != 4) $stop; + if (Pkg::Cls8_t::get_p() != 8) $stop; - if (c12.get_p() != 12) $stop; - if (c4.get_p() != 4) $stop; - if (c8.get_p() != 8) $stop; - if (w16.get_p() != 16) $stop; - if (w32.get_p() != 32) $stop; + if (c12.get_p() != 12) $stop; + if (c4.get_p() != 4) $stop; + if (c8.get_p() != 8) $stop; + if (w16.get_p() != 16) $stop; + if (w32.get_p() != 32) $stop; - // verilator lint_off WIDTH - c12.member = 32'haaaaaaaa; - c4.member = 32'haaaaaaaa; - c8.member = 32'haaaaaaaa; - // verilator lint_on WIDTH - if (c12.member != 12'haaa) $stop; - if (c4.member != 4'ha) $stop; - if (c12.get_member() != 12'haaa) $stop; - if (c4.get_member() != 4'ha) $stop; - `checkp(c12, "'{member:'haaa}"); - `checkp(c4, "'{member:'ha}"); + // verilator lint_off WIDTH + c12.member = 32'haaaaaaaa; + c4.member = 32'haaaaaaaa; + c8.member = 32'haaaaaaaa; + // verilator lint_on WIDTH + if (c12.member != 12'haaa) $stop; + if (c4.member != 4'ha) $stop; + if (c12.get_member() != 12'haaa) $stop; + if (c4.get_member() != 4'ha) $stop; + `checkp(c12, "'{member:'haaa}"); + `checkp(c4, "'{member:'ha}"); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_subtype.v b/test_regress/t/t_class_param_subtype.v index b3158eab7..a586a5033 100644 --- a/test_regress/t/t_class_param_subtype.v +++ b/test_regress/t/t_class_param_subtype.v @@ -6,44 +6,48 @@ // Test for bug4281 -class CParam #(parameter PARAM=10); - typedef int type_t; +class CParam #( + parameter PARAM = 10 +); + typedef int type_t; endclass -class CParam2 #(parameter PARAM=10); - typedef int type_t; +class CParam2 #( + parameter PARAM = 10 +); + typedef int type_t; - typedef logic [PARAM-1:0] type2_t; + typedef logic [PARAM-1:0] type2_t; endclass `ifdef CONSTSIM -module sub(); - parameter N = 32; - for (genvar i = 0; i < N/8; i = i + 1) begin - initial begin - end +module sub (); + parameter N = 32; + for (genvar i = 0; i < N / 8; i = i + 1) begin + initial begin end - // Test for bug4281, usage conflict of user2 with constant simulator in V3Param.cpp + end + // Test for bug4281, usage conflict of user2 with constant simulator in V3Param.cpp endmodule `endif module t; `ifdef BAD_PAREN - CParam::type_t val_0 = 100; + CParam::type_t val_0 = 100; `else - CParam#()::type_t val_0 = 100; + CParam #()::type_t val_0 = 100; `endif - CParam2#()::type_t val_2 = 200; + CParam2 #()::type_t val_2 = 200; `ifdef CONSTSIM - sub i_sub(); + sub i_sub (); `endif - initial begin - if (val_0 != 100) $stop; - if (val_2 != 200) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (val_0 != 100) $stop; + if (val_2 != 200) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_subtype2.v b/test_regress/t/t_class_param_subtype2.v index 3d7b22591..39a0476d1 100644 --- a/test_regress/t/t_class_param_subtype2.v +++ b/test_regress/t/t_class_param_subtype2.v @@ -4,23 +4,25 @@ // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -class Class1 #(type T); - static function int get(); - return T::Helper::getter(); - endfunction +class Class1 #( + type T +); + static function int get(); + return T::Helper::getter(); + endfunction endclass class Class2; - typedef Class2 Helper; - static function int getter(); - return 13; - endfunction + typedef Class2 Helper; + static function int getter(); + return 13; + endfunction endclass module t; - initial begin - if (Class1#(Class2)::get() != 13) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (Class1#(Class2)::get() != 13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_subtype_bad_paren.out b/test_regress/t/t_class_param_subtype_bad_paren.out index 80797cc6a..e471ad9da 100644 --- a/test_regress/t/t_class_param_subtype_bad_paren.out +++ b/test_regress/t/t_class_param_subtype_bad_paren.out @@ -1,6 +1,6 @@ -%Error: t/t_class_param_subtype.v:32:5: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) +%Error: t/t_class_param_subtype.v:36:3: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) : ... Suggest use 'CParam#()' - 32 | CParam::type_t val_0 = 100; - | ^~~~~~ + 36 | CParam::type_t val_0 = 100; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_param_type.v b/test_regress/t/t_class_param_type.v index 038abcc6f..0586aeb10 100644 --- a/test_regress/t/t_class_param_type.v +++ b/test_regress/t/t_class_param_type.v @@ -6,160 +6,179 @@ // See also t_class_param.v -class Parcls #(type T); - static function int get_p; - return T::get_p(); - endfunction +class Parcls #( + type T +); + static function int get_p; + return T::get_p(); + endfunction endclass class Cls; - static function int get_p; - return 20; - endfunction + static function int get_p; + return 20; + endfunction endclass -class ParclsDefaultType #(type T=Cls); - static function int get_p; - return T::get_p(); - endfunction +class ParclsDefaultType #( + type T = Cls +); + static function int get_p; + return T::get_p(); + endfunction endclass typedef Cls cls_t; typedef cls_t cls2_t; -class Singleton #(type T=int); - static function Singleton#(T) self; - static Singleton#(T) c = new; - return c; - endfunction - function int get_size; - return $bits(T); - endfunction +class Singleton #( + type T = int +); + static function Singleton#(T) self; + static Singleton #(T) c = new; + return c; + endfunction + function int get_size; + return $bits(T); + endfunction endclass -class SingletonUnusedDefault #(type T=int); - static function SingletonUnusedDefault#(T) self; - static SingletonUnusedDefault#(T) c = new; - return c; - endfunction +class SingletonUnusedDefault #( + type T = int +); + static function SingletonUnusedDefault#(T) self; + static SingletonUnusedDefault #(T) c = new; + return c; + endfunction endclass class Empty; endclass -class Foo #(type IF=Empty) extends IF; - typedef Foo foo_t; - int a = 1; +class Foo #( + type IF = Empty +) extends IF; + typedef Foo foo_t; + int a = 1; endclass -class Bar #(type A=int, type B=A) extends Foo#(); - function int get_size_A; - return $bits(A); - endfunction - function int get_size_B; - return $bits(B); - endfunction +class Bar #( + type A = int, + type B = A +) extends Foo #(); + function int get_size_A; + return $bits(A); + endfunction + function int get_size_B; + return $bits(B); + endfunction endclass class Empty2; endclass -class Baz #(type T=Empty2) extends Foo#(); +class Baz #( + type T = Empty2 +) extends Foo #(); endclass -class Getter1 extends Baz#(); - function int get_1; - foo_t f = new; - return f.a; - endfunction +class Getter1 extends Baz #(); + function int get_1; + foo_t f = new; + return f.a; + endfunction endclass class MyInt1; - int x = 1; + int x = 1; endclass class MyInt2; - int x = 2; + int x = 2; endclass -class ExtendsMyInt #(type T=MyInt1) extends T; - typedef ExtendsMyInt#(T) this_type; - function int get_this_type_x; - this_type t = new; - return t.x; - endfunction +class ExtendsMyInt #( + type T = MyInt1 +) extends T; + typedef ExtendsMyInt#(T) this_type; + function int get_this_type_x; + this_type t = new; + return t.x; + endfunction endclass class StaticX; - static int val = 1; + static int val = 1; endclass -class GetStaticXVal #(type T = int); - static function int get; - return T::val; - endfunction +class GetStaticXVal #( + type T = int +); + static function int get; + return T::val; + endfunction endclass module t; - initial begin - automatic ParclsDefaultType#(Cls) pdt1 = new; - automatic ParclsDefaultType#(cls_t) pdt2 = pdt1; - automatic ParclsDefaultType#(cls2_t) pdt3 = pdt2; - automatic Parcls#(Cls) p1 = new; - automatic Parcls#(cls_t) p2 = p1; - automatic Parcls#(cls2_t) p3 = p2; + initial begin + automatic ParclsDefaultType #(Cls) pdt1 = new; + automatic ParclsDefaultType #(cls_t) pdt2 = pdt1; + automatic ParclsDefaultType #(cls2_t) pdt3 = pdt2; + automatic Parcls #(Cls) p1 = new; + automatic Parcls #(cls_t) p2 = p1; + automatic Parcls #(cls2_t) p3 = p2; - automatic Singleton #(int) s_int1 = Singleton#(int)::self(); - automatic Singleton #(int) s_int2 = Singleton#(int)::self(); - automatic Singleton #(bit) s_bit1 = Singleton#(bit)::self(); - automatic Singleton #(bit) s_bit2 = Singleton#(bit)::self(); - automatic SingletonUnusedDefault #(bit) sud1 = SingletonUnusedDefault#(bit)::self(); - automatic SingletonUnusedDefault #(bit) sud2 = SingletonUnusedDefault#(bit)::self(); + automatic Singleton #(int) s_int1 = Singleton#(int)::self(); + automatic Singleton #(int) s_int2 = Singleton#(int)::self(); + automatic Singleton #(bit) s_bit1 = Singleton#(bit)::self(); + automatic Singleton #(bit) s_bit2 = Singleton#(bit)::self(); + automatic SingletonUnusedDefault #(bit) sud1 = SingletonUnusedDefault#(bit)::self(); + automatic SingletonUnusedDefault #(bit) sud2 = SingletonUnusedDefault#(bit)::self(); - automatic Getter1 getter1 = new; + automatic Getter1 getter1 = new; - automatic ExtendsMyInt#() ext1 = new; - automatic ExtendsMyInt#(MyInt2) ext2 = new; + automatic ExtendsMyInt #() ext1 = new; + automatic ExtendsMyInt #(MyInt2) ext2 = new; - automatic GetStaticXVal#(StaticX) get_statix_x_val = new; + automatic GetStaticXVal #(StaticX) get_statix_x_val = new; - typedef bit my_bit_t; - automatic Bar#(.A(my_bit_t)) bar_a_bit = new; - automatic Bar#(.B(my_bit_t)) bar_b_bit = new; - automatic Bar#() bar_default = new; + typedef bit my_bit_t; + automatic Bar #(.A(my_bit_t)) bar_a_bit = new; + automatic Bar #(.B(my_bit_t)) bar_b_bit = new; + automatic Bar #() bar_default = new; - if (bar_a_bit.get_size_A != 1) $stop; - if (bar_a_bit.get_size_B != 1) $stop; - if (bar_b_bit.get_size_A != 32) $stop; - if (bar_b_bit.get_size_B != 1) $stop; - if (bar_default.get_size_A != 32) $stop; - if (bar_default.get_size_B != 32) $stop; + if (bar_a_bit.get_size_A != 1) $stop; + if (bar_a_bit.get_size_B != 1) $stop; + if (bar_b_bit.get_size_A != 32) $stop; + if (bar_b_bit.get_size_B != 1) $stop; + if (bar_default.get_size_A != 32) $stop; + if (bar_default.get_size_B != 32) $stop; - if (pdt1 != pdt2) $stop; - if (pdt2 != pdt3) $stop; - if (p1 != p2) $stop; - if (p2 != p3) $stop; + if (pdt1 != pdt2) $stop; + if (pdt2 != pdt3) $stop; + if (p1 != p2) $stop; + if (p2 != p3) $stop; - if (s_int1 != s_int2) $stop; - if (s_bit1 != s_bit2) $stop; - if (sud1 != sud2) $stop; + if (s_int1 != s_int2) $stop; + if (s_bit1 != s_bit2) $stop; + if (sud1 != sud2) $stop; - if (s_int1.get_size() != 32) $stop; - if (s_bit1.get_size() != 1) $stop; + if (s_int1.get_size() != 32) $stop; + if (s_bit1.get_size() != 1) $stop; - if (p1.get_p() != 20) $stop; - if (pdt1.get_p() != 20) $stop; - if (Parcls#(cls2_t)::get_p() != 20) $stop; + if (p1.get_p() != 20) $stop; + if (pdt1.get_p() != 20) $stop; + if (Parcls#(cls2_t)::get_p() != 20) $stop; - if (getter1.get_1() != 1) $stop; + if (getter1.get_1() != 1) $stop; - if (ext1.get_this_type_x() != 1) $stop; - if (ext2.get_this_type_x() != 2) $stop; + if (ext1.get_this_type_x() != 1) $stop; + if (ext2.get_this_type_x() != 2) $stop; - if (get_statix_x_val.get() != 1) $stop; + if (get_statix_x_val.get() != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_typedef.v b/test_regress/t/t_class_param_typedef.v index 3d1862b69..35186b362 100644 --- a/test_regress/t/t_class_param_typedef.v +++ b/test_regress/t/t_class_param_typedef.v @@ -4,69 +4,78 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Foo #(type T=int); - typedef Foo#(T) this_type; - function int get_x; - return T::get_s_x(); - endfunction +class Foo #( + type T = int +); + typedef Foo#(T) this_type; + function int get_x; + return T::get_s_x(); + endfunction endclass -class Bar #(type S=int); - typedef Bar #(S) this_type; - typedef Foo#(this_type) foo_type; - function int get_x; - foo_type f = new; - return f.get_x(); - endfunction - static function int get_s_x; - return S::x; - endfunction +class Bar #( + type S = int +); + typedef Bar#(S) this_type; + typedef Foo#(this_type) foo_type; + function int get_x; + foo_type f = new; + return f.get_x(); + endfunction + static function int get_s_x; + return S::x; + endfunction endclass class Cls1; - static int x = 1; - typedef Bar#(Cls1) type_id; + static int x = 1; + typedef Bar#(Cls1) type_id; endclass class Cls2; - static int x = 2; - typedef Bar#(Cls2) type_id; + static int x = 2; + typedef Bar#(Cls2) type_id; endclass typedef int my_int; -class ClsTypedefParam #(type T=my_int); - int x; +class ClsTypedefParam #( + type T = my_int +); + int x; endclass -class uvm_sequencer #(type REQ=int, RSP=REQ); - int x; - typedef uvm_sequencer #(REQ, RSP) this_type; +class uvm_sequencer #( + type REQ = int, + RSP = REQ +); + int x; + typedef uvm_sequencer#(REQ, RSP) this_type; endclass module t; - initial begin - automatic Cls1::type_id bar1 = new; - automatic Cls2::type_id bar2 = new; + initial begin + automatic Cls1::type_id bar1 = new; + automatic Cls2::type_id bar2 = new; - automatic ClsTypedefParam #(int) cls_int = new; - automatic ClsTypedefParam#() cls_def; + automatic ClsTypedefParam #(int) cls_int = new; + automatic ClsTypedefParam #() cls_def; - automatic uvm_sequencer #(int, int) uvm_seq1 = new; - automatic uvm_sequencer #(int, int)::this_type uvm_seq2; + automatic uvm_sequencer #(int, int) uvm_seq1 = new; + automatic uvm_sequencer #(int, int)::this_type uvm_seq2; - if (bar1.get_x() != 1) $stop; - if (bar2.get_x() != 2) $stop; + if (bar1.get_x() != 1) $stop; + if (bar2.get_x() != 2) $stop; - cls_int.x = 1; - cls_def = cls_int; - if (cls_def.x != 1) $stop; + cls_int.x = 1; + cls_def = cls_int; + if (cls_def.x != 1) $stop; - uvm_seq1.x = 2; - uvm_seq2 = uvm_seq1; - if (uvm_seq2.x != 2) $stop; + uvm_seq1.x = 2; + uvm_seq2 = uvm_seq1; + if (uvm_seq2.x != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_unused_default.v b/test_regress/t/t_class_param_unused_default.v index e1563c077..ff5e5d1f7 100644 --- a/test_regress/t/t_class_param_unused_default.v +++ b/test_regress/t/t_class_param_unused_default.v @@ -4,23 +4,25 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -class Bar#(type T = int); - T t; - function new; - t = new; - endfunction +class Bar #( + type T = int +); + T t; + function new; + t = new; + endfunction endclass class Baz; - int x = 1; + int x = 1; endclass module t; - initial begin - automatic Bar#(Baz) bar_baz = new; - if (bar_baz.t.x != 1) $stop; + initial begin + automatic Bar #(Baz) bar_baz = new; + if (bar_baz.t.x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_virtual_bad.out b/test_regress/t/t_class_param_virtual_bad.out index c53f4d7b3..011f3ddbb 100644 --- a/test_regress/t/t_class_param_virtual_bad.out +++ b/test_regress/t/t_class_param_virtual_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_class_param_virtual_bad.v:23:38: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21) +%Error: t/t_class_param_virtual_bad.v:27:37: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21) : ... note: In instance 't' - 23 | automatic ClsVirt#(VBase) cv = new; - | ^~~ + 27 | automatic ClsVirt #(VBase) cv = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_param_virtual_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) - : ... note: In instance 't' - 13 | t = new; - | ^~~ +%Error: t/t_class_param_virtual_bad.v:15:9: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) + : ... note: In instance 't' + 15 | t = new; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_param_virtual_bad.v b/test_regress/t/t_class_param_virtual_bad.v index d53651d88..e5ee0a326 100644 --- a/test_regress/t/t_class_param_virtual_bad.v +++ b/test_regress/t/t_class_param_virtual_bad.v @@ -7,20 +7,24 @@ virtual class VBase; endclass -class Cls#(parameter type T = VBase); - T t; - function new; - t = new; - endfunction +class Cls #( + parameter type T = VBase +); + T t; + function new; + t = new; + endfunction endclass -virtual class ClsVirt#(parameter type T); +virtual class ClsVirt #( + parameter type T +); endclass module t; - initial begin - automatic Cls c = new; // Error - automatic ClsVirt#(VBase) cv = new; // Error - $stop; - end + initial begin + automatic Cls c = new; // Error + automatic ClsVirt #(VBase) cv = new; // Error + $stop; + end endmodule diff --git a/test_regress/t/t_class_ref_bad.out b/test_regress/t/t_class_ref_bad.out index 76e076d4f..40fe20c54 100644 --- a/test_regress/t/t_class_ref_bad.out +++ b/test_regress/t/t_class_ref_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_ref_bad.v:15:11: Package/class for ':: reference' not found: 'ClsRigh' - : ... Suggested alternative: 'ClsRight' - 15 | s = ClsRigh::m_s; - | ^~~~~~~ +%Error: t/t_class_ref_bad.v:15:9: Package/class for ':: reference' not found: 'ClsRigh' + : ... Suggested alternative: 'ClsRight' + 15 | s = ClsRigh::m_s; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_ref_bad.v b/test_regress/t/t_class_ref_bad.v index d1242cb1c..152c800d4 100644 --- a/test_regress/t/t_class_ref_bad.v +++ b/test_regress/t/t_class_ref_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 class ClsRight; - string m_s; + string m_s; endclass module t; - string s; - initial begin - // verilator lint_off PKGNODECL - s = ClsRigh::m_s; // Bad typo, issue #5475 - end + string s; + initial begin + // verilator lint_off PKGNODECL + s = ClsRigh::m_s; // Bad typo, issue #5475 + end endmodule diff --git a/test_regress/t/t_class_ref_ref.v b/test_regress/t/t_class_ref_ref.v index 948ba2b22..574813650 100644 --- a/test_regress/t/t_class_ref_ref.v +++ b/test_regress/t/t_class_ref_ref.v @@ -4,18 +4,20 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class Cls#(type T = bit); +class Cls #( + type T = bit +); endclass module t; - Cls#(bit) cb; + Cls #(bit) cb; - Cls#(Cls#(bit)) ccb; + Cls #(Cls #(bit)) ccb; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_reference_name_colision.v b/test_regress/t/t_class_reference_name_colision.v index 96d64f245..7aca2b70b 100644 --- a/test_regress/t/t_class_reference_name_colision.v +++ b/test_regress/t/t_class_reference_name_colision.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 class setup_coefficients; - static function int create(); - return 1; - endfunction + static function int create(); + return 1; + endfunction endclass class biquad_vseq; - int c_setup = setup_coefficients::create(); - function void setup_coefficients(); - endfunction -endclass: biquad_vseq + int c_setup = setup_coefficients::create(); + function void setup_coefficients(); + endfunction +endclass : biquad_vseq diff --git a/test_regress/t/t_class_short_circuit.v b/test_regress/t/t_class_short_circuit.v index 02318d569..bfbb199e9 100644 --- a/test_regress/t/t_class_short_circuit.v +++ b/test_regress/t/t_class_short_circuit.v @@ -5,29 +5,29 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int x; - function new; - x = 10; - endfunction - function bit set_x(int a); - x = a; - return 1; - endfunction - function int get_x; - return x; - endfunction + int x; + function new; + x = 10; + endfunction + function bit set_x(int a); + x = a; + return 1; + endfunction + function int get_x; + return x; + endfunction endclass module t; - initial begin - Cls cls; - if (cls != null && cls.x == 10) $stop; - if (cls != null && cls.get_x() == 10) $stop; - cls = new; - if (!cls.set_x(1) || cls.x != 1) $stop; - if (!cls.set_x(2) || cls.get_x() != 2) $stop; + initial begin + Cls cls; + if (cls != null && cls.x == 10) $stop; + if (cls != null && cls.get_x() == 10) $stop; + cls = new; + if (!cls.set_x(1) || cls.x != 1) $stop; + if (!cls.set_x(2) || cls.get_x() != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_split.v b/test_regress/t/t_class_split.v index decfb1ebf..649046b42 100644 --- a/test_regress/t/t_class_split.v +++ b/test_regress/t/t_class_split.v @@ -5,30 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - int ctr; - task run(); - $display("%d", ctr); - ctr = ctr + 1; - endtask: run -endclass; + int ctr; + task run(); + $display("%d", ctr); + ctr = ctr + 1; + endtask : run +endclass class Cls2 extends Cls1; - task runtask(); - run(); - run(); - run(); - run(); - run(); - run(); - endtask: runtask + task runtask(); + run(); + run(); + run(); + run(); + run(); + run(); + endtask : runtask endclass module top; - Cls2 o; - initial begin - o = new; - o.runtask(); - $write("*-* All Finished *-*\n"); - $finish; - end + Cls2 o; + initial begin + o = new; + o.runtask(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static.v b/test_regress/t/t_class_static.v index 002034221..4c73e5e42 100644 --- a/test_regress/t/t_class_static.v +++ b/test_regress/t/t_class_static.v @@ -4,64 +4,65 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; - int c_no = 2; - //automatic int c_au = 2; // automatic not a legal keyword here - static int c_st = 2; + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 2; - function int f_c_no (); - ++c_no; return c_no; - endfunction - function int f_c_st (); - ++c_st; return c_st; - endfunction + function int f_c_no (); + ++c_no; return c_no; + endfunction + function int f_c_st (); + ++c_st; return c_st; + endfunction - function int f_no_no (); - int au = 2; au++; return au; - endfunction - function int f_no_st (); - static int st = 2; st++; return st; - endfunction - function int f_no_au (); - automatic int au = 2; au++; return au; - endfunction + function int f_no_no (); + int au = 2; au++; return au; + endfunction + function int f_no_st (); + static int st = 2; st++; return st; + endfunction + function int f_no_au (); + automatic int au = 2; au++; return au; + endfunction endclass module t; - Cls a = new; - Cls b = new; + Cls a = new; + Cls b = new; - int v; + int v; - initial begin - v = a.f_c_no(); `checkh(v,3); - v = a.f_c_no(); `checkh(v, 4); - v = b.f_c_no(); `checkh(v, 3); - v = b.f_c_no(); `checkh(v, 4); - v = a.f_c_st(); `checkh(v,3); - v = a.f_c_st(); `checkh(v, 4); - v = b.f_c_st(); `checkh(v, 5); - v = b.f_c_st(); `checkh(v, 6); - // - v = a.f_no_no(); `checkh(v, 3); - v = a.f_no_no(); `checkh(v, 3); - v = b.f_no_no(); `checkh(v, 3); - v = b.f_no_no(); `checkh(v, 3); - v = a.f_no_st(); `checkh(v, 3); - v = a.f_no_st(); `checkh(v, 4); - v = b.f_no_st(); `checkh(v, 5); - v = b.f_no_st(); `checkh(v, 6); - v = a.f_no_au(); `checkh(v, 3); - v = a.f_no_au(); `checkh(v, 3); - v = b.f_no_au(); `checkh(v, 3); - v = b.f_no_au(); `checkh(v, 3); + initial begin + v = a.f_c_no(); `checkh(v,3); + v = a.f_c_no(); `checkh(v, 4); + v = b.f_c_no(); `checkh(v, 3); + v = b.f_c_no(); `checkh(v, 4); + v = a.f_c_st(); `checkh(v,3); + v = a.f_c_st(); `checkh(v, 4); + v = b.f_c_st(); `checkh(v, 5); + v = b.f_c_st(); `checkh(v, 6); + // + v = a.f_no_no(); `checkh(v, 3); + v = a.f_no_no(); `checkh(v, 3); + v = b.f_no_no(); `checkh(v, 3); + v = b.f_no_no(); `checkh(v, 3); + v = a.f_no_st(); `checkh(v, 3); + v = a.f_no_st(); `checkh(v, 4); + v = b.f_no_st(); `checkh(v, 5); + v = b.f_no_st(); `checkh(v, 6); + v = a.f_no_au(); `checkh(v, 3); + v = a.f_no_au(); `checkh(v, 3); + v = b.f_no_au(); `checkh(v, 3); + v = b.f_no_au(); `checkh(v, 3); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_default_arg.v b/test_regress/t/t_class_static_default_arg.v index bd6a4d7d2..ced4057b6 100644 --- a/test_regress/t/t_class_static_default_arg.v +++ b/test_regress/t/t_class_static_default_arg.v @@ -5,23 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - static function bit get_first(bit q[$] = {1'b1}); - return q[0]; - endfunction + static function bit get_first(bit q[$] = {1'b1}); + return q[0]; + endfunction endclass module t; - initial begin - bit first; - automatic bit arg[$] = {1'b0, 1'b1}; - first = Foo::get_first(); - if (first != 1) $stop; - first = Foo::get_first(arg); - if (first != 0) $stop; + initial begin + bit first; + automatic bit arg[$] = {1'b0, 1'b1}; + first = Foo::get_first(); + if (first != 1) $stop; + first = Foo::get_first(arg); + if (first != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_member.v b/test_regress/t/t_class_static_member.v index 9f1cb99ad..d11111b87 100644 --- a/test_regress/t/t_class_static_member.v +++ b/test_regress/t/t_class_static_member.v @@ -4,54 +4,70 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; - class InnerCls; - static function int f_inner_cs_st(); - ++c_st; return c_st; - endfunction - endclass + class InnerCls; + static function int f_inner_cs_st(); + ++c_st; + return c_st; + endfunction + endclass - int c_no = 2; - //automatic int c_au = 2; // automatic not a legal keyword here - static int c_st = 22; + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 22; - function int f_c_no (); - ++c_no; return c_no; - endfunction - function int f_c_st (); - ++c_st; return c_st; - endfunction + function int f_c_no(); + ++c_no; + return c_no; + endfunction + function int f_c_st(); + ++c_st; + return c_st; + endfunction - static function int f_cs_st (); - ++c_st; return c_st; - endfunction + static function int f_cs_st(); + ++c_st; + return c_st; + endfunction endclass module t; - Cls a = new; - Cls b = new; + Cls a = new; + Cls b = new; - int v; + int v; - initial begin - v = a.f_c_no(); `checkh(v, 3); - v = a.f_c_no(); `checkh(v, 4); - v = b.f_c_no(); `checkh(v, 3); - v = b.f_c_no(); `checkh(v, 4); - v = a.f_c_st(); `checkh(v, 23); - v = a.f_c_st(); `checkh(v, 24); - v = b.f_c_st(); `checkh(v, 25); - v = b.f_c_st(); `checkh(v, 26); - // - v = Cls::f_cs_st(); `checkh(v, 27); - v = Cls::InnerCls::f_inner_cs_st(); `checkh(v, 28); + initial begin + v = a.f_c_no(); + `checkh(v, 3); + v = a.f_c_no(); + `checkh(v, 4); + v = b.f_c_no(); + `checkh(v, 3); + v = b.f_c_no(); + `checkh(v, 4); + v = a.f_c_st(); + `checkh(v, 23); + v = a.f_c_st(); + `checkh(v, 24); + v = b.f_c_st(); + `checkh(v, 25); + v = b.f_c_st(); + `checkh(v, 26); + // + v = Cls::f_cs_st(); + `checkh(v, 27); + v = Cls::InnerCls::f_inner_cs_st(); + `checkh(v, 28); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_member_pkg.v b/test_regress/t/t_class_static_member_pkg.v index b51eb6333..d80bfad5b 100644 --- a/test_regress/t/t_class_static_member_pkg.v +++ b/test_regress/t/t_class_static_member_pkg.v @@ -4,50 +4,64 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package Pkg; -class Cls; - int c_no = 2; - //automatic int c_au = 2; // automatic not a legal keyword here - static int c_st = 22; + class Cls; + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 22; - function int f_c_no (); - ++c_no; return c_no; - endfunction - function int f_c_st (); - ++c_st; return c_st; - endfunction + function int f_c_no(); + ++c_no; + return c_no; + endfunction + function int f_c_st(); + ++c_st; + return c_st; + endfunction - static function int f_cs_st (); - ++c_st; return c_st; - endfunction + static function int f_cs_st(); + ++c_st; + return c_st; + endfunction -endclass + endclass endpackage module t; - Pkg::Cls a = new; - Pkg::Cls b = new; + Pkg::Cls a = new; + Pkg::Cls b = new; - int v; + int v; - initial begin - v = a.f_c_no(); `checkh(v, 3); - v = a.f_c_no(); `checkh(v, 4); - v = b.f_c_no(); `checkh(v, 3); - v = b.f_c_no(); `checkh(v, 4); - v = a.f_c_st(); `checkh(v, 23); - v = a.f_c_st(); `checkh(v, 24); - v = b.f_c_st(); `checkh(v, 25); - v = b.f_c_st(); `checkh(v, 26); - // - v = Pkg::Cls::f_cs_st(); `checkh(v, 27); + initial begin + v = a.f_c_no(); + `checkh(v, 3); + v = a.f_c_no(); + `checkh(v, 4); + v = b.f_c_no(); + `checkh(v, 3); + v = b.f_c_no(); + `checkh(v, 4); + v = a.f_c_st(); + `checkh(v, 23); + v = a.f_c_st(); + `checkh(v, 24); + v = b.f_c_st(); + `checkh(v, 25); + v = b.f_c_st(); + `checkh(v, 26); + // + v = Pkg::Cls::f_cs_st(); + `checkh(v, 27); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_member_sel.v b/test_regress/t/t_class_static_member_sel.v index e83659fb2..42425cfb5 100644 --- a/test_regress/t/t_class_static_member_sel.v +++ b/test_regress/t/t_class_static_member_sel.v @@ -5,86 +5,86 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - static int x = 1; + static int x = 1; endclass class Bar; - Foo f; - function new; - f = new; - endfunction + Foo f; + function new; + f = new; + endfunction endclass class Baz; - static function Bar get_bar; - Bar b = new; - return b; - endfunction + static function Bar get_bar; + Bar b = new; + return b; + endfunction endclass class IntWrapper; - int x; + int x; endclass class Cls; - static IntWrapper iw; - function new; - if (iw == null) iw = new; - endfunction + static IntWrapper iw; + function new; + if (iw == null) iw = new; + endfunction endclass class ExtendCls extends Cls; endclass class Getter1; - static function int get_1; - return 1; - endfunction + static function int get_1; + return 1; + endfunction endclass class uvm_root; - int x; - static uvm_root m_inst; - static function uvm_root get_inst(); - if (m_inst == null) m_inst = new; - return m_inst; - endfunction - function int get_7(); - return 7; - endfunction + int x; + static uvm_root m_inst; + static function uvm_root get_inst(); + if (m_inst == null) m_inst = new; + return m_inst; + endfunction + function int get_7(); + return 7; + endfunction endclass module t; - initial begin - automatic Foo foo = new; - automatic Bar bar = new; - automatic Baz baz = new; - automatic ExtendCls ec = new; - automatic Getter1 getter1 = new; + initial begin + automatic Foo foo = new; + automatic Bar bar = new; + automatic Baz baz = new; + automatic ExtendCls ec = new; + automatic Getter1 getter1 = new; - if (foo.x != 1) $stop; + if (foo.x != 1) $stop; - foo.x = 2; - if (foo.x != 2) $stop; + foo.x = 2; + if (foo.x != 2) $stop; - bar.f.x = 3; - if (bar.f.x != 3) $stop; + bar.f.x = 3; + if (bar.f.x != 3) $stop; - baz.get_bar().f.x = 4; - if (baz.get_bar().f.x != 4) $stop; + baz.get_bar().f.x = 4; + if (baz.get_bar().f.x != 4) $stop; - ec.iw.x = 5; - if (ec.iw.x != 5) $stop; + ec.iw.x = 5; + if (ec.iw.x != 5) $stop; - if (getter1.get_1 != 1) $stop; + if (getter1.get_1 != 1) $stop; - uvm_root::get_inst().x = 6; - if (uvm_root::get_inst().x != 6) $stop; + uvm_root::get_inst().x = 6; + if (uvm_root::get_inst().x != 6) $stop; - if (uvm_root::get_inst().get_7() != 7) $stop; + if (uvm_root::get_inst().get_7() != 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_method.v b/test_regress/t/t_class_static_method.v index a7ba8a4a3..ee100b51c 100644 --- a/test_regress/t/t_class_static_method.v +++ b/test_regress/t/t_class_static_method.v @@ -6,46 +6,46 @@ class Cls; - static task static_task(int x); - $write("Called static task: %d\n", x); - if (x != 16) $stop; - endtask + static task static_task(int x); + $write("Called static task: %d\n", x); + if (x != 16) $stop; + endtask - static function int static_function(int x); - $write("Called static function: %d\n", x); - if (x != 23) $stop; - return 42; - endfunction + static function int static_function(int x); + $write("Called static function: %d\n", x); + if (x != 23) $stop; + return 42; + endfunction endclass : Cls class OCls; - int i; - static function OCls create(); - OCls o = new; - o.i = 42; - return o; - endfunction - static task test_obj(OCls o); - if (o.i != 42) $stop; - endtask + int i; + static function OCls create(); + OCls o = new; + o.i = 42; + return o; + endfunction + static task test_obj(OCls o); + if (o.i != 42) $stop; + endtask endclass module t; - initial begin - int x; - OCls oc; + initial begin + int x; + OCls oc; - Cls::static_task(16); - x = Cls::static_function(23); - $write("Static function result: %d\n", x); - if (x != 42) $stop; + Cls::static_task(16); + x = Cls::static_function(23); + $write("Static function result: %d\n", x); + if (x != 42) $stop; - oc = OCls::create(); - OCls::test_obj(oc); + oc = OCls::create(); + OCls::test_obj(oc); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_static_order.v b/test_regress/t/t_class_static_order.v index bf639f50c..b3611ca1c 100644 --- a/test_regress/t/t_class_static_order.v +++ b/test_regress/t/t_class_static_order.v @@ -5,56 +5,56 @@ // SPDX-License-Identifier: CC0-1.0 class ClsZ; - function new(); - $display("ClsZ::new"); - endfunction + function new(); + $display("ClsZ::new"); + endfunction endclass class ClsA; - function new(); - $display("ClsA::new"); - endfunction - function void access; - $display("ClsA::access"); - endfunction + function new(); + $display("ClsA::new"); + endfunction + function void access; + $display("ClsA::access"); + endfunction endclass class ClsB; - static ClsZ z = new; - function new(); - $display("ClsB::new"); - endfunction - function void access; - $display("ClsB::access"); - endfunction + static ClsZ z = new; + function new(); + $display("ClsB::new"); + endfunction + function void access; + $display("ClsB::access"); + endfunction endclass class ClsC; - // Elaboration will call these - static ClsA a = new; - static ClsB b = new; - function new(); - $display("ClsC::new"); - endfunction - function void access; - $display("ClsC::access"); - a = new; - a.access; - endfunction + // Elaboration will call these + static ClsA a = new; + static ClsB b = new; + function new(); + $display("ClsC::new"); + endfunction + function void access; + $display("ClsC::access"); + a = new; + a.access; + endfunction endclass module t; - function void makec; - ClsC c; - $display("c = new;"); - c = new; - $display("c.access;"); - c.access; - endfunction - initial begin - $display("makec;"); - makec; - $write("*-* All Finished *-*\n"); - $finish; - end + function void makec; + ClsC c; + $display("c = new;"); + c = new; + $display("c.access;"); + c.access; + endfunction + initial begin + $display("makec;"); + makec; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_super_bad.out b/test_regress/t/t_class_super_bad.out index 42d40c058..f698f2290 100644 --- a/test_regress/t/t_class_super_bad.out +++ b/test_regress/t/t_class_super_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_super_bad.v:12:12: 'super' used outside class (IEEE 1800-2023 8.15) - 12 | super.addr = 2; - | ^ +%Error: t/t_class_super_bad.v:12:10: 'super' used outside class (IEEE 1800-2023 8.15) + 12 | super.addr = 2; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_super_bad.v b/test_regress/t/t_class_super_bad.v index e4de0c364..b959fb0c8 100644 --- a/test_regress/t/t_class_super_bad.v +++ b/test_regress/t/t_class_super_bad.v @@ -7,10 +7,10 @@ module t; - bit [3:0] addr; - initial begin - super.addr = 2; - $write("*-* All Finished *-*\n"); - $finish; - end + bit [3:0] addr; + initial begin + super.addr = 2; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_super_bad2.out b/test_regress/t/t_class_super_bad2.out index d5db4aade..95b909de5 100644 --- a/test_regress/t/t_class_super_bad2.out +++ b/test_regress/t/t_class_super_bad2.out @@ -1,5 +1,5 @@ -%Error: t/t_class_super_bad2.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15) - 10 | super.i = 1; - | ^ +%Error: t/t_class_super_bad2.v:10:10: 'super' used on non-extended class (IEEE 1800-2023 8.15) + 10 | super.i = 1; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_super_bad2.v b/test_regress/t/t_class_super_bad2.v index 8a75239b5..c33d8eaa5 100644 --- a/test_regress/t/t_class_super_bad2.v +++ b/test_regress/t/t_class_super_bad2.v @@ -6,7 +6,7 @@ // class Cls; - task t; - super.i = 1; // Bad - no extends - endtask + task t; + super.i = 1; // Bad - no extends + endtask endclass diff --git a/test_regress/t/t_class_super_new.v b/test_regress/t/t_class_super_new.v index e439cb91a..62425e4f4 100644 --- a/test_regress/t/t_class_super_new.v +++ b/test_regress/t/t_class_super_new.v @@ -4,155 +4,163 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Foo; - int x; - function new; - this.x = 10; - endfunction + int x; + function new; + this.x = 10; + endfunction endclass class Bar extends Foo; - function new; - super.new; - endfunction + function new; + super.new; + endfunction endclass class BarUnusedArg extends Foo; - function new (int a); - super.new; - endfunction + function new(int a); + super.new; + endfunction endclass class FooArg; - int x; - function new (int a); - this.x = a; - endfunction + int x; + function new(int a); + this.x = a; + endfunction endclass class BarArg extends FooArg; - function new (int a); - super.new(a); - endfunction + function new(int a); + super.new(a); + endfunction endclass class BarArgWithReturnInIf extends FooArg; - function new (int a); - super.new(a); - if (a < 10) begin - return; - end - this.x = 20; - endfunction + function new(int a); + super.new(a); + if (a < 10) begin + return; + end + this.x = 20; + endfunction endclass class BarExpr extends FooArg; - function new (int a, string b); - super.new(a + b.len()); - endfunction + function new(int a, string b); + super.new(a + b.len()); + endfunction endclass class Foo2Args; - int x; - function new (int a, int b); - this.x = a + b; - endfunction + int x; + function new(int a, int b); + this.x = a + b; + endfunction endclass class Bar2Args extends Foo2Args; - function new (int a, int b); - super.new(a, b); - endfunction + function new(int a, int b); + super.new(a, b); + endfunction endclass class OptArgInNew; - int x; - function new (int y=1); - x = y; - endfunction + int x; + function new(int y = 1); + x = y; + endfunction endclass class NoNew extends OptArgInNew; endclass class NewWithoutSuper extends OptArgInNew; - function new; - endfunction + function new; + endfunction endclass -class OptArgInNewParam #(parameter int P=1); - int x; - function new (int y=1); - x = y; - endfunction +class OptArgInNewParam #( + parameter int P = 1 +); + int x; + function new(int y = 1); + x = y; + endfunction endclass -class NoNewParam#(parameter int R) extends OptArgInNewParam#(R); +class NoNewParam #( + parameter int R +) extends OptArgInNewParam #(R); endclass -class NewWithoutSuperParam#(parameter int R) extends OptArgInNewParam#(); - function new; - endfunction +class NewWithoutSuperParam #( + parameter int R +) extends OptArgInNewParam #(); + function new; + endfunction endclass -module t (/*AUTOARG*/ - ); +module t ( /*AUTOARG*/ +); - class FooInModule; - int x; - function new; - this.x = 15; - endfunction - endclass + class FooInModule; + int x; + function new; + this.x = 15; + endfunction + endclass - class BarInModule extends FooInModule; - function new; - super.new; - endfunction - endclass + class BarInModule extends FooInModule; + function new; + super.new; + endfunction + endclass - Bar bar; - BarInModule barInModule; - BarUnusedArg barUnusedArg; - BarArg barArg; - BarExpr barExpr; - Bar2Args bar2Args; - NoNew noNew; - NewWithoutSuper newWithoutSuper; - NoNewParam#(2) noNewParam; - NewWithoutSuperParam#(1) newWithoutSuperParam; - BarArgWithReturnInIf barIf1, barIf10; + Bar bar; + BarInModule barInModule; + BarUnusedArg barUnusedArg; + BarArg barArg; + BarExpr barExpr; + Bar2Args bar2Args; + NoNew noNew; + NewWithoutSuper newWithoutSuper; + NoNewParam #(2) noNewParam; + NewWithoutSuperParam #(1) newWithoutSuperParam; + BarArgWithReturnInIf barIf1, barIf10; - initial begin - bar = new; - `checkh(bar.x, 10); - barInModule = new; - `checkh(barInModule.x, 15); - barUnusedArg = new(2); - `checkh(barUnusedArg.x, 10); - barArg = new(2); - `checkh(barArg.x, 2); - barExpr = new (7, "ABCDEFGHI"); - `checkh(barExpr.x, 16); - bar2Args = new(2, 12); - `checkh(bar2Args.x, 14); - noNew = new; - `checkh(noNew.x, 1); - newWithoutSuper = new; - `checkh(newWithoutSuper.x, 1); - noNewParam = new; - `checkh(noNewParam.x, 1); - newWithoutSuperParam = new; - `checkh(newWithoutSuperParam.x, 1); - barIf1 = new(1); - `checkh(barIf1.x, 1); - barIf10 = new(10); - `checkh(barIf10.x, 20); + initial begin + bar = new; + `checkh(bar.x, 10); + barInModule = new; + `checkh(barInModule.x, 15); + barUnusedArg = new(2); + `checkh(barUnusedArg.x, 10); + barArg = new(2); + `checkh(barArg.x, 2); + barExpr = new(7, "ABCDEFGHI"); + `checkh(barExpr.x, 16); + bar2Args = new(2, 12); + `checkh(bar2Args.x, 14); + noNew = new; + `checkh(noNew.x, 1); + newWithoutSuper = new; + `checkh(newWithoutSuper.x, 1); + noNewParam = new; + `checkh(noNewParam.x, 1); + newWithoutSuperParam = new; + `checkh(newWithoutSuperParam.x, 1); + barIf1 = new(1); + `checkh(barIf1.x, 1); + barIf10 = new(10); + `checkh(barIf10.x, 20); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_super_new2.v b/test_regress/t/t_class_super_new2.v index c3b35deee..5221b4398 100644 --- a/test_regress/t/t_class_super_new2.v +++ b/test_regress/t/t_class_super_new2.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 class svunit_base; - function new(string name); - endfunction + function new(string name); + endfunction endclass class svunit_testcase extends svunit_base; - function new(string name); - super.new(name); - endfunction + function new(string name); + super.new(name); + endfunction endclass module dut_unit_test; - svunit_testcase svunit_ut = new("dut_ut"); + svunit_testcase svunit_ut = new("dut_ut"); endmodule module t; - dut_unit_test dut_ut(); + dut_unit_test dut_ut (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_super_new_bad_nfirst.out b/test_regress/t/t_class_super_new_bad_nfirst.out index c33bfe35b..60fc86911 100644 --- a/test_regress/t/t_class_super_new_bad_nfirst.out +++ b/test_regress/t/t_class_super_new_bad_nfirst.out @@ -1,8 +1,8 @@ -%Error: t/t_class_super_new_bad_nfirst.v:18:13: 'super.new' not first statement in new function (IEEE 1800-2023 8.15) - 18 | super.new(imemberc); - | ^~~ - t/t_class_super_new_bad_nfirst.v:17:16: ... Location of earlier statement - 17 | imemberc = 10; - | ^ +%Error: t/t_class_super_new_bad_nfirst.v:18:11: 'super.new' not first statement in new function (IEEE 1800-2023 8.15) + 18 | super.new(imemberc); + | ^~~ + t/t_class_super_new_bad_nfirst.v:17:14: ... Location of earlier statement + 17 | imemberc = 10; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_super_new_bad_nfirst.v b/test_regress/t/t_class_super_new_bad_nfirst.v index f5505c012..4e487b3ff 100644 --- a/test_regress/t/t_class_super_new_bad_nfirst.v +++ b/test_regress/t/t_class_super_new_bad_nfirst.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 class Base; - int imemberb; - function new(int adder); - imemberb = 5 + adder; - endfunction + int imemberb; + function new(int adder); + imemberb = 5 + adder; + endfunction endclass class Cls extends Base; - int imemberc; - function new(); - imemberc = 10; - super.new(imemberc); // BAD not first - endfunction + int imemberc; + function new(); + imemberc = 10; + super.new(imemberc); // BAD not first + endfunction endclass module t; - initial begin - Cls c; - c = new; - if (c.imemberc != 10) $stop; - if (c.imemberb != 5) $stop; + initial begin + Cls c; + c = new; + if (c.imemberc != 10) $stop; + if (c.imemberb != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_this_constructor.v b/test_regress/t/t_class_this_constructor.v index 70bf8f045..338eff336 100644 --- a/test_regress/t/t_class_this_constructor.v +++ b/test_regress/t/t_class_this_constructor.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - bit x = 1'b0; - function new; - Cls c; - if (c == this) begin - x = 1'b1; - end - endfunction + bit x = 1'b0; + function new; + Cls c; + if (c == this) begin + x = 1'b1; + end + endfunction endclass module t; - Cls c; - initial begin - c = new; - if (c.x) $stop; + Cls c; + initial begin + c = new; + if (c.x) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_typedef.v b/test_regress/t/t_class_typedef.v index 89a79f563..16efdaf71 100644 --- a/test_regress/t/t_class_typedef.v +++ b/test_regress/t/t_class_typedef.v @@ -5,41 +5,44 @@ // SPDX-License-Identifier: CC0-1.0 class uvm_resource_types; - typedef int rsrc_q_t; + typedef int rsrc_q_t; endclass class uvm_resource_pool; - uvm_resource_types::rsrc_q_t rtab [string]; + uvm_resource_types::rsrc_q_t rtab[string]; endclass -virtual class C#(parameter type T = logic, parameter SIZE = 1); - typedef logic [SIZE-1:0] t_vector; - typedef T t_array [SIZE-1:0]; - typedef struct { - t_vector m0 [2*SIZE-1:0]; - t_array m1; - } t_struct; +virtual class C #( + parameter type T = logic, + parameter SIZE = 1 +); + typedef logic [SIZE-1:0] t_vector; + typedef T t_array[SIZE-1:0]; + typedef struct { + t_vector m0[2*SIZE-1:0]; + t_array m1; + } t_struct; endclass module t; - initial begin - automatic uvm_resource_pool pool = new; - typedef logic [7:0] t_t0; - C#(t_t0,3)::t_vector v0; - C#(t_t0,3)::t_array a0; - C#(bit,4)::t_struct s0; + initial begin + automatic uvm_resource_pool pool = new; + typedef logic [7:0] t_t0; + C #(t_t0, 3)::t_vector v0; + C #(t_t0, 3)::t_array a0; + C #(bit, 4)::t_struct s0; - pool.rtab["a"] = 1; - if ($bits(pool.rtab["a"]) != 32) $stop; + pool.rtab["a"] = 1; + if ($bits(pool.rtab["a"]) != 32) $stop; - if ($bits(v0) != 3) $stop; - if ($size(a0) != 3) $stop; - if ($bits(a0[0]) != 8) $stop; - if ($size(s0.m0) != 8) $stop; - if ($size(s0.m1) != 4) $stop; - if ($bits(s0.m1[2]) != 1) $stop; + if ($bits(v0) != 3) $stop; + if ($size(a0) != 3) $stop; + if ($bits(a0[0]) != 8) $stop; + if ($size(s0.m0) != 8) $stop; + if ($size(s0.m1) != 4) $stop; + if ($bits(s0.m1[2]) != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index 13febcf47..4d2c116c2 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_class_unsup_bad.v:24:21: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration - 24 | rand typedef int irand_t; - | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:24:20: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration + 24 | rand typedef int irand_t; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_unsup_bad.v:25:22: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration - 25 | randc typedef int icrand_t; - | ^~~~~~~~ -%Error: t/t_class_unsup_bad.v:31:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration - 31 | const function void func_const; endfunction - | ^~~~~~~~~~ +%Error: t/t_class_unsup_bad.v:25:21: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration + 25 | randc typedef int icrand_t; + | ^~~~~~~~ +%Error: t/t_class_unsup_bad.v:31:23: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration + 31 | const function void func_const; endfunction + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_unsup_bad.v b/test_regress/t/t_class_unsup_bad.v index 776fc3590..451a62bd8 100644 --- a/test_regress/t/t_class_unsup_bad.v +++ b/test_regress/t/t_class_unsup_bad.v @@ -11,25 +11,25 @@ typedef class c; typedef interface class ic; class C #(parameter P=1); - localparam LOCPAR = 10; - int imember; - static int istatic; + localparam LOCPAR = 10; + int imember; + static int istatic; - local int loc; - protected int prot; + local int loc; + protected int prot; - rand int irand; - randc int icrand; + rand int irand; + randc int icrand; - rand typedef int irand_t; - randc typedef int icrand_t; + rand typedef int irand_t; + randc typedef int icrand_t; - task classtask; endtask - function int classfunc; endfunction - virtual function void func_virtual; endfunction - pure virtual function void func_pure_virtual; - const function void func_const; endfunction - extern task exttask; + task classtask; endtask + function int classfunc; endfunction + virtual function void func_virtual; endfunction + pure virtual function void func_pure_virtual; + const function void func_const; endfunction + extern task exttask; endclass virtual class VC; @@ -42,8 +42,8 @@ typedef class uvm_root; typedef class uvm_coreservice_t; class uvm_default_coreservice_t extends uvm_coreservice_t; - virtual function uvm_root get_root(); - uvm_root::m_forward_task_call(); - return uvm_root::m_uvm_get_root(); - endfunction + virtual function uvm_root get_root(); + uvm_root::m_forward_task_call(); + return uvm_root::m_uvm_get_root(); + endfunction endclass diff --git a/test_regress/t/t_class_uses_this.v b/test_regress/t/t_class_uses_this.v index 5c34a587a..8887f7c6b 100644 --- a/test_regress/t/t_class_uses_this.v +++ b/test_regress/t/t_class_uses_this.v @@ -5,71 +5,71 @@ // SPDX-License-Identifier: CC0-1.0 // class Cls; - bit [3:0] addr; - function void set(bit [3:0] addr); - begin : body - this.addr = addr; - end : body - endfunction - function void set2(bit [3:0] addr); - begin : body - Cls c2 = this; - c2.addr = addr; - end : body - endfunction - extern function void setext(bit [3:0] addr); - extern function void setext2(bit [3:0] addr); + bit [3:0] addr; + function void set(bit [3:0] addr); + begin : body + this.addr = addr; + end : body + endfunction + function void set2(bit [3:0] addr); + begin : body + Cls c2 = this; + c2.addr = addr; + end : body + endfunction + extern function void setext(bit [3:0] addr); + extern function void setext2(bit [3:0] addr); endclass function void Cls::setext(bit [3:0] addr); - this.addr = addr; + this.addr = addr; endfunction function void Cls::setext2(bit [3:0] addr); - Cls c2 = this; - c2.addr = addr; + Cls c2 = this; + c2.addr = addr; endfunction class wrapped_int; - int x; - static wrapped_int q[$]; - function new(int a); - this.x = a; - endfunction - function void push_this; - q.push_back(this); - endfunction + int x; + static wrapped_int q[$]; + function new(int a); + this.x = a; + endfunction + function void push_this; + q.push_back(this); + endfunction endclass module t; - Cls bar; - Cls baz; - wrapped_int i1, i2; + Cls bar; + Cls baz; + wrapped_int i1, i2; - initial begin - bar = new(); - baz = new(); - bar.set(4); + initial begin + bar = new(); + baz = new(); + bar.set(4); `ifdef TEST_VERBOSE - $display(bar.addr); - $display(baz.addr); + $display(bar.addr); + $display(baz.addr); `endif - if (bar.addr != 4) $stop; - bar.set2(1); - if (bar.addr != 1) $stop; - bar.setext(2); - if (bar.addr != 2) $stop; - bar.setext2(3); - if (bar.addr != 3) $stop; + if (bar.addr != 4) $stop; + bar.set2(1); + if (bar.addr != 1) $stop; + bar.setext(2); + if (bar.addr != 2) $stop; + bar.setext2(3); + if (bar.addr != 3) $stop; - i1 = new(1); - i1.push_this(); - i2 = new(2); - i2.push_this(); - if (wrapped_int::q.size() != 2) $stop; + i1 = new(1); + i1.push_this(); + i2 = new(2); + i2.push_this(); + if (wrapped_int::q.size() != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_uses_this_bad.out b/test_regress/t/t_class_uses_this_bad.out index 3f6c06578..8f5e23b2f 100644 --- a/test_regress/t/t_class_uses_this_bad.out +++ b/test_regress/t/t_class_uses_this_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_uses_this_bad.v:11:12: 'this' used outside class (IEEE 1800-2023 8.11) - 11 | this.addr = 2; - | ^ +%Error: t/t_class_uses_this_bad.v:11:9: 'this' used outside class (IEEE 1800-2023 8.11) + 11 | this.addr = 2; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_uses_this_bad.v b/test_regress/t/t_class_uses_this_bad.v index 604eb42ed..1b1a198b2 100644 --- a/test_regress/t/t_class_uses_this_bad.v +++ b/test_regress/t/t_class_uses_this_bad.v @@ -6,10 +6,10 @@ // module t; - bit [3:0] addr; - initial begin - this.addr = 2; - $write("*-* All Finished *-*\n"); - $finish; - end + bit [3:0] addr; + initial begin + this.addr = 2; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_virtual.v b/test_regress/t/t_class_virtual.v index be46496e0..71c92db91 100644 --- a/test_regress/t/t_class_virtual.v +++ b/test_regress/t/t_class_virtual.v @@ -5,104 +5,104 @@ // SPDX-License-Identifier: CC0-1.0 virtual class VBase; - virtual function int hello; - return 1; - endfunction - virtual class VNested; - virtual function int hello; - return 10; - endfunction - endclass + virtual function int hello; + return 1; + endfunction + virtual class VNested; + virtual function int hello; + return 10; + endfunction + endclass endclass class VA extends VBase; - virtual function int hello; - return 2; - endfunction - class VNested extends VBase::VNested; - virtual function int hello; - return 20; - endfunction - endclass + virtual function int hello; + return 2; + endfunction + class VNested extends VBase::VNested; + virtual function int hello; + return 20; + endfunction + endclass endclass class VB extends VBase; - virtual function int hello; - return 3; - endfunction - class VNested extends VBase::VNested; - virtual function int hello; - return 30; - endfunction - endclass + virtual function int hello; + return 3; + endfunction + class VNested extends VBase::VNested; + virtual function int hello; + return 30; + endfunction + endclass endclass virtual class uvm_phase; - virtual function int exec_func; - return 0; - endfunction + virtual function int exec_func; + return 0; + endfunction endclass class uvm_topdown_phase extends uvm_phase; - function int get1; - return exec_func(); - endfunction + function int get1; + return exec_func(); + endfunction endclass class uvm_build_phase extends uvm_topdown_phase; - virtual function int exec_func; - return 1; - endfunction + virtual function int exec_func; + return 1; + endfunction endclass virtual class Cls; - uvm_phase ph; + uvm_phase ph; endclass class ExtendsCls extends Cls; - function new; - uvm_build_phase bp = new; - ph = bp; - endfunction + function new; + uvm_build_phase bp = new; + ph = bp; + endfunction - function int get1; - return super.ph.exec_func(); - endfunction + function int get1; + return super.ph.exec_func(); + endfunction endclass module t; - initial begin - automatic VA va = new; - automatic VB vb = new; - automatic VA::VNested vna = new; - automatic VB::VNested vnb = new; - automatic VBase b; - automatic VBase::VNested bn; + initial begin + automatic VA va = new; + automatic VB vb = new; + automatic VA::VNested vna = new; + automatic VB::VNested vnb = new; + automatic VBase b; + automatic VBase::VNested bn; - uvm_build_phase ph; - ExtendsCls ec; + uvm_build_phase ph; + ExtendsCls ec; - if (va.hello() != 2) $stop; - if (vb.hello() != 3) $stop; - if (vna.hello() != 20) $stop; - if (vnb.hello() != 30) $stop; + if (va.hello() != 2) $stop; + if (vb.hello() != 3) $stop; + if (vna.hello() != 20) $stop; + if (vnb.hello() != 30) $stop; - b = va; - bn = vna; - if (b.hello() != 2) $stop; - if (bn.hello() != 20) $stop; - b = vb; - bn = vnb; - if (b.hello() != 3) $stop; - if (bn.hello() != 30) $stop; + b = va; + bn = vna; + if (b.hello() != 2) $stop; + if (bn.hello() != 20) $stop; + b = vb; + bn = vnb; + if (b.hello() != 3) $stop; + if (bn.hello() != 30) $stop; - ph = new; - if (ph.get1() != 1) $stop; + ph = new; + if (ph.get1() != 1) $stop; - ec = new; - if (ec.get1() != 1) $stop; + ec = new; + if (ec.get1() != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_virtual_bad.out b/test_regress/t/t_class_virtual_bad.out index 9174bb2ab..1730824d7 100644 --- a/test_regress/t/t_class_virtual_bad.out +++ b/test_regress/t/t_class_virtual_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_virtual_bad.v:12:27: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) +%Error: t/t_class_virtual_bad.v:12:25: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) : ... note: In instance 't' - 12 | automatic VBase b = new; - | ^~~ + 12 | automatic VBase b = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_virtual_bad.v b/test_regress/t/t_class_virtual_bad.v index 86e3d6fb8..d5d2cf02e 100644 --- a/test_regress/t/t_class_virtual_bad.v +++ b/test_regress/t/t_class_virtual_bad.v @@ -8,7 +8,7 @@ virtual class VBase; endclass module t; - initial begin - automatic VBase b = new; // Error - end + initial begin + automatic VBase b = new; // Error + end endmodule diff --git a/test_regress/t/t_class_virtual_chain_ctor.v b/test_regress/t/t_class_virtual_chain_ctor.v index 0ac078f73..25ca09192 100644 --- a/test_regress/t/t_class_virtual_chain_ctor.v +++ b/test_regress/t/t_class_virtual_chain_ctor.v @@ -9,26 +9,27 @@ // VBase b = new; // see t_class_virtual_bad virtual class VBase; - function new(); endfunction + function new(); + endfunction endclass // Another constructor of an abstact class in the chain virtual class VChild1 extends VBase; - function new(); - super.new(); - endfunction + function new(); + super.new(); + endfunction endclass // It shall be perfectly fine to create an instance of a // non-abstract VChild2 class VChild2 extends VChild1; - function new(); - super.new(); - endfunction + function new(); + super.new(); + endfunction endclass module t; - initial begin - automatic VChild2 c = new; - end + initial begin + automatic VChild2 c = new; + end endmodule diff --git a/test_regress/t/t_class_virtual_pure_bad.out b/test_regress/t/t_class_virtual_pure_bad.out index bd8f0eab7..28c6e2907 100644 --- a/test_regress/t/t_class_virtual_pure_bad.out +++ b/test_regress/t/t_class_virtual_pure_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_virtual_pure_bad.v:8:22: Illegal to have 'pure virtual' in non-virtual class (IEEE 1800-2023 8.21) - 8 | pure virtual task pure_task; - | ^~~~~~~~~ +%Error: t/t_class_virtual_pure_bad.v:8:21: Illegal to have 'pure virtual' in non-virtual class (IEEE 1800-2023 8.21) + 8 | pure virtual task pure_task; + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_virtual_pure_bad.v b/test_regress/t/t_class_virtual_pure_bad.v index f235902f3..e58be88f5 100644 --- a/test_regress/t/t_class_virtual_pure_bad.v +++ b/test_regress/t/t_class_virtual_pure_bad.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 class VBase; - pure virtual task pure_task; + pure virtual task pure_task; endclass diff --git a/test_regress/t/t_class_vparam.v b/test_regress/t/t_class_vparam.v index 2ca8a683f..ca6e7d562 100644 --- a/test_regress/t/t_class_vparam.v +++ b/test_regress/t/t_class_vparam.v @@ -8,32 +8,38 @@ typedef class paramed_class_t; typedef class arg_class_t; -typedef paramed_class_t#(logic[3:0], 1) paramed_class_logic4_t; +typedef paramed_class_t#(logic [3:0], 1) paramed_class_logic4_t; -virtual class vclass #(type CTYPE_t = arg_class_t, int I = 0); - pure virtual function void funcname(paramed_class_t #(CTYPE_t) v); +virtual class vclass #( + type CTYPE_t = arg_class_t, + int I = 0 +); + pure virtual function void funcname(paramed_class_t#(CTYPE_t) v); endclass -class paramed_class_t #(type TYPE, int I = 0); - TYPE memb; +class paramed_class_t #( + type TYPE, + int I = 0 +); + TYPE memb; endclass class arg_class_t; - int ifield; + int ifield; endclass module t; - vclass vir; - paramed_class_t#(arg_class_t) argu; + vclass vir; + paramed_class_t #(arg_class_t) argu; - initial begin - argu = new; - argu.memb = new; - argu.memb.ifield = 1234; - // vir.funcname(argu); - if (argu.memb.ifield != 1234) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + argu = new; + argu.memb = new; + argu.memb.ifield = 1234; + // vir.funcname(argu); + if (argu.memb.ifield != 1234) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_wide.v b/test_regress/t/t_class_wide.v index 22fe39756..625520bd4 100644 --- a/test_regress/t/t_class_wide.v +++ b/test_regress/t/t_class_wide.v @@ -9,21 +9,20 @@ `endif class item; - bit [`WIDTH-1:0] data; + bit [`WIDTH-1:0] data; endclass module t; - logic [`WIDTH-1:0] data; - item item0 = new; + logic [`WIDTH-1:0] data; + item item0 = new; - initial begin - item0.data = `WIDTH'hda7ada7a; - data = item0.data; + initial begin + item0.data = `WIDTH'hda7ada7a; + data = item0.data; - if (data != `WIDTH'hda7ada7a) - $stop(); + if (data != `WIDTH'hda7ada7a) $stop(); - $write("*-* All Finished *-*\n"); - $finish(); - end + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_clk_2in.v b/test_regress/t/t_clk_2in.v index 1f40623b3..4d0f14290 100644 --- a/test_regress/t/t_clk_2in.v +++ b/test_regress/t/t_clk_2in.v @@ -6,51 +6,51 @@ `ifndef VERILATOR module t; - /*AUTOREGINPUT*/ - // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) - reg c0; // To t2 of t2.v - reg c1; // To t2 of t2.v - reg check; // To t2 of t2.v - reg [1:0] clks; // To t2 of t2.v - // End of automatics - t2 t2 (/*AUTOINST*/ - // Inputs - .clks (clks[1:0]), - .c0 (c0), - .c1 (c1), - .check (check)); - task clockit (input v1, v0); - c1 = v1; - c0 = v0; - clks[1] = v1; - clks[0] = v0; + /*AUTOREGINPUT*/ + // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) + reg c0; // To t2 of t2.v + reg c1; // To t2 of t2.v + reg check; // To t2 of t2.v + reg [1:0] clks; // To t2 of t2.v + // End of automatics + t2 t2 (/*AUTOINST*/ + // Inputs + .clks (clks[1:0]), + .c0 (c0), + .c1 (c1), + .check (check)); + task clockit (input v1, v0); + c1 = v1; + c0 = v0; + clks[1] = v1; + clks[0] = v0; `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif - #1; - endtask - initial begin - check = '0; - c0 = '0; - c1 = '0; - clks = '0; - #1 - t2.clear(); - #10; - for (int i=0; i<2; i++) begin - clockit(0, 0); - clockit(0, 0); - clockit(0, 1); - clockit(1, 1); - clockit(0, 0); - clockit(1, 1); - clockit(1, 0); - clockit(0, 0); - clockit(1, 0); - clockit(0, 1); - clockit(0, 0); - end - check = 1; + #1; + endtask + initial begin + check = '0; + c0 = '0; + c1 = '0; + clks = '0; + #1 + t2.clear(); + #10; + for (int i=0; i<2; i++) begin clockit(0, 0); - end + clockit(0, 0); + clockit(0, 1); + clockit(1, 1); + clockit(0, 0); + clockit(1, 1); + clockit(1, 0); + clockit(0, 0); + clockit(1, 0); + clockit(0, 1); + clockit(0, 0); + end + check = 1; + clockit(0, 0); + end endmodule `endif @@ -61,103 +61,103 @@ endmodule `endif module `t2 ( - input [1:0] clks, - input c0, - input c1, - input check - ); + input [1:0] clks, + input c0, + input c1, + input check + ); `ifdef T_CLK_2IN_VEC - wire clk0 = clks[0]; - wire clk1 = clks[1]; + wire clk0 = clks[0]; + wire clk1 = clks[1]; `else - wire clk0 = c0; - wire clk1 = c1; + wire clk0 = c0; + wire clk1 = c1; `endif - integer p0 = 0; - integer p1 = 0; - integer p01 = 0; - integer n0 = 0; - integer n1 = 0; - integer n01 = 0; - integer vp = 0; - integer vn = 0; - integer vpn = 0; - task clear; + integer p0 = 0; + integer p1 = 0; + integer p01 = 0; + integer n0 = 0; + integer n1 = 0; + integer n01 = 0; + integer vp = 0; + integer vn = 0; + integer vpn = 0; + task clear; `ifdef TEST_VERBOSE $display("[%0t] clear\n", $time); `endif - p0 = 0; - p1 = 0; - p01 = 0; - n0 = 0; - n1 = 0; - n01 = 0; - vp = 0; - vn = 0; - vpn = 0; - endtask + p0 = 0; + p1 = 0; + p01 = 0; + n0 = 0; + n1 = 0; + n01 = 0; + vp = 0; + vn = 0; + vpn = 0; + endtask `define display_counts(text) begin \ - $write("[%0t] ", $time); \ - `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \ - $write(text); \ - $write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \ - end + $write("[%0t] ", $time); \ + `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \ + $write(text); \ + $write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \ + end - always @ (posedge clk0) begin - p0 = p0 + 1; // Want blocking, so don't miss clock counts + always @ (posedge clk0) begin + p0 = p0 + 1; // Want blocking, so don't miss clock counts `ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif - end - always @ (posedge clk1) begin - p1 = p1 + 1; + end + always @ (posedge clk1) begin + p1 = p1 + 1; `ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif - end - always @ (posedge clk0 or posedge clk1) begin - p01 = p01 + 1; + end + always @ (posedge clk0 or posedge clk1) begin + p01 = p01 + 1; `ifdef TEST_VERBOSE `display_counts("posedge *"); `endif - end + end - always @ (negedge clk0) begin - n0 = n0 + 1; + always @ (negedge clk0) begin + n0 = n0 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif - end - always @ (negedge clk1) begin - n1 = n1 + 1; + end + always @ (negedge clk1) begin + n1 = n1 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif - end - always @ (negedge clk0 or negedge clk1) begin - n01 = n01 + 1; + end + always @ (negedge clk0 or negedge clk1) begin + n01 = n01 + 1; `ifdef TEST_VERBOSE `display_counts("negedge *"); `endif - end + end `ifndef VERILATOR - always @ (posedge clks) begin - vp = vp + 1; -`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif - end - always @ (negedge clks) begin - vn = vn + 1; -`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif - end - always @ (posedge clks or negedge clks) begin - vpn = vpn + 1; -`ifdef TEST_VERBOSE `display_counts("or vec"); `endif - end + always @ (posedge clks) begin + vp = vp + 1; +`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif + end + always @ (negedge clks) begin + vn = vn + 1; +`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif + end + always @ (posedge clks or negedge clks) begin + vpn = vpn + 1; +`ifdef TEST_VERBOSE `display_counts("or vec"); `endif + end `endif - always @ (posedge check) begin - if (p0!=6) $stop; - if (p1!=6) $stop; - if (p01!=10) $stop; - if (n0!=6) $stop; - if (n1!=6) $stop; - if (n01!=10) $stop; + always @ (posedge check) begin + if (p0!=6) $stop; + if (p1!=6) $stop; + if (p01!=10) $stop; + if (n0!=6) $stop; + if (n1!=6) $stop; + if (n01!=10) $stop; `ifndef VERILATOR - if (vp!=6) $stop; - if (vn!=6) $stop; - if (vpn!=12) $stop; + if (vp!=6) $stop; + if (vn!=6) $stop; + if (vpn!=12) $stop; `endif - $write("*-* All Finished *-*\n"); - end + $write("*-* All Finished *-*\n"); + end endmodule diff --git a/test_regress/t/t_clk_concat.v b/test_regress/t/t_clk_concat.v index 7e432d795..49a433e2e 100644 --- a/test_regress/t/t_clk_concat.v +++ b/test_regress/t/t_clk_concat.v @@ -5,99 +5,90 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [1 : 0] some_state; + logic [1:0] some_other_state; - always @(posedge wrclk) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge wrclk) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (wrclk) - some_other_state <= 0; - end + if (wrclk) some_other_state <= 0; + end endmodule `define BROKEN -module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [3:0] i_clks, + input i_clk0, + input i_clk1 +); - some_module - some_module - ( + some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk(i_clks[3]) `else - .wrclk (i_clk1) + .wrclk(i_clk1) `endif - ); + ); endmodule -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [3:0] the_clks; + logic data_q; - assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; + assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; - always @(posedge i_clk0) begin - data_q <= i_data; - end + always @(posedge i_clk0) begin + data_q <= i_data; + end - t1 t1 - ( - .i_clks (the_clks), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) - ); + t1 t1 ( + .i_clks(the_clks), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); endmodule -module t( +module t ( `ifdef ATTRIBUTES - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, `else - input clk0, - input clk1, - input clk2, + input clk0, + input clk1, + input clk2, `endif - input data_in - ); + input data_in +); - logic [2:0] clks; + logic [2:0] clks; - assign clks = {1'b0, clk1, clk0}; + assign clks = {1'b0, clk1, clk0}; - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk1), + .i_clk2(clk2), + .i_data(data_in) + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clk_concat2.v b/test_regress/t/t_clk_concat2.v index e13a56832..a69a984c0 100644 --- a/test_regress/t/t_clk_concat2.v +++ b/test_regress/t/t_clk_concat2.v @@ -5,102 +5,93 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [1 : 0] some_state; + logic [1:0] some_other_state; - always @(posedge wrclk) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge wrclk) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (wrclk) - some_other_state <= 0; - end + if (wrclk) some_other_state <= 0; + end endmodule `define BROKEN -module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [3:0] i_clks, + input i_clk0, + input i_clk1 +); - some_module - some_module - ( + some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk(i_clks[3]) `else - .wrclk (i_clk1) + .wrclk(i_clk1) `endif - ); + ); endmodule -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [3:0] the_clks; + logic data_q; - assign the_clks[3] = i_clk1; - assign the_clks[2] = i_clk2; - assign the_clks[1] = i_clk1; - assign the_clks[0] = i_clk0; + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; - always @(posedge i_clk0) begin - data_q <= i_data; - end + always @(posedge i_clk0) begin + data_q <= i_data; + end - t1 t1 - ( - .i_clks (the_clks), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) - ); + t1 t1 ( + .i_clks(the_clks), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); endmodule -module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); +module t ( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in +); - input clk; + input clk; - logic [2:0] clks; + logic [2:0] clks; - assign clks = {1'b0, clk1, clk0}; + assign clks = {1'b0, clk1, clk0}; - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk), + .i_clk2(clk2), + .i_data(data_in) + ); - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clk_concat3.v b/test_regress/t/t_clk_concat3.v index aa5a67c9e..12357961c 100644 --- a/test_regress/t/t_clk_concat3.v +++ b/test_regress/t/t_clk_concat3.v @@ -6,96 +6,87 @@ /* verilator lint_off ASCRANGE */ module some_module ( - input wrclk - ); + input wrclk +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [1 : 0] some_state; + logic [1:0] some_other_state; - always @(posedge wrclk) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge wrclk) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (wrclk) - some_other_state <= 0; - end + if (wrclk) some_other_state <= 0; + end endmodule `define BROKEN -module t1( - input [-12:-9] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [-12:-9] i_clks, + input i_clk0, + input i_clk1 +); - some_module - some_module - ( + some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[-12]) + .wrclk(i_clks[-12]) `else - .wrclk (i_clk1) + .wrclk(i_clk1) `endif - ); + ); endmodule -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [-12:-9] the_clks; - logic data_q; +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [-12:-9] the_clks; + logic data_q; - assign the_clks[-12] = i_clk1; - assign the_clks[-11] = i_clk2; - assign the_clks[-10] = i_clk1; - assign the_clks[-9] = i_clk0; + assign the_clks[-12] = i_clk1; + assign the_clks[-11] = i_clk2; + assign the_clks[-10] = i_clk1; + assign the_clks[-9] = i_clk0; - always @(posedge i_clk0) begin - data_q <= i_data; - end + always @(posedge i_clk0) begin + data_q <= i_data; + end - t1 t1 - ( - .i_clks (the_clks), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) - ); + t1 t1 ( + .i_clks(the_clks), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); endmodule -module t( - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); +module t ( + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in +); - logic [2:0] clks; + logic [2:0] clks; - assign clks = {1'b0, clk1, clk0}; + assign clks = {1'b0, clk1, clk0}; - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk1), + .i_clk2(clk2), + .i_data(data_in) + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clk_concat4.v b/test_regress/t/t_clk_concat4.v index 98a9b1407..2749f7dc2 100644 --- a/test_regress/t/t_clk_concat4.v +++ b/test_regress/t/t_clk_concat4.v @@ -5,101 +5,92 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [1 : 0] some_state; + logic [1:0] some_other_state; - always @(posedge wrclk) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge wrclk) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (wrclk) - some_other_state <= 0; - end + if (wrclk) some_other_state <= 0; + end endmodule `define BROKEN -module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [3:0] i_clks, + input i_clk0, + input i_clk1 +); - generate - genvar i; - for (i = 0; i < 2; i = i + 1) begin: a_generate_block - some_module - some_module - ( + generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin : a_generate_block + some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk(i_clks[3]) `else - .wrclk (i_clk1) + .wrclk(i_clk1) `endif - ); - end - endgenerate -endmodule - -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; - - assign the_clks[3] = i_clk1; - assign the_clks[2] = i_clk2; - assign the_clks[1] = i_clk1; - assign the_clks[0] = i_clk0; - - always @(posedge i_clk0) begin - data_q <= i_data; - end - - t1 t1 - ( - .i_clks (the_clks), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) ); + end + endgenerate endmodule -module t( - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [3:0] the_clks; + logic data_q; - logic [2:0] clks; + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; - assign clks = {1'b0, clk1, clk0}; + always @(posedge i_clk0) begin + data_q <= i_data; + end - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + t1 t1 ( + .i_clks(the_clks), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); +endmodule + +module t ( + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in +); + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk1), + .i_clk2(clk2), + .i_data(data_in) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clk_concat5.v b/test_regress/t/t_clk_concat5.v index 245a0e323..1757f1f44 100644 --- a/test_regress/t/t_clk_concat5.v +++ b/test_regress/t/t_clk_concat5.v @@ -5,100 +5,89 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input [3:0] i_clks - ); + input [3:0] i_clks +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [1 : 0] some_state; + logic [1:0] some_other_state; - always @(posedge i_clks[3]) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge i_clks[3]) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (i_clks[3]) - some_other_state <= 0; + if (i_clks[3]) some_other_state <= 0; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule `define BROKEN -module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [3:0] i_clks, + input i_clk0, + input i_clk1 +); - some_module - some_module - ( - .i_clks (i_clks) - ); + some_module some_module (.i_clks(i_clks)); endmodule -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [3:0] the_clks; + logic data_q; - assign the_clks[3] = i_clk1; - assign the_clks[2] = i_clk2; - assign the_clks[1] = i_clk1; - assign the_clks[0] = i_clk0; + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; - always @(posedge i_clk0) begin - data_q <= i_data; - end + always @(posedge i_clk0) begin + data_q <= i_data; + end - t1 t1 - ( - .i_clks (the_clks), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) - ); + t1 t1 ( + .i_clks(the_clks), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); endmodule -module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); +module t ( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in +); - input clk; + input clk; - logic [2:0] clks; + logic [2:0] clks; - assign clks = {1'b0, clk1, clk0}; + assign clks = {1'b0, clk1, clk0}; - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk), + .i_clk2(clk2), + .i_data(data_in) + ); - // initial begin - // $write("*-* All Finished *-*\n"); - // $finish; - // end + // initial begin + // $write("*-* All Finished *-*\n"); + // $finish; + // end endmodule diff --git a/test_regress/t/t_clk_concat6.v b/test_regress/t/t_clk_concat6.v index 07b623e97..78d5e79e8 100644 --- a/test_regress/t/t_clk_concat6.v +++ b/test_regress/t/t_clk_concat6.v @@ -5,109 +5,96 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input [3:0] i_clks - ); + input [3:0] i_clks +); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; - logic the_clk; + logic [1 : 0] some_state; + logic [1:0] some_other_state; + logic the_clk; - assign the_clk = i_clks[3]; + assign the_clk = i_clks[3]; - always @(posedge the_clk) begin - case (some_state) - 2'b11: - if (some_other_state == 0) - some_state <= 2'b00; - default: - $display ("This is a display statement"); - endcase + always @(posedge the_clk) begin + case (some_state) + 2'b11: if (some_other_state == 0) some_state <= 2'b00; + default: $display("This is a display statement"); + endcase - if (the_clk) - some_other_state <= 0; + if (the_clk) some_other_state <= 0; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule `define BROKEN -module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); +module t1 ( + input [3:0] i_clks, + input i_clk0, + input i_clk1 +); - some_module - some_module - ( - .i_clks (i_clks) - ); + some_module some_module (.i_clks(i_clks)); endmodule -module ident( - input i_ident, - output o_ident - ); - assign o_ident = i_ident; +module ident ( + input i_ident, + output o_ident +); + assign o_ident = i_ident; endmodule -module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; - logic ident_clk1; +module t2 ( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data +); + logic [3:0] the_clks; + logic data_q; + logic ident_clk1; - always @(posedge i_clk0) begin - data_q <= i_data; - end + always @(posedge i_clk0) begin + data_q <= i_data; + end - ident - ident - ( - .i_ident (i_clk1), - .o_ident (ident_clk1) - ); + ident ident ( + .i_ident(i_clk1), + .o_ident(ident_clk1) + ); - t1 t1 - ( - .i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}), - .i_clk0 (i_clk0), - .i_clk1 (i_clk1) - ); + t1 t1 ( + .i_clks({ident_clk1, i_clk2, ident_clk1, i_clk0}), + .i_clk0(i_clk0), + .i_clk1(i_clk1) + ); endmodule -module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/ /*verilator public_flat*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); +module t ( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/ /*verilator public_flat*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in +); - input clk; + input clk; - logic [2:0] clks; + logic [2:0] clks; - assign clks = {1'b0, clk1, clk0}; + assign clks = {1'b0, clk1, clk0}; - t2 - t2 - ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + t2 t2 ( + .i_clks(clks), + .i_clk0(clk0), + .i_clk1(clk), + .i_clk2(clk2), + .i_data(data_in) + ); endmodule diff --git a/test_regress/t/t_clk_condflop.v b/test_regress/t/t_clk_condflop.v index f64151e29..483738a78 100644 --- a/test_regress/t/t_clk_condflop.v +++ b/test_regress/t/t_clk_condflop.v @@ -4,122 +4,167 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + clk +); + input clk; - reg [0:0] d1; - reg [2:0] d3; - reg [7:0] d8; + reg [0:0] d1; + reg [2:0] d3; + reg [7:0] d8; - wire [0:0] q1; - wire [2:0] q3; - wire [7:0] q8; + wire [0:0] q1; + wire [2:0] q3; + wire [7:0] q8; - reg ena; + reg ena; - condff #(12) condff - (.clk(clk), .sen(1'b0), .ena(ena), - .d({d8,d3,d1}), - .q({q8,q3,q1})); + condff #(12) condff ( + .clk(clk), + .sen(1'b0), + .ena(ena), + .d({d8, d3, d1}), + .q({q8, q3, q1}) + ); - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - //$write("%x %x %x %x\n", cyc, q8, q3, q1); - cyc <= cyc + 1; - if (cyc==1) begin - d1 <= 1'b1; d3<=3'h1; d8<=8'h11; - ena <= 1'b1; - end - if (cyc==2) begin - d1 <= 1'b0; d3<=3'h2; d8<=8'h33; - ena <= 1'b0; - end - if (cyc==3) begin - d1 <= 1'b1; d3<=3'h3; d8<=8'h44; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==4) begin - d1 <= 1'b1; d3<=3'h4; d8<=8'h77; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==5) begin - d1 <= 1'b1; d3<=3'h0; d8<=8'h88; - ena <= 1'b1; - if (q8 != 8'h44) $stop; - end - if (cyc==6) begin - if (q8 != 8'h77) $stop; - end - if (cyc==7) begin - if (q8 != 8'h88) $stop; - end - // - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + //$write("%x %x %x %x\n", cyc, q8, q3, q1); + cyc <= cyc + 1; + if (cyc == 1) begin + d1 <= 1'b1; + d3 <= 3'h1; + d8 <= 8'h11; + ena <= 1'b1; end - end + if (cyc == 2) begin + d1 <= 1'b0; + d3 <= 3'h2; + d8 <= 8'h33; + ena <= 1'b0; + end + if (cyc == 3) begin + d1 <= 1'b1; + d3 <= 3'h3; + d8 <= 8'h44; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc == 4) begin + d1 <= 1'b1; + d3 <= 3'h4; + d8 <= 8'h77; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc == 5) begin + d1 <= 1'b1; + d3 <= 3'h0; + d8 <= 8'h88; + ena <= 1'b1; + if (q8 != 8'h44) $stop; + end + if (cyc == 6) begin + if (q8 != 8'h77) $stop; + end + if (cyc == 7) begin + if (q8 != 8'h88) $stop; + end + // + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module condff (clk, sen, ena, d, q); - parameter WIDTH = 1; - input clk; +module condff ( + clk, + sen, + ena, + d, + q +); + parameter WIDTH = 1; + input clk; - input sen; - input ena; - input [WIDTH-1:0] d; - output [WIDTH-1:0] q; + input sen; + input ena; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; - condffimp #(.WIDTH(WIDTH)) - imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); + condffimp #( + .WIDTH(WIDTH) + ) imp ( + .clk(clk), + .sen(sen), + .ena(ena), + .d(d), + .q(q) + ); endmodule -module condffimp (clk, sen, ena, d, q); - parameter WIDTH = 1; - input clk; - input sen; - input ena; - input [WIDTH-1:0] d; - output reg [WIDTH-1:0] q; - wire gatedclk; +module condffimp ( + clk, + sen, + ena, + d, + q +); + parameter WIDTH = 1; + input clk; + input sen; + input ena; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + wire gatedclk; - clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); + clockgate clockgate ( + .clk(clk), + .sen(sen), + .ena(ena), + .gatedclk(gatedclk) + ); - always @(posedge gatedclk) begin - if (gatedclk === 1'bX) begin - q <= {WIDTH{1'bX}}; - end - else begin - q <= d; - end - end + always @(posedge gatedclk) begin + if (gatedclk === 1'bX) begin + q <= {WIDTH{1'bX}}; + end + else begin + q <= d; + end + end endmodule -module clockgate (clk, sen, ena, gatedclk); - input clk; - input sen; - input ena; - output gatedclk; +module clockgate ( + clk, + sen, + ena, + gatedclk +); + input clk; + input sen; + input ena; + output gatedclk; - reg ena_b; - wire gatedclk = clk & ena_b; + reg ena_b; + wire gatedclk = clk & ena_b; - // verilator lint_off COMBDLY - // verilator lint_off LATCH - always @(clk or ena or sen) begin - if (~clk) begin - ena_b <= ena | sen; - end - else begin - if ((clk^sen)===1'bX) ena_b <= 1'bX; - end - end - // verilator lint_on LATCH - // verilator lint_on COMBDLY + // verilator lint_off COMBDLY + // verilator lint_off LATCH + always @(clk or ena or sen) begin + if (~clk) begin + ena_b <= ena | sen; + end + else begin + if ((clk ^ sen) === 1'bX) ena_b <= 1'bX; + end + end + // verilator lint_on LATCH + // verilator lint_on COMBDLY endmodule diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v index 6a7b74236..1d580c69d 100644 --- a/test_regress/t/t_clk_dpulse.v +++ b/test_regress/t/t_clk_dpulse.v @@ -4,42 +4,43 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - reg [7:0] cyc; initial cyc = 0; - reg genclk; - // verilator lint_off MULTIDRIVEN - reg [7:0] set_both; - // verilator lint_on MULTIDRIVEN + reg [7:0] cyc; + initial cyc = 0; + reg genclk; + // verilator lint_off MULTIDRIVEN + reg [7:0] set_both; + // verilator lint_on MULTIDRIVEN - wire genthiscyc = ( (cyc % 2) == 1 ); + wire genthiscyc = ((cyc % 2) == 1); - always @ (posedge clk) begin - cyc <= cyc + 8'h1; - genclk <= genthiscyc; - set_both <= cyc; - $write ("SB set_both %x <= cyc %x\n", set_both, cyc); - if (genthiscyc) begin - if (cyc>1 && set_both != (cyc - 8'h1)) $stop; - end - else begin - if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 8'h1; + genclk <= genthiscyc; + set_both <= cyc; + $write("SB set_both %x <= cyc %x\n", set_both, cyc); + if (genthiscyc) begin + if (cyc > 1 && set_both != (cyc - 8'h1)) $stop; + end + else begin + if (cyc > 1 && set_both != ~(cyc - 8'h1)) $stop; + end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @ (posedge genclk) begin - set_both <= ~ set_both; - $write ("SB set_both %x <= cyc %x\n", set_both, ~cyc); - if (cyc>1 && set_both != (cyc - 8'h1)) $stop; - end + always @(posedge genclk) begin + set_both <= ~set_both; + $write("SB set_both %x <= cyc %x\n", set_both, ~cyc); + if (cyc > 1 && set_both != (cyc - 8'h1)) $stop; + end endmodule diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v index 5d3c205c0..0298d7b67 100644 --- a/test_regress/t/t_clk_dsp.v +++ b/test_regress/t/t_clk_dsp.v @@ -4,171 +4,180 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - reg [7:0] cyc; initial cyc = 0; - reg [7:0] padd; - reg dsp_ph1, dsp_ph2, dsp_reset; + reg [7:0] cyc; + initial cyc = 0; + reg [7:0] padd; + reg dsp_ph1, dsp_ph2, dsp_reset; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] out; // From dspchip of t_dspchip.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] out; // From dspchip of t_dspchip.v + // End of automatics - t_dspchip dspchip (/*AUTOINST*/ - // Outputs - .out (out[7:0]), - // Inputs - .dsp_ph1 (dsp_ph1), - .dsp_ph2 (dsp_ph2), - .dsp_reset (dsp_reset), - .padd (padd[7:0])); + t_dspchip dspchip ( /*AUTOINST*/ + // Outputs + .out(out[7:0]), + // Inputs + .dsp_ph1(dsp_ph1), + .dsp_ph2(dsp_ph2), + .dsp_reset(dsp_reset), + .padd(padd[7:0]) + ); - always @ (posedge clk) begin - $write("cyc %d\n",cyc); - if (cyc == 8'd0) begin - cyc <= 8'd1; - dsp_reset <= 0; // Need a posedge - padd <= 0; - end - else if (cyc == 8'd20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - cyc <= cyc + 8'd1; - dsp_ph1 <= ((cyc&8'd3) == 8'd0); - dsp_ph2 <= ((cyc&8'd3) == 8'd2); - dsp_reset <= (cyc == 8'd1); - padd <= cyc; - //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); - case (cyc) - default: $stop; - 8'd01: ; - 8'd02: ; - 8'd03: ; - 8'd04: ; - 8'd05: ; - 8'd06: ; - 8'd07: ; - 8'd08: ; - 8'd09: if (out!==8'h04) $stop; - 8'd10: if (out!==8'h04) $stop; - 8'd11: if (out!==8'h08) $stop; - 8'd12: if (out!==8'h08) $stop; - 8'd13: if (out!==8'h00) $stop; - 8'd14: if (out!==8'h00) $stop; - 8'd15: if (out!==8'h00) $stop; - 8'd16: if (out!==8'h00) $stop; - 8'd17: if (out!==8'h0c) $stop; - 8'd18: if (out!==8'h0c) $stop; - 8'd19: if (out!==8'h10) $stop; - endcase - end - end + always @(posedge clk) begin + $write("cyc %d\n", cyc); + if (cyc == 8'd0) begin + cyc <= 8'd1; + dsp_reset <= 0; // Need a posedge + padd <= 0; + end + else if (cyc == 8'd20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + cyc <= cyc + 8'd1; + dsp_ph1 <= ((cyc & 8'd3) == 8'd0); + dsp_ph2 <= ((cyc & 8'd3) == 8'd2); + dsp_reset <= (cyc == 8'd1); + padd <= cyc; + //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); + case (cyc) + default: $stop; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: ; + 8'd05: ; + 8'd06: ; + 8'd07: ; + 8'd08: ; + 8'd09: if (out !== 8'h04) $stop; + 8'd10: if (out !== 8'h04) $stop; + 8'd11: if (out !== 8'h08) $stop; + 8'd12: if (out !== 8'h08) $stop; + 8'd13: if (out !== 8'h00) $stop; + 8'd14: if (out !== 8'h00) $stop; + 8'd15: if (out !== 8'h00) $stop; + 8'd16: if (out !== 8'h00) $stop; + 8'd17: if (out !== 8'h0c) $stop; + 8'd18: if (out !== 8'h0c) $stop; + 8'd19: if (out !== 8'h10) $stop; + endcase + end + end endmodule -module t_dspchip (/*AUTOARG*/ - // Outputs - out, - // Inputs - dsp_ph1, dsp_ph2, dsp_reset, padd - ); - input dsp_ph1, dsp_ph2, dsp_reset; - input [7:0] padd; - output [7:0] out; +module t_dspchip ( /*AUTOARG*/ + // Outputs + out, + // Inputs + dsp_ph1, + dsp_ph2, + dsp_reset, + padd +); + input dsp_ph1, dsp_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out; - wire dsp_ph1, dsp_ph2; - wire [7:0] out; - wire pla_ph1, pla_ph2; - wire out1_r; - wire [7:0] out2_r, padd; - wire clk_en; + wire dsp_ph1, dsp_ph2; + wire [7:0] out; + wire pla_ph1, pla_ph2; + wire out1_r; + wire [7:0] out2_r, padd; + wire clk_en; - t_dspcore t_dspcore (/*AUTOINST*/ - // Outputs - .out1_r (out1_r), - .pla_ph1 (pla_ph1), - .pla_ph2 (pla_ph2), - // Inputs - .dsp_ph1 (dsp_ph1), - .dsp_ph2 (dsp_ph2), - .dsp_reset (dsp_reset), - .clk_en (clk_en)); - t_dsppla t_dsppla (/*AUTOINST*/ - // Outputs - .out2_r (out2_r[7:0]), - // Inputs - .pla_ph1 (pla_ph1), - .pla_ph2 (pla_ph2), - .dsp_reset (dsp_reset), - .padd (padd[7:0])); + t_dspcore t_dspcore ( /*AUTOINST*/ + // Outputs + .out1_r(out1_r), + .pla_ph1(pla_ph1), + .pla_ph2(pla_ph2), + // Inputs + .dsp_ph1(dsp_ph1), + .dsp_ph2(dsp_ph2), + .dsp_reset(dsp_reset), + .clk_en(clk_en) + ); + t_dsppla t_dsppla ( /*AUTOINST*/ + // Outputs + .out2_r(out2_r[7:0]), + // Inputs + .pla_ph1(pla_ph1), + .pla_ph2(pla_ph2), + .dsp_reset(dsp_reset), + .padd(padd[7:0]) + ); - assign out = out1_r ? 8'h00 : out2_r; - assign clk_en = 1'b1; + assign out = out1_r ? 8'h00 : out2_r; + assign clk_en = 1'b1; endmodule -module t_dspcore (/*AUTOARG*/ - // Outputs - out1_r, pla_ph1, pla_ph2, - // Inputs - dsp_ph1, dsp_ph2, dsp_reset, clk_en - ); - input dsp_ph1, dsp_ph2, dsp_reset; - input clk_en; - output out1_r, pla_ph1, pla_ph2; +module t_dspcore ( /*AUTOARG*/ + // Outputs + out1_r, + pla_ph1, + pla_ph2, + // Inputs + dsp_ph1, + dsp_ph2, + dsp_reset, + clk_en +); + input dsp_ph1, dsp_ph2, dsp_reset; + input clk_en; + output out1_r, pla_ph1, pla_ph2; - wire dsp_ph1, dsp_ph2, dsp_reset; - wire pla_ph1, pla_ph2; - reg out1_r; + wire dsp_ph1, dsp_ph2, dsp_reset; + wire pla_ph1, pla_ph2; + reg out1_r; - always @(posedge dsp_ph1 or posedge dsp_reset) begin - if (dsp_reset) - out1_r <= 1'h0; - else - out1_r <= ~out1_r; - end + always @(posedge dsp_ph1 or posedge dsp_reset) begin + if (dsp_reset) out1_r <= 1'h0; + else out1_r <= ~out1_r; + end - assign pla_ph1 = dsp_ph1; - assign pla_ph2 = dsp_ph2 & clk_en; + assign pla_ph1 = dsp_ph1; + assign pla_ph2 = dsp_ph2 & clk_en; endmodule -module t_dsppla (/*AUTOARG*/ - // Outputs - out2_r, - // Inputs - pla_ph1, pla_ph2, dsp_reset, padd - ); - input pla_ph1, pla_ph2, dsp_reset; - input [7:0] padd; - output [7:0] out2_r; +module t_dsppla ( /*AUTOARG*/ + // Outputs + out2_r, + // Inputs + pla_ph1, + pla_ph2, + dsp_reset, + padd +); + input pla_ph1, pla_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out2_r; - wire pla_ph1, pla_ph2, dsp_reset; - wire [7:0] padd; - reg [7:0] out2_r; + wire pla_ph1, pla_ph2, dsp_reset; + wire [7:0] padd; + reg [7:0] out2_r; - reg [7:0] latched_r; + reg [7:0] latched_r; - always @(posedge pla_ph1 or posedge dsp_reset) begin - if (dsp_reset) - latched_r <= 8'h00; - else - latched_r <= padd; - end + always @(posedge pla_ph1 or posedge dsp_reset) begin + if (dsp_reset) latched_r <= 8'h00; + else latched_r <= padd; + end - always @(posedge pla_ph2 or posedge dsp_reset) begin - if (dsp_reset) - out2_r <= 8'h00; - else - out2_r <= latched_r; - end + always @(posedge pla_ph2 or posedge dsp_reset) begin + if (dsp_reset) out2_r <= 8'h00; + else out2_r <= latched_r; + end endmodule diff --git a/test_regress/t/t_clk_first.v b/test_regress/t/t_clk_first.v index 2080733d0..5a971d02a 100644 --- a/test_regress/t/t_clk_first.v +++ b/test_regress/t/t_clk_first.v @@ -4,196 +4,220 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, fastclk - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + fastclk +); - input clk; - input fastclk; - reg reset_l; + input clk; + input fastclk; + reg reset_l; - int cyc; - initial reset_l = 0; - always @ (posedge clk) begin - if (cyc==0) reset_l <= 1'b1; - else if (cyc==1) reset_l <= 1'b0; - else if (cyc==10) reset_l <= 1'b1; - end + int cyc; + initial reset_l = 0; + always @(posedge clk) begin + if (cyc == 0) reset_l <= 1'b1; + else if (cyc == 1) reset_l <= 1'b0; + else if (cyc == 10) reset_l <= 1'b1; + end - t_clk t (/*AUTOINST*/ - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l)); + t_clk t ( /*AUTOINST*/ + // Inputs + .clk(clk), + .fastclk(fastclk), + .reset_l(reset_l) + ); endmodule -module t_clk (/*AUTOARG*/ - // Inputs - clk, fastclk, reset_l - ); +module t_clk ( /*AUTOARG*/ + // Inputs + clk, + fastclk, + reset_l +); - input clk; - input fastclk; - input reset_l; + input clk; + input fastclk; + input reset_l; - // surefire lint_off STMINI - // surefire lint_off CWECSB - // surefire lint_off NBAJAM - reg _ranit; initial _ranit=0; - // surefire lint_off UDDSMX - reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT - wire [7:0] clk_clocks_d1r; - wire [7:0] clk_clocks_d1sr; - wire [7:0] clk_clocks_cp2_d1r; - wire [7:0] clk_clocks_cp2_d1sr; - // verilator lint_off MULTIDRIVEN - reg [7:0] int_clocks; initial int_clocks = 0; - // verilator lint_on MULTIDRIVEN - reg [7:0] int_clocks_copy; + // surefire lint_off STMINI + // surefire lint_off CWECSB + // surefire lint_off NBAJAM + reg _ranit; + initial _ranit = 0; + // surefire lint_off UDDSMX + reg [7:0] clk_clocks; + initial clk_clocks = 0; // surefire lint_off_line WRTWRT + wire [7:0] clk_clocks_d1r; + wire [7:0] clk_clocks_d1sr; + wire [7:0] clk_clocks_cp2_d1r; + wire [7:0] clk_clocks_cp2_d1sr; + // verilator lint_off MULTIDRIVEN + reg [7:0] int_clocks; + initial int_clocks = 0; + // verilator lint_on MULTIDRIVEN + reg [7:0] int_clocks_copy; - reg internal_clk; initial internal_clk = 0; - reg reset_int_; + reg internal_clk; + initial internal_clk = 0; + reg reset_int_; - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] CLK1 %x\n", $time, reset_l); + $write("[%0t] CLK1 %x\n", $time, reset_l); `endif - if (!reset_l) begin - clk_clocks <= 0; - int_clocks <= 0; - internal_clk <= 1'b1; - reset_int_ <= 0; - end - else begin - internal_clk <= ~internal_clk; - if (!_ranit) begin - _ranit <= 1; + if (!reset_l) begin + clk_clocks <= 0; + int_clocks <= 0; + internal_clk <= 1'b1; + reset_int_ <= 0; + end + else begin + internal_clk <= ~internal_clk; + if (!_ranit) begin + _ranit <= 1; `ifdef TEST_VERBOSE - $write("[%0t] t_clk: Running\n", $time); + $write("[%0t] t_clk: Running\n", $time); `endif - reset_int_ <= 1; - end + reset_int_ <= 1; end - end + end + end - reg [7:0] sig_rst; - always @ (posedge clk or negedge reset_l) begin + reg [7:0] sig_rst; + always @(posedge clk or negedge reset_l) begin `ifdef TEST_VERBOSE - $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst); + $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst); `endif - if (!reset_l) begin - sig_rst <= 0; - end - else begin - sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB - end - end + if (!reset_l) begin + sig_rst <= 0; + end + else begin + sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB + end + end - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst); + $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst); `endif - if (!reset_l) begin - clk_clocks <= 0; + if (!reset_l) begin + clk_clocks <= 0; + end + else begin + clk_clocks <= clk_clocks + 8'd1; + if (clk_clocks == 4) begin + if (sig_rst !== 4) $stop; + if (clk_clocks_d1r !== 3) $stop; + if (int_clocks !== 2) $stop; + if (int_clocks_copy !== 2) $stop; + if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; + if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - else begin - clk_clocks <= clk_clocks + 8'd1; - if (clk_clocks == 4) begin - if (sig_rst !== 4) $stop; - if (clk_clocks_d1r !== 3) $stop; - if (int_clocks !== 2) $stop; - if (int_clocks_copy !== 2) $stop; - if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; - if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - end + end + end - reg [7:0] resetted; - always @ (posedge clk or negedge reset_int_) begin + reg [7:0] resetted; + always @(posedge clk or negedge reset_int_) begin `ifdef TEST_VERBOSE - $write("[%0t] CLK4 %x\n", $time, reset_l); + $write("[%0t] CLK4 %x\n", $time, reset_l); `endif - if (!reset_int_) begin - resetted <= 0; - end - else begin - resetted <= resetted + 8'd1; - end - end + if (!reset_int_) begin + resetted <= 0; + end + else begin + resetted <= resetted + 8'd1; + end + end - always @ (int_clocks) begin - int_clocks_copy = int_clocks; - end + always @(int_clocks) begin + int_clocks_copy = int_clocks; + end - always @ (negedge internal_clk) begin - int_clocks <= int_clocks + 8'd1; - end + always @(negedge internal_clk) begin + int_clocks <= int_clocks + 8'd1; + end - t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks), - .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); - t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks), - .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); - t_clk_two two (/*AUTOINST*/ - // Inputs - .fastclk (fastclk), - .reset_l (reset_l)); + t_clk_flop flopa ( + .clk(clk), + .clk2(fastclk), + .a(clk_clocks), + .q(clk_clocks_d1r), + .q2(clk_clocks_d1sr) + ); + t_clk_flop flopb ( + .clk(clk), + .clk2(fastclk), + .a(clk_clocks), + .q(clk_clocks_cp2_d1r), + .q2(clk_clocks_cp2_d1sr) + ); + t_clk_two two ( /*AUTOINST*/ + // Inputs + .fastclk(fastclk), + .reset_l(reset_l) + ); endmodule -module t_clk_flop (/*AUTOARG*/ - // Outputs - q, q2, - // Inputs - clk, clk2, a - ); - parameter WIDTH=8; - input clk; - input clk2; - input [(WIDTH-1):0] a; - output [(WIDTH-1):0] q; - output [(WIDTH-1):0] q2; - reg [(WIDTH-1):0] q; - reg [(WIDTH-1):0] q2; - always @ (posedge clk) q<=a; - always @ (posedge clk2) q2<=a; +module t_clk_flop ( /*AUTOARG*/ + // Outputs + q, + q2, + // Inputs + clk, + clk2, + a +); + parameter WIDTH = 8; + input clk; + input clk2; + input [(WIDTH-1):0] a; + output [(WIDTH-1):0] q; + output [(WIDTH-1):0] q2; + reg [(WIDTH-1):0] q; + reg [(WIDTH-1):0] q2; + always @(posedge clk) q <= a; + always @(posedge clk2) q2 <= a; endmodule -module t_clk_two (/*AUTOARG*/ - // Inputs - fastclk, reset_l - ); - input fastclk; - input reset_l; - reg clk2; - reg [31:0] count; +module t_clk_two ( /*AUTOARG*/ + // Inputs + fastclk, + reset_l +); + input fastclk; + input reset_l; + reg clk2; + reg [31:0] count; - t_clk_twob tb (.*); + t_clk_twob tb (.*); - wire reset_h = ~reset_l; - always @ (posedge fastclk) begin - if (reset_h) clk2 <= 0; - else clk2 <= ~clk2; - end - always @ (posedge clk2) begin - if (reset_h) count <= 0; - else count <= count + 1; - end + wire reset_h = ~reset_l; + always @(posedge fastclk) begin + if (reset_h) clk2 <= 0; + else clk2 <= ~clk2; + end + always @(posedge clk2) begin + if (reset_h) count <= 0; + else count <= count + 1; + end endmodule -module t_clk_twob (/*AUTOARG*/ - // Inputs - fastclk, reset_l - ); - input fastclk; - input reset_l; +module t_clk_twob ( /*AUTOARG*/ + // Inputs + fastclk, + reset_l +); + input fastclk; + input reset_l; - always @ (posedge fastclk) begin - // Extra line coverage point, just to make sure coverage - // hierarchy under inlining lands properly - if (reset_l) ; - end + always @(posedge fastclk) begin + // Extra line coverage point, just to make sure coverage + // hierarchy under inlining lands properly + if (reset_l); + end endmodule diff --git a/test_regress/t/t_clk_first_bad.out b/test_regress/t/t_clk_first_bad.out index 0f3358053..9ce9543db 100644 --- a/test_regress/t/t_clk_first_bad.out +++ b/test_regress/t/t_clk_first_bad.out @@ -1,5 +1,5 @@ %Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is ignored - 12 | input clk /*verilator sc_clock*/; + 12 | input clk /*verilator sc_clock*/; | ^~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_clk_first_deprecated.v b/test_regress/t/t_clk_first_deprecated.v index f0f38a74c..9142eb9ab 100644 --- a/test_regress/t/t_clk_first_deprecated.v +++ b/test_regress/t/t_clk_first_deprecated.v @@ -4,11 +4,11 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk /*verilator sc_clock*/; + input clk /*verilator sc_clock*/; endmodule diff --git a/test_regress/t/t_clk_gate_ext.v b/test_regress/t/t_clk_gate_ext.v index 1be4eec74..bae2e4c82 100644 --- a/test_regress/t/t_clk_gate_ext.v +++ b/test_regress/t/t_clk_gate_ext.v @@ -4,28 +4,28 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - reg clk_en = 1'b0; - wire clk_gated = clk & clk_en; - wire [1:0] clks = {1'b0, clk_gated}; + reg clk_en = 1'b0; + wire clk_gated = clk & clk_en; + wire [1:0] clks = {1'b0, clk_gated}; - always @(posedge clks[0]) begin - $display("ERROR: clks[0] should not be active!"); - $stop; - end + always @(posedge clks[0]) begin + $display("ERROR: clks[0] should not be active!"); + $stop; + end - int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_clk_gated_1.v b/test_regress/t/t_clk_gated_1.v index a4bbebcaf..38fca1da6 100644 --- a/test_regress/t/t_clk_gated_1.v +++ b/test_regress/t/t_clk_gated_1.v @@ -18,39 +18,39 @@ // SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - reg gated_clk_en = 1'b0 ; - reg [1:0] pc = 2'b0; - reg [1:0] res = 2'b0; + reg gated_clk_en = 1'b0; + reg [1:0] pc = 2'b0; + reg [1:0] res = 2'b0; - wire gated_clk = gated_clk_en & clk; + wire gated_clk = gated_clk_en & clk; - always @(posedge clk) begin - pc <= pc + 1; - gated_clk_en <= 1'b1; - end + always @(posedge clk) begin + pc <= pc + 1; + gated_clk_en <= 1'b1; + end - always @(posedge gated_clk) begin - res <= pc; - end + always @(posedge gated_clk) begin + res <= pc; + end - always @(posedge clk) begin - if (pc == 2'b11) begin - // Correct behaviour is that res should be lagging pc in the count - // by one cycle - if (res == 2'b10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end + always @(posedge clk) begin + if (pc == 2'b11) begin + // Correct behaviour is that res should be lagging pc in the count + // by one cycle + if (res == 2'b10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + else begin + $stop; + end + end + end endmodule diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v index 1b14bc9b3..d42ee3414 100644 --- a/test_regress/t/t_clk_gater.v +++ b/test_regress/t/t_clk_gater.v @@ -4,157 +4,161 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - reg reset; - reg enable; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; + reg enable; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .reset (reset), - .enable (enable), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[31:0]), + // Inputs + .clk(clk), + .reset(reset), + .enable(enable), + .in(in[31:0]) + ); - wire [63:0] result = {32'h0, out}; + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - reset <= (cyc < 5); - enable <= cyc[4] || (cyc < 2); - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h01e1553da1dcf3af - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + reset <= (cyc < 5); + enable <= cyc[4] || (cyc < 2); + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h01e1553da1dcf3af + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, reset, enable, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + reset, + enable, + in +); - input clk; - input reset; - input enable; - input [31:0] in; - output [31:0] out; + input clk; + input reset; + input enable; + input [31:0] in; + output [31:0] out; - // No gating - reg [31:0] d10; - always @(posedge clk) begin - d10 <= in; - end + // No gating + reg [31:0] d10; + always @(posedge clk) begin + d10 <= in; + end - reg displayit; + reg displayit; `ifdef VERILATOR // Harder test - initial displayit = $c1("0"); // Something that won't optimize away + initial displayit = $c1("0"); // Something that won't optimize away `else - initial displayit = '0; + initial displayit = '0; `endif - // Obvious gating + PLI - reg [31:0] d20; - always @(posedge clk) begin - if (enable) begin - d20 <= d10; // Obvious gating - if (displayit) begin - $display("hello!"); // Must glob with other PLI statements - end + // Obvious gating + PLI + reg [31:0] d20; + always @(posedge clk) begin + if (enable) begin + d20 <= d10; // Obvious gating + if (displayit) begin + $display("hello!"); // Must glob with other PLI statements end - end + end + end - // Reset means second-level gating - reg [31:0] d30, d31a, d31b, d32; - always @(posedge clk) begin - d32 <= d31b; - if (reset) begin - d30 <= 32'h0; - d31a <= 32'h0; - d31b <= 32'h0; - d32 <= 32'h0; // Overlaps above, just to make things interesting + // Reset means second-level gating + reg [31:0] d30, d31a, d31b, d32; + always @(posedge clk) begin + d32 <= d31b; + if (reset) begin + d30 <= 32'h0; + d31a <= 32'h0; + d31b <= 32'h0; + d32 <= 32'h0; // Overlaps above, just to make things interesting + end + else begin + // Mix two outputs + d30 <= d20; + if (enable) begin + d31a <= d30; + d31b <= d31a; + end + end + end + + // Multiple ORs for gater + reg [31:0] d40a, d40b; + always @(posedge clk) begin + if (reset) begin + d40a <= 32'h0; + d40b <= 32'h0; + end + if (enable) begin + d40a <= d32; + d40b <= d40a; + end + end + + // Non-optimizable + reg [31:0] d91, d92; + reg [31:0] inverted; + always @(posedge clk) begin + inverted = ~d40b; + if (reset) begin + d91 <= 32'h0; + end + else begin + if (enable) begin + d91 <= inverted; end else begin - // Mix two outputs - d30 <= d20; - if (enable) begin - d31a <= d30; - d31b <= d31a; - end + d92 <= inverted ^ 32'h12341234; // Inverted gating condition end - end + end + end - // Multiple ORs for gater - reg [31:0] d40a,d40b; - always @(posedge clk) begin - if (reset) begin - d40a <= 32'h0; - d40b <= 32'h0; - end - if (enable) begin - d40a <= d32; - d40b <= d40a; - end - end - - // Non-optimizable - reg [31:0] d91, d92; - reg [31:0] inverted; - always @(posedge clk) begin - inverted = ~d40b; - if (reset) begin - d91 <= 32'h0; - end - else begin - if (enable) begin - d91 <= inverted; - end - else begin - d92 <= inverted ^ 32'h12341234; // Inverted gating condition - end - end - end - - wire [31:0] out = d91 ^ d92; + wire [31:0] out = d91 ^ d92; endmodule diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v index 1e5c4a15d..dbcf5039a 100644 --- a/test_regress/t/t_clk_gen.v +++ b/test_regress/t/t_clk_gen.v @@ -4,83 +4,85 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; - integer cyc; initial cyc=1; + input clk; + integer cyc; + initial cyc = 1; - reg gendlyclk_r; - reg [31:0] gendlydata_r; - reg [31:0] dlydata_gr; + reg gendlyclk_r; + reg [31:0] gendlydata_r; + reg [31:0] dlydata_gr; - reg genblkclk; - reg [31:0] genblkdata; - reg [31:0] blkdata_gr; + reg genblkclk; + reg [31:0] genblkdata; + reg [31:0] blkdata_gr; - wire [31:0] constwire = 32'h11; - reg [31:0] initwire; + wire [31:0] constwire = 32'h11; + reg [31:0] initwire; - integer i; - initial begin - for (i=0; i<10000; i=i+1) begin - initwire = 32'h2200; + integer i; + initial begin + for (i = 0; i < 10000; i = i + 1) begin + initwire = 32'h2200; + end + end + + wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; + wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; + + always @(posedge clk) begin + gendlydata_r <= 32'h0011_0000; + gendlyclk_r <= 0; + // surefire lint_off SEQASS + genblkclk = 0; + genblkdata = 0; + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 2) begin + gendlyclk_r <= 1; + gendlydata_r <= 32'h00540000; + genblkclk = 1; + genblkdata = 32'hace; + $write("[%0t] Send pulse\n", $time); end - end - - wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; - wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; - - always @ (posedge clk) begin - gendlydata_r <= 32'h0011_0000; - gendlyclk_r <= 0; - // surefire lint_off SEQASS - genblkclk = 0; - genblkdata = 0; - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==2) begin - gendlyclk_r <= 1; - gendlydata_r <= 32'h00540000; - genblkclk = 1; - genblkdata = 32'hace; - $write("[%0t] Send pulse\n", $time); - end - if (cyc==3) begin - genblkdata = 32'hdce; - gendlydata_r <= 32'h00ff0000; - if (either != 32'h87542211) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 3) begin + genblkdata = 32'hdce; + gendlydata_r <= 32'h00ff0000; + if (either != 32'h87542211) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - // surefire lint_on SEQASS - end + end + // surefire lint_on SEQASS + end - always @ (posedge gendlyclk_r) begin - if ($time>0) begin // Hack, don't split the block - $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); - dlydata_gr <= 32'h80000000; - // Delayed activity list will already be completed for gendlydata - // because genclk is from a delayed assignment. - // Thus we get the NEW not old value of gendlydata_r - if (gendlydata_r != 32'h00540000) $stop; - if (genblkdata != 32'hace) $stop; - end - end + always @(posedge gendlyclk_r) begin + if ($time > 0) begin // Hack, don't split the block + $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + dlydata_gr <= 32'h80000000; + // Delayed activity list will already be completed for gendlydata + // because genclk is from a delayed assignment. + // Thus we get the NEW not old value of gendlydata_r + if (gendlydata_r != 32'h00540000) $stop; + if (genblkdata != 32'hace) $stop; + end + end - always @ (posedge genblkclk) begin - if ($time>0) begin // Hack, don't split the block - $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); - blkdata_gr <= 32'h07000000; - // Clock from non-delayed assignment, we get old value of gendlydata_r -`ifdef verilator `else // V3.2 races... technically legal - if (gendlydata_r != 32'h00110000) $stop; + always @(posedge genblkclk) begin + if ($time > 0) begin // Hack, don't split the block + $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + blkdata_gr <= 32'h07000000; + // Clock from non-delayed assignment, we get old value of gendlydata_r +`ifdef verilator +`else // V3.2 races... technically legal + if (gendlydata_r != 32'h00110000) $stop; `endif - if (genblkdata != 32'hace) $stop; - end - end + if (genblkdata != 32'hace) $stop; + end + end endmodule diff --git a/test_regress/t/t_clk_inp_init.v b/test_regress/t/t_clk_inp_init.v index aafc767bb..f88651141 100644 --- a/test_regress/t/t_clk_inp_init.v +++ b/test_regress/t/t_clk_inp_init.v @@ -10,73 +10,82 @@ // bug1327 // This models some device under test with an asynchronous reset pin // which counts to 15. -module dut (input wire clk, - input wire rst_n, - output wire done); +module dut ( + input wire clk, + input wire rst_n, + output wire done +); - reg [3:0] counter; + reg [3:0] counter; - always @(posedge clk or negedge rst_n) begin - if (rst_n & ! clk) begin - $display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", - $time, clk, rst_n); - $stop; - end + always @(posedge clk or negedge rst_n) begin + if (rst_n & !clk) begin + $display( + "[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", + $time, clk, rst_n); + $stop; + end - if (! rst_n) begin - counter <= 4'd0; - end else begin - counter <= counter < 4'd15 ? counter + 4'd1 : counter; - end - end + if (!rst_n) begin + counter <= 4'd0; + end + else begin + counter <= counter < 4'd15 ? counter + 4'd1 : counter; + end + end - assign done = rst_n & (counter == 4'd15); + assign done = rst_n & (counter == 4'd15); endmodule -module t(input wire clk, - input wire rst_n); +module t ( + input wire clk, + input wire rst_n +); - wire dut_done; + wire dut_done; - // A small FSM for driving the test - // - // This is just designed to be enough to force Verilator to make a - // "VinpClk" variant of dut_rst_n. + // A small FSM for driving the test + // + // This is just designed to be enough to force Verilator to make a + // "VinpClk" variant of dut_rst_n. - // Possible states: - // - // 0: Device in reset - // 1: Device running - // 2: Device finished - reg [1:0] state; - always @(posedge clk or negedge rst_n) begin - if (! rst_n) begin - state <= 0; - end else begin - if (state == 2'd0) begin - // One clock after resetting the device, we switch to running - // it. - state <= 2'd1; - end - else if (state == 2'd1) begin - // If the device is running, we switch to finished when its - // done signal goes high. - state <= dut_done ? 2'd2 : 2'd1; - end - else begin - // If the dut has finished, the test is done. - $write("*-* All Finished *-*\n"); - $finish; - end + // Possible states: + // + // 0: Device in reset + // 1: Device running + // 2: Device finished + reg [1:0] state; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= 0; + end + else begin + if (state == 2'd0) begin + // One clock after resetting the device, we switch to running + // it. + state <= 2'd1; end - end + else if (state == 2'd1) begin + // If the device is running, we switch to finished when its + // done signal goes high. + state <= dut_done ? 2'd2 : 2'd1; + end + else begin + // If the dut has finished, the test is done. + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - wire dut_rst_n = rst_n & (state != 0); + wire dut_rst_n = rst_n & (state != 0); - wire done; - dut dut_i (.clk (clk), - .rst_n (dut_rst_n), - .done (dut_done)); + wire done; + dut dut_i ( + .clk(clk), + .rst_n(dut_rst_n), + .done(dut_done) + ); endmodule diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v index 28cd61119..a9800b26c 100644 --- a/test_regress/t/t_clk_latch.v +++ b/test_regress/t/t_clk_latch.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - fastclk, clk - ); + // Inputs + fastclk, clk + ); -`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge +`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge `define posstyle posedge `define negstyle negedge `else @@ -17,95 +17,95 @@ module t (/*AUTOARG*/ `define negstyle `endif - input fastclk; - input clk; + input fastclk; + input clk; - reg [7:0] data; - reg [7:0] data_a; - reg [7:0] data_a_a; - reg [7:0] data_a_b; - reg [7:0] data_b; - reg [7:0] data_b_a; - reg [7:0] data_b_b; + reg [7:0] data; + reg [7:0] data_a; + reg [7:0] data_a_a; + reg [7:0] data_a_b; + reg [7:0] data_b; + reg [7:0] data_b_a; + reg [7:0] data_b_b; - reg [8*6-1:0] check [100:0]; - wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b}; - initial begin - check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; - check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; - check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; - check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; - check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; - check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; - check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; - check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; - check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; - check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; - check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; - check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; - check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; - check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; - check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; - check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; - check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; - check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; - check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; - end + reg [8*6-1:0] check [100:0]; + wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b}; + initial begin + check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; + check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; + check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; + check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; + end - // verilator lint_off COMBDLY - // verilator lint_off LATCH - always @ (`posstyle clk /*AS*/ or data) begin - if (clk) begin - data_a <= data + 8'd1; - end - end + // verilator lint_off COMBDLY + // verilator lint_off LATCH + always @ (`posstyle clk /*AS*/ or data) begin + if (clk) begin + data_a <= data + 8'd1; + end + end - always @ (`posstyle clk /*AS*/ or data_a) begin - if (clk) begin - data_a_a <= data_a + 8'd1; - end - end + always @ (`posstyle clk /*AS*/ or data_a) begin + if (clk) begin + data_a_a <= data_a + 8'd1; + end + end - always @ (`posstyle clk /*AS*/ or data_b) begin - if (clk) begin - data_b_a <= data_b + 8'd1; - end - end + always @ (`posstyle clk /*AS*/ or data_b) begin + if (clk) begin + data_b_a <= data_b + 8'd1; + end + end - always @ (`negstyle clk /*AS*/ or data or data_a) begin - if (~clk) begin - data_b <= data + 8'd1; - data_a_b <= data_a + 8'd1; - data_b_b <= data_b + 8'd1; - end - end + always @ (`negstyle clk /*AS*/ or data or data_a) begin + if (~clk) begin + data_b <= data + 8'd1; + data_a_b <= data_a + 8'd1; + data_b_b <= data_b + 8'd1; + end + end - integer cyc; initial cyc = 0; + integer cyc; initial cyc = 0; - always @ (posedge fastclk) begin - cyc <= cyc+1; + always @ (posedge fastclk) begin + cyc <= cyc+1; `ifdef TEST_VERBOSE - $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); + $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); `endif - if (cyc>=19 && cyc<36) begin - if (compare !== check[cyc]) begin - $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); - $stop; - end + if (cyc>=19 && cyc<36) begin + if (compare !== check[cyc]) begin + $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); + $stop; end - if (cyc == 10) begin - data <= 8'd12; - end - if (cyc == 20) begin - data <= 8'd20; - end - if (cyc == 30) begin - data <= 8'd30; - end - if (cyc == 40) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + if (cyc == 10) begin + data <= 8'd12; + end + if (cyc == 20) begin + data <= 8'd20; + end + if (cyc == 30) begin + data <= 8'd30; + end + if (cyc == 40) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_clk_latchgate.v b/test_regress/t/t_clk_latchgate.v index 484083a8c..1523fd77e 100644 --- a/test_regress/t/t_clk_latchgate.v +++ b/test_regress/t/t_clk_latchgate.v @@ -21,160 +21,170 @@ // A side effect of the problem is this warning, disabled by default // Test Bench -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; + integer cyc = 0; + reg [63:0] crc; - // Take CRC data and apply to testblock inputs - wire [7:0] dvld = crc[7:0]; - wire [7:0] ff_en_e1 = crc[15:8]; + // Take CRC data and apply to testblock inputs + wire [7:0] dvld = crc[7:0]; + wire [7:0] ff_en_e1 = crc[15:8]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] entry_vld; // From test of Test.v - wire [7:0] ff_en_vld; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] entry_vld; // From test of Test.v + wire [7:0] ff_en_vld; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .ff_en_vld (ff_en_vld[7:0]), - .entry_vld (entry_vld[7:0]), - // Inputs - .clk (clk), - .dvld (dvld[7:0]), - .ff_en_e1 (ff_en_e1[7:0])); + Test test ( /*AUTOINST*/ + // Outputs + .ff_en_vld(ff_en_vld[7:0]), + .entry_vld(entry_vld[7:0]), + // Inputs + .clk(clk), + .dvld(dvld[7:0]), + .ff_en_e1(ff_en_e1[7:0]) + ); - reg err_code; - reg ffq_clk_active; - reg [7:0] prv_dvld; + reg err_code; + reg ffq_clk_active; + reg [7:0] prv_dvld; - initial begin - err_code = 0; - ffq_clk_active = 0; - end - always @ (posedge clk) begin - prv_dvld = test.dvld; - end - always @ (negedge test.ff_entry_dvld_0.clk) begin - ffq_clk_active = 1; - if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; - end + initial begin + err_code = 0; + ffq_clk_active = 0; + end + always @(posedge clk) begin + prv_dvld = test.dvld; + end + always @(negedge test.ff_entry_dvld_0.clk) begin + ffq_clk_active = 1; + if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; + end - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc); - $display(" en=%b fen=%b d=%b ev=%b", - test.flop_en_vld[0], test.ff_en_vld[0], - test.dvld[0], test.entry_vld[0]); + $write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc); + $display(" en=%b fen=%b d=%b ev=%b", test.flop_en_vld[0], test.ff_en_vld[0], test.dvld[0], + test.entry_vld[0]); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc<3) begin - crc <= 64'h5aef0c8d_d70a4497; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc < 3) begin + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + if (ffq_clk_active == 0) begin + $display("----"); + $display("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); + $display("----"); + $stop; end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); - if (ffq_clk_active == 0) begin - $display ("----"); - $display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); - $display ("----"); - $stop; - end - else if (err_code) begin - $display ("----"); - $display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs"); - $display ("----"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end + else if (err_code) begin + $display("----"); + $display("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs"); + $display("----"); + $stop; end - end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module llq (clk, d, q); - parameter WIDTH = 32; - input clk; - input [WIDTH-1:0] d; - output [WIDTH-1:0] q; +module llq ( + clk, + d, + q +); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; - reg [WIDTH-1:0] qr; + reg [WIDTH-1:0] qr; - /* verilator lint_off COMBDLY */ - /* verilator lint_off LATCH */ + /* verilator lint_off COMBDLY */ + /* verilator lint_off LATCH */ - always @(clk or d) - if (clk == 1'b0) - qr <= d; + always @(clk or d) if (clk == 1'b0) qr <= d; - /* verilator lint_on LATCH */ - /* verilator lint_on COMBDLY */ + /* verilator lint_on LATCH */ + /* verilator lint_on COMBDLY */ - assign q = qr; + assign q = qr; endmodule -module ffq (clk, d, q); - parameter WIDTH = 32; - input clk; - input [WIDTH-1:0] d; - output [WIDTH-1:0] q; +module ffq ( + clk, + d, + q +); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; - reg [WIDTH-1:0] qr; + reg [WIDTH-1:0] qr; - always @(posedge clk) - qr <= d; + always @(posedge clk) qr <= d; - assign q = qr; + assign q = qr; endmodule // DUT module -module Test (/*AUTOARG*/ - // Outputs - ff_en_vld, entry_vld, - // Inputs - clk, dvld, ff_en_e1 - ); - input clk; +module Test ( /*AUTOARG*/ + // Outputs + ff_en_vld, + entry_vld, + // Inputs + clk, + dvld, + ff_en_e1 +); + input clk; - input [7:0] dvld; - input [7:0] ff_en_e1; + input [7:0] dvld; + input [7:0] ff_en_e1; - output [7:0] ff_en_vld; - output wire [7:0] entry_vld; + output [7:0] ff_en_vld; + output wire [7:0] entry_vld; - wire [7:0] gclk_vld; - wire [7:0] ff_en_vld; - reg [7:0] flop_en_vld; + wire [7:0] gclk_vld; + wire [7:0] ff_en_vld; + reg [7:0] flop_en_vld; - always @(posedge clk) flop_en_vld <= ff_en_e1; + always @(posedge clk) flop_en_vld <= ff_en_e1; - // clock gating + // clock gating `ifdef GATED_CLK_TESTCASE - assign gclk_vld = {8{clk}} & ff_en_vld; + assign gclk_vld = {8{clk}} & ff_en_vld; `else - assign gclk_vld = {8{clk}}; + assign gclk_vld = {8{clk}}; `endif - // latch for avoiding glitch on the clock gating control - llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); + // verilog_format: off + // latch for avoiding glitch on the clock gating control + llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); - // flops that use the gated clock signal - ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); - ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); - ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); - ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); - ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); - ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); - ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); - ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); + // flops that use the gated clock signal + ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); + ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); + ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); + ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); + ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); + ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); + ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); + ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); + // verilog_format: on endmodule diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v index 64e8f6f64..4dca010ad 100644 --- a/test_regress/t/t_clk_powerdn.v +++ b/test_regress/t/t_clk_powerdn.v @@ -4,118 +4,120 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - reg reset_l; + reg reset_l; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + // End of automatics - reg clkgate_e2r; - reg clkgate_e1r_l; - always @(posedge clk or negedge reset_l) begin - if (!reset_l) begin - clkgate_e1r_l <= ~1'b1; - end - else begin - clkgate_e1r_l <= ~clkgate_e2r; - end - end + reg clkgate_e2r; + reg clkgate_e1r_l; + always @(posedge clk or negedge reset_l) begin + if (!reset_l) begin + clkgate_e1r_l <= ~1'b1; + end + else begin + clkgate_e1r_l <= ~clkgate_e2r; + end + end - reg clkgate_e1f; - always @(negedge clk) begin - // Yes, it's really a = - clkgate_e1f = ~clkgate_e1r_l | ~reset_l; - end + reg clkgate_e1f; + always @(negedge clk) begin + // Yes, it's really a = + clkgate_e1f = ~clkgate_e1r_l | ~reset_l; + end - wire clkgated = clk & clkgate_e1f; + wire clkgated = clk & clkgate_e1f; - reg [31:0] countgated; - always @(posedge clkgated or negedge reset_l) begin - if (!reset_l) begin - countgated <= 32'h1000; - end - else begin - countgated <= countgated + 32'd1; - end - end + reg [31:0] countgated; + always @(posedge clkgated or negedge reset_l) begin + if (!reset_l) begin + countgated <= 32'h1000; + end + else begin + countgated <= countgated + 32'd1; + end + end - reg [31:0] count; - always @(posedge clk or negedge reset_l) begin - if (!reset_l) begin - count <= 32'h1000; - end - else begin - count <= count + 32'd1; - end - end + reg [31:0] count; + always @(posedge clk or negedge reset_l) begin + if (!reset_l) begin + count <= 32'h1000; + end + else begin + count <= count + 32'd1; + end + end - reg [7:0] cyc; initial cyc = 0; - always @ (posedge clk) begin + reg [7:0] cyc; + initial cyc = 0; + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n", $time,reset_l,cyc,clkgate_e1f,count,countgated); + $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n", $time, reset_l, cyc, clkgate_e1f, count, + countgated); `endif - cyc <= cyc + 8'd1; - case (cyc) - 8'd00: begin - reset_l <= ~1'b0; - clkgate_e2r <= 1'b1; - end - 8'd01: begin - reset_l <= ~1'b0; - end - 8'd02: begin - end - 8'd03: begin - reset_l <= ~1'b1; // Need a posedge - end - 8'd04: begin - end - 8'd05: begin - reset_l <= ~1'b0; - end - 8'd09: begin - clkgate_e2r <= 1'b0; - end - 8'd11: begin - clkgate_e2r <= 1'b1; - end - 8'd20: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; - endcase - case (cyc) - 8'd00: ; - 8'd01: ; - 8'd02: ; - 8'd03: ; - 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; - 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; - 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; - 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; - 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; - 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; - 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; - 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; - 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; - 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; - 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; - 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; - 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; - 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; - default: $stop; - endcase - end + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + reset_l <= ~1'b0; + clkgate_e2r <= 1'b1; + end + 8'd01: begin + reset_l <= ~1'b0; + end + 8'd02: begin + end + 8'd03: begin + reset_l <= ~1'b1; // Need a posedge + end + 8'd04: begin + end + 8'd05: begin + reset_l <= ~1'b0; + end + 8'd09: begin + clkgate_e2r <= 1'b0; + end + 8'd11: begin + clkgate_e2r <= 1'b1; + end + 8'd20: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: if (count != 32'h00001000 || countgated != 32'h00001000) $stop; + 8'd05: if (count != 32'h00001000 || countgated != 32'h00001000) $stop; + 8'd06: if (count != 32'h00001000 || countgated != 32'h00001000) $stop; + 8'd07: if (count != 32'h00001001 || countgated != 32'h00001001) $stop; + 8'd08: if (count != 32'h00001002 || countgated != 32'h00001002) $stop; + 8'd09: if (count != 32'h00001003 || countgated != 32'h00001003) $stop; + 8'd10: if (count != 32'h00001004 || countgated != 32'h00001004) $stop; + 8'd11: if (count != 32'h00001005 || countgated != 32'h00001005) $stop; + 8'd12: if (count != 32'h00001006 || countgated != 32'h00001005) $stop; + 8'd13: if (count != 32'h00001007 || countgated != 32'h00001005) $stop; + 8'd14: if (count != 32'h00001008 || countgated != 32'h00001006) $stop; + 8'd15: if (count != 32'h00001009 || countgated != 32'h00001007) $stop; + 8'd16: if (count != 32'h0000100a || countgated != 32'h00001008) $stop; + 8'd17: if (count != 32'h0000100b || countgated != 32'h00001009) $stop; + 8'd18: if (count != 32'h0000100c || countgated != 32'h0000100a) $stop; + 8'd19: if (count != 32'h0000100d || countgated != 32'h0000100b) $stop; + 8'd20: if (count != 32'h0000100e || countgated != 32'h0000100c) $stop; + default: $stop; + endcase + end endmodule diff --git a/test_regress/t/t_clk_scope_bad.v b/test_regress/t/t_clk_scope_bad.v index f0fe53a15..e60e917db 100644 --- a/test_regress/t/t_clk_scope_bad.v +++ b/test_regress/t/t_clk_scope_bad.v @@ -4,35 +4,38 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module t ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - input clk; - input [2:0] in; - output [2:0] out; + input clk; + input [2:0] in; + output [2:0] out; - logic [2:0] r_in; - always_ff @ (posedge clk) r_in <= in; + logic [2:0] r_in; + always_ff @(posedge clk) r_in <= in; - flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); - flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); - flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); + // verilog_format: off + flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); + flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); + flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); + // verilog_format: on endmodule -module flop - ( - input d, - input clk, - output logic q); +module flop ( + input d, + input clk, + output logic q +); - // verilator no_inline_module + // verilator no_inline_module - always_ff @ (posedge clk) begin - q <= d; - end + always_ff @(posedge clk) begin + q <= d; + end endmodule diff --git a/test_regress/t/t_clk_vecgen1.v b/test_regress/t/t_clk_vecgen1.v index 0f8948d12..62a037de8 100644 --- a/test_regress/t/t_clk_vecgen1.v +++ b/test_regress/t/t_clk_vecgen1.v @@ -4,121 +4,117 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [1:0] clkvec = crc[1:0]; + wire [1:0] clkvec = crc[1:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] count; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] count; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .count (count[1:0]), - // Inputs - .clkvec (clkvec[1:0])); + Test test ( /*AUTOINST*/ + // Outputs + .count(count[1:0]), + // Inputs + .clkvec(clkvec[1:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {62'h0, count}; + // Aggregate outputs into a single result vector + wire [63:0] result = {62'h0, count}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'hfe8bac0bb1a0e53b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule `ifdef T_TEST1 -module Test - ( - input wire [1:0] clkvec, - // verilator lint_off MULTIDRIVEN - output reg [1:0] count - // verilator lint_on MULTIDRIVEN - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - initial count[igen] = 1'b0; - always @ (posedge clkvec[igen]) - count[igen] <= count[igen] + 1; - end - endgenerate - always @ (count) begin - $write("hi\n"); - end +module Test ( + input wire [1:0] clkvec, + // verilator lint_off MULTIDRIVEN + output reg [1:0] count + // verilator lint_on MULTIDRIVEN +); + genvar igen; + generate + for (igen = 0; igen < 2; igen = igen + 1) begin : code_gen + initial count[igen] = 1'b0; + always @(posedge clkvec[igen]) count[igen] <= count[igen] + 1; + end + endgenerate + always @(count) begin + $write("hi\n"); + end endmodule `endif `ifdef T_TEST2 -module Test - ( - input wire [1:0] clkvec, - // verilator lint_off MULTIDRIVEN - output reg [1:0] count - // verilator lint_on MULTIDRIVEN - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - // Unsupported: Count is multidriven, though if we did better analysis it wouldn't - // need to be. - initial count[igen] = 1'b0; - always @ (posedge clk_tmp) - count[igen] <= count[igen] + 1; - end - endgenerate +module Test ( + input wire [1:0] clkvec, + // verilator lint_off MULTIDRIVEN + output reg [1:0] count + // verilator lint_on MULTIDRIVEN +); + genvar igen; + generate + for (igen = 0; igen < 2; igen = igen + 1) begin : code_gen + wire clk_tmp = clkvec[igen]; + // Unsupported: Count is multidriven, though if we did better analysis it wouldn't + // need to be. + initial count[igen] = 1'b0; + always @(posedge clk_tmp) count[igen] <= count[igen] + 1; + end + endgenerate endmodule `endif `ifdef T_TEST3 -module Test - ( - input wire [1:0] clkvec, - output wire [1:0] count - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - reg tmp_count = 1'b0; - always @ (posedge clk_tmp) begin - tmp_count <= tmp_count + 1; - end - assign count[igen] = tmp_count; +module Test ( + input wire [1:0] clkvec, + output wire [1:0] count +); + genvar igen; + generate + for (igen = 0; igen < 2; igen = igen + 1) begin : code_gen + wire clk_tmp = clkvec[igen]; + reg tmp_count = 1'b0; + always @(posedge clk_tmp) begin + tmp_count <= tmp_count + 1; end - endgenerate + assign count[igen] = tmp_count; + end + endgenerate endmodule `endif diff --git a/test_regress/t/t_clocking_bad1.out b/test_regress/t/t_clocking_bad1.out index 84617682a..a5c4e0ff9 100644 --- a/test_regress/t/t_clocking_bad1.out +++ b/test_regress/t/t_clocking_bad1.out @@ -1,6 +1,6 @@ -%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12) +%Error: t/t_clocking_bad1.v:14:11: Only one default clocking block allowed per module (IEEE 1800-2023 14.12) : ... note: In instance 't' - 16 | default clocking @(posedge clk); - | ^~~~~~~~ + 14 | default clocking @(posedge clk); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_clocking_bad1.v b/test_regress/t/t_clocking_bad1.v index deed6ce53..4aba9e146 100644 --- a/test_regress/t/t_clocking_bad1.v +++ b/test_regress/t/t_clocking_bad1.v @@ -4,15 +4,13 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - default clocking @(posedge clk); - endclocking + default clocking @(posedge clk); + endclocking - default clocking @(posedge clk); - endclocking + default clocking @(posedge clk); + endclocking endmodule diff --git a/test_regress/t/t_clocking_bad2.out b/test_regress/t/t_clocking_bad2.out index 80ca14402..984d8fe5a 100644 --- a/test_regress/t/t_clocking_bad2.out +++ b/test_regress/t/t_clocking_bad2.out @@ -1,11 +1,11 @@ -%Error: t/t_clocking_bad2.v:16:23: Multiple default input skews not allowed - 16 | default input #2 output #2; - | ^ +%Error: t/t_clocking_bad2.v:14:20: Multiple default input skews not allowed + 14 | default input #2 output #2; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_clocking_bad2.v:16:33: Multiple default output skews not allowed - 16 | default input #2 output #2; - | ^ -%Error: t/t_clocking_bad2.v:18:8: Multiple clockvars with the same name not allowed - 18 | output out; - | ^~~~~~ +%Error: t/t_clocking_bad2.v:14:30: Multiple default output skews not allowed + 14 | default input #2 output #2; + | ^ +%Error: t/t_clocking_bad2.v:16:5: Multiple clockvars with the same name not allowed + 16 | output out; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_clocking_bad2.v b/test_regress/t/t_clocking_bad2.v index a9386b0e6..bd4b54803 100644 --- a/test_regress/t/t_clocking_bad2.v +++ b/test_regress/t/t_clocking_bad2.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic in, out; - clocking cb @(posedge clk); - default input #1 output #1step; // Now allowed - default input #2 output #2; - output #1step out; // Now allowed - output out; - endclocking + logic in, out; + clocking cb @(posedge clk); + default input #1 output #1step; // Now allowed + default input #2 output #2; + output #1step out; // Now allowed + output out; + endclocking endmodule diff --git a/test_regress/t/t_clocking_bad3.out b/test_regress/t/t_clocking_bad3.out index 16302e365..5e4605ad5 100644 --- a/test_regress/t/t_clocking_bad3.out +++ b/test_regress/t/t_clocking_bad3.out @@ -1,14 +1,14 @@ -%Error: t/t_clocking_bad3.v:14:14: Corresponding variable 'in' does not exist - 14 | input in; - | ^~ +%Error: t/t_clocking_bad3.v:12:11: Corresponding variable 'in' does not exist + 12 | input in; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_clocking_bad3.v:15:15: Corresponding variable 'out' does not exist - 15 | output out; - | ^~~ -%Error: t/t_clocking_bad3.v:18:13: Duplicate declaration of CLOCKING 'cb': 'cb' - 18 | clocking cb @(posedge clk); - | ^~ - t/t_clocking_bad3.v:13:13: ... Location of original declaration - 13 | clocking cb @(posedge clk); - | ^~ +%Error: t/t_clocking_bad3.v:13:12: Corresponding variable 'out' does not exist + 13 | output out; + | ^~~ +%Error: t/t_clocking_bad3.v:16:12: Duplicate declaration of CLOCKING 'cb': 'cb' + 16 | clocking cb @(posedge clk); + | ^~ + t/t_clocking_bad3.v:11:12: ... Location of original declaration + 11 | clocking cb @(posedge clk); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_clocking_bad3.v b/test_regress/t/t_clocking_bad3.v index a529a9f4c..99f9c60f8 100644 --- a/test_regress/t/t_clocking_bad3.v +++ b/test_regress/t/t_clocking_bad3.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - clocking cb @(posedge clk); - input in; - output out; - endclocking + clocking cb @(posedge clk); + input in; + output out; + endclocking - clocking cb @(posedge clk); - endclocking + clocking cb @(posedge clk); + endclocking endmodule diff --git a/test_regress/t/t_clocking_bad4.out b/test_regress/t/t_clocking_bad4.out index 9db9f5d70..8107fc352 100644 --- a/test_regress/t/t_clocking_bad4.out +++ b/test_regress/t/t_clocking_bad4.out @@ -1,46 +1,46 @@ -%Error: t/t_clocking_bad4.v:23:15: Skew must be constant (IEEE 1800-2023 14.4) +%Error: t/t_clocking_bad4.v:21:12: Skew must be constant (IEEE 1800-2023 14.4) : ... note: In instance 't' - 23 | input #cyc in; - | ^~~ + 21 | input #cyc in; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_clocking_bad4.v:24:16: Skew cannot be negative +%Error: t/t_clocking_bad4.v:22:13: Skew cannot be negative : ... note: In instance 't' - 24 | input #(-1) out; - | ^ -%Error: t/t_clocking_bad4.v:31:11: Usage of cycle delays requires default clocking (IEEE 1800-2023 14.11) + 22 | input #(-1) out; + | ^ +%Error: t/t_clocking_bad4.v:29:10: Usage of cycle delays requires default clocking (IEEE 1800-2023 14.11) : ... note: In instance 't' - 31 | always ##1; - | ^~ -%Error: t/t_clocking_bad4.v:32:15: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) + 29 | always ##1; + | ^~ +%Error: t/t_clocking_bad4.v:30:14: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' - 32 | always cb1.out = clk; - | ^~~ -%Error: t/t_clocking_bad4.v:33:15: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) + 30 | always cb1.out = clk; + | ^~~ +%Error: t/t_clocking_bad4.v:31:14: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' - 33 | assign cb1.out = clk; - | ^~~ -%Error: t/t_clocking_bad4.v:34:21: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) + 31 | assign cb1.out = clk; + | ^~~ +%Error: t/t_clocking_bad4.v:32:20: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' - 34 | always write(cb1.out); - | ^~~ -%Error: t/t_clocking_bad4.v:35:22: Event controls cannot be used in synchronous drives (IEEE 1800-2023 14.16) + 32 | always write(cb1.out); + | ^~~ +%Error: t/t_clocking_bad4.v:33:21: Event controls cannot be used in synchronous drives (IEEE 1800-2023 14.16) : ... note: In instance 't' - 35 | always cb1.out <= @(posedge clk) 1; - | ^ -%Error: t/t_clocking_bad4.v:36:22: Only cycle delays can be used in synchronous drives (IEEE 1800-2023 14.16) + 33 | always cb1.out <= @(posedge clk) 1; + | ^ +%Error: t/t_clocking_bad4.v:34:21: Only cycle delays can be used in synchronous drives (IEEE 1800-2023 14.16) : ... note: In instance 't' - 36 | always cb1.out <= #1 1; - | ^ -%Error: t/t_clocking_bad4.v:37:18: Cycle delays not allowed as intra-assignment delays (IEEE 1800-2023 14.11) + 34 | always cb1.out <= #1 1; + | ^ +%Error: t/t_clocking_bad4.v:35:17: Cycle delays not allowed as intra-assignment delays (IEEE 1800-2023 14.11) : ... note: In instance 't' - 37 | always out <= ##1 1; - | ^~ -%Error: t/t_clocking_bad4.v:40:12: Cannot write to input clockvar (IEEE 1800-2023 14.3) + 35 | always out <= ##1 1; + | ^~ +%Error: t/t_clocking_bad4.v:38:9: Cannot write to input clockvar (IEEE 1800-2023 14.3) + : ... note: In instance 't' + 38 | cb1.in = 1; + | ^~ +%Error: t/t_clocking_bad4.v:39:18: Cannot read from output clockvar (IEEE 1800-2023 14.3) : ... note: In instance 't' - 40 | cb1.in = 1; - | ^~ -%Error: t/t_clocking_bad4.v:41:21: Cannot read from output clockvar (IEEE 1800-2023 14.3) - : ... note: In instance 't' - 41 | $display(cb1.out); - | ^~~ + 39 | $display(cb1.out); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_clocking_bad4.v b/test_regress/t/t_clocking_bad4.v index 00a35ea6c..cb959628d 100644 --- a/test_regress/t/t_clocking_bad4.v +++ b/test_regress/t/t_clocking_bad4.v @@ -4,40 +4,38 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic in, out; - clocking cb1 @(posedge clk); - input in; - output out; - endclocking + logic in, out; + clocking cb1 @(posedge clk); + input in; + output out; + endclocking - int cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - clocking cb2 @(negedge clk); - input #cyc in; - input #(-1) out; - endclocking + clocking cb2 @(negedge clk); + input #cyc in; + input #(-1) out; + endclocking - task write(output x); - x = 1; - endtask + task write(output x); + x = 1; + endtask - always ##1; - always cb1.out = clk; - assign cb1.out = clk; - always write(cb1.out); - always cb1.out <= @(posedge clk) 1; - always cb1.out <= #1 1; - always out <= ##1 1; + always ##1; + always cb1.out = clk; + assign cb1.out = clk; + always write(cb1.out); + always cb1.out <= @(posedge clk) 1; + always cb1.out <= #1 1; + always out <= ##1 1; - always @(posedge clk) begin - cb1.in = 1; - $display(cb1.out); - end + always @(posedge clk) begin + cb1.in = 1; + $display(cb1.out); + end endmodule diff --git a/test_regress/t/t_clocking_bad5.out b/test_regress/t/t_clocking_bad5.out index 7fd7b5bd9..1188c6794 100644 --- a/test_regress/t/t_clocking_bad5.out +++ b/test_regress/t/t_clocking_bad5.out @@ -1,23 +1,23 @@ -%Error: t/t_clocking_bad5.v:29:20: Duplicate declaration of CLOCKING 'ck': '$global_clock' - 29 | global clocking ogck @(posedge clk); endclocking - | ^~~~ - t/t_clocking_bad5.v:26:20: ... Location of original declaration - 26 | global clocking ck @(posedge clk); endclocking - | ^~ +%Error: t/t_clocking_bad5.v:27:19: Duplicate declaration of CLOCKING 'ck': '$global_clock' + 27 | global clocking ogck @(posedge clk); + | ^~~~ + t/t_clocking_bad5.v:23:19: ... Location of original declaration + 23 | global clocking ck @(posedge clk); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_clocking_bad5.v:32:20: Duplicate declaration of CLOCKING 'ogck': '$global_clock' - 32 | global clocking ck @(posedge clk); endclocking - | ^~ - t/t_clocking_bad5.v:29:20: ... Location of original declaration - 29 | global clocking ogck @(posedge clk); endclocking - | ^~~~ -%Error: t/t_clocking_bad5.v:32:20: Duplicate declaration of CLOCKING 'ck': 'ck' - 32 | global clocking ck @(posedge clk); endclocking - | ^~ - t/t_clocking_bad5.v:26:20: ... Location of original declaration - 26 | global clocking ck @(posedge clk); endclocking - | ^~ -%Error: t/t_clocking_bad5.v:16:14: Can't find definition of variable: '$global_clock' - 16 | always @ ($global_clock) $display; - | ^~~~~~~~~~~~~ +%Error: t/t_clocking_bad5.v:31:19: Duplicate declaration of CLOCKING 'ogck': '$global_clock' + 31 | global clocking ck @(posedge clk); + | ^~ + t/t_clocking_bad5.v:27:19: ... Location of original declaration + 27 | global clocking ogck @(posedge clk); + | ^~~~ +%Error: t/t_clocking_bad5.v:31:19: Duplicate declaration of CLOCKING 'ck': 'ck' + 31 | global clocking ck @(posedge clk); + | ^~ + t/t_clocking_bad5.v:23:19: ... Location of original declaration + 23 | global clocking ck @(posedge clk); + | ^~ +%Error: t/t_clocking_bad5.v:15:12: Can't find definition of variable: '$global_clock' + 15 | always @($global_clock) $display; + | ^~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_clocking_bad5.v b/test_regress/t/t_clocking_bad5.v index 7af05b672..1b5576b1f 100644 --- a/test_regress/t/t_clocking_bad5.v +++ b/test_regress/t/t_clocking_bad5.v @@ -4,31 +4,31 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + // Inputs + input clk +); - sub sub(.*); + sub sub (.*); - // Bad - no global clock - always @ ($global_clock) $display; + // Bad - no global clock + always @($global_clock) $display; endmodule -module sub(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module sub ( + input clk +); - global clocking ck @(posedge clk); endclocking + global clocking ck @(posedge clk); + endclocking - // Bad - global duplicate - global clocking ogck @(posedge clk); endclocking + // Bad - global duplicate + global clocking ogck @(posedge clk); + endclocking - // Bad - name duplicate - global clocking ck @(posedge clk); endclocking + // Bad - name duplicate + global clocking ck @(posedge clk); + endclocking endmodule diff --git a/test_regress/t/t_clocking_concat.v b/test_regress/t/t_clocking_concat.v index 17e1bfe70..da64a40c5 100644 --- a/test_regress/t/t_clocking_concat.v +++ b/test_regress/t/t_clocking_concat.v @@ -4,34 +4,32 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic[3:0] D1, D2, Q1, Q2; - always @(posedge clk) begin - {Q1, Q2} <= {D1, D2}; - end + logic [3:0] D1, D2, Q1, Q2; + always @(posedge clk) begin + {Q1, Q2} <= {D1, D2}; + end - always @(posedge clk) $display("[%0t] posedge clk", $time); + always @(posedge clk) $display("[%0t] posedge clk", $time); - clocking cb @(posedge clk); - input #0 Q = {Q1, Q2}; - output #0 D = {D1, D2}; - endclocking + clocking cb @(posedge clk); + input #0 Q = {Q1, Q2}; + output #0 D = {D1, D2}; + endclocking - initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, {D1,D2}, {Q1,Q2}, cb.Q); + initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, {D1, D2}, {Q1, Q2}, cb.Q); - int cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc > 1 && cb.Q != {D1 - 4'd1, D2 - 4'd1}) $stop; - cb.D <= {D1 + 4'd1, D2 + 4'd1}; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc > 1 && cb.Q != {D1 - 4'd1, D2 - 4'd1}) $stop; + cb.D <= {D1 + 4'd1, D2 + 4'd1}; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_clocking_empty_block.v b/test_regress/t/t_clocking_empty_block.v index 3bacba39b..b84715ead 100644 --- a/test_regress/t/t_clocking_empty_block.v +++ b/test_regress/t/t_clocking_empty_block.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic clk = 0; - logic x; - logic y; - always #1ns clk = ~clk; - clocking cb @(posedge clk); - output #1ns x; - input #1step y; - endclocking - initial begin - repeat(10) @(posedge clk); - $display("*-* All Finished *-*"); - $finish(); - end + logic clk = 0; + logic x; + logic y; + always #1ns clk = ~clk; + clocking cb @(posedge clk); + output #1ns x; + input #1step y; + endclocking + initial begin + repeat (10) @(posedge clk); + $display("*-* All Finished *-*"); + $finish(); + end endmodule diff --git a/test_regress/t/t_clocking_inout.v b/test_regress/t/t_clocking_inout.v index cf93fd18d..ac6e6bfa9 100644 --- a/test_regress/t/t_clocking_inout.v +++ b/test_regress/t/t_clocking_inout.v @@ -5,40 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit clk = 0, foo = 0, bar = 0; + bit clk = 0, foo = 0, bar = 0; - always #5 clk = ~clk; + always #5 clk = ~clk; - clocking cb @(posedge clk); - input #11 output #2 foo; - inout bar; - endclocking + clocking cb @(posedge clk); + input #11 output #2 foo; + inout bar; + endclocking - initial begin - cb.foo <= 1; - cb.bar <= 1; - if (foo != 0 || cb.foo != 0) $stop; - if (bar != 0 || cb.bar != 0) $stop; + initial begin + cb.foo <= 1; + cb.bar <= 1; + if (foo != 0 || cb.foo != 0) $stop; + if (bar != 0 || cb.bar != 0) $stop; - @(posedge bar) - if ($time != 5) $stop; - if (foo != 0 || cb.foo != 0) $stop; - if (cb.bar != 0) $stop; + @(posedge bar) if ($time != 5) $stop; + if (foo != 0 || cb.foo != 0) $stop; + if (cb.bar != 0) $stop; - #1 - if (foo != 0 || cb.foo != 0) $stop; - if (cb.bar == 1) $stop; + #1 if (foo != 0 || cb.foo != 0) $stop; + if (cb.bar == 1) $stop; - @(posedge foo) - if ($time != 7) $stop; - if (cb.foo != 0) $stop; + @(posedge foo) if ($time != 7) $stop; + if (cb.foo != 0) $stop; - #9 // $time == 16 - if (cb.foo != 0) $stop; + #9 // $time == 16 + if (cb.foo != 0) + $stop; - #10 // $time == 26 - if (cb.foo != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + #10 // $time == 26 + if (cb.foo != 1) + $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clocking_react.v b/test_regress/t/t_clocking_react.v index fed57a5a2..e920bc624 100644 --- a/test_regress/t/t_clocking_react.v +++ b/test_regress/t/t_clocking_react.v @@ -5,38 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 interface axi_if; - logic clk; - wire rlast; - wire rvalid; - clocking cb @(posedge clk); - inout rlast, rvalid; - endclocking + logic clk; + wire rlast; + wire rvalid; + clocking cb @(posedge clk); + inout rlast, rvalid; + endclocking endinterface module t; - axi_if axi_vi(); - initial begin - axi_vi.clk = 1'b0; - #1 axi_vi.clk = 1'b1; // triggers line 26 - #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen) - #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen) - end - initial begin - @(negedge axi_vi.rvalid); - $display("[%0t] rvalid==%b", $time, axi_vi.rvalid); - $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1); - if (axi_vi.rlast === 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - initial begin - $display("[%0t] rvalid <= 1", $time); - axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13) - @(posedge axi_vi.rvalid); - $display("[%0t] rvalid <= 0", $time); - axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first - @(negedge axi_vi.clk); - $display("[%0t] rlast <= 1", $time); - axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen - end + axi_if axi_vi (); + initial begin + axi_vi.clk = 1'b0; + #1 axi_vi.clk = 1'b1; // triggers line 26 + #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen) + #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen) + end + initial begin + @(negedge axi_vi.rvalid); + $display("[%0t] rvalid==%b", $time, axi_vi.rvalid); + $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1); + if (axi_vi.rlast === 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + initial begin + $display("[%0t] rvalid <= 1", $time); + axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13) + @(posedge axi_vi.rvalid); + $display("[%0t] rvalid <= 0", $time); + axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first + @(negedge axi_vi.clk); + $display("[%0t] rlast <= 1", $time); + axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen + end endmodule diff --git a/test_regress/t/t_clocking_timing.v b/test_regress/t/t_clocking_timing.v index b8188242f..1ff03f122 100644 --- a/test_regress/t/t_clocking_timing.v +++ b/test_regress/t/t_clocking_timing.v @@ -4,12 +4,12 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -`timescale 10ns/1ns +`timescale 10ns / 1ns `ifdef TEST_VERBOSE - `define WRITE_VERBOSE(args) $write args +`define WRITE_VERBOSE(args) $write args `else - `define WRITE_VERBOSE(args) +`define WRITE_VERBOSE(args) `endif `ifndef TEST_WIDTH @@ -33,59 +33,58 @@ `endif module t; - typedef logic[`TEST_BITS-1:0] sig_t; - sig_t D, Q; - always @(posedge clk) Q <= D; + typedef logic [`TEST_BITS-1:0] sig_t; + sig_t D, Q; + always @(posedge clk) Q <= D; - logic clk = 0; - always #(`TEST_CLK_PERIOD/2) clk = ~clk; + logic clk = 0; + always #(`TEST_CLK_PERIOD / 2) clk = ~clk; - always @(posedge clk) `WRITE_VERBOSE(("[%0t] posedge clk\n", $time)); + always @(posedge clk) `WRITE_VERBOSE(("[%0t] posedge clk\n", $time)); - default clocking cb @(posedge clk); - default input #`TEST_INPUT_SKEW output #`TEST_OUTPUT_SKEW; - input Q; - output D; - endclocking + default clocking cb @(posedge clk); + default input #`TEST_INPUT_SKEW output #`TEST_OUTPUT_SKEW; + input Q; + output D; + endclocking `ifdef TEST_VERBOSE - initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, D, Q, cb.Q); + initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, D, Q, cb.Q); `endif - always - begin - sig_t val; - val = '0; - cb.D <= val; - for (int i = 0; i < 5; i++) begin ##(`TEST_CYCLE_DELAY+`TEST_OUTPUT_SKEW/`TEST_CLK_PERIOD+1) - val = {`TEST_WIDTH{(`TEST_BITS/`TEST_WIDTH)'('ha + i)}}; - `WRITE_VERBOSE(("[%0t] cb.D <= ##%0d %x\n", $time, `TEST_CYCLE_DELAY, val)); - cb.D <= ##(`TEST_CYCLE_DELAY) val; - fork - #(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW-0.1) begin - if (D == val) begin - `WRITE_VERBOSE(("[%0t] D == %x == %x\n", $time, D, val)); - $stop; - end - if (cb.Q != D) begin - `WRITE_VERBOSE(("[%0t] cb.Q == %x != %x\n", $time, cb.Q, D)); - $stop; - end - end - #(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW+0.1) begin - if (D != val) begin - `WRITE_VERBOSE(("[%0t] D == %x != %x\n", $time, D, val)); - $stop; - end - if (cb.Q == D) begin - `WRITE_VERBOSE(("[%0t] cb.Q == %x == %x\n", $time, cb.Q, D)); - $stop; - end - end - join_none - end - ##4 - $write("*-* All Finished *-*\n"); - $finish; - end + always begin + sig_t val; + val = '0; + cb.D <= val; + for (int i = 0; i < 5; i++) begin + ##(`TEST_CYCLE_DELAY + `TEST_OUTPUT_SKEW / `TEST_CLK_PERIOD + 1) + val = {`TEST_WIDTH{(`TEST_BITS / `TEST_WIDTH)'('ha + i)}}; + `WRITE_VERBOSE(("[%0t] cb.D <= ##%0d %x\n", $time, `TEST_CYCLE_DELAY, val)); + cb.D <= ##(`TEST_CYCLE_DELAY) val; + fork + #(`TEST_CYCLE_DELAY * `TEST_CLK_PERIOD + `TEST_OUTPUT_SKEW - 0.1) begin + if (D == val) begin + `WRITE_VERBOSE(("[%0t] D == %x == %x\n", $time, D, val)); + $stop; + end + if (cb.Q != D) begin + `WRITE_VERBOSE(("[%0t] cb.Q == %x != %x\n", $time, cb.Q, D)); + $stop; + end + end + #(`TEST_CYCLE_DELAY * `TEST_CLK_PERIOD + `TEST_OUTPUT_SKEW + 0.1) begin + if (D != val) begin + `WRITE_VERBOSE(("[%0t] D == %x != %x\n", $time, D, val)); + $stop; + end + if (cb.Q == D) begin + `WRITE_VERBOSE(("[%0t] cb.Q == %x == %x\n", $time, cb.Q, D)); + $stop; + end + end + join_none + end + ##4 $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_clocking_unsup1.out b/test_regress/t/t_clocking_unsup1.out index 9904a7a65..8f94706a0 100644 --- a/test_regress/t/t_clocking_unsup1.out +++ b/test_regress/t/t_clocking_unsup1.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_clocking_unsup1.v:14:15: Unsupported: clocking event edge override - 14 | output posedge #1 a; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_clocking_unsup1.v:12:12: Unsupported: clocking event edge override + 12 | output posedge #1 a; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_clocking_unsup1.v:15:15: Unsupported: clocking event edge override - 15 | output negedge #1 b; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_clocking_unsup1.v:16:15: Unsupported: clocking event edge override - 16 | output edge #1 b; - | ^~~~ +%Error-UNSUPPORTED: t/t_clocking_unsup1.v:13:12: Unsupported: clocking event edge override + 13 | output negedge #1 b; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_clocking_unsup1.v:14:12: Unsupported: clocking event edge override + 14 | output edge #1 b; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_clocking_unsup1.v b/test_regress/t/t_clocking_unsup1.v index 16a14a248..83334e1a9 100644 --- a/test_regress/t/t_clocking_unsup1.v +++ b/test_regress/t/t_clocking_unsup1.v @@ -4,16 +4,14 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - clocking cb @(posedge clk); - output posedge #1 a; - output negedge #1 b; - output edge #1 b; - endclocking + clocking cb @(posedge clk); + output posedge #1 a; + output negedge #1 b; + output edge #1 b; + endclocking endmodule diff --git a/test_regress/t/t_clocking_unsup2.out b/test_regress/t/t_clocking_unsup2.out index 9d4b7df46..acefbfd3b 100644 --- a/test_regress/t/t_clocking_unsup2.out +++ b/test_regress/t/t_clocking_unsup2.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_clocking_unsup2.v:16:11: Unsupported: ##0 delays +%Error-UNSUPPORTED: t/t_clocking_unsup2.v:14:10: Unsupported: ##0 delays : ... note: In instance 't' - 16 | always ##0; - | ^~ + 14 | always ##0; + | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_clocking_unsup2.v b/test_regress/t/t_clocking_unsup2.v index 4fec1b610..0bf19a5d6 100644 --- a/test_regress/t/t_clocking_unsup2.v +++ b/test_regress/t/t_clocking_unsup2.v @@ -4,14 +4,12 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - default clocking @(posedge clk); - endclocking + default clocking @(posedge clk); + endclocking - always ##0; + always ##0; endmodule diff --git a/test_regress/t/t_clocking_virtual.v b/test_regress/t/t_clocking_virtual.v index 206b0495b..35204493f 100644 --- a/test_regress/t/t_clocking_virtual.v +++ b/test_regress/t/t_clocking_virtual.v @@ -5,55 +5,50 @@ // SPDX-License-Identifier: CC0-1.0 interface Iface; - logic clk = 1'b0, inp = 1'b0, io = 1'b0, out = 1'b0, out2 = 1'b0; - clocking cb @(posedge clk); - input #7 inp; - output out; - inout io; - endclocking - always @(posedge clk) inp <= 1'b1; - always #5 clk <= ~clk; - assign out2 = out; + logic clk = 1'b0, inp = 1'b0, io = 1'b0, out = 1'b0, out2 = 1'b0; + clocking cb @(posedge clk); + input #7 inp; + output out; + inout io; + endclocking + always @(posedge clk) inp <= 1'b1; + always #5 clk <= ~clk; + assign out2 = out; endinterface module main; - initial begin - #6; - t.mod1.cb.io <= 1'b1; - t.mod1.cb.out <= 1'b1; - if (t.mod0.io != 1'b0) $stop; - if (t.mod1.cb.io != 1'b0) $stop; - if (t.mod1.cb.inp != 1'b0) $stop; - @(posedge t.mod0.io) - if ($time != 15) $stop; - if (t.mod0.io != 1'b1) $stop; - if (t.mod1.cb.io != 1'b0) $stop; - #1 - if (t.mod0.cb.io != 1'b0) $stop; - if (t.mod1.cb.io != 1'b0) $stop; - if (t.mod1.cb.inp != 1'b1) $stop; - #8; - t.mod0.inp = 1'b0; - if (t.mod0.cb.inp != 1'b1) $stop; - @(t.mod1.cb) - if ($time != 25) $stop; - if (t.mod0.cb.inp != 1'b1) $stop; - t.mod0.inp = 1'b0; - @(t.mod0.cb) - if ($time != 35) $stop; - if (t.mod0.cb.inp != 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - initial begin - @(posedge t.mod0.out) - if ($time != 15) $stop; - if (t.mod1.out2 != 1'b1) $stop; - end + initial begin + #6; + t.mod1.cb.io <= 1'b1; + t.mod1.cb.out <= 1'b1; + if (t.mod0.io != 1'b0) $stop; + if (t.mod1.cb.io != 1'b0) $stop; + if (t.mod1.cb.inp != 1'b0) $stop; + @(posedge t.mod0.io) if ($time != 15) $stop; + if (t.mod0.io != 1'b1) $stop; + if (t.mod1.cb.io != 1'b0) $stop; + #1 if (t.mod0.cb.io != 1'b0) $stop; + if (t.mod1.cb.io != 1'b0) $stop; + if (t.mod1.cb.inp != 1'b1) $stop; + #8; + t.mod0.inp = 1'b0; + if (t.mod0.cb.inp != 1'b1) $stop; + @(t.mod1.cb) if ($time != 25) $stop; + if (t.mod0.cb.inp != 1'b1) $stop; + t.mod0.inp = 1'b0; + @(t.mod0.cb) if ($time != 35) $stop; + if (t.mod0.cb.inp != 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + initial begin + @(posedge t.mod0.out) if ($time != 15) $stop; + if (t.mod1.out2 != 1'b1) $stop; + end endmodule module t; - main main1(); - Iface mod0(); - virtual Iface mod1 = mod0; + main main1 (); + Iface mod0 (); + virtual Iface mod1 = mod0; endmodule diff --git a/test_regress/t/t_clocking_xref.v b/test_regress/t/t_clocking_xref.v index ca70d7a5c..47627bb8c 100644 --- a/test_regress/t/t_clocking_xref.v +++ b/test_regress/t/t_clocking_xref.v @@ -5,42 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 module mod; - bit clk = 1'b0; - bit inp = 1'b0; - clocking cb @(posedge clk); - input #3 inp; - endclocking - always @(posedge clk) inp <= 1'b1; - always #1 clk = ~clk; + bit clk = 1'b0; + bit inp = 1'b0; + clocking cb @(posedge clk); + input #3 inp; + endclocking + always @(posedge clk) inp <= 1'b1; + always #1 clk = ~clk; endmodule module main; - bit clk = 1'b0; - bit inp = 1'b0; - always begin - #2 - if (t.mod1.cb.inp != 1'b0) $stop; - if (t.main1.cbb.inp != 1'b0) $stop; - if (t.main2.cbb.inp != 1'b0) $stop; - #4; - if (t.mod1.cb.inp != 1'b1) $stop; - if (t.main1.cbb.inp != 1'b1) $stop; - if (t.main2.cbb.inp != 1'b1) $stop; - end - clocking cbb @(posedge clk); - input #3 inp; - endclocking - always @(posedge clk) inp <= 1'b1; - always #1 clk = ~clk; + bit clk = 1'b0; + bit inp = 1'b0; + always begin + #2 if (t.mod1.cb.inp != 1'b0) $stop; + if (t.main1.cbb.inp != 1'b0) $stop; + if (t.main2.cbb.inp != 1'b0) $stop; + #4; + if (t.mod1.cb.inp != 1'b1) $stop; + if (t.main1.cbb.inp != 1'b1) $stop; + if (t.main2.cbb.inp != 1'b1) $stop; + end + clocking cbb @(posedge clk); + input #3 inp; + endclocking + always @(posedge clk) inp <= 1'b1; + always #1 clk = ~clk; endmodule module t; - main main1(); - mod mod1(); - main main2(); - initial begin - #7; - $write("*-* All Finished *-*\n"); - $finish; - end + main main1 (); + mod mod1 (); + main main2 (); + initial begin + #7; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint.v b/test_regress/t/t_constraint.v index d0240ece0..8cc1583ac 100644 --- a/test_regress/t/t_constraint.v +++ b/test_regress/t/t_constraint.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int one; + rand int one; - constraint a { one > 0 && one < 2; } + constraint a {one > 0 && one < 2;} - constraint empty { } + constraint empty {} endclass module t; - Packet p; + Packet p; - int v; + int v; - initial begin - p = new; - v = p.randomize(); - if (v != 1) $stop; - if (p.one != 1) $stop; + initial begin + p = new; + v = p.randomize(); + if (v != 1) $stop; + if (p.one != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_assoc_arr_bad.out b/test_regress/t/t_constraint_assoc_arr_bad.out index 78f52a9f1..726ac3ed7 100644 --- a/test_regress/t/t_constraint_assoc_arr_bad.out +++ b/test_regress/t/t_constraint_assoc_arr_bad.out @@ -1,16 +1,16 @@ -%Warning-CONSTRAINTIGN: t/t_constraint_assoc_arr_bad.v:12:20: Unsupported: Constrained randomization of associative array keys of 144bits, limit is 128 bits - 12 | string_arr["a_very_long_string"] == 65; - | ^~~~~~~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_assoc_arr_bad.v:11:28: Unsupported: Constrained randomization of associative array keys of 144bits, limit is 128 bits + 11 | constraint c {string_arr["a_very_long_string"] == 65;} + | ^~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Error: t/t_constraint_assoc_arr_bad.v:30:26: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) - 30 | constraint c1 { data[cl] > 0;} - | ^~ +%Error: t/t_constraint_assoc_arr_bad.v:28:23: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) + 28 | constraint c1 {data[cl] > 0;} + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_constraint_assoc_arr_bad.v:44:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) - 44 | constraint c2 { foreach (data[i]) data[i] < 100; } - | ^ -%Error: t/t_constraint_assoc_arr_bad.v:58:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) - 58 | constraint c3 { foreach (data[i]) data[i] > 0; } - | ^ +%Error: t/t_constraint_assoc_arr_bad.v:43:28: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) + 43 | foreach (data[i]) data[i] < 100; + | ^ +%Error: t/t_constraint_assoc_arr_bad.v:58:41: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) + 58 | constraint c3 {foreach (data[i]) data[i] > 0;} + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_constraint_assoc_arr_bad.v b/test_regress/t/t_constraint_assoc_arr_bad.v index 05893bf2a..1a83ae5cf 100644 --- a/test_regress/t/t_constraint_assoc_arr_bad.v +++ b/test_regress/t/t_constraint_assoc_arr_bad.v @@ -6,88 +6,88 @@ // Long String index associative array class AssocArrayString; - rand int string_arr [string]; + rand int string_arr[string]; - constraint c { - string_arr["a_very_long_string"] == 65; - } - function new(); - string_arr["a_very_long_string"] = 0; - endfunction + constraint c {string_arr["a_very_long_string"] == 65;} + function new(); + string_arr["a_very_long_string"] = 0; + endfunction endclass class keyClass; - int id; - function new(); - id = 3; - endfunction + int id; + function new(); + id = 3; + endfunction endclass // Class index associative array class AssocArrayClass; - rand bit [31:0] data [keyClass]; - keyClass cl; - // constraint c4 { foreach (data[i]) data[i] > 0;} Unsupported index type for an associative array in an iterative constraint. - constraint c1 { data[cl] > 0;} // Illegal index expression of unpacked type in constraint. - function new(); - cl = new(); - data[cl] = 32'd77; - endfunction + rand bit [31:0] data[keyClass]; + keyClass cl; + // constraint c4 { foreach (data[i]) data[i] > 0;} Unsupported index type for an associative array in an iterative constraint. + constraint c1 {data[cl] > 0;} // Illegal index expression of unpacked type in constraint. + function new(); + cl = new(); + data[cl] = 32'd77; + endfunction endclass typedef struct { - int a; - int b; + int a; + int b; } UnpackedIndexType; // Struct (unpacked) index associative array class AssocArrayUnpackedStruct; - rand bit [31:0] data [UnpackedIndexType]; - constraint c2 { foreach (data[i]) data[i] < 100; } // Illegal non-integral expression in random constraint. + rand bit [31:0] data[UnpackedIndexType]; + constraint c2 { + foreach (data[i]) data[i] < 100; + } // Illegal non-integral expression in random constraint. - function new(); - UnpackedIndexType idx; - idx.a = 1; - idx.b = 2; - data[idx] = 32'd25; - endfunction + function new(); + UnpackedIndexType idx; + idx.a = 1; + idx.b = 2; + data[idx] = 32'd25; + endfunction endclass // Array (unpacked) index associative array typedef logic [2:0] IndexArrayType[3]; class AssocArrayArrayIndex; - rand bit [31:0] data [IndexArrayType]; - constraint c3 { foreach (data[i]) data[i] > 0; } + rand bit [31:0] data[IndexArrayType]; + constraint c3 {foreach (data[i]) data[i] > 0;} - function new(); - IndexArrayType idx; - for (int j = 0; j < 4; j++) begin - idx[j] = 3'd0; - end - data[idx] = 32'd75; - endfunction + function new(); + IndexArrayType idx; + for (int j = 0; j < 4; j++) begin + idx[j] = 3'd0; + end + data[idx] = 32'd75; + endfunction endclass module t_constraint_assoc_arr_bad; - AssocArrayString test_str; - AssocArrayClass test_cls; - AssocArrayUnpackedStruct test_unp_struct; - AssocArrayArrayIndex test_unp_arr; - int success = 0; + AssocArrayString test_str; + AssocArrayClass test_cls; + AssocArrayUnpackedStruct test_unp_struct; + AssocArrayArrayIndex test_unp_arr; + int success = 0; - initial begin - test_str = new(); - test_cls = new(); - test_unp_struct = new(); - test_unp_arr = new(); + initial begin + test_str = new(); + test_cls = new(); + test_unp_struct = new(); + test_unp_arr = new(); - success += test_str.randomize(); - success += test_cls.randomize(); - success += test_unp_struct.randomize(); - success += test_unp_arr.randomize(); + success += test_str.randomize(); + success += test_cls.randomize(); + success += test_unp_struct.randomize(); + success += test_unp_arr.randomize(); - if(success != 4) $stop; + if (success != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_assoc_arr_basic.v b/test_regress/t/t_constraint_assoc_arr_basic.v index 02799421c..db4600e2e 100644 --- a/test_regress/t/t_constraint_assoc_arr_basic.v +++ b/test_regress/t/t_constraint_assoc_arr_basic.v @@ -6,211 +6,214 @@ class constrained_associative_array_basic; - rand int int_index_arr [int]; - rand int string_index_arr [string]; - rand int string_index_arr_2 [string]; - /* verilator lint_off SIDEEFFECT */ - // Constraints for both arrays - constraint int_index_constraints { - foreach (int_index_arr[i]) int_index_arr[i] inside {10, 20, 30, 40, 50}; - } - constraint string_index_constraints { - string_index_arr["Alice"] == 35; - string_index_arr["Bob"] inside {50, 60}; - string_index_arr["Charlie"] > 25; - } - constraint string_index_2_constraints { - foreach (string_index_arr_2[i]) string_index_arr_2[i] > 10; // nodep->bitp() would be VARREF, instead of CVTPACKSTRING - } + rand int int_index_arr[int]; + rand int string_index_arr[string]; + rand int string_index_arr_2[string]; + /* verilator lint_off SIDEEFFECT */ + // Constraints for both arrays + constraint int_index_constraints { + foreach (int_index_arr[i]) + int_index_arr[i] inside {10, 20, 30, 40, 50}; + } + constraint string_index_constraints { + string_index_arr["Alice"] == 35; + string_index_arr["Bob"] inside {50, 60}; + string_index_arr["Charlie"] > 25; + } + constraint string_index_2_constraints { + foreach (string_index_arr_2[i]) + string_index_arr_2[i] > 10; // nodep->bitp() would be VARREF, instead of CVTPACKSTRING + } - // Constructor to initialize arrays - function new(); - int_index_arr = '{1: 0, 8: 0, 7: 0}; - string_index_arr = '{"Alice": 25, "Bob": 50, "Charlie": 45}; - string_index_arr_2 = '{"key1": 15, "key2": 20, "key3": 30}; - endfunction + // Constructor to initialize arrays + function new(); + int_index_arr = '{1: 0, 8: 0, 7: 0}; + string_index_arr = '{"Alice": 25, "Bob": 50, "Charlie": 45}; + string_index_arr_2 = '{"key1": 15, "key2": 20, "key3": 30}; + endfunction - // Function to check and display the arrays - function void self_check(); - foreach (int_index_arr[i]) begin - if (!(int_index_arr[i] inside {10, 20, 30, 40, 50})) $stop; - end - foreach (string_index_arr[name]) begin - if ((name == "Alice" && string_index_arr[name] != 35) || + // Function to check and display the arrays + function void self_check(); + foreach (int_index_arr[i]) begin + if (!(int_index_arr[i] inside {10, 20, 30, 40, 50})) $stop; + end + foreach (string_index_arr[name]) begin + if ((name == "Alice" && string_index_arr[name] != 35) || (name == "Bob" && !(string_index_arr[name] inside {50, 60})) || - (name == "Charlie" && string_index_arr[name] <= 25)) $stop; - end - foreach (string_index_arr_2[i]) begin - if (string_index_arr_2[i] <= 10) $stop; - end - endfunction + (name == "Charlie" && string_index_arr[name] <= 25)) + $stop; + end + foreach (string_index_arr_2[i]) begin + if (string_index_arr_2[i] <= 10) $stop; + end + endfunction endclass class constrained_1d_associative_array; - rand int string_index_arr [string]; - rand int int_index_arr [int]; - rand int shortint_index_arr [shortint]; - rand int longint_index_arr[longint]; - rand int byte_index_arr [byte]; - rand int bit_index_arr [bit[5:0]]; - rand int logic_index_arr [logic[3:0]]; - rand int bit_index_arr_1 [bit[55:0]]; + rand int string_index_arr[string]; + rand int int_index_arr[int]; + rand int shortint_index_arr[shortint]; + rand int longint_index_arr[longint]; + rand int byte_index_arr[byte]; + rand int bit_index_arr[bit [5:0]]; + rand int logic_index_arr[logic [3:0]]; + rand int bit_index_arr_1[bit [55:0]]; - // Constraints - constraint associative_array_constraints { - string_index_arr["key1"] == 100; - string_index_arr["key2"] inside {200, 300, 400}; - int_index_arr[40000] + int_index_arr[2000000000] == 2; - shortint_index_arr[2000] == 200; - longint_index_arr[64'd4000000000] == 300; - byte_index_arr[8'd255] == 50; - bit_index_arr[6'd30] - bit_index_arr_1[56'd66] == 3; - logic_index_arr[4'b0011] == 70; - } + // Constraints + constraint associative_array_constraints { + string_index_arr["key1"] == 100; + string_index_arr["key2"] inside {200, 300, 400}; + int_index_arr[40000] + int_index_arr[2000000000] == 2; + shortint_index_arr[2000] == 200; + longint_index_arr[64'd4000000000] == 300; + byte_index_arr[8'd255] == 50; + bit_index_arr[6'd30] - bit_index_arr_1[56'd66] == 3; + logic_index_arr[4'b0011] == 70; + } - function new(); - string_index_arr = '{"key1":0, "key2":0}; - int_index_arr = '{40000:0, 2000000000:0}; - shortint_index_arr = '{2000:0}; - longint_index_arr = '{64'd4000000000:0}; - byte_index_arr = '{8'd255:0}; - bit_index_arr = '{6'd30:0}; - bit_index_arr_1 = '{56'd66:0}; - logic_index_arr = '{4'd3:0}; - endfunction + function new(); + string_index_arr = '{"key1": 0, "key2": 0}; + int_index_arr = '{40000: 0, 2000000000: 0}; + shortint_index_arr = '{2000: 0}; + longint_index_arr = '{64'd4000000000: 0}; + byte_index_arr = '{8'd255: 0}; + bit_index_arr = '{6'd30: 0}; + bit_index_arr_1 = '{56'd66: 0}; + logic_index_arr = '{4'd3: 0}; + endfunction - function void self_check(); - if (string_index_arr["key1"] != 100) $stop; - if (!(string_index_arr["key2"] inside {200, 300, 400})) $stop; - if ((int_index_arr[40000] + int_index_arr[2000000000]) != 2) $stop; - if (shortint_index_arr[2000] != 200) $stop; - if (longint_index_arr[64'd4000000000] != 300) $stop; - if (byte_index_arr[8'd255] != 50) $stop; - if (bit_index_arr[6'd30] - bit_index_arr_1[56'd66] != 3) $stop; - if (logic_index_arr[4'd3] != 70) $stop; - endfunction + function void self_check(); + if (string_index_arr["key1"] != 100) $stop; + if (!(string_index_arr["key2"] inside {200, 300, 400})) $stop; + if ((int_index_arr[40000] + int_index_arr[2000000000]) != 2) $stop; + if (shortint_index_arr[2000] != 200) $stop; + if (longint_index_arr[64'd4000000000] != 300) $stop; + if (byte_index_arr[8'd255] != 50) $stop; + if (bit_index_arr[6'd30] - bit_index_arr_1[56'd66] != 3) $stop; + if (logic_index_arr[4'd3] != 70) $stop; + endfunction - function void debug_display(); - $display("string_index_arr[\"key1\"] = %0d", string_index_arr["key1"]); - $display("string_index_arr[\"key2\"] = %0d", string_index_arr["key2"]); - $display("int_index_arr[40000] = %0d", int_index_arr[40000]); - $display("int_index_arr[2000000000] = %0d", int_index_arr[2000000000]); - $display("shortint_index_arr[2000] = %0d", shortint_index_arr[2000]); - $display("longint_index_arr[4000000000] = %0d", longint_index_arr[64'd4000000000]); - $display("byte_index_arr[255] = %0d", byte_index_arr[8'd255]); - $display("bit_index_arr[30] = %0d", bit_index_arr[6'd30]); - $display("bit_index_arr_1[66] = %0d", bit_index_arr_1[56'd66]); - $display("logic_index_arr[3] = %0d", logic_index_arr[4'd3]); - endfunction + function void debug_display(); + $display("string_index_arr[\"key1\"] = %0d", string_index_arr["key1"]); + $display("string_index_arr[\"key2\"] = %0d", string_index_arr["key2"]); + $display("int_index_arr[40000] = %0d", int_index_arr[40000]); + $display("int_index_arr[2000000000] = %0d", int_index_arr[2000000000]); + $display("shortint_index_arr[2000] = %0d", shortint_index_arr[2000]); + $display("longint_index_arr[4000000000] = %0d", longint_index_arr[64'd4000000000]); + $display("byte_index_arr[255] = %0d", byte_index_arr[8'd255]); + $display("bit_index_arr[30] = %0d", bit_index_arr[6'd30]); + $display("bit_index_arr_1[66] = %0d", bit_index_arr_1[56'd66]); + $display("logic_index_arr[3] = %0d", logic_index_arr[4'd3]); + endfunction endclass class constrained_2d_associative_array; - rand int string_int_index_arr [string][int]; - rand int int_bit_index_arr [int][bit[5:0]]; - rand int string_bit_index_arr [string][bit[7:0]]; - rand int unpacked_assoc_array_2d [string][2]; + rand int string_int_index_arr[string][int]; + rand int int_bit_index_arr[int][bit [5:0]]; + rand int string_bit_index_arr[string][bit [7:0]]; + rand int unpacked_assoc_array_2d[string][2]; - // Constraints - constraint associative_array_constraints { - string_int_index_arr["key1"][2000] == 100; - string_int_index_arr["key2"][3000] inside {200, 300, 400}; - int_bit_index_arr[40000][6'd30] == 60; - int_bit_index_arr[50000][6'd40] inside {100, 200}; - string_bit_index_arr["key3"][8'd100] == 150; - string_bit_index_arr["key4"][8'd200] inside {250, 350}; - unpacked_assoc_array_2d["key5"][0] == 7; - } + // Constraints + constraint associative_array_constraints { + string_int_index_arr["key1"][2000] == 100; + string_int_index_arr["key2"][3000] inside {200, 300, 400}; + int_bit_index_arr[40000][6'd30] == 60; + int_bit_index_arr[50000][6'd40] inside {100, 200}; + string_bit_index_arr["key3"][8'd100] == 150; + string_bit_index_arr["key4"][8'd200] inside {250, 350}; + unpacked_assoc_array_2d["key5"][0] == 7; + } - function new(); - string_int_index_arr = '{"key1":'{2000:0}, "key2":'{3000:0}}; - int_bit_index_arr = '{40000:'{6'd30:0}, 50000:'{6'd40:0}}; - string_bit_index_arr = '{"key3":'{8'd100:0}, "key4":'{8'd200:0}}; - unpacked_assoc_array_2d["key5"][0] = 0; - unpacked_assoc_array_2d["key5"][1] = 0; - endfunction + function new(); + string_int_index_arr = '{"key1": '{2000: 0}, "key2": '{3000: 0}}; + int_bit_index_arr = '{40000: '{6'd30: 0}, 50000: '{6'd40: 0}}; + string_bit_index_arr = '{"key3": '{8'd100: 0}, "key4": '{8'd200: 0}}; + unpacked_assoc_array_2d["key5"][0] = 0; + unpacked_assoc_array_2d["key5"][1] = 0; + endfunction - function void self_check(); - if (string_int_index_arr["key1"][2000] != 100) $stop; - if (!(string_int_index_arr["key2"][3000] inside {200, 300, 400})) $stop; - if (int_bit_index_arr[40000][6'd30] != 60) $stop; - if (!(int_bit_index_arr[50000][6'd40] inside {100, 200})) $stop; - if (string_bit_index_arr["key3"][8'd100] != 150) $stop; - if (!(string_bit_index_arr["key4"][8'd200] inside {250, 350})) $stop; - if (unpacked_assoc_array_2d["key5"][0] != 7) $stop; - endfunction + function void self_check(); + if (string_int_index_arr["key1"][2000] != 100) $stop; + if (!(string_int_index_arr["key2"][3000] inside {200, 300, 400})) $stop; + if (int_bit_index_arr[40000][6'd30] != 60) $stop; + if (!(int_bit_index_arr[50000][6'd40] inside {100, 200})) $stop; + if (string_bit_index_arr["key3"][8'd100] != 150) $stop; + if (!(string_bit_index_arr["key4"][8'd200] inside {250, 350})) $stop; + if (unpacked_assoc_array_2d["key5"][0] != 7) $stop; + endfunction - function void debug_display(); - $display("string_int_index_arr[\"key1\"][2000] = %0d", string_int_index_arr["key1"][2000]); - $display("string_int_index_arr[\"key2\"][3000] = %0d", string_int_index_arr["key2"][3000]); - $display("int_bit_index_arr[40000][30] = %0d", int_bit_index_arr[40000][6'd30]); - $display("int_bit_index_arr[50000][40] = %0d", int_bit_index_arr[50000][6'd40]); - $display("string_bit_index_arr[\"key3\"][100] = %0d", string_bit_index_arr["key3"][8'd100]); - $display("string_bit_index_arr[\"key4\"][200] = %0d", string_bit_index_arr["key4"][8'd200]); - $display("unpacked_assoc_array_2d[\"key5\"][0] = %0d", unpacked_assoc_array_2d["key5"][0]); - endfunction - /* verilator lint_off SIDEEFFECT */ + function void debug_display(); + $display("string_int_index_arr[\"key1\"][2000] = %0d", string_int_index_arr["key1"][2000]); + $display("string_int_index_arr[\"key2\"][3000] = %0d", string_int_index_arr["key2"][3000]); + $display("int_bit_index_arr[40000][30] = %0d", int_bit_index_arr[40000][6'd30]); + $display("int_bit_index_arr[50000][40] = %0d", int_bit_index_arr[50000][6'd40]); + $display("string_bit_index_arr[\"key3\"][100] = %0d", string_bit_index_arr["key3"][8'd100]); + $display("string_bit_index_arr[\"key4\"][200] = %0d", string_bit_index_arr["key4"][8'd200]); + $display("unpacked_assoc_array_2d[\"key5\"][0] = %0d", unpacked_assoc_array_2d["key5"][0]); + endfunction + /* verilator lint_off SIDEEFFECT */ endclass class AssocArray64bitMoreTest; - rand int bit_index_arr [bit[78:0]]; - rand int logic_index_arr [logic[64:0]]; + rand int bit_index_arr[bit [78:0]]; + rand int logic_index_arr[logic [64:0]]; - constraint c { - bit_index_arr[79'd66] == 65; - logic_index_arr[65'd3] == 70; - } - function new(); - bit_index_arr = '{79'd66:0}; - logic_index_arr = '{65'd3:0}; - endfunction - function void self_check(); - if (bit_index_arr[79'd66] != 65) $stop; - if (logic_index_arr[65'd3] != 70) $stop; - endfunction + constraint c { + bit_index_arr[79'd66] == 65; + logic_index_arr[65'd3] == 70; + } + function new(); + bit_index_arr = '{79'd66: 0}; + logic_index_arr = '{65'd3: 0}; + endfunction + function void self_check(); + if (bit_index_arr[79'd66] != 65) $stop; + if (logic_index_arr[65'd3] != 70) $stop; + endfunction endclass module t_constraint_assoc_arr_basic; - constrained_associative_array_basic my_array; - constrained_1d_associative_array my_1d_array; - constrained_2d_associative_array my_2d_array; + constrained_associative_array_basic my_array; + constrained_1d_associative_array my_1d_array; + constrained_2d_associative_array my_2d_array; - AssocArray64bitMoreTest test_obj; - int success; + AssocArray64bitMoreTest test_obj; + int success; - initial begin - my_array = new(); - success = my_array.randomize(); - if (success == 0) $stop; - my_array.self_check(); + initial begin + my_array = new(); + success = my_array.randomize(); + if (success == 0) $stop; + my_array.self_check(); - my_1d_array = new(); - success = my_1d_array.randomize(); - if (success == 0) $stop; - my_1d_array.self_check(); + my_1d_array = new(); + success = my_1d_array.randomize(); + if (success == 0) $stop; + my_1d_array.self_check(); - my_2d_array = new(); - success = my_2d_array.randomize(); - if (success == 0) $stop; - my_2d_array.self_check(); + my_2d_array = new(); + success = my_2d_array.randomize(); + if (success == 0) $stop; + my_2d_array.self_check(); - test_obj = new(); - repeat(2) begin - success = test_obj.randomize(); - if (success != 1) $stop; - end - - // my_1d_array.debug_display(); - // my_2d_array.debug_display(); - - $write("*-* All Finished *-*\n"); - $finish; + test_obj = new(); + repeat (2) begin + success = test_obj.randomize(); + if (success != 1) $stop; end + // my_1d_array.debug_display(); + // my_2d_array.debug_display(); + + $write("*-* All Finished *-*\n"); + $finish; + end + endmodule diff --git a/test_regress/t/t_constraint_assoc_arr_others.v b/test_regress/t/t_constraint_assoc_arr_others.v index 3cae0007c..716c876d0 100644 --- a/test_regress/t/t_constraint_assoc_arr_others.v +++ b/test_regress/t/t_constraint_assoc_arr_others.v @@ -5,96 +5,100 @@ // SPDX-License-Identifier: CC0-1.0 // Enum-based associative array -typedef enum { RED, GREEN, YELLOW } color_t; +typedef enum { + RED, + GREEN, + YELLOW +} color_t; class AssocArrayEnum; - rand bit [7:0] colors [color_t]; - constraint c1 { foreach (colors[i]) colors[i] == 4; } + rand bit [7:0] colors[color_t]; + constraint c1 {foreach (colors[i]) colors[i] == 4;} - function new(); - colors[RED] = 8'd5; - colors[GREEN] = 8'd10; - colors[YELLOW] = 8'd15; - endfunction + function new(); + colors[RED] = 8'd5; + colors[GREEN] = 8'd10; + colors[YELLOW] = 8'd15; + endfunction - function void self_check(); - foreach (colors[i]) begin - if (colors[i] != 4) $stop; - end - endfunction + function void self_check(); + foreach (colors[i]) begin + if (colors[i] != 4) $stop; + end + endfunction endclass // Struct (packed) index associative array typedef struct packed { - bit [2:0] high; - bit [1:0] low; + bit [2:0] high; + bit [1:0] low; } PackedIndexType; class AssocArrayPackedStruct; - rand bit [31:0] data [PackedIndexType]; - constraint c2 { foreach (data[i]) data[i] == 100; } + rand bit [31:0] data[PackedIndexType]; + constraint c2 {foreach (data[i]) data[i] == 100;} - function new(); - PackedIndexType idx; - idx.high = 3'd1; - idx.low = 2'd1; - data[idx] = 32'd50; - endfunction + function new(); + PackedIndexType idx; + idx.high = 3'd1; + idx.low = 2'd1; + data[idx] = 32'd50; + endfunction - function void self_check(); - foreach (data[i]) begin - if (data[i] != 100) $stop; - end - endfunction + function void self_check(); + foreach (data[i]) begin + if (data[i] != 100) $stop; + end + endfunction endclass // Array (packed) index associative array typedef logic [2:0][7:0] IndexArrayType; class AssocArrayArrayIndex; - rand bit [31:0] data [IndexArrayType]; - constraint c3 { foreach (data[i]) data[i] == 0; } + rand bit [31:0] data[IndexArrayType]; + constraint c3 {foreach (data[i]) data[i] == 0;} - function new(); - IndexArrayType idx; - idx = 0; - data[idx] = 32'd75; - endfunction + function new(); + IndexArrayType idx; + idx = 0; + data[idx] = 32'd75; + endfunction - function void self_check(); - foreach (data[i]) begin - if (data[i] != 0) $stop; - end - endfunction + function void self_check(); + foreach (data[i]) begin + if (data[i] != 0) $stop; + end + endfunction endclass module t_constraint_assoc_array_others; - AssocArrayEnum enum_arr; - AssocArrayPackedStruct packed_arr; - AssocArrayArrayIndex array_arr; - int success = 0; + AssocArrayEnum enum_arr; + AssocArrayPackedStruct packed_arr; + AssocArrayArrayIndex array_arr; + int success = 0; - initial begin - // Create instances of the classes - enum_arr = new(); - packed_arr = new(); - array_arr = new(); + initial begin + // Create instances of the classes + enum_arr = new(); + packed_arr = new(); + array_arr = new(); - // Randomization and self-check - success = enum_arr.randomize(); - if (success != 1) $stop; - enum_arr.self_check(); + // Randomization and self-check + success = enum_arr.randomize(); + if (success != 1) $stop; + enum_arr.self_check(); - success = packed_arr.randomize(); - if (success != 1) $stop; - packed_arr.self_check(); + success = packed_arr.randomize(); + if (success != 1) $stop; + packed_arr.self_check(); - success = array_arr.randomize(); - if (success != 1) $stop; - array_arr.self_check(); + success = array_arr.randomize(); + if (success != 1) $stop; + array_arr.self_check(); - $write("*-* All Finished *-*"); - $finish; - end + $write("*-* All Finished *-*"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_before_randc_bad.out b/test_regress/t/t_constraint_before_randc_bad.out index 0d53a0ec5..54ab30db7 100644 --- a/test_regress/t/t_constraint_before_randc_bad.out +++ b/test_regress/t/t_constraint_before_randc_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_constraint_before_randc_bad.v:11:45: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9) - 11 | constraint raint2_bad { solve b1 before b2; } - | ^~ - t/t_constraint_before_randc_bad.v:11:29: ... Location of restricting expression - 11 | constraint raint2_bad { solve b1 before b2; } - | ^~~~~ +%Error: t/t_constraint_before_randc_bad.v:11:42: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9) + 11 | constraint raint2_bad {solve b1 before b2;} + | ^~ + t/t_constraint_before_randc_bad.v:11:26: ... Location of restricting expression + 11 | constraint raint2_bad {solve b1 before b2;} + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_before_randc_bad.v b/test_regress/t/t_constraint_before_randc_bad.v index 9c8868d41..fd99a454f 100644 --- a/test_regress/t/t_constraint_before_randc_bad.v +++ b/test_regress/t/t_constraint_before_randc_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - rand bit b1; - randc int b2; + rand bit b1; + randc int b2; - constraint raint2_bad { solve b1 before b2; } // BAD no randc vars here + constraint raint2_bad {solve b1 before b2;} // BAD no randc vars here endclass module t; diff --git a/test_regress/t/t_constraint_dist.v b/test_regress/t/t_constraint_dist.v index 56cacf9c6..7d27d8748 100644 --- a/test_regress/t/t_constraint_dist.v +++ b/test_regress/t/t_constraint_dist.v @@ -6,46 +6,46 @@ `define check_rand(cl, field, cond) \ begin \ - automatic longint prev_result; \ - automatic int ok; \ - if (!bit'(cl.randomize())) $stop; \ - prev_result = longint'(field); \ - if (!(cond)) $stop; \ - repeat(9) begin \ - longint result; \ - if (!bit'(cl.randomize())) $stop; \ - result = longint'(field); \ - if (!(cond)) $stop; \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end class C; - rand int x, y, z, w; - int que[$] = '{3, 4, 5}; - int arr[3] = '{5, 6, 7}; - constraint distrib { - x dist { [1:3] := 0, [5:6], [9:15] :/ 0 }; - y dist { [1:3] := 0, 5, 6 := 8, [9:15] :/0 }; // /0 intentional to check yP_COLONDIV - x < 20; - }; - constraint distinside { - z dist {que}; - w dist {arr}; - }; + rand int x, y, z, w; + int que[$] = '{3, 4, 5}; + int arr[3] = '{5, 6, 7}; + constraint distrib { + x dist { [1:3] := 0, [5:6], [9:15] :/ 0 }; + y dist { [1:3] := 0, 5, 6 := 8, [9:15] :/0 }; // /0 intentional to check yP_COLONDIV + x < 20; + }; + constraint distinside { + z dist {que}; + w dist {arr}; + }; endclass module t; - initial begin - C c; - c = new; - `check_rand(c, c.x, 5 <= c.x && c.x <= 6); - `check_rand(c, c.y, 5 <= c.y && c.y <= 6); - `check_rand(c, c.z, 3 <= c.z && c.z <= 5); - `check_rand(c, c.w, 5 <= c.w && c.w <= 7); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + C c; + c = new; + `check_rand(c, c.x, 5 <= c.x && c.x <= 6); + `check_rand(c, c.y, 5 <= c.y && c.y <= 6); + `check_rand(c, c.z, 3 <= c.z && c.z <= 5); + `check_rand(c, c.w, 5 <= c.w && c.w <= 7); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_dist_randc_bad.out b/test_regress/t/t_constraint_dist_randc_bad.out index 19ce4e62c..a4afdd756 100644 --- a/test_regress/t/t_constraint_dist_randc_bad.out +++ b/test_regress/t/t_constraint_dist_randc_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_constraint_dist_randc_bad.v:10:23: Randc variables not allowed in 'constraint dist' (IEEE 1800-2023 18.5.3) - 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } - | ^~ - t/t_constraint_dist_randc_bad.v:10:26: ... Location of restricting expression - 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } - | ^~~~ +%Error: t/t_constraint_dist_randc_bad.v:10:22: Randc variables not allowed in 'constraint dist' (IEEE 1800-2023 18.5.3) + 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } + | ^~ + t/t_constraint_dist_randc_bad.v:10:25: ... Location of restricting expression + 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_dist_randc_bad.v b/test_regress/t/t_constraint_dist_randc_bad.v index 9b1e13d7f..065a1b16c 100644 --- a/test_regress/t/t_constraint_dist_randc_bad.v +++ b/test_regress/t/t_constraint_dist_randc_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - randc int rc; + randc int rc; - constraint c_bad { rc dist {3 := 0, 10 := 5}; } // Bad, no dist on randc + constraint c_bad { rc dist {3 := 0, 10 := 5}; } // Bad, no dist on randc endclass module t; diff --git a/test_regress/t/t_constraint_dyn_queue_basic.v b/test_regress/t/t_constraint_dyn_queue_basic.v index ee1a5cd1a..e402c2640 100644 --- a/test_regress/t/t_constraint_dyn_queue_basic.v +++ b/test_regress/t/t_constraint_dyn_queue_basic.v @@ -4,110 +4,112 @@ // SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class ConstrainedDynamicQueueArray; - rand int queue_1d[$]; - rand int queue[$][$]; - rand int dyn[][]; - rand int queue_dyn[$][]; - rand int dyn_queue[][$]; - rand int queue_unp[$][3]; - rand int unp_queue[3][$]; - rand int \array_w[ith_es]cape [3][2]; + rand int queue_1d[$]; + rand int queue[$][$]; + rand int dyn[][]; + rand int queue_dyn[$][]; + rand int dyn_queue[][$]; + rand int queue_unp[$][3]; + rand int unp_queue[3][$]; + rand int \array_w[ith_es]cape [3][2]; - // Constraints for the queues and dynamic arrays - constraint queue_constraints { - foreach (queue_1d[i]) queue_1d[i] == i + 2; - foreach (queue[i, j]) queue[i][j] == (2 * i) + j; - } + // Constraints for the queues and dynamic arrays + constraint queue_constraints { + foreach (queue_1d[i]) queue_1d[i] == i + 2; + foreach (queue[i, j]) queue[i][j] == (2 * i) + j; + } - constraint dyn_constraints { - dyn[0][0] == 10; - dyn[1][0] inside {20, 30, 40}; - dyn[1][1] > 50; - dyn[0][1] < 100; - dyn[0][2] inside {5, 15, 25}; - } + constraint dyn_constraints { + dyn[0][0] == 10; + dyn[1][0] inside {20, 30, 40}; + dyn[1][1] > 50; + dyn[0][1] < 100; + dyn[0][2] inside {5, 15, 25}; + } - constraint queue_dyn_constraints { - foreach (queue_dyn[i, j]) queue_dyn[i][j] == i + j + 3; - } + constraint queue_dyn_constraints { + foreach (queue_dyn[i, j]) queue_dyn[i][j] == i + j + 3; + } - constraint dyn_queue_constraints { - foreach (dyn_queue[i, j]) dyn_queue[i][j] == (3 * i) + j + 2; - } + constraint dyn_queue_constraints { + foreach (dyn_queue[i, j]) dyn_queue[i][j] == (3 * i) + j + 2; + } - constraint unp_queue_constraints { - foreach (unp_queue[i, j]) unp_queue[i][j] == (i * 5) + j + 1; - } + constraint unp_queue_constraints { + foreach (unp_queue[i, j]) unp_queue[i][j] == (i * 5) + j + 1; + } - constraint array_with_escape_constraints { - \array_w[ith_es]cape [0][0] == 6; - } + constraint array_with_escape_constraints { + \array_w[ith_es]cape [0][0] == 6; + } - // Constructor - function new(); - queue_1d = {1, 2, 3, 4}; - queue = '{ '{1, 2}, '{3, 4, 5}, '{6}}; - dyn = new[2]; - dyn[0] = new[3]; - dyn[1] = new[4]; + // Constructor + function new(); + queue_1d = {1, 2, 3, 4}; + queue = '{ '{1, 2}, '{3, 4, 5}, '{6}}; + dyn = new[2]; + dyn[0] = new[3]; + dyn[1] = new[4]; - queue_dyn = {}; - queue_dyn[0] = new[3]; - queue_dyn[1] = new[4]; + queue_dyn = {}; + queue_dyn[0] = new[3]; + queue_dyn[1] = new[4]; - dyn_queue = new[2]; - dyn_queue[0] = {7, 8, 9}; - dyn_queue[1] = {10}; + dyn_queue = new[2]; + dyn_queue[0] = {7, 8, 9}; + dyn_queue[1] = {10}; - queue_unp = {}; + queue_unp = {}; - unp_queue[0] = {17, 18}; - unp_queue[1] = {19}; - unp_queue[2] = {20}; - endfunction + unp_queue[0] = {17, 18}; + unp_queue[1] = {19}; + unp_queue[2] = {20}; + endfunction - // Self-check function - function void check(); - foreach (queue_1d[i]) `checkh(queue_1d[i], i + 2) + // Self-check function + function void check(); + foreach (queue_1d[i]) `checkh(queue_1d[i], i + 2) - foreach (queue[i, j]) `checkh(queue[i][j], (2 * i) + j) + foreach (queue[i, j]) `checkh(queue[i][j], (2 * i) + j) - `checkh(dyn[0][0], 10) - `checkh(dyn[1][0] inside {20, 30, 40}, 1'b1) - `checkh(dyn[1][1] > 50, 1'b1) - `checkh(dyn[0][1] < 100, 1'b1) - `checkh(dyn[0][2] inside {5, 15, 25}, 1'b1) + `checkh(dyn[0][0], 10) + `checkh(dyn[1][0] inside {20, 30, 40}, 1'b1) + `checkh(dyn[1][1] > 50, 1'b1) + `checkh(dyn[0][1] < 100, 1'b1) + `checkh(dyn[0][2] inside {5, 15, 25}, 1'b1) - foreach (queue_dyn[i, j]) `checkh(queue_dyn[i][j], i + j + 3) + foreach (queue_dyn[i, j]) `checkh(queue_dyn[i][j], i + j + 3) - foreach (dyn_queue[i, j]) `checkh(dyn_queue[i][j], (3 * i) + j + 2) + foreach (dyn_queue[i, j]) `checkh(dyn_queue[i][j], (3 * i) + j + 2) - `checkh(unp_queue[0][0], (0 * 5) + 0 + 1) - `checkh(unp_queue[0][1], (0 * 5) + 1 + 1) - `checkh(unp_queue[1][0], (1 * 5) + 0 + 1) - `checkh(unp_queue[2][0], (2 * 5) + 0 + 1) + `checkh(unp_queue[0][0], (0 * 5) + 0 + 1) + `checkh(unp_queue[0][1], (0 * 5) + 1 + 1) + `checkh(unp_queue[1][0], (1 * 5) + 0 + 1) + `checkh(unp_queue[2][0], (2 * 5) + 0 + 1) - `checkh(\array_w[ith_es]cape [0][0], 6) - endfunction + `checkh(\array_w[ith_es]cape [0][0], 6) + endfunction endclass module t_constraint_dyn_queue_basic; - ConstrainedDynamicQueueArray array_test; - int success; - initial begin - $display("Test: Randomization for dynamic and mixed queues and arrays:"); - array_test = new(); - repeat(2) begin - success = array_test.randomize(); - `checkh(success, 1) - array_test.check(); - end - - $write("*-* All Finished *-*\n"); - $finish; + ConstrainedDynamicQueueArray array_test; + int success; + initial begin + $display("Test: Randomization for dynamic and mixed queues and arrays:"); + array_test = new(); + repeat(2) begin + success = array_test.randomize(); + `checkh(success, 1) + array_test.check(); end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_extern.v b/test_regress/t/t_constraint_extern.v index 8e8103b4a..fbacd3841 100644 --- a/test_regress/t/t_constraint_extern.v +++ b/test_regress/t/t_constraint_extern.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int one; - rand int two; + rand int one; + rand int two; - extern function void f(); - constraint cone; - extern constraint ctwo; - constraint cmissing; // Ok per IEEE 1800-2023 18.5.1 + extern function void f(); + constraint cone; + extern constraint ctwo; + constraint cmissing; // Ok per IEEE 1800-2023 18.5.1 endclass @@ -24,18 +24,18 @@ endfunction module t; - Packet p; + Packet p; - int v; + int v; - initial begin - p = new; - v = p.randomize(); - if (v != 1) $stop; - if (p.one != 1) $stop; - if (p.two != 2) $stop; + initial begin + p = new; + v = p.randomize(); + if (v != 1) $stop; + if (p.one != 1) $stop; + if (p.two != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_extern_bad.out b/test_regress/t/t_constraint_extern_bad.out index c47d59249..88b886fa7 100644 --- a/test_regress/t/t_constraint_extern_bad.out +++ b/test_regress/t/t_constraint_extern_bad.out @@ -1,6 +1,6 @@ -%Error-PROTOTYPEMIS: t/t_constraint_extern_bad.v:8:22: Definition not found for extern prototype 'missing_bad' - 8 | extern constraint missing_bad; - | ^~~~~~~~~~~ +%Error-PROTOTYPEMIS: t/t_constraint_extern_bad.v:8:21: Definition not found for extern prototype 'missing_bad' + 8 | extern constraint missing_bad; + | ^~~~~~~~~~~ ... For error description see https://verilator.org/warn/PROTOTYPEMIS?v=latest %Error: t/t_constraint_extern_bad.v:11:20: extern not found that declares 'missing_extern' 11 | constraint Packet::missing_extern { } diff --git a/test_regress/t/t_constraint_extern_bad.v b/test_regress/t/t_constraint_extern_bad.v index 7157122a8..6e02153c0 100644 --- a/test_regress/t/t_constraint_extern_bad.v +++ b/test_regress/t/t_constraint_extern_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - extern constraint missing_bad; + extern constraint missing_bad; endclass constraint Packet::missing_extern { } diff --git a/test_regress/t/t_constraint_foreach.v b/test_regress/t/t_constraint_foreach.v index bc56a8488..cd09269cb 100644 --- a/test_regress/t/t_constraint_foreach.v +++ b/test_regress/t/t_constraint_foreach.v @@ -4,68 +4,70 @@ // SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define check_rand(cl, field, cond) \ begin \ - automatic longint prev_result; \ - automatic int ok; \ - if (!bit'(cl.randomize())) $stop; \ - prev_result = longint'(field); \ - if (!(cond)) $stop; \ - repeat(9) begin \ - longint result; \ - if (!bit'(cl.randomize())) $stop; \ - result = longint'(field); \ - if (!(cond)) $stop; \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end +// verilog_format: on class C; - rand int x; - int q[$] = {0, 0, 0, 0, 0}; - constraint fore { - x < 7; - foreach(q[i]) - x > i; - foreach(q[i]) // loop again with the same index name - x > i; - }; + rand int x; + int q[$] = {0, 0, 0, 0, 0}; + constraint fore { + x < 7; + foreach(q[i]) + x > i; + foreach(q[i]) // loop again with the same index name + x > i; + }; endclass class D; - rand bit posit; - rand int x; - int o[$]; // empty - int p[$] = {1}; - int q[$] = {0, 0, 0, 0, 0}; - constraint fore { - if (posit == 1) { - foreach(o[i]) o[i] > 0; - } - if (posit == 1) { - foreach(p[i]) p[i] > 0; - } - if (posit == 1) { - x < 7; - foreach(q[i]) - x > i; - } else { - x > -3; - foreach(q[i]) - x < i; - } - }; + rand bit posit; + rand int x; + int o[$]; // empty + int p[$] = {1}; + int q[$] = {0, 0, 0, 0, 0}; + constraint fore { + if (posit == 1) { + foreach(o[i]) o[i] > 0; + } + if (posit == 1) { + foreach(p[i]) p[i] > 0; + } + if (posit == 1) { + x < 7; + foreach(q[i]) + x > i; + } else { + x > -3; + foreach(q[i]) + x < i; + } + }; endclass module t; - initial begin - automatic C c = new; - automatic D d = new; - `check_rand(c, c.x, 4 < c.x && c.x < 7); - `check_rand(d, d.posit, (d.posit ? 4 : -3) < d.x && d.x < (d.posit ? 7 : 0)); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic C c = new; + automatic D d = new; + `check_rand(c, c.x, 4 < c.x && c.x < 7); + `check_rand(d, d.posit, (d.posit ? 4 : -3) < d.x && d.x < (d.posit ? 7 : 0)); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index 96e145376..293a70a29 100644 --- a/test_regress/t/t_constraint_json_only.out +++ b/test_regress/t/t_constraint_json_only.out @@ -2,16 +2,16 @@ "modulesp": [ {"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:11,69:12","dtypep":"(H)","origName":"p","verilogName":"p","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"Packet","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:4,71:11", + {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:10,69:11","dtypep":"(H)","origName":"p","verilogName":"p","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"Packet","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:3,71:10", "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(J)","loc":"d,71:12,71:17","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(J)","loc":"d,71:11,71:16","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(K)","loc":"d,73:7,73:13", + {"type":"DISPLAY","name":"","addr":"(K)","loc":"d,73:5,73:11", "fmtp": [ - {"type":"SFORMATF","name":"*-* All Finished *-*\\n","addr":"(L)","loc":"d,73:7,73:13","dtypep":"(M)","exprsp": [],"scopeNamep": []} + {"type":"SFORMATF","name":"*-* All Finished *-*\\n","addr":"(L)","loc":"d,73:5,73:11","dtypep":"(M)","exprsp": [],"scopeNamep": []} ],"filep": []}, - {"type":"FINISH","name":"","addr":"(N)","loc":"d,74:7,74:14"} + {"type":"FINISH","name":"","addr":"(N)","loc":"d,74:5,74:12"} ]} ]} ]}, @@ -19,40 +19,40 @@ "stmtsp": [ {"type":"CLASS","name":"Packet","addr":"(O)","loc":"d,7:1,7:6","origName":"Packet","verilogName":"Packet","level":3,"timeunit":"1ps","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"header","addr":"(P)","loc":"d,8:13,8:19","dtypep":"(Q)","origName":"header","verilogName":"header","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"length","addr":"(R)","loc":"d,9:13,9:19","dtypep":"(Q)","origName":"length","verilogName":"length","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"sublength","addr":"(S)","loc":"d,10:13,10:22","dtypep":"(Q)","origName":"sublength","verilogName":"sublength","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"if_4","addr":"(T)","loc":"d,11:13,11:17","dtypep":"(U)","origName":"if_4","verilogName":"if_4","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"iff_5_6","addr":"(V)","loc":"d,12:13,12:20","dtypep":"(U)","origName":"iff_5_6","verilogName":"iff_5_6","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"if_state_ok","addr":"(W)","loc":"d,13:13,13:24","dtypep":"(U)","origName":"if_state_ok","verilogName":"if_state_ok","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"array","addr":"(X)","loc":"d,15:13,15:18","dtypep":"(Y)","origName":"array","verilogName":"array","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"state","addr":"(Z)","loc":"d,17:11,17:16","dtypep":"(M)","origName":"state","verilogName":"state","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"FUNC","name":"strings_equal","addr":"(AB)","loc":"d,61:17,61:30","dtypep":"(U)","method":true,"cname":"strings_equal", + {"type":"VAR","name":"header","addr":"(P)","loc":"d,8:12,8:18","dtypep":"(Q)","origName":"header","verilogName":"header","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"length","addr":"(R)","loc":"d,9:12,9:18","dtypep":"(Q)","origName":"length","verilogName":"length","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"sublength","addr":"(S)","loc":"d,10:12,10:21","dtypep":"(Q)","origName":"sublength","verilogName":"sublength","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"if_4","addr":"(T)","loc":"d,11:12,11:16","dtypep":"(U)","origName":"if_4","verilogName":"if_4","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"iff_5_6","addr":"(V)","loc":"d,12:12,12:19","dtypep":"(U)","origName":"iff_5_6","verilogName":"iff_5_6","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"if_state_ok","addr":"(W)","loc":"d,13:12,13:23","dtypep":"(U)","origName":"if_state_ok","verilogName":"if_state_ok","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"array","addr":"(X)","loc":"d,15:12,15:17","dtypep":"(Y)","origName":"array","verilogName":"array","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"state","addr":"(Z)","loc":"d,17:10,17:15","dtypep":"(M)","origName":"state","verilogName":"state","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"FUNC","name":"strings_equal","addr":"(AB)","loc":"d,61:16,61:29","dtypep":"(U)","method":true,"cname":"strings_equal", "fvarp": [ - {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:17,61:30","dtypep":"(U)","origName":"strings_equal","verilogName":"strings_equal","direction":"OUTPUT","noCReset":true,"isFuncReturn":true,"isFuncLocal":true,"lifetime":"VAUTOM","varType":"VAR","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:16,61:29","dtypep":"(U)","origName":"strings_equal","verilogName":"strings_equal","direction":"OUTPUT","noCReset":true,"isFuncReturn":true,"isFuncLocal":true,"lifetime":"VAUTOM","varType":"VAR","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"classOrPackagep": [], "stmtsp": [ - {"type":"VAR","name":"a","addr":"(CB)","loc":"d,61:38,61:39","dtypep":"(M)","origName":"a","verilogName":"a","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"b","addr":"(DB)","loc":"d,61:48,61:49","dtypep":"(M)","origName":"b","verilogName":"b","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ASSIGN","name":"","addr":"(EB)","loc":"d,61:17,61:30","dtypep":"(U)", + {"type":"VAR","name":"a","addr":"(CB)","loc":"d,61:37,61:38","dtypep":"(M)","origName":"a","verilogName":"a","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"b","addr":"(DB)","loc":"d,61:47,61:48","dtypep":"(M)","origName":"b","verilogName":"b","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ASSIGN","name":"","addr":"(EB)","loc":"d,61:16,61:29","dtypep":"(U)", "rhsp": [ - {"type":"CONST","name":"1'h0","addr":"(FB)","loc":"d,61:17,61:30","dtypep":"(GB)"} + {"type":"CONST","name":"1'h0","addr":"(FB)","loc":"d,61:16,61:29","dtypep":"(GB)"} ], "lhsp": [ - {"type":"VARREF","name":"strings_equal","addr":"(HB)","loc":"d,61:17,61:30","dtypep":"(U)","access":"WR","varp":"(BB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"strings_equal","addr":"(HB)","loc":"d,61:16,61:29","dtypep":"(U)","access":"WR","varp":"(BB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, - {"type":"ASSIGN","name":"","addr":"(IB)","loc":"d,62:7,62:13","dtypep":"(U)", + {"type":"ASSIGN","name":"","addr":"(IB)","loc":"d,62:5,62:11","dtypep":"(U)", "rhsp": [ - {"type":"EQN","name":"","addr":"(JB)","loc":"d,62:16,62:18","dtypep":"(GB)", + {"type":"EQN","name":"","addr":"(JB)","loc":"d,62:14,62:16","dtypep":"(GB)", "lhsp": [ - {"type":"VARREF","name":"a","addr":"(KB)","loc":"d,62:14,62:15","dtypep":"(M)","access":"RD","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} + {"type":"VARREF","name":"a","addr":"(KB)","loc":"d,62:12,62:13","dtypep":"(M)","access":"RD","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} ], "rhsp": [ - {"type":"VARREF","name":"b","addr":"(LB)","loc":"d,62:19,62:20","dtypep":"(M)","access":"RD","varp":"(DB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} + {"type":"VARREF","name":"b","addr":"(LB)","loc":"d,62:17,62:18","dtypep":"(M)","access":"RD","varp":"(DB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} ]} ], "lhsp": [ - {"type":"VARREF","name":"strings_equal","addr":"(MB)","loc":"d,62:7,62:13","dtypep":"(U)","access":"WR","varp":"(BB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"strings_equal","addr":"(MB)","loc":"d,62:5,62:11","dtypep":"(U)","access":"WR","varp":"(BB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"new","addr":"(NB)","loc":"d,7:1,7:6","dtypep":"(OB)","method":true,"cname":"new","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, @@ -63,23 +63,23 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(OB)", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,22:14,22:15","dtypep":"(GB)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,25:21,25:22","dtypep":"(RB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"string","addr":"(M)","loc":"d,73:7,73:13","dtypep":"(M)","keyword":"string","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:9,11:12","dtypep":"(U)","keyword":"bit","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","declRange":"[0:1]","signed":true,"refDTypep":"(Q)","childDTypep": [], + {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,22:12,22:13","dtypep":"(GB)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,25:19,25:20","dtypep":"(RB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"string","addr":"(M)","loc":"d,73:5,73:11","dtypep":"(M)","keyword":"string","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:8,8:11","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:8,11:11","dtypep":"(U)","keyword":"bit","generic":true,"rangep": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:17,15:18","dtypep":"(Y)","declRange":"[0:1]","signed":true,"refDTypep":"(Q)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(SB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true, + {"type":"RANGE","name":"","addr":"(SB)","loc":"d,15:17,15:18","ascending":true,"fromBracket":true, "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(TB)","loc":"d,15:19,15:20","dtypep":"(RB)"} + {"type":"CONST","name":"32'h0","addr":"(TB)","loc":"d,15:18,15:19","dtypep":"(RB)"} ], "rightp": [ - {"type":"CONST","name":"32'h1","addr":"(UB)","loc":"d,15:19,15:20","dtypep":"(RB)"} + {"type":"CONST","name":"32'h1","addr":"(UB)","loc":"d,15:18,15:19","dtypep":"(RB)"} ]} ]}, {"type":"VOIDDTYPE","name":"","addr":"(OB)","loc":"d,7:1,7:6","dtypep":"(OB)"}, - {"type":"CLASSREFDTYPE","name":"Packet","addr":"(H)","loc":"d,69:4,69:10","dtypep":"(H)","classp":"(O)","classOrPackagep":"(O)","paramsp": []}, + {"type":"CLASSREFDTYPE","name":"Packet","addr":"(H)","loc":"d,69:3,69:9","dtypep":"(H)","classp":"(O)","classOrPackagep":"(O)","paramsp": []}, {"type":"BASICDTYPE","name":"VlRandomizer","addr":"(QB)","loc":"d,7:1,7:6","dtypep":"(QB)","keyword":"VlRandomizer","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_constraint_json_only.v b/test_regress/t/t_constraint_json_only.v index 93bb4ca33..33beda4de 100644 --- a/test_regress/t/t_constraint_json_only.v +++ b/test_regress/t/t_constraint_json_only.v @@ -5,72 +5,72 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int header; // 0..7 - rand int length; // 0..15 - rand int sublength; // 0..15 - rand bit if_4; - rand bit iff_5_6; - rand bit if_state_ok; + rand int header; // 0..7 + rand int length; // 0..15 + rand int sublength; // 0..15 + rand bit if_4; + rand bit iff_5_6; + rand bit if_state_ok; - rand int array[2]; // 2,4,6 + rand int array[2]; // 2,4,6 - string state; + string state; - constraint empty {} + constraint empty {} - constraint size { - header > 0 && header <= 7; - length <= 15; - length >= header; - length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; - } + constraint size { + header > 0 && header <= 7; + length <= 15; + length >= header; + length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; + } - constraint ifs { - if (header > 4) { - if_4 == '1; - } - if (header == 5 || header == 6) { - iff_5_6 == '1; - iff_5_6 == '1; - iff_5_6 == '1; - } else { - iff_5_6 == '0; - } - } + constraint ifs { + if (header > 4) { + if_4 == '1; + } + if (header == 5 || header == 6) { + iff_5_6 == '1; + iff_5_6 == '1; + iff_5_6 == '1; + } else { + iff_5_6 == '0; + } + } - constraint arr_uniq { - foreach (array[i]) { - array[i] inside {2, 4, 6}; - } - unique { array[0], array[1] }; - } + constraint arr_uniq { + foreach (array[i]) { + array[i] inside {2, 4, 6}; + } + unique { array[0], array[1] }; + } - constraint order { solve length before header; } + constraint order { solve length before header; } - constraint dis { - soft sublength; - disable soft sublength; - sublength <= length; - } + constraint dis { + soft sublength; + disable soft sublength; + sublength <= length; + } - constraint meth { - if (strings_equal(state, "ok")) - if_state_ok == '1; - } + constraint meth { + if (strings_equal(state, "ok")) + if_state_ok == '1; + } - function bit strings_equal(string a, string b); - return a == b; - endfunction + function bit strings_equal(string a, string b); + return a == b; + endfunction endclass module t; - Packet p; + Packet p; - initial begin - // Not testing use of constraints - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Not testing use of constraints + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_method_bad.out b/test_regress/t/t_constraint_method_bad.out index 4fba6ec70..a4843268a 100644 --- a/test_regress/t/t_constraint_method_bad.out +++ b/test_regress/t/t_constraint_method_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_constraint_method_bad.v:13:12: No such constraint method 'bad_method' +%Error: t/t_constraint_method_bad.v:13:10: No such constraint method 'bad_method' : ... note: In instance 't' - 13 | cons.bad_method(1); - | ^~~~~~~~~~ + 13 | cons.bad_method(1); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_method_bad.v b/test_regress/t/t_constraint_method_bad.v index af2252995..8fb1e1ebb 100644 --- a/test_regress/t/t_constraint_method_bad.v +++ b/test_regress/t/t_constraint_method_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int m_one; + rand int m_one; - constraint cons { m_one > 0 && m_one < 2; } + constraint cons { m_one > 0 && m_one < 2; } - task test1; - cons.bad_method(1); // BAD - endtask + task test1; + cons.bad_method(1); // BAD + endtask endclass diff --git a/test_regress/t/t_constraint_mode_bad.out b/test_regress/t/t_constraint_mode_bad.out index 643bcaf5d..ac35b623e 100644 --- a/test_regress/t/t_constraint_mode_bad.out +++ b/test_regress/t/t_constraint_mode_bad.out @@ -1,24 +1,24 @@ -%Error: t/t_constraint_mode_bad.v:21:15: Cannot call 'constraint_mode()' on a non-class variable +%Error: t/t_constraint_mode_bad.v:21:13: Cannot call 'constraint_mode()' on a non-class variable : ... note: In instance 't' - 21 | p.m_one.constraint_mode(0); - | ^~~~~~~~~~~~~~~ + 21 | p.m_one.constraint_mode(0); + | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_constraint_mode_bad.v:22:45: Cannot call 'constraint_mode()' as a function on a variable +%Error: t/t_constraint_mode_bad.v:22:43: Cannot call 'constraint_mode()' as a function on a variable : ... note: In instance 't' - 22 | $display("p.constraint_mode()=%0d", p.constraint_mode()); - | ^~~~~~~~~~~~~~~ -%Error: t/t_constraint_mode_bad.v:23:18: 'constraint_mode()' with arguments cannot be called as a function + 22 | $display("p.constraint_mode()=%0d", p.constraint_mode()); + | ^~~~~~~~~~~~~~~ +%Error: t/t_constraint_mode_bad.v:23:16: 'constraint_mode()' with arguments cannot be called as a function : ... note: In instance 't' - 23 | $display(p.constraint_mode(0)); - | ^~~~~~~~~~~~~~~ -%Warning-IGNOREDRETURN: t/t_constraint_mode_bad.v:24:14: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 23 | $display(p.constraint_mode(0)); + | ^~~~~~~~~~~~~~~ +%Warning-IGNOREDRETURN: t/t_constraint_mode_bad.v:24:12: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) : ... note: In instance 't' - 24 | p.cons.constraint_mode(); - | ^~~~~~~~~~~~~~~ + 24 | p.cons.constraint_mode(); + | ^~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. -%Error: t/t_constraint_mode_bad.v:12:14: Cannot call 'constraint_mode()' as a function on a variable +%Error: t/t_constraint_mode_bad.v:12:12: Cannot call 'constraint_mode()' as a function on a variable : ... note: In instance 't' - 12 | return constraint_mode(); - | ^~~~~~~~~~~~~~~ + 12 | return constraint_mode(); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_constraint_mode_bad.v b/test_regress/t/t_constraint_mode_bad.v index 7aa527fe8..8cc81af04 100644 --- a/test_regress/t/t_constraint_mode_bad.v +++ b/test_regress/t/t_constraint_mode_bad.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - int m_one; - constraint cons { m_one > 0 && m_one < 2; } + int m_one; + constraint cons { m_one > 0 && m_one < 2; } - function int get_constraint_mode; - return constraint_mode(); - endfunction + function int get_constraint_mode; + return constraint_mode(); + endfunction endclass module t; - Packet p; + Packet p; - initial begin - p = new; - p.m_one.constraint_mode(0); - $display("p.constraint_mode()=%0d", p.constraint_mode()); - $display(p.constraint_mode(0)); - p.cons.constraint_mode(); - end + initial begin + p = new; + p.m_one.constraint_mode(0); + $display("p.constraint_mode()=%0d", p.constraint_mode()); + $display(p.constraint_mode(0)); + p.cons.constraint_mode(); + end endmodule diff --git a/test_regress/t/t_constraint_operators.v b/test_regress/t/t_constraint_operators.v index b9d1b1ba0..3070007d7 100644 --- a/test_regress/t/t_constraint_operators.v +++ b/test_regress/t/t_constraint_operators.v @@ -5,131 +5,131 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int x; - rand int y; - rand int z; - rand int w; - rand int v; - rand int u; - rand bit [31:0] b; - rand bit [31:0] c; - rand bit [31:0] d; - rand bit [31:0] e; - rand bit [31:0] f; - rand bit tiny; - rand bit zero; - rand bit one; - rand int out0, out1, out2, out3, out4, out5, out6; + rand int x; + rand int y; + rand int z; + rand int w; + rand int v; + rand int u; + rand bit [31:0] b; + rand bit [31:0] c; + rand bit [31:0] d; + rand bit [31:0] e; + rand bit [31:0] f; + rand bit tiny; + rand bit zero; + rand bit one; + rand int out0, out1, out2, out3, out4, out5, out6; - bit state; + bit state; - typedef bit signed [63:0] s64; - typedef bit [63:0] u64; + typedef bit signed [63:0] s64; + typedef bit [63:0] u64; - constraint arith { x + x - x == x; } - constraint divmod { int'((x % 5) / 2) != (b % 99) / 7; } - constraint mul { x * 9 != b * 3; } - constraint mul_signed { - y * y == 4; - y > 0; - y < 4; - z * z == 4; - z < 0; - z > -4; - } - constraint c_power { e ** 32'h5 < 10000; } - constraint c_power_ss { w ** 5 < 10000; } - constraint c_power_us { f ** 5 < 10000; } - constraint c_power_su { v ** 32'h5 < 10000; } - constraint c_power_many { u ** 2 ** 3 < 1000; u > 2; u < 10; } - // check for negative values in constant - constraint c_power_neg_exp { v ** 4'shf == 0; } - constraint c_power_u_neg_exp { f ** 4'shf == 0; } - constraint c_power_zero_exp { v ** 0 == 1; } - constraint c_power_u_zero_exp { f ** 0 == 1; } - constraint impl { tiny == 1 -> x != 10; } - constraint concat { {c, b} != 'h1111; } - constraint unary { !(-~c == 'h22); } - constraint log { ((b ^ c) & (b >>> c | b >> c | b << c)) > 0; } - constraint cmps { x < x || x <= x || x > x || x >= x; } - constraint cmpu { b < b || b <= b || b > b || b >= b; } - constraint ext { s64'(x) != u64'(tiny); } - constraint cond { (tiny == 1 ? b : c) != 17; } - constraint zero_c { zero == 0; } - constraint one_c { one == 1; } - constraint sel { d[15:8] == 8'h55; } - constraint ifelse { - if (one) out0 == 'h333; + constraint arith { x + x - x == x; } + constraint divmod { int'((x % 5) / 2) != (b % 99) / 7; } + constraint mul { x * 9 != b * 3; } + constraint mul_signed { + y * y == 4; + y > 0; + y < 4; + z * z == 4; + z < 0; + z > -4; + } + constraint c_power { e ** 32'h5 < 10000; } + constraint c_power_ss { w ** 5 < 10000; } + constraint c_power_us { f ** 5 < 10000; } + constraint c_power_su { v ** 32'h5 < 10000; } + constraint c_power_many { u ** 2 ** 3 < 1000; u > 2; u < 10; } + // check for negative values in constant + constraint c_power_neg_exp { v ** 4'shf == 0; } + constraint c_power_u_neg_exp { f ** 4'shf == 0; } + constraint c_power_zero_exp { v ** 0 == 1; } + constraint c_power_u_zero_exp { f ** 0 == 1; } + constraint impl { tiny == 1 -> x != 10; } + constraint concat { {c, b} != 'h1111; } + constraint unary { !(-~c == 'h22); } + constraint log { ((b ^ c) & (b >>> c | b >> c | b << c)) > 0; } + constraint cmps { x < x || x <= x || x > x || x >= x; } + constraint cmpu { b < b || b <= b || b > b || b >= b; } + constraint ext { s64'(x) != u64'(tiny); } + constraint cond { (tiny == 1 ? b : c) != 17; } + constraint zero_c { zero == 0; } + constraint one_c { one == 1; } + constraint sel { d[15:8] == 8'h55; } + constraint ifelse { + if (one) out0 == 'h333; - if (!one) tiny != tiny; - else out1 == 'h333; - if (one == 1) out2 == 'h333; + if (!one) tiny != tiny; + else out1 == 'h333; + if (one == 1) out2 == 'h333; + else tiny != tiny; + if (0) tiny != tiny; + else out3 == 'h333; + if (1) out4 == 'h333; + else tiny != tiny; + + if (one == 1) + if (1) { out5 == 'h333; out5 == 'h333; out5 == 'h333; } else tiny != tiny; - if (0) tiny != tiny; - else out3 == 'h333; - if (1) out4 == 'h333; + else + if (1) tiny != tiny; + else { tiny != tiny; } + + if (1) + if (one == 1) { out6 == 'h333; out6 == 'h333; out6 == 'h333; } else tiny != tiny; + else + if (one == 1) tiny != tiny; + else { tiny != tiny; } - if (one == 1) - if (1) { out5 == 'h333; out5 == 'h333; out5 == 'h333; } - else tiny != tiny; - else - if (1) tiny != tiny; - else { tiny != tiny; } - - if (1) - if (one == 1) { out6 == 'h333; out6 == 'h333; out6 == 'h333; } - else tiny != tiny; - else - if (one == 1) tiny != tiny; - else { tiny != tiny; } - - if (one && zero) tiny != tiny; - if (~one && zero) tiny != tiny; - if (zero || (one & zero)) tiny != tiny; - if (zero && (one | zero)) tiny != tiny; - } + if (one && zero) tiny != tiny; + if (~one && zero) tiny != tiny; + if (zero || (one & zero)) tiny != tiny; + if (zero && (one | zero)) tiny != tiny; + } endclass module t; - Packet p; + Packet p; - int v; + int v; - initial begin - p = new; - v = p.randomize(); - if (v != 1) $stop; - if ((p.x % 5) / 2 == (p.b % 99) / 7) $stop; - if (p.x * 9 == p.b * 3) $stop; - if (p.y != 2) $stop; - if (p.z != -2) $stop; - if (p.w ** 5 >= 10000) $stop; - if (p.e ** 32'h5 >= 10000) $stop; - if (p.v ** 32'h5 >= 10000) $stop; - if (p.f ** 5 >= 10000) $stop; - if (p.u != 3) $stop; - if (p.tiny && p.x == 10) $stop; - if ({p.c, p.b} == 'h1111) $stop; - if (-~p.c == 'h22) $stop; - if (((p.b ^ p.c) & (p.b >>> p.c | p.b >> p.c | p.b << p.c)) <= 0) $stop; - if (p.x == int'(p.tiny)) $stop; - if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; - if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; - if (p.zero != 0) $stop; - if (p.one != 1) $stop; - if (p.out0 != 'h333) $stop; - if (p.out1 != 'h333) $stop; - if (p.out2 != 'h333) $stop; - if (p.out3 != 'h333) $stop; - if (p.out4 != 'h333) $stop; - if (p.out5 != 'h333) $stop; - if (p.out6 != 'h333) $stop; - if (p.d[15:8] != 'h55) $stop; + initial begin + p = new; + v = p.randomize(); + if (v != 1) $stop; + if ((p.x % 5) / 2 == (p.b % 99) / 7) $stop; + if (p.x * 9 == p.b * 3) $stop; + if (p.y != 2) $stop; + if (p.z != -2) $stop; + if (p.w ** 5 >= 10000) $stop; + if (p.e ** 32'h5 >= 10000) $stop; + if (p.v ** 32'h5 >= 10000) $stop; + if (p.f ** 5 >= 10000) $stop; + if (p.u != 3) $stop; + if (p.tiny && p.x == 10) $stop; + if ({p.c, p.b} == 'h1111) $stop; + if (-~p.c == 'h22) $stop; + if (((p.b ^ p.c) & (p.b >>> p.c | p.b >> p.c | p.b << p.c)) <= 0) $stop; + if (p.x == int'(p.tiny)) $stop; + if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; + if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; + if (p.zero != 0) $stop; + if (p.one != 1) $stop; + if (p.out0 != 'h333) $stop; + if (p.out1 != 'h333) $stop; + if (p.out2 != 'h333) $stop; + if (p.out3 != 'h333) $stop; + if (p.out4 != 'h333) $stop; + if (p.out5 != 'h333) $stop; + if (p.out6 != 'h333) $stop; + if (p.d[15:8] != 'h55) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_pure.v b/test_regress/t/t_constraint_pure.v index 17e5d7bd5..befb0c9a3 100644 --- a/test_regress/t/t_constraint_pure.v +++ b/test_regress/t/t_constraint_pure.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 virtual class Base; - pure constraint raint; + pure constraint raint; endclass class Cls extends Base; - rand int b2; - constraint raint { b2 == 5; } + rand int b2; + constraint raint { b2 == 5; } endclass virtual class Virt extends Base; - // No constraint needed + // No constraint needed endclass module t; - initial begin - automatic Cls c = new; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic Cls c = new; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_pure_missing_bad.out b/test_regress/t/t_constraint_pure_missing_bad.out index 425b26c88..e1aa98684 100644 --- a/test_regress/t/t_constraint_pure_missing_bad.out +++ b/test_regress/t/t_constraint_pure_missing_bad.out @@ -1,8 +1,8 @@ %Error: t/t_constraint_pure_missing_bad.v:11:1: Class 'Cls' extends 'Base' but is missing constraint implementation for 'raint' (IEEE 1800-2023 18.5.2) 11 | class Cls extends Base; | ^~~~~ - t/t_constraint_pure_missing_bad.v:8:21: ... Location of interface class's pure constraint - 8 | pure constraint raint; - | ^~~~~ + t/t_constraint_pure_missing_bad.v:8:20: ... Location of interface class's pure constraint + 8 | pure constraint raint; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_pure_missing_bad.v b/test_regress/t/t_constraint_pure_missing_bad.v index 39af139bb..8042a4074 100644 --- a/test_regress/t/t_constraint_pure_missing_bad.v +++ b/test_regress/t/t_constraint_pure_missing_bad.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 virtual class Base; - pure constraint raint; + pure constraint raint; endclass class Cls extends Base; - // Bad: Missing 'constraint raint' + // Bad: Missing 'constraint raint' endclass module t; diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.out b/test_regress/t/t_constraint_pure_nonabs_bad.out index 9ad026d65..3de1a490d 100644 --- a/test_regress/t/t_constraint_pure_nonabs_bad.out +++ b/test_regress/t/t_constraint_pure_nonabs_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_constraint_pure_nonabs_bad.v:8:21: Illegal to have 'pure constraint' in non-abstract class (IEEE 1800-2023 18.5.2) +%Error: t/t_constraint_pure_nonabs_bad.v:8:20: Illegal to have 'pure constraint' in non-abstract class (IEEE 1800-2023 18.5.2) : ... note: In instance 't' - 8 | pure constraint raintBad; - | ^~~~~~~~ + 8 | pure constraint raintBad; + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.v b/test_regress/t/t_constraint_pure_nonabs_bad.v index 9f3343f12..0ecef66a6 100644 --- a/test_regress/t/t_constraint_pure_nonabs_bad.v +++ b/test_regress/t/t_constraint_pure_nonabs_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 class NonAsbstract; - pure constraint raintBad; // Bad: Not in abstract class + pure constraint raintBad; // Bad: Not in abstract class endclass module t; diff --git a/test_regress/t/t_constraint_soft_randc_bad.out b/test_regress/t/t_constraint_soft_randc_bad.out index 61ab00601..5a20ca3cd 100644 --- a/test_regress/t/t_constraint_soft_randc_bad.out +++ b/test_regress/t/t_constraint_soft_randc_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_constraint_soft_randc_bad.v:10:28: Randc variables not allowed in 'constraint soft' (IEEE 1800-2023 18.5.13.1) - 10 | constraint c_bad { soft rc > 4; } - | ^~ - t/t_constraint_soft_randc_bad.v:10:23: ... Location of restricting expression - 10 | constraint c_bad { soft rc > 4; } - | ^~~~ +%Error: t/t_constraint_soft_randc_bad.v:10:27: Randc variables not allowed in 'constraint soft' (IEEE 1800-2023 18.5.13.1) + 10 | constraint c_bad { soft rc > 4; } + | ^~ + t/t_constraint_soft_randc_bad.v:10:22: ... Location of restricting expression + 10 | constraint c_bad { soft rc > 4; } + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_soft_randc_bad.v b/test_regress/t/t_constraint_soft_randc_bad.v index f9581baf9..e1fb5f933 100644 --- a/test_regress/t/t_constraint_soft_randc_bad.v +++ b/test_regress/t/t_constraint_soft_randc_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 class Cls1; - randc int rc; + randc int rc; - constraint c_bad { soft rc > 4; } // Bad, no soft on randc + constraint c_bad { soft rc > 4; } // Bad, no soft on randc endclass module t; diff --git a/test_regress/t/t_constraint_struct.v b/test_regress/t/t_constraint_struct.v index 49f921015..8c1bb2acb 100644 --- a/test_regress/t/t_constraint_struct.v +++ b/test_regress/t/t_constraint_struct.v @@ -5,83 +5,83 @@ // SPDX-License-Identifier: CC0-1.0 typedef struct packed { - bit [7:0] byte_value; - int int_value; + bit [7:0] byte_value; + int int_value; } PackedStruct; typedef struct { - rand bit [7:0] byte_value; - rand int int_value; - int non_rand_value; // Non-randomized member + rand bit [7:0] byte_value; + rand int int_value; + int non_rand_value; // Non-randomized member } UnpackedStruct; class PackedStructTest; - rand PackedStruct packed_struct; + rand PackedStruct packed_struct; - function new(); - packed_struct.byte_value = 8'hA0; - packed_struct.int_value = 0; - endfunction + function new(); + packed_struct.byte_value = 8'hA0; + packed_struct.int_value = 0; + endfunction - // Constraint block for packed struct - constraint packed_struct_constraint { - packed_struct.byte_value == 8'hA0; - packed_struct.int_value inside {[0:100]}; - } + // Constraint block for packed struct + constraint packed_struct_constraint { + packed_struct.byte_value == 8'hA0; + packed_struct.int_value inside {[0 : 100]}; + } - // Self-check function for packed struct - function void check(); - if (packed_struct.byte_value != 8'hA0) $stop; - if (!(packed_struct.int_value inside {[0:100]})) $stop; - endfunction + // Self-check function for packed struct + function void check(); + if (packed_struct.byte_value != 8'hA0) $stop; + if (!(packed_struct.int_value inside {[0 : 100]})) $stop; + endfunction endclass class UnpackedStructTest; - rand UnpackedStruct unpacked_struct; + rand UnpackedStruct unpacked_struct; - function new(); - unpacked_struct.byte_value = 8'h00; - unpacked_struct.int_value = 0; - unpacked_struct.non_rand_value = 42; - endfunction + function new(); + unpacked_struct.byte_value = 8'h00; + unpacked_struct.int_value = 0; + unpacked_struct.non_rand_value = 42; + endfunction - // Constraint block for unpacked struct - constraint unpacked_struct_constraint { - unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0}; - unpacked_struct.int_value inside {[50:150]}; - } + // Constraint block for unpacked struct + constraint unpacked_struct_constraint { + unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0}; + unpacked_struct.int_value inside {[50 : 150]}; + } - // Self-check function for unpacked struct - function void check(); - if (!(unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0})) $stop; - if (!(unpacked_struct.int_value inside {[50:150]})) $stop; - if (unpacked_struct.non_rand_value != 42) $stop; // Check non-randomized member - endfunction + // Self-check function for unpacked struct + function void check(); + if (!(unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0})) $stop; + if (!(unpacked_struct.int_value inside {[50 : 150]})) $stop; + if (unpacked_struct.non_rand_value != 42) $stop; // Check non-randomized member + endfunction endclass module t_constraint_struct; - PackedStructTest packed_struct_test; - UnpackedStructTest unpacked_struct_test; - int success; + PackedStructTest packed_struct_test; + UnpackedStructTest unpacked_struct_test; + int success; - initial begin - // Test packed struct - packed_struct_test = new(); - repeat(10) begin - success = packed_struct_test.randomize(); - if (success == 0) $stop; - packed_struct_test.check(); // Self-check for packed struct - end - - // Test unpacked struct - unpacked_struct_test = new(); - repeat(10) begin - success = unpacked_struct_test.randomize(); - if (success == 0) $stop; - unpacked_struct_test.check(); // Self-check for unpacked struct - end - - $write("*-* All Finished *-*\n"); - $finish; + initial begin + // Test packed struct + packed_struct_test = new(); + repeat (10) begin + success = packed_struct_test.randomize(); + if (success == 0) $stop; + packed_struct_test.check(); // Self-check for packed struct end + + // Test unpacked struct + unpacked_struct_test = new(); + repeat (10) begin + success = unpacked_struct_test.randomize(); + if (success == 0) $stop; + unpacked_struct_test.check(); // Self-check for unpacked struct + end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_struct_complex.v b/test_regress/t/t_constraint_struct_complex.v index a9a319f83..bc978181e 100644 --- a/test_regress/t/t_constraint_struct_complex.v +++ b/test_regress/t/t_constraint_struct_complex.v @@ -6,487 +6,487 @@ class ArrayStruct; - /* verilator lint_off SIDEEFFECT */ + /* verilator lint_off SIDEEFFECT */ - // Struct with an unpacked array - typedef int arr_3_t[3]; - typedef int arr_4_t[4]; - typedef struct { - rand arr_3_t arr_3; - arr_4_t arr_4; - rand int arr[3]; - } unpacked_struct_t; + // Struct with an unpacked array + typedef int arr_3_t[3]; + typedef int arr_4_t[4]; + typedef struct { + rand arr_3_t arr_3; + arr_4_t arr_4; + rand int arr[3]; + } unpacked_struct_t; - // Struct with a dynamic array - typedef struct { - rand int arr[]; - } dynamic_struct_t; + // Struct with a dynamic array + typedef struct { + rand int arr[]; + } dynamic_struct_t; - // Struct with a queue - typedef struct { - rand int arr[$]; - } queue_struct_t; + // Struct with a queue + typedef struct { + rand int arr[$]; + } queue_struct_t; - // Struct with an associative array (string as index) - typedef struct { - rand int arr[string]; - } associative_struct_t; + // Struct with an associative array (string as index) + typedef struct { + rand int arr[string]; + } associative_struct_t; - // Struct with a multi-dimensional array - typedef struct { - rand int arr[2][3]; - } multi_dim_struct_t; + // Struct with a multi-dimensional array + typedef struct { + rand int arr[2][3]; + } multi_dim_struct_t; - // Struct with a mix of dynamic and unpacked arrays - typedef struct { - rand int mix_arr[3][]; - } mixed_struct_t; + // Struct with a mix of dynamic and unpacked arrays + typedef struct { + rand int mix_arr[3][]; + } mixed_struct_t; - rand unpacked_struct_t s1; - rand dynamic_struct_t s2; - rand queue_struct_t s3; - rand associative_struct_t s4; - rand multi_dim_struct_t s5; - rand mixed_struct_t s6; + rand unpacked_struct_t s1; + rand dynamic_struct_t s2; + rand queue_struct_t s3; + rand associative_struct_t s4; + rand multi_dim_struct_t s5; + rand mixed_struct_t s6; - constraint c_unpacked { - foreach (s1.arr[i]) s1.arr[i] inside {1, 2, 3, 4}; - foreach (s1.arr_3[i]) s1.arr_3[i] inside {11, 22, 33, 44, 55}; - } + constraint c_unpacked { + foreach (s1.arr[i]) s1.arr[i] inside {1, 2, 3, 4}; + foreach (s1.arr_3[i]) s1.arr_3[i] inside {11, 22, 33, 44, 55}; + } - constraint c_dynamic { foreach (s2.arr[i]) s2.arr[i] inside {[10:20]}; } + constraint c_dynamic { foreach (s2.arr[i]) s2.arr[i] inside {[10:20]}; } - constraint c_queue { foreach (s3.arr[i]) s3.arr[i] inside {[100:200]}; } + constraint c_queue { foreach (s3.arr[i]) s3.arr[i] inside {[100:200]}; } - constraint c_assoc { - s4.arr["one"] inside {[10:50]}; - s4.arr["two"] inside {[51:100]}; - s4.arr["three"] inside {[101:150]}; - } + constraint c_assoc { + s4.arr["one"] inside {[10:50]}; + s4.arr["two"] inside {[51:100]}; + s4.arr["three"] inside {[101:150]}; + } - constraint c_multi_dim { foreach (s5.arr[i, j]) s5.arr[i][j] inside {[0:9]}; } + constraint c_multi_dim { foreach (s5.arr[i, j]) s5.arr[i][j] inside {[0:9]}; } - constraint c_mix { - foreach (s6.mix_arr[i, j]) s6.mix_arr[i][j] inside {[50:100]}; - } + constraint c_mix { + foreach (s6.mix_arr[i, j]) s6.mix_arr[i][j] inside {[50:100]}; + } - function new(); + function new(); - s1.arr = '{1, 2, 3}; - s1.arr_3 = '{1, 2, 3}; - s1.arr_4 = '{0, 2, 3, 4}; - s2.arr = new[3]; - foreach(s2.arr[i]) begin - s2.arr[i] = 'h0 + i; - end - s3.arr.push_back(100); - s3.arr.push_back(200); - s3.arr.push_back(300); - s4.arr["one"] = 1000; - s4.arr["two"] = 2000; - s4.arr["three"] = 3000; - s5.arr = '{ '{default:0}, '{default:0} }; - foreach (s6.mix_arr[i]) begin - s6.mix_arr[i] = new[i + 1]; - end + s1.arr = '{1, 2, 3}; + s1.arr_3 = '{1, 2, 3}; + s1.arr_4 = '{0, 2, 3, 4}; + s2.arr = new[3]; + foreach(s2.arr[i]) begin + s2.arr[i] = 'h0 + i; + end + s3.arr.push_back(100); + s3.arr.push_back(200); + s3.arr.push_back(300); + s4.arr["one"] = 1000; + s4.arr["two"] = 2000; + s4.arr["three"] = 3000; + s5.arr = '{ '{default:0}, '{default:0} }; + foreach (s6.mix_arr[i]) begin + s6.mix_arr[i] = new[i + 1]; + end - endfunction + endfunction - function void print(); + function void print(); - foreach (s1.arr[i]) $display("s1.arr[%0d] = %0d", i, s1.arr[i]); - foreach (s1.arr_3[i]) $display("s1.arr_3[%0d] = %0d", i, s1.arr_3[i]); - foreach (s1.arr_4[i]) $display("s1.arr_4[%0d] = %0d", i, s1.arr_4[i]); - foreach (s2.arr[i]) $display("s2.arr[%0d] = %0d", i, s2.arr[i]); - foreach (s3.arr[i]) $display("s3.arr[%0d] = %0d", i, s3.arr[i]); - foreach (s4.arr[i]) $display("s4.arr[\"%s\"] = %0d", i, s4.arr[i]); - foreach (s5.arr[i, j]) $display("s5.arr[%0d][%0d] = %0d", i, j, s5.arr[i][j]); - foreach (s6.mix_arr[i, j]) $display("s6.mix_arr[%0d][%0d] = %0d", i, j, s6.mix_arr[i][j]); + foreach (s1.arr[i]) $display("s1.arr[%0d] = %0d", i, s1.arr[i]); + foreach (s1.arr_3[i]) $display("s1.arr_3[%0d] = %0d", i, s1.arr_3[i]); + foreach (s1.arr_4[i]) $display("s1.arr_4[%0d] = %0d", i, s1.arr_4[i]); + foreach (s2.arr[i]) $display("s2.arr[%0d] = %0d", i, s2.arr[i]); + foreach (s3.arr[i]) $display("s3.arr[%0d] = %0d", i, s3.arr[i]); + foreach (s4.arr[i]) $display("s4.arr[\"%s\"] = %0d", i, s4.arr[i]); + foreach (s5.arr[i, j]) $display("s5.arr[%0d][%0d] = %0d", i, j, s5.arr[i][j]); + foreach (s6.mix_arr[i, j]) $display("s6.mix_arr[%0d][%0d] = %0d", i, j, s6.mix_arr[i][j]); - endfunction + endfunction - // Self-test function to verify constraints - function void self_test(); + // Self-test function to verify constraints + function void self_test(); - foreach (s1.arr[i]) if (!(s1.arr[i] inside {1, 2, 3, 4})) $stop; - foreach (s1.arr_3[i]) if (!(s1.arr_3[i] inside {11, 22, 33, 44, 55})) $stop; - // Note: s1.arr_4[0] is not rand - if ((s1.arr_4[0] != 0) || (s1.arr_4[1] != 2) || (s1.arr_4[2] != 3) || (s1.arr_4[3] != 4)) $stop; - foreach (s2.arr[i]) if (!(s2.arr[i] inside {[10:20]})) $stop; - foreach (s3.arr[i]) if (!(s3.arr[i] inside {[100:200]})) $stop; - if (!(s4.arr["one"] inside {[10:50]})) $stop; - if (!(s4.arr["two"] inside {[51:100]})) $stop; - if (!(s4.arr["three"] inside {[101:150]})) $stop; - foreach (s5.arr[i, j]) if (!(s5.arr[i][j] inside {[0:9]})) $stop; - foreach (s6.mix_arr[i]) if (s6.mix_arr[i].size() == 0) $stop; - foreach (s6.mix_arr[i, j]) if (!(s6.mix_arr[i][j] inside {[50:100]})) $stop; + foreach (s1.arr[i]) if (!(s1.arr[i] inside {1, 2, 3, 4})) $stop; + foreach (s1.arr_3[i]) if (!(s1.arr_3[i] inside {11, 22, 33, 44, 55})) $stop; + // Note: s1.arr_4[0] is not rand + if ((s1.arr_4[0] != 0) || (s1.arr_4[1] != 2) || (s1.arr_4[2] != 3) || (s1.arr_4[3] != 4)) $stop; + foreach (s2.arr[i]) if (!(s2.arr[i] inside {[10:20]})) $stop; + foreach (s3.arr[i]) if (!(s3.arr[i] inside {[100:200]})) $stop; + if (!(s4.arr["one"] inside {[10:50]})) $stop; + if (!(s4.arr["two"] inside {[51:100]})) $stop; + if (!(s4.arr["three"] inside {[101:150]})) $stop; + foreach (s5.arr[i, j]) if (!(s5.arr[i][j] inside {[0:9]})) $stop; + foreach (s6.mix_arr[i]) if (s6.mix_arr[i].size() == 0) $stop; + foreach (s6.mix_arr[i, j]) if (!(s6.mix_arr[i][j] inside {[50:100]})) $stop; - endfunction - /* verilator lint_off SIDEEFFECT */ + endfunction + /* verilator lint_off SIDEEFFECT */ endclass class StructArray; - /* verilator lint_off WIDTHTRUNC */ - typedef struct { - rand int arr[3]; // static unpacked array - rand int a; - rand bit [3:0] b; - bit c; - } struct_t; + /* verilator lint_off WIDTHTRUNC */ + typedef struct { + rand int arr[3]; // static unpacked array + rand int a; + rand bit [3:0] b; + bit c; + } struct_t; - rand struct_t s_arr[2]; - rand struct_t s_2d_arr[2][3]; - rand struct_t s_dyn_arr[]; - rand struct_t s_que_arr[$]; - rand struct_t s_assoc_arr[string]; - rand struct_t s_assoc_arr_2[bit[5:0]]; + rand struct_t s_arr[2]; + rand struct_t s_2d_arr[2][3]; + rand struct_t s_dyn_arr[]; + rand struct_t s_que_arr[$]; + rand struct_t s_assoc_arr[string]; + rand struct_t s_assoc_arr_2[bit[5:0]]; - constraint c_arr { - foreach (s_arr[i]) - foreach (s_arr[i].arr[j]) - s_arr[i].arr[j] inside {[0:9]}; - foreach (s_2d_arr[i, j]) - foreach (s_2d_arr[i][j].arr[k]) - s_2d_arr[i][j].arr[k] inside {[9:19]}; - foreach (s_dyn_arr[i]) - foreach (s_dyn_arr[i].arr[j]) - s_dyn_arr[i].arr[j] inside {[19:29]}; - foreach (s_que_arr[i]) - foreach (s_que_arr[i].arr[j]) - s_que_arr[i].arr[j] inside {[29:39]}; - foreach (s_assoc_arr[i]) - foreach (s_assoc_arr[i].arr[j]) - s_assoc_arr[i].arr[j] inside {[39:49]}; - foreach (s_assoc_arr_2[i]) - foreach (s_assoc_arr_2[i].arr[j]) - s_assoc_arr_2[i].arr[j] inside {[49:59]}; - } + constraint c_arr { + foreach (s_arr[i]) + foreach (s_arr[i].arr[j]) + s_arr[i].arr[j] inside {[0:9]}; + foreach (s_2d_arr[i, j]) + foreach (s_2d_arr[i][j].arr[k]) + s_2d_arr[i][j].arr[k] inside {[9:19]}; + foreach (s_dyn_arr[i]) + foreach (s_dyn_arr[i].arr[j]) + s_dyn_arr[i].arr[j] inside {[19:29]}; + foreach (s_que_arr[i]) + foreach (s_que_arr[i].arr[j]) + s_que_arr[i].arr[j] inside {[29:39]}; + foreach (s_assoc_arr[i]) + foreach (s_assoc_arr[i].arr[j]) + s_assoc_arr[i].arr[j] inside {[39:49]}; + foreach (s_assoc_arr_2[i]) + foreach (s_assoc_arr_2[i].arr[j]) + s_assoc_arr_2[i].arr[j] inside {[49:59]}; + } - constraint c_others { - foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; - foreach (s_arr[i]) s_arr[i].b inside {[0:7]}; + constraint c_others { + foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; + foreach (s_arr[i]) s_arr[i].b inside {[0:7]}; - foreach (s_2d_arr[i, j]) s_2d_arr[i][j].a inside {[50:60]}; + foreach (s_2d_arr[i, j]) s_2d_arr[i][j].a inside {[50:60]}; - foreach (s_dyn_arr[i]) s_dyn_arr[i].a inside {[60:70]}; + foreach (s_dyn_arr[i]) s_dyn_arr[i].a inside {[60:70]}; - foreach (s_que_arr[i]) s_que_arr[i].a inside {[70:80]}; + foreach (s_que_arr[i]) s_que_arr[i].a inside {[70:80]}; - foreach (s_assoc_arr[i]) s_assoc_arr[i].a inside {[80:90]}; + foreach (s_assoc_arr[i]) s_assoc_arr[i].a inside {[80:90]}; - foreach (s_assoc_arr_2[i]) s_assoc_arr_2[i].a inside {[90:100]}; - } + foreach (s_assoc_arr_2[i]) s_assoc_arr_2[i].a inside {[90:100]}; + } - function new(); + function new(); - foreach (s_arr[i]) begin - foreach (s_arr[i].arr[j]) - s_arr[i].arr[j] = j; - s_arr[i].a = 40 + i; - s_arr[i].b = i; - s_arr[i].c = 0; - end + foreach (s_arr[i]) begin + foreach (s_arr[i].arr[j]) + s_arr[i].arr[j] = j; + s_arr[i].a = 40 + i; + s_arr[i].b = i; + s_arr[i].c = 0; + end - foreach (s_2d_arr[i, j]) begin - foreach (s_2d_arr[i][j].arr[k]) - s_2d_arr[i][j].arr[k] = k + 10; - s_2d_arr[i][j].a = 50 + i + j; - s_2d_arr[i][j].b = i + j; - s_2d_arr[i][j].c = 0; - end + foreach (s_2d_arr[i, j]) begin + foreach (s_2d_arr[i][j].arr[k]) + s_2d_arr[i][j].arr[k] = k + 10; + s_2d_arr[i][j].a = 50 + i + j; + s_2d_arr[i][j].b = i + j; + s_2d_arr[i][j].c = 0; + end - foreach (s_dyn_arr[i]) begin - s_dyn_arr = new[3]; - foreach (s_dyn_arr[i].arr[j]) - s_dyn_arr[i].arr[j] = j + 20; - s_dyn_arr[i].a = 60 + i; - s_dyn_arr[i].b = i; - s_dyn_arr[i].c = 0; - end + foreach (s_dyn_arr[i]) begin + s_dyn_arr = new[3]; + foreach (s_dyn_arr[i].arr[j]) + s_dyn_arr[i].arr[j] = j + 20; + s_dyn_arr[i].a = 60 + i; + s_dyn_arr[i].b = i; + s_dyn_arr[i].c = 0; + end - for (int i = 0; i < 3; i++) begin - s_que_arr.push_back('{arr: '{30, 31, 32}, a: 70 + i, b: i, c: 0}); - end + for (int i = 0; i < 3; i++) begin + s_que_arr.push_back('{arr: '{30, 31, 32}, a: 70 + i, b: i, c: 0}); + end - // Associative array with string index - foreach (s_assoc_arr["x"].arr[j]) - s_assoc_arr["x"].arr[j] = j + 40; - foreach (s_assoc_arr["y"].arr[j]) - s_assoc_arr["y"].arr[j] = j + 50; - foreach (s_assoc_arr["long_string_index"].arr[j]) - s_assoc_arr["long_string_index"].arr[j] = j + 60; - s_assoc_arr["x"].a = 80; - s_assoc_arr["x"].b = 0; - s_assoc_arr["x"].c = 0; - s_assoc_arr["y"].a = 90; - s_assoc_arr["y"].b = 1; - s_assoc_arr["y"].c = 0; - s_assoc_arr["long_string_index"].a = 100; - s_assoc_arr["long_string_index"].b = 2; - s_assoc_arr["long_string_index"].c = 0; + // Associative array with string index + foreach (s_assoc_arr["x"].arr[j]) + s_assoc_arr["x"].arr[j] = j + 40; + foreach (s_assoc_arr["y"].arr[j]) + s_assoc_arr["y"].arr[j] = j + 50; + foreach (s_assoc_arr["long_string_index"].arr[j]) + s_assoc_arr["long_string_index"].arr[j] = j + 60; + s_assoc_arr["x"].a = 80; + s_assoc_arr["x"].b = 0; + s_assoc_arr["x"].c = 0; + s_assoc_arr["y"].a = 90; + s_assoc_arr["y"].b = 1; + s_assoc_arr["y"].c = 0; + s_assoc_arr["long_string_index"].a = 100; + s_assoc_arr["long_string_index"].b = 2; + s_assoc_arr["long_string_index"].c = 0; - foreach (s_assoc_arr_2[6'd30].arr[j]) - s_assoc_arr_2[6'd30].arr[j] = j + 70; - foreach (s_assoc_arr_2[6'd7].arr[j]) - s_assoc_arr_2[6'd7].arr[j] = j + 80; - s_assoc_arr_2[6'd30].a = 90; - s_assoc_arr_2[6'd30].b = 0; - s_assoc_arr_2[6'd30].c = 0; - s_assoc_arr_2[6'd7].a = 100; - s_assoc_arr_2[6'd7].b = 1; - s_assoc_arr_2[6'd7].c = 0; + foreach (s_assoc_arr_2[6'd30].arr[j]) + s_assoc_arr_2[6'd30].arr[j] = j + 70; + foreach (s_assoc_arr_2[6'd7].arr[j]) + s_assoc_arr_2[6'd7].arr[j] = j + 80; + s_assoc_arr_2[6'd30].a = 90; + s_assoc_arr_2[6'd30].b = 0; + s_assoc_arr_2[6'd30].c = 0; + s_assoc_arr_2[6'd7].a = 100; + s_assoc_arr_2[6'd7].b = 1; + s_assoc_arr_2[6'd7].c = 0; - endfunction + endfunction - function void print(); + function void print(); - foreach (s_arr[i]) begin - foreach (s_arr[i].arr[j]) - $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); - $display("s_arr[%0d].a = %0d", i, s_arr[i].a); - $display("s_arr[%0d].b = %0d", i, s_arr[i].b); - $display("s_arr[%0d].c = %0d", i, s_arr[i].c); - end + foreach (s_arr[i]) begin + foreach (s_arr[i].arr[j]) + $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); + $display("s_arr[%0d].a = %0d", i, s_arr[i].a); + $display("s_arr[%0d].b = %0d", i, s_arr[i].b); + $display("s_arr[%0d].c = %0d", i, s_arr[i].c); + end - foreach (s_2d_arr[i, j]) begin - foreach (s_2d_arr[i][j].arr[k]) - $display("s_2d_arr[%0d][%0d].arr[%0d] = %0d", i, j, k, s_2d_arr[i][j].arr[k]); - $display("s_2d_arr[%0d][%0d].a = %0d", i, j, s_2d_arr[i][j].a); - $display("s_2d_arr[%0d][%0d].b = %0d", i, j, s_2d_arr[i][j].b); - $display("s_2d_arr[%0d][%0d].c = %0d", i, j, s_2d_arr[i][j].c); - end + foreach (s_2d_arr[i, j]) begin + foreach (s_2d_arr[i][j].arr[k]) + $display("s_2d_arr[%0d][%0d].arr[%0d] = %0d", i, j, k, s_2d_arr[i][j].arr[k]); + $display("s_2d_arr[%0d][%0d].a = %0d", i, j, s_2d_arr[i][j].a); + $display("s_2d_arr[%0d][%0d].b = %0d", i, j, s_2d_arr[i][j].b); + $display("s_2d_arr[%0d][%0d].c = %0d", i, j, s_2d_arr[i][j].c); + end - foreach (s_dyn_arr[i]) begin - foreach (s_dyn_arr[i].arr[j]) - $display("s_dyn_arr[%0d].arr[%0d] = %0d", i, j, s_dyn_arr[i].arr[j]); - $display("s_dyn_arr[%0d].a = %0d", i, s_dyn_arr[i].a); - $display("s_dyn_arr[%0d].b = %0d", i, s_dyn_arr[i].b); - $display("s_dyn_arr[%0d].c = %0d", i, s_dyn_arr[i].c); - end + foreach (s_dyn_arr[i]) begin + foreach (s_dyn_arr[i].arr[j]) + $display("s_dyn_arr[%0d].arr[%0d] = %0d", i, j, s_dyn_arr[i].arr[j]); + $display("s_dyn_arr[%0d].a = %0d", i, s_dyn_arr[i].a); + $display("s_dyn_arr[%0d].b = %0d", i, s_dyn_arr[i].b); + $display("s_dyn_arr[%0d].c = %0d", i, s_dyn_arr[i].c); + end - foreach (s_que_arr[i]) begin - foreach (s_que_arr[i].arr[j]) - $display("s_que_arr[%0d].arr[%0d] = %0d", i, j, s_que_arr[i].arr[j]); - $display("s_que_arr[%0d].a = %0d", i, s_que_arr[i].a); - $display("s_que_arr[%0d].b = %0d", i, s_que_arr[i].b); - $display("s_que_arr[%0d].c = %0d", i, s_que_arr[i].c); - end + foreach (s_que_arr[i]) begin + foreach (s_que_arr[i].arr[j]) + $display("s_que_arr[%0d].arr[%0d] = %0d", i, j, s_que_arr[i].arr[j]); + $display("s_que_arr[%0d].a = %0d", i, s_que_arr[i].a); + $display("s_que_arr[%0d].b = %0d", i, s_que_arr[i].b); + $display("s_que_arr[%0d].c = %0d", i, s_que_arr[i].c); + end - foreach (s_assoc_arr["x"].arr[j]) - $display("s_assoc_arr[x].arr[%0d] = %0d", j, s_assoc_arr["x"].arr[j]); - $display("s_assoc_arr[x].a = %0d", s_assoc_arr["x"].a); - $display("s_assoc_arr[x].b = %0d", s_assoc_arr["x"].b); - $display("s_assoc_arr[x].c = %0d", s_assoc_arr["x"].c); - foreach (s_assoc_arr["y"].arr[j]) - $display("s_assoc_arr[y].arr[%0d] = %0d", j, s_assoc_arr["y"].arr[j]); - $display("s_assoc_arr[y].a = %0d", s_assoc_arr["y"].a); - $display("s_assoc_arr[y].b = %0d", s_assoc_arr["y"].b); - $display("s_assoc_arr[y].c = %0d", s_assoc_arr["y"].c); - foreach (s_assoc_arr["long_string_index"].arr[j]) - $display("s_assoc_arr[long_string_index].arr[%0d] = %0d", j, s_assoc_arr["long_string_index"].arr[j]); - $display("s_assoc_arr[long_string_index].a = %0d", s_assoc_arr["long_string_index"].a); - $display("s_assoc_arr[long_string_index].b = %0d", s_assoc_arr["long_string_index"].b); - $display("s_assoc_arr[long_string_index].c = %0d", s_assoc_arr["long_string_index"].c); + foreach (s_assoc_arr["x"].arr[j]) + $display("s_assoc_arr[x].arr[%0d] = %0d", j, s_assoc_arr["x"].arr[j]); + $display("s_assoc_arr[x].a = %0d", s_assoc_arr["x"].a); + $display("s_assoc_arr[x].b = %0d", s_assoc_arr["x"].b); + $display("s_assoc_arr[x].c = %0d", s_assoc_arr["x"].c); + foreach (s_assoc_arr["y"].arr[j]) + $display("s_assoc_arr[y].arr[%0d] = %0d", j, s_assoc_arr["y"].arr[j]); + $display("s_assoc_arr[y].a = %0d", s_assoc_arr["y"].a); + $display("s_assoc_arr[y].b = %0d", s_assoc_arr["y"].b); + $display("s_assoc_arr[y].c = %0d", s_assoc_arr["y"].c); + foreach (s_assoc_arr["long_string_index"].arr[j]) + $display("s_assoc_arr[long_string_index].arr[%0d] = %0d", j, s_assoc_arr["long_string_index"].arr[j]); + $display("s_assoc_arr[long_string_index].a = %0d", s_assoc_arr["long_string_index"].a); + $display("s_assoc_arr[long_string_index].b = %0d", s_assoc_arr["long_string_index"].b); + $display("s_assoc_arr[long_string_index].c = %0d", s_assoc_arr["long_string_index"].c); - foreach (s_assoc_arr_2[6'd30].arr[j]) - $display("s_assoc_arr_2[30].arr[%0d] = %0d", j, s_assoc_arr_2[6'd30].arr[j]); - $display("s_assoc_arr_2[30].a = %0d", s_assoc_arr_2[6'd30].a); - $display("s_assoc_arr_2[30].b = %0d", s_assoc_arr_2[6'd30].b); - $display("s_assoc_arr_2[30].c = %0d", s_assoc_arr_2[6'd30].c); - foreach (s_assoc_arr_2[6'd7].arr[j]) - $display("s_assoc_arr_2[7].arr[%0d] = %0d", j, s_assoc_arr_2[6'd7].arr[j]); - $display("s_assoc_arr_2[7].a = %0d", s_assoc_arr_2[6'd7].a); - $display("s_assoc_arr_2[7].b = %0d", s_assoc_arr_2[6'd7].b); - $display("s_assoc_arr_2[7].c = %0d", s_assoc_arr_2[6'd7].c); + foreach (s_assoc_arr_2[6'd30].arr[j]) + $display("s_assoc_arr_2[30].arr[%0d] = %0d", j, s_assoc_arr_2[6'd30].arr[j]); + $display("s_assoc_arr_2[30].a = %0d", s_assoc_arr_2[6'd30].a); + $display("s_assoc_arr_2[30].b = %0d", s_assoc_arr_2[6'd30].b); + $display("s_assoc_arr_2[30].c = %0d", s_assoc_arr_2[6'd30].c); + foreach (s_assoc_arr_2[6'd7].arr[j]) + $display("s_assoc_arr_2[7].arr[%0d] = %0d", j, s_assoc_arr_2[6'd7].arr[j]); + $display("s_assoc_arr_2[7].a = %0d", s_assoc_arr_2[6'd7].a); + $display("s_assoc_arr_2[7].b = %0d", s_assoc_arr_2[6'd7].b); + $display("s_assoc_arr_2[7].c = %0d", s_assoc_arr_2[6'd7].c); - endfunction + endfunction - function void self_test(); + function void self_test(); - foreach (s_arr[i]) begin - foreach (s_arr[i].arr[j]) - if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; - if (!(s_arr[i].a inside {[40:50]})) $stop; - end + foreach (s_arr[i]) begin + foreach (s_arr[i].arr[j]) + if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; + if (!(s_arr[i].a inside {[40:50]})) $stop; + end - foreach (s_2d_arr[i, j]) begin - foreach (s_2d_arr[i][j].arr[k]) - if (!(s_2d_arr[i][j].arr[k] inside {[9:19]})) $stop; - if (!(s_2d_arr[i][j].a inside {[50:60]})) $stop; - end + foreach (s_2d_arr[i, j]) begin + foreach (s_2d_arr[i][j].arr[k]) + if (!(s_2d_arr[i][j].arr[k] inside {[9:19]})) $stop; + if (!(s_2d_arr[i][j].a inside {[50:60]})) $stop; + end - foreach (s_dyn_arr[i]) begin - foreach (s_dyn_arr[i].arr[j]) - if (!(s_dyn_arr[i].arr[j] inside {[19:29]})) $stop; - if (!(s_dyn_arr[i].a inside {[60:70]})) $stop; - end + foreach (s_dyn_arr[i]) begin + foreach (s_dyn_arr[i].arr[j]) + if (!(s_dyn_arr[i].arr[j] inside {[19:29]})) $stop; + if (!(s_dyn_arr[i].a inside {[60:70]})) $stop; + end - foreach (s_que_arr[i]) begin - foreach (s_que_arr[i].arr[j]) - if (!(s_que_arr[i].arr[j] inside {[29:39]})) $stop; - if (!(s_que_arr[i].a inside {[70:80]})) $stop; - end + foreach (s_que_arr[i]) begin + foreach (s_que_arr[i].arr[j]) + if (!(s_que_arr[i].arr[j] inside {[29:39]})) $stop; + if (!(s_que_arr[i].a inside {[70:80]})) $stop; + end - foreach (s_assoc_arr["x"].arr[j]) - if (!(s_assoc_arr["x"].arr[j] inside {[39:49]})) $stop; - if (!(s_assoc_arr["x"].a inside {[80:90]})) $stop; - foreach (s_assoc_arr["y"].arr[j]) - if (!(s_assoc_arr["y"].arr[j] inside {[39:49]})) $stop; - if (!(s_assoc_arr["y"].a inside {[80:90]})) $stop; - foreach (s_assoc_arr["long_string_index"].arr[j]) - if (!(s_assoc_arr["long_string_index"].arr[j] inside {[39:49]})) $stop; - if (!(s_assoc_arr["long_string_index"].a inside {[80:90]})) $stop; + foreach (s_assoc_arr["x"].arr[j]) + if (!(s_assoc_arr["x"].arr[j] inside {[39:49]})) $stop; + if (!(s_assoc_arr["x"].a inside {[80:90]})) $stop; + foreach (s_assoc_arr["y"].arr[j]) + if (!(s_assoc_arr["y"].arr[j] inside {[39:49]})) $stop; + if (!(s_assoc_arr["y"].a inside {[80:90]})) $stop; + foreach (s_assoc_arr["long_string_index"].arr[j]) + if (!(s_assoc_arr["long_string_index"].arr[j] inside {[39:49]})) $stop; + if (!(s_assoc_arr["long_string_index"].a inside {[80:90]})) $stop; - foreach (s_assoc_arr_2[6'd30].arr[j]) - if (!(s_assoc_arr_2[6'd30].arr[j] inside {[49:59]})) $stop; - if (!(s_assoc_arr_2[6'd30].a inside {[90:100]})) $stop; - foreach (s_assoc_arr_2[6'd7].arr[j]) - if (!(s_assoc_arr_2[6'd7].arr[j] inside {[49:59]})) $stop; - if (!(s_assoc_arr_2[6'd7].a inside {[90:100]})) $stop; + foreach (s_assoc_arr_2[6'd30].arr[j]) + if (!(s_assoc_arr_2[6'd30].arr[j] inside {[49:59]})) $stop; + if (!(s_assoc_arr_2[6'd30].a inside {[90:100]})) $stop; + foreach (s_assoc_arr_2[6'd7].arr[j]) + if (!(s_assoc_arr_2[6'd7].arr[j] inside {[49:59]})) $stop; + if (!(s_assoc_arr_2[6'd7].a inside {[90:100]})) $stop; - endfunction + endfunction - /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHTRUNC */ endclass class MixedStructure; - /* verilator lint_off WIDTHTRUNC */ - typedef struct { - rand int arr[3]; // static unpacked array - rand int dyn[]; // dynamic array - rand int que[$]; // queue - rand int assoc[string]; // associative array with string key - rand int a; - rand bit [3:0] b; - bit c; - } struct_t; + /* verilator lint_off WIDTHTRUNC */ + typedef struct { + rand int arr[3]; // static unpacked array + rand int dyn[]; // dynamic array + rand int que[$]; // queue + rand int assoc[string]; // associative array with string key + rand int a; + rand bit [3:0] b; + bit c; + } struct_t; - rand struct_t s_arr[2]; + rand struct_t s_arr[2]; - constraint c_static { - foreach (s_arr[i]) - foreach (s_arr[i].arr[j]) - s_arr[i].arr[j] inside {[0:9]}; + constraint c_static { + foreach (s_arr[i]) + foreach (s_arr[i].arr[j]) + s_arr[i].arr[j] inside {[0:9]}; + } + + constraint c_dyn { + foreach (s_arr[i]) + foreach (s_arr[i].dyn[j]) + s_arr[i].dyn[j] inside {[10:19]}; + } + + constraint c_queue { + foreach (s_arr[i]) + foreach (s_arr[i].que[j]) + s_arr[i].que[j] inside {[20:29]}; + } + + constraint c_assoc { + foreach (s_arr[i]) { + s_arr[i].assoc["x"] inside {[30:39]}; + s_arr[i].assoc["y"] inside {[30:39]}; } + } - constraint c_dyn { - foreach (s_arr[i]) - foreach (s_arr[i].dyn[j]) - s_arr[i].dyn[j] inside {[10:19]}; - } + constraint c_other { + foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; + } - constraint c_queue { - foreach (s_arr[i]) - foreach (s_arr[i].que[j]) - s_arr[i].que[j] inside {[20:29]}; - } + function new(); - constraint c_assoc { - foreach (s_arr[i]) { - s_arr[i].assoc["x"] inside {[30:39]}; - s_arr[i].assoc["y"] inside {[30:39]}; - } - } + foreach (s_arr[i]) begin + s_arr[i].dyn = new[2]; + s_arr[i].que = {0, 0}; + s_arr[i].assoc = '{"x": 0, "y": 0}; - constraint c_other { - foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; - } + foreach (s_arr[i].arr[j]) + s_arr[i].arr[j] = j; + foreach (s_arr[i].dyn[j]) + s_arr[i].dyn[j] = 10 + j; + foreach (s_arr[i].que[j]) + s_arr[i].que[j] = 20 + j; - function new(); + s_arr[i].assoc["x"] = i + 30; + s_arr[i].assoc["y"] = i + 31; + s_arr[i].a = 40 + i; + s_arr[i].b = i; + s_arr[i].c = i; + end - foreach (s_arr[i]) begin - s_arr[i].dyn = new[2]; - s_arr[i].que = {0, 0}; - s_arr[i].assoc = '{"x": 0, "y": 0}; + endfunction - foreach (s_arr[i].arr[j]) - s_arr[i].arr[j] = j; - foreach (s_arr[i].dyn[j]) - s_arr[i].dyn[j] = 10 + j; - foreach (s_arr[i].que[j]) - s_arr[i].que[j] = 20 + j; + function void print(); - s_arr[i].assoc["x"] = i + 30; - s_arr[i].assoc["y"] = i + 31; - s_arr[i].a = 40 + i; - s_arr[i].b = i; - s_arr[i].c = i; - end + foreach (s_arr[i]) begin + foreach (s_arr[i].arr[j]) + $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); + foreach (s_arr[i].dyn[j]) + $display("s_arr[%0d].dyn[%0d] = %0d", i, j, s_arr[i].dyn[j]); + foreach (s_arr[i].que[j]) + $display("s_arr[%0d].que[%0d] = %0d", i, j, s_arr[i].que[j]); - endfunction + $display("s_arr[%0d].assoc[\"x\"] = %0d", i, s_arr[i].assoc["x"]); + $display("s_arr[%0d].assoc[\"y\"] = %0d", i, s_arr[i].assoc["y"]); + $display("s_arr[%0d].a = %0d", i, s_arr[i].a); + $display("s_arr[%0d].b = %0d", i, s_arr[i].b); + $display("s_arr[%0d].c = %0d", i, s_arr[i].c); + end - function void print(); + endfunction - foreach (s_arr[i]) begin - foreach (s_arr[i].arr[j]) - $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); - foreach (s_arr[i].dyn[j]) - $display("s_arr[%0d].dyn[%0d] = %0d", i, j, s_arr[i].dyn[j]); - foreach (s_arr[i].que[j]) - $display("s_arr[%0d].que[%0d] = %0d", i, j, s_arr[i].que[j]); + function void self_test(); - $display("s_arr[%0d].assoc[\"x\"] = %0d", i, s_arr[i].assoc["x"]); - $display("s_arr[%0d].assoc[\"y\"] = %0d", i, s_arr[i].assoc["y"]); - $display("s_arr[%0d].a = %0d", i, s_arr[i].a); - $display("s_arr[%0d].b = %0d", i, s_arr[i].b); - $display("s_arr[%0d].c = %0d", i, s_arr[i].c); - end + foreach (s_arr[i]) begin + foreach (s_arr[i].arr[j]) + if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; + foreach (s_arr[i].dyn[j]) + if (!(s_arr[i].dyn[j] inside {[10:19]})) $stop; + foreach (s_arr[i].que[j]) + if (!(s_arr[i].que[j] inside {[20:29]})) $stop; + if (!(s_arr[i].assoc.exists("x") && s_arr[i].assoc["x"] inside {[30:39]})) $stop; + if (!(s_arr[i].assoc.exists("y") && s_arr[i].assoc["y"] inside {[30:39]})) $stop; + if (!(s_arr[i].a inside {[40:50]})) $stop; + if (i == 0 && s_arr[i].c != 0) $stop; + if (i == 1 && s_arr[i].c != 1) $stop; + end - endfunction + endfunction - function void self_test(); - - foreach (s_arr[i]) begin - foreach (s_arr[i].arr[j]) - if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; - foreach (s_arr[i].dyn[j]) - if (!(s_arr[i].dyn[j] inside {[10:19]})) $stop; - foreach (s_arr[i].que[j]) - if (!(s_arr[i].que[j] inside {[20:29]})) $stop; - if (!(s_arr[i].assoc.exists("x") && s_arr[i].assoc["x"] inside {[30:39]})) $stop; - if (!(s_arr[i].assoc.exists("y") && s_arr[i].assoc["y"] inside {[30:39]})) $stop; - if (!(s_arr[i].a inside {[40:50]})) $stop; - if (i == 0 && s_arr[i].c != 0) $stop; - if (i == 1 && s_arr[i].c != 1) $stop; - end - - endfunction - - /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHTRUNC */ endclass module t_constraint_struct_complex; - int success; - ArrayStruct as_c; - StructArray sa_c; - MixedStructure mixed_c; + int success; + ArrayStruct as_c; + StructArray sa_c; + MixedStructure mixed_c; - initial begin - as_c = new(); - sa_c = new(); - mixed_c = new(); + initial begin + as_c = new(); + sa_c = new(); + mixed_c = new(); - success = as_c.randomize(); - if (success != 1) $stop; - as_c.self_test(); - // as_c.print(); - // $display(" ArrayStruct passed! \n"); + success = as_c.randomize(); + if (success != 1) $stop; + as_c.self_test(); + // as_c.print(); + // $display(" ArrayStruct passed! \n"); - success = sa_c.randomize(); - if (success != 1) $stop; - sa_c.self_test(); - // sa_c.print(); - // $display(" StructArray passed! \n"); + success = sa_c.randomize(); + if (success != 1) $stop; + sa_c.self_test(); + // sa_c.print(); + // $display(" StructArray passed! \n"); - success = mixed_c.randomize(); - if (success != 1) $stop; - mixed_c.self_test(); - // mixed_c.print(); - // $display(" MixedStructure passed! \n"); + success = mixed_c.randomize(); + if (success != 1) $stop; + mixed_c.self_test(); + // mixed_c.print(); + // $display(" MixedStructure passed! \n"); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_unpacked_array.v b/test_regress/t/t_constraint_unpacked_array.v index 9ee4ae6c8..9671d31e6 100644 --- a/test_regress/t/t_constraint_unpacked_array.v +++ b/test_regress/t/t_constraint_unpacked_array.v @@ -4,21 +4,23 @@ // SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define check_rand(cl, field) \ begin \ - longint prev_result; \ - int ok = 0; \ - void'(cl.randomize()); \ - prev_result = longint'(field); \ - repeat(9) begin \ - longint result; \ - void'(cl.randomize()); \ - result = longint'(field); \ - if (result != prev_result) ok = 1; \ - prev_result = result; \ - end \ - if (ok != 1) $stop; \ + longint prev_result; \ + int ok = 0; \ + void'(cl.randomize()); \ + prev_result = longint'(field); \ + repeat(9) begin \ + longint result; \ + void'(cl.randomize()); \ + result = longint'(field); \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ end +// verilog_format: on class con_rand_1d_array_test; rand bit [7:0] data[5]; diff --git a/test_regress/t/t_cover_const_compare.v b/test_regress/t/t_cover_const_compare.v index 9b380cd25..41807e46c 100644 --- a/test_regress/t/t_cover_const_compare.v +++ b/test_regress/t/t_cover_const_compare.v @@ -4,29 +4,27 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; initial cyc=1; + wire a = cyc[0]; + wire b = cyc[0]; - wire a = cyc[0]; - wire b = cyc[0]; - - always @ (posedge clk) begin - cyc <= cyc + 1; - // Before this was optimized, with --coverage-line - // error: self-comparison always evaluates to true [-Werror=tautological-compare] - // if (((1U & vlSelf->t__DOT__cyc) == (1U & vlSelf->t__DOT__cyc))) - if (a != cyc[0]) $stop; // Becomes cyc == cyc after substitution - if (b != cyc[0]) $stop; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + // Before this was optimized, with --coverage-line + // error: self-comparison always evaluates to true [-Werror=tautological-compare] + // if (((1U & vlSelf->t__DOT__cyc) == (1U & vlSelf->t__DOT__cyc))) + if (a != cyc[0]) $stop; // Becomes cyc == cyc after substitution + if (b != cyc[0]) $stop; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_cover_expr.out b/test_regress/t/t_cover_expr.out index d82c98c8d..9acf096c7 100644 --- a/test_regress/t/t_cover_expr.out +++ b/test_regress/t/t_cover_expr.out @@ -6,144 +6,141 @@ // SPDX-License-Identifier: CC0-1.0 class cls; - rand int x; + rand int x; endclass - module t (/*AUTOARG*/ - // Inputs - clk - ); + module t ( + input clk + ); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; - initial cyc=1; + logic [63:32] cyc2; + always_comb cyc2 = cyc; - logic [63:32] cyc2; - always_comb cyc2 = cyc; + integer some_int; + integer other_int; + logic some_bool; - integer some_int; - integer other_int; - logic some_bool; + wire t1 = cyc[0]; + wire t2 = cyc[1]; + wire t3 = cyc[2]; + wire t4 = cyc[3]; - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; + localparam bit ONE = 1'b1; + localparam bit ZERO = 1'b0; - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; - - function automatic bit invert(bit x); -%000005 return ~x; + function automatic bit invert(bit x); +%000005 return ~x; -000004 point: type=expr comment=(x==0) => 1 hier=top.t -000005 point: type=expr comment=(x==1) => 0 hier=top.t - endfunction + endfunction - function automatic bit and_oper(bit a, bit b); -%000005 return a & b; + function automatic bit and_oper(bit a, bit b); +%000005 return a & b; -000004 point: type=expr comment=(a==0) => 0 hier=top.t -000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t -000005 point: type=expr comment=(b==0) => 0 hier=top.t - endfunction + endfunction - localparam int NUM_INTFS = 4; - intf the_intfs [NUM_INTFS-1:0] (); - genvar intf_i; - for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin - always_comb the_intfs[intf_i].t = cyc[intf_i]; - end + localparam int NUM_INTFS = 4; + intf the_intfs[NUM_INTFS-1:0] (); + genvar intf_i; + for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin + always_comb the_intfs[intf_i].t = cyc[intf_i]; + end - always @ (posedge clk) begin - cyc <= cyc + 1; -%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); + always @(posedge clk) begin + cyc <= cyc + 1; +%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); +%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); +%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000005 if (t3 && (t1 == t2)) $write(""); +%000005 if (t3 && (t1 == t2)) $write(""); -000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); +%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000004 some_int <= (t2 || t3) ? 345 : 567; +%000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000004 point: type=expr comment=(t3==1) => 1 hier=top.t -%000005 some_bool <= t1 && t2; +%000005 some_bool <= t1 && t2; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2) $write(""); +%000005 if (t1 & t2) $write(""); -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); +%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000003 if (t1 ^ t2) $write(""); +%000003 if (t1 ^ t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -%000005 if (~(t1 & t2)) $write(""); +%000005 if (~(t1 & t2)) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 1 hier=top.t -%000004 if (t1 -> t2) $write(""); +%000004 if (t1 -> t2) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000003 if (t1 <-> t2) $write(""); +%000003 if (t1 <-> t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -%000005 if (&cyc[2:0]) $write(""); +%000005 if (&cyc[2:0]) $write(""); -000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t -%000007 if (&cyc[3:2]) $write(""); +%000007 if (&cyc[3:2]) $write(""); -000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t -%000005 if (|cyc[2:0]) $write(""); +%000005 if (|cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -%000002 if (^cyc[2:0]) $write(""); +%000002 if (^cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t @@ -152,87 +149,88 @@ -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -%000005 if (|cyc[2:0] || cyc[3]) $write(""); +%000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t -%000005 if (t1 & t2 & 1'b1) $write(""); +%000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & 1'b0) $write(""); +%000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2 & ONE) $write(""); +%000005 if (t1 & t2 & ONE) $write(""); -000000 point: type=expr comment=(ONE==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & ZERO) $write(""); +%000009 if (t1 & t2 & ZERO) $write(""); -000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 && t2) begin +%000005 if (t1 && t2) begin -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - $write(""); -%000003 end else if (t1 || t2) begin + $write(""); + end +%000003 else if (t1 || t2) begin -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: type=expr comment=(t1==1) => 1 hier=top.t -000002 point: type=expr comment=(t2==1) => 1 hier=top.t - $write(""); - end -%000005 if (invert(t1) && t2) $write(""); + $write(""); + end +%000005 if (invert(t1) && t2) $write(""); -000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t -000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - if (and_oper(t1, t2)) $write(""); -%000005 if (t2 && t3) begin + if (and_oper(t1, t2)) $write(""); +%000005 if (t2 && t3) begin -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -%000001 if (t1 && t2) $write(""); +%000001 if (t1 && t2) $write(""); -000001 point: type=expr comment=(t1==0) => 0 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - if (0 == 1) begin - for (int loop_var = 0; loop_var < 1; loop_var++) begin -%000000 if (cyc[loop_var] && t2) $write(""); + end + if (0 == 1) begin + for (int loop_var = 0; loop_var < 1; loop_var++) begin +%000000 if (cyc[loop_var] && t2) $write(""); -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - end - // stop at the first layer even if there's more to find -%000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); + end + end + // stop at the first layer even if there's more to find +%000007 if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); -000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t - // impossible branches and redundant terms -%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); + // impossible branches and redundant terms +%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - // demonstrate current limitations of term matching scheme -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); + // demonstrate current limitations of term matching scheme +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t @@ -241,95 +239,97 @@ -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on - if ((~t1 && t2) -%000004 || + //verilator coverage_off + if (t1 && t2) $write(""); + //verilator coverage_on +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t - (~t3 && t4)) $write(""); - // intentionally testing wonkified expression terms - if ( - cyc[ - 0 -%000005 ] & + // intentionally testing wonkified expression terms +%000005 if (cyc[0] & cyc[1]) $write(""); -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - cyc - [1]) $write(""); - // for now each ternary condition is considered in isolation -%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; + // for now each ternary condition is considered in isolation +%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t - // no expression coverage for multi-bit expressions - if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); - // truth table is too large - if (^cyc[6:0]) $write(""); - // this one is too big even for t_cover_expr_max - if (^cyc) $write(""); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // no expression coverage for multi-bit expressions + if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); + // truth table is too large + if (^cyc[6:0]) $write(""); + // this one is too big even for t_cover_expr_max + if (^cyc) $write(""); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end + end - always_comb begin -%000005 if (t1 && t2) $write(""); + always_comb begin +%000005 if (t1 && t2) $write(""); -000005 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - end + end - logic ta, tb, tc; - initial begin - automatic cls obj = new; - automatic cls null_obj = null; - automatic int q[5]; - automatic int qv[$]; + logic ta, tb, tc; + initial begin + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; - q = '{1, 2, 2, 4, 3}; - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug - qv = q.find_first with (item[0] & item[1]); - ta = '1; - tb = '0; - tc = '0; -%000001 while (ta || tb || tc) begin + q = '{1, 2, 2, 4, 3}; + // lambas not handled + // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) + // tracing_off does not work around the bug + qv = q.find_first with (item[0] & item[1]); + ta = '1; + tb = '0; + tc = '0; +%000001 while (ta || tb || tc) begin -000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: type=expr comment=(ta==1) => 1 hier=top.t -000000 point: type=expr comment=(tb==1) => 1 hier=top.t -000000 point: type=expr comment=(tc==1) => 1 hier=top.t - tc = tb; - tb = ta; - ta = '0; - end - if (!bit'(obj.randomize() with {x < 100;})) $write(""); - if (null_obj != null && null_obj.x == 5) $write(""); + tc = tb; + tb = ta; + ta = '0; end + if (!bit'(obj.randomize() with {x < 100;})) $write(""); + if (null_obj != null && null_obj.x == 5) $write(""); + end - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); + sub the_sub_1 ( + .p(t1), + .q(t2) + ); + sub the_sub_2 ( + .p(t3), + .q(t4) + ); + // TODO -- non-process expressions + sub the_sub_3 ( + .p(t1 ? t2 : t3), + .q(t4) + ); - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. + // TODO + // pragma for expr coverage off / on + // investigate cover point sorting in annotated source + // consider reporting don't care terms + // + // Branches which are statically impossible to reach are still reported. + // E.g. + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // These could potentially be pruned, but they currently follow suit for + // what branch coverage does. Perhaps a switch should be added to not + // count statically impossible things. endmodule @@ -338,16 +338,16 @@ input q ); - always_comb begin -~000019 if (p && q) $write(""); + always_comb begin +~000019 if (p && q) $write(""); +000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* - end + end endmodule - interface intf(); - logic t; + interface intf (); + logic t; endinterface diff --git a/test_regress/t/t_cover_expr.v b/test_regress/t/t_cover_expr.v index 488569a2d..ff5ecc410 100644 --- a/test_regress/t/t_cover_expr.v +++ b/test_regress/t/t_cover_expr.v @@ -5,167 +5,167 @@ // SPDX-License-Identifier: CC0-1.0 class cls; - rand int x; + rand int x; endclass -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; - initial cyc=1; + logic [63:32] cyc2; + always_comb cyc2 = cyc; - logic [63:32] cyc2; - always_comb cyc2 = cyc; + integer some_int; + integer other_int; + logic some_bool; - integer some_int; - integer other_int; - logic some_bool; + wire t1 = cyc[0]; + wire t2 = cyc[1]; + wire t3 = cyc[2]; + wire t4 = cyc[3]; - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; + localparam bit ONE = 1'b1; + localparam bit ZERO = 1'b0; - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; + function automatic bit invert(bit x); + return ~x; + endfunction - function automatic bit invert(bit x); - return ~x; - endfunction + function automatic bit and_oper(bit a, bit b); + return a & b; + endfunction - function automatic bit and_oper(bit a, bit b); - return a & b; - endfunction + localparam int NUM_INTFS = 4; + intf the_intfs[NUM_INTFS-1:0] (); + genvar intf_i; + for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin + always_comb the_intfs[intf_i].t = cyc[intf_i]; + end - localparam int NUM_INTFS = 4; - intf the_intfs [NUM_INTFS-1:0] (); - genvar intf_i; - for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin - always_comb the_intfs[intf_i].t = cyc[intf_i]; + always @(posedge clk) begin + cyc <= cyc + 1; + if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); + if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); + if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); + if ((~t1 && t2) || (~t3 && t4)) $write(""); + if (t3 && (t1 == t2)) $write(""); + if (123 == (124 - 32'(t1 || t2))) $write(""); + some_int <= (t2 || t3) ? 345 : 567; + some_bool <= t1 && t2; + if (t1 & t2) $write(""); + if ((!t1 && t2) | (~t3 && t4)) $write(""); + if (t1 ^ t2) $write(""); + if (~(t1 & t2)) $write(""); + if (t1 -> t2) $write(""); + if (t1 <-> t2) $write(""); + if (&cyc[2:0]) $write(""); + if (&cyc[3:2]) $write(""); + if (|cyc[2:0]) $write(""); + if (^cyc[2:0]) $write(""); + if (|cyc[2:0] || cyc[3]) $write(""); + if (t1 & t2 & 1'b1) $write(""); + if (t1 & t2 & 1'b0) $write(""); + if (t1 & t2 & ONE) $write(""); + if (t1 & t2 & ZERO) $write(""); + if (t1 && t2) begin + $write(""); end - - always @ (posedge clk) begin - cyc <= cyc + 1; - if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); - if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); - if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); - if ((~t1 && t2) || (~t3 && t4)) $write(""); - if (t3 && (t1 == t2)) $write(""); - if (123 == (124 - 32'(t1 || t2))) $write(""); - some_int <= (t2 || t3) ? 345 : 567; - some_bool <= t1 && t2; - if (t1 & t2) $write(""); - if ((!t1 && t2) | (~t3 && t4)) $write(""); - if (t1 ^ t2) $write(""); - if (~(t1 & t2)) $write(""); - if (t1 -> t2) $write(""); - if (t1 <-> t2) $write(""); - if (&cyc[2:0]) $write(""); - if (&cyc[3:2]) $write(""); - if (|cyc[2:0]) $write(""); - if (^cyc[2:0]) $write(""); - if (|cyc[2:0] || cyc[3]) $write(""); - if (t1 & t2 & 1'b1) $write(""); - if (t1 & t2 & 1'b0) $write(""); - if (t1 & t2 & ONE) $write(""); - if (t1 & t2 & ZERO) $write(""); - if (t1 && t2) begin - $write(""); - end else if (t1 || t2) begin - $write(""); - end - if (invert(t1) && t2) $write(""); - if (and_oper(t1, t2)) $write(""); - if (t2 && t3) begin - if (t1 && t2) $write(""); - end - if (0 == 1) begin - for (int loop_var = 0; loop_var < 1; loop_var++) begin - if (cyc[loop_var] && t2) $write(""); - end - end - // stop at the first layer even if there's more to find - if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); - // impossible branches and redundant terms - if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); - if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); - // demonstrate current limitations of term matching scheme - if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on - if ((~t1 && t2) - || - (~t3 && t4)) $write(""); - // intentionally testing wonkified expression terms - if ( - cyc[ - 0 - ] & - cyc - [1]) $write(""); - // for now each ternary condition is considered in isolation - other_int <= t1 ? t2 ? 1 : 2 : 3; - // no expression coverage for multi-bit expressions - if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); - // truth table is too large - if (^cyc[6:0]) $write(""); - // this one is too big even for t_cover_expr_max - if (^cyc) $write(""); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + else if (t1 || t2) begin + $write(""); end - - always_comb begin - if (t1 && t2) $write(""); + if (invert(t1) && t2) $write(""); + if (and_oper(t1, t2)) $write(""); + if (t2 && t3) begin + if (t1 && t2) $write(""); end - - logic ta, tb, tc; - initial begin - automatic cls obj = new; - automatic cls null_obj = null; - automatic int q[5]; - automatic int qv[$]; - - q = '{1, 2, 2, 4, 3}; - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug - qv = q.find_first with (item[0] & item[1]); - ta = '1; - tb = '0; - tc = '0; - while (ta || tb || tc) begin - tc = tb; - tb = ta; - ta = '0; - end - if (!bit'(obj.randomize() with {x < 100;})) $write(""); - if (null_obj != null && null_obj.x == 5) $write(""); + if (0 == 1) begin + for (int loop_var = 0; loop_var < 1; loop_var++) begin + if (cyc[loop_var] && t2) $write(""); + end end + // stop at the first layer even if there's more to find + if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); + // impossible branches and redundant terms + if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); + if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); + // demonstrate current limitations of term matching scheme + if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); + //verilator coverage_off + if (t1 && t2) $write(""); + //verilator coverage_on + if ((~t1 && t2) || (~t3 && t4)) $write(""); + // intentionally testing wonkified expression terms + if (cyc[0] & cyc[1]) $write(""); + // for now each ternary condition is considered in isolation + other_int <= t1 ? t2 ? 1 : 2 : 3; + // no expression coverage for multi-bit expressions + if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); + // truth table is too large + if (^cyc[6:0]) $write(""); + // this one is too big even for t_cover_expr_max + if (^cyc) $write(""); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); + always_comb begin + if (t1 && t2) $write(""); + end - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. + logic ta, tb, tc; + initial begin + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; + + q = '{1, 2, 2, 4, 3}; + // lambas not handled + // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) + // tracing_off does not work around the bug + qv = q.find_first with (item[0] & item[1]); + ta = '1; + tb = '0; + tc = '0; + while (ta || tb || tc) begin + tc = tb; + tb = ta; + ta = '0; + end + if (!bit'(obj.randomize() with {x < 100;})) $write(""); + if (null_obj != null && null_obj.x == 5) $write(""); + end + + sub the_sub_1 ( + .p(t1), + .q(t2) + ); + sub the_sub_2 ( + .p(t3), + .q(t4) + ); + // TODO -- non-process expressions + sub the_sub_3 ( + .p(t1 ? t2 : t3), + .q(t4) + ); + + // TODO + // pragma for expr coverage off / on + // investigate cover point sorting in annotated source + // consider reporting don't care terms + // + // Branches which are statically impossible to reach are still reported. + // E.g. + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // These could potentially be pruned, but they currently follow suit for + // what branch coverage does. Perhaps a switch should be added to not + // count statically impossible things. endmodule @@ -174,12 +174,12 @@ module sub ( input q ); - always_comb begin - if (p && q) $write(""); - end + always_comb begin + if (p && q) $write(""); + end endmodule -interface intf(); - logic t; +interface intf (); + logic t; endinterface diff --git a/test_regress/t/t_cover_expr_array_class.v b/test_regress/t/t_cover_expr_array_class.v index e2f6f2d3a..3b61522db 100644 --- a/test_regress/t/t_cover_expr_array_class.v +++ b/test_regress/t/t_cover_expr_array_class.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Class1; - int value0 = 7; + int value0 = 7; endclass module t; - initial begin - int i; - Class1 q[15]; - for (int j = 0; j < 15; j = j + 1) begin - automatic Class1 x = new; - q[j] = x; - end - while (i < 15) begin - if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; - i += 1; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int i; + Class1 q[15]; + for (int j = 0; j < 15; j = j + 1) begin + automatic Class1 x = new; + q[j] = x; + end + while (i < 15) begin + if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; + i += 1; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_expr_dyn_array_class.v b/test_regress/t/t_cover_expr_dyn_array_class.v index 47e4ede5b..92dfef617 100644 --- a/test_regress/t/t_cover_expr_dyn_array_class.v +++ b/test_regress/t/t_cover_expr_dyn_array_class.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Class1; - int value0 = 7; + int value0 = 7; endclass module t; - initial begin - automatic int i; - automatic Class1 q[] = new [15]; - for (int j = 0; j < 15; j = j + 1) begin - automatic Class1 x = new; - q[j] = x; - end - while (i < 15) begin - if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; - i += 1; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic int i; + automatic Class1 q[] = new[15]; + for (int j = 0; j < 15; j = j + 1) begin + automatic Class1 x = new; + q[j] = x; + end + while (i < 15) begin + if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; + i += 1; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_expr_max.out b/test_regress/t/t_cover_expr_max.out index 39d5174f4..c1faed6a8 100644 --- a/test_regress/t/t_cover_expr_max.out +++ b/test_regress/t/t_cover_expr_max.out @@ -6,144 +6,141 @@ // SPDX-License-Identifier: CC0-1.0 class cls; - rand int x; + rand int x; endclass - module t (/*AUTOARG*/ - // Inputs - clk - ); + module t ( + input clk + ); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; - initial cyc=1; + logic [63:32] cyc2; + always_comb cyc2 = cyc; - logic [63:32] cyc2; - always_comb cyc2 = cyc; + integer some_int; + integer other_int; + logic some_bool; - integer some_int; - integer other_int; - logic some_bool; + wire t1 = cyc[0]; + wire t2 = cyc[1]; + wire t3 = cyc[2]; + wire t4 = cyc[3]; - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; + localparam bit ONE = 1'b1; + localparam bit ZERO = 1'b0; - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; - - function automatic bit invert(bit x); -%000005 return ~x; + function automatic bit invert(bit x); +%000005 return ~x; -000004 point: type=expr comment=(x==0) => 1 hier=top.t -000005 point: type=expr comment=(x==1) => 0 hier=top.t - endfunction + endfunction - function automatic bit and_oper(bit a, bit b); -%000005 return a & b; + function automatic bit and_oper(bit a, bit b); +%000005 return a & b; -000004 point: type=expr comment=(a==0) => 0 hier=top.t -000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t -000005 point: type=expr comment=(b==0) => 0 hier=top.t - endfunction + endfunction - localparam int NUM_INTFS = 4; - intf the_intfs [NUM_INTFS-1:0] (); - genvar intf_i; - for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin - always_comb the_intfs[intf_i].t = cyc[intf_i]; - end + localparam int NUM_INTFS = 4; + intf the_intfs[NUM_INTFS-1:0] (); + genvar intf_i; + for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin + always_comb the_intfs[intf_i].t = cyc[intf_i]; + end - always @ (posedge clk) begin - cyc <= cyc + 1; -%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); + always @(posedge clk) begin + cyc <= cyc + 1; +%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); +%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); +%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000005 if (t3 && (t1 == t2)) $write(""); +%000005 if (t3 && (t1 == t2)) $write(""); -000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); +%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000004 some_int <= (t2 || t3) ? 345 : 567; +%000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000004 point: type=expr comment=(t3==1) => 1 hier=top.t -%000005 some_bool <= t1 && t2; +%000005 some_bool <= t1 && t2; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2) $write(""); +%000005 if (t1 & t2) $write(""); -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); +%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000003 if (t1 ^ t2) $write(""); +%000003 if (t1 ^ t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -%000005 if (~(t1 & t2)) $write(""); +%000005 if (~(t1 & t2)) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 1 hier=top.t -%000004 if (t1 -> t2) $write(""); +%000004 if (t1 -> t2) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000003 if (t1 <-> t2) $write(""); +%000003 if (t1 <-> t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -%000005 if (&cyc[2:0]) $write(""); +%000005 if (&cyc[2:0]) $write(""); -000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t -%000007 if (&cyc[3:2]) $write(""); +%000007 if (&cyc[3:2]) $write(""); -000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t -%000005 if (|cyc[2:0]) $write(""); +%000005 if (|cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -%000002 if (^cyc[2:0]) $write(""); +%000002 if (^cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t @@ -152,87 +149,88 @@ -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -%000005 if (|cyc[2:0] || cyc[3]) $write(""); +%000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t -%000005 if (t1 & t2 & 1'b1) $write(""); +%000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & 1'b0) $write(""); +%000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2 & ONE) $write(""); +%000005 if (t1 & t2 & ONE) $write(""); -000000 point: type=expr comment=(ONE==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & ZERO) $write(""); +%000009 if (t1 & t2 & ZERO) $write(""); -000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 && t2) begin +%000005 if (t1 && t2) begin -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - $write(""); -%000003 end else if (t1 || t2) begin + $write(""); + end +%000003 else if (t1 || t2) begin -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: type=expr comment=(t1==1) => 1 hier=top.t -000002 point: type=expr comment=(t2==1) => 1 hier=top.t - $write(""); - end -%000005 if (invert(t1) && t2) $write(""); + $write(""); + end +%000005 if (invert(t1) && t2) $write(""); -000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t -000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - if (and_oper(t1, t2)) $write(""); -%000005 if (t2 && t3) begin + if (and_oper(t1, t2)) $write(""); +%000005 if (t2 && t3) begin -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -%000001 if (t1 && t2) $write(""); +%000001 if (t1 && t2) $write(""); -000001 point: type=expr comment=(t1==0) => 0 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - if (0 == 1) begin - for (int loop_var = 0; loop_var < 1; loop_var++) begin -%000000 if (cyc[loop_var] && t2) $write(""); + end + if (0 == 1) begin + for (int loop_var = 0; loop_var < 1; loop_var++) begin +%000000 if (cyc[loop_var] && t2) $write(""); -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - end - // stop at the first layer even if there's more to find -%000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); + end + end + // stop at the first layer even if there's more to find +%000007 if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); -000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t - // impossible branches and redundant terms -%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); + // impossible branches and redundant terms +%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - // demonstrate current limitations of term matching scheme -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); + // demonstrate current limitations of term matching scheme +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t @@ -241,36 +239,29 @@ -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on - if ((~t1 && t2) -%000004 || + //verilator coverage_off + if (t1 && t2) $write(""); + //verilator coverage_on +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t - (~t3 && t4)) $write(""); - // intentionally testing wonkified expression terms - if ( - cyc[ - 0 -%000005 ] & + // intentionally testing wonkified expression terms +%000005 if (cyc[0] & cyc[1]) $write(""); -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - cyc - [1]) $write(""); - // for now each ternary condition is considered in isolation -%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; + // for now each ternary condition is considered in isolation +%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t - // no expression coverage for multi-bit expressions - if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); - // truth table is too large -%000001 if (^cyc[6:0]) $write(""); + // no expression coverage for multi-bit expressions + if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); + // truth table is too large +%000001 if (^cyc[6:0]) $write(""); -000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t @@ -399,65 +390,74 @@ -000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t - // this one is too big even for t_cover_expr_max - if (^cyc) $write(""); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // this one is too big even for t_cover_expr_max + if (^cyc) $write(""); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end + end - always_comb begin -%000005 if (t1 && t2) $write(""); + always_comb begin +%000005 if (t1 && t2) $write(""); -000005 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - end + end - logic ta, tb, tc; - initial begin - automatic cls obj = new; - automatic cls null_obj = null; - automatic int q[5]; - automatic int qv[$]; + logic ta, tb, tc; + initial begin + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; - q = '{1, 2, 2, 4, 3}; - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug - qv = q.find_first with (item[0] & item[1]); - ta = '1; - tb = '0; - tc = '0; -%000001 while (ta || tb || tc) begin + q = '{1, 2, 2, 4, 3}; + // lambas not handled + // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) + // tracing_off does not work around the bug + qv = q.find_first with (item[0] & item[1]); + ta = '1; + tb = '0; + tc = '0; +%000001 while (ta || tb || tc) begin -000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: type=expr comment=(ta==1) => 1 hier=top.t -000000 point: type=expr comment=(tb==1) => 1 hier=top.t -000000 point: type=expr comment=(tc==1) => 1 hier=top.t - tc = tb; - tb = ta; - ta = '0; - end - if (!bit'(obj.randomize() with {x < 100;})) $write(""); - if (null_obj != null && null_obj.x == 5) $write(""); + tc = tb; + tb = ta; + ta = '0; end + if (!bit'(obj.randomize() with {x < 100;})) $write(""); + if (null_obj != null && null_obj.x == 5) $write(""); + end - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); + sub the_sub_1 ( + .p(t1), + .q(t2) + ); + sub the_sub_2 ( + .p(t3), + .q(t4) + ); + // TODO -- non-process expressions + sub the_sub_3 ( + .p(t1 ? t2 : t3), + .q(t4) + ); - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. + // TODO + // pragma for expr coverage off / on + // investigate cover point sorting in annotated source + // consider reporting don't care terms + // + // Branches which are statically impossible to reach are still reported. + // E.g. + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // These could potentially be pruned, but they currently follow suit for + // what branch coverage does. Perhaps a switch should be added to not + // count statically impossible things. endmodule @@ -466,16 +466,16 @@ input q ); - always_comb begin -~000019 if (p && q) $write(""); + always_comb begin +~000019 if (p && q) $write(""); +000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* - end + end endmodule - interface intf(); - logic t; + interface intf (); + logic t; endinterface diff --git a/test_regress/t/t_cover_expr_queue_class.v b/test_regress/t/t_cover_expr_queue_class.v index abae5e3b5..17bc55734 100644 --- a/test_regress/t/t_cover_expr_queue_class.v +++ b/test_regress/t/t_cover_expr_queue_class.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 class Class1; - int value0 = 7; + int value0 = 7; endclass module t; - initial begin - int i; - Class1 q[$]; - repeat(15) begin - automatic Class1 x = new; - q = { q, x }; - end - while (i < q.size()) begin - if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; - i += 1; - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int i; + Class1 q[$]; + repeat (15) begin + automatic Class1 x = new; + q = {q, x}; + end + while (i < q.size()) begin + if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; + i += 1; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_expr_trace.out b/test_regress/t/t_cover_expr_trace.out index d82c98c8d..9acf096c7 100644 --- a/test_regress/t/t_cover_expr_trace.out +++ b/test_regress/t/t_cover_expr_trace.out @@ -6,144 +6,141 @@ // SPDX-License-Identifier: CC0-1.0 class cls; - rand int x; + rand int x; endclass - module t (/*AUTOARG*/ - // Inputs - clk - ); + module t ( + input clk + ); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; - initial cyc=1; + logic [63:32] cyc2; + always_comb cyc2 = cyc; - logic [63:32] cyc2; - always_comb cyc2 = cyc; + integer some_int; + integer other_int; + logic some_bool; - integer some_int; - integer other_int; - logic some_bool; + wire t1 = cyc[0]; + wire t2 = cyc[1]; + wire t3 = cyc[2]; + wire t4 = cyc[3]; - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; + localparam bit ONE = 1'b1; + localparam bit ZERO = 1'b0; - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; - - function automatic bit invert(bit x); -%000005 return ~x; + function automatic bit invert(bit x); +%000005 return ~x; -000004 point: type=expr comment=(x==0) => 1 hier=top.t -000005 point: type=expr comment=(x==1) => 0 hier=top.t - endfunction + endfunction - function automatic bit and_oper(bit a, bit b); -%000005 return a & b; + function automatic bit and_oper(bit a, bit b); +%000005 return a & b; -000004 point: type=expr comment=(a==0) => 0 hier=top.t -000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t -000005 point: type=expr comment=(b==0) => 0 hier=top.t - endfunction + endfunction - localparam int NUM_INTFS = 4; - intf the_intfs [NUM_INTFS-1:0] (); - genvar intf_i; - for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin - always_comb the_intfs[intf_i].t = cyc[intf_i]; - end + localparam int NUM_INTFS = 4; + intf the_intfs[NUM_INTFS-1:0] (); + genvar intf_i; + for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin + always_comb the_intfs[intf_i].t = cyc[intf_i]; + end - always @ (posedge clk) begin - cyc <= cyc + 1; -%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); + always @(posedge clk) begin + cyc <= cyc + 1; +%000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); +%000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); +%000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000005 if (t3 && (t1 == t2)) $write(""); +%000005 if (t3 && (t1 == t2)) $write(""); -000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); +%000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000004 some_int <= (t2 || t3) ? 345 : 567; +%000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000004 point: type=expr comment=(t3==1) => 1 hier=top.t -%000005 some_bool <= t1 && t2; +%000005 some_bool <= t1 && t2; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2) $write(""); +%000005 if (t1 & t2) $write(""); -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); +%000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000003 if (t1 ^ t2) $write(""); +%000003 if (t1 ^ t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -%000005 if (~(t1 & t2)) $write(""); +%000005 if (~(t1 & t2)) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 1 hier=top.t -%000004 if (t1 -> t2) $write(""); +%000004 if (t1 -> t2) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -%000003 if (t1 <-> t2) $write(""); +%000003 if (t1 <-> t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -%000005 if (&cyc[2:0]) $write(""); +%000005 if (&cyc[2:0]) $write(""); -000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t -%000007 if (&cyc[3:2]) $write(""); +%000007 if (&cyc[3:2]) $write(""); -000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t -%000005 if (|cyc[2:0]) $write(""); +%000005 if (|cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -%000002 if (^cyc[2:0]) $write(""); +%000002 if (^cyc[2:0]) $write(""); -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t @@ -152,87 +149,88 @@ -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -%000005 if (|cyc[2:0] || cyc[3]) $write(""); +%000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t -%000005 if (t1 & t2 & 1'b1) $write(""); +%000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & 1'b0) $write(""); +%000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 & t2 & ONE) $write(""); +%000005 if (t1 & t2 & ONE) $write(""); -000000 point: type=expr comment=(ONE==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000009 if (t1 & t2 & ZERO) $write(""); +%000009 if (t1 & t2 & ZERO) $write(""); -000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if (t1 && t2) begin +%000005 if (t1 && t2) begin -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - $write(""); -%000003 end else if (t1 || t2) begin + $write(""); + end +%000003 else if (t1 || t2) begin -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: type=expr comment=(t1==1) => 1 hier=top.t -000002 point: type=expr comment=(t2==1) => 1 hier=top.t - $write(""); - end -%000005 if (invert(t1) && t2) $write(""); + $write(""); + end +%000005 if (invert(t1) && t2) $write(""); -000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t -000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - if (and_oper(t1, t2)) $write(""); -%000005 if (t2 && t3) begin + if (and_oper(t1, t2)) $write(""); +%000005 if (t2 && t3) begin -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -%000001 if (t1 && t2) $write(""); +%000001 if (t1 && t2) $write(""); -000001 point: type=expr comment=(t1==0) => 0 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - if (0 == 1) begin - for (int loop_var = 0; loop_var < 1; loop_var++) begin -%000000 if (cyc[loop_var] && t2) $write(""); + end + if (0 == 1) begin + for (int loop_var = 0; loop_var < 1; loop_var++) begin +%000000 if (cyc[loop_var] && t2) $write(""); -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - end - // stop at the first layer even if there's more to find -%000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); + end + end + // stop at the first layer even if there's more to find +%000007 if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); -000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t - // impossible branches and redundant terms -%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); + // impossible branches and redundant terms +%000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - // demonstrate current limitations of term matching scheme -%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); + // demonstrate current limitations of term matching scheme +%000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t @@ -241,95 +239,97 @@ -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on - if ((~t1 && t2) -%000004 || + //verilator coverage_off + if (t1 && t2) $write(""); + //verilator coverage_on +%000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t - (~t3 && t4)) $write(""); - // intentionally testing wonkified expression terms - if ( - cyc[ - 0 -%000005 ] & + // intentionally testing wonkified expression terms +%000005 if (cyc[0] & cyc[1]) $write(""); -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - cyc - [1]) $write(""); - // for now each ternary condition is considered in isolation -%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; + // for now each ternary condition is considered in isolation +%000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t - // no expression coverage for multi-bit expressions - if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); - // truth table is too large - if (^cyc[6:0]) $write(""); - // this one is too big even for t_cover_expr_max - if (^cyc) $write(""); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // no expression coverage for multi-bit expressions + if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); + // truth table is too large + if (^cyc[6:0]) $write(""); + // this one is too big even for t_cover_expr_max + if (^cyc) $write(""); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end + end - always_comb begin -%000005 if (t1 && t2) $write(""); + always_comb begin +%000005 if (t1 && t2) $write(""); -000005 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t - end + end - logic ta, tb, tc; - initial begin - automatic cls obj = new; - automatic cls null_obj = null; - automatic int q[5]; - automatic int qv[$]; + logic ta, tb, tc; + initial begin + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; - q = '{1, 2, 2, 4, 3}; - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug - qv = q.find_first with (item[0] & item[1]); - ta = '1; - tb = '0; - tc = '0; -%000001 while (ta || tb || tc) begin + q = '{1, 2, 2, 4, 3}; + // lambas not handled + // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) + // tracing_off does not work around the bug + qv = q.find_first with (item[0] & item[1]); + ta = '1; + tb = '0; + tc = '0; +%000001 while (ta || tb || tc) begin -000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: type=expr comment=(ta==1) => 1 hier=top.t -000000 point: type=expr comment=(tb==1) => 1 hier=top.t -000000 point: type=expr comment=(tc==1) => 1 hier=top.t - tc = tb; - tb = ta; - ta = '0; - end - if (!bit'(obj.randomize() with {x < 100;})) $write(""); - if (null_obj != null && null_obj.x == 5) $write(""); + tc = tb; + tb = ta; + ta = '0; end + if (!bit'(obj.randomize() with {x < 100;})) $write(""); + if (null_obj != null && null_obj.x == 5) $write(""); + end - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); + sub the_sub_1 ( + .p(t1), + .q(t2) + ); + sub the_sub_2 ( + .p(t3), + .q(t4) + ); + // TODO -- non-process expressions + sub the_sub_3 ( + .p(t1 ? t2 : t3), + .q(t4) + ); - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. + // TODO + // pragma for expr coverage off / on + // investigate cover point sorting in annotated source + // consider reporting don't care terms + // + // Branches which are statically impossible to reach are still reported. + // E.g. + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // These could potentially be pruned, but they currently follow suit for + // what branch coverage does. Perhaps a switch should be added to not + // count statically impossible things. endmodule @@ -338,16 +338,16 @@ input q ); - always_comb begin -~000019 if (p && q) $write(""); + always_comb begin +~000019 if (p && q) $write(""); +000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* - end + end endmodule - interface intf(); - logic t; + interface intf (); + logic t; endinterface diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index 77bcb7402..a826d835a 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -6,553 +6,553 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - input clk; + input clk; - reg toggle; -%000001 initial toggle=0; + reg toggle; +%000001 initial toggle=0; -000001 point: type=line comment=block hier=top.t - integer cyc; -%000001 initial cyc=1; + integer cyc; +%000001 initial cyc=1; -000001 point: type=line comment=block hier=top.t - wire [7:0] cyc_copy = cyc[7:0]; + wire [7:0] cyc_copy = cyc[7:0]; - alpha a1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - alpha a2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tsk t1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tab tab1 (/*AUTOINST*/ - // Inputs - .clk (clk)); - par par1 (/*AUTOINST*/); - cond cond1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .cyc (cyc)); + alpha a1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + alpha a2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + tsk t1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + tab tab1 (/*AUTOINST*/ + // Inputs + .clk (clk)); + par par1 (/*AUTOINST*/); + cond cond1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .cyc (cyc)); - 000010 always @ (posedge clk) begin + 000010 always @ (posedge clk) begin +000010 point: type=line comment=block hier=top.t -~000010 if (cyc!=0) begin +~000010 if (cyc!=0) begin +000010 point: type=branch comment=if hier=top.t -000000 point: type=branch comment=else hier=top.t - 000010 cyc <= cyc + 1; + 000010 cyc <= cyc + 1; +000010 point: type=branch comment=if hier=top.t - 000010 toggle <= '0; + 000010 toggle <= '0; +000010 point: type=branch comment=if hier=top.t - // Single and multiline if -%000009 if (cyc==3) $write(""); + // Single and multiline if +%000009 if (cyc==3) $write(""); -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -%000009 if (cyc==3) +%000009 if (cyc==3) -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -%000001 begin +%000001 begin -000001 point: type=branch comment=if hier=top.t -%000001 $write(""); +%000001 $write(""); -000001 point: type=branch comment=if hier=top.t - end - // Single and multiline else -%000009 if (cyc==3) ; else $write(""); + end + // Single and multiline else +%000009 if (cyc==3) ; else $write(""); -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -%000009 if (cyc==3) ; +%000009 if (cyc==3) ; -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t - else -%000009 begin + else +%000009 begin -000009 point: type=branch comment=else hier=top.t -%000009 $write(""); +%000009 $write(""); -000009 point: type=branch comment=else hier=top.t - end - // Single and multiline if else -%000009 if (cyc==3) $write(""); else $write(""); + end + // Single and multiline if else +%000009 if (cyc==3) $write(""); else $write(""); -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -%000009 if (cyc==3) +%000009 if (cyc==3) -000001 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -%000001 begin +%000001 begin -000001 point: type=branch comment=if hier=top.t -%000001 $write(""); +%000001 $write(""); -000001 point: type=branch comment=if hier=top.t - end - else -%000009 begin + end + else +%000009 begin -000009 point: type=branch comment=else hier=top.t -%000009 $write(""); +%000009 $write(""); -000009 point: type=branch comment=else hier=top.t - end - // multiline elseif -%000001 if (cyc==3) + end + // multiline elseif +%000001 if (cyc==3) -000001 point: type=line comment=elsif hier=top.t -%000001 begin +%000001 begin -000001 point: type=line comment=elsif hier=top.t -%000001 $write(""); +%000001 $write(""); -000001 point: type=line comment=elsif hier=top.t - end -%000001 else if (cyc==4) + end +%000001 else if (cyc==4) -000001 point: type=line comment=elsif hier=top.t -%000001 begin +%000001 begin -000001 point: type=line comment=elsif hier=top.t -%000001 $write(""); +%000001 $write(""); -000001 point: type=line comment=elsif hier=top.t - end -%000007 else if (cyc==5) + end +%000007 else if (cyc==5) -000001 point: type=line comment=if hier=top.t -000007 point: type=line comment=else hier=top.t -%000001 begin +%000001 begin -000001 point: type=line comment=if hier=top.t -%000001 $write(""); +%000001 $write(""); -000001 point: type=line comment=if hier=top.t - end - else -%000007 begin + end + else +%000007 begin -000007 point: type=line comment=else hier=top.t -%000007 $write(""); +%000007 $write(""); -000007 point: type=line comment=else hier=top.t - end - // Single and multiline while -%000000 while (0); + end + // Single and multiline while +%000000 while (0); -000000 point: type=line comment=block hier=top.t -%000000 while (0) begin +%000000 while (0) begin -000000 point: type=line comment=block hier=top.t -%000000 $write(""); +%000000 $write(""); -000000 point: type=line comment=block hier=top.t - end -%000000 do ; while (0); + end +%000000 do ; while (0); -000000 point: type=line comment=block hier=top.t -~000010 do begin +~000010 do begin -000000 point: type=line comment=block hier=top.t +000010 point: type=line comment=block hier=top.t - 000010 $write(""); + 000010 $write(""); +000010 point: type=line comment=block hier=top.t -~000010 end while (0); +~000010 end while (0); -000000 point: type=line comment=block hier=top.t +000010 point: type=line comment=block hier=top.t - //=== - // Task and complicated -%000001 if (cyc==3) begin + //=== + // Task and complicated +%000001 if (cyc==3) begin -000001 point: type=line comment=elsif hier=top.t -%000001 toggle <= '1; +%000001 toggle <= '1; -000001 point: type=line comment=elsif hier=top.t - end -%000001 else if (cyc==5) begin + end +%000001 else if (cyc==5) begin -000001 point: type=line comment=elsif hier=top.t `ifdef VERILATOR -%000001 $c("this->call_task();"); +%000001 $c("this->call_task();"); -000001 point: type=line comment=elsif hier=top.t `else - call_task(); + call_task(); `endif - end -%000007 else if (cyc==10) begin + end +%000007 else if (cyc==10) begin -000001 point: type=branch comment=if hier=top.t -000007 point: type=branch comment=else hier=top.t -%000001 $write("*-* All Finished *-*\n"); +%000001 $write("*-* All Finished *-*\n"); -000001 point: type=branch comment=if hier=top.t -%000001 $finish; +%000001 $finish; -000001 point: type=branch comment=if hier=top.t - end end - end + end + end -%000001 task call_task; +%000001 task call_task; -000001 point: type=line comment=block hier=top.t - /* verilator public */ -%000001 t1.center_task(1'b1); + /* verilator public */ +%000001 t1.center_task(1'b1); -000001 point: type=line comment=block hier=top.t - endtask + endtask endmodule module alpha (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - 000020 always @ (posedge clk) begin + // Inputs + clk, toggle + ); + input clk; + input toggle; + 000020 always @ (posedge clk) begin +000020 point: type=line comment=block hier=top.t.a* -~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) +~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) -000002 point: type=branch comment=if hier=top.t.a* +000018 point: type=branch comment=else hier=top.t.a* -%000002 $write(""); +%000002 $write(""); -000002 point: type=branch comment=if hier=top.t.a* - // t.a1 and t.a2 collapse to a count of 2 - end - 000018 if (toggle) begin // *** t_cover_line.vlt turns this off + // t.a1 and t.a2 collapse to a count of 2 + end + 000018 if (toggle) begin // *** t_cover_line.vlt turns this off +000018 point: type=line comment=else hier=top.t.a* - $write(""); // CHECK_COVER_MISSING(0) - // This doesn't even get added + $write(""); // CHECK_COVER_MISSING(0) + // This doesn't even get added `ifdef ATTRIBUTE - // verilator coverage_block_off + // verilator coverage_block_off `endif - end - end + end + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - /* verilator public_module */ + /* verilator public_module */ - 000020 always @ (posedge clk) begin + 000020 always @ (posedge clk) begin +000020 point: type=line comment=block hier=top.t.b* - 000020 $write(""); // Always covered + 000020 $write(""); // Always covered +000020 point: type=line comment=block hier=top.t.b* -~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) +~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) -000000 point: type=branch comment=if hier=top.t.b* +000020 point: type=branch comment=else hier=top.t.b* - // Make sure that we don't optimize away zero buckets -%000000 $write(""); + // Make sure that we don't optimize away zero buckets +%000000 $write(""); -000000 point: type=branch comment=if hier=top.t.b* - end -~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) + end +~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) -000002 point: type=branch comment=if hier=top.t.b* +000018 point: type=branch comment=else hier=top.t.b* - // t.b1 and t.b2 collapse to a count of 2 -%000002 $write(""); + // t.b1 and t.b2 collapse to a count of 2 +%000002 $write(""); -000002 point: type=branch comment=if hier=top.t.b* - end - 000018 if (toggle) begin : block + end + 000018 if (toggle) begin : block +000018 point: type=line comment=else hier=top.t.b* - // This doesn't + // This doesn't `ifdef ATTRIBUTE - // verilator coverage_block_off + // verilator coverage_block_off `endif - begin end // *** t_cover_line.vlt turns this off (so need begin/end) - if (1) begin end // CHECK_COVER_MISSING(0) - $write(""); // CHECK_COVER_MISSING(0) - end - end + begin end // *** t_cover_line.vlt turns this off (so need begin/end) + if (1) begin end // CHECK_COVER_MISSING(0) + $write(""); // CHECK_COVER_MISSING(0) + end + end endmodule class Cls; - bit m_toggle; - 000011 function new(bit toggle); + bit m_toggle; + 000011 function new(bit toggle); +000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg - 000011 m_toggle = toggle; + 000011 m_toggle = toggle; +000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg -~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg -000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg - 000011 $write(""); + 000011 $write(""); +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction - 000011 static function void fstatic(bit toggle); + end + endfunction + 000011 static function void fstatic(bit toggle); +000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg -~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg -000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg - 000011 $write(""); + 000011 $write(""); +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction - 000011 function void fauto(); + end + endfunction + 000011 function void fauto(); +000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg -~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) +~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg -000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg - 000011 $write(""); + 000011 $write(""); +000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg - end - endfunction + end + endfunction endclass module tsk (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - /* verilator public_module */ + /* verilator public_module */ - 000010 always @ (posedge clk) begin + 000010 always @ (posedge clk) begin +000010 point: type=line comment=block hier=top.t.t1 - 000010 center_task(1'b0); + 000010 center_task(1'b0); +000010 point: type=line comment=block hier=top.t.t1 - end + end - 000011 task automatic center_task; + 000011 task automatic center_task; +000011 point: type=line comment=block hier=top.t.t1 - input external; - 000011 begin + input external; + 000011 begin +000011 point: type=line comment=block hier=top.t.t1 -~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) +~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: type=branch comment=if hier=top.t.t1 +000010 point: type=branch comment=else hier=top.t.t1 -%000001 $write(""); +%000001 $write(""); -000001 point: type=branch comment=if hier=top.t.t1 - end -~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) + end +~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: type=branch comment=if hier=top.t.t1 +000010 point: type=branch comment=else hier=top.t.t1 -%000001 $write("[%0t] Got external pulse\n", $time); +%000001 $write("[%0t] Got external pulse\n", $time); -000001 point: type=branch comment=if hier=top.t.t1 - end end - 000011 begin + end + 000011 begin +000011 point: type=line comment=block hier=top.t.t1 - 000011 Cls c; + 000011 Cls c; +000011 point: type=line comment=block hier=top.t.t1 - 000011 c = new(1'b1); + 000011 c = new(1'b1); +000011 point: type=line comment=block hier=top.t.t1 - 000011 c.fauto(); + 000011 c.fauto(); +000011 point: type=line comment=block hier=top.t.t1 - 000011 Cls::fstatic(1'b1); + 000011 Cls::fstatic(1'b1); +000011 point: type=line comment=block hier=top.t.t1 - end - endtask + end + endtask endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - // verilator coverage_off - always @ (posedge clk) begin - if (toggle) begin - $write(""); // CHECK_COVER_MISSING(0) - // because under coverage_module_off - end - end - // verilator coverage_on - 000010 always @ (posedge clk) begin + // verilator coverage_off + always @ (posedge clk) begin + if (toggle) begin + $write(""); // CHECK_COVER_MISSING(0) + // because under coverage_module_off + end + end + // verilator coverage_on + 000010 always @ (posedge clk) begin +000010 point: type=line comment=block hier=top.t.o1 -%000009 if (toggle) begin +%000009 if (toggle) begin -000001 point: type=branch comment=if hier=top.t.o1 -000009 point: type=branch comment=else hier=top.t.o1 - // because under coverage_module_off -%000001 $write(""); + // because under coverage_module_off +%000001 $write(""); -000001 point: type=branch comment=if hier=top.t.o1 -%000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) +%000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) -000000 point: type=branch comment=if hier=top.t.o1 -000001 point: type=branch comment=else hier=top.t.o1 - end - end + end + end endmodule module tab (input clk); - bit [3:0] cyc4; - int decoded; + bit [3:0] cyc4; + int decoded; - 000010 always @ (posedge clk) begin + 000010 always @ (posedge clk) begin +000010 point: type=line comment=block hier=top.t.tab1 - 000010 case (cyc4) + 000010 case (cyc4) +000010 point: type=line comment=block hier=top.t.tab1 -%000001 1: decoded = 10; +%000001 1: decoded = 10; -000001 point: type=line comment=case hier=top.t.tab1 -%000001 2: decoded = 20; +%000001 2: decoded = 20; -000001 point: type=line comment=case hier=top.t.tab1 -%000001 3: decoded = 30; +%000001 3: decoded = 30; -000001 point: type=line comment=case hier=top.t.tab1 -%000001 4: decoded = 40; +%000001 4: decoded = 40; -000001 point: type=line comment=case hier=top.t.tab1 -%000001 5: decoded = 50; +%000001 5: decoded = 50; -000001 point: type=line comment=case hier=top.t.tab1 -%000005 default: decoded = 0; +%000005 default: decoded = 0; -000005 point: type=line comment=case hier=top.t.tab1 - endcase - end + endcase + end - 000010 always @ (posedge clk) begin + 000010 always @ (posedge clk) begin +000010 point: type=line comment=block hier=top.t.tab1 - 000010 cyc4 <= cyc4 + 1; + 000010 cyc4 <= cyc4 + 1; +000010 point: type=line comment=block hier=top.t.tab1 - end + end endmodule module par(); - localparam int CALLS_FUNC = param_func(1); + localparam int CALLS_FUNC = param_func(1); - // We don't currently count elaboration time use towards coverage. This - // seems safer for functions used both at elaboration time and not - but may - // revisit this. -%000000 function automatic int param_func(int i); + // We don't currently count elaboration time use towards coverage. This + // seems safer for functions used both at elaboration time and not - but may + // revisit this. +%000000 function automatic int param_func(int i); -000000 point: type=line comment=block hier=top.t.par1 -%000000 if (i == 0) begin +%000000 if (i == 0) begin -000000 point: type=branch comment=if hier=top.t.par1 -000000 point: type=branch comment=else hier=top.t.par1 -%000000 i = 99; // Uncovered +%000000 i = 99; // Uncovered -000000 point: type=branch comment=if hier=top.t.par1 - end -%000000 else begin + end +%000000 else begin -000000 point: type=branch comment=else hier=top.t.par1 -%000000 i = i + 1; +%000000 i = i + 1; -000000 point: type=branch comment=else hier=top.t.par1 - end -%000000 return i; + end +%000000 return i; -000000 point: type=line comment=block hier=top.t.par1 - endfunction + endfunction endmodule package my_pkg; -%000001 int x = 1 ? 1 : 0; +%000001 int x = 1 ? 1 : 0; -000001 point: type=line comment=block hier=top.my_pkg endpackage %000001 class Getter1; -000001 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg - 000020 function int get_1; + 000020 function int get_1; +000020 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg - 000020 return 1; + 000020 return 1; +000020 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg - endfunction + endfunction endclass module cond(input logic clk, input int cyc); - logic a, b, c, d, e, f, g, h, k, l, m; - logic [5:0] tab; - typedef logic [7:0] arr_t[1:0]; - arr_t data[1:0]; -%000001 Getter1 getter1 = new; + logic a, b, c, d, e, f, g, h, k, l, m; + logic [5:0] tab; + typedef logic [7:0] arr_t[1:0]; + arr_t data[1:0]; +%000001 Getter1 getter1 = new; -000001 point: type=line comment=block hier=top.t.cond1 - string s; + string s; - struct packed { - logic unsigned [15:0] a; - logic unsigned [15:0] b; - } pstruct; + struct packed { + logic unsigned [15:0] a; + logic unsigned [15:0] b; + } pstruct; -%000001 function logic func_side_effect; +%000001 function logic func_side_effect; -000001 point: type=line comment=block hier=top.t.cond1 -%000001 $display("SIDE EFFECT"); +%000001 $display("SIDE EFFECT"); -000001 point: type=line comment=block hier=top.t.cond1 -%000001 return 1; +%000001 return 1; -000001 point: type=line comment=block hier=top.t.cond1 - endfunction + endfunction - 000010 function arr_t get_arr; + 000010 function arr_t get_arr; +000010 point: type=line comment=block hier=top.t.cond1 - 000010 arr_t arr; + 000010 arr_t arr; +000010 point: type=line comment=block hier=top.t.cond1 - 000010 return arr; + 000010 return arr; +000010 point: type=line comment=block hier=top.t.cond1 - endfunction + endfunction -~000011 assign a = (cyc == 0) ? clk : 1'bz; +~000011 assign a = (cyc == 0) ? clk : 1'bz; -000000 point: type=branch comment=cond_then hier=top.t.cond1 +000011 point: type=branch comment=cond_else hier=top.t.cond1 -~000028 assign b = (cyc == 1) ? clk : 0; +~000028 assign b = (cyc == 1) ? clk : 0; -000003 point: type=branch comment=cond_then hier=top.t.cond1 +000028 point: type=branch comment=cond_else hier=top.t.cond1 -%000001 assign c = func_side_effect() ? clk : 0; +%000001 assign c = func_side_effect() ? clk : 0; -000001 point: type=branch comment=cond_then hier=top.t.cond1 -000000 point: type=branch comment=cond_else hier=top.t.cond1 - 000010 always @(posedge clk) begin + 000010 always @(posedge clk) begin +000010 point: type=line comment=block hier=top.t.cond1 -~000010 d = (cyc % 3 == 0) ? 1 : 0; +~000010 d = (cyc % 3 == 0) ? 1 : 0; +000010 point: type=line comment=block hier=top.t.cond1 -000003 point: type=branch comment=cond_then hier=top.t.cond1 -000007 point: type=branch comment=cond_else hier=top.t.cond1 -~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); +~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); +000010 point: type=line comment=block hier=top.t.cond1 -000000 point: type=branch comment=cond_then hier=top.t.cond1 +000010 point: type=branch comment=cond_else hier=top.t.cond1 - end -~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; + end +~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; +000012 point: type=branch comment=cond_then hier=top.t.cond1 +000019 point: type=branch comment=cond_else hier=top.t.cond1 -000007 point: type=branch comment=cond_then hier=top.t.cond1 -000005 point: type=branch comment=cond_else hier=top.t.cond1 - // ternary operator in condition shouldn't be included to the coverae -~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; + // ternary operator in condition shouldn't be included to the coverae +~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; +000011 point: type=branch comment=cond_then hier=top.t.cond1 -000000 point: type=branch comment=cond_else hier=top.t.cond1 - // the same as in index - assign tab[clk ? 1 : 0] = 1; - assign m = tab[clk ? 3 : 4]; + // the same as in index + assign tab[clk ? 1 : 0] = 1; + assign m = tab[clk ? 3 : 4]; - for (genvar i = 0; i < 2; i++) begin - 000022 assign g = clk ? 1 : 0; + for (genvar i = 0; i < 2; i++) begin + 000022 assign g = clk ? 1 : 0; +000020 point: type=branch comment=cond_then hier=top.t.cond1 +000022 point: type=branch comment=cond_else hier=top.t.cond1 - end + end - 000011 always begin + 000011 always begin +000011 point: type=line comment=block hier=top.t.cond1 -~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; +~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; -000000 point: type=branch comment=cond_then hier=top.t.cond1 -000001 point: type=branch comment=cond_else hier=top.t.cond1 -000001 point: type=branch comment=if hier=top.t.cond1 +000010 point: type=branch comment=else hier=top.t.cond1 - 000010 else h = 1; + 000010 else h = 1; +000010 point: type=branch comment=else hier=top.t.cond1 -~000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); +~000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); +000011 point: type=line comment=block hier=top.t.cond1 -000001 point: type=branch comment=cond_then hier=top.t.cond1 +000010 point: type=branch comment=cond_else hier=top.t.cond1 - // ternary operator in conditions should be skipped - 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin + // ternary operator in conditions should be skipped + 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin +000011 point: type=line comment=block hier=top.t.cond1 +000055 point: type=line comment=block hier=top.t.cond1 - 000055 k = 1'(i); + 000055 k = 1'(i); +000055 point: type=line comment=block hier=top.t.cond1 - end - 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin + end + 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin +000011 point: type=line comment=block hier=top.t.cond1 +000011 point: type=branch comment=cond_then hier=top.t.cond1 +000033 point: type=branch comment=cond_else hier=top.t.cond1 +000044 point: type=line comment=block hier=top.t.cond1 - 000044 k = 1'(i); + 000044 k = 1'(i); +000044 point: type=line comment=block hier=top.t.cond1 - end + end -~000011 if (k ? 1 : 0) k = 1; +~000011 if (k ? 1 : 0) k = 1; -000000 point: type=branch comment=if hier=top.t.cond1 +000011 point: type=branch comment=else hier=top.t.cond1 - 000011 else k = 0; + 000011 else k = 0; +000011 point: type=branch comment=else hier=top.t.cond1 - end + end -~000010 assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; +~000010 assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; -000001 point: type=branch comment=cond_then hier=top.t.cond1 +000010 point: type=branch comment=cond_else hier=top.t.cond1 - assign pstruct.b = 16'd0; + assign pstruct.b = 16'd0; - 000010 always @(posedge clk) begin + 000010 always @(posedge clk) begin +000010 point: type=line comment=block hier=top.t.cond1 -%000009 if (cyc == 2) $display("%08x", pstruct); +%000009 if (cyc == 2) $display("%08x", pstruct); -000001 point: type=branch comment=if hier=top.t.cond1 -000009 point: type=branch comment=else hier=top.t.cond1 - end + end endmodule diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 64bf8350a..95d10a275 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -5,372 +5,372 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - input clk; + input clk; - reg toggle; - initial toggle=0; + reg toggle; + initial toggle=0; - integer cyc; - initial cyc=1; + integer cyc; + initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; + wire [7:0] cyc_copy = cyc[7:0]; - alpha a1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - alpha a2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - beta b2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tsk t1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); - tab tab1 (/*AUTOINST*/ - // Inputs - .clk (clk)); - par par1 (/*AUTOINST*/); - cond cond1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .cyc (cyc)); + alpha a1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + alpha a2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + tsk t1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + tab tab1 (/*AUTOINST*/ + // Inputs + .clk (clk)); + par par1 (/*AUTOINST*/); + cond cond1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .cyc (cyc)); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= '0; - // Single and multiline if - if (cyc==3) $write(""); - if (cyc==3) - begin - $write(""); - end - // Single and multiline else - if (cyc==3) ; else $write(""); - if (cyc==3) ; - else - begin - $write(""); - end - // Single and multiline if else - if (cyc==3) $write(""); else $write(""); - if (cyc==3) - begin - $write(""); - end - else - begin - $write(""); - end - // multiline elseif - if (cyc==3) - begin - $write(""); - end - else if (cyc==4) - begin - $write(""); - end - else if (cyc==5) - begin - $write(""); - end - else - begin - $write(""); - end - // Single and multiline while - while (0); - while (0) begin - $write(""); - end - do ; while (0); - do begin - $write(""); - end while (0); - //=== - // Task and complicated - if (cyc==3) begin - toggle <= '1; - end - else if (cyc==5) begin -`ifdef VERILATOR - $c("this->call_task();"); -`else - call_task(); -`endif - end - else if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= '0; + // Single and multiline if + if (cyc==3) $write(""); + if (cyc==3) + begin + $write(""); + end + // Single and multiline else + if (cyc==3) ; else $write(""); + if (cyc==3) ; + else + begin + $write(""); + end + // Single and multiline if else + if (cyc==3) $write(""); else $write(""); + if (cyc==3) + begin + $write(""); + end + else + begin + $write(""); + end + // multiline elseif + if (cyc==3) + begin + $write(""); + end + else if (cyc==4) + begin + $write(""); + end + else if (cyc==5) + begin + $write(""); + end + else + begin + $write(""); + end + // Single and multiline while + while (0); + while (0) begin + $write(""); end - end + do ; while (0); + do begin + $write(""); + end while (0); + //=== + // Task and complicated + if (cyc==3) begin + toggle <= '1; + end + else if (cyc==5) begin +`ifdef VERILATOR + $c("this->call_task();"); +`else + call_task(); +`endif + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - task call_task; - /* verilator public */ - t1.center_task(1'b1); - endtask + task call_task; + /* verilator public */ + t1.center_task(1'b1); + endtask endmodule module alpha (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; - always @ (posedge clk) begin - if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) - $write(""); - // t.a1 and t.a2 collapse to a count of 2 - end - if (toggle) begin // *** t_cover_line.vlt turns this off - $write(""); // CHECK_COVER_MISSING(0) - // This doesn't even get added + // Inputs + clk, toggle + ); + input clk; + input toggle; + always @ (posedge clk) begin + if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) + $write(""); + // t.a1 and t.a2 collapse to a count of 2 + end + if (toggle) begin // *** t_cover_line.vlt turns this off + $write(""); // CHECK_COVER_MISSING(0) + // This doesn't even get added `ifdef ATTRIBUTE - // verilator coverage_block_off + // verilator coverage_block_off `endif - end - end + end + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - $write(""); // Always covered - if (0) begin // CHECK_COVER(0,"top.t.b*",0) - // Make sure that we don't optimize away zero buckets - $write(""); - end - if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) - // t.b1 and t.b2 collapse to a count of 2 - $write(""); - end - if (toggle) begin : block - // This doesn't + always @ (posedge clk) begin + $write(""); // Always covered + if (0) begin // CHECK_COVER(0,"top.t.b*",0) + // Make sure that we don't optimize away zero buckets + $write(""); + end + if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) + // t.b1 and t.b2 collapse to a count of 2 + $write(""); + end + if (toggle) begin : block + // This doesn't `ifdef ATTRIBUTE - // verilator coverage_block_off + // verilator coverage_block_off `endif - begin end // *** t_cover_line.vlt turns this off (so need begin/end) - if (1) begin end // CHECK_COVER_MISSING(0) - $write(""); // CHECK_COVER_MISSING(0) - end - end + begin end // *** t_cover_line.vlt turns this off (so need begin/end) + if (1) begin end // CHECK_COVER_MISSING(0) + $write(""); // CHECK_COVER_MISSING(0) + end + end endmodule class Cls; - bit m_toggle; - function new(bit toggle); - m_toggle = toggle; - if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) - $write(""); - end - endfunction - static function void fstatic(bit toggle); - if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) - $write(""); - end - endfunction - function void fauto(); - if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) - $write(""); - end - endfunction + bit m_toggle; + function new(bit toggle); + m_toggle = toggle; + if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) + $write(""); + end + endfunction + static function void fstatic(bit toggle); + if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) + $write(""); + end + endfunction + function void fauto(); + if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) + $write(""); + end + endfunction endclass module tsk (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - center_task(1'b0); - end + always @ (posedge clk) begin + center_task(1'b0); + end - task automatic center_task; - input external; - begin - if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) - $write(""); - end - if (external) begin // CHECK_COVER(0,"top.t.t1",1) - $write("[%0t] Got external pulse\n", $time); - end + task automatic center_task; + input external; + begin + if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) + $write(""); end - begin - Cls c; - c = new(1'b1); - c.fauto(); - Cls::fstatic(1'b1); + if (external) begin // CHECK_COVER(0,"top.t.t1",1) + $write("[%0t] Got external pulse\n", $time); end - endtask + end + begin + Cls c; + c = new(1'b1); + c.fauto(); + Cls::fstatic(1'b1); + end + endtask endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); - input clk; - input toggle; + // Inputs + clk, toggle + ); + input clk; + input toggle; - // verilator coverage_off - always @ (posedge clk) begin - if (toggle) begin - $write(""); // CHECK_COVER_MISSING(0) - // because under coverage_module_off - end - end - // verilator coverage_on - always @ (posedge clk) begin - if (toggle) begin - // because under coverage_module_off - $write(""); - if (0) ; // CHECK_COVER(0,"top.t.o1",1) - end - end + // verilator coverage_off + always @ (posedge clk) begin + if (toggle) begin + $write(""); // CHECK_COVER_MISSING(0) + // because under coverage_module_off + end + end + // verilator coverage_on + always @ (posedge clk) begin + if (toggle) begin + // because under coverage_module_off + $write(""); + if (0) ; // CHECK_COVER(0,"top.t.o1",1) + end + end endmodule module tab (input clk); - bit [3:0] cyc4; - int decoded; + bit [3:0] cyc4; + int decoded; - always @ (posedge clk) begin - case (cyc4) - 1: decoded = 10; - 2: decoded = 20; - 3: decoded = 30; - 4: decoded = 40; - 5: decoded = 50; - default: decoded = 0; - endcase - end + always @ (posedge clk) begin + case (cyc4) + 1: decoded = 10; + 2: decoded = 20; + 3: decoded = 30; + 4: decoded = 40; + 5: decoded = 50; + default: decoded = 0; + endcase + end - always @ (posedge clk) begin - cyc4 <= cyc4 + 1; - end + always @ (posedge clk) begin + cyc4 <= cyc4 + 1; + end endmodule module par(); - localparam int CALLS_FUNC = param_func(1); + localparam int CALLS_FUNC = param_func(1); - // We don't currently count elaboration time use towards coverage. This - // seems safer for functions used both at elaboration time and not - but may - // revisit this. - function automatic int param_func(int i); - if (i == 0) begin - i = 99; // Uncovered - end - else begin - i = i + 1; - end - return i; - endfunction + // We don't currently count elaboration time use towards coverage. This + // seems safer for functions used both at elaboration time and not - but may + // revisit this. + function automatic int param_func(int i); + if (i == 0) begin + i = 99; // Uncovered + end + else begin + i = i + 1; + end + return i; + endfunction endmodule package my_pkg; - int x = 1 ? 1 : 0; + int x = 1 ? 1 : 0; endpackage class Getter1; - function int get_1; - return 1; - endfunction + function int get_1; + return 1; + endfunction endclass module cond(input logic clk, input int cyc); - logic a, b, c, d, e, f, g, h, k, l, m; - logic [5:0] tab; - typedef logic [7:0] arr_t[1:0]; - arr_t data[1:0]; - Getter1 getter1 = new; - string s; + logic a, b, c, d, e, f, g, h, k, l, m; + logic [5:0] tab; + typedef logic [7:0] arr_t[1:0]; + arr_t data[1:0]; + Getter1 getter1 = new; + string s; - struct packed { - logic unsigned [15:0] a; - logic unsigned [15:0] b; - } pstruct; + struct packed { + logic unsigned [15:0] a; + logic unsigned [15:0] b; + } pstruct; - function logic func_side_effect; - $display("SIDE EFFECT"); - return 1; - endfunction + function logic func_side_effect; + $display("SIDE EFFECT"); + return 1; + endfunction - function arr_t get_arr; - arr_t arr; - return arr; - endfunction + function arr_t get_arr; + arr_t arr; + return arr; + endfunction - assign a = (cyc == 0) ? clk : 1'bz; - assign b = (cyc == 1) ? clk : 0; - assign c = func_side_effect() ? clk : 0; - always @(posedge clk) begin - d = (cyc % 3 == 0) ? 1 : 0; - s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); - end - assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; + assign a = (cyc == 0) ? clk : 1'bz; + assign b = (cyc == 1) ? clk : 0; + assign c = func_side_effect() ? clk : 0; + always @(posedge clk) begin + d = (cyc % 3 == 0) ? 1 : 0; + s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); + end + assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; - // ternary operator in condition shouldn't be included to the coverae - assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; - // the same as in index - assign tab[clk ? 1 : 0] = 1; - assign m = tab[clk ? 3 : 4]; + // ternary operator in condition shouldn't be included to the coverae + assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; + // the same as in index + assign tab[clk ? 1 : 0] = 1; + assign m = tab[clk ? 3 : 4]; - for (genvar i = 0; i < 2; i++) begin - assign g = clk ? 1 : 0; - end + for (genvar i = 0; i < 2; i++) begin + assign g = clk ? 1 : 0; + end - always begin - if (cyc == 5) h = cyc > 5 ? 1 : 0; - else h = 1; + always begin + if (cyc == 5) h = cyc > 5 ? 1 : 0; + else h = 1; - data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); + data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); - // ternary operator in conditions should be skipped - for (int i = 0; (i < 5) ? 1 : 0; i++) begin - k = 1'(i); - end - for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin - k = 1'(i); - end + // ternary operator in conditions should be skipped + for (int i = 0; (i < 5) ? 1 : 0; i++) begin + k = 1'(i); + end + for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin + k = 1'(i); + end - if (k ? 1 : 0) k = 1; - else k = 0; - end + if (k ? 1 : 0) k = 1; + else k = 0; + end - assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; - assign pstruct.b = 16'd0; + assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; + assign pstruct.b = 16'd0; - always @(posedge clk) begin - if (cyc == 2) $display("%08x", pstruct); - end + always @(posedge clk) begin + if (cyc == 2) $display("%08x", pstruct); + end endmodule diff --git a/test_regress/t/t_cover_line_expr.out b/test_regress/t/t_cover_line_expr.out index df46e1e92..b74986880 100644 --- a/test_regress/t/t_cover_line_expr.out +++ b/test_regress/t/t_cover_line_expr.out @@ -7,68 +7,64 @@ %000001 class cls; -000001 point: type=line comment=block hier=top.$unit::cls__Vclpkg - rand int x; + rand int x; endclass - module t (/*AUTOARG*/ - // Inputs - clk - ); + module t ( + input clk + ); - input clk; - - integer cyc; -%000001 initial cyc=1; + integer cyc; +%000001 initial cyc = 1; -000001 point: type=line comment=block hier=top.t - logic [63:32] cyc2; -%000001 always_comb cyc2 = cyc; + logic [63:32] cyc2; +%000001 always_comb cyc2 = cyc; -000001 point: type=line comment=block hier=top.t - integer some_int; - integer other_int; - logic some_bool; + integer some_int; + integer other_int; + logic some_bool; - wire t1 = cyc[0]; - wire t2 = cyc[1]; - wire t3 = cyc[2]; - wire t4 = cyc[3]; + wire t1 = cyc[0]; + wire t2 = cyc[1]; + wire t3 = cyc[2]; + wire t4 = cyc[3]; - localparam bit ONE = 1'b1; - localparam bit ZERO = 1'b0; + localparam bit ONE = 1'b1; + localparam bit ZERO = 1'b0; -%000009 function automatic bit invert(bit x); +%000009 function automatic bit invert(bit x); -000009 point: type=line comment=block hier=top.t -%000009 return ~x; +%000009 return ~x; -000009 point: type=line comment=block hier=top.t -000004 point: type=expr comment=(x==0) => 1 hier=top.t -000005 point: type=expr comment=(x==1) => 0 hier=top.t - endfunction + endfunction -%000009 function automatic bit and_oper(bit a, bit b); +%000009 function automatic bit and_oper(bit a, bit b); -000009 point: type=line comment=block hier=top.t -%000009 return a & b; +%000009 return a & b; -000009 point: type=line comment=block hier=top.t -000004 point: type=expr comment=(a==0) => 0 hier=top.t -000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t -000005 point: type=expr comment=(b==0) => 0 hier=top.t - endfunction + endfunction - localparam int NUM_INTFS = 4; - intf the_intfs [NUM_INTFS-1:0] (); - genvar intf_i; -%000004 for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin + localparam int NUM_INTFS = 4; + intf the_intfs[NUM_INTFS-1:0] (); + genvar intf_i; +%000004 for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin -000004 point: type=line comment=block hier=top.t -%000004 always_comb the_intfs[intf_i].t = cyc[intf_i]; +%000004 always_comb the_intfs[intf_i].t = cyc[intf_i]; -000004 point: type=line comment=block hier=top.t - end + end -%000009 always @ (posedge clk) begin +%000009 always @(posedge clk) begin -000009 point: type=line comment=block hier=top.t -%000009 cyc <= cyc + 1; +%000009 cyc <= cyc + 1; -000009 point: type=line comment=block hier=top.t -%000005 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000005 point: type=branch comment=else hier=top.t +%000005 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t @@ -76,8 +72,8 @@ -000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000005 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000005 point: type=branch comment=else hier=top.t +%000005 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t @@ -85,8 +81,8 @@ -000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000005 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000005 point: type=branch comment=else hier=top.t +%000005 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t @@ -94,8 +90,8 @@ -000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000005 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000005 point: type=branch comment=else hier=top.t +%000005 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t @@ -103,38 +99,38 @@ -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000007 if (t3 && (t1 == t2)) $write(""); --000007 point: type=branch comment=else hier=top.t +-000005 point: type=branch comment=else hier=top.t +%000007 if (t3 && (t1 == t2)) $write(""); -000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000007 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: type=branch comment=else hier=top.t +-000007 point: type=branch comment=else hier=top.t +%000007 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000007 point: type=branch comment=if hier=top.t -%000009 some_int <= (t2 || t3) ? 345 : 567; +-000002 point: type=branch comment=else hier=top.t +%000009 some_int <= (t2 || t3) ? 345 : 567; -000009 point: type=line comment=block hier=top.t -000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000004 point: type=expr comment=(t3==1) => 1 hier=top.t -000006 point: type=branch comment=cond_then hier=top.t -000003 point: type=branch comment=cond_else hier=top.t -%000009 some_bool <= t1 && t2; +%000009 some_bool <= t1 && t2; -000009 point: type=line comment=block hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -%000007 if (t1 & t2) $write(""); --000007 point: type=branch comment=else hier=top.t +%000007 if (t1 & t2) $write(""); -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000005 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000005 point: type=branch comment=else hier=top.t +-000007 point: type=branch comment=else hier=top.t +%000005 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t @@ -142,53 +138,55 @@ -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000005 if (t1 ^ t2) $write(""); --000004 point: type=branch comment=else hier=top.t +-000005 point: type=branch comment=else hier=top.t +%000005 if (t1 ^ t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: type=branch comment=if hier=top.t -%000007 if (~(t1 & t2)) $write(""); +-000004 point: type=branch comment=else hier=top.t +%000007 if (~(t1 & t2)) $write(""); +-000007 point: type=branch comment=if hier=top.t -000002 point: type=branch comment=else hier=top.t -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 1 hier=top.t --000007 point: type=branch comment=if hier=top.t -%000006 if (t1 -> t2) $write(""); --000003 point: type=branch comment=else hier=top.t +%000006 if (t1 -> t2) $write(""); -000004 point: type=expr comment=(t1==0) => 1 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: type=expr comment=(t2==1) => 1 hier=top.t -000006 point: type=branch comment=if hier=top.t -%000005 if (t1 <-> t2) $write(""); --000005 point: type=branch comment=else hier=top.t +-000003 point: type=branch comment=else hier=top.t +%000005 if (t1 <-> t2) $write(""); -000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000004 point: type=branch comment=if hier=top.t -%000008 if (&cyc[2:0]) $write(""); +-000005 point: type=branch comment=else hier=top.t +%000008 if (&cyc[2:0]) $write(""); +-000001 point: type=branch comment=if hier=top.t -000008 point: type=branch comment=else hier=top.t -000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t --000001 point: type=branch comment=if hier=top.t -%000009 if (&cyc[3:2]) $write(""); +%000009 if (&cyc[3:2]) $write(""); +-000000 point: type=branch comment=if hier=top.t -000009 point: type=branch comment=else hier=top.t -000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t --000000 point: type=branch comment=if hier=top.t -%000008 if (|cyc[2:0]) $write(""); +%000008 if (|cyc[2:0]) $write(""); +-000008 point: type=branch comment=if hier=top.t -000001 point: type=branch comment=else hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t --000008 point: type=branch comment=if hier=top.t -%000005 if (^cyc[2:0]) $write(""); +%000005 if (^cyc[2:0]) $write(""); +-000005 point: type=branch comment=if hier=top.t -000004 point: type=branch comment=else hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t @@ -198,105 +196,104 @@ -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: type=branch comment=if hier=top.t -%000009 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: type=branch comment=else hier=top.t +%000009 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t -000009 point: type=branch comment=if hier=top.t -%000007 if (t1 & t2 & 1'b1) $write(""); --000007 point: type=branch comment=else hier=top.t +-000000 point: type=branch comment=else hier=top.t +%000007 if (t1 & t2 & 1'b1) $write(""); -000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: type=branch comment=else hier=top.t +-000007 point: type=branch comment=else hier=top.t +%000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000000 point: type=branch comment=if hier=top.t -%000007 if (t1 & t2 & ONE) $write(""); --000007 point: type=branch comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t +%000007 if (t1 & t2 & ONE) $write(""); -000000 point: type=expr comment=(ONE==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000009 if (t1 & t2 & ZERO) $write(""); --000009 point: type=branch comment=else hier=top.t +-000007 point: type=branch comment=else hier=top.t +%000009 if (t1 & t2 & ZERO) $write(""); -000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000000 point: type=branch comment=if hier=top.t -%000005 if (t1 && t2) begin +-000009 point: type=branch comment=else hier=top.t +%000005 if (t1 && t2) begin -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=line comment=elsif hier=top.t -%000002 $write(""); +%000002 $write(""); -000002 point: type=line comment=elsif hier=top.t -%000005 end else if (t1 || t2) begin + end +%000005 else if (t1 || t2) begin -000005 point: type=branch comment=if hier=top.t -000002 point: type=branch comment=else hier=top.t -000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: type=expr comment=(t1==1) => 1 hier=top.t -000002 point: type=expr comment=(t2==1) => 1 hier=top.t -%000005 $write(""); +%000005 $write(""); -000005 point: type=branch comment=if hier=top.t - end -%000007 if (invert(t1) && t2) $write(""); --000007 point: type=branch comment=else hier=top.t + end +%000007 if (invert(t1) && t2) $write(""); -000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t -000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000007 if (and_oper(t1, t2)) $write(""); -000007 point: type=branch comment=else hier=top.t +%000007 if (and_oper(t1, t2)) $write(""); -000002 point: type=branch comment=if hier=top.t -%000007 if (t2 && t3) begin -000007 point: type=branch comment=else hier=top.t +%000007 if (t2 && t3) begin -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: type=expr comment=(t3==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t -%000001 if (t1 && t2) $write(""); --000001 point: type=branch comment=if hier=top.t --000001 point: type=branch comment=else hier=top.t +-000007 point: type=branch comment=else hier=top.t +%000001 if (t1 && t2) $write(""); -000001 point: type=expr comment=(t1==0) => 0 hier=top.t -000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end -%000009 if (0 == 1) begin --000009 point: type=branch comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t + end +%000009 if (0 == 1) begin -000000 point: type=branch comment=if hier=top.t -%000000 for (int loop_var = 0; loop_var < 1; loop_var++) begin +-000009 point: type=branch comment=else hier=top.t +%000000 for (int loop_var = 0; loop_var < 1; loop_var++) begin -000000 point: type=branch comment=if hier=top.t -000000 point: type=line comment=block hier=top.t -%000000 if (cyc[loop_var] && t2) $write(""); --000000 point: type=branch comment=if hier=top.t +%000000 if (cyc[loop_var] && t2) $write(""); -000000 point: type=branch comment=else hier=top.t -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: type=expr comment=(t2==0) => 0 hier=top.t - end - end - // stop at the first layer even if there's more to find -%000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: type=branch comment=else hier=top.t +-000000 point: type=branch comment=if hier=top.t + end + end + // stop at the first layer even if there's more to find +%000007 if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); +-000007 point: type=branch comment=if hier=top.t -000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t --000007 point: type=branch comment=if hier=top.t - // impossible branches and redundant terms -%000008 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000008 point: type=branch comment=else hier=top.t +-000002 point: type=branch comment=else hier=top.t + // impossible branches and redundant terms +%000008 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t @@ -304,18 +301,19 @@ -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000001 point: type=branch comment=if hier=top.t -%000008 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000008 point: type=branch comment=else hier=top.t +%000008 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); +-000001 point: type=branch comment=if hier=top.t -000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t --000001 point: type=branch comment=if hier=top.t - // demonstrate current limitations of term matching scheme -%000008 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000008 point: type=branch comment=else hier=top.t + // demonstrate current limitations of term matching scheme +%000008 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); +-000001 point: type=branch comment=if hier=top.t -000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t @@ -324,37 +322,28 @@ -000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t --000001 point: type=branch comment=if hier=top.t - //verilator coverage_off - if (t1 && t2) $write(""); - //verilator coverage_on -%000005 if ((~t1 && t2) --000005 point: type=branch comment=else hier=top.t --000004 point: type=branch comment=if hier=top.t -%000004 || +-000008 point: type=branch comment=else hier=top.t + //verilator coverage_off + if (t1 && t2) $write(""); + //verilator coverage_on +%000005 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t -%000004 (~t3 && t4)) $write(""); -000004 point: type=branch comment=if hier=top.t - // intentionally testing wonkified expression terms -%000007 if ( --000007 point: type=branch comment=else hier=top.t --000002 point: type=branch comment=if hier=top.t - cyc[ - 0 -%000005 ] & +-000005 point: type=branch comment=else hier=top.t + // intentionally testing wonkified expression terms +%000007 if (cyc[0] & cyc[1]) $write(""); -000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t -000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t - cyc -%000002 [1]) $write(""); -000002 point: type=branch comment=if hier=top.t - // for now each ternary condition is considered in isolation -%000009 other_int <= t1 ? t2 ? 1 : 2 : 3; +-000007 point: type=branch comment=else hier=top.t + // for now each ternary condition is considered in isolation +%000009 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: type=expr comment=(t1==0) => 0 hier=top.t -000005 point: type=expr comment=(t1==1) => 1 hier=top.t -000005 point: type=branch comment=cond_then hier=top.t @@ -362,100 +351,109 @@ -000002 point: type=branch comment=cond_then hier=top.t -000003 point: type=branch comment=cond_else hier=top.t -000009 point: type=line comment=block hier=top.t - // no expression coverage for multi-bit expressions -%000009 if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); --000009 point: type=branch comment=else hier=top.t + // no expression coverage for multi-bit expressions +%000009 if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); -000000 point: type=branch comment=if hier=top.t - // truth table is too large -%000005 if (^cyc[6:0]) $write(""); --000004 point: type=branch comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t + // truth table is too large +%000005 if (^cyc[6:0]) $write(""); -000005 point: type=branch comment=if hier=top.t - // this one is too big even for t_cover_expr_max -%000005 if (^cyc) $write(""); -000004 point: type=branch comment=else hier=top.t + // this one is too big even for t_cover_expr_max +%000005 if (^cyc) $write(""); -000005 point: type=branch comment=if hier=top.t -%000008 if (cyc==9) begin +-000004 point: type=branch comment=else hier=top.t +%000008 if (cyc == 9) begin +-000001 point: type=branch comment=if hier=top.t -000008 point: type=branch comment=else hier=top.t +%000001 $write("*-* All Finished *-*\n"); -000001 point: type=branch comment=if hier=top.t -%000001 $write("*-* All Finished *-*\n"); +%000001 $finish; -000001 point: type=branch comment=if hier=top.t -%000001 $finish; --000001 point: type=branch comment=if hier=top.t - end end + end - 000010 always_comb begin + 000010 always_comb begin +000010 point: type=line comment=block hier=top.t -%000008 if (t1 && t2) $write(""); --000008 point: type=branch comment=else hier=top.t +%000008 if (t1 && t2) $write(""); -000005 point: type=expr comment=(t1==0) => 0 hier=top.t -000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: type=expr comment=(t2==0) => 0 hier=top.t -000002 point: type=branch comment=if hier=top.t - end +-000008 point: type=branch comment=else hier=top.t + end - logic ta, tb, tc; -%000001 initial begin + logic ta, tb, tc; +%000001 initial begin -000001 point: type=line comment=block hier=top.t -%000001 automatic cls obj = new; +%000001 automatic cls obj = new; -000001 point: type=line comment=block hier=top.t -%000001 automatic cls null_obj = null; +%000001 automatic cls null_obj = null; -000001 point: type=line comment=block hier=top.t -%000001 automatic int q[5]; +%000001 automatic int q[5]; -000001 point: type=line comment=block hier=top.t -%000001 automatic int qv[$]; +%000001 automatic int qv[$]; -000001 point: type=line comment=block hier=top.t -%000001 q = '{1, 2, 2, 4, 3}; +%000001 q = '{1, 2, 2, 4, 3}; -000001 point: type=line comment=block hier=top.t - // lambas not handled - // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) - // tracing_off does not work around the bug -%000001 qv = q.find_first with (item[0] & item[1]); + // lambas not handled + // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) + // tracing_off does not work around the bug +%000001 qv = q.find_first with (item[0] & item[1]); -000001 point: type=line comment=block hier=top.t -%000001 ta = '1; +%000001 ta = '1; -000001 point: type=line comment=block hier=top.t -%000001 tb = '0; +%000001 tb = '0; -000001 point: type=line comment=block hier=top.t -%000001 tc = '0; +%000001 tc = '0; -000001 point: type=line comment=block hier=top.t -%000003 while (ta || tb || tc) begin +%000003 while (ta || tb || tc) begin -000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: type=expr comment=(ta==1) => 1 hier=top.t -000000 point: type=expr comment=(tb==1) => 1 hier=top.t -000000 point: type=expr comment=(tc==1) => 1 hier=top.t -000003 point: type=line comment=block hier=top.t -%000003 tc = tb; +%000003 tc = tb; -000003 point: type=line comment=block hier=top.t -%000003 tb = ta; +%000003 tb = ta; -000003 point: type=line comment=block hier=top.t -%000003 ta = '0; +%000003 ta = '0; -000003 point: type=line comment=block hier=top.t - end -%000001 if (!bit'(obj.randomize() with {x < 100;})) $write(""); --000000 point: type=branch comment=else hier=top.t --000001 point: type=branch comment=if hier=top.t -%000001 if (null_obj != null && null_obj.x == 5) $write(""); --000001 point: type=branch comment=else hier=top.t --000000 point: type=branch comment=if hier=top.t end +%000001 if (!bit'(obj.randomize() with {x < 100;})) $write(""); +-000001 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t +%000001 if (null_obj != null && null_obj.x == 5) $write(""); +-000000 point: type=branch comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t + end - sub the_sub_1 (.p(t1), .q(t2)); - sub the_sub_2 (.p(t3), .q(t4)); - // TODO -- non-process expressions - sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); + sub the_sub_1 ( + .p(t1), + .q(t2) + ); + sub the_sub_2 ( + .p(t3), + .q(t4) + ); + // TODO -- non-process expressions + sub the_sub_3 ( + .p(t1 ? t2 : t3), + .q(t4) + ); - // TODO - // pragma for expr coverage off / on - // investigate cover point sorting in annotated source - // consider reporting don't care terms - // - // Branches which are statically impossible to reach are still reported. - // E.g. - // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t - // These could potentially be pruned, but they currently follow suit for - // what branch coverage does. Perhaps a switch should be added to not - // count statically impossible things. + // TODO + // pragma for expr coverage off / on + // investigate cover point sorting in annotated source + // consider reporting don't care terms + // + // Branches which are statically impossible to reach are still reported. + // E.g. + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // These could potentially be pruned, but they currently follow suit for + // what branch coverage does. Perhaps a switch should be added to not + // count statically impossible things. endmodule @@ -464,19 +462,19 @@ input q ); - 000030 always_comb begin + 000030 always_comb begin +000030 point: type=line comment=block hier=top.t.the_sub_* -~000028 if (p && q) $write(""); -+000028 point: type=branch comment=else hier=top.t.the_sub_* +~000028 if (p && q) $write(""); +000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* -000002 point: type=branch comment=if hier=top.t.the_sub_* - end ++000028 point: type=branch comment=else hier=top.t.the_sub_* + end endmodule - interface intf(); - logic t; + interface intf (); + logic t; endinterface diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index 57c616be0..06582613c 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -93,16 +93,16 @@ $timescale 1ps $end $var wire 1 H! l $end $var wire 1 >! m $end $var wire 6 2 tab [5:0] $end - $var wire 8 h data[0][0] [7:0] $end - $var wire 8 i data[0][1] [7:0] $end - $var wire 8 j data[1][0] [7:0] $end - $var wire 8 k data[1][1] [7:0] $end + $var wire 8 h data[1][1] [7:0] $end + $var wire 8 i data[1][0] [7:0] $end + $var wire 8 j data[0][1] [7:0] $end + $var wire 8 k data[0][0] [7:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__315_block [31:0] $end $var wire 32 l pstruct [31:0] $end $var wire 32 % vlCoverageLineTrace_t_cover_line__323_block [31:0] $end $var wire 32 m vlCoverageLineTrace_t_cover_line__328_block [31:0] $end - $var wire 8 & get_arr__Vstatic__arr[0] [7:0] $end - $var wire 8 ' get_arr__Vstatic__arr[1] [7:0] $end + $var wire 8 & get_arr__Vstatic__arr[1] [7:0] $end + $var wire 8 ' get_arr__Vstatic__arr[0] [7:0] $end $var wire 32 : vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end $var wire 32 ; vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end $var wire 32 < vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end @@ -360,8 +360,8 @@ b00000000000000000000000000000001 ` b00000000000000000000000000000001 a b00000000000000000000000000000001 b b00000000000000000000000000000001 d -b00000010 h -b00000001 i +b00000001 j +b00000010 k b00000000000000110000000000000000 l b00000000000000000000000000000001 n b00000000000000000000000000000001 o @@ -425,8 +425,8 @@ b00000000000000000000000000000010 ` b00000000000000000000000000000010 a b00000000000000000000000000000010 b b00000000000000000000000000000010 d -b00000000 h -b00000000 i +b00000000 j +b00000000 k b00000000000000000000000000000010 m b00000000000000000000000000000010 n b00000000000000000000000000000010 o diff --git a/test_regress/t/t_cover_line_wide_ternary.out b/test_regress/t/t_cover_line_wide_ternary.out index ddbc770fd..b7e42464c 100644 --- a/test_regress/t/t_cover_line_wide_ternary.out +++ b/test_regress/t/t_cover_line_wide_ternary.out @@ -5,39 +5,36 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 - interface intf(); - logic foo; - logic [31:0] bar; - logic [127:0] baz; + interface intf (); + logic foo; + logic [31:0] bar; + logic [127:0] baz; endinterface - module t (/*AUTOARG*/ - // Inputs - clk - ); + module t ( + input clk + ); - input clk; - - integer cyc; -%000001 initial cyc=1; + integer cyc; +%000001 initial cyc = 1; -000001 point: type=line comment=block hier=top.t - intf intfs [2] (); - intf intf_sel_ff(); - intf intf_sel_comb(); - intf intf_sel_assign(); + intf intfs[2] (); + intf intf_sel_ff (); + intf intf_sel_comb (); + intf intf_sel_assign (); -%000001 always_comb begin +%000001 always_comb begin -000001 point: type=line comment=block hier=top.t -%000001 intfs[0].bar = 123; +%000001 intfs[0].bar = 123; -000001 point: type=line comment=block hier=top.t -%000001 intfs[1].bar = 456; +%000001 intfs[1].bar = 456; -000001 point: type=line comment=block hier=top.t - end + end -%000009 always_ff @ (posedge clk) begin +%000009 always_ff @(posedge clk) begin -000009 point: type=line comment=block hier=top.t -%000009 {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= +%000009 {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= -000009 point: type=line comment=block hier=top.t %000005 cyc[0] ? -000005 point: type=branch comment=cond_then hier=top.t @@ -46,11 +43,11 @@ -000004 point: type=branch comment=cond_else hier=top.t %000004 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -000004 point: type=branch comment=cond_else hier=top.t - end + end - 000010 always_comb begin + 000010 always_comb begin +000010 point: type=line comment=block hier=top.t - 000010 {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = + 000010 {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = +000010 point: type=line comment=block hier=top.t %000005 cyc[0] ? -000005 point: type=branch comment=cond_then hier=top.t @@ -59,9 +56,9 @@ -000005 point: type=branch comment=cond_else hier=top.t %000005 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -000005 point: type=branch comment=cond_else hier=top.t - end + end - assign + assign {intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} = %000005 cyc[0] ? -000005 point: type=branch comment=cond_then hier=top.t @@ -71,24 +68,24 @@ %000005 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -000005 point: type=branch comment=cond_else hier=top.t -%000009 always @ (posedge clk) begin +%000009 always @(posedge clk) begin -000009 point: type=line comment=block hier=top.t -%000009 cyc <= cyc + 1; +%000009 cyc <= cyc + 1; -000009 point: type=line comment=block hier=top.t -%000008 if (cyc==9) begin +%000008 if (cyc == 9) begin +-000001 point: type=branch comment=if hier=top.t -000008 point: type=branch comment=else hier=top.t --000001 point: type=branch comment=if hier=top.t -%000001 if (intf_sel_ff.bar != 123) $stop(); +%000001 if (intf_sel_ff.bar != 123) $stop(); -000001 point: type=line comment=else hier=top.t -%000001 if (intf_sel_comb.bar != 456) $stop(); +%000001 if (intf_sel_comb.bar != 456) $stop(); -000001 point: type=line comment=else hier=top.t -%000001 if (intf_sel_assign.bar != 456) $stop(); +%000001 if (intf_sel_assign.bar != 456) $stop(); -000001 point: type=line comment=else hier=top.t -%000001 $write("*-* All Finished *-*\n"); +%000001 $write("*-* All Finished *-*\n"); -000001 point: type=branch comment=if hier=top.t -%000001 $finish; +%000001 $finish; -000001 point: type=branch comment=if hier=top.t - end end + end endmodule diff --git a/test_regress/t/t_cover_line_wide_ternary.v b/test_regress/t/t_cover_line_wide_ternary.v index 53d8e2652..aa0fdeec7 100644 --- a/test_regress/t/t_cover_line_wide_ternary.v +++ b/test_regress/t/t_cover_line_wide_ternary.v @@ -4,60 +4,57 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface intf(); - logic foo; - logic [31:0] bar; - logic [127:0] baz; +interface intf (); + logic foo; + logic [31:0] bar; + logic [127:0] baz; endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; - integer cyc; - initial cyc=1; + intf intfs[2] (); + intf intf_sel_ff (); + intf intf_sel_comb (); + intf intf_sel_assign (); - intf intfs [2] (); - intf intf_sel_ff(); - intf intf_sel_comb(); - intf intf_sel_assign(); + always_comb begin + intfs[0].bar = 123; + intfs[1].bar = 456; + end - always_comb begin - intfs[0].bar = 123; - intfs[1].bar = 456; - end - - always_ff @ (posedge clk) begin - {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= + always_ff @(posedge clk) begin + {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; - end + end - always_comb begin - {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = + always_comb begin + {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; - end + end - assign + assign {intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} = cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==9) begin - if (intf_sel_ff.bar != 123) $stop(); - if (intf_sel_comb.bar != 456) $stop(); - if (intf_sel_assign.bar != 456) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 9) begin + if (intf_sel_ff.bar != 123) $stop(); + if (intf_sel_comb.bar != 456) $stop(); + if (intf_sel_assign.bar != 456) $stop(); + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule diff --git a/test_regress/t/t_cover_main.out b/test_regress/t/t_cover_main.out index 9b2f61600..37e5aa160 100644 --- a/test_regress/t/t_cover_main.out +++ b/test_regress/t/t_cover_main.out @@ -1,2 +1,2 @@ # SystemC::Coverage-3 -C 'ft/t_cover_main.vl9n4tlinepagev_line/toblockS9-11ht' 1 +C 'ft/t_cover_main.vl9n3tlinepagev_line/toblockS9-11ht' 1 diff --git a/test_regress/t/t_cover_main.v b/test_regress/t/t_cover_main.v index c80765137..a50d42787 100644 --- a/test_regress/t/t_cover_main.v +++ b/test_regress/t/t_cover_main.v @@ -6,8 +6,8 @@ module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_sva_notflat.v b/test_regress/t/t_cover_sva_notflat.v index fff88f2c5..d9b239855 100644 --- a/test_regress/t/t_cover_sva_notflat.v +++ b/test_regress/t/t_cover_sva_notflat.v @@ -4,57 +4,59 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg toggle; - integer cyc; initial cyc=1; + reg toggle; + integer cyc; + initial cyc = 1; - Test suba (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); - Test subb (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); - Test subc (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + Test suba ( /*AUTOINST*/ + // Inputs + .clk(clk), + .toggle(toggle), + .cyc(cyc[31:0]) + ); + Test subb ( /*AUTOINST*/ + // Inputs + .clk(clk), + .toggle(toggle), + .cyc(cyc[31:0]) + ); + Test subc ( /*AUTOINST*/ + // Inputs + .clk(clk), + .toggle(toggle), + .cyc(cyc[31:0]) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==9) begin - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc == 9) begin end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module Test - ( - input clk, - input toggle, - input [31:0] cyc - ); +module Test ( + input clk, + input toggle, + input [31:0] cyc +); - // Don't flatten out these modules please: - // verilator no_inline_module + // Don't flatten out these modules please: + // verilator no_inline_module - // Labeled cover - cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + // Labeled cover + cyc_eq_5 : + cover property (@(posedge clk) cyc == 5) $display("*COVER: Cyc==5"); endmodule diff --git a/test_regress/t/t_cover_toggle.out b/test_regress/t/t_cover_toggle.out index ec84bf328..51ab8c553 100644 --- a/test_regress/t/t_cover_toggle.out +++ b/test_regress/t/t_cover_toggle.out @@ -8,253 +8,253 @@ typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); + // Inputs + clk, check_real, check_array_real, check_string + ); -~000010 input clk; - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 +~000010 input clk; + input real check_real; // Check issue #2741 + input real check_array_real [1:0]; + input string check_string; // Check issue #2766 - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; + typedef struct packed { + union packed { + logic ua; + logic ub; + } u; + logic b; + } str_t; -%000001 reg toggle; initial toggle='0; +%000001 reg toggle; initial toggle='0; - logic _under_toggle = toggle; // For --coverage-underscore + logic _under_toggle = toggle; // For --coverage-underscore -%000001 str_t stoggle; initial stoggle='0; +%000001 str_t stoggle; initial stoggle='0; -~000010 str_logic strl; initial strl='0; +~000010 str_logic strl; initial strl='0; - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; + union { + real val1; // TODO use bit [7:0] here + real val2; // TODO use bit [3:0] here + } utoggle; - const reg aconst = '0; + const reg aconst = '0; -%000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; +%000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; - integer cyc; initial cyc=1; -%000006 wire [7:0] cyc_copy = cyc[7:0]; -%000001 wire toggle_up; + integer cyc; initial cyc=1; +%000006 wire [7:0] cyc_copy = cyc[7:0]; +%000001 wire toggle_up; - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; + typedef struct { + int q[$]; + } str_queue_t; + str_queue_t str_queue; - typedef struct packed { - // verilator lint_off ASCRANGE - bit [3:5] x; - // verilator lint_on ASCRANGE - bit [0:0] y; - } str_bit_t; -%000001 str_bit_t str_bit; -%000001 str_bit_t [5:2] str_bit_arr; + typedef struct packed { + // verilator lint_off ASCRANGE + bit [3:5] x; + // verilator lint_on ASCRANGE + bit [0:0] y; + } str_bit_t; +%000001 str_bit_t str_bit; +%000001 str_bit_t [5:2] str_bit_arr; - assign strl.a = clk; + assign strl.a = clk; - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + alpha a1 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + alpha a2 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle_up (toggle_up)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#(1) p1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#() p2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - mod_struct i_mod_struct (/*AUTOINST*/ - // Inputs - .input_struct (strl)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); -%000001 reg [1:0] memory[121:110]; +%000001 reg [1:0] memory[121:110]; - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) + wire [1023:0] largeish = {992'h0, cyc}; + // CHECK_COVER_MISSING(-1) - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - str_bit.x <= '1; - str_bit.y <= '1; - str_bit_arr[4].x <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - str_bit.x[3] <= 0; - str_bit.y[0] <= 0; - str_bit_arr[4].x[3] <= 0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + utoggle.val1 <= real'(cyc[7:0]); + ptoggle[0][0] <= toggle; + if (cyc == 3) begin + str_queue.q.push_back(1); + toggle <= '1; + str_bit.x <= '1; + str_bit.y <= '1; + str_bit_arr[4].x <= '1; end - end + if (cyc == 4) begin + if (str_queue.q.size() != 1) $stop; + toggle <= '0; + str_bit.x[3] <= 0; + str_bit.y[0] <= 0; + str_bit_arr[4].x[3] <= 0; + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); + // Outputs + toggle_up, + // Inputs + clk, toggle, cyc_copy + ); - // t.a1 and t.a2 collapse to a count of 2 + // t.a1 and t.a2 collapse to a count of 2 - 000020 input clk; + 000020 input clk; -%000002 input toggle; - // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) - // (t.a1 and t.a2) +%000002 input toggle; + // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) + // (t.a1 and t.a2) -~000012 input [7:0] cyc_copy; - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) - // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) - // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) - // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) - // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) - // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) - // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) - // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) - // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) +~000012 input [7:0] cyc_copy; + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) + // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) + // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) + // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) + // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) + // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) + // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) + // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) + // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) -%000002 reg toggle_internal; - // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) - // (t.a1 and t.a2) +%000002 reg toggle_internal; + // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) + // (t.a1 and t.a2) -%000002 output reg toggle_up; - // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) - // (t.a1 and t.a2) +%000002 output reg toggle_up; + // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) + // (t.a1 and t.a2) - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end + always @ (posedge clk) begin + toggle_internal <= toggle; + toggle_up <= toggle; + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); + // Inputs + clk, toggle_up + ); -~000010 input clk; +~000010 input clk; -%000001 input toggle_up; - // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) - // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) +%000001 input toggle_up; + // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) + // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end + always @ (posedge clk) begin + if (0 && toggle_up) begin end + end endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) + // verilator coverage_off + input clk; + // CHECK_COVER_MISSING(-1) - // verilator coverage_on -%000001 input toggle; - // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) - // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) + // verilator coverage_on +%000001 input toggle; + // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) + // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); -~000010 input clk; -%000001 input toggle; +~000010 input clk; +%000001 input toggle; -%000001 logic z; +%000001 logic z; - for (genvar i = 0; i < P; i++) begin -%000001 logic x; - always @ (posedge clk) begin - x <= toggle; + for (genvar i = 0; i < P; i++) begin +%000001 logic x; + always @ (posedge clk) begin + x <= toggle; + end + for (genvar j = 0; j < 3; j++) begin +%000002 logic [2:0] y; + always @ (negedge clk) begin + y <= {toggle, ~toggle, 1'b1}; end - for (genvar j = 0; j < 3; j++) begin -%000002 logic [2:0] y; - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end - end - end - if (P > 1) begin : gen_1 - assign z = 1; - end + end + end + if (P > 1) begin : gen_1 + assign z = 1; + end endmodule module mod_struct(/*AUTOARG*/ - // Inputs - input_struct - ); + // Inputs + input_struct + ); -~000010 input str_logic input_struct; +~000010 input str_logic input_struct; endmodule diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index e0a21df21..cc66bbdd6 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -7,252 +7,252 @@ typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); + // Inputs + clk, check_real, check_array_real, check_string + ); - input clk; - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 + input clk; + input real check_real; // Check issue #2741 + input real check_array_real [1:0]; + input string check_string; // Check issue #2766 - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; + typedef struct packed { + union packed { + logic ua; + logic ub; + } u; + logic b; + } str_t; - reg toggle; initial toggle='0; + reg toggle; initial toggle='0; - logic _under_toggle = toggle; // For --coverage-underscore + logic _under_toggle = toggle; // For --coverage-underscore - str_t stoggle; initial stoggle='0; + str_t stoggle; initial stoggle='0; - str_logic strl; initial strl='0; + str_logic strl; initial strl='0; - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; + union { + real val1; // TODO use bit [7:0] here + real val2; // TODO use bit [3:0] here + } utoggle; - const reg aconst = '0; + const reg aconst = '0; - reg [1:0][1:0] ptoggle; initial ptoggle=0; + reg [1:0][1:0] ptoggle; initial ptoggle=0; - integer cyc; initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; - wire toggle_up; + integer cyc; initial cyc=1; + wire [7:0] cyc_copy = cyc[7:0]; + wire toggle_up; - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; + typedef struct { + int q[$]; + } str_queue_t; + str_queue_t str_queue; - typedef struct packed { - // verilator lint_off ASCRANGE - bit [3:5] x; - // verilator lint_on ASCRANGE - bit [0:0] y; - } str_bit_t; - str_bit_t str_bit; - str_bit_t [5:2] str_bit_arr; + typedef struct packed { + // verilator lint_off ASCRANGE + bit [3:5] x; + // verilator lint_on ASCRANGE + bit [0:0] y; + } str_bit_t; + str_bit_t str_bit; + str_bit_t [5:2] str_bit_arr; - assign strl.a = clk; + assign strl.a = clk; - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + alpha a1 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + alpha a2 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle_up (toggle_up)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#(1) p1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#() p2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - mod_struct i_mod_struct (/*AUTOINST*/ - // Inputs - .input_struct (strl)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); - reg [1:0] memory[121:110]; + reg [1:0] memory[121:110]; - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) + wire [1023:0] largeish = {992'h0, cyc}; + // CHECK_COVER_MISSING(-1) - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - str_bit.x <= '1; - str_bit.y <= '1; - str_bit_arr[4].x <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - str_bit.x[3] <= 0; - str_bit.y[0] <= 0; - str_bit_arr[4].x[3] <= 0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + utoggle.val1 <= real'(cyc[7:0]); + ptoggle[0][0] <= toggle; + if (cyc == 3) begin + str_queue.q.push_back(1); + toggle <= '1; + str_bit.x <= '1; + str_bit.y <= '1; + str_bit_arr[4].x <= '1; end - end + if (cyc == 4) begin + if (str_queue.q.size() != 1) $stop; + toggle <= '0; + str_bit.x[3] <= 0; + str_bit.y[0] <= 0; + str_bit_arr[4].x[3] <= 0; + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); + // Outputs + toggle_up, + // Inputs + clk, toggle, cyc_copy + ); - // t.a1 and t.a2 collapse to a count of 2 + // t.a1 and t.a2 collapse to a count of 2 - input clk; + input clk; - input toggle; - // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) - // (t.a1 and t.a2) + input toggle; + // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) + // (t.a1 and t.a2) - input [7:0] cyc_copy; - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) - // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) - // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) - // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) - // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) - // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) - // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) - // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) - // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) + input [7:0] cyc_copy; + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) + // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) + // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) + // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) + // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) + // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) + // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) + // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) + // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) - reg toggle_internal; - // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) - // (t.a1 and t.a2) + reg toggle_internal; + // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) + // (t.a1 and t.a2) - output reg toggle_up; - // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) - // (t.a1 and t.a2) + output reg toggle_up; + // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) + // (t.a1 and t.a2) - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end + always @ (posedge clk) begin + toggle_internal <= toggle; + toggle_up <= toggle; + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); + // Inputs + clk, toggle_up + ); - input clk; + input clk; - input toggle_up; - // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) - // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) + input toggle_up; + // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) + // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end + always @ (posedge clk) begin + if (0 && toggle_up) begin end + end endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) + // verilator coverage_off + input clk; + // CHECK_COVER_MISSING(-1) - // verilator coverage_on - input toggle; - // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) - // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) + // verilator coverage_on + input toggle; + // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) + // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - input clk; - input toggle; + input clk; + input toggle; - logic z; + logic z; - for (genvar i = 0; i < P; i++) begin - logic x; - always @ (posedge clk) begin - x <= toggle; + for (genvar i = 0; i < P; i++) begin + logic x; + always @ (posedge clk) begin + x <= toggle; + end + for (genvar j = 0; j < 3; j++) begin + logic [2:0] y; + always @ (negedge clk) begin + y <= {toggle, ~toggle, 1'b1}; end - for (genvar j = 0; j < 3; j++) begin - logic [2:0] y; - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end - end - end - if (P > 1) begin : gen_1 - assign z = 1; - end + end + end + if (P > 1) begin : gen_1 + assign z = 1; + end endmodule module mod_struct(/*AUTOARG*/ - // Inputs - input_struct - ); + // Inputs + input_struct + ); - input str_logic input_struct; + input str_logic input_struct; endmodule diff --git a/test_regress/t/t_cover_toggle__all.out b/test_regress/t/t_cover_toggle__all.out index 61281e1da..0c2431db8 100644 --- a/test_regress/t/t_cover_toggle__all.out +++ b/test_regress/t/t_cover_toggle__all.out @@ -8,253 +8,253 @@ typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); + // Inputs + clk, check_real, check_array_real, check_string + ); - 000010 input clk; - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 + 000010 input clk; + input real check_real; // Check issue #2741 + input real check_array_real [1:0]; + input string check_string; // Check issue #2766 - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; + typedef struct packed { + union packed { + logic ua; + logic ub; + } u; + logic b; + } str_t; - 000001 reg toggle; initial toggle='0; + 000001 reg toggle; initial toggle='0; - logic _under_toggle = toggle; // For --coverage-underscore + logic _under_toggle = toggle; // For --coverage-underscore - 000001 str_t stoggle; initial stoggle='0; + 000001 str_t stoggle; initial stoggle='0; - 000010 str_logic strl; initial strl='0; + 000010 str_logic strl; initial strl='0; - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; + union { + real val1; // TODO use bit [7:0] here + real val2; // TODO use bit [3:0] here + } utoggle; - const reg aconst = '0; + const reg aconst = '0; -~000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; +~000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; - integer cyc; initial cyc=1; -~000006 wire [7:0] cyc_copy = cyc[7:0]; - 000001 wire toggle_up; + integer cyc; initial cyc=1; +~000006 wire [7:0] cyc_copy = cyc[7:0]; + 000001 wire toggle_up; - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; + typedef struct { + int q[$]; + } str_queue_t; + str_queue_t str_queue; - typedef struct packed { - // verilator lint_off ASCRANGE - bit [3:5] x; - // verilator lint_on ASCRANGE - bit [0:0] y; - } str_bit_t; -~000001 str_bit_t str_bit; -~000001 str_bit_t [5:2] str_bit_arr; + typedef struct packed { + // verilator lint_off ASCRANGE + bit [3:5] x; + // verilator lint_on ASCRANGE + bit [0:0] y; + } str_bit_t; +~000001 str_bit_t str_bit; +~000001 str_bit_t [5:2] str_bit_arr; - assign strl.a = clk; + assign strl.a = clk; - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + alpha a1 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + alpha a2 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle_up (toggle_up)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#(1) p1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#() p2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - mod_struct i_mod_struct (/*AUTOINST*/ - // Inputs - .input_struct (strl)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); -~000001 reg [1:0] memory[121:110]; +~000001 reg [1:0] memory[121:110]; - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) + wire [1023:0] largeish = {992'h0, cyc}; + // CHECK_COVER_MISSING(-1) - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - str_bit.x <= '1; - str_bit.y <= '1; - str_bit_arr[4].x <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - str_bit.x[3] <= 0; - str_bit.y[0] <= 0; - str_bit_arr[4].x[3] <= 0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + utoggle.val1 <= real'(cyc[7:0]); + ptoggle[0][0] <= toggle; + if (cyc == 3) begin + str_queue.q.push_back(1); + toggle <= '1; + str_bit.x <= '1; + str_bit.y <= '1; + str_bit_arr[4].x <= '1; end - end + if (cyc == 4) begin + if (str_queue.q.size() != 1) $stop; + toggle <= '0; + str_bit.x[3] <= 0; + str_bit.y[0] <= 0; + str_bit_arr[4].x[3] <= 0; + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); + // Outputs + toggle_up, + // Inputs + clk, toggle, cyc_copy + ); - // t.a1 and t.a2 collapse to a count of 2 + // t.a1 and t.a2 collapse to a count of 2 - 000020 input clk; + 000020 input clk; - 000002 input toggle; - // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) - // (t.a1 and t.a2) + 000002 input toggle; + // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) + // (t.a1 and t.a2) -~000012 input [7:0] cyc_copy; - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) - // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) - // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) - // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) - // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) - // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) - // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) - // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) - // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) +~000012 input [7:0] cyc_copy; + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) + // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) + // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) + // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) + // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) + // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) + // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) + // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) + // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) - 000002 reg toggle_internal; - // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) - // (t.a1 and t.a2) + 000002 reg toggle_internal; + // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) + // (t.a1 and t.a2) - 000002 output reg toggle_up; - // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) - // (t.a1 and t.a2) + 000002 output reg toggle_up; + // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) + // (t.a1 and t.a2) - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end + always @ (posedge clk) begin + toggle_internal <= toggle; + toggle_up <= toggle; + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); + // Inputs + clk, toggle_up + ); - 000010 input clk; + 000010 input clk; - 000001 input toggle_up; - // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) - // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) + 000001 input toggle_up; + // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) + // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end + always @ (posedge clk) begin + if (0 && toggle_up) begin end + end endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) + // verilator coverage_off + input clk; + // CHECK_COVER_MISSING(-1) - // verilator coverage_on - 000001 input toggle; - // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) - // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) + // verilator coverage_on + 000001 input toggle; + // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) + // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - 000010 input clk; - 000001 input toggle; + 000010 input clk; + 000001 input toggle; -~000001 logic z; +~000001 logic z; - for (genvar i = 0; i < P; i++) begin - 000001 logic x; - always @ (posedge clk) begin - x <= toggle; + for (genvar i = 0; i < P; i++) begin + 000001 logic x; + always @ (posedge clk) begin + x <= toggle; + end + for (genvar j = 0; j < 3; j++) begin +~000002 logic [2:0] y; + always @ (negedge clk) begin + y <= {toggle, ~toggle, 1'b1}; end - for (genvar j = 0; j < 3; j++) begin -~000002 logic [2:0] y; - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end - end - end - if (P > 1) begin : gen_1 - assign z = 1; - end + end + end + if (P > 1) begin : gen_1 + assign z = 1; + end endmodule module mod_struct(/*AUTOARG*/ - // Inputs - input_struct - ); + // Inputs + input_struct + ); - 000010 input str_logic input_struct; + 000010 input str_logic input_struct; endmodule diff --git a/test_regress/t/t_cover_toggle__points.out b/test_regress/t/t_cover_toggle__points.out index 25f537907..58b226354 100644 --- a/test_regress/t/t_cover_toggle__points.out +++ b/test_regress/t/t_cover_toggle__points.out @@ -8,49 +8,49 @@ typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ - // Inputs - clk, check_real, check_array_real, check_string - ); + // Inputs + clk, check_real, check_array_real, check_string + ); -~000010 input clk; +~000010 input clk; +000010 point: type=toggle comment=clk:0->1 hier=top.t -000009 point: type=toggle comment=clk:1->0 hier=top.t - input real check_real; // Check issue #2741 - input real check_array_real [1:0]; - input string check_string; // Check issue #2766 + input real check_real; // Check issue #2741 + input real check_array_real [1:0]; + input string check_string; // Check issue #2766 - typedef struct packed { - union packed { - logic ua; - logic ub; - } u; - logic b; - } str_t; + typedef struct packed { + union packed { + logic ua; + logic ub; + } u; + logic b; + } str_t; -%000001 reg toggle; initial toggle='0; +%000001 reg toggle; initial toggle='0; -000001 point: type=toggle comment=toggle:0->1 hier=top.t -000001 point: type=toggle comment=toggle:1->0 hier=top.t - logic _under_toggle = toggle; // For --coverage-underscore + logic _under_toggle = toggle; // For --coverage-underscore -%000001 str_t stoggle; initial stoggle='0; +%000001 str_t stoggle; initial stoggle='0; -000001 point: type=toggle comment=stoggle.b:0->1 hier=top.t -000001 point: type=toggle comment=stoggle.b:1->0 hier=top.t -000001 point: type=toggle comment=stoggle.u.ua:0->1 hier=top.t -000001 point: type=toggle comment=stoggle.u.ua:1->0 hier=top.t -~000010 str_logic strl; initial strl='0; +~000010 str_logic strl; initial strl='0; +000010 point: type=toggle comment=strl.a:0->1 hier=top.t -000009 point: type=toggle comment=strl.a:1->0 hier=top.t - union { - real val1; // TODO use bit [7:0] here - real val2; // TODO use bit [3:0] here - } utoggle; + union { + real val1; // TODO use bit [7:0] here + real val2; // TODO use bit [3:0] here + } utoggle; - const reg aconst = '0; + const reg aconst = '0; -%000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; +%000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; -000001 point: type=toggle comment=ptoggle[0][0]:0->1 hier=top.t -000001 point: type=toggle comment=ptoggle[0][0]:1->0 hier=top.t -000000 point: type=toggle comment=ptoggle[0][1]:0->1 hier=top.t @@ -60,8 +60,8 @@ -000000 point: type=toggle comment=ptoggle[1][1]:0->1 hier=top.t -000000 point: type=toggle comment=ptoggle[1][1]:1->0 hier=top.t - integer cyc; initial cyc=1; -%000006 wire [7:0] cyc_copy = cyc[7:0]; + integer cyc; initial cyc=1; +%000006 wire [7:0] cyc_copy = cyc[7:0]; -000006 point: type=toggle comment=cyc_copy[0]:0->1 hier=top.t -000005 point: type=toggle comment=cyc_copy[0]:1->0 hier=top.t -000003 point: type=toggle comment=cyc_copy[1]:0->1 hier=top.t @@ -78,22 +78,22 @@ -000000 point: type=toggle comment=cyc_copy[6]:1->0 hier=top.t -000000 point: type=toggle comment=cyc_copy[7]:0->1 hier=top.t -000000 point: type=toggle comment=cyc_copy[7]:1->0 hier=top.t -%000001 wire toggle_up; +%000001 wire toggle_up; -000001 point: type=toggle comment=toggle_up:0->1 hier=top.t -000001 point: type=toggle comment=toggle_up:1->0 hier=top.t - typedef struct { - int q[$]; - } str_queue_t; - str_queue_t str_queue; + typedef struct { + int q[$]; + } str_queue_t; + str_queue_t str_queue; - typedef struct packed { - // verilator lint_off ASCRANGE - bit [3:5] x; - // verilator lint_on ASCRANGE - bit [0:0] y; - } str_bit_t; -%000001 str_bit_t str_bit; + typedef struct packed { + // verilator lint_off ASCRANGE + bit [3:5] x; + // verilator lint_on ASCRANGE + bit [0:0] y; + } str_bit_t; +%000001 str_bit_t str_bit; -000001 point: type=toggle comment=str_bit.x[3]:0->1 hier=top.t -000001 point: type=toggle comment=str_bit.x[3]:1->0 hier=top.t -000001 point: type=toggle comment=str_bit.x[4]:0->1 hier=top.t @@ -102,7 +102,7 @@ -000000 point: type=toggle comment=str_bit.x[5]:1->0 hier=top.t -000001 point: type=toggle comment=str_bit.y[0]:0->1 hier=top.t -000001 point: type=toggle comment=str_bit.y[0]:1->0 hier=top.t -%000001 str_bit_t [5:2] str_bit_arr; +%000001 str_bit_t [5:2] str_bit_arr; -000000 point: type=toggle comment=str_bit_arr[2].x[3]:0->1 hier=top.t -000000 point: type=toggle comment=str_bit_arr[2].x[3]:1->0 hier=top.t -000000 point: type=toggle comment=str_bit_arr[2].x[4]:0->1 hier=top.t @@ -136,49 +136,49 @@ -000000 point: type=toggle comment=str_bit_arr[5].y[0]:0->1 hier=top.t -000000 point: type=toggle comment=str_bit_arr[5].y[0]:1->0 hier=top.t - assign strl.a = clk; + assign strl.a = clk; - alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); - alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + alpha a1 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + alpha a2 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); - beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle_up (toggle_up)); - off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#(1) p1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#(1) p1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - param#() p2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + param#() p2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); - mod_struct i_mod_struct (/*AUTOINST*/ - // Inputs - .input_struct (strl)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); -%000001 reg [1:0] memory[121:110]; +%000001 reg [1:0] memory[121:110]; -000001 point: type=toggle comment=memory[110][0]:0->1 hier=top.t -000000 point: type=toggle comment=memory[110][0]:1->0 hier=top.t -000000 point: type=toggle comment=memory[110][1]:0->1 hier=top.t @@ -228,62 +228,62 @@ -000000 point: type=toggle comment=memory[121][1]:0->1 hier=top.t -000000 point: type=toggle comment=memory[121][1]:1->0 hier=top.t - wire [1023:0] largeish = {992'h0, cyc}; - // CHECK_COVER_MISSING(-1) + wire [1023:0] largeish = {992'h0, cyc}; + // CHECK_COVER_MISSING(-1) - always @ (posedge clk) begin - if (cyc != 0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - utoggle.val1 <= real'(cyc[7:0]); - ptoggle[0][0] <= toggle; - if (cyc == 3) begin - str_queue.q.push_back(1); - toggle <= '1; - str_bit.x <= '1; - str_bit.y <= '1; - str_bit_arr[4].x <= '1; - end - if (cyc == 4) begin - if (str_queue.q.size() != 1) $stop; - toggle <= '0; - str_bit.x[3] <= 0; - str_bit.y[0] <= 0; - str_bit_arr[4].x[3] <= 0; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + utoggle.val1 <= real'(cyc[7:0]); + ptoggle[0][0] <= toggle; + if (cyc == 3) begin + str_queue.q.push_back(1); + toggle <= '1; + str_bit.x <= '1; + str_bit.y <= '1; + str_bit_arr[4].x <= '1; end - end + if (cyc == 4) begin + if (str_queue.q.size() != 1) $stop; + toggle <= '0; + str_bit.x[3] <= 0; + str_bit.y[0] <= 0; + str_bit_arr[4].x[3] <= 0; + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module alpha (/*AUTOARG*/ - // Outputs - toggle_up, - // Inputs - clk, toggle, cyc_copy - ); + // Outputs + toggle_up, + // Inputs + clk, toggle, cyc_copy + ); - // t.a1 and t.a2 collapse to a count of 2 + // t.a1 and t.a2 collapse to a count of 2 - 000020 input clk; + 000020 input clk; +000020 point: type=toggle comment=clk:0->1 hier=top.t.a* +000018 point: type=toggle comment=clk:1->0 hier=top.t.a* -%000002 input toggle; +%000002 input toggle; -000002 point: type=toggle comment=toggle:0->1 hier=top.t.a* -000002 point: type=toggle comment=toggle:1->0 hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) - // (t.a1 and t.a2) + // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) + // (t.a1 and t.a2) -~000012 input [7:0] cyc_copy; +~000012 input [7:0] cyc_copy; +000012 point: type=toggle comment=cyc_copy[0]:0->1 hier=top.t.a* +000010 point: type=toggle comment=cyc_copy[0]:1->0 hier=top.t.a* -000006 point: type=toggle comment=cyc_copy[1]:0->1 hier=top.t.a* @@ -300,118 +300,118 @@ -000000 point: type=toggle comment=cyc_copy[6]:1->0 hier=top.t.a* -000000 point: type=toggle comment=cyc_copy[7]:0->1 hier=top.t.a* -000000 point: type=toggle comment=cyc_copy[7]:1->0 hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) - // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) - // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) - // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) - // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) - // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) - // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) - // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) - // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) - // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) - // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) - // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) - // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) - // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) - // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) - // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) + // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) + // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) + // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) + // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) + // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) + // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) + // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) + // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) -%000002 reg toggle_internal; +%000002 reg toggle_internal; -000002 point: type=toggle comment=toggle_internal:0->1 hier=top.t.a* -000002 point: type=toggle comment=toggle_internal:1->0 hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) - // (t.a1 and t.a2) + // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) + // (t.a1 and t.a2) -%000002 output reg toggle_up; +%000002 output reg toggle_up; -000002 point: type=toggle comment=toggle_up:0->1 hier=top.t.a* -000002 point: type=toggle comment=toggle_up:1->0 hier=top.t.a* - // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) - // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) - // (t.a1 and t.a2) + // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) + // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) + // (t.a1 and t.a2) - always @ (posedge clk) begin - toggle_internal <= toggle; - toggle_up <= toggle; - end + always @ (posedge clk) begin + toggle_internal <= toggle; + toggle_up <= toggle; + end endmodule module beta (/*AUTOARG*/ - // Inputs - clk, toggle_up - ); + // Inputs + clk, toggle_up + ); -~000010 input clk; +~000010 input clk; +000010 point: type=toggle comment=clk:0->1 hier=top.t.b1 -000009 point: type=toggle comment=clk:1->0 hier=top.t.b1 -%000001 input toggle_up; +%000001 input toggle_up; -000001 point: type=toggle comment=toggle_up:0->1 hier=top.t.b1 -000001 point: type=toggle comment=toggle_up:1->0 hier=top.t.b1 - // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) - // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) + // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) + // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) - /* verilator public_module */ + /* verilator public_module */ - always @ (posedge clk) begin - if (0 && toggle_up) begin end - end + always @ (posedge clk) begin + if (0 && toggle_up) begin end + end endmodule module off (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); - // verilator coverage_off - input clk; - // CHECK_COVER_MISSING(-1) + // verilator coverage_off + input clk; + // CHECK_COVER_MISSING(-1) - // verilator coverage_on -%000001 input toggle; + // verilator coverage_on +%000001 input toggle; -000001 point: type=toggle comment=toggle:0->1 hier=top.t.o1 -000001 point: type=toggle comment=toggle:1->0 hier=top.t.o1 - // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) - // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) + // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) + // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ - // Inputs - clk, toggle - ); + // Inputs + clk, toggle + ); -~000010 input clk; +~000010 input clk; +000010 point: type=toggle comment=clk:0->1 hier=top.t.p2 -000009 point: type=toggle comment=clk:1->0 hier=top.t.p2 +000010 point: type=toggle comment=clk:0->1 hier=top.t.p1 -000009 point: type=toggle comment=clk:1->0 hier=top.t.p1 -%000001 input toggle; +%000001 input toggle; -000001 point: type=toggle comment=toggle:0->1 hier=top.t.p2 -000001 point: type=toggle comment=toggle:1->0 hier=top.t.p2 -000001 point: type=toggle comment=toggle:0->1 hier=top.t.p1 -000001 point: type=toggle comment=toggle:1->0 hier=top.t.p1 -%000001 logic z; +%000001 logic z; -000001 point: type=toggle comment=z:0->1 hier=top.t.p2 -000000 point: type=toggle comment=z:1->0 hier=top.t.p2 -000000 point: type=toggle comment=z:0->1 hier=top.t.p1 -000000 point: type=toggle comment=z:1->0 hier=top.t.p1 - for (genvar i = 0; i < P; i++) begin -%000001 logic x; + for (genvar i = 0; i < P; i++) begin +%000001 logic x; -000001 point: type=toggle comment=genblk1[0].x:0->1 hier=top.t.p2 -000001 point: type=toggle comment=genblk1[0].x:1->0 hier=top.t.p2 -000001 point: type=toggle comment=genblk1[1].x:0->1 hier=top.t.p2 -000001 point: type=toggle comment=genblk1[1].x:1->0 hier=top.t.p2 -000001 point: type=toggle comment=genblk1[0].x:0->1 hier=top.t.p1 -000001 point: type=toggle comment=genblk1[0].x:1->0 hier=top.t.p1 - always @ (posedge clk) begin - x <= toggle; - end - for (genvar j = 0; j < 3; j++) begin -%000002 logic [2:0] y; + always @ (posedge clk) begin + x <= toggle; + end + for (genvar j = 0; j < 3; j++) begin +%000002 logic [2:0] y; -000001 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p2 -000000 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p2 -000002 point: type=toggle comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p2 @@ -466,22 +466,22 @@ -000001 point: type=toggle comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p1 -000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p1 -000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p1 - always @ (negedge clk) begin - y <= {toggle, ~toggle, 1'b1}; - end + always @ (negedge clk) begin + y <= {toggle, ~toggle, 1'b1}; end - end - if (P > 1) begin : gen_1 - assign z = 1; - end + end + end + if (P > 1) begin : gen_1 + assign z = 1; + end endmodule module mod_struct(/*AUTOARG*/ - // Inputs - input_struct - ); + // Inputs + input_struct + ); -~000010 input str_logic input_struct; +~000010 input str_logic input_struct; +000010 point: type=toggle comment=input_struct.a:0->1 hier=top.t.i_mod_struct -000009 point: type=toggle comment=input_struct.a:1->0 hier=top.t.i_mod_struct endmodule diff --git a/test_regress/t/t_cover_toggle_min.v b/test_regress/t/t_cover_toggle_min.v index c41c82dc4..53c81769d 100644 --- a/test_regress/t/t_cover_toggle_min.v +++ b/test_regress/t/t_cover_toggle_min.v @@ -7,16 +7,16 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - logic[1:0] a; - logic[1:0] b; - logic[1:0] c; + logic [1:0] a; + logic [1:0] b; + logic [1:0] c; - initial begin - #1 a = 2'b01; - #1 b = 2'b10; - #1 c = 2'b11; - #1 c = 2'b10; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #1 a = 2'b01; + #1 b = 2'b10; + #1 c = 2'b11; + #1 c = 2'b10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_trace_always.out b/test_regress/t/t_cover_trace_always.out index 417236b8b..2b4581d1e 100644 --- a/test_regress/t/t_cover_trace_always.out +++ b/test_regress/t/t_cover_trace_always.out @@ -1,32 +1,32 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end - $var wire 1 $ p $end - $var wire 1 % q $end - $var wire 1 & r $end - $var wire 32 ' vlCoverageLineTrace_t_cover_trace_always__24_block [31:0] $end + $var wire 1 # p $end + $var wire 1 $ q $end + $var wire 1 % r $end + $var wire 32 & vlCoverageLineTrace_t_cover_trace_always__32_block [31:0] $end $scope module dut $end - $var wire 1 $ p $end - $var wire 1 % q $end - $var wire 1 & r $end - $var wire 32 # vlCoverageLineTrace_t_cover_trace_always__12_block [31:0] $end - $var wire 32 ( vlCoverageLineTrace_t_cover_trace_always__13_expr_0 [31:0] $end - $var wire 32 ) vlCoverageLineTrace_t_cover_trace_always__13_expr_1 [31:0] $end - $var wire 32 * vlCoverageLineTrace_t_cover_trace_always__13_expr_2 [31:0] $end + $var wire 1 # p $end + $var wire 1 $ q $end + $var wire 1 % r $end + $var wire 32 " vlCoverageLineTrace_t_cover_trace_always__16_block [31:0] $end + $var wire 32 ' vlCoverageLineTrace_t_cover_trace_always__17_expr_0 [31:0] $end + $var wire 32 ( vlCoverageLineTrace_t_cover_trace_always__17_expr_1 [31:0] $end + $var wire 32 ) vlCoverageLineTrace_t_cover_trace_always__17_expr_2 [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 -b00000000000000000000000000000001 # -1$ -0% -1& +b00000000000000000000000000000001 " +1# +0$ +1% +b00000000000000000000000000000000 & b00000000000000000000000000000000 ' -b00000000000000000000000000000000 ( -b00000000000000000000000000000001 ) -b00000000000000000000000000000000 * +b00000000000000000000000000000001 ( +b00000000000000000000000000000000 ) #1 -b00000000000000000000000000000001 ' -b00000000000000000000000000000011 ) +b00000000000000000000000000000001 & +b00000000000000000000000000000011 ( diff --git a/test_regress/t/t_cover_trace_always.v b/test_regress/t/t_cover_trace_always.v index 74d4eaf13..783bcc698 100644 --- a/test_regress/t/t_cover_trace_always.v +++ b/test_regress/t/t_cover_trace_always.v @@ -8,28 +8,36 @@ `define STRINGIFY(x) `"x`" -module imply(input logic p, input logic q, output logic r); - always_comb begin - r = p | q; - end +module imply ( + input logic p, + input logic q, + output logic r +); + always_comb begin + r = p | q; + end endmodule module t; - logic p; - logic q; - logic r; + logic p; + logic q; + logic r; - imply dut(.p(p), .q(q), .r(r)); + imply dut ( + .p(p), + .q(q), + .r(r) + ); - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(); - // - p = 1; - q = 0; - $strobe("[%0t] %d, %d, %d", $time, p, q, r); - #1; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(); + // + p = 1; + q = 0; + $strobe("[%0t] %d, %d, %d", $time, p, q, r); + #1; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cover_unused_bad.out b/test_regress/t/t_cover_unused_bad.out index 32656657e..dc791dcc4 100644 --- a/test_regress/t/t_cover_unused_bad.out +++ b/test_regress/t/t_cover_unused_bad.out @@ -1,7 +1,7 @@ -%Warning-UNUSEDSIGNAL: t/t_cover_unused_bad.v:14:10: Signal is not used: 'unu3' - : ... note: In instance 't' - 14 | logic unu3 = 0; - | ^~~~ +%Warning-UNUSEDSIGNAL: t/t_cover_unused_bad.v:11:9: Signal is not used: 'unu3' + : ... note: In instance 't' + 11 | logic unu3 = 0; + | ^~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_cover_unused_bad.v b/test_regress/t/t_cover_unused_bad.v index f85b4a5f0..c49a2f5c0 100644 --- a/test_regress/t/t_cover_unused_bad.v +++ b/test_regress/t/t_cover_unused_bad.v @@ -4,16 +4,13 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic unu3 = 0; - logic unu3 = 0; - - logic isusd = 0; - cover property (@(posedge clk) isusd == 0); + logic isusd = 0; + cover property (@(posedge clk) isusd == 0); endmodule diff --git a/test_regress/t/t_covergroup_coverpoints_unsup.out b/test_regress/t/t_covergroup_coverpoints_unsup.out index 5e65dcbeb..417ecd3f2 100644 --- a/test_regress/t/t_covergroup_coverpoints_unsup.out +++ b/test_regress/t/t_covergroup_coverpoints_unsup.out @@ -1,52 +1,52 @@ -%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:19: Ignoring unsupported: coverage clocking event - 21 | covergroup cg @(posedge clk); - | ^ +%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:19:17: Ignoring unsupported: coverage clocking event + 19 | covergroup cg @(posedge clk); + | ^ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:22:9: Ignoring unsupported: coverpoint - 22 | coverpoint a; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:24:31: Ignoring unsupported: cover bin specification - 24 | bins the_bins [5] = { [0:20] }; - | ^ -%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:23:9: Ignoring unsupported: coverpoint - 23 | coverpoint b { - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:5: Ignoring unsupported: covergroup - 21 | covergroup cg @(posedge clk); +%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:20:5: Ignoring unsupported: coverpoint + 20 | coverpoint a; | ^~~~~~~~~~ -%Error: t/t_covergroup_coverpoints_unsup.v:35:48: Member 'a' not found in covergroup 'cg' +%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:36: Ignoring unsupported: cover bin specification + 21 | coverpoint b {bins the_bins[5] = {[0 : 20]};} + | ^ +%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:5: Ignoring unsupported: coverpoint + 21 | coverpoint b {bins the_bins[5] = {[0 : 20]};} + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:19:3: Ignoring unsupported: covergroup + 19 | covergroup cg @(posedge clk); + | ^~~~~~~~~~ +%Error: t/t_covergroup_coverpoints_unsup.v:31:42: Member 'a' not found in covergroup 'cg' : ... note: In instance 't' - 35 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); - | ^ + 31 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:35:50: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' +%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:31:44: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' - 35 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); - | ^~~~~~~~~~~~~~~~~ + 31 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); + | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_covergroup_coverpoints_unsup.v:36:48: Member 'b' not found in covergroup 'cg' +%Error: t/t_covergroup_coverpoints_unsup.v:32:42: Member 'b' not found in covergroup 'cg' : ... note: In instance 't' - 36 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); - | ^ -%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:36:50: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' + 32 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); + | ^ +%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:32:44: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' - 36 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_covergroup_coverpoints_unsup.v:37:24: Member 'a' not found in covergroup 'cg' + 32 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_covergroup_coverpoints_unsup.v:33:18: Member 'a' not found in covergroup 'cg' : ... note: In instance 't' - 37 | if (the_cg.a.get_inst_coverage() != 15/16.0) $stop(); - | ^ -%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:37:26: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' + 33 | if (the_cg.a.get_inst_coverage() != 15 / 16.0) $stop(); + | ^ +%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:33:20: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' - 37 | if (the_cg.a.get_inst_coverage() != 15/16.0) $stop(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_covergroup_coverpoints_unsup.v:38:24: Member 'b' not found in covergroup 'cg' + 33 | if (the_cg.a.get_inst_coverage() != 15 / 16.0) $stop(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_covergroup_coverpoints_unsup.v:34:18: Member 'b' not found in covergroup 'cg' : ... note: In instance 't' - 38 | if (the_cg.b.get_inst_coverage() != 4/5.0) $stop(); - | ^ -%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:38:26: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' + 34 | if (the_cg.b.get_inst_coverage() != 4 / 5.0) $stop(); + | ^ +%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:34:20: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' - 38 | if (the_cg.b.get_inst_coverage() != 4/5.0) $stop(); - | ^~~~~~~~~~~~~~~~~ + 34 | if (the_cg.b.get_inst_coverage() != 4 / 5.0) $stop(); + | ^~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_coverpoints_unsup.v b/test_regress/t/t_covergroup_coverpoints_unsup.v index 8a06ca3d6..4752457ec 100644 --- a/test_regress/t/t_covergroup_coverpoints_unsup.v +++ b/test_regress/t/t_covergroup_coverpoints_unsup.v @@ -4,40 +4,36 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - logic [3:0] a; - int b; - int cyc = 0; + logic [3:0] a; + int b; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - end - - covergroup cg @(posedge clk); - coverpoint a; - coverpoint b { - bins the_bins [5] = { [0:20] }; - } - endgroup - - cg the_cg = new; - - assign a = cyc[3:0]; - assign b = cyc; - - always @(posedge clk) begin - if (cyc == 14) begin - $display("coverage a = %f", the_cg.a.get_inst_coverage()); - $display("coverage b = %f", the_cg.b.get_inst_coverage()); - if (the_cg.a.get_inst_coverage() != 15/16.0) $stop(); - if (the_cg.b.get_inst_coverage() != 4/5.0) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end + + covergroup cg @(posedge clk); + coverpoint a; + coverpoint b {bins the_bins[5] = {[0 : 20]};} + endgroup + + cg the_cg = new; + + assign a = cyc[3:0]; + assign b = cyc; + + always @(posedge clk) begin + if (cyc == 14) begin + $display("coverage a = %f", the_cg.a.get_inst_coverage()); + $display("coverage b = %f", the_cg.b.get_inst_coverage()); + if (the_cg.a.get_inst_coverage() != 15 / 16.0) $stop(); + if (the_cg.b.get_inst_coverage() != 4 / 5.0) $stop(); + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule diff --git a/test_regress/t/t_covergroup_extends.v b/test_regress/t/t_covergroup_extends.v index ddf547d28..880857d4b 100644 --- a/test_regress/t/t_covergroup_extends.v +++ b/test_regress/t/t_covergroup_extends.v @@ -6,34 +6,34 @@ /* verilator lint_off COVERIGN */ module t; - class base; - enum {red, green, blue} color; - covergroup g1 (bit [3:0] a) with function sample(bit b); - option.weight = 10; - option.per_instance = 1; - coverpoint a; - coverpoint b; - c: coverpoint color; - endgroup - function new(); - g1 = new(0); - endfunction - endclass + class base; + enum {red, green, blue} color; + covergroup g1 (bit [3:0] a) with function sample(bit b); + option.weight = 10; + option.per_instance = 1; + coverpoint a; + coverpoint b; + c: coverpoint color; + endgroup + function new(); + g1 = new(0); + endfunction + endclass - class derived extends base; - bit d; - covergroup extends g1; - option.weight = 1; // overrides the weight from base g1 - // uses per_instance = 1 from base g1 - c: coverpoint color // overrides the c coverpoint in base g1 - { - ignore_bins ignore = {blue}; - } - coverpoint d; // adds new coverpoint - cross a, d; // crosses new coverpoint with inherited one - endgroup :g1 - function new(); - super.new(); - endfunction - endclass + class derived extends base; + bit d; + covergroup extends g1; + option.weight = 1; // overrides the weight from base g1 + // uses per_instance = 1 from base g1 + c: coverpoint color // overrides the c coverpoint in base g1 + { + ignore_bins ignore = {blue}; + } + coverpoint d; // adds new coverpoint + cross a, d; // crosses new coverpoint with inherited one + endgroup :g1 + function new(); + super.new(); + endfunction + endclass endmodule diff --git a/test_regress/t/t_covergroup_extends_newfirst.v b/test_regress/t/t_covergroup_extends_newfirst.v index 39a385529..aee7a2f7b 100644 --- a/test_regress/t/t_covergroup_extends_newfirst.v +++ b/test_regress/t/t_covergroup_extends_newfirst.v @@ -6,34 +6,34 @@ /* verilator lint_off COVERIGN */ module t; - class base; - function new(); - g1 = new(0); - endfunction - enum {red, green, blue} color; - covergroup g1 (bit [3:0] a) with function sample(bit b); - option.weight = 10; - option.per_instance = 1; - coverpoint a; - coverpoint b; - c: coverpoint color; - endgroup - endclass + class base; + function new(); + g1 = new(0); + endfunction + enum {red, green, blue} color; + covergroup g1 (bit [3:0] a) with function sample(bit b); + option.weight = 10; + option.per_instance = 1; + coverpoint a; + coverpoint b; + c: coverpoint color; + endgroup + endclass - class derived extends base; - bit d; - function new(); - super.new(); - endfunction - covergroup extends g1; - option.weight = 1; // overrides the weight from base g1 - // uses per_instance = 1 from base g1 - c: coverpoint color // overrides the c coverpoint in base g1 - { - ignore_bins ignore = {blue}; - } - coverpoint d; // adds new coverpoint - cross a, d; // crosses new coverpoint with inherited one - endgroup :g1 - endclass + class derived extends base; + bit d; + function new(); + super.new(); + endfunction + covergroup extends g1; + option.weight = 1; // overrides the weight from base g1 + // uses per_instance = 1 from base g1 + c: coverpoint color // overrides the c coverpoint in base g1 + { + ignore_bins ignore = {blue}; + } + coverpoint d; // adds new coverpoint + cross a, d; // crosses new coverpoint with inherited one + endgroup :g1 + endclass endmodule diff --git a/test_regress/t/t_covergroup_func_override_bad.out b/test_regress/t/t_covergroup_func_override_bad.out index a8073404e..c32fa1226 100644 --- a/test_regress/t/t_covergroup_func_override_bad.out +++ b/test_regress/t/t_covergroup_func_override_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_covergroup_func_override_bad.v:10:5: syntax error, unexpected function - 10 | function sample(); - | ^~~~~~~~ +%Error: t/t_covergroup_func_override_bad.v:10:3: syntax error, unexpected function + 10 | function sample(); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_func_override_bad.v b/test_regress/t/t_covergroup_func_override_bad.v index 2f758be96..0cb3e7fb3 100644 --- a/test_regress/t/t_covergroup_func_override_bad.v +++ b/test_regress/t/t_covergroup_func_override_bad.v @@ -6,12 +6,12 @@ /* verilator lint_off COVERIGN */ module t; - covergroup cg; - function sample(); + covergroup cg; + function sample(); - endfunction - function get_coverage(); + endfunction + function get_coverage(); - endfunction - endgroup + endfunction + endgroup endmodule diff --git a/test_regress/t/t_covergroup_new_override_bad.out b/test_regress/t/t_covergroup_new_override_bad.out index 4a8175f0f..ee49b92fd 100644 --- a/test_regress/t/t_covergroup_new_override_bad.out +++ b/test_regress/t/t_covergroup_new_override_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_covergroup_new_override_bad.v:10:5: syntax error, unexpected function - 10 | function new(); - | ^~~~~~~~ +%Error: t/t_covergroup_new_override_bad.v:10:3: syntax error, unexpected function + 10 | function new(); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_new_override_bad.v b/test_regress/t/t_covergroup_new_override_bad.v index a38753936..0fb501871 100644 --- a/test_regress/t/t_covergroup_new_override_bad.v +++ b/test_regress/t/t_covergroup_new_override_bad.v @@ -6,9 +6,9 @@ /* verilator lint_off COVERIGN */ module t; - covergroup cg; - function new(); + covergroup cg; + function new(); - endfunction - endgroup + endfunction + endgroup endmodule diff --git a/test_regress/t/t_covergroup_unsup.out b/test_regress/t/t_covergroup_unsup.out index 963e36b49..11fd37c51 100644 --- a/test_regress/t/t_covergroup_unsup.out +++ b/test_regress/t/t_covergroup_unsup.out @@ -1,408 +1,408 @@ -%Warning-COVERIGN: t/t_covergroup_unsup.v:39:4: Ignoring unsupported: covergroup - 39 | covergroup cg_empty; - | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:38:3: Ignoring unsupported: covergroup + 38 | covergroup cg_empty; + | ^~~~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_covergroup_unsup.v:42:4: Ignoring unsupported: covergroup - 42 | covergroup cg_opt; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:61:34: Ignoring unsupported: coverage clocking event - 61 | covergroup cg_clockingevent() @(posedge clk); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:61:4: Ignoring unsupported: covergroup - 61 | covergroup cg_clockingevent() @(posedge clk); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:63:4: Ignoring unsupported: covergroup - 63 | covergroup cg_withfunction() with function sample (a); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:65:25: Ignoring unsupported: coverage '@@' events - 65 | covergroup cg_atat() @@ (begin funca or end funcb); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:65:4: Ignoring unsupported: covergroup - 65 | covergroup cg_atat() @@ (begin funca or end funcb); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:67:4: Ignoring unsupported: covergroup - 67 | covergroup cg_bracket; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:70:4: Ignoring unsupported: covergroup - 70 | covergroup cg_bracket2; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:74:7: Ignoring unsupported: coverpoint - 74 | coverpoint a; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:73:4: Ignoring unsupported: covergroup - 73 | covergroup cg_cp; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:77:20: Ignoring unsupported: cover 'iff' - 77 | coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:77:7: Ignoring unsupported: coverpoint - 77 | coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:76:4: Ignoring unsupported: covergroup - 76 | covergroup cg_cp_iff; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:80:24: Ignoring unsupported: cover 'iff' - 80 | id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:80:11: Ignoring unsupported: coverpoint - 80 | id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:79:4: Ignoring unsupported: covergroup - 79 | covergroup cg_id_cp_iff; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:83:28: Ignoring unsupported: cover 'iff' - 83 | int id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:83:15: Ignoring unsupported: coverpoint - 83 | int id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:82:4: Ignoring unsupported: covergroup - 82 | covergroup cg_id_cp_id1; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:86:32: Ignoring unsupported: cover 'iff' - 86 | var int id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:86:19: Ignoring unsupported: coverpoint - 86 | var int id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:85:4: Ignoring unsupported: covergroup - 85 | covergroup cg_id_cp_id2; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:89:34: Ignoring unsupported: cover 'iff' - 89 | var [3:0] id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:89:21: Ignoring unsupported: coverpoint - 89 | var [3:0] id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:88:4: Ignoring unsupported: covergroup - 88 | covergroup cg_id_cp_id3; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:92:30: Ignoring unsupported: cover 'iff' - 92 | [3:0] id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:92:17: Ignoring unsupported: coverpoint - 92 | [3:0] id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:91:4: Ignoring unsupported: covergroup - 91 | covergroup cg_id_cp_id4; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:95:31: Ignoring unsupported: cover 'iff' - 95 | signed id: coverpoint a iff (b); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:95:18: Ignoring unsupported: coverpoint - 95 | signed id: coverpoint a iff (b); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:94:4: Ignoring unsupported: covergroup - 94 | covergroup cg_id_cp_id5; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:99:18: Ignoring unsupported: cover 'iff' - 99 | cross a, b iff (!rst); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:99:7: Ignoring unsupported: cover cross - 99 | cross a, b iff (!rst); - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:98:4: Ignoring unsupported: covergroup - 98 | covergroup cg_cross; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:102:18: Ignoring unsupported: cover 'iff' - 102 | cross a, b iff (!rst) {} - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:102:7: Ignoring unsupported: cover cross - 102 | cross a, b iff (!rst) {} - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:101:4: Ignoring unsupported: covergroup - 101 | covergroup cg_cross2; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:105:7: Ignoring unsupported: cover cross - 105 | cross a, b { option.comment = "cross"; option.weight = 12; } - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:104:4: Ignoring unsupported: covergroup - 104 | covergroup cg_cross3; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:109:24: Ignoring unsupported: coverage cross 'function' declaration - 109 | function void crossfunc; endfunction - | ^~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:110:21: Ignoring unsupported: coverage select function call - 110 | bins one = crossfunc(); - | ^~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:110:10: Ignoring unsupported: coverage cross bin - 110 | bins one = crossfunc(); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:108:7: Ignoring unsupported: cover cross - 108 | cross a, b { - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:107:4: Ignoring unsupported: covergroup - 107 | covergroup cg_cross4; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:114:28: Ignoring unsupported: cover 'iff' - 114 | my_cg_id: cross a, b iff (!rst); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:114:17: Ignoring unsupported: cover cross - 114 | my_cg_id: cross a, b iff (!rst); - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:113:4: Ignoring unsupported: covergroup - 113 | covergroup cg_cross_id; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:119:17: Ignoring unsupported: cover bin specification - 119 | { bins ba = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:120:24: Ignoring unsupported: cover 'iff' - 120 | { bins bar = {a} iff (!rst); } - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:120:18: Ignoring unsupported: cover bin specification - 120 | { bins bar = {a} iff (!rst); } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:121:26: Ignoring unsupported: cover bin specification - 121 | { illegal_bins ila = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:122:25: Ignoring unsupported: cover bin specification - 122 | { ignore_bins iga = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:124:19: Ignoring unsupported: cover bin specification - 124 | { bins ba[] = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:125:20: Ignoring unsupported: cover bin specification - 125 | { bins ba[2] = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:127:23: Ignoring unsupported: cover bin 'with' specification - 127 | { bins ba = {a} with ( b ); } - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:129:27: Ignoring unsupported: cover bin 'wildcard' specification - 129 | { wildcard bins bwa = {a}; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:130:34: Ignoring unsupported: cover bin 'wildcard' 'with' specification - 130 | { wildcard bins bwaw = {a} with ( b ); } - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:132:20: Ignoring unsupported: cover bin 'default' - 132 | { bins def = default; } - | ^~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:133:29: Ignoring unsupported: cover bin 'default' 'sequence' - 133 | { bins defs = default sequence; } - | ^~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:135:18: Ignoring unsupported: cover bin trans list - 135 | { bins bts = ( 1, 2 ); } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:136:9: Ignoring unsupported: cover bin 'wildcard' trans list - 136 | { wildcard bins wbts = ( 1, 2 ); } - | ^~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:137:33: Ignoring unsupported: covergroup value range - 137 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } +%Warning-COVERIGN: t/t_covergroup_unsup.v:41:3: Ignoring unsupported: covergroup + 41 | covergroup cg_opt; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:60:33: Ignoring unsupported: coverage clocking event + 60 | covergroup cg_clockingevent() @(posedge clk); | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:137:44: Ignoring unsupported: covergroup value range - 137 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:137:59: Ignoring unsupported: covergroup value range - 137 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:137:19: Ignoring unsupported: cover bin trans list - 137 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:139:27: Ignoring unsupported: cover trans set '=>' - 139 | { bins bts2 = ( 1,5 => 6,7 ) ; } - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:139:19: Ignoring unsupported: cover bin trans list - 139 | { bins bts2 = ( 1,5 => 6,7 ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:140:25: Ignoring unsupported: cover '[*' - 140 | { bins bts2 = ( 3 [*5] ) ; } - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:140:19: Ignoring unsupported: cover bin trans list - 140 | { bins bts2 = ( 3 [*5] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:141:25: Ignoring unsupported: cover '[*' - 141 | { bins bts2 = ( 3 [*5:6] ) ; } - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:141:19: Ignoring unsupported: cover bin trans list - 141 | { bins bts2 = ( 3 [*5:6] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:142:25: Ignoring unsupported: cover '[->' - 142 | { bins bts2 = ( 3 [->5] ) ; } - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:142:19: Ignoring unsupported: cover bin trans list - 142 | { bins bts2 = ( 3 [->5] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:143:25: Ignoring unsupported: cover '[->' - 143 | { bins bts2 = ( 3 [->5:6] ) ; } - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:143:19: Ignoring unsupported: cover bin trans list - 143 | { bins bts2 = ( 3 [->5:6] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:144:25: Ignoring unsupported: cover '[=' - 144 | { bins bts2 = ( 3 [=5] ) ; } - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:144:19: Ignoring unsupported: cover bin trans list - 144 | { bins bts2 = ( 3 [=5] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:145:25: Ignoring unsupported: cover '[=' - 145 | { bins bts2 = ( 3 [=5:6] ) ; } - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:145:19: Ignoring unsupported: cover bin trans list - 145 | { bins bts2 = ( 3 [=5:6] ) ; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:117:4: Ignoring unsupported: covergroup - 117 | covergroup cg_binsoroptions_bk1; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:150:26: Ignoring unsupported: cover bin 'with' specification - 150 | bins div_by_2 = a with (item % 2 == 0); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:151:34: Ignoring unsupported: cover bin 'with' specification - 151 | bins div_by_2_paren[] = a with (item % 2 == 0); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:149:6: Ignoring unsupported: coverpoint - 149 | coverpoint a { - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:148:4: Ignoring unsupported: covergroup - 148 | covergroup cg_coverpoint_ref; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:157:23: Ignoring unsupported: coverage select expression 'binsof' - 157 | bins bin_a = binsof(a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:157:10: Ignoring unsupported: coverage cross bin - 157 | bins bin_a = binsof(a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:158:24: Ignoring unsupported: coverage select expression 'binsof' - 158 | bins bin_ai = binsof(a) iff (!rst); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:158:34: Ignoring unsupported: cover 'iff' - 158 | bins bin_ai = binsof(a) iff (!rst); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:158:10: Ignoring unsupported: coverage cross bin - 158 | bins bin_ai = binsof(a) iff (!rst); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:159:23: Ignoring unsupported: coverage select expression 'binsof' - 159 | bins bin_c = binsof(cp.x); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:159:10: Ignoring unsupported: coverage cross bin - 159 | bins bin_c = binsof(cp.x); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:160:24: Ignoring unsupported: coverage select expression 'binsof' - 160 | bins bin_na = ! binsof(a); +%Warning-COVERIGN: t/t_covergroup_unsup.v:60:3: Ignoring unsupported: covergroup + 60 | covergroup cg_clockingevent() @(posedge clk); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:62:3: Ignoring unsupported: covergroup + 62 | covergroup cg_withfunction() with function sample (a); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:64:24: Ignoring unsupported: coverage '@@' events + 64 | covergroup cg_atat() @@ (begin funca or end funcb); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:64:3: Ignoring unsupported: covergroup + 64 | covergroup cg_atat() @@ (begin funca or end funcb); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:66:3: Ignoring unsupported: covergroup + 66 | covergroup cg_bracket; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:69:3: Ignoring unsupported: covergroup + 69 | covergroup cg_bracket2; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:73:5: Ignoring unsupported: coverpoint + 73 | coverpoint a; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:72:3: Ignoring unsupported: covergroup + 72 | covergroup cg_cp; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:76:18: Ignoring unsupported: cover 'iff' + 76 | coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:76:5: Ignoring unsupported: coverpoint + 76 | coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:75:3: Ignoring unsupported: covergroup + 75 | covergroup cg_cp_iff; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:79:22: Ignoring unsupported: cover 'iff' + 79 | id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:79:9: Ignoring unsupported: coverpoint + 79 | id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:78:3: Ignoring unsupported: covergroup + 78 | covergroup cg_id_cp_iff; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:82:26: Ignoring unsupported: cover 'iff' + 82 | int id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:82:13: Ignoring unsupported: coverpoint + 82 | int id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:81:3: Ignoring unsupported: covergroup + 81 | covergroup cg_id_cp_id1; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:85:30: Ignoring unsupported: cover 'iff' + 85 | var int id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:85:17: Ignoring unsupported: coverpoint + 85 | var int id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:84:3: Ignoring unsupported: covergroup + 84 | covergroup cg_id_cp_id2; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:88:32: Ignoring unsupported: cover 'iff' + 88 | var [3:0] id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:88:19: Ignoring unsupported: coverpoint + 88 | var [3:0] id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:87:3: Ignoring unsupported: covergroup + 87 | covergroup cg_id_cp_id3; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:91:28: Ignoring unsupported: cover 'iff' + 91 | [3:0] id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:91:15: Ignoring unsupported: coverpoint + 91 | [3:0] id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:90:3: Ignoring unsupported: covergroup + 90 | covergroup cg_id_cp_id4; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:94:29: Ignoring unsupported: cover 'iff' + 94 | signed id: coverpoint a iff (b); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:94:16: Ignoring unsupported: coverpoint + 94 | signed id: coverpoint a iff (b); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:93:3: Ignoring unsupported: covergroup + 93 | covergroup cg_id_cp_id5; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:98:16: Ignoring unsupported: cover 'iff' + 98 | cross a, b iff (!rst); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:98:5: Ignoring unsupported: cover cross + 98 | cross a, b iff (!rst); + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:97:3: Ignoring unsupported: covergroup + 97 | covergroup cg_cross; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:101:16: Ignoring unsupported: cover 'iff' + 101 | cross a, b iff (!rst) {} + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:101:5: Ignoring unsupported: cover cross + 101 | cross a, b iff (!rst) {} + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:100:3: Ignoring unsupported: covergroup + 100 | covergroup cg_cross2; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:104:5: Ignoring unsupported: cover cross + 104 | cross a, b { option.comment = "cross"; option.weight = 12; } + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:103:3: Ignoring unsupported: covergroup + 103 | covergroup cg_cross3; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:108:21: Ignoring unsupported: coverage cross 'function' declaration + 108 | function void crossfunc; endfunction + | ^~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:109:18: Ignoring unsupported: coverage select function call + 109 | bins one = crossfunc(); + | ^~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:109:7: Ignoring unsupported: coverage cross bin + 109 | bins one = crossfunc(); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:107:5: Ignoring unsupported: cover cross + 107 | cross a, b { + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:106:3: Ignoring unsupported: covergroup + 106 | covergroup cg_cross4; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:113:26: Ignoring unsupported: cover 'iff' + 113 | my_cg_id: cross a, b iff (!rst); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:113:15: Ignoring unsupported: cover cross + 113 | my_cg_id: cross a, b iff (!rst); + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:112:3: Ignoring unsupported: covergroup + 112 | covergroup cg_cross_id; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:118:15: Ignoring unsupported: cover bin specification + 118 | { bins ba = {a}; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:119:22: Ignoring unsupported: cover 'iff' + 119 | { bins bar = {a} iff (!rst); } + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:119:16: Ignoring unsupported: cover bin specification + 119 | { bins bar = {a} iff (!rst); } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:120:24: Ignoring unsupported: cover bin specification + 120 | { illegal_bins ila = {a}; } | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:160:10: Ignoring unsupported: coverage cross bin - 160 | bins bin_na = ! binsof(a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:162:33: Ignoring unsupported: coverage select expression 'intersect' - 162 | bins bin_d = binsof(a) intersect { b }; - | ^~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:162:10: Ignoring unsupported: coverage cross bin - 162 | bins bin_d = binsof(a) intersect { b }; - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:34: Ignoring unsupported: coverage select expression 'intersect' - 163 | bins bin_nd = ! binsof(a) intersect { b }; - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:10: Ignoring unsupported: coverage cross bin - 163 | bins bin_nd = ! binsof(a) intersect { b }; - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:165:23: Ignoring unsupported: coverage select expression with - 165 | bins bin_e = with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:165:10: Ignoring unsupported: coverage cross bin - 165 | bins bin_e = with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:27: Ignoring unsupported: coverage select expression with - 166 | bins bin_not_e = ! with (a); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:10: Ignoring unsupported: coverage cross bin - 166 | bins bin_not_e = ! with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:168:26: Ignoring unsupported: coverage select expression 'binsof' - 168 | bins bin_par = (binsof(a)); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:168:10: Ignoring unsupported: coverage cross bin - 168 | bins bin_par = (binsof(a)); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:169:25: Ignoring unsupported: coverage select expression 'binsof' - 169 | bins bin_and = binsof(a) && binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:169:38: Ignoring unsupported: coverage select expression 'binsof' - 169 | bins bin_and = binsof(a) && binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:169:35: Ignoring unsupported: coverage select expression '&&' - 169 | bins bin_and = binsof(a) && binsof(b); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:169:10: Ignoring unsupported: coverage cross bin - 169 | bins bin_and = binsof(a) && binsof(b); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:170:24: Ignoring unsupported: coverage select expression 'binsof' - 170 | bins bin_or = binsof(a) || binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:170:37: Ignoring unsupported: coverage select expression 'binsof' - 170 | bins bin_or = binsof(a) || binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:170:34: Ignoring unsupported: coverage select expression '||' - 170 | bins bin_or = binsof(a) || binsof(b); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:170:10: Ignoring unsupported: coverage cross bin - 170 | bins bin_or = binsof(a) || binsof(b); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:171:26: Ignoring unsupported: coverage select expression 'binsof' - 171 | bins bin_with = binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:171:36: Ignoring unsupported: coverage select expression with - 171 | bins bin_with = binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:171:10: Ignoring unsupported: coverage cross bin - 171 | bins bin_with = binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:29: Ignoring unsupported: coverage select expression 'binsof' - 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:42: Ignoring unsupported: coverage select expression 'binsof' - 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:52: Ignoring unsupported: coverage select expression with - 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:39: Ignoring unsupported: coverage select expression '||' - 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:10: Ignoring unsupported: coverage cross bin - 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:173:30: Ignoring unsupported: coverage select expression 'binsof' - 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:173:43: Ignoring unsupported: coverage select expression 'binsof' - 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:173:53: Ignoring unsupported: coverage select expression with - 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:173:40: Ignoring unsupported: coverage select expression '&&' - 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:173:10: Ignoring unsupported: coverage cross bin - 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:174:37: Ignoring unsupported: coverage select expression 'binsof' - 174 | bins bin_multiple_fields = binsof(p.inner_packet.field); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:174:10: Ignoring unsupported: coverage cross bin - 174 | bins bin_multiple_fields = binsof(p.inner_packet.field); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:156:7: Ignoring unsupported: cover cross - 156 | cross a, b { - | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:155:4: Ignoring unsupported: covergroup - 155 | covergroup cg_cross_bins; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:178:4: Ignoring unsupported: covergroup - 178 | covergroup cgArgs(int cg_lim); - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:185:23: Ignoring unsupported: coverage clocking event - 185 | covergroup cov1 @m_z; +%Warning-COVERIGN: t/t_covergroup_unsup.v:121:23: Ignoring unsupported: cover bin specification + 121 | { ignore_bins iga = {a}; } | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:186:10: Ignoring unsupported: coverpoint - 186 | coverpoint m_x; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:187:10: Ignoring unsupported: coverpoint - 187 | coverpoint m_y; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:185:7: Ignoring unsupported: covergroup - 185 | covergroup cov1 @m_z; +%Warning-COVERIGN: t/t_covergroup_unsup.v:123:17: Ignoring unsupported: cover bin specification + 123 | { bins ba[] = {a}; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:124:18: Ignoring unsupported: cover bin specification + 124 | { bins ba[2] = {a}; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:126:21: Ignoring unsupported: cover bin 'with' specification + 126 | { bins ba = {a} with ( b ); } + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:128:25: Ignoring unsupported: cover bin 'wildcard' specification + 128 | { wildcard bins bwa = {a}; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:129:32: Ignoring unsupported: cover bin 'wildcard' 'with' specification + 129 | { wildcard bins bwaw = {a} with ( b ); } + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:131:18: Ignoring unsupported: cover bin 'default' + 131 | { bins def = default; } + | ^~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:132:27: Ignoring unsupported: cover bin 'default' 'sequence' + 132 | { bins defs = default sequence; } + | ^~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:134:16: Ignoring unsupported: cover bin trans list + 134 | { bins bts = ( 1, 2 ); } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:135:7: Ignoring unsupported: cover bin 'wildcard' trans list + 135 | { wildcard bins wbts = ( 1, 2 ); } + | ^~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:136:31: Ignoring unsupported: covergroup value range + 136 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:136:42: Ignoring unsupported: covergroup value range + 136 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:136:57: Ignoring unsupported: covergroup value range + 136 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:136:17: Ignoring unsupported: cover bin trans list + 136 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:138:25: Ignoring unsupported: cover trans set '=>' + 138 | { bins bts2 = ( 1,5 => 6,7 ) ; } + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:138:17: Ignoring unsupported: cover bin trans list + 138 | { bins bts2 = ( 1,5 => 6,7 ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:139:23: Ignoring unsupported: cover '[*' + 139 | { bins bts2 = ( 3 [*5] ) ; } + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:139:17: Ignoring unsupported: cover bin trans list + 139 | { bins bts2 = ( 3 [*5] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:140:23: Ignoring unsupported: cover '[*' + 140 | { bins bts2 = ( 3 [*5:6] ) ; } + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:140:17: Ignoring unsupported: cover bin trans list + 140 | { bins bts2 = ( 3 [*5:6] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:141:23: Ignoring unsupported: cover '[->' + 141 | { bins bts2 = ( 3 [->5] ) ; } + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:141:17: Ignoring unsupported: cover bin trans list + 141 | { bins bts2 = ( 3 [->5] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:142:23: Ignoring unsupported: cover '[->' + 142 | { bins bts2 = ( 3 [->5:6] ) ; } + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:142:17: Ignoring unsupported: cover bin trans list + 142 | { bins bts2 = ( 3 [->5:6] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:143:23: Ignoring unsupported: cover '[=' + 143 | { bins bts2 = ( 3 [=5] ) ; } + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:143:17: Ignoring unsupported: cover bin trans list + 143 | { bins bts2 = ( 3 [=5] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:144:23: Ignoring unsupported: cover '[=' + 144 | { bins bts2 = ( 3 [=5:6] ) ; } + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:144:17: Ignoring unsupported: cover bin trans list + 144 | { bins bts2 = ( 3 [=5:6] ) ; } + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:116:3: Ignoring unsupported: covergroup + 116 | covergroup cg_binsoroptions_bk1; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:149:24: Ignoring unsupported: cover bin 'with' specification + 149 | bins div_by_2 = a with (item % 2 == 0); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:150:32: Ignoring unsupported: cover bin 'with' specification + 150 | bins div_by_2_paren[] = a with (item % 2 == 0); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:148:5: Ignoring unsupported: coverpoint + 148 | coverpoint a { + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:147:3: Ignoring unsupported: covergroup + 147 | covergroup cg_coverpoint_ref; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:156:20: Ignoring unsupported: coverage select expression 'binsof' + 156 | bins bin_a = binsof(a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:156:7: Ignoring unsupported: coverage cross bin + 156 | bins bin_a = binsof(a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:157:21: Ignoring unsupported: coverage select expression 'binsof' + 157 | bins bin_ai = binsof(a) iff (!rst); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:157:31: Ignoring unsupported: cover 'iff' + 157 | bins bin_ai = binsof(a) iff (!rst); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:157:7: Ignoring unsupported: coverage cross bin + 157 | bins bin_ai = binsof(a) iff (!rst); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:158:20: Ignoring unsupported: coverage select expression 'binsof' + 158 | bins bin_c = binsof(cp.x); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:158:7: Ignoring unsupported: coverage cross bin + 158 | bins bin_c = binsof(cp.x); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:159:21: Ignoring unsupported: coverage select expression 'binsof' + 159 | bins bin_na = ! binsof(a); + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:159:7: Ignoring unsupported: coverage cross bin + 159 | bins bin_na = ! binsof(a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:161:30: Ignoring unsupported: coverage select expression 'intersect' + 161 | bins bin_d = binsof(a) intersect { b }; + | ^~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:161:7: Ignoring unsupported: coverage cross bin + 161 | bins bin_d = binsof(a) intersect { b }; + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:162:31: Ignoring unsupported: coverage select expression 'intersect' + 162 | bins bin_nd = ! binsof(a) intersect { b }; + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:162:7: Ignoring unsupported: coverage cross bin + 162 | bins bin_nd = ! binsof(a) intersect { b }; + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:164:20: Ignoring unsupported: coverage select expression with + 164 | bins bin_e = with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:164:7: Ignoring unsupported: coverage cross bin + 164 | bins bin_e = with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:165:24: Ignoring unsupported: coverage select expression with + 165 | bins bin_not_e = ! with (a); + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:165:7: Ignoring unsupported: coverage cross bin + 165 | bins bin_not_e = ! with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:167:23: Ignoring unsupported: coverage select expression 'binsof' + 167 | bins bin_par = (binsof(a)); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:167:7: Ignoring unsupported: coverage cross bin + 167 | bins bin_par = (binsof(a)); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:168:22: Ignoring unsupported: coverage select expression 'binsof' + 168 | bins bin_and = binsof(a) && binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:168:35: Ignoring unsupported: coverage select expression 'binsof' + 168 | bins bin_and = binsof(a) && binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:168:32: Ignoring unsupported: coverage select expression '&&' + 168 | bins bin_and = binsof(a) && binsof(b); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:168:7: Ignoring unsupported: coverage cross bin + 168 | bins bin_and = binsof(a) && binsof(b); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:21: Ignoring unsupported: coverage select expression 'binsof' + 169 | bins bin_or = binsof(a) || binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:34: Ignoring unsupported: coverage select expression 'binsof' + 169 | bins bin_or = binsof(a) || binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:31: Ignoring unsupported: coverage select expression '||' + 169 | bins bin_or = binsof(a) || binsof(b); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:7: Ignoring unsupported: coverage cross bin + 169 | bins bin_or = binsof(a) || binsof(b); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:23: Ignoring unsupported: coverage select expression 'binsof' + 170 | bins bin_with = binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:33: Ignoring unsupported: coverage select expression with + 170 | bins bin_with = binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:7: Ignoring unsupported: coverage cross bin + 170 | bins bin_with = binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:26: Ignoring unsupported: coverage select expression 'binsof' + 171 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:39: Ignoring unsupported: coverage select expression 'binsof' + 171 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:49: Ignoring unsupported: coverage select expression with + 171 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:36: Ignoring unsupported: coverage select expression '||' + 171 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:7: Ignoring unsupported: coverage cross bin + 171 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:27: Ignoring unsupported: coverage select expression 'binsof' + 172 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:40: Ignoring unsupported: coverage select expression 'binsof' + 172 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:50: Ignoring unsupported: coverage select expression with + 172 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:37: Ignoring unsupported: coverage select expression '&&' + 172 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:7: Ignoring unsupported: coverage cross bin + 172 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:34: Ignoring unsupported: coverage select expression 'binsof' + 173 | bins bin_multiple_fields = binsof(p.inner_packet.field); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:7: Ignoring unsupported: coverage cross bin + 173 | bins bin_multiple_fields = binsof(p.inner_packet.field); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:155:5: Ignoring unsupported: cover cross + 155 | cross a, b { + | ^~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:154:3: Ignoring unsupported: covergroup + 154 | covergroup cg_cross_bins; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:177:3: Ignoring unsupported: covergroup + 177 | covergroup cgArgs(int cg_lim); + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:184:21: Ignoring unsupported: coverage clocking event + 184 | covergroup cov1 @m_z; + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:185:7: Ignoring unsupported: coverpoint + 185 | coverpoint m_x; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:195:7: Ignoring unsupported: covergroup - 195 | covergroup extends cg_empty; +%Warning-COVERIGN: t/t_covergroup_unsup.v:186:7: Ignoring unsupported: coverpoint + 186 | coverpoint m_y; | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:184:5: Ignoring unsupported: covergroup + 184 | covergroup cov1 @m_z; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:194:5: Ignoring unsupported: covergroup + 194 | covergroup extends cg_empty; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_unsup.v b/test_regress/t/t_covergroup_unsup.v index dcdac2852..36e6d7aa7 100644 --- a/test_regress/t/t_covergroup_unsup.v +++ b/test_regress/t/t_covergroup_unsup.v @@ -4,209 +4,208 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - class InnerPacket; - bit field; - endclass - class Packet; - InnerPacket inner_packet; - endclass +module t ( + input clk + ); - Packet p; - input clk; - logic rst; - int a; - int b; - logic c; - int cyc = 0; + class InnerPacket; + bit field; + endclass + class Packet; + InnerPacket inner_packet; + endclass - always @(posedge clk) begin - cyc <= cyc + 1; - end + Packet p; + logic rst; + int a; + int b; + logic c; + int cyc = 0; - function automatic void funca(); - endfunction + always @(posedge clk) begin + cyc <= cyc + 1; + end - function automatic void funcb(); - endfunction + function automatic void funca(); + endfunction - // NOTE this grammar hasn't been checked with other simulators, - // is here just to avoid uncovered code lines in the grammar. + function automatic void funcb(); + endfunction - covergroup cg_empty; - endgroup + // NOTE this grammar hasn't been checked with other simulators, + // is here just to avoid uncovered code lines in the grammar. - covergroup cg_opt; - type_option.weight = 1; // cg, cp, cross - type_option.goal = 99; // cg, cp, cross - type_option.comment = "type_option_comment"; // cg, cp, cross - type_option.strobe = 0; // cg - type_option.merge_instances = 1; // cg - type_option.distribute_first = 1; // cg - option.name = "the_name"; // cg - option.weight = 1; // cg, cp, cross - option.goal = 98; // cg, cp, cross - option.comment = "option_comment"; // cg, cp, cross - option.at_least = 20; // cg, cp, cross - option.auto_bin_max = 10; // cg, cp - option.cross_num_print_missing = 2; // cg, cross - option.detect_overlap = 1; // cg, cp - option.per_instance = 1; // cg - option.get_inst_coverage = 1; // cg - endgroup + covergroup cg_empty; + endgroup - covergroup cg_clockingevent() @(posedge clk); - endgroup - covergroup cg_withfunction() with function sample (a); - endgroup - covergroup cg_atat() @@ (begin funca or end funcb); - endgroup - covergroup cg_bracket; - {} - endgroup - covergroup cg_bracket2; - { option.name = "option"; } - endgroup - covergroup cg_cp; - coverpoint a; - endgroup - covergroup cg_cp_iff; - coverpoint a iff (b); - endgroup - covergroup cg_id_cp_iff; - id: coverpoint a iff (b); - endgroup - covergroup cg_id_cp_id1; - int id: coverpoint a iff (b); - endgroup - covergroup cg_id_cp_id2; - var int id: coverpoint a iff (b); - endgroup - covergroup cg_id_cp_id3; - var [3:0] id: coverpoint a iff (b); - endgroup - covergroup cg_id_cp_id4; - [3:0] id: coverpoint a iff (b); - endgroup - covergroup cg_id_cp_id5; - signed id: coverpoint a iff (b); - endgroup + covergroup cg_opt; + type_option.weight = 1; // cg, cp, cross + type_option.goal = 99; // cg, cp, cross + type_option.comment = "type_option_comment"; // cg, cp, cross + type_option.strobe = 0; // cg + type_option.merge_instances = 1; // cg + type_option.distribute_first = 1; // cg + option.name = "the_name"; // cg + option.weight = 1; // cg, cp, cross + option.goal = 98; // cg, cp, cross + option.comment = "option_comment"; // cg, cp, cross + option.at_least = 20; // cg, cp, cross + option.auto_bin_max = 10; // cg, cp + option.cross_num_print_missing = 2; // cg, cross + option.detect_overlap = 1; // cg, cp + option.per_instance = 1; // cg + option.get_inst_coverage = 1; // cg + endgroup - covergroup cg_cross; - cross a, b iff (!rst); - endgroup - covergroup cg_cross2; - cross a, b iff (!rst) {} - endgroup - covergroup cg_cross3; - cross a, b { option.comment = "cross"; option.weight = 12; } - endgroup - covergroup cg_cross4; - cross a, b { - function void crossfunc; endfunction - bins one = crossfunc(); - } - endgroup - covergroup cg_cross_id; - my_cg_id: cross a, b iff (!rst); - endgroup + covergroup cg_clockingevent() @(posedge clk); + endgroup + covergroup cg_withfunction() with function sample (a); + endgroup + covergroup cg_atat() @@ (begin funca or end funcb); + endgroup + covergroup cg_bracket; + {} + endgroup + covergroup cg_bracket2; + { option.name = "option"; } + endgroup + covergroup cg_cp; + coverpoint a; + endgroup + covergroup cg_cp_iff; + coverpoint a iff (b); + endgroup + covergroup cg_id_cp_iff; + id: coverpoint a iff (b); + endgroup + covergroup cg_id_cp_id1; + int id: coverpoint a iff (b); + endgroup + covergroup cg_id_cp_id2; + var int id: coverpoint a iff (b); + endgroup + covergroup cg_id_cp_id3; + var [3:0] id: coverpoint a iff (b); + endgroup + covergroup cg_id_cp_id4; + [3:0] id: coverpoint a iff (b); + endgroup + covergroup cg_id_cp_id5; + signed id: coverpoint a iff (b); + endgroup - covergroup cg_binsoroptions_bk1; - // bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' iffE - { bins ba = {a}; } - { bins bar = {a} iff (!rst); } - { illegal_bins ila = {a}; } - { ignore_bins iga = {a}; } + covergroup cg_cross; + cross a, b iff (!rst); + endgroup + covergroup cg_cross2; + cross a, b iff (!rst) {} + endgroup + covergroup cg_cross3; + cross a, b { option.comment = "cross"; option.weight = 12; } + endgroup + covergroup cg_cross4; + cross a, b { + function void crossfunc; endfunction + bins one = crossfunc(); + } + endgroup + covergroup cg_cross_id; + my_cg_id: cross a, b iff (!rst); + endgroup - { bins ba[] = {a}; } - { bins ba[2] = {a}; } + covergroup cg_binsoroptions_bk1; + // bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' iffE + { bins ba = {a}; } + { bins bar = {a} iff (!rst); } + { illegal_bins ila = {a}; } + { ignore_bins iga = {a}; } - { bins ba = {a} with ( b ); } + { bins ba[] = {a}; } + { bins ba[2] = {a}; } - { wildcard bins bwa = {a}; } - { wildcard bins bwaw = {a} with ( b ); } + { bins ba = {a} with ( b ); } - { bins def = default; } - { bins defs = default sequence; } + { wildcard bins bwa = {a}; } + { wildcard bins bwaw = {a} with ( b ); } - { bins bts = ( 1, 2 ); } - { wildcard bins wbts = ( 1, 2 ); } - { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } + { bins def = default; } + { bins defs = default sequence; } - { bins bts2 = ( 1,5 => 6,7 ) ; } - { bins bts2 = ( 3 [*5] ) ; } - { bins bts2 = ( 3 [*5:6] ) ; } - { bins bts2 = ( 3 [->5] ) ; } - { bins bts2 = ( 3 [->5:6] ) ; } - { bins bts2 = ( 3 [=5] ) ; } - { bins bts2 = ( 3 [=5:6] ) ; } - endgroup + { bins bts = ( 1, 2 ); } + { wildcard bins wbts = ( 1, 2 ); } + { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } - covergroup cg_coverpoint_ref; - coverpoint a { - bins div_by_2 = a with (item % 2 == 0); - bins div_by_2_paren[] = a with (item % 2 == 0); - } - endgroup + { bins bts2 = ( 1,5 => 6,7 ) ; } + { bins bts2 = ( 3 [*5] ) ; } + { bins bts2 = ( 3 [*5:6] ) ; } + { bins bts2 = ( 3 [->5] ) ; } + { bins bts2 = ( 3 [->5:6] ) ; } + { bins bts2 = ( 3 [=5] ) ; } + { bins bts2 = ( 3 [=5:6] ) ; } + endgroup - covergroup cg_cross_bins; - cross a, b { - bins bin_a = binsof(a); - bins bin_ai = binsof(a) iff (!rst); - bins bin_c = binsof(cp.x); - bins bin_na = ! binsof(a); + covergroup cg_coverpoint_ref; + coverpoint a { + bins div_by_2 = a with (item % 2 == 0); + bins div_by_2_paren[] = a with (item % 2 == 0); + } + endgroup - bins bin_d = binsof(a) intersect { b }; - bins bin_nd = ! binsof(a) intersect { b }; + covergroup cg_cross_bins; + cross a, b { + bins bin_a = binsof(a); + bins bin_ai = binsof(a) iff (!rst); + bins bin_c = binsof(cp.x); + bins bin_na = ! binsof(a); - bins bin_e = with (a); - bins bin_not_e = ! with (a); + bins bin_d = binsof(a) intersect { b }; + bins bin_nd = ! binsof(a) intersect { b }; - bins bin_par = (binsof(a)); - bins bin_and = binsof(a) && binsof(b); - bins bin_or = binsof(a) || binsof(b); - bins bin_with = binsof(a) with (a); - bins bin_or_with = binsof(a) || binsof(a) with (a); - bins bin_and_with = binsof(a) && binsof(a) with (a); - bins bin_multiple_fields = binsof(p.inner_packet.field); - } - endgroup + bins bin_e = with (a); + bins bin_not_e = ! with (a); - covergroup cgArgs(int cg_lim); - endgroup + bins bin_par = (binsof(a)); + bins bin_and = binsof(a) && binsof(b); + bins bin_or = binsof(a) || binsof(b); + bins bin_with = binsof(a) with (a); + bins bin_or_with = binsof(a) || binsof(a) with (a); + bins bin_and_with = binsof(a) && binsof(a) with (a); + bins bin_multiple_fields = binsof(p.inner_packet.field); + } + endgroup - class CgCls; - int m_x; - int m_y; - int m_z; - covergroup cov1 @m_z; - coverpoint m_x; - coverpoint m_y; - endgroup + covergroup cgArgs(int cg_lim); + endgroup + + class CgCls; + int m_x; + int m_y; + int m_z; + covergroup cov1 @m_z; + coverpoint m_x; + coverpoint m_y; + endgroup `ifndef T_COVERGROUP_UNSUP_IGN - function new(); cov1 = new; endfunction + function new(); cov1 = new; endfunction `endif - endclass + endclass - class CgEmb; - covergroup extends cg_empty; - endgroup - endclass + class CgEmb; + covergroup extends cg_empty; + endgroup + endclass - initial begin - automatic cg_empty cov1 = new; + initial begin + automatic cg_empty cov1 = new; `ifndef T_COVERGROUP_UNSUP_IGN - automatic cgArgs cov2 = new(2); + automatic cgArgs cov2 = new(2); `endif - end + end - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index 674b3537a..9594487f1 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -6,353 +6,353 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - localparam PKG_PARAM = 1; + localparam PKG_PARAM = 1; - typedef enum int { - FOO = 0, - BAR, - BAZ - } enum_t; + typedef enum int { + FOO = 0, + BAR, + BAZ + } enum_t; endpackage package PkgImp; - import Pkg::*; - export Pkg::*; + import Pkg::*; + export Pkg::*; endpackage class Cls; - int member = 1; - function void method; - if (this != this) $stop; - endfunction + int member = 1; + function void method; + if (this != this) $stop; + endfunction endclass interface Iface ( - input clk + input clk ); - logic ifsig; - modport mp(input ifsig); + logic ifsig; + modport mp(input ifsig); endinterface module t (/*AUTOARG*/ - // Inputs - clk, in - ); - input clk; - input in; + // Inputs + clk, in + ); + input clk; + input in; - // verilator lint_off UNPACKED + // verilator lint_off UNPACKED - typedef enum [2:0] { - ZERO, - ONE = 1 - } e_t; + typedef enum [2:0] { + ZERO, + ONE = 1 + } e_t; - typedef struct packed { - e_t a; - } ps_t; - typedef struct { - logic signed [2:0] a; - } us_t; - typedef union { - logic a; - } union_t; + typedef struct packed { + e_t a; + } ps_t; + typedef struct { + logic signed [2:0] a; + } us_t; + typedef union { + logic a; + } union_t; - const ps_t ps[3]; - us_t us; - union_t unu; + const ps_t ps[3]; + us_t us; + union_t unu; - integer i1; - int array[3]; - initial array = '{1,2,3}; - logic [63:32] downto_32 = '0; + integer i1; + int array[3]; + initial array = '{1,2,3}; + logic [63:32] downto_32 = '0; - function automatic int ident(int value); - return value; - endfunction + function automatic int ident(int value); + return value; + endfunction - Iface the_ifaces [3:0] (.*); + Iface the_ifaces [3:0] (.*); - initial begin - if ($test$plusargs("HELLO")) $display("Hello argument found."); - if (Pkg::FOO == 0) $write(""); - if (ZERO == 0) $write(""); - if ($value$plusargs("TEST=%d", i1)) - $display("value was %d", i1); - else - $display("+TEST= not found"); - if (downto_32[33]) $write(""); - if (downto_32[ident(33)]) $write(""); - if (|downto_32[48:40]) $write(""); - if (|downto_32[55+:3]) $write(""); - if (|downto_32[60-:7]) $write(""); - if (the_ifaces[2].ifsig) $write(""); - #1 $write("After #1 delay"); - end + initial begin + if ($test$plusargs("HELLO")) $display("Hello argument found."); + if (Pkg::FOO == 0) $write(""); + if (ZERO == 0) $write(""); + if ($value$plusargs("TEST=%d", i1)) + $display("value was %d", i1); + else + $display("+TEST= not found"); + if (downto_32[33]) $write(""); + if (downto_32[ident(33)]) $write(""); + if (|downto_32[48:40]) $write(""); + if (|downto_32[55+:3]) $write(""); + if (|downto_32[60-:7]) $write(""); + if (the_ifaces[2].ifsig) $write(""); + #1 $write("After #1 delay"); + end - bit [6:5][4:3][2:1] arraymanyd[10:11][12:13][14:15]; + bit [6:5][4:3][2:1] arraymanyd[10:11][12:13][14:15]; - reg [15:0] pubflat /*verilator public_flat_rw @(posedge clk) */; + reg [15:0] pubflat /*verilator public_flat_rw @(posedge clk) */; - reg [15:0] pubflat_r; - wire [15:0] pubflat_w = pubflat; - int fd; - int i; + reg [15:0] pubflat_r; + wire [15:0] pubflat_w = pubflat; + int fd; + int i; - int q[$]; - int qb[$ : 3]; - int assoc[string]; - int assocassoc[string][real]; - int dyn[]; + int q[$]; + int qb[$ : 3]; + int assoc[string]; + int assocassoc[string][real]; + int dyn[]; - typedef struct packed { - logic nn1; - } nested_named_t; - typedef struct packed { - struct packed { - logic nn2; - } nested_anonymous; - nested_named_t nested_named; - logic [11:10] nn3; - } nibble_t; - nibble_t [5:4] nibblearray[3:2]; + typedef struct packed { + logic nn1; + } nested_named_t; + typedef struct packed { + struct packed { + logic nn2; + } nested_anonymous; + nested_named_t nested_named; + logic [11:10] nn3; + } nibble_t; + nibble_t [5:4] nibblearray[3:2]; - task t; - $display("stmt"); - endtask - function int f(input int v); - $display("stmt"); - return v == 0 ? 99 : ~v + 1; - endfunction + task t; + $display("stmt"); + endtask + function int f(input int v); + $display("stmt"); + return v == 0 ? 99 : ~v + 1; + endfunction - sub sub(.*); + sub sub(.*); - initial begin - int other; - begin //unnamed - for (int i = 0; i < 3; ++i) begin - other = f(i); - $display("stmt %d %d", i, other); - t(); - end + initial begin + int other; + begin //unnamed + for (int i = 0; i < 3; ++i) begin + other = f(i); + $display("stmt %d %d", i, other); + t(); end - begin : named - $display("stmt"); - end : named - end - final begin + end + begin : named $display("stmt"); - end + end : named + end + final begin + $display("stmt"); + end - always @ (in) begin - $display("stmt"); - end - always @ (posedge clk) begin - $display("posedge clk"); - pubflat_r <= pubflat_w; - end - always @ (negedge clk) begin - $display("negedge clk, pfr = %x", pubflat_r); - end + always @ (in) begin + $display("stmt"); + end + always @ (posedge clk) begin + $display("posedge clk"); + pubflat_r <= pubflat_w; + end + always @ (negedge clk) begin + $display("negedge clk, pfr = %x", pubflat_r); + end - int cyc; - int fo; - int sum; - real r; - string str; - int mod_val; - int mod_res; - always_ff @ (posedge clk) begin - cyc <= cyc + 1; - r <= r + 0.01; - fo = cyc; - sub.inc(fo, sum); - sum = sub.f(sum); - $display("[%0t] sum = %d", $time, sum); - $display("a?= %d", $c(1) ? $c32(20) : $c32(30)); + int cyc; + int fo; + int sum; + real r; + string str; + int mod_val; + int mod_res; + always_ff @ (posedge clk) begin + cyc <= cyc + 1; + r <= r + 0.01; + fo = cyc; + sub.inc(fo, sum); + sum = sub.f(sum); + $display("[%0t] sum = %d", $time, sum); + $display("a?= %d", $c(1) ? $c32(20) : $c32(30)); - $c(";"); - $display("%d", $c("0")); - fd = $fopen("/dev/null"); - $fclose(fd); - fd = $fopen("/dev/null", "r"); - $fgetc(fd); // stmt - $fflush(fd); - $fscanf(fd, "%d", sum); - $fdisplay("i = ", sum); - $fwrite(fd, "hello"); - $readmemh(fd, array); - $readmemh(fd, array, 0); - $readmemh(fd, array, 0, 0); + $c(";"); + $display("%d", $c("0")); + fd = $fopen("/dev/null"); + $fclose(fd); + fd = $fopen("/dev/null", "r"); + $fgetc(fd); // stmt + $fflush(fd); + $fscanf(fd, "%d", sum); + $fdisplay("i = ", sum); + $fwrite(fd, "hello"); + $readmemh(fd, array); + $readmemh(fd, array, 0); + $readmemh(fd, array, 0, 0); - sum = 0; - for (int i = 0; i < cyc; ++i) begin - sum += i; - if (sum > 10) break; - else sum += 1; - end - if (cyc == 99) $finish; - if (cyc == 100) $stop; + sum = 0; + for (int i = 0; i < cyc; ++i) begin + sum += i; + if (sum > 10) break; + else sum += 1; + end + if (cyc == 99) $finish; + if (cyc == 100) $stop; - case (in) // synopsys full_case parallel_case - 1: $display("1"); - default: $display("default"); - endcase - priority case (in) - 1: $display("1"); - default: $display("default"); - endcase - unique case (in) - 1: $display("1"); - default: $display("default"); - endcase - unique0 case (in) - 1: $display("1"); - default: $display("default"); - endcase - if (in) $display("1"); else $display("0"); - priority if (in) $display("1"); else $display("0"); - unique if (in) $display("1"); else $display("0"); - unique0 if (in) $display("1"); else $display("0"); + case (in) // synopsys full_case parallel_case + 1: $display("1"); + default: $display("default"); + endcase + priority case (in) + 1: $display("1"); + default: $display("default"); + endcase + unique case (in) + 1: $display("1"); + default: $display("default"); + endcase + unique0 case (in) + 1: $display("1"); + default: $display("default"); + endcase + if (in) $display("1"); else $display("0"); + priority if (in) $display("1"); else $display("0"); + unique if (in) $display("1"); else $display("0"); + unique0 if (in) $display("1"); else $display("0"); - $display($past(cyc), $past(cyc, 1)); + $display($past(cyc), $past(cyc, 1)); - str = $sformatf("cyc=%d", cyc); - $display("str = %s", str); - $display("struct = %p", ps); - $display("%% [%t] [%t] to=%o td=%d", $time, $realtime, $time, $time); - $sscanf("foo=5", "foo=%d", i); - $printtimescale; - if (i != 5) $stop; + str = $sformatf("cyc=%d", cyc); + $display("str = %s", str); + $display("struct = %p", ps); + $display("%% [%t] [%t] to=%o td=%d", $time, $realtime, $time, $time); + $sscanf("foo=5", "foo=%d", i); + $printtimescale; + if (i != 5) $stop; - sum = $random; - sum = $random(10); - sum = $urandom; - sum = $urandom(10); + sum = $random; + sum = $random(10); + sum = $urandom; + sum = $urandom(10); - sum = array.sum with (item * 2); + sum = array.sum with (item * 2); - if (Pkg::PKG_PARAM != 1) $stop; - sub.r = 62.0; + if (Pkg::PKG_PARAM != 1) $stop; + sub.r = 62.0; - mod_res = mod_val % 5; + mod_res = mod_val % 5; - $display("%g", $log10(r)); - $display("%g", $ln(r)); - $display("%g", $exp(r)); - $display("%g", $sqrt(r)); - $display("%g", $floor(r)); - $display("%g", $ceil(r)); - $display("%g", $sin(r)); - $display("%g", $cos(r)); - $display("%g", $tan(r)); - $display("%g", $asin(r)); - $display("%g", $acos(r)); - $display("%g", $atan(r)); - $display("%g", $sinh(r)); - $display("%g", $cosh(r)); - $display("%g", $tanh(r)); - $display("%g", $asinh(r)); - $display("%g", $acosh(r)); - $display("%g", $atanh(r)); + $display("%g", $log10(r)); + $display("%g", $ln(r)); + $display("%g", $exp(r)); + $display("%g", $sqrt(r)); + $display("%g", $floor(r)); + $display("%g", $ceil(r)); + $display("%g", $sin(r)); + $display("%g", $cos(r)); + $display("%g", $tan(r)); + $display("%g", $asin(r)); + $display("%g", $acos(r)); + $display("%g", $atan(r)); + $display("%g", $sinh(r)); + $display("%g", $cosh(r)); + $display("%g", $tanh(r)); + $display("%g", $asinh(r)); + $display("%g", $acosh(r)); + $display("%g", $atanh(r)); - if ($sampled(cyc[1])) $write(""); - if ($rose(cyc)) $write(""); - if ($fell(cyc)) $write(""); - if ($stable(cyc)) $write(""); - if ($changed(cyc)) $write(""); - if ($past(cyc[1])) $write(""); + if ($sampled(cyc[1])) $write(""); + if ($rose(cyc)) $write(""); + if ($fell(cyc)) $write(""); + if ($stable(cyc)) $write(""); + if ($changed(cyc)) $write(""); + if ($past(cyc[1])) $write(""); - if ($rose(cyc, clk)) $write(""); - if ($fell(cyc, clk)) $write(""); - if ($stable(cyc, clk)) $write(""); - if ($changed(cyc, clk)) $write(""); - if ($past(cyc[1], 5)) $write(""); + if ($rose(cyc, clk)) $write(""); + if ($fell(cyc, clk)) $write(""); + if ($stable(cyc, clk)) $write(""); + if ($changed(cyc, clk)) $write(""); + if ($past(cyc[1], 5)) $write(""); - force sum = 10; - repeat (2) if (sum != 10) $stop; - release sum; - end + force sum = 10; + repeat (2) if (sum != 10) $stop; + release sum; + end - property p; - @(posedge clk) ##1 sum[0] - endproperty - property p1; - @(clk) sum[0] - endproperty + property p; + @(posedge clk) ##1 sum[0] + endproperty + property p1; + @(clk) sum[0] + endproperty - assert property (@(clk) not ##1 in); + assert property (@(clk) not ##1 in); - initial begin - assert_simple_immediate_else: assert(0) else $display("fail"); - assert_simple_immediate_stmt: assert(0) $display("pass"); - assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); + initial begin + assert_simple_immediate_else: assert(0) else $display("fail"); + assert_simple_immediate_stmt: assert(0) $display("pass"); + assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); - assume_simple_immediate: assume(0); - assume_simple_immediate_else: assume(0) else $display("fail"); - assume_simple_immediate_stmt: assume(0) $display("pass"); - assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); - end + assume_simple_immediate: assume(0); + assume_simple_immediate_else: assume(0) else $display("fail"); + assume_simple_immediate_stmt: assume(0) $display("pass"); + assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); + end - assert_observed_deferred_immediate: assert #0 (0); - assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); - assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); - assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); + assert_observed_deferred_immediate: assert #0 (0); + assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); + assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); + assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); - assume_observed_deferred_immediate: assume #0 (0); - assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); - assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); - assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); + assume_observed_deferred_immediate: assume #0 (0); + assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); + assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); + assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); - assert_final_deferred_immediate: assert final (0); - assert_final_deferred_immediate_else: assert final (0) else $display("fail"); - assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); - assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); + assert_final_deferred_immediate: assert final (0); + assert_final_deferred_immediate_else: assert final (0) else $display("fail"); + assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); + assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); - assume_final_deferred_immediate: assume final (0); - assume_final_deferred_immediate_else: assume final (0) else $display("fail"); - assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); - assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); + assume_final_deferred_immediate: assume final (0); + assume_final_deferred_immediate_else: assume final (0) else $display("fail"); + assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); + assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); - property prop(); - @(posedge clk) 0 - endproperty + property prop(); + @(posedge clk) 0 + endproperty - assert_concurrent: assert property (prop); - assert_concurrent_else: assert property(prop) else $display("fail"); - assert_concurrent_stmt: assert property(prop) $display("pass"); - assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); + assert_concurrent: assert property (prop); + assert_concurrent_else: assert property(prop) else $display("fail"); + assert_concurrent_stmt: assert property(prop) $display("pass"); + assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); - assume_concurrent: assume property(prop); - assume_concurrent_else: assume property(prop) else $display("fail"); - assume_concurrent_stmt: assume property(prop) $display("pass"); - assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); + assume_concurrent: assume property(prop); + assume_concurrent_else: assume property(prop) else $display("fail"); + assume_concurrent_stmt: assume property(prop) $display("pass"); + assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); - cover_concurrent: cover property(prop); - cover_concurrent_stmt: cover property(prop) $display("pass"); + cover_concurrent: cover property(prop); + cover_concurrent_stmt: cover property(prop) $display("pass"); - int a; - int ao; + int a; + int ao; - // verilator lint_off CASTCONST - initial begin : assert_intrinsic - $cast(ao, a); - end + // verilator lint_off CASTCONST + initial begin : assert_intrinsic + $cast(ao, a); + end - restrict property (@(posedge clk) ##1 a[0]); + restrict property (@(posedge clk) ##1 a[0]); endmodule module sub(input logic clk); - task inc(input int i, output int o); - o = {1'b0, i[31:1]} + 32'd1; - endtask - function int f(input int v); - if (v == 0) return 33; - return {31'd0, v[2]} + 32'd1; - endfunction - real r; + task inc(input int i, output int o); + o = {1'b0, i[31:1]} + 32'd1; + endtask + function int f(input int v); + if (v == 0) return 33; + return {31'd0, v[2]} + 32'd1; + endfunction + real r; endmodule package p; - logic pkgvar; + logic pkgvar; endpackage diff --git a/test_regress/t/t_debug_gate.v b/test_regress/t/t_debug_gate.v index bb5eec667..00996a908 100644 --- a/test_regress/t/t_debug_gate.v +++ b/test_regress/t/t_debug_gate.v @@ -5,24 +5,27 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - o, - // Inputs - i - ); - input i; - output o; - sub sub (.i, .o); +module t ( /*AUTOARG*/ + // Outputs + o, + // Inputs + i +); + input i; + output o; + sub sub ( + .i, + .o + ); endmodule -module sub(/*AUTOARG*/ - // Outputs - o, - // Inputs - i - ); - input i; - output o; - assign o = !i; +module sub ( /*AUTOARG*/ + // Outputs + o, + // Inputs + i +); + input i; + output o; + assign o = !i; endmodule diff --git a/test_regress/t/t_debug_trace.v b/test_regress/t/t_debug_trace.v index f1656701e..accbd71df 100644 --- a/test_regress/t/t_debug_trace.v +++ b/test_regress/t/t_debug_trace.v @@ -5,14 +5,14 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - a - ); - input a; - sub sub (); +module t ( /*AUTOARG*/ + // Inputs + a +); + input a; + sub sub (); endmodule module sub; - reg svar; + reg svar; endmodule diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v index 241d67644..858d0c719 100644 --- a/test_regress/t/t_delay.v +++ b/test_regress/t/t_delay.v @@ -4,57 +4,55 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 100ns/1ns +`timescale 100ns / 1ns -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc; + int cyc; - reg [31:0] dly0; - wire [31:0] dly1; - wire [31:0] dly2 = dly1 + 32'h1; - wire [31:0] dly3; - wire [31:0] dly4; + reg [31:0] dly0; + wire [31:0] dly1; + wire [31:0] dly2 = dly1 + 32'h1; + wire [31:0] dly3; + wire [31:0] dly4; - typedef struct packed { int dly; } dly_s_t; - dly_s_t dly_s; + typedef struct packed {int dly;} dly_s_t; + dly_s_t dly_s; - assign #(1.2000000000000000) dly1 = dly0 + 32'h1; - assign #(sub.delay) dly3 = dly1 + 1; - assign #sub.delay dly4 = dly1 + 1; + assign #(1.2000000000000000) dly1 = dly0 + 32'h1; + assign #(sub.delay) dly3 = dly1 + 1; + assign #sub.delay dly4 = dly1 + 1; - sub sub(); + sub sub (); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - dly0 <= #0 32'h11; - end - else if (cyc == 2) begin - dly0 <= #0.12 dly0 + 32'h12; - end - else if (cyc == 3) begin - if (dly0 !== 32'h23) $stop; - if (dly2 !== 32'h25) $stop; - end - else if (cyc == 4) begin - dly_s.dly = 55; - dly0 <= #(dly_s.dly) 32'h55; - //dly0 <= # dly_s.dly 32'h55; // Unsupported, issue #2410 - end - else if (cyc == 99) begin - if (dly3 !== 32'h57) $stop; - $write("*-* All Finished *-*\n"); - #100 $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + dly0 <= #0 32'h11; + end + else if (cyc == 2) begin + dly0 <= #0.12 dly0 + 32'h12; + end + else if (cyc == 3) begin + if (dly0 !== 32'h23) $stop; + if (dly2 !== 32'h25) $stop; + end + else if (cyc == 4) begin + dly_s.dly = 55; + dly0 <= #(dly_s.dly) 32'h55; + //dly0 <= # dly_s.dly 32'h55; // Unsupported, issue #2410 + end + else if (cyc == 99) begin + if (dly3 !== 32'h57) $stop; + $write("*-* All Finished *-*\n"); + #100 $finish; + end + end endmodule module sub; - realtime delay = 2.3; + realtime delay = 2.3; endmodule diff --git a/test_regress/t/t_delay_compare.v b/test_regress/t/t_delay_compare.v index 31723d1be..b1e83471f 100644 --- a/test_regress/t/t_delay_compare.v +++ b/test_regress/t/t_delay_compare.v @@ -5,33 +5,33 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int tim1; - int tim2; - real rtim1; - real rtim2; + int tim1; + int tim2; + real rtim1; + real rtim2; - // verilator lint_off ZERODLY - initial begin - tim1 = 2; - tim2 = 3; - // verilator lint_off WIDTHEXPAND - # (tim1 < tim2); - // verilator lint_on WIDTHEXPAND - if ($time != 1) $stop; + // verilator lint_off ZERODLY + initial begin + tim1 = 2; + tim2 = 3; + // verilator lint_off WIDTHEXPAND + #(tim1 < tim2); + // verilator lint_on WIDTHEXPAND + if ($time != 1) $stop; - // verilator lint_off WIDTHEXPAND - # (tim1); - // verilator lint_on WIDTHEXPAND - if ($time != 1 + 2) $stop; + // verilator lint_off WIDTHEXPAND + #(tim1); + // verilator lint_on WIDTHEXPAND + if ($time != 1 + 2) $stop; - rtim1 = 2; - rtim2 = 2.6; - # (rtim1 + rtim2); // Rounds up - if ($time != 1 + 2 + 5) $stop; + rtim1 = 2; + rtim2 = 2.6; + #(rtim1 + rtim2); // Rounds up + if ($time != 1 + 2 + 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - // verilator lint_on ZERODLY + $write("*-* All Finished *-*\n"); + $finish; + end + // verilator lint_on ZERODLY endmodule diff --git a/test_regress/t/t_delay_incr.v b/test_regress/t/t_delay_incr.v index 8242d5f92..39d406cac 100644 --- a/test_regress/t/t_delay_incr.v +++ b/test_regress/t/t_delay_incr.v @@ -4,24 +4,22 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 100ns/1ns +`timescale 100ns / 1ns module t; - int ia; - int ib; + int ia; + int ib; - initial begin - ia = 0; - #1 ib = ++ia; - #1 - if (ia !== ib) $stop; + initial begin + ia = 0; + #1 ib = ++ia; + #1 if (ia !== ib) $stop; - #1 ib = ia++; - #1 - if (ia == ib) $stop; - #10; + #1 ib = ia++; + #1 if (ia == ib) $stop; + #10; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index 4622e46ce..3ce50f781 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -1,54 +1,54 @@ -%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing +%Warning-ASSIGNDLY: t/t_delay.v:24:10: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' - 26 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; - | ^ + 24 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; + | ^ ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. -%Warning-ASSIGNDLY: t/t_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing +%Warning-ASSIGNDLY: t/t_delay.v:25:10: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' - 27 | assign #(sub.delay) dly3 = dly1 + 1; - | ^ -%Warning-ASSIGNDLY: t/t_delay.v:28:11: Ignoring timing control on this assignment/primitive due to --no-timing - : ... note: In instance 't' - 28 | assign #sub.delay dly4 = dly1 + 1; - | ^ -%Warning-ASSIGNDLY: t/t_delay.v:35:18: Ignoring timing control on this assignment/primitive due to --no-timing - : ... note: In instance 't' - 35 | dly0 <= #0 32'h11; - | ^ -%Warning-ASSIGNDLY: t/t_delay.v:38:18: Ignoring timing control on this assignment/primitive due to --no-timing - : ... note: In instance 't' - 38 | dly0 <= #0.12 dly0 + 32'h12; - | ^ -%Warning-ASSIGNDLY: t/t_delay.v:46:18: Ignoring timing control on this assignment/primitive due to --no-timing - : ... note: In instance 't' - 46 | dly0 <= #(dly_s.dly) 32'h55; - | ^ -%Warning-STMTDLY: t/t_delay.v:52:10: Ignoring delay on this statement due to --no-timing - : ... note: In instance 't' - 52 | #100 $finish; + 25 | assign #(sub.delay) dly3 = dly1 + 1; | ^ +%Warning-ASSIGNDLY: t/t_delay.v:26:10: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 26 | assign #sub.delay dly4 = dly1 + 1; + | ^ +%Warning-ASSIGNDLY: t/t_delay.v:33:15: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 33 | dly0 <= #0 32'h11; + | ^ +%Warning-ASSIGNDLY: t/t_delay.v:36:15: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 36 | dly0 <= #0.12 dly0 + 32'h12; + | ^ +%Warning-ASSIGNDLY: t/t_delay.v:44:15: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 44 | dly0 <= #(dly_s.dly) 32'h55; + | ^ +%Warning-STMTDLY: t/t_delay.v:50:7: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 50 | #100 $finish; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Warning-BLKSEQ: t/t_delay.v:45:20: Blocking assignment '=' in sequential logic process +%Warning-BLKSEQ: t/t_delay.v:43:17: Blocking assignment '=' in sequential logic process : ... note: In instance 't' : ... Suggest using delayed assignment '<=' - 45 | dly_s.dly = 55; - | ^ + 43 | dly_s.dly = 55; + | ^ ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. -%Warning-UNUSEDSIGNAL: t/t_delay.v:21:16: Signal is not used: 'dly4' +%Warning-UNUSEDSIGNAL: t/t_delay.v:19:15: Signal is not used: 'dly4' : ... note: In instance 't' - 21 | wire [31:0] dly4; - | ^~~~ + 19 | wire [31:0] dly4; + | ^~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. -%Warning-UNUSEDSIGNAL: t/t_delay.v:24:12: Signal is not used: 'dly_s' +%Warning-UNUSEDSIGNAL: t/t_delay.v:22:11: Signal is not used: 'dly_s' : ... note: In instance 't' - 24 | dly_s_t dly_s; - | ^~~~~ -%Warning-UNUSEDSIGNAL: t/t_delay.v:59:13: Signal is not used: 'delay' + 22 | dly_s_t dly_s; + | ^~~~~ +%Warning-UNUSEDSIGNAL: t/t_delay.v:57:12: Signal is not used: 'delay' : ... note: In instance 't.sub' - 59 | realtime delay = 2.3; - | ^~~~~ + 57 | realtime delay = 2.3; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_delay_var.v b/test_regress/t/t_delay_var.v index a74b0857a..b7be09350 100644 --- a/test_regress/t/t_delay_var.v +++ b/test_regress/t/t_delay_var.v @@ -5,26 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 module t; - parameter PDLY = 1.2; - real rdly = 1.3; - integer idly = 1; + parameter PDLY = 1.2; + real rdly = 1.3; + integer idly = 1; - reg in = 1'b0; + reg in = 1'b0; - wire #1.1 d_const = in; - wire #idly d_int = in; - wire #rdly d_real = in; - wire #PDLY d_param = in; + wire #1.1 d_const = in; + wire #idly d_int = in; + wire #rdly d_real = in; + wire #PDLY d_param = in; - initial begin - #2 in = 1'b1; - #100; - if (d_const != 1) $stop; - if (d_int != 1) $stop; - if (d_real != 1) $stop; - if (d_param != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #2 in = 1'b1; + #100; + if (d_const != 1) $stop; + if (d_int != 1) $stop; + if (d_real != 1) $stop; + if (d_param != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_depth_flop.v b/test_regress/t/t_depth_flop.v index fd4f80dc0..ed0ea0c3f 100644 --- a/test_regress/t/t_depth_flop.v +++ b/test_regress/t/t_depth_flop.v @@ -4,80 +4,81 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8, clk_9, clk_10, - clk_11, clk_12, clk_13, clk_14, clk_15, clk_16, clk_17, clk_18, clk_19, - rstn_0, rstn_1, rstn_2, rstn_3, rstn_4, rstn_5, rstn_6, rstn_7, rstn_8, - rstn_9, rstn_10, rstn_11, rstn_12, rstn_13, rstn_14, rstn_15, rstn_16, - rstn_17, rstn_18, rstn_19 - ); + // Outputs + out, + // Inputs + clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8, clk_9, clk_10, + clk_11, clk_12, clk_13, clk_14, clk_15, clk_16, clk_17, clk_18, clk_19, + rstn_0, rstn_1, rstn_2, rstn_3, rstn_4, rstn_5, rstn_6, rstn_7, rstn_8, + rstn_9, rstn_10, rstn_11, rstn_12, rstn_13, rstn_14, rstn_15, rstn_16, + rstn_17, rstn_18, rstn_19 + ); - input clk_0; - input clk_1; - input clk_2; - input clk_3; - input clk_4; - input clk_5; - input clk_6; - input clk_7; - input clk_8; - input clk_9; - input clk_10; - input clk_11; - input clk_12; - input clk_13; - input clk_14; - input clk_15; - input clk_16; - input clk_17; - input clk_18; - input clk_19; - input rstn_0; - input rstn_1; - input rstn_2; - input rstn_3; - input rstn_4; - input rstn_5; - input rstn_6; - input rstn_7; - input rstn_8; - input rstn_9; - input rstn_10; - input rstn_11; - input rstn_12; - input rstn_13; - input rstn_14; - input rstn_15; - input rstn_16; - input rstn_17; - input rstn_18; - input rstn_19; + input clk_0; + input clk_1; + input clk_2; + input clk_3; + input clk_4; + input clk_5; + input clk_6; + input clk_7; + input clk_8; + input clk_9; + input clk_10; + input clk_11; + input clk_12; + input clk_13; + input clk_14; + input clk_15; + input clk_16; + input clk_17; + input clk_18; + input clk_19; + input rstn_0; + input rstn_1; + input rstn_2; + input rstn_3; + input rstn_4; + input rstn_5; + input rstn_6; + input rstn_7; + input rstn_8; + input rstn_9; + input rstn_10; + input rstn_11; + input rstn_12; + input rstn_13; + input rstn_14; + input rstn_15; + input rstn_16; + input rstn_17; + input rstn_18; + input rstn_19; - // verilator lint_off MULTIDRIVEN - output reg out [0:29-1]; + // verilator lint_off MULTIDRIVEN + output reg out [0:29-1]; - always_ff @(posedge clk_0, negedge rstn_0) if ((rstn_0 == 0)) out[0] <= 0; - always_ff @(posedge clk_1, negedge rstn_1) if ((rstn_1 == 0)) out[1] <= 0; - always_ff @(posedge clk_2, negedge rstn_2) if ((rstn_2 == 0)) out[2] <= 0; - always_ff @(posedge clk_3, negedge rstn_3) if ((rstn_3 == 0)) out[3] <= 0; - always_ff @(posedge clk_4, negedge rstn_4) if ((rstn_4 == 0)) out[4] <= 0; - always_ff @(posedge clk_5, negedge rstn_5) if ((rstn_5 == 0)) out[5] <= 0; - always_ff @(posedge clk_6, negedge rstn_6) if ((rstn_6 == 0)) out[6] <= 0; - always_ff @(posedge clk_7, negedge rstn_7) if ((rstn_7 == 0)) out[7] <= 0; - always_ff @(posedge clk_8, negedge rstn_8) if ((rstn_8 == 0)) out[8] <= 0; - always_ff @(posedge clk_9, negedge rstn_9) if ((rstn_9 == 0)) out[9] <= 0; - always_ff @(posedge clk_10, negedge rstn_10) if ((rstn_10 == 0)) out[10] <= 0; - always_ff @(posedge clk_11, negedge rstn_11) if ((rstn_11 == 0)) out[11] <= 0; - always_ff @(posedge clk_12, negedge rstn_12) if ((rstn_12 == 0)) out[12] <= 0; - always_ff @(posedge clk_13, negedge rstn_13) if ((rstn_13 == 0)) out[13] <= 0; - always_ff @(posedge clk_14, negedge rstn_14) if ((rstn_14 == 0)) out[14] <= 0; - always_ff @(posedge clk_15, negedge rstn_15) if ((rstn_15 == 0)) out[15] <= 0; - always_ff @(posedge clk_16, negedge rstn_16) if ((rstn_16 == 0)) out[16] <= 0; - always_ff @(posedge clk_17, negedge rstn_17) if ((rstn_17 == 0)) out[17] <= 0; - always_ff @(posedge clk_18, negedge rstn_18) if ((rstn_18 == 0)) out[18] <= 0; - always_ff @(posedge clk_19, negedge rstn_19) if ((rstn_19 == 0)) out[19] <= 0; + always_ff @(posedge clk_0, negedge rstn_0) if ((rstn_0 == 0)) out[0] <= 0; + always_ff @(posedge clk_1, negedge rstn_1) if ((rstn_1 == 0)) out[1] <= 0; + always_ff @(posedge clk_2, negedge rstn_2) if ((rstn_2 == 0)) out[2] <= 0; + always_ff @(posedge clk_3, negedge rstn_3) if ((rstn_3 == 0)) out[3] <= 0; + always_ff @(posedge clk_4, negedge rstn_4) if ((rstn_4 == 0)) out[4] <= 0; + always_ff @(posedge clk_5, negedge rstn_5) if ((rstn_5 == 0)) out[5] <= 0; + always_ff @(posedge clk_6, negedge rstn_6) if ((rstn_6 == 0)) out[6] <= 0; + always_ff @(posedge clk_7, negedge rstn_7) if ((rstn_7 == 0)) out[7] <= 0; + always_ff @(posedge clk_8, negedge rstn_8) if ((rstn_8 == 0)) out[8] <= 0; + always_ff @(posedge clk_9, negedge rstn_9) if ((rstn_9 == 0)) out[9] <= 0; + always_ff @(posedge clk_10, negedge rstn_10) if ((rstn_10 == 0)) out[10] <= 0; + always_ff @(posedge clk_11, negedge rstn_11) if ((rstn_11 == 0)) out[11] <= 0; + always_ff @(posedge clk_12, negedge rstn_12) if ((rstn_12 == 0)) out[12] <= 0; + always_ff @(posedge clk_13, negedge rstn_13) if ((rstn_13 == 0)) out[13] <= 0; + always_ff @(posedge clk_14, negedge rstn_14) if ((rstn_14 == 0)) out[14] <= 0; + always_ff @(posedge clk_15, negedge rstn_15) if ((rstn_15 == 0)) out[15] <= 0; + always_ff @(posedge clk_16, negedge rstn_16) if ((rstn_16 == 0)) out[16] <= 0; + always_ff @(posedge clk_17, negedge rstn_17) if ((rstn_17 == 0)) out[17] <= 0; + always_ff @(posedge clk_18, negedge rstn_18) if ((rstn_18 == 0)) out[18] <= 0; + always_ff @(posedge clk_19, negedge rstn_19) if ((rstn_19 == 0)) out[19] <= 0; endmodule diff --git a/test_regress/t/t_detectarray_1.v b/test_regress/t/t_detectarray_1.v index d0e4b2927..b6422f59b 100644 --- a/test_regress/t/t_detectarray_1.v +++ b/test_regress/t/t_detectarray_1.v @@ -7,34 +7,32 @@ localparam ID_MSB = 1; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - typedef struct packed { - logic [ID_MSB:0] id; - } context_t; + typedef struct packed {logic [ID_MSB:0] id;} context_t; - context_t tsb; + context_t tsb; - assign tsb.id = {tsb.id[0], clk}; + assign tsb.id = {tsb.id[0], clk}; - initial begin - tsb.id = 0; - end + initial begin + tsb.id = 0; + end - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE - $write("tsb.id = %x\n", tsb.id); + $write("tsb.id = %x\n", tsb.id); `endif - if (tsb.id[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (tsb.id[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_detectarray_2.v b/test_regress/t/t_detectarray_2.v index 2694efdb2..bd4c7c278 100644 --- a/test_regress/t/t_detectarray_2.v +++ b/test_regress/t/t_detectarray_2.v @@ -7,34 +7,30 @@ localparam ID_MSB = 1; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef struct packed { - logic [1:0] id; - } context_t; + typedef struct packed {logic [1:0] id;} context_t; - context_t tsb; + context_t tsb; - assign tsb.id = {tsb.id[0], clk}; + assign tsb.id = {tsb.id[0], clk}; - initial begin - tsb.id = 0; - end + initial begin + tsb.id = 0; + end - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE - $write("tsb.id = %x\n", tsb.id); + $write("tsb.id = %x\n", tsb.id); `endif - if (tsb.id[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (tsb.id[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_detectarray_3.v b/test_regress/t/t_detectarray_3.v index fe0060533..89788a97b 100644 --- a/test_regress/t/t_detectarray_3.v +++ b/test_regress/t/t_detectarray_3.v @@ -7,32 +7,32 @@ localparam ID_MSB = 1; -module t (/*AUTOARG*/ - // Inputs - clk, - res - ); - input clk; - output [8:0][8:0] res; +module t ( /*AUTOARG*/ + // Inputs + clk, + res +); + input clk; + output [8:0][8:0] res; - logic a = 1'b1; - logic [8:0] b [8:0]; // where the error is reported - logic [8:0][8:0] c; // where the error is reported + logic a = 1'b1; + logic [8:0] b[8:0]; // where the error is reported + logic [8:0][8:0] c; // where the error is reported - // following just to make c as circular - assign c[0] = c[0] | a << 1; - assign b[0] = b[0] | a << 2; + // following just to make c as circular + assign c[0] = c[0] | a << 1; + assign b[0] = b[0] | a << 2; - assign res[0] = c[0]; - assign res[1] = b[0]; + assign res[0] = c[0]; + assign res[1] = b[0]; - always @(posedge clk or negedge clk) begin + always @(posedge clk or negedge clk) begin - if (res != 0) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (res != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dfg_3676.v b/test_regress/t/t_dfg_3676.v index fdc6cb2b8..f7cd6d2f8 100644 --- a/test_regress/t/t_dfg_3676.v +++ b/test_regress/t/t_dfg_3676.v @@ -6,19 +6,19 @@ // verilator lint_off UNOPTFLAT -module t( - input wire [3:0] i, - output wire [2:0][3:0] o +module t ( + input wire [3:0] i, + output wire [2:0][3:0] o ); - wire [2:0][3:0] v; + wire [2:0][3:0] v; - // This circular logic used to trip up DFG decomposition + // This circular logic used to trip up DFG decomposition - assign v[0] = i; - assign v[1][0] = v[0][1] | v[0][0]; + assign v[0] = i; + assign v[1][0] = v[0][1] | v[0][0]; - assign o[1][2] = v[0][2]; - assign o[2][1:0] = {v[1][0] , o[1][0]}; + assign o[1][2] = v[0][2]; + assign o[2][1:0] = {v[1][0], o[1][0]}; endmodule diff --git a/test_regress/t/t_dfg_3679.v b/test_regress/t/t_dfg_3679.v index f9b336625..324307103 100644 --- a/test_regress/t/t_dfg_3679.v +++ b/test_regress/t/t_dfg_3679.v @@ -4,35 +4,33 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - reg [31:0] dly0; + reg [31:0] dly0; - // DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2', - // but the 'dly0 + 1' term having multiple sinks needs to considered. - wire [31:0] dly1 = dly0 + 32'h1; - wire [31:0] dly2 = dly1 + 32'h1; - wire [31:0] dly3 = dly0 + 32'h1; + // DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2', + // but the 'dly0 + 1' term having multiple sinks needs to considered. + wire [31:0] dly1 = dly0 + 32'h1; + wire [31:0] dly2 = dly1 + 32'h1; + wire [31:0] dly3 = dly0 + 32'h1; - always @ (posedge clk) begin - $display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3); - cyc <= cyc + 1; - if (cyc == 1) begin - dly0 <= 32'h55; - end - else if (cyc == 3) begin - if (dly1 !== 32'h56) $stop; - if (dly2 !== 32'h57) $stop; - if (dly3 !== 32'h56) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3); + cyc <= cyc + 1; + if (cyc == 1) begin + dly0 <= 32'h55; + end + else if (cyc == 3) begin + if (dly1 !== 32'h56) $stop; + if (dly2 !== 32'h57) $stop; + if (dly3 !== 32'h56) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dfg_3726.v b/test_regress/t/t_dfg_3726.v index 3009d7545..c9e151380 100644 --- a/test_regress/t/t_dfg_3726.v +++ b/test_regress/t/t_dfg_3726.v @@ -4,16 +4,16 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - x, - // Inputs - i - ); +module t ( /*AUTOARG*/ + // Outputs + x, + // Inputs + i +); - input i; - output x; + input i; + output x; - assign x = (i ? 0 : 1) && 1; + assign x = (i ? 0 : 1) && 1; endmodule diff --git a/test_regress/t/t_dfg_bin_to_one_hot.v b/test_regress/t/t_dfg_bin_to_one_hot.v index dad77a90f..dafd2bf0f 100644 --- a/test_regress/t/t_dfg_bin_to_one_hot.v +++ b/test_regress/t/t_dfg_bin_to_one_hot.v @@ -13,291 +13,291 @@ module t ( input clk ); - reg [31:0] cyc = 0; - reg [6:0] cntA = 0; - reg [6:0] cntB = 0; - reg [6:0] cntC = 0; - reg [6:0] cntD = 0; + reg [31:0] cyc = 0; + reg [6:0] cntA = 0; + reg [6:0] cntB = 0; + reg [6:0] cntC = 0; + reg [6:0] cntD = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc[0]) cntA <= cntA + 7'd1; - if (cntA[0]) cntB <= cntB + 7'd1; - if (cntB[0]) cntC <= cntC + 7'd1; - if (cntC[0]) cntD <= cntD + 7'd1; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc[0]) cntA <= cntA + 7'd1; + if (cntA[0]) cntB <= cntB + 7'd1; + if (cntB[0]) cntC <= cntC + 7'd1; + if (cntC[0]) cntD <= cntD + 7'd1; - if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - // Should create decoder - wire [127:0] cntAOneHot = { - cntA == 7'd127, - cntA == 7'd126, - cntA == 7'd125, - cntA == 7'd124, - cntA == 7'd123, - cntA == 7'd122, - cntA == 7'd121, - cntA == 7'd120, - cntA == 7'd119, - cntA == 7'd118, - cntA == 7'd117, - cntA == 7'd116, - cntA == 7'd115, - cntA == 7'd114, - cntA == 7'd113, - cntA == 7'd112, - cntA == 7'd111, - cntA == 7'd110, - cntA == 7'd109, - cntA == 7'd108, - cntA == 7'd107, - cntA == 7'd106, - cntA == 7'd105, - cntA == 7'd104, - cntA == 7'd103, - cntA == 7'd102, - cntA == 7'd101, - cntA == 7'd100, - cntA == 7'd99, - cntA == 7'd98, - cntA == 7'd97, - cntA == 7'd96, - cntA == 7'd95, - cntA == 7'd94, - cntA == 7'd93, - cntA == 7'd92, - cntA == 7'd91, - cntA == 7'd90, - cntA == 7'd89, - cntA == 7'd88, - cntA == 7'd87, - cntA == 7'd86, - cntA == 7'd85, - cntA == 7'd84, - cntA == 7'd83, - cntA == 7'd82, - cntA == 7'd81, - cntA == 7'd80, - cntA == 7'd79, - cntA == 7'd78, - cntA == 7'd77, - cntA == 7'd76, - cntA == 7'd75, - cntA == 7'd74, - cntA == 7'd73, - cntA == 7'd72, - cntA == 7'd71, - cntA == 7'd70, - cntA == 7'd69, - cntA == 7'd68, - cntA == 7'd67, - cntA == 7'd66, - cntA == 7'd65, - cntA == 7'd64, - cntA == 7'd63, - cntA == 7'd62, - cntA == 7'd61, - cntA == 7'd60, - cntA == 7'd59, - cntA == 7'd58, - cntA == 7'd57, - cntA == 7'd56, - cntA == 7'd55, - cntA == 7'd54, - cntA == 7'd53, - cntA == 7'd52, - cntA == 7'd51, - cntA == 7'd50, - cntA == 7'd49, - cntA == 7'd48, - cntA == 7'd47, - cntA == 7'd46, - cntA == 7'd45, - cntA == 7'd44, - cntA == 7'd43, - cntA == 7'd42, - cntA == 7'd41, - cntA == 7'd40, - cntA == 7'd39, - cntA == 7'd38, - cntA == 7'd37, - cntA == 7'd36, - cntA == 7'd35, - cntA == 7'd34, - cntA == 7'd33, - cntA == 7'd32, - cntA == 7'd31, - cntA == 7'd30, - cntA == 7'd29, - cntA == 7'd28, - cntA == 7'd27, - cntA == 7'd26, - cntA == 7'd25, - cntA == 7'd24, - cntA == 7'd23, - cntA == 7'd22, - cntA == 7'd21, - cntA == 7'd20, - cntA == 7'd19, - cntA == 7'd18, - cntA == 7'd17, - cntA == 7'd16, - cntA == 7'd15, - cntA == 7'd14, - cntA == 7'd13, - cntA == 7'd12, - cntA == 7'd11, - cntA == 7'd10, - cntA == 7'd9, - cntA == 7'd8, - cntA == 7'd7, - cntA == 7'd6, - cntA == 7'd5, - cntA == 7'd4, - cntA == 7'd3, - cntA == 7'd2, - cntA == 7'd1, - cntA == 7'd0 - }; + // Should create decoder + wire [127:0] cntAOneHot = { + cntA == 7'd127, + cntA == 7'd126, + cntA == 7'd125, + cntA == 7'd124, + cntA == 7'd123, + cntA == 7'd122, + cntA == 7'd121, + cntA == 7'd120, + cntA == 7'd119, + cntA == 7'd118, + cntA == 7'd117, + cntA == 7'd116, + cntA == 7'd115, + cntA == 7'd114, + cntA == 7'd113, + cntA == 7'd112, + cntA == 7'd111, + cntA == 7'd110, + cntA == 7'd109, + cntA == 7'd108, + cntA == 7'd107, + cntA == 7'd106, + cntA == 7'd105, + cntA == 7'd104, + cntA == 7'd103, + cntA == 7'd102, + cntA == 7'd101, + cntA == 7'd100, + cntA == 7'd99, + cntA == 7'd98, + cntA == 7'd97, + cntA == 7'd96, + cntA == 7'd95, + cntA == 7'd94, + cntA == 7'd93, + cntA == 7'd92, + cntA == 7'd91, + cntA == 7'd90, + cntA == 7'd89, + cntA == 7'd88, + cntA == 7'd87, + cntA == 7'd86, + cntA == 7'd85, + cntA == 7'd84, + cntA == 7'd83, + cntA == 7'd82, + cntA == 7'd81, + cntA == 7'd80, + cntA == 7'd79, + cntA == 7'd78, + cntA == 7'd77, + cntA == 7'd76, + cntA == 7'd75, + cntA == 7'd74, + cntA == 7'd73, + cntA == 7'd72, + cntA == 7'd71, + cntA == 7'd70, + cntA == 7'd69, + cntA == 7'd68, + cntA == 7'd67, + cntA == 7'd66, + cntA == 7'd65, + cntA == 7'd64, + cntA == 7'd63, + cntA == 7'd62, + cntA == 7'd61, + cntA == 7'd60, + cntA == 7'd59, + cntA == 7'd58, + cntA == 7'd57, + cntA == 7'd56, + cntA == 7'd55, + cntA == 7'd54, + cntA == 7'd53, + cntA == 7'd52, + cntA == 7'd51, + cntA == 7'd50, + cntA == 7'd49, + cntA == 7'd48, + cntA == 7'd47, + cntA == 7'd46, + cntA == 7'd45, + cntA == 7'd44, + cntA == 7'd43, + cntA == 7'd42, + cntA == 7'd41, + cntA == 7'd40, + cntA == 7'd39, + cntA == 7'd38, + cntA == 7'd37, + cntA == 7'd36, + cntA == 7'd35, + cntA == 7'd34, + cntA == 7'd33, + cntA == 7'd32, + cntA == 7'd31, + cntA == 7'd30, + cntA == 7'd29, + cntA == 7'd28, + cntA == 7'd27, + cntA == 7'd26, + cntA == 7'd25, + cntA == 7'd24, + cntA == 7'd23, + cntA == 7'd22, + cntA == 7'd21, + cntA == 7'd20, + cntA == 7'd19, + cntA == 7'd18, + cntA == 7'd17, + cntA == 7'd16, + cntA == 7'd15, + cntA == 7'd14, + cntA == 7'd13, + cntA == 7'd12, + cntA == 7'd11, + cntA == 7'd10, + cntA == 7'd9, + cntA == 7'd8, + cntA == 7'd7, + cntA == 7'd6, + cntA == 7'd5, + cntA == 7'd4, + cntA == 7'd3, + cntA == 7'd2, + cntA == 7'd1, + cntA == 7'd0 + }; - // Should create decoder - with temporary needed for index variabls - wire [127:0] notCntAOneHot = { - ~cntA == 7'd127, - ~cntA == 7'd126, - ~cntA == 7'd125, - ~cntA == 7'd124, - ~cntA == 7'd123, - ~cntA == 7'd122, - ~cntA == 7'd121, - ~cntA == 7'd120, - ~cntA == 7'd119, - ~cntA == 7'd118, - ~cntA == 7'd117, - ~cntA == 7'd116, - ~cntA == 7'd115, - ~cntA == 7'd114, - ~cntA == 7'd113, - ~cntA == 7'd112, - ~cntA == 7'd111, - ~cntA == 7'd110, - ~cntA == 7'd109, - ~cntA == 7'd108, - ~cntA == 7'd107, - ~cntA == 7'd106, - ~cntA == 7'd105, - ~cntA == 7'd104, - ~cntA == 7'd103, - ~cntA == 7'd102, - ~cntA == 7'd101, - ~cntA == 7'd100, - ~cntA == 7'd99, - ~cntA == 7'd98, - ~cntA == 7'd97, - ~cntA == 7'd96, - ~cntA == 7'd95, - ~cntA == 7'd94, - ~cntA == 7'd93, - ~cntA == 7'd92, - ~cntA == 7'd91, - ~cntA == 7'd90, - ~cntA == 7'd89, - ~cntA == 7'd88, - ~cntA == 7'd87, - ~cntA == 7'd86, - ~cntA == 7'd85, - ~cntA == 7'd84, - ~cntA == 7'd83, - ~cntA == 7'd82, - ~cntA == 7'd81, - ~cntA == 7'd80, - ~cntA == 7'd79, - ~cntA == 7'd78, - ~cntA == 7'd77, - ~cntA == 7'd76, - ~cntA == 7'd75, - ~cntA == 7'd74, - ~cntA == 7'd73, - ~cntA == 7'd72, - ~cntA == 7'd71, - ~cntA == 7'd70, - ~cntA == 7'd69, - ~cntA == 7'd68, - ~cntA == 7'd67, - ~cntA == 7'd66, - ~cntA == 7'd65, - ~cntA == 7'd64, - ~cntA == 7'd63, - ~cntA == 7'd62, - ~cntA == 7'd61, - ~cntA == 7'd60, - ~cntA == 7'd59, - ~cntA == 7'd58, - ~cntA == 7'd57, - ~cntA == 7'd56, - ~cntA == 7'd55, - ~cntA == 7'd54, - ~cntA == 7'd53, - ~cntA == 7'd52, - ~cntA == 7'd51, - ~cntA == 7'd50, - ~cntA == 7'd49, - ~cntA == 7'd48, - ~cntA == 7'd47, - ~cntA == 7'd46, - ~cntA == 7'd45, - ~cntA == 7'd44, - ~cntA == 7'd43, - ~cntA == 7'd42, - ~cntA == 7'd41, - ~cntA == 7'd40, - ~cntA == 7'd39, - ~cntA == 7'd38, - ~cntA == 7'd37, - ~cntA == 7'd36, - ~cntA == 7'd35, - ~cntA == 7'd34, - ~cntA == 7'd33, - ~cntA == 7'd32, - ~cntA == 7'd31, - ~cntA == 7'd30, - ~cntA == 7'd29, - ~cntA == 7'd28, - ~cntA == 7'd27, - ~cntA == 7'd26, - ~cntA == 7'd25, - ~cntA == 7'd24, - ~cntA == 7'd23, - ~cntA == 7'd22, - ~cntA == 7'd21, - ~cntA == 7'd20, - ~cntA == 7'd19, - ~cntA == 7'd18, - ~cntA == 7'd17, - ~cntA == 7'd16, - ~cntA == 7'd15, - ~cntA == 7'd14, - ~cntA == 7'd13, - ~cntA == 7'd12, - ~cntA == 7'd11, - ~cntA == 7'd10, - ~cntA == 7'd9, - ~cntA == 7'd8, - ~cntA == 7'd7, - ~cntA == 7'd6, - ~cntA == 7'd5, - ~cntA == 7'd4, - ~cntA == 7'd3, - ~cntA == 7'd2, - ~cntA == 7'd1, - ~cntA == 7'd0 - }; + // Should create decoder - with temporary needed for index variabls + wire [127:0] notCntAOneHot = { + ~cntA == 7'd127, + ~cntA == 7'd126, + ~cntA == 7'd125, + ~cntA == 7'd124, + ~cntA == 7'd123, + ~cntA == 7'd122, + ~cntA == 7'd121, + ~cntA == 7'd120, + ~cntA == 7'd119, + ~cntA == 7'd118, + ~cntA == 7'd117, + ~cntA == 7'd116, + ~cntA == 7'd115, + ~cntA == 7'd114, + ~cntA == 7'd113, + ~cntA == 7'd112, + ~cntA == 7'd111, + ~cntA == 7'd110, + ~cntA == 7'd109, + ~cntA == 7'd108, + ~cntA == 7'd107, + ~cntA == 7'd106, + ~cntA == 7'd105, + ~cntA == 7'd104, + ~cntA == 7'd103, + ~cntA == 7'd102, + ~cntA == 7'd101, + ~cntA == 7'd100, + ~cntA == 7'd99, + ~cntA == 7'd98, + ~cntA == 7'd97, + ~cntA == 7'd96, + ~cntA == 7'd95, + ~cntA == 7'd94, + ~cntA == 7'd93, + ~cntA == 7'd92, + ~cntA == 7'd91, + ~cntA == 7'd90, + ~cntA == 7'd89, + ~cntA == 7'd88, + ~cntA == 7'd87, + ~cntA == 7'd86, + ~cntA == 7'd85, + ~cntA == 7'd84, + ~cntA == 7'd83, + ~cntA == 7'd82, + ~cntA == 7'd81, + ~cntA == 7'd80, + ~cntA == 7'd79, + ~cntA == 7'd78, + ~cntA == 7'd77, + ~cntA == 7'd76, + ~cntA == 7'd75, + ~cntA == 7'd74, + ~cntA == 7'd73, + ~cntA == 7'd72, + ~cntA == 7'd71, + ~cntA == 7'd70, + ~cntA == 7'd69, + ~cntA == 7'd68, + ~cntA == 7'd67, + ~cntA == 7'd66, + ~cntA == 7'd65, + ~cntA == 7'd64, + ~cntA == 7'd63, + ~cntA == 7'd62, + ~cntA == 7'd61, + ~cntA == 7'd60, + ~cntA == 7'd59, + ~cntA == 7'd58, + ~cntA == 7'd57, + ~cntA == 7'd56, + ~cntA == 7'd55, + ~cntA == 7'd54, + ~cntA == 7'd53, + ~cntA == 7'd52, + ~cntA == 7'd51, + ~cntA == 7'd50, + ~cntA == 7'd49, + ~cntA == 7'd48, + ~cntA == 7'd47, + ~cntA == 7'd46, + ~cntA == 7'd45, + ~cntA == 7'd44, + ~cntA == 7'd43, + ~cntA == 7'd42, + ~cntA == 7'd41, + ~cntA == 7'd40, + ~cntA == 7'd39, + ~cntA == 7'd38, + ~cntA == 7'd37, + ~cntA == 7'd36, + ~cntA == 7'd35, + ~cntA == 7'd34, + ~cntA == 7'd33, + ~cntA == 7'd32, + ~cntA == 7'd31, + ~cntA == 7'd30, + ~cntA == 7'd29, + ~cntA == 7'd28, + ~cntA == 7'd27, + ~cntA == 7'd26, + ~cntA == 7'd25, + ~cntA == 7'd24, + ~cntA == 7'd23, + ~cntA == 7'd22, + ~cntA == 7'd21, + ~cntA == 7'd20, + ~cntA == 7'd19, + ~cntA == 7'd18, + ~cntA == 7'd17, + ~cntA == 7'd16, + ~cntA == 7'd15, + ~cntA == 7'd14, + ~cntA == 7'd13, + ~cntA == 7'd12, + ~cntA == 7'd11, + ~cntA == 7'd10, + ~cntA == 7'd9, + ~cntA == 7'd8, + ~cntA == 7'd7, + ~cntA == 7'd6, + ~cntA == 7'd5, + ~cntA == 7'd4, + ~cntA == 7'd3, + ~cntA == 7'd2, + ~cntA == 7'd1, + ~cntA == 7'd0 + }; - // Should create decoder - wire stupidWayToWriteConstOne = 1'b0 + // Should create decoder + wire stupidWayToWriteConstOne = 1'b0 + (cntB == 7'd127) + (cntB == 7'd126) + (cntB == 7'd125) @@ -410,8 +410,8 @@ module t ( + (cntB == 7'd18) + (cntB <= 7'd17); - // Should not create decoder - wire [6:0] twiceCntC = + // Should not create decoder + wire [6:0] twiceCntC = cntC == 7'd127 ? (7'd127 * 7'd2) : cntC == 7'd126 ? (7'd126 * 7'd2) : cntC == 7'd125 ? (7'd125 * 7'd2) : @@ -541,9 +541,9 @@ module t ( cntC == 7'd1 ? (7'd1 * 7'd2) : 7'd0; - // Should create decoder - wire [127:0] cntD_OH = 128'h1 << cntD; - wire [6:0] cntD_sel = + // Should create decoder + wire [127:0] cntD_OH = 128'h1 << cntD; + wire [6:0] cntD_sel = (cntD_OH[127] ? 7'd127 : 0) | (cntD_OH[126] ? 7'd126 : 0) | (cntD_OH[125] ? 7'd125 : 0) | @@ -673,24 +673,24 @@ module t ( (cntD_OH[1] ? 7'd1 : 0) | (cntD_OH[0] ? 7'd0 : 0); - always @(posedge clk) begin - `check(cntAOneHot[cntA], 1'b1); - for (int i = 0; i < $bits(cntAOneHot); i = i + 1) begin - if (i == int'(cntA)) continue; - `check(cntAOneHot[i], 1'b0); - end + always @(posedge clk) begin + `check(cntAOneHot[cntA], 1'b1); + for (int i = 0; i < $bits(cntAOneHot); i = i + 1) begin + if (i == int'(cntA)) continue; + `check(cntAOneHot[i], 1'b0); + end - `check(notCntAOneHot[~cntA], 1'b1); - for (int i = 0; i < $bits(notCntAOneHot); i = i + 1) begin - if (i == {25'd0, ~cntA}) continue; - `check(notCntAOneHot[i], 1'b0); - end + `check(notCntAOneHot[~cntA], 1'b1); + for (int i = 0; i < $bits(notCntAOneHot); i = i + 1) begin + if (i == {25'd0, ~cntA}) continue; + `check(notCntAOneHot[i], 1'b0); + end - `check(stupidWayToWriteConstOne, 1'b1); + `check(stupidWayToWriteConstOne, 1'b1); - `check(twiceCntC, cntC * 7'd2); + `check(twiceCntC, cntC * 7'd2); - `check(cntD_sel, cntD); - end + `check(cntD_sel, cntD); + end endmodule diff --git a/test_regress/t/t_dfg_circular.v b/test_regress/t/t_dfg_circular.v index f77c7fa98..b99282ad9 100644 --- a/test_regress/t/t_dfg_circular.v +++ b/test_regress/t/t_dfg_circular.v @@ -10,35 +10,35 @@ module t ( input wire i, output wire o ); - wire a; - wire b; - wire c; - wire d; + wire a; + wire b; + wire c; + wire d; - assign c = i + 1'b1; - assign d = c + 1'b1; - assign a = b + d; - assign b = a + 1'b1; + assign c = i + 1'b1; + assign d = c + 1'b1; + assign a = b + d; + assign b = a + 1'b1; - wire p; - wire q; - wire r; - wire s; + wire p; + wire q; + wire r; + wire s; - assign p = i + 1'b1; - assign q = p + 1'b1; - assign r = s ^ q; - assign s = r + 1'b1; + assign p = i + 1'b1; + assign q = p + 1'b1; + assign r = s ^ q; + assign s = r + 1'b1; - wire x; - wire y; - wire z; - wire w; + wire x; + wire y; + wire z; + wire w; - assign x = y ^ i; - assign y = x; - assign z = w; - assign w = y & z; + assign x = y ^ i; + assign y = x; + assign z = w; + assign w = y & z; - assign o = b | x; + assign o = b | x; endmodule diff --git a/test_regress/t/t_dfg_inline_forced.v b/test_regress/t/t_dfg_inline_forced.v index 2de16d1b9..89975935a 100644 --- a/test_regress/t/t_dfg_inline_forced.v +++ b/test_regress/t/t_dfg_inline_forced.v @@ -4,21 +4,26 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module top(input wire clk); +module top ( + input wire clk +); - logic [1:0][31:0] i; - logic o; + logic [1:0][31:0] i; + logic o; - always @(posedge clk) begin - force i = 64'hFFFFFFFF_FFFFFFFF; - end + always @(posedge clk) begin + force i = 64'hFFFFFFFF_FFFFFFFF; + end - sub sub_i(.i(i), .o(o)); + sub sub_i ( + .i(i), + .o(o) + ); endmodule module sub ( - input logic [63:0] i, + input logic [63:0] i, output logic o ); - assign o = |i; + assign o = |i; endmodule diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.out b/test_regress/t/t_dfg_multidriver_dfg_bad.out index 92a73f8a3..b7ccc6082 100644 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.out +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.out @@ -1,120 +1,120 @@ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:45:18: Bit [1] of signal 'y' have multiple combinational drivers. This can cause performance degradation. +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:45:16: Bit [1] of signal 'y' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver - 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; - | ^ - t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver - 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; - | ^ + t/t_dfg_multidriver_dfg_bad.v:48:22: ... Location of offending driver + 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; + | ^ + t/t_dfg_multidriver_dfg_bad.v:48:22: ... Location of offending driver + 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; + | ^ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [3:1] of signal 'a' have multiple combinational drivers. This can cause performance degradation. +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:16: Bits [3:1] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver - 17 | assign a[3:0] = i[3:0]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:18:19: ... Location of offending driver - 18 | assign a[4:1] = ~i[4:1]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [3] of signal 'a' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver - 17 | assign a[3:0] = i[3:0]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:19:17: ... Location of offending driver - 19 | assign a[3] = ~i[3]; + t/t_dfg_multidriver_dfg_bad.v:17:17: ... Location of offending driver + 17 | assign a[3:0] = i[3:0]; | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [7:6] of signal 'a' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:20:19: ... Location of offending driver - 20 | assign a[8:5] = i[8:5]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:21:19: ... Location of offending driver - 21 | assign a[7:6] = ~i[7:6]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [9] of signal 'a' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:22:17: ... Location of offending driver - 22 | assign a[9] = i[9]; + t/t_dfg_multidriver_dfg_bad.v:18:17: ... Location of offending driver + 18 | assign a[4:1] = ~i[4:1]; | ^ - t/t_dfg_multidriver_dfg_bad.v:23:17: ... Location of offending driver - 23 | assign a[9] = ~i[9]; +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:16: Bit [3] of signal 'a' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:17:17: ... Location of offending driver + 17 | assign a[3:0] = i[3:0]; | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:26:18: Elements [3:0] of signal 'u' have multiple combinational drivers. This can cause performance degradation. + t/t_dfg_multidriver_dfg_bad.v:19:15: ... Location of offending driver + 19 | assign a[3] = ~i[3]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:16: Bits [7:6] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:27:14: ... Location of offending driver - 27 | assign u = j; - | ^ - t/t_dfg_multidriver_dfg_bad.v:28:14: ... Location of offending driver - 28 | assign u = k; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:30:18: Element [1] of signal 'v' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:31:14: ... Location of offending driver - 31 | assign v = j; - | ^ - t/t_dfg_multidriver_dfg_bad.v:32:13: ... Location of offending driver - 32 | assign v[1] = i; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:34:18: Element [0] of signal 'w' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:35:13: ... Location of offending driver - 35 | assign w[0] = i; - | ^ - t/t_dfg_multidriver_dfg_bad.v:36:14: ... Location of offending driver - 36 | assign w = j; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:38:18: Bits [3:2] of signal 'x[3]' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:39:17: ... Location of offending driver - 39 | assign x[3] = i; + t/t_dfg_multidriver_dfg_bad.v:20:17: ... Location of offending driver + 20 | assign a[8:5] = i[8:5]; | ^ - t/t_dfg_multidriver_dfg_bad.v:40:22: ... Location of offending driver - 40 | assign x[3][3:2] = ~i[1:0]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [2:1] of signal 'z' have multiple combinational drivers. This can cause performance degradation. - : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:53:14: ... Location of offending driver - 53 | z[2:0] = i[2:0]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:58:17: ... Location of offending driver - 58 | z[3:1] = i[3:1]; + t/t_dfg_multidriver_dfg_bad.v:21:17: ... Location of offending driver + 21 | assign a[7:6] = ~i[7:6]; | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [6:5] of signal 'z' have multiple combinational drivers. This can cause performance degradation. +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:16: Bit [9] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:57:14: ... Location of offending driver - 57 | z[6:4] = i[6:4]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver - 54 | z[7:5] = i[7:5]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bit [7] of signal 'z' have multiple combinational drivers. This can cause performance degradation. + t/t_dfg_multidriver_dfg_bad.v:22:15: ... Location of offending driver + 22 | assign a[9] = i[9]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:23:15: ... Location of offending driver + 23 | assign a[9] = ~i[9]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:26:16: Elements [3:0] of signal 'u' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' - t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver - 54 | z[7:5] = i[7:5]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:60:20: ... Location of offending driver - 60 | assign z[10:7] = i[10:7]; + t/t_dfg_multidriver_dfg_bad.v:27:12: ... Location of offending driver + 27 | assign u = j; + | ^ + t/t_dfg_multidriver_dfg_bad.v:28:12: ... Location of offending driver + 28 | assign u = k; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:30:16: Element [1] of signal 'v' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:31:12: ... Location of offending driver + 31 | assign v = j; + | ^ + t/t_dfg_multidriver_dfg_bad.v:32:11: ... Location of offending driver + 32 | assign v[1] = i; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:34:16: Element [0] of signal 'w' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:35:11: ... Location of offending driver + 35 | assign w[0] = i; + | ^ + t/t_dfg_multidriver_dfg_bad.v:36:12: ... Location of offending driver + 36 | assign w = j; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:38:16: Bits [3:2] of signal 'x[3]' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:39:15: ... Location of offending driver + 39 | assign x[3] = i; + | ^ + t/t_dfg_multidriver_dfg_bad.v:40:20: ... Location of offending driver + 40 | assign x[3][3:2] = ~i[1:0]; | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [5:2] of signal 't.sub_1.a' have multiple combinational drivers. This can cause performance degradation. - t/t_dfg_multidriver_dfg_bad.v:63:20: ... Location of offending driver - 63 | assign sub_1.a = i; - | ^ - t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver - 75 | assign a[5:2] = i[5:2]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [3:2] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. - t/t_dfg_multidriver_dfg_bad.v:67:25: ... Location of offending driver - 67 | assign sub_2.a[3:0] = i[3:0]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver - 75 | assign a[5:2] = i[5:2]; - | ^ -%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bit [5] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. - t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver - 75 | assign a[5:2] = i[5:2]; - | ^ - t/t_dfg_multidriver_dfg_bad.v:66:26: ... Location of offending driver - 66 | assign sub_2.a[10:5] = i[10:5]; - | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:16: Bits [2:1] of signal 'z' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:53:12: ... Location of offending driver + 53 | z[2:0] = i[2:0]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:58:15: ... Location of offending driver + 58 | z[3:1] = i[3:1]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:16: Bits [6:5] of signal 'z' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:57:12: ... Location of offending driver + 57 | z[6:4] = i[6:4]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:54:12: ... Location of offending driver + 54 | z[7:5] = i[7:5]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:16: Bit [7] of signal 'z' have multiple combinational drivers. This can cause performance degradation. + : ... note: In instance 't' + t/t_dfg_multidriver_dfg_bad.v:54:12: ... Location of offending driver + 54 | z[7:5] = i[7:5]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:60:18: ... Location of offending driver + 60 | assign z[10:7] = i[10:7]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:76:16: Bits [5:2] of signal 't.sub_1.a' have multiple combinational drivers. This can cause performance degradation. + t/t_dfg_multidriver_dfg_bad.v:63:18: ... Location of offending driver + 63 | assign sub_1.a = i; + | ^ + t/t_dfg_multidriver_dfg_bad.v:77:17: ... Location of offending driver + 77 | assign a[5:2] = i[5:2]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:76:16: Bits [3:2] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. + t/t_dfg_multidriver_dfg_bad.v:67:23: ... Location of offending driver + 67 | assign sub_2.a[3:0] = i[3:0]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:77:17: ... Location of offending driver + 77 | assign a[5:2] = i[5:2]; + | ^ +%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:76:16: Bit [5] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. + t/t_dfg_multidriver_dfg_bad.v:77:17: ... Location of offending driver + 77 | assign a[5:2] = i[5:2]; + | ^ + t/t_dfg_multidriver_dfg_bad.v:66:24: ... Location of offending driver + 66 | assign sub_2.a[10:5] = i[10:5]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.v b/test_regress/t/t_dfg_multidriver_dfg_bad.v index 0c629eae7..39ceec7e9 100644 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.v +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.v @@ -6,71 +6,73 @@ `default_nettype none -module t( +module t ( input wire [10:0] i, - input wire [10:0] j [4], - input wire [10:0] k [4], + input wire [10:0] j[4], + input wire [10:0] k[4], output wire [10:0] o ); - logic [10:0] a; - assign a[3:0] = i[3:0]; - assign a[4:1] = ~i[4:1]; - assign a[3] = ~i[3]; - assign a[8:5] = i[8:5]; - assign a[7:6] = ~i[7:6]; - assign a[9] = i[9]; - assign a[9] = ~i[9]; - assign a[10] = i[10]; + logic [10:0] a; + assign a[3:0] = i[3:0]; + assign a[4:1] = ~i[4:1]; + assign a[3] = ~i[3]; + assign a[8:5] = i[8:5]; + assign a[7:6] = ~i[7:6]; + assign a[9] = i[9]; + assign a[9] = ~i[9]; + assign a[10] = i[10]; - logic [10:0] u [4]; - assign u = j; - assign u = k; + logic [10:0] u[4]; + assign u = j; + assign u = k; - logic [10:0] v [4]; - assign v = j; - assign v[1] = i; + logic [10:0] v[4]; + assign v = j; + assign v[1] = i; - logic [10:0] w [4]; - assign w[0] = i; - assign w = j; + logic [10:0] w[4]; + assign w[0] = i; + assign w = j; - logic [10:0] x [4]; - assign x[3] = i; - assign x[3][3:2] = ~i[1:0]; - // No warning for w[2]! - assign x[2][3:2] = ~i[1:0]; - assign x[2][1:0] = ~i[1:0]; + logic [10:0] x[4]; + assign x[3] = i; + assign x[3][3:2] = ~i[1:0]; + // No warning for w[2]! + assign x[2][3:2] = ~i[1:0]; + assign x[2][1:0] = ~i[1:0]; - logic [10:0] y; - always_comb begin - y = i; - {y[1:0], y[2:1]} = i[3:0] + 4'd5; - end + logic [10:0] y; + always_comb begin + y = i; + {y[1:0], y[2:1]} = i[3:0] + 4'd5; + end - logic [10:0] z; - always_comb begin - z[2:0] = i[2:0]; - z[7:5] = i[7:5]; - end - always_comb begin - z[6:4] = i[6:4]; - z[3:1] = i[3:1]; - end - assign z[10:7] = i[10:7]; + logic [10:0] z; + always_comb begin + z[2:0] = i[2:0]; + z[7:5] = i[7:5]; + end + always_comb begin + z[6:4] = i[6:4]; + z[3:1] = i[3:1]; + end + assign z[10:7] = i[10:7]; - sub sub_1(i); - assign sub_1.a = i; + sub sub_1 (i); + assign sub_1.a = i; - sub sub_2(i); - assign sub_2.a[10:5] = i[10:5]; - assign sub_2.a[3:0] = i[3:0]; + sub sub_2 (i); + assign sub_2.a[10:5] = i[10:5]; + assign sub_2.a[3:0] = i[3:0]; - assign o = a ^ u[3] ^ v[3] ^ w[3] ^ x[3] ^ y ^ z ^ sub_1.a ^ sub_2.a; + assign o = a ^ u[3] ^ v[3] ^ w[3] ^ x[3] ^ y ^ z ^ sub_1.a ^ sub_2.a; endmodule -module sub(input wire [10:0] i); - logic [10:0] a; - assign a[5:2] = i[5:2]; +module sub ( + input wire [10:0] i +); + logic [10:0] a; + assign a[5:2] = i[5:2]; endmodule diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.v b/test_regress/t/t_dfg_multidriver_non_dfg.v index d3112693f..ce5adbc53 100644 --- a/test_regress/t/t_dfg_multidriver_non_dfg.v +++ b/test_regress/t/t_dfg_multidriver_non_dfg.v @@ -6,17 +6,17 @@ `default_nettype none -module t( - input wire i, +module t ( + input wire i, output wire o ); - logic a; - logic b; - initial begin - a = 1'd0; - b = 1'd0; - end - assign a = ~i; - assign b = a; - assign o = b; + logic a; + logic b; + initial begin + a = 1'd0; + b = 1'd0; + end + assign a = ~i; + assign b = a; + assign o = b; endmodule diff --git a/test_regress/t/t_dfg_peephole.v b/test_regress/t/t_dfg_peephole.v index 0b182343b..026112bf4 100644 --- a/test_regress/t/t_dfg_peephole.v +++ b/test_regress/t/t_dfg_peephole.v @@ -8,277 +8,277 @@ module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py - rand_a, rand_b, srand_a, srand_b, arand_a, arand_b - ); + rand_a, rand_b, srand_a, srand_b, arand_a, arand_b + ); `include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py - input rand_a; - input rand_b; - input srand_a; - input srand_b; - input arand_a; - input arand_b; - wire logic [63:0] rand_a; - wire logic [63:0] rand_b; - wire logic signed [63:0] srand_a; - wire logic signed [63:0] srand_b; - // verilator lint_off ASCRANGE - wire logic [0:63] arand_a; - wire logic [0:63] arand_b; - // verilator lint_on ASCRANGE + input rand_a; + input rand_b; + input srand_a; + input srand_b; + input arand_a; + input arand_b; + wire logic [63:0] rand_a; + wire logic [63:0] rand_b; + wire logic signed [63:0] srand_a; + wire logic signed [63:0] srand_b; + // verilator lint_off ASCRANGE + wire logic [0:63] arand_a; + wire logic [0:63] arand_b; + // verilator lint_on ASCRANGE - wire logic randbit_a = rand_a[0]; - wire logic [127:0] rand_ba = {rand_b, rand_a}; - wire logic [127:0] rand_aa = {2{rand_a}}; - wire logic [63:0] const_a; - wire logic [63:0] const_b; - wire logic signed [63:0] sconst_a; - wire logic signed [63:0] sconst_b; - logic [63:0] array [3:0]; - logic [63:0] unitArrayWhole [0:0]; - logic [63:0] unitArrayParts [0:0]; - assign array[0] = (rand_a << 32) | (rand_a >> 32); - assign array[1] = (rand_a << 16) | (rand_a >> 48); - assign array[2][3:0] = rand_a[3:0]; - always @(rand_b) begin // Intentional non-combinational partial driver - array[2][7:4] = rand_a[7:4]; - end - assign unitArrayWhole[0] = rand_a; - assign unitArrayParts[0][1] = rand_a[1]; - assign unitArrayParts[0][9] = rand_a[9]; + wire logic randbit_a = rand_a[0]; + wire logic [127:0] rand_ba = {rand_b, rand_a}; + wire logic [127:0] rand_aa = {2{rand_a}}; + wire logic [63:0] const_a; + wire logic [63:0] const_b; + wire logic signed [63:0] sconst_a; + wire logic signed [63:0] sconst_b; + logic [63:0] array [3:0]; + logic [63:0] unitArrayWhole [0:0]; + logic [63:0] unitArrayParts [0:0]; + assign array[0] = (rand_a << 32) | (rand_a >> 32); + assign array[1] = (rand_a << 16) | (rand_a >> 48); + assign array[2][3:0] = rand_a[3:0]; + always @(rand_b) begin // Intentional non-combinational partial driver + array[2][7:4] = rand_a[7:4]; + end + assign unitArrayWhole[0] = rand_a; + assign unitArrayParts[0][1] = rand_a[1]; + assign unitArrayParts[0][9] = rand_a[9]; - `signal(FOLD_UNARY_LogNot, !const_a[0]); - `signal(FOLD_UNARY_Negate, -const_a); - `signal(FOLD_UNARY_Not, ~const_a); - `signal(FOLD_UNARY_RedAnd, &const_a); - `signal(FOLD_UNARY_RedOr, |const_a); - `signal(FOLD_UNARY_RedXor, ^const_a); - // verilator lint_off WIDTH - wire logic [79:0] tmp_FOLD_UNARY_Extend = const_a; - wire logic signed [79:0] tmp_FOLD_UNARY_ExtendS = sconst_a; - //verilator lint_on WIDTH - `signal(FOLD_UNARY_Extend, tmp_FOLD_UNARY_Extend); - `signal(FOLD_UNARY_ExtendS, tmp_FOLD_UNARY_ExtendS); + `signal(FOLD_UNARY_LogNot, !const_a[0]); + `signal(FOLD_UNARY_Negate, -const_a); + `signal(FOLD_UNARY_Not, ~const_a); + `signal(FOLD_UNARY_RedAnd, &const_a); + `signal(FOLD_UNARY_RedOr, |const_a); + `signal(FOLD_UNARY_RedXor, ^const_a); + // verilator lint_off WIDTH + wire logic [79:0] tmp_FOLD_UNARY_Extend = const_a; + wire logic signed [79:0] tmp_FOLD_UNARY_ExtendS = sconst_a; + //verilator lint_on WIDTH + `signal(FOLD_UNARY_Extend, tmp_FOLD_UNARY_Extend); + `signal(FOLD_UNARY_ExtendS, tmp_FOLD_UNARY_ExtendS); - `signal(FOLD_BINARY_Add, const_a + const_b); - `signal(FOLD_BINARY_And, const_a & const_b); - `signal(FOLD_BINARY_Concat, {const_a, const_b}); - `signal(FOLD_BINARY_Div, const_a / 64'd3); - `signal(FOLD_BINARY_DivS, sconst_a / 64'sd3); - `signal(FOLD_BINARY_Eq, const_a == const_b); - `signal(FOLD_BINARY_Gt, const_a > const_b); - `signal(FOLD_BINARY_GtS, sconst_a > sconst_b); - `signal(FOLD_BINARY_Gte, const_a >= const_b); - `signal(FOLD_BINARY_GteS, sconst_a >= sconst_b); - `signal(FOLD_BINARY_LogAnd, const_a[0] && const_b[0]); - `signal(FOLD_BINARY_LogEq, const_a[0] <-> const_b[0]); - `signal(FOLD_BINARY_LogIf, const_a[0] -> const_b[0]); - `signal(FOLD_BINARY_LogOr, const_a[0] || const_b[0]); - `signal(FOLD_BINARY_Lt, const_a < const_b); - `signal(FOLD_BINARY_Lt2, const_a < const_a); - `signal(FOLD_BINARY_LtS, sconst_a < sconst_b); - `signal(FOLD_BINARY_LtS2, sconst_a < sconst_a); - `signal(FOLD_BINARY_Lte, const_a <= const_b); - `signal(FOLD_BINARY_Lte2, const_a <= const_a); - `signal(FOLD_BINARY_LteS, sconst_a <= sconst_b); - `signal(FOLD_BINARY_LteS2, sconst_a <= sconst_a); - `signal(FOLD_BINARY_ModDiv, const_a % 64'd3); - `signal(FOLD_BINARY_ModDivS, sconst_a % 64'sd3); - `signal(FOLD_BINARY_Mul, const_a * 64'd3); - `signal(FOLD_BINARY_MulS, sconst_a * 64'sd3); - `signal(FOLD_BINARY_Neq, const_a != const_b); - `signal(FOLD_BINARY_Or, const_a | const_b); - `signal(FOLD_BINARY_Pow, const_a ** 64'd2); - `signal(FOLD_BINARY_PowSS, sconst_a ** 64'sd2); - `signal(FOLD_BINARY_PowSU, sconst_a ** 64'd2); - `signal(FOLD_BINARY_PowUS, const_a ** 64'sd2); - `signal(FOLD_BINARY_Replicate, {2{const_a}}); - `signal(FOLD_BINARY_ShiftL, const_a << 2); - `signal(FOLD_BINARY_ShiftR, const_a >> 2); - `signal(FOLD_BINARY_ShiftRS, sconst_a >>> 2); - `signal(FOLD_BINARY_Sub, const_a - const_b); - `signal(FOLD_BINARY_Xor, const_a ^ const_b); + `signal(FOLD_BINARY_Add, const_a + const_b); + `signal(FOLD_BINARY_And, const_a & const_b); + `signal(FOLD_BINARY_Concat, {const_a, const_b}); + `signal(FOLD_BINARY_Div, const_a / 64'd3); + `signal(FOLD_BINARY_DivS, sconst_a / 64'sd3); + `signal(FOLD_BINARY_Eq, const_a == const_b); + `signal(FOLD_BINARY_Gt, const_a > const_b); + `signal(FOLD_BINARY_GtS, sconst_a > sconst_b); + `signal(FOLD_BINARY_Gte, const_a >= const_b); + `signal(FOLD_BINARY_GteS, sconst_a >= sconst_b); + `signal(FOLD_BINARY_LogAnd, const_a[0] && const_b[0]); + `signal(FOLD_BINARY_LogEq, const_a[0] <-> const_b[0]); + `signal(FOLD_BINARY_LogIf, const_a[0] -> const_b[0]); + `signal(FOLD_BINARY_LogOr, const_a[0] || const_b[0]); + `signal(FOLD_BINARY_Lt, const_a < const_b); + `signal(FOLD_BINARY_Lt2, const_a < const_a); + `signal(FOLD_BINARY_LtS, sconst_a < sconst_b); + `signal(FOLD_BINARY_LtS2, sconst_a < sconst_a); + `signal(FOLD_BINARY_Lte, const_a <= const_b); + `signal(FOLD_BINARY_Lte2, const_a <= const_a); + `signal(FOLD_BINARY_LteS, sconst_a <= sconst_b); + `signal(FOLD_BINARY_LteS2, sconst_a <= sconst_a); + `signal(FOLD_BINARY_ModDiv, const_a % 64'd3); + `signal(FOLD_BINARY_ModDivS, sconst_a % 64'sd3); + `signal(FOLD_BINARY_Mul, const_a * 64'd3); + `signal(FOLD_BINARY_MulS, sconst_a * 64'sd3); + `signal(FOLD_BINARY_Neq, const_a != const_b); + `signal(FOLD_BINARY_Or, const_a | const_b); + `signal(FOLD_BINARY_Pow, const_a ** 64'd2); + `signal(FOLD_BINARY_PowSS, sconst_a ** 64'sd2); + `signal(FOLD_BINARY_PowSU, sconst_a ** 64'd2); + `signal(FOLD_BINARY_PowUS, const_a ** 64'sd2); + `signal(FOLD_BINARY_Replicate, {2{const_a}}); + `signal(FOLD_BINARY_ShiftL, const_a << 2); + `signal(FOLD_BINARY_ShiftR, const_a >> 2); + `signal(FOLD_BINARY_ShiftRS, sconst_a >>> 2); + `signal(FOLD_BINARY_Sub, const_a - const_b); + `signal(FOLD_BINARY_Xor, const_a ^ const_b); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_And, (const_a & (const_b & rand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Or, (const_a | (const_b | rand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Xor, (const_a ^ (const_b ^ rand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Add, (const_a + (const_b + rand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Mul, (const_a * (const_b * rand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_MulS, (sconst_a * (sconst_b * srand_a))); - `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Concat, {const_a, {const_b, rand_a}}); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_And, (const_a & (const_b & rand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Or, (const_a | (const_b | rand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Xor, (const_a ^ (const_b ^ rand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Add, (const_a + (const_b + rand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Mul, (const_a * (const_b * rand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_MulS, (sconst_a * (sconst_b * srand_a))); + `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Concat, {const_a, {const_b, rand_a}}); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_And, ((rand_a & const_b) & const_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Or, ((rand_a | const_b) | const_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Xor, ((rand_a ^ const_b) ^ const_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Add, ((rand_a + const_b) + const_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Mul, ((rand_a * const_b) * const_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_MulS, ((srand_a * sconst_b) * sconst_a)); - `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Concat, {{rand_a, const_b}, const_a}); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_And, ((rand_a & const_b) & const_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Or, ((rand_a | const_b) | const_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Xor, ((rand_a ^ const_b) ^ const_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Add, ((rand_a + const_b) + const_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Mul, ((rand_a * const_b) * const_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_MulS, ((srand_a * sconst_b) * sconst_a)); + `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Concat, {{rand_a, const_b}, const_a}); - `signal(FOLD_SEL, const_a[3:1]); + `signal(FOLD_SEL, const_a[3:1]); - `signal(SWAP_CONST_IN_COMMUTATIVE_BINARY, rand_a + const_a); - `signal(SWAP_NOT_IN_COMMUTATIVE_BINARY, rand_a + ~rand_a); - `signal(SWAP_VAR_IN_COMMUTATIVE_BINARY, rand_b + rand_a); - `signal(PUSH_BITWISE_OP_THROUGH_CONCAT, 32'h12345678 ^ {8'h0, rand_a[23:0]}); - `signal(PUSH_BITWISE_OP_THROUGH_CONCAT_2, 32'h12345678 ^ {rand_b[7:0], rand_a[23:0]}); - `signal(PUSH_COMPARE_OP_THROUGH_CONCAT, 4'b1011 == {2'b10, rand_a[1:0]}); - `signal(PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH, |(rand_a[32] ? rand_a[3:0] : 4'h0)); - `signal(REPLACE_REDUCTION_OF_CONST_AND, &const_a); - `signal(REPLACE_REDUCTION_OF_CONST_OR, |const_a); - `signal(REPLACE_REDUCTION_OF_CONST_XOR, ^const_a); - `signal(REPLACE_EXTEND, 4'(rand_a[0])); - `signal(PUSH_NOT_THROUGH_COND, ~(rand_a[0] ? rand_a[4:0] : 5'hb)); - `signal(REMOVE_NOT_NOT, ~~rand_a); - `signal(REPLACE_NOT_NEQ, ~(rand_a != rand_b)); - `signal(REPLACE_NOT_EQ, ~(srand_a == srand_b)); - `signal(REPLACE_NOT_OF_CONST, ~4'd0); - `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABAC, ((rand_a >> 10) | (rand_b >> 10)) & ((rand_a >> 10) | (srand_b >> 10))); - `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABCA, ((rand_a >> 11) | (rand_b >> 11)) & ((srand_b >> 11) | (rand_a >> 11))); - `signal(REPLACE_DISTRIBUTIVE_AND_OR_BAAC, ((rand_b >> 12) | (rand_a >> 12)) & ((rand_a >> 12) | (srand_b >> 12))); - `signal(REPLACE_DISTRIBUTIVE_AND_OR_BACA, ((rand_b >> 13) | (rand_a >> 13)) & ((srand_b >> 13) | (rand_a >> 13))); - `signal(REPLACE_AND_OF_NOT_AND_NOT, ~rand_a[1] & ~rand_b[1]); - `signal(REPLACE_AND_OF_NOT_AND_NEQ, ~rand_a[2] & (rand_b != 64'd2)); - `signal(REPLACE_AND_OF_CONST_AND_CONST, const_a & const_b); - `signal(REPLACE_AND_WITH_ZERO, 64'd0 & rand_a); - `signal(REMOVE_AND_WITH_ONES, -64'd1 & rand_a); - `signal(REMOVE_AND_WITH_SELF, ~rand_a & ~rand_a); - `signal(REPLACE_CONTRADICTORY_AND, rand_a & ~rand_a); - `signal(REPLACE_CONTRADICTORY_AND_3, ~(rand_a + 1) & ((rand_a + 1) & rand_b)); - `signal(REPLACE_OR_DISTRIBUTIVE, (rand_a & rand_b) | (rand_a & srand_b)); - `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABAC, ((rand_a >> 14) & (rand_b >> 14)) | ((rand_a >> 14) & (srand_b >> 14))); - `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABCA, ((rand_a >> 15) & (rand_b >> 15)) | ((srand_b >> 15) & (rand_a >> 15))); - `signal(REPLACE_DISTRIBUTIVE_OR_AND_BAAC, ((rand_b >> 16) & (rand_a >> 16)) | ((rand_a >> 16) & (srand_b >> 16))); - `signal(REPLACE_DISTRIBUTIVE_OR_AND_BACA, ((rand_b >> 17) & (rand_a >> 17)) | ((srand_b >> 17) & (rand_a >> 17))); - `signal(REPLACE_OR_OF_NOT_AND_NOT, ~rand_a[3] | ~rand_b[3]); - `signal(REPLACE_OR_OF_NOT_AND_NEQ, ~rand_a[4] | (rand_b != 64'd3)); - `signal(REPLACE_OR_OF_CONCAT_ZERO_LHS_AND_CONCAT_RHS_ZERO, {2'd0, rand_a[1:0]} | {rand_b[1:0], 2'd0}); - `signal(REPLACE_OR_OF_CONCAT_LHS_ZERO_AND_CONCAT_ZERO_RHS, {rand_a[1:0], 2'd0} | {2'd0, rand_b[1:0]}); - `signal(REPLACE_OR_OF_CONST_AND_CONST, const_a | const_b); - `signal(REPLACE_OR_WITH_ONES, -64'd1 | rand_a); - `signal(REMOVE_OR_WITH_SELF, ~rand_a | ~rand_a); - `signal(REMOVE_OR_WITH_ZERO, 64'd0 | rand_a); - `signal(REPLACE_TAUTOLOGICAL_OR, rand_a | ~rand_a); - `signal(REPLACE_TAUTOLOGICAL_OR_3, ~(rand_a + 1) | ((rand_a + 1) | rand_b)); - `signal(REMOVE_SUB_ZERO, rand_a - 64'd0); - `signal(REPLACE_SUB_WITH_NOT, rand_a[0] - 1'b1); - `signal(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT, rand_a << {2'b0, rand_a[2:0]}); - `signal(REPLACE_EQ_OF_CONST_AND_CONST, 4'd0 == 4'd1); - `signal(REMOVE_FULL_WIDTH_SEL, rand_a[63:0]); - `signal(REMOVE_SEL_FROM_RHS_OF_CONCAT, rand_ba[63:0]); - `signal(REMOVE_SEL_FROM_LHS_OF_CONCAT, rand_ba[127:64]); - `signal(PUSH_SEL_THROUGH_CONCAT, rand_ba[120:0]); - `signal(PUSH_SEL_THROUGH_REPLICATE, rand_aa[0]); - `signal(REPLACE_SEL_FROM_CONST, const_a[2]); - `signal(REPLACE_CONCAT_OF_CONSTS, {const_a, const_b}); - `signal(REPLACE_CONCAT_ZERO_AND_SEL_TOP_WITH_SHIFTR, {62'd0, rand_a[63:62]}); - `signal(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL, {rand_a[1:0], 62'd0}); - `signal(PUSH_CONCAT_THROUGH_NOTS, {~(rand_a+64'd101), ~(rand_b+64'd101)} ); - `signal(REMOVE_CONCAT_OF_ADJOINING_SELS, {rand_a[10:3], rand_a[2:1]}); - `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS_CAT, {rand_a[2:1], rand_b}); - `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS_CAT, {rand_b, rand_a[10:3]}); - `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], {rand_a[2:1], rand_b}}); - `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {{rand_b, rand_a[10:3]}, rand_a[2:1]}); - `signal(REMOVE_COND_WITH_FALSE_CONDITION, 1'd0 ? rand_a : rand_b); - `signal(REMOVE_COND_WITH_TRUE_CONDITION, 1'd1 ? rand_a : rand_b); - `signal(REMOVE_COND_WITH_BRANCHES_SAME, rand_a[0] ? ~rand_b : ~rand_b); - `signal(SWAP_COND_WITH_NOT_CONDITION, (~rand_a[0] & 1'd1) ? rand_a : rand_b); - `signal(SWAP_COND_WITH_NEQ_CONDITION, rand_b != rand_a ? rand_a : rand_b); - `signal(PULL_NOTS_THROUGH_COND, rand_a[0] ? ~rand_a[4:0] : ~rand_b[4:0]); - `signal(REPLACE_COND_OR_THEN_COND_LHS, (rand_a[0] | rand_b[0] ? (rand_a[0] ? rand_a : rand_b) : srand_a)); - `signal(REPLACE_COND_OR_THEN_COND_RHS, (rand_a[0] | rand_b[0] ? (rand_b[0] ? rand_a : rand_b) : srand_a)); - `signal(REPLACE_COND_WITH_THEN_BRANCH_COND, rand_a[0] ? rand_a[0] : rand_a[1]); - `signal(REPLACE_COND_WITH_THEN_BRANCH_ZERO, rand_a[0] ? 1'd0 : rand_a[1]); - `signal(REPLACE_COND_WITH_THEN_BRANCH_ONES, rand_a[0] ? 1'd1 : rand_a[1]); - `signal(REPLACE_COND_WITH_ELSE_BRANCH_ZERO, rand_a[0] ? rand_a[1] : 1'd0); - `signal(REPLACE_COND_WITH_ELSE_BRANCH_ONES, rand_a[0] ? rand_a[1] : 1'd1); - `signal(INLINE_ARRAYSEL_SPLICE, array[0]); - `signal(NO_INLINE_ARRAYSEL_SPLICE_PARTIAL, array[2]); - `signal(INLINE_ARRAYSEL_UNIT, unitArrayWhole[0]); - `signal(NO_INLINE_ARRAYSEL_UNIT_PARTIAL, unitArrayParts[0]); - `signal(PUSH_BITWISE_THROUGH_REDUCTION_AND, (&(rand_a + 64'd105)) & (&(rand_b + 64'd108))); - `signal(PUSH_BITWISE_THROUGH_REDUCTION_OR, (|(rand_a + 64'd106)) | (|(rand_b + 64'd109))); - `signal(PUSH_BITWISE_THROUGH_REDUCTION_XOR, (^(rand_a + 64'd107)) ^ (^(rand_b + 64'd110))); - `signal(PUSH_REDUCTION_THROUGH_CONCAT_AND, &{1'd1, rand_b}); - `signal(PUSH_REDUCTION_THROUGH_CONCAT_OR, |{1'd1, rand_b}); - `signal(PUSH_REDUCTION_THROUGH_CONCAT_XOR, ^{1'd1, rand_b}); - `signal(REMOVE_WIDTH_ONE_REDUCTION_AND, &rand_a[0]); - `signal(REMOVE_WIDTH_ONE_REDUCTION_OR, |rand_a[0]); - `signal(REMOVE_WIDTH_ONE_REDUCTION_XOR, ^rand_a[0]); - `signal(REMOVE_XOR_WITH_ZERO, 64'd0 ^ rand_a); - `signal(REPLACE_XOR_WITH_SELF, ~rand_a ^ ~rand_a); - `signal(REPLACE_XOR_WITH_ONES, -64'd1 ^ rand_a); - `signal(REPLACE_COND_DEC, randbit_a ? rand_b - 64'b1 : rand_b); - `signal(REPLACE_COND_INC, randbit_a ? rand_b + 64'b1 : rand_b); - `signal(NO_REPLACE_COND_DEC, randbit_a ? rand_b - 64'hf000000000000000 : rand_b); - `signal(NO_REPLACE_COND_INC, randbit_a ? rand_b + 64'hf000000000000000 : rand_b); - `signal(REPLACE_LOGAND_WITH_AND, rand_a[0] && rand_a[1]); - `signal(REPLACE_LOGOR_WITH_OR, rand_a[0] || rand_a[1]); - `signal(RIGHT_LEANING_ASSOC, (((rand_a + rand_b) + rand_a) + rand_b)); - `signal(RIGHT_LEANING_CONCET, {{{rand_a, rand_b}, rand_a}, rand_b}); + `signal(SWAP_CONST_IN_COMMUTATIVE_BINARY, rand_a + const_a); + `signal(SWAP_NOT_IN_COMMUTATIVE_BINARY, rand_a + ~rand_a); + `signal(SWAP_VAR_IN_COMMUTATIVE_BINARY, rand_b + rand_a); + `signal(PUSH_BITWISE_OP_THROUGH_CONCAT, 32'h12345678 ^ {8'h0, rand_a[23:0]}); + `signal(PUSH_BITWISE_OP_THROUGH_CONCAT_2, 32'h12345678 ^ {rand_b[7:0], rand_a[23:0]}); + `signal(PUSH_COMPARE_OP_THROUGH_CONCAT, 4'b1011 == {2'b10, rand_a[1:0]}); + `signal(PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH, |(rand_a[32] ? rand_a[3:0] : 4'h0)); + `signal(REPLACE_REDUCTION_OF_CONST_AND, &const_a); + `signal(REPLACE_REDUCTION_OF_CONST_OR, |const_a); + `signal(REPLACE_REDUCTION_OF_CONST_XOR, ^const_a); + `signal(REPLACE_EXTEND, 4'(rand_a[0])); + `signal(PUSH_NOT_THROUGH_COND, ~(rand_a[0] ? rand_a[4:0] : 5'hb)); + `signal(REMOVE_NOT_NOT, ~~rand_a); + `signal(REPLACE_NOT_NEQ, ~(rand_a != rand_b)); + `signal(REPLACE_NOT_EQ, ~(srand_a == srand_b)); + `signal(REPLACE_NOT_OF_CONST, ~4'd0); + `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABAC, ((rand_a >> 10) | (rand_b >> 10)) & ((rand_a >> 10) | (srand_b >> 10))); + `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABCA, ((rand_a >> 11) | (rand_b >> 11)) & ((srand_b >> 11) | (rand_a >> 11))); + `signal(REPLACE_DISTRIBUTIVE_AND_OR_BAAC, ((rand_b >> 12) | (rand_a >> 12)) & ((rand_a >> 12) | (srand_b >> 12))); + `signal(REPLACE_DISTRIBUTIVE_AND_OR_BACA, ((rand_b >> 13) | (rand_a >> 13)) & ((srand_b >> 13) | (rand_a >> 13))); + `signal(REPLACE_AND_OF_NOT_AND_NOT, ~rand_a[1] & ~rand_b[1]); + `signal(REPLACE_AND_OF_NOT_AND_NEQ, ~rand_a[2] & (rand_b != 64'd2)); + `signal(REPLACE_AND_OF_CONST_AND_CONST, const_a & const_b); + `signal(REPLACE_AND_WITH_ZERO, 64'd0 & rand_a); + `signal(REMOVE_AND_WITH_ONES, -64'd1 & rand_a); + `signal(REMOVE_AND_WITH_SELF, ~rand_a & ~rand_a); + `signal(REPLACE_CONTRADICTORY_AND, rand_a & ~rand_a); + `signal(REPLACE_CONTRADICTORY_AND_3, ~(rand_a + 1) & ((rand_a + 1) & rand_b)); + `signal(REPLACE_OR_DISTRIBUTIVE, (rand_a & rand_b) | (rand_a & srand_b)); + `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABAC, ((rand_a >> 14) & (rand_b >> 14)) | ((rand_a >> 14) & (srand_b >> 14))); + `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABCA, ((rand_a >> 15) & (rand_b >> 15)) | ((srand_b >> 15) & (rand_a >> 15))); + `signal(REPLACE_DISTRIBUTIVE_OR_AND_BAAC, ((rand_b >> 16) & (rand_a >> 16)) | ((rand_a >> 16) & (srand_b >> 16))); + `signal(REPLACE_DISTRIBUTIVE_OR_AND_BACA, ((rand_b >> 17) & (rand_a >> 17)) | ((srand_b >> 17) & (rand_a >> 17))); + `signal(REPLACE_OR_OF_NOT_AND_NOT, ~rand_a[3] | ~rand_b[3]); + `signal(REPLACE_OR_OF_NOT_AND_NEQ, ~rand_a[4] | (rand_b != 64'd3)); + `signal(REPLACE_OR_OF_CONCAT_ZERO_LHS_AND_CONCAT_RHS_ZERO, {2'd0, rand_a[1:0]} | {rand_b[1:0], 2'd0}); + `signal(REPLACE_OR_OF_CONCAT_LHS_ZERO_AND_CONCAT_ZERO_RHS, {rand_a[1:0], 2'd0} | {2'd0, rand_b[1:0]}); + `signal(REPLACE_OR_OF_CONST_AND_CONST, const_a | const_b); + `signal(REPLACE_OR_WITH_ONES, -64'd1 | rand_a); + `signal(REMOVE_OR_WITH_SELF, ~rand_a | ~rand_a); + `signal(REMOVE_OR_WITH_ZERO, 64'd0 | rand_a); + `signal(REPLACE_TAUTOLOGICAL_OR, rand_a | ~rand_a); + `signal(REPLACE_TAUTOLOGICAL_OR_3, ~(rand_a + 1) | ((rand_a + 1) | rand_b)); + `signal(REMOVE_SUB_ZERO, rand_a - 64'd0); + `signal(REPLACE_SUB_WITH_NOT, rand_a[0] - 1'b1); + `signal(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT, rand_a << {2'b0, rand_a[2:0]}); + `signal(REPLACE_EQ_OF_CONST_AND_CONST, 4'd0 == 4'd1); + `signal(REMOVE_FULL_WIDTH_SEL, rand_a[63:0]); + `signal(REMOVE_SEL_FROM_RHS_OF_CONCAT, rand_ba[63:0]); + `signal(REMOVE_SEL_FROM_LHS_OF_CONCAT, rand_ba[127:64]); + `signal(PUSH_SEL_THROUGH_CONCAT, rand_ba[120:0]); + `signal(PUSH_SEL_THROUGH_REPLICATE, rand_aa[0]); + `signal(REPLACE_SEL_FROM_CONST, const_a[2]); + `signal(REPLACE_CONCAT_OF_CONSTS, {const_a, const_b}); + `signal(REPLACE_CONCAT_ZERO_AND_SEL_TOP_WITH_SHIFTR, {62'd0, rand_a[63:62]}); + `signal(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL, {rand_a[1:0], 62'd0}); + `signal(PUSH_CONCAT_THROUGH_NOTS, {~(rand_a+64'd101), ~(rand_b+64'd101)} ); + `signal(REMOVE_CONCAT_OF_ADJOINING_SELS, {rand_a[10:3], rand_a[2:1]}); + `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS_CAT, {rand_a[2:1], rand_b}); + `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS_CAT, {rand_b, rand_a[10:3]}); + `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], {rand_a[2:1], rand_b}}); + `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {{rand_b, rand_a[10:3]}, rand_a[2:1]}); + `signal(REMOVE_COND_WITH_FALSE_CONDITION, 1'd0 ? rand_a : rand_b); + `signal(REMOVE_COND_WITH_TRUE_CONDITION, 1'd1 ? rand_a : rand_b); + `signal(REMOVE_COND_WITH_BRANCHES_SAME, rand_a[0] ? ~rand_b : ~rand_b); + `signal(SWAP_COND_WITH_NOT_CONDITION, (~rand_a[0] & 1'd1) ? rand_a : rand_b); + `signal(SWAP_COND_WITH_NEQ_CONDITION, rand_b != rand_a ? rand_a : rand_b); + `signal(PULL_NOTS_THROUGH_COND, rand_a[0] ? ~rand_a[4:0] : ~rand_b[4:0]); + `signal(REPLACE_COND_OR_THEN_COND_LHS, (rand_a[0] | rand_b[0] ? (rand_a[0] ? rand_a : rand_b) : srand_a)); + `signal(REPLACE_COND_OR_THEN_COND_RHS, (rand_a[0] | rand_b[0] ? (rand_b[0] ? rand_a : rand_b) : srand_a)); + `signal(REPLACE_COND_WITH_THEN_BRANCH_COND, rand_a[0] ? rand_a[0] : rand_a[1]); + `signal(REPLACE_COND_WITH_THEN_BRANCH_ZERO, rand_a[0] ? 1'd0 : rand_a[1]); + `signal(REPLACE_COND_WITH_THEN_BRANCH_ONES, rand_a[0] ? 1'd1 : rand_a[1]); + `signal(REPLACE_COND_WITH_ELSE_BRANCH_ZERO, rand_a[0] ? rand_a[1] : 1'd0); + `signal(REPLACE_COND_WITH_ELSE_BRANCH_ONES, rand_a[0] ? rand_a[1] : 1'd1); + `signal(INLINE_ARRAYSEL_SPLICE, array[0]); + `signal(NO_INLINE_ARRAYSEL_SPLICE_PARTIAL, array[2]); + `signal(INLINE_ARRAYSEL_UNIT, unitArrayWhole[0]); + `signal(NO_INLINE_ARRAYSEL_UNIT_PARTIAL, unitArrayParts[0]); + `signal(PUSH_BITWISE_THROUGH_REDUCTION_AND, (&(rand_a + 64'd105)) & (&(rand_b + 64'd108))); + `signal(PUSH_BITWISE_THROUGH_REDUCTION_OR, (|(rand_a + 64'd106)) | (|(rand_b + 64'd109))); + `signal(PUSH_BITWISE_THROUGH_REDUCTION_XOR, (^(rand_a + 64'd107)) ^ (^(rand_b + 64'd110))); + `signal(PUSH_REDUCTION_THROUGH_CONCAT_AND, &{1'd1, rand_b}); + `signal(PUSH_REDUCTION_THROUGH_CONCAT_OR, |{1'd1, rand_b}); + `signal(PUSH_REDUCTION_THROUGH_CONCAT_XOR, ^{1'd1, rand_b}); + `signal(REMOVE_WIDTH_ONE_REDUCTION_AND, &rand_a[0]); + `signal(REMOVE_WIDTH_ONE_REDUCTION_OR, |rand_a[0]); + `signal(REMOVE_WIDTH_ONE_REDUCTION_XOR, ^rand_a[0]); + `signal(REMOVE_XOR_WITH_ZERO, 64'd0 ^ rand_a); + `signal(REPLACE_XOR_WITH_SELF, ~rand_a ^ ~rand_a); + `signal(REPLACE_XOR_WITH_ONES, -64'd1 ^ rand_a); + `signal(REPLACE_COND_DEC, randbit_a ? rand_b - 64'b1 : rand_b); + `signal(REPLACE_COND_INC, randbit_a ? rand_b + 64'b1 : rand_b); + `signal(NO_REPLACE_COND_DEC, randbit_a ? rand_b - 64'hf000000000000000 : rand_b); + `signal(NO_REPLACE_COND_INC, randbit_a ? rand_b + 64'hf000000000000000 : rand_b); + `signal(REPLACE_LOGAND_WITH_AND, rand_a[0] && rand_a[1]); + `signal(REPLACE_LOGOR_WITH_OR, rand_a[0] || rand_a[1]); + `signal(RIGHT_LEANING_ASSOC, (((rand_a + rand_b) + rand_a) + rand_b)); + `signal(RIGHT_LEANING_CONCET, {{{rand_a, rand_b}, rand_a}, rand_b}); - // Operators that should work wiht mismatched widths - `signal(MISMATCHED_ShiftL,const_a << 4'd2); - `signal(MISMATCHED_ShiftR,const_a >> 4'd2); - `signal(MISMATCHED_ShiftRS, const_a >> 4'd2); - `signal(MISMATCHED_PowUU, rand_a ** 4'd5); - `signal(MISMATCHED_PowSS, srand_a ** 4'sd5); - `signal(MISMATCHED_PowSU, srand_b ** 4'd5); - `signal(MISMATCHED_PowUS, rand_b ** 4'sd5); + // Operators that should work wiht mismatched widths + `signal(MISMATCHED_ShiftL,const_a << 4'd2); + `signal(MISMATCHED_ShiftR,const_a >> 4'd2); + `signal(MISMATCHED_ShiftRS, const_a >> 4'd2); + `signal(MISMATCHED_PowUU, rand_a ** 4'd5); + `signal(MISMATCHED_PowSS, srand_a ** 4'sd5); + `signal(MISMATCHED_PowSU, srand_b ** 4'd5); + `signal(MISMATCHED_PowUS, rand_b ** 4'sd5); - // Some selects need extra temporaries - wire [63:0] sel_from_cond = rand_a[0] ? rand_a : const_a; - wire [63:0] sel_from_shiftl = rand_a << 10; - wire [31:0] sel_from_sel = rand_a[10+:32]; + // Some selects need extra temporaries + wire [63:0] sel_from_cond = rand_a[0] ? rand_a : const_a; + wire [63:0] sel_from_shiftl = rand_a << 10; + wire [31:0] sel_from_sel = rand_a[10+:32]; - `signal(PUSH_SEL_THROUGH_COND, sel_from_cond[2]); - `signal(PUSH_SEL_THROUGH_SHIFTL, sel_from_shiftl[20:0]); - `signal(REPLACE_SEL_FROM_SEL, sel_from_sel[4:3]); + `signal(PUSH_SEL_THROUGH_COND, sel_from_cond[2]); + `signal(PUSH_SEL_THROUGH_SHIFTL, sel_from_shiftl[20:0]); + `signal(REPLACE_SEL_FROM_SEL, sel_from_sel[4:3]); - logic [2:0] sel_from_partial_tmp;; - always_comb begin - sel_from_partial_tmp[1:0] = 2'd0; - if (rand_a[0]) begin - sel_from_partial_tmp[0] = rand_b[0]; - end - end - `signal(PUSH_SEL_THROUGH_SPLICE, sel_from_partial_tmp[1:0]); + logic [2:0] sel_from_partial_tmp;; + always_comb begin + sel_from_partial_tmp[1:0] = 2'd0; + if (rand_a[0]) begin + sel_from_partial_tmp[0] = rand_b[0]; + end + end + `signal(PUSH_SEL_THROUGH_SPLICE, sel_from_partial_tmp[1:0]); - `signal(PUSH_CONCAT_THROUGH_COND_LHS, {5'd0, rand_a[0] ? {rand_b[4], 1'b0} : {1'b0, rand_b[6]}}); - `signal(PUSH_CONCAT_THROUGH_COND_RHS, {rand_a[0] ? {rand_b[5], 1'b0} : {1'b0, rand_b[7]}, 5'd0}); + `signal(PUSH_CONCAT_THROUGH_COND_LHS, {5'd0, rand_a[0] ? {rand_b[4], 1'b0} : {1'b0, rand_b[6]}}); + `signal(PUSH_CONCAT_THROUGH_COND_RHS, {rand_a[0] ? {rand_b[5], 1'b0} : {1'b0, rand_b[7]}, 5'd0}); - `signal(REPLACE_SHIFTL_CAT, {31'd0, rand_a[42 +: 7]} << 31); - `signal(REPLACE_SHIFTRL_CAT, {rand_a[13 +: 7], rand_b[8 +: 27]} >> 27 << 27); + `signal(REPLACE_SHIFTL_CAT, {31'd0, rand_a[42 +: 7]} << 31); + `signal(REPLACE_SHIFTRL_CAT, {rand_a[13 +: 7], rand_b[8 +: 27]} >> 27 << 27); - // Asscending ranges - `signal(ASCENDNG_SEL, arand_a[0:4]); - // verilator lint_off ASCRANGE - wire [0:7] ascending_assign; - // verilator lint_on ASCRANGE - assign ascending_assign[0:3] = arand_a[4:7]; - assign ascending_assign[4:7] = arand_b[0:3]; - `signal(ASCENDING_ASSIGN, ascending_assign); + // Asscending ranges + `signal(ASCENDNG_SEL, arand_a[0:4]); + // verilator lint_off ASCRANGE + wire [0:7] ascending_assign; + // verilator lint_on ASCRANGE + assign ascending_assign[0:3] = arand_a[4:7]; + assign ascending_assign[4:7] = arand_b[0:3]; + `signal(ASCENDING_ASSIGN, ascending_assign); - // Special cases to be covered - `signal(REPLICATE_WIDTH, {4'd8{rand_a[0]}}); // Replicate count unsigned, but MSB set - if ($bits(REPLICATE_WIDTH) != 8) $fatal("%0d != 8", $bits(REPLICATE_WIDTH)); + // Special cases to be covered + `signal(REPLICATE_WIDTH, {4'd8{rand_a[0]}}); // Replicate count unsigned, but MSB set + if ($bits(REPLICATE_WIDTH) != 8) $fatal("%0d != 8", $bits(REPLICATE_WIDTH)); - // Sel from not requires the operand to have a sinle sink, so can't use - // the chekc due to the raw expression referencing the operand - wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]); - wire sel_from_not = sel_from_not_tmp[2]; - always @(posedge randbit_a) if ($c(0)) $display(sel_from_not); // Do not remove signal + // Sel from not requires the operand to have a sinle sink, so can't use + // the chekc due to the raw expression referencing the operand + wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]); + wire sel_from_not = sel_from_not_tmp[2]; + always @(posedge randbit_a) if ($c(0)) $display(sel_from_not); // Do not remove signal - // Narrow concatenation - wire [9:0] narrow_concat = {5'd0, ~rand_a[44 +: 5]}; - `signal(NARROW_CONCAT_A, narrow_concat[5:1]); - `signal(NARROW_CONCAT_B, narrow_concat[8:4]); - `signal(NARROW_CONCAT_C, narrow_concat[5:4]); + // Narrow concatenation + wire [9:0] narrow_concat = {5'd0, ~rand_a[44 +: 5]}; + `signal(NARROW_CONCAT_A, narrow_concat[5:1]); + `signal(NARROW_CONCAT_B, narrow_concat[8:4]); + `signal(NARROW_CONCAT_C, narrow_concat[5:4]); - // Assigned at the end to avoid inlining by other passes - assign const_a = 64'h0123456789abcdef; - assign const_b = 64'h98badefc10325647; - assign sconst_a = 64'hfedcba9876543210; - assign sconst_b = 64'hba0123456789cdef; + // Assigned at the end to avoid inlining by other passes + assign const_a = 64'h0123456789abcdef; + assign const_b = 64'h98badefc10325647; + assign sconst_a = 64'hfedcba9876543210; + assign sconst_b = 64'hba0123456789cdef; endmodule diff --git a/test_regress/t/t_dfg_regularize_circular.v b/test_regress/t/t_dfg_regularize_circular.v index ca56732e7..76e903677 100644 --- a/test_regress/t/t_dfg_regularize_circular.v +++ b/test_regress/t/t_dfg_regularize_circular.v @@ -5,15 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module A ( - output [2:0] Y + output [2:0] Y ); endmodule module B; wire [2:0] w1; wire w2; - A A ( - .Y({ w1[2], w1[0], w2 }) - ); + A A (.Y({w1[2], w1[0], w2})); assign w1[1] = w1[2]; endmodule diff --git a/test_regress/t/t_dfg_result_var_ext_write.v b/test_regress/t/t_dfg_result_var_ext_write.v index e50a267ea..f2fd51a0a 100644 --- a/test_regress/t/t_dfg_result_var_ext_write.v +++ b/test_regress/t/t_dfg_result_var_ext_write.v @@ -11,57 +11,57 @@ module top; - logic clk = 0; - always #5 clk = ~clk; + logic clk = 0; + always #5 clk = ~clk; - int cnt = 0; - always @(posedge clk) cnt <= cnt + 1; + int cnt = 0; + always @(posedge clk) cnt <= cnt + 1; - wire forcedVar = &cnt[2:1]; - wire sharedTerm = &cnt[2:1]; - wire otherVar = ~sharedTerm; + wire forcedVar = &cnt[2:1]; + wire sharedTerm = &cnt[2:1]; + wire otherVar = ~sharedTerm; - initial begin - repeat (50) begin - @(posedge clk); - `check(otherVar == ~forcedVar, 1); - end - - force forcedVar = 1'b1; - - repeat (50) begin - @(posedge clk); - `check(otherVar == ~forcedVar, cnt[2] & cnt[1]); - end - - release forcedVar; - - repeat (50) begin - @(posedge clk); - `check(otherVar == ~forcedVar, 1); - end - - force forcedVar = 1'b0; - - repeat (50) begin - @(posedge clk); - `check(otherVar == ~forcedVar, ~cnt[2] | ~cnt[1]); - end - - release forcedVar; - - repeat (50) begin - @(posedge clk); - `check(otherVar == ~forcedVar, 1); - end - - - $write("*-* All Finished *-*\n"); - $finish; + initial begin + repeat (50) begin + @(posedge clk); + `check(otherVar == ~forcedVar, 1); end - always @(sharedTerm or otherVar) begin - `check(otherVar, ~sharedTerm); + force forcedVar = 1'b1; + + repeat (50) begin + @(posedge clk); + `check(otherVar == ~forcedVar, cnt[2] & cnt[1]); end + release forcedVar; + + repeat (50) begin + @(posedge clk); + `check(otherVar == ~forcedVar, 1); + end + + force forcedVar = 1'b0; + + repeat (50) begin + @(posedge clk); + `check(otherVar == ~forcedVar, ~cnt[2] | ~cnt[1]); + end + + release forcedVar; + + repeat (50) begin + @(posedge clk); + `check(otherVar == ~forcedVar, 1); + end + + + $write("*-* All Finished *-*\n"); + $finish; + end + + always @(sharedTerm or otherVar) begin + `check(otherVar, ~sharedTerm); + end + endmodule diff --git a/test_regress/t/t_dfg_stats_patterns.v b/test_regress/t/t_dfg_stats_patterns.v index d539ea165..94851f764 100644 --- a/test_regress/t/t_dfg_stats_patterns.v +++ b/test_regress/t/t_dfg_stats_patterns.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input wire [3:0] a, - input wire [3:0] b, - input wire [3:0] c, - output wire [10:0] o + input wire [3:0] a, + input wire [3:0] b, + input wire [3:0] c, + output wire [10:0] o ); - wire [ 3:0] x = ~a & ~b; - wire [ 3:0] y = ~b & ~c; - wire [ 3:0] z = ~c & ~a; - wire [ 0:0] w1 = x[0]; - wire [ 7:0] w8 = {8{x[1]}}; + wire [3:0] x = ~a & ~b; + wire [3:0] y = ~b & ~c; + wire [3:0] z = ~c & ~a; + wire [0:0] w1 = x[0]; + wire [7:0] w8 = {8{x[1]}}; wire [15:0] w16 = {2{w8}}; wire [31:0] w32 = {2{w16}}; wire [63:0] w64a = {2{w32}}; diff --git a/test_regress/t/t_disable.out b/test_regress/t/t_disable.out index a70dd874c..e3b1a7498 100644 --- a/test_regress/t/t_disable.out +++ b/test_regress/t/t_disable.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_disable.v:17:13: Unsupported: disabling block that contains a fork - 17 | disable forked; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_disable.v:17:9: Unsupported: disabling block that contains a fork + 17 | disable forked; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_disable.v b/test_regress/t/t_disable.v index 309983ddf..b5be11209 100644 --- a/test_regress/t/t_disable.v +++ b/test_regress/t/t_disable.v @@ -6,21 +6,21 @@ module t; - initial begin - fork : foo - disable foo; - #1 $stop; + initial begin + fork : foo + disable foo; + #1 $stop; + join_none + #2; + begin : forked + fork + disable forked; + #1 $stop; join_none - #2; - begin : forked - fork - disable forked; - #1 $stop; - join_none - end - #2; - $write("*-* All Finished *-*\n"); - $finish; - end + end + #2; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_disable_empty.out b/test_regress/t/t_disable_empty.out index 48d8fd58b..584a6d714 100644 --- a/test_regress/t/t_disable_empty.out +++ b/test_regress/t/t_disable_empty.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_disable_empty.v:12:7: disable isn't underneath a begin with name: 'block' - 12 | disable block; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_disable_empty.v:12:5: disable isn't underneath a begin with name: 'block' + 12 | disable block; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_disable_empty.v b/test_regress/t/t_disable_empty.v index 2ed96492d..762ff418c 100644 --- a/test_regress/t/t_disable_empty.v +++ b/test_regress/t/t_disable_empty.v @@ -6,12 +6,12 @@ module t; - initial begin - if (0) begin : block - end - disable block; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (0) begin : block + end + disable block; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_disable_empty_outside.v b/test_regress/t/t_disable_empty_outside.v index de71c4429..e3ba541db 100644 --- a/test_regress/t/t_disable_empty_outside.v +++ b/test_regress/t/t_disable_empty_outside.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - begin : blk - static int x = 0; - fork : fork_blk - begin - end - begin - x = 1; - #2; - x = 2; - end - join_none - #1; - disable fork_blk; - #2; - if (x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + begin : blk + static int x = 0; + fork : fork_blk + begin + end + begin + x = 1; + #2; + x = 2; + end + join_none + #1; + disable fork_blk; + #2; + if (x != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_disable_fork1.v b/test_regress/t/t_disable_fork1.v index 6e05450e2..88dce5218 100644 --- a/test_regress/t/t_disable_fork1.v +++ b/test_regress/t/t_disable_fork1.v @@ -7,43 +7,48 @@ `define N 3 class Cls; - task runforks(integer n); - for (integer i = 0; i < n; i++) fork - #1 $stop; - join_none - endtask + task runforks(integer n); + for (integer i = 0; i < n; i++) + fork + #1 $stop; + join_none + endtask endclass module t; - Cls cls = new; + Cls cls = new; - initial begin - // run forks - for (integer i = 0; i < `N; i++) fork - #1 $stop; - join_none + initial begin + // run forks + for (integer i = 0; i < `N; i++) + fork + #1 $stop; + join_none - // run forks inside a method - cls.runforks(`N); + // run forks inside a method + cls.runforks(`N); - // run forks in forks - for (integer i = 0; i < `N; i++) fork - for (integer j = 0; j < `N; j++) fork - #1 $stop; - join_none - join_none - - for (integer i = 0; i < `N; i++) fork - cls.runforks(`N); - join_none - - // kill them all - disable fork; - - // check if we can still fork + // run forks in forks + for (integer i = 0; i < `N; i++) + fork + for (integer j = 0; j < `N; j++) fork - #2 $write("*-* All Finished *-*\n"); - #3 $finish; + #1 $stop; join_none - end + join_none + + for (integer i = 0; i < `N; i++) + fork + cls.runforks(`N); + join_none + + // kill them all + disable fork; + + // check if we can still fork + fork + #2 $write("*-* All Finished *-*\n"); + #3 $finish; + join_none + end endmodule diff --git a/test_regress/t/t_disable_fork2.v b/test_regress/t/t_disable_fork2.v index 8df074fab..11ec22ae5 100644 --- a/test_regress/t/t_disable_fork2.v +++ b/test_regress/t/t_disable_fork2.v @@ -24,44 +24,54 @@ // To check if that corresponds to reality, see blue nodes in proc_deps.dot class Cls; - task print; /*NO*/ - $write("*-* All "); - endtask - task disable_fork_func; /*YES*/ - disable fork; - endtask - task common_func; /*YES*/ - fork /*YES*/ #1; join_none - endtask - task fork_func; /*YES*/ - fork /*YES*/ #1 $stop; join_none - endtask - task delay_func; /*NO*/ - fork /*NO*/ #1 $write("Finished *-*\n"); join_none - endtask - task empty_fork; - fork - begin - end - join_none - disable fork; - endtask + task print; /*NO*/ + $write("*-* All "); + endtask + task disable_fork_func; /*YES*/ + disable fork; + endtask + task common_func; /*YES*/ + fork /*YES*/ + #1; + join_none + endtask + task fork_func; /*YES*/ + fork /*YES*/ + #1 $stop; + join_none + endtask + task delay_func; /*NO*/ + fork /*NO*/ + #1 $write("Finished *-*\n"); + join_none + endtask + task empty_fork; + fork + begin + end + join_none + disable fork; + endtask endclass module t; - Cls cls = new; + Cls cls = new; - initial begin /*YES*/ - fork /*YES*/ cls.common_func(); join_none - cls.fork_func(); - cls.disable_fork_func(); - cls.empty_fork(); - cls.print(); - end - - initial begin /*NO*/ - cls.delay_func(); + initial begin /*YES*/ + fork /*YES*/ cls.common_func(); - fork /*YES*/ disable fork; join_none - end + join_none + cls.fork_func(); + cls.disable_fork_func(); + cls.empty_fork(); + cls.print(); + end + + initial begin /*NO*/ + cls.delay_func(); + cls.common_func(); + fork /*YES*/ + disable fork; + join_none + end endmodule diff --git a/test_regress/t/t_disable_fork3.v b/test_regress/t/t_disable_fork3.v index 10b1d27fb..290f79f5f 100644 --- a/test_regress/t/t_disable_fork3.v +++ b/test_regress/t/t_disable_fork3.v @@ -5,21 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 class C; - task proc; - disable fork; - wait fork; - endtask + task proc; + disable fork; + wait fork; + endtask endclass module t; - initial begin - fork begin - fork begin + initial begin + fork + begin + fork + begin #3 $stop; - end join_none - #1; - end join_none - #2 disable fork; - end - initial #4 $write("*-* All Finished *-*\n"); + end + join_none + #1; + end + join_none + #2 disable fork; + end + initial #4 $write("*-* All Finished *-*\n"); endmodule diff --git a/test_regress/t/t_disable_fork_notiming.out b/test_regress/t/t_disable_fork_notiming.out index 63f71caef..36f89ca23 100644 --- a/test_regress/t/t_disable_fork_notiming.out +++ b/test_regress/t/t_disable_fork_notiming.out @@ -1,6 +1,6 @@ -%Error-NOTIMING: t/t_disable_fork_notiming.v:8:12: Support for disable fork statement requires --timing +%Error-NOTIMING: t/t_disable_fork_notiming.v:8:11: Support for disable fork statement requires --timing : ... note: In instance 't' - 8 | initial disable fork; - | ^~~~~~~ + 8 | initial disable fork; + | ^~~~~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_disable_fork_notiming.v b/test_regress/t/t_disable_fork_notiming.v index 519442866..ede65dc0f 100644 --- a/test_regress/t/t_disable_fork_notiming.v +++ b/test_regress/t/t_disable_fork_notiming.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial disable fork; + initial disable fork; endmodule diff --git a/test_regress/t/t_disable_func_bad.out b/test_regress/t/t_disable_func_bad.out index 0b3a8de88..1c788d2c2 100644 --- a/test_regress/t/t_disable_func_bad.out +++ b/test_regress/t/t_disable_func_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_disable_func_bad.v:19:13: Node of type FUNCREF 'increment_x' referenced by disable - 19 | #1 disable increment_x; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_disable_func_bad.v:19:10: Node of type FUNCREF 'increment_x' referenced by disable + 19 | #1 disable increment_x; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_disable_func_bad.v b/test_regress/t/t_disable_func_bad.v index b8479cf59..6ad547931 100644 --- a/test_regress/t/t_disable_func_bad.v +++ b/test_regress/t/t_disable_func_bad.v @@ -7,17 +7,17 @@ int x = 0; function int increment_x; - x++; - return x; + x++; + return x; endfunction module t; - initial begin - fork - increment_x(); - #1 disable increment_x; - join - end + initial begin + fork + increment_x(); + #1 disable increment_x; + join + end endmodule diff --git a/test_regress/t/t_disable_iff_multi_bad.out b/test_regress/t/t_disable_iff_multi_bad.out index 3c3eb788b..51b9324e6 100644 --- a/test_regress/t/t_disable_iff_multi_bad.out +++ b/test_regress/t/t_disable_iff_multi_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_disable_iff_multi_bad.v:14:4: Only one 'default disable iff' allowed per module (IEEE 1800-2023 16.15) +%Error: t/t_disable_iff_multi_bad.v:12:3: Only one 'default disable iff' allowed per module (IEEE 1800-2023 16.15) : ... note: In instance 't' - 14 | default disable iff (!rstn); - | ^~~~~~~ + 12 | default disable iff (!rstn); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_disable_iff_multi_bad.v b/test_regress/t/t_disable_iff_multi_bad.v index 6e2fd08fa..dd4663951 100644 --- a/test_regress/t/t_disable_iff_multi_bad.v +++ b/test_regress/t/t_disable_iff_multi_bad.v @@ -4,13 +4,11 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - rstn - ); - input rstn; +module t( + input rstn +); - default disable iff (!rstn); - default disable iff (!rstn); + default disable iff (!rstn); + default disable iff (!rstn); endmodule diff --git a/test_regress/t/t_disable_outside.v b/test_regress/t/t_disable_outside.v index 065bdee7e..f8da8789c 100644 --- a/test_regress/t/t_disable_outside.v +++ b/test_regress/t/t_disable_outside.v @@ -5,22 +5,22 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - begin : blk - int x; - fork : fork_blk - begin - x = 1; - #2; - x = 2; - end - join_none - #1; - disable fork_blk; - #2; - if (x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + begin : blk + int x; + fork : fork_blk + begin + x = 1; + #2; + x = 2; + end + join_none + #1; + disable fork_blk; + #2; + if (x != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_disable_outside2.v b/test_regress/t/t_disable_outside2.v index cd4a4e8f3..823b35a6e 100644 --- a/test_regress/t/t_disable_outside2.v +++ b/test_regress/t/t_disable_outside2.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - for (int i = 0; i < 3; i++) begin - begin : blk - int x; - fork : fork_blk - begin - x = 1; - #2; - x = 2; - end - join_none - #1; - if (i < 2) disable fork_blk; + initial begin + for (int i = 0; i < 3; i++) begin + begin : blk + int x; + fork : fork_blk + begin + x = 1; #2; - if (i < 2 && x != 1) $stop; - if (i == 2 && x != 2) $stop; - end + x = 2; + end + join_none + #1; + if (i < 2) disable fork_blk; + #2; + if (i < 2 && x != 1) $stop; + if (i == 2 && x != 2) $stop; end - $write("*-* All Finished *-*\n"); - $finish; - end + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_disable_outside3.v b/test_regress/t/t_disable_outside3.v index 0193608ea..e80a17571 100644 --- a/test_regress/t/t_disable_outside3.v +++ b/test_regress/t/t_disable_outside3.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - begin : blk - int x; - fork : fork_blk - begin - #4; - x = 3; - end - begin : begin_blk - x = 1; - #2; - x = 2; - end - join_none - #1; - disable fork_blk.begin_blk; - #2; - if (x != 1) $stop; - #2; - if (x != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + begin : blk + int x; + fork : fork_blk + begin + #4; + x = 3; + end + begin : begin_blk + x = 1; + #2; + x = 2; + end + join_none + #1; + disable fork_blk.begin_blk; + #2; + if (x != 1) $stop; + #2; + if (x != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_disable_outside4.v b/test_regress/t/t_disable_outside4.v index 02942a608..caf008053 100644 --- a/test_regress/t/t_disable_outside4.v +++ b/test_regress/t/t_disable_outside4.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - begin : blk - int x; - fork - begin - #1; - disable begin_blk; - end - begin : begin_blk - x = 1; - #2; - x = 2; - end - join_none - #3; - if (x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + begin : blk + int x; + fork + begin + #1; + disable begin_blk; + end + begin : begin_blk + x = 1; + #2; + x = 2; + end + join_none + #3; + if (x != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_disable_within_task_unsup.out b/test_regress/t/t_disable_within_task_unsup.out index 2435b8d8e..95b7ce788 100644 --- a/test_regress/t/t_disable_within_task_unsup.out +++ b/test_regress/t/t_disable_within_task_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_disable_within_task_unsup.v:8:4: Unsupported: disabling fork from task / function - 8 | disable t.init.fork_blk; - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_disable_within_task_unsup.v:8:3: Unsupported: disabling fork from task / function + 8 | disable t.init.fork_blk; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_disable_within_task_unsup.v b/test_regress/t/t_disable_within_task_unsup.v index 4ae25c626..ba70872c1 100644 --- a/test_regress/t/t_disable_within_task_unsup.v +++ b/test_regress/t/t_disable_within_task_unsup.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 task disable_fork_blk; - disable t.init.fork_blk; + disable t.init.fork_blk; endtask module t; - initial begin : init - int x; - fork : fork_blk - begin - x = 1; - disable_fork_blk(); - x = 2; - end - begin - #1; - x = 3; - end - join - if (x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin : init + int x; + fork : fork_blk + begin + x = 1; + disable_fork_blk(); + x = 2; + end + begin + #1; + x = 3; + end + join + if (x != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_bad.out b/test_regress/t/t_display_bad.out index 1c0308db9..8bfaeca50 100644 --- a/test_regress/t/t_display_bad.out +++ b/test_regress/t/t_display_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_display_bad.v:11:7: Missing arguments for $display-like format - 11 | $display("%x"); - | ^~~~~~~~ +%Error: t/t_display_bad.v:12:5: Missing arguments for $display-like format + 12 | $display("%x"); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_display_bad.v:13:7: Unknown $display-like format code: '%q' - 13 | $display("%q"); - | ^~~~~~~~ +%Error: t/t_display_bad.v:14:5: Unknown $display-like format code: '%q' + 14 | $display("%q"); + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_display_bad.v b/test_regress/t/t_display_bad.v index 00bc9d14d..be2f00132 100644 --- a/test_regress/t/t_display_bad.v +++ b/test_regress/t/t_display_bad.v @@ -5,13 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; - initial begin - // Display formatting - $display("%x"); // Too few - $display("%x",disp,disp); // Too many - $display("%q"); // Bad escape - $write("*-* All Finished *-*\n"); - $finish; - end + reg [40:0] disp; + initial disp = 41'ha_bbbb_cccc; + initial begin + // Display formatting + $display("%x"); // Too few + $display("%x", disp, disp); // Too many + $display("%q"); // Bad escape + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_concat.v b/test_regress/t/t_display_concat.v index 557c25289..7c0748b1d 100644 --- a/test_regress/t/t_display_concat.v +++ b/test_regress/t/t_display_concat.v @@ -4,29 +4,27 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int cyc = 0; - always @ (posedge clk) ++cyc; + int cyc = 0; + always @(posedge clk)++cyc; - reg [15 : 0] t2; + reg [15 : 0] t2; - always@(posedge clk) begin - if (cyc == 0) begin - t2 <= 16'd0; - end - else if (cyc == 2) begin - t2 <= 16'habcd; - end - else if (cyc == 4) begin - $display("abcd=%x", t2); - $display("ab0d=%x", { t2[15:8], 4'd0, t2[3:0] }); - $write("*-* All Finished *-*\n"); - $finish(32'd0); - end - end + always @(posedge clk) begin + if (cyc == 0) begin + t2 <= 16'd0; + end + else if (cyc == 2) begin + t2 <= 16'habcd; + end + else if (cyc == 4) begin + $display("abcd=%x", t2); + $display("ab0d=%x", {t2[15:8], 4'd0, t2[3:0]}); + $write("*-* All Finished *-*\n"); + $finish(32'd0); + end + end endmodule diff --git a/test_regress/t/t_display_concat2.v b/test_regress/t/t_display_concat2.v index bed6d74f7..bf025aea5 100644 --- a/test_regress/t/t_display_concat2.v +++ b/test_regress/t/t_display_concat2.v @@ -4,27 +4,24 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module test( - /*AUTOARG*/ - // Inputs - clk - ); +module test ( + input clk +); - input clk; + int cnt = 32'h12345678; + int cyc = 0; - int cnt = 32'h12345678; - int cyc = 0; - - always @(posedge clk) begin - if (cyc > 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - cyc <= cyc + 1; - cnt <= cnt + 1; - $write("%08x\n", {16'h0, cnt[15: 0]}); - $write("%08x\n", {16'h0, cnt[31:16]}); - end - end + always @(posedge clk) begin + if (cyc > 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + cyc <= cyc + 1; + cnt <= cnt + 1; + $write("%08x\n", {16'h0, cnt[15:0]}); + $write("%08x\n", {16'h0, cnt[31:16]}); + end + end endmodule diff --git a/test_regress/t/t_display_cwide_bad.out b/test_regress/t/t_display_cwide_bad.out index 604986459..900f43601 100644 --- a/test_regress/t/t_display_cwide_bad.out +++ b/test_regress/t/t_display_cwide_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTHTRUNC: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value - 10 | $display("%c", 32'h1234); - | ^~~~~~~~ +%Warning-WIDTHTRUNC: t/t_display_cwide_bad.v:10:5: $display-like format of %c format of > 8 bit value + 10 | $display("%c", 32'h1234); + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_display_cwide_bad.v b/test_regress/t/t_display_cwide_bad.v index ec30be7b7..610ce0864 100644 --- a/test_regress/t/t_display_cwide_bad.v +++ b/test_regress/t/t_display_cwide_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - // Display formatting - $display("%c", 32'h1234); // Bad wide %c - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Display formatting + $display("%c", 32'h1234); // Bad wide %c + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_esc_bad.out b/test_regress/t/t_display_esc_bad.out index 9f7d5dbda..9c56bbe29 100644 --- a/test_regress/t/t_display_esc_bad.out +++ b/test_regress/t/t_display_esc_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_display_esc_bad.v:9:16: Unknown escape sequence: \x - 9 | $display("\x\y\z"); - | ^~~~~~~~ +%Error: t/t_display_esc_bad.v:9:14: Unknown escape sequence: \x + 9 | $display("\x\y\z"); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_display_esc_bad.v b/test_regress/t/t_display_esc_bad.v index bd4df9d7c..23ea1bbd1 100644 --- a/test_regress/t/t_display_esc_bad.v +++ b/test_regress/t/t_display_esc_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $display("\x\y\z"); // Illegal escapes - end + initial begin + $display("\x\y\z"); // Illegal escapes + end endmodule diff --git a/test_regress/t/t_display_format_wide_decimal.v b/test_regress/t/t_display_format_wide_decimal.v index 3e2b3efeb..c9892b67a 100644 --- a/test_regress/t/t_display_format_wide_decimal.v +++ b/test_regress/t/t_display_format_wide_decimal.v @@ -6,34 +6,35 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int cycle; - bit [1023:0] x; + int cycle; + bit [1023:0] x; - initial x = '1; + initial x = '1; - always @(posedge clk) begin - if (cycle == 0) begin - // Format very wide constant number (which has more bits than can - // be counted in exponent of a double precision float), with %d. - $display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff); - end else begin - // Same, but for a variable with value only known at run-time - $display("%d", x); - end + always @(posedge clk) begin + if (cycle == 0) begin + // Format very wide constant number (which has more bits than can + // be counted in exponent of a double precision float), with %d. + $display( + "%d", + 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff); + end + else begin + // Same, but for a variable with value only known at run-time + $display("%d", x); + end - cycle <= cycle + 1; - x <= x >> 1; + cycle <= cycle + 1; + x <= x >> 1; - if (cycle == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cycle == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_display_impure.v b/test_regress/t/t_display_impure.v index 4e232adff..b9d369622 100644 --- a/test_regress/t/t_display_impure.v +++ b/test_regress/t/t_display_impure.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 function integer f; - static integer i = 0; - return ++i; + static integer i = 0; + return ++i; endfunction module t; - initial begin - $display("%d", f()); - $display("%d", f()); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("%d", f()); + $display("%d", f()); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_io.v b/test_regress/t/t_display_io.v index 14fac2d84..3d81ab0a3 100644 --- a/test_regress/t/t_display_io.v +++ b/test_regress/t/t_display_io.v @@ -4,25 +4,25 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - o, - // Inputs - i - ); +module t ( /*AUTOARG*/ + // Outputs + o, + // Inputs + i +); - input logic [95:0] i; - output logic [95:0] o; + input logic [95:0] i; + output logic [95:0] o; - string a_s; + string a_s; - initial begin - o = ~i; - $sformat(a_s, "%h", i); - $display(a_s); - $sformat(a_s, "%h", o); - $display(a_s); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + o = ~i; + $sformat(a_s, "%h", i); + $display(a_s); + $sformat(a_s, "%h", o); + $display(a_s); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_l.v b/test_regress/t/t_display_l.v index cff26cf20..ec779d407 100644 --- a/test_regress/t/t_display_l.v +++ b/test_regress/t/t_display_l.v @@ -6,11 +6,12 @@ module t; - initial begin - assert (0 == 0) else $fatal(2, "%l %m : %d", 0); - $display("%l %m"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + assert (0 == 0) + else $fatal(2, "%l %m : %d", 0); + $display("%l %m"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_mcd.v b/test_regress/t/t_display_mcd.v index 1d298549d..c099e3228 100644 --- a/test_regress/t/t_display_mcd.v +++ b/test_regress/t/t_display_mcd.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $fwrite(32'h8000_0001, "To stdout\n"); - $fflush(32'h8000_0001); - $fwrite(32'h8000_0002, "To stderr\n"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $fwrite(32'h8000_0001, "To stdout\n"); + $fflush(32'h8000_0001); + $fwrite(32'h8000_0002, "To stderr\n"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_merge.v b/test_regress/t/t_display_merge.v index d53f2f3bd..cba23bad2 100644 --- a/test_regress/t/t_display_merge.v +++ b/test_regress/t/t_display_merge.v @@ -5,67 +5,65 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int one = + int one = `ifdef verilator - $c32(1) + $c32(1) `else - 1 + 1 `endif - ; + ; - initial begin - $display("Merge:"); - $write("This "); - $write("should "); - $display("merge"); + initial begin + $display("Merge:"); + $write("This "); + $write("should "); + $display("merge"); - $display("Merge:"); - $write("This ", "", "should ", "", "also "); - $display("merge"); + $display("Merge:"); + $write("This ", "", "should ", "", "also "); + $display("merge"); - $display("f"); - $write(" 1=%0d a=%m 1=%0d", one, one); - $display(" 1=%0d b=%m 1=%0d", one, one); - $display(" pre"); - $display(" t=%0d", $time); - $display(" t2=%0d", $time); - $display(" post"); - $display(" t3=%0d", $time); - $display(" t4=%0d t5=%0d", $time,$time,$time); - $display("m"); - $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); - $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); - $display("mm"); - $display(""); + $display("f"); + $write(" 1=%0d a=%m 1=%0d", one, one); + $display(" 1=%0d b=%m 1=%0d", one, one); + $display(" pre"); + $display(" t=%0d", $time); + $display(" t2=%0d", $time); + $display(" post"); + $display(" t3=%0d", $time); + $display(" t4=%0d t5=%0d", $time, $time, $time); + $display("m"); + $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time, $time, $time, $time, $time); + $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time, $time, $time, $time, $time); + $display("mm"); + $display(""); - $write("f"); - $write(" a=%m"); - $write(" b=%m"); - $write(" pre"); - $write(" t=%0d", $time); - $write(" t2=%0d", $time); - $write(" post"); - $write(" t3=%0d", $time); - $write(" t4=%0d t5=%0d", $time,$time,$time); - $write("m"); - $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); - $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); - $display("mm"); + $write("f"); + $write(" a=%m"); + $write(" b=%m"); + $write(" pre"); + $write(" t=%0d", $time); + $write(" t2=%0d", $time); + $write(" post"); + $write(" t3=%0d", $time); + $write(" t4=%0d t5=%0d", $time, $time, $time); + $write("m"); + $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time, $time, $time, $time, $time); + $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time, $time, $time, $time, $time); + $display("mm"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("very very very very very very very very very very very very very very very very very very very very very very"); - $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", - one, one, one, one, one, - one, one, one, one, one); - $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", - one, one, one, one, one, - one, one, one, one, one); - $write("\n*-* All Finished *-*\n"); - $finish; - end + // verilog_format: off + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("very very very very very very very very very very very very very very very very very very very very very very"); + $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", one, one, one, one, one, one, one, one, one, one); + $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", one, one, one, one, one, one, one, one, one, one); + // verilog_format: on + $write("\n*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_qqq.v b/test_regress/t/t_display_qqq.v index 80c03f8d0..e866e9ebd 100644 --- a/test_regress/t/t_display_qqq.v +++ b/test_regress/t/t_display_qqq.v @@ -6,12 +6,12 @@ module t; - initial begin - $display("""First "quoted"\nsecond\ + initial begin + $display("""First "quoted"\nsecond\ third fourth"""); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_real.v b/test_regress/t/t_display_real.v index 606813027..518cd3ae8 100644 --- a/test_regress/t/t_display_real.v +++ b/test_regress/t/t_display_real.v @@ -5,41 +5,47 @@ // SPDX-License-Identifier: CC0-1.0 module t; - real n0; initial n0 = 0.0; - real n1; initial n1 = 1.0; - real n2; initial n2 = 0.1; - real n3; initial n3 = 1.2345e-15; - real n4; initial n4 = 2.579e+15; - reg [7:0] r8; initial r8 = 3; - integer iconst = 0; + real n0; + initial n0 = 0.0; + real n1; + initial n1 = 1.0; + real n2; + initial n2 = 0.1; + real n3; + initial n3 = 1.2345e-15; + real n4; + initial n4 = 2.579e+15; + reg [7:0] r8; + initial r8 = 3; + integer iconst = 0; - initial begin - // Display formatting - $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); - $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); - $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); - $display; - $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); - $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); - $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); - $display; - $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); - $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); - $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); - $display; - $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); - $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); - $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); - $display; - $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); - $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); - $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); - $display; - $display("r8=%d n1=%g n2=%g", r8, n1, n2); - $display("n1=%g n2=%g r8=%d", n1, n2, r8); - $display; - $display("iconst=%e %f %g", iconst, iconst, iconst); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Display formatting + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n0, n0, n0, n0, n0); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n0, n0, n0, n0, n0); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n0, n0, n0, n0, n0); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n1, n1, n1, n1, n1); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n1, n1, n1, n1, n1); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n1, n1, n1, n1, n1); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n2, n2, n2, n2, n2); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n2, n2, n2, n2, n2); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n2, n2, n2, n2, n2); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n3, n3, n3, n3, n3); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n3, n3, n3, n3, n3); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n3, n3, n3, n3, n3); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n4, n4, n4, n4, n4); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n4, n4, n4, n4, n4); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n4, n4, n4, n4, n4); + $display; + $display("r8=%d n1=%g n2=%g", r8, n1, n2); + $display("n1=%g n2=%g r8=%d", n1, n2, r8); + $display; + $display("iconst=%e %f %g", iconst, iconst, iconst); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_realtime.v b/test_regress/t/t_display_realtime.v index be6bfd6f6..0f74b7bc6 100644 --- a/test_regress/t/t_display_realtime.v +++ b/test_regress/t/t_display_realtime.v @@ -4,20 +4,18 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - $display("TestCase at %1t (%s)", $realtime, cyc[0] ? "Option1" : "Option2"); - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + $display("TestCase at %1t (%s)", $realtime, cyc[0] ? "Option1" : "Option2"); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_display_recurse.v b/test_regress/t/t_display_recurse.v index 40fd2eaee..f832b6ca1 100644 --- a/test_regress/t/t_display_recurse.v +++ b/test_regress/t/t_display_recurse.v @@ -4,49 +4,47 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer i; - integer count = 'd0; + integer i; + integer count = 'd0; - always @(posedge clk) begin - count <= count + 1; - if (count == 10) begin - for(i=0; i<30; i=i+4) begin - // See issue #4480, verilator may inline getb() which has another display inside it - $display("%d: %02x%02x%02x%02x", i, getb(i+3), getb(i+2), getb(i+1), getb(i)); - end + always @(posedge clk) begin + count <= count + 1; + if (count == 10) begin + for (i = 0; i < 30; i = i + 4) begin + // See issue #4480, verilator may inline getb() which has another display inside it + $display("%d: %02x%02x%02x%02x", i, getb(i + 3), getb(i + 2), getb(i + 1), getb(i)); end - if (count == 11) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + if (count == 11) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - localparam SIZE = 64*1024; - localparam ADDRW = $clog2(SIZE/4); - reg [31: 0] ram [(SIZE/4)-1: 0]; + localparam SIZE = 64 * 1024; + localparam ADDRW = $clog2(SIZE / 4); + reg [31:0] ram[(SIZE/4)-1:0]; - function [7:0] getb; - input [31:0] address; - if (address[31:ADDRW+2] != 0) begin - $display("Address out of range"); - end - case(address[1:0]) - 0: getb = ram[address[ADDRW+1: 2]][8*0+7:8*0]; - 1: getb = ram[address[ADDRW+1: 2]][8*1+7:8*1]; - 2: getb = ram[address[ADDRW+1: 2]][8*2+7:8*2]; - 3: getb = ram[address[ADDRW+1: 2]][8*3+7:8*3]; - endcase - endfunction + function [7:0] getb; + input [31:0] address; + if (address[31:ADDRW+2] != 0) begin + $display("Address out of range"); + end + case (address[1:0]) + 0: getb = ram[address[ADDRW+1:2]][8*0+7:8*0]; + 1: getb = ram[address[ADDRW+1:2]][8*1+7:8*1]; + 2: getb = ram[address[ADDRW+1:2]][8*2+7:8*2]; + 3: getb = ram[address[ADDRW+1:2]][8*3+7:8*3]; + endcase + endfunction - initial begin - for (i=0; i= 10) begin - // Display formatting - $write; // Check missing arguments work - $write("default: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 0, "", 0); - $write("-9,0,,0: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 0, "", 10); - $write("-9,0,,10: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 0, "ns", 5); - $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 3, "ns", 8); - $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 3, "ns"); - $write("-9,3,ns : [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9, 3); - $write("-9,3: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9); - $write("-9: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(); - $write(": [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $timeformat(-9,,,); - $write("-9,,,: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", - $time, $time, $time, $time); - $write("\n"); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if ($time >= 10) begin + // Display formatting + $write; // Check missing arguments work + $write("default: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 0, "", 0); + $write("-9,0,,0: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 0, "", 10); + $write("-9,0,,10: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 0, "ns", 5); + $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 3, "ns", 8); + $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 3, "ns"); + $write("-9,3,ns : [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9, 3); + $write("-9,3: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9); + $write("-9: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(); + $write(": [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $timeformat(-9,,,); + $write("-9,,,: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); + $write("\n"); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_display_type_bad.out b/test_regress/t/t_display_type_bad.out index aff55a449..aa2325d51 100644 --- a/test_regress/t/t_display_type_bad.out +++ b/test_regress/t/t_display_type_bad.out @@ -1,22 +1,22 @@ -%Error: t/t_display_type_bad.v:10:31: $display-line format of '%d' illegal with string argument +%Error: t/t_display_type_bad.v:10:29: $display-line format of '%d' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' - 10 | $display("%d %x %f %t", s, s, s, s); - | ^ + 10 | $display("%d %x %f %t", s, s, s, s); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_display_type_bad.v:10:34: $display-line format of '%x' illegal with string argument +%Error: t/t_display_type_bad.v:10:32: $display-line format of '%x' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' - 10 | $display("%d %x %f %t", s, s, s, s); - | ^ -%Error: t/t_display_type_bad.v:10:37: $display-line format of '%f' illegal with string argument + 10 | $display("%d %x %f %t", s, s, s, s); + | ^ +%Error: t/t_display_type_bad.v:10:35: $display-line format of '%f' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' - 10 | $display("%d %x %f %t", s, s, s, s); - | ^ -%Error: t/t_display_type_bad.v:10:40: $display-line format of '%t' illegal with string argument + 10 | $display("%d %x %f %t", s, s, s, s); + | ^ +%Error: t/t_display_type_bad.v:10:38: $display-line format of '%t' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' - 10 | $display("%d %x %f %t", s, s, s, s); - | ^ + 10 | $display("%d %x %f %t", s, s, s, s); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_display_type_bad.v b/test_regress/t/t_display_type_bad.v index 84407ecdd..b4e91b265 100644 --- a/test_regress/t/t_display_type_bad.v +++ b/test_regress/t/t_display_type_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - string s = "a string"; - initial begin - $display("%d %x %f %t", s, s, s, s); - $write("*-* All Finished *-*\n"); - $finish; - end + string s = "a string"; + initial begin + $display("%d %x %f %t", s, s, s, s); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_display_wide.v b/test_regress/t/t_display_wide.v index ef3595e03..ed33e482f 100644 --- a/test_regress/t/t_display_wide.v +++ b/test_regress/t/t_display_wide.v @@ -4,31 +4,32 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [4095:0] crc; + integer cyc = 0; + reg [4095:0] crc; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) - if (cyc==0) begin - // Setup - crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x%x%x%x\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); - $write("[%0t] cyc==%0d crc=%b%b%b%b\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); - //Unsupported: $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); - if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc - ) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) + if (cyc == 0) begin + // Setup + crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x%x%x%x\n", $time, cyc, crc[4095:3072], crc[2071:2048], + crc[2047:1024], crc[1023:0]); + $write("[%0t] cyc==%0d crc=%b%b%b%b\n", $time, cyc, crc[4095:3072], crc[2071:2048], + crc[2047:1024], crc[1023:0]); + //Unsupported: $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc + ) + $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_display_wide_bad.out b/test_regress/t/t_display_wide_bad.out index 363b2c68e..1276d3d05 100644 --- a/test_regress/t/t_display_wide_bad.out +++ b/test_regress/t/t_display_wide_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_display_wide_bad.v:25:10: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments - 25 | $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_display_wide_bad.v:23:7: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments + 23 | $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_display_wide_bad.v b/test_regress/t/t_display_wide_bad.v index 7278a7480..fbd1ecd27 100644 --- a/test_regress/t/t_display_wide_bad.v +++ b/test_regress/t/t_display_wide_bad.v @@ -4,27 +4,25 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [4095:0] crc; + integer cyc = 0; + reg [4095:0] crc; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) - if (cyc==0) begin - // Setup - crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); // Too wide - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) + if (cyc == 0) begin + // Setup + crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); // Too wide + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_do_while.v b/test_regress/t/t_do_while.v index 10e734d52..f384a95f2 100644 --- a/test_regress/t/t_do_while.v +++ b/test_regress/t/t_do_while.v @@ -5,63 +5,63 @@ // SPDX-License-Identifier: CC0-1.0 function automatic int get_1; - int a = 0; - do begin - int x = 1; - a += x; - end while (a < 0); - return a; + int a = 0; + do begin + int x = 1; + a += x; + end while (a < 0); + return a; endfunction module t; - int a; - initial begin - if (get_1() != 1) $stop; + int a; + initial begin + if (get_1() != 1) $stop; - a = 0; + a = 0; + do begin + automatic int x = 1; + a += x; + if (a == 1) begin + a = 2; + end + end while (a < 0); + if (a != 2) $stop; + + a = 1; + do begin + if (a == 1) begin + a = 2; + end + if (a == 2) begin + a = 3; + end + end while (a < 0); + if (a != 3) $stop; + + a = 1; + do begin + if (a == 1) begin + do begin + a++; + end while (a < 5); + end + if (a == 2) begin + a = 3; + end + end while (a < 0); + if (a != 5) $stop; + + a = 1; + do begin do begin - automatic int x = 1; - a += x; - if (a == 1) begin - a = 2; - end - end while (a < 0); - if (a != 2) $stop; + automatic int x = 1; + a += x; + end while (a < 3); + end while (a < 5); + if (a != 5) $stop; - a = 1; - do begin - if (a == 1) begin - a = 2; - end - if (a == 2) begin - a = 3; - end - end while (a < 0); - if (a != 3) $stop; - - a = 1; - do begin - if (a == 1) begin - do begin - a++; - end while (a < 5); - end - if (a == 2) begin - a = 3; - end - end while (a < 0); - if (a != 5) $stop; - - a = 1; - do begin - do begin - automatic int x = 1; - a += x; - end while (a < 3); - end while (a < 5); - if (a != 5) $stop; - - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_do_while_continue_bad.out b/test_regress/t/t_do_while_continue_bad.out index db937c0fd..2db86ede9 100644 --- a/test_regress/t/t_do_while_continue_bad.out +++ b/test_regress/t/t_do_while_continue_bad.out @@ -1,6 +1,6 @@ -%Warning-INFINITELOOP: t/t_do_while_continue_bad.v:14:7: Infinite loop (condition always true) - 14 | do begin - | ^~ +%Warning-INFINITELOOP: t/t_do_while_continue_bad.v:12:5: Infinite loop (condition always true) + 12 | do begin + | ^~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_do_while_continue_bad.v b/test_regress/t/t_do_while_continue_bad.v index e542ef30a..91b910a85 100644 --- a/test_regress/t/t_do_while_continue_bad.v +++ b/test_regress/t/t_do_while_continue_bad.v @@ -4,21 +4,18 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; + function void infinite_loop; + do begin + continue; + end while (1); + endfunction - function void infinite_loop; - do begin - continue; - end - while (1); - endfunction - - always @(posedge clk) begin - infinite_loop(); - $stop; - end + always @(posedge clk) begin + infinite_loop(); + $stop; + end endmodule diff --git a/test_regress/t/t_do_while_jumps.v b/test_regress/t/t_do_while_jumps.v index 74096ed8f..5706aaeac 100644 --- a/test_regress/t/t_do_while_jumps.v +++ b/test_regress/t/t_do_while_jumps.v @@ -4,171 +4,160 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; + function automatic bit test_1; + int iterations = 0; + do begin + iterations++; + break; + end while (1); + return iterations == 1; + endfunction - function automatic bit test_1; - int iterations = 0; + function automatic bit test_2; + int iterations = 0; + do begin + break; + iterations++; + end while (1); + return iterations == 0; + endfunction + + function bit test_3; + do break; while (1); + return 1'b1; + endfunction + + function automatic bit test_4; + int incr = 0; + do begin + incr++; + break; + incr++; + end while (1); + return incr == 1; + endfunction + + function automatic bit test_5; + int incr = 0; + do begin + do incr++; while (incr < 9); + incr++; + break; + incr++; + end while (1); + return incr == 10; + endfunction + + function automatic bit test_6; + int incr = 0; + do begin do begin - iterations++; - break; - end - while (1); - return iterations == 1; - endfunction + incr += 1; + incr += 2; + end while (incr < 9); + incr++; + break; + incr++; + end while (1); + return incr == 10; + endfunction - function automatic bit test_2; - int iterations = 0; + function automatic bit test_7; + int incr = 0; + do begin do begin - break; - iterations++; - end - while (1); - return iterations == 0; - endfunction + incr += 1; + break; + incr += 2; + end while (incr < 9); + incr++; + break; + incr++; + end while (1); + return incr == 2; + endfunction - function bit test_3; - do - break; - while (1); - return 1'b1; - endfunction + function automatic bit test_8; + int incr = 0; + do begin + incr++; + continue; + incr++; + end while (0); + return incr == 1; + endfunction - function automatic bit test_4; - int incr = 0; + function automatic bit test_9; + int incr = 0; + do begin + incr++; + continue; + incr++; + end while (incr < 5); + return incr == 5; + endfunction + + function automatic bit test_10; + do begin + continue; + end while (0); + return 1'b1; + endfunction + + function automatic bit test_11; + int incr = 0; + do begin + do incr++; while (0); + incr++; + continue; + incr++; + end while (incr < 11); + return incr == 12; + endfunction + + function automatic bit test_12; + int incr = 0; + do begin do begin - incr++; - break; - incr++; - end - while (1); - return incr == 1; - endfunction + incr++; + continue; + incr++; + end while (0); + incr++; + continue; + incr++; + end while (incr < 11); + return incr == 12; + endfunction - function automatic bit test_5; - int incr = 0; - do begin - do - incr++; - while (incr < 9); - incr++; - break; - incr++; - end - while (1); - return incr == 10; - endfunction + always @(posedge clk) begin + bit [11:0] results; + results = { + test_1(), + test_2(), + test_3(), + test_4(), + test_5(), + test_6(), + test_7(), + test_8(), + test_9(), + test_10(), + test_11(), + test_12() + }; - function automatic bit test_6; - int incr = 0; - do begin - do begin - incr += 1; - incr += 2; - end - while (incr < 9); - incr++; - break; - incr++; - end - while (1); - return incr == 10; - endfunction - - function automatic bit test_7; - int incr = 0; - do begin - do begin - incr += 1; - break; - incr += 2; - end - while (incr < 9); - incr++; - break; - incr++; - end - while (1); - return incr == 2; - endfunction - - function automatic bit test_8; - int incr = 0; - do begin - incr++; - continue; - incr++; - end - while (0); - return incr == 1; - endfunction - - function automatic bit test_9; - int incr = 0; - do begin - incr++; - continue; - incr++; - end - while (incr < 5); - return incr == 5; - endfunction - - function automatic bit test_10; - do begin - continue; - end - while (0); - return 1'b1; - endfunction - - function automatic bit test_11; - int incr = 0; - do begin - do - incr++; - while (0); - incr++; - continue; - incr++; - end - while (incr < 11); - return incr == 12; - endfunction - - function automatic bit test_12; - int incr = 0; - do begin - do begin - incr++; - continue; - incr++; - end - while (0); - incr++; - continue; - incr++; - end - while (incr < 11); - return incr == 12; - endfunction - - always @(posedge clk) begin - bit [11:0] results; - results = {test_1(), test_2(), test_3(), test_4(), test_5(), - test_6(), test_7(), test_8(), test_9(), test_10(), - test_11(), test_12()}; - - if (results == '1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Results: %b\n", results); - $stop; - end - end + if (results == '1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Results: %b\n", results); + $stop; + end + end endmodule diff --git a/test_regress/t/t_dos.v b/test_regress/t/t_dos.v index f684b38ef..5e6930cbd 100644 --- a/test_regress/t/t_dos.v +++ b/test_regress/t/t_dos.v @@ -5,17 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule // This file has DOS carrage returns in it! diff --git a/test_regress/t/t_dpi_2exp_bad.out b/test_regress/t/t_dpi_2exp_bad.out index 9b8483fa7..70ca433b2 100644 --- a/test_regress/t/t_dpi_2exp_bad.out +++ b/test_regress/t/t_dpi_2exp_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_dpi_2exp_bad.v:12:45: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' - 12 | export "DPI-C" dpix_t_int_renamed = task dpix_twice; - | ^~~~~~~~~~ +%Error: t/t_dpi_2exp_bad.v:12:44: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' + 12 | export "DPI-C" dpix_t_int_renamed = task dpix_twice; + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_2exp_bad.v b/test_regress/t/t_dpi_2exp_bad.v index 083077413..ace7bc7f7 100644 --- a/test_regress/t/t_dpi_2exp_bad.v +++ b/test_regress/t/t_dpi_2exp_bad.v @@ -8,11 +8,13 @@ module t; - export "DPI-C" task dpix_twice; - export "DPI-C" dpix_t_int_renamed = task dpix_twice; - task dpix_twice(input int i, output int o); o = ~i; endtask + export "DPI-C" task dpix_twice; + export "DPI-C" dpix_t_int_renamed = task dpix_twice; + task dpix_twice(input int i, output int o); + o = ~i; + endtask - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_2exparg_bad.out b/test_regress/t/t_dpi_2exparg_bad.out index 785f99a46..e908a6f57 100644 --- a/test_regress/t/t_dpi_2exparg_bad.out +++ b/test_regress/t/t_dpi_2exparg_bad.out @@ -1,21 +1,21 @@ -%Warning-WIDTHEXPAND: t/t_dpi_2exparg_bad.v:19:56: Operator NOT expects 64 bits on the LHS, but LHS's VARREF 'i' generates 32 bits. - : ... note: In instance 't.b' - 19 | task dpix_twice(input int i, output [63:0] o); o = ~i; endtask - | ^ +%Warning-WIDTHEXPAND: t/t_dpi_2exparg_bad.v:22:9: Operator NOT expects 64 bits on the LHS, but LHS's VARREF 'i' generates 32 bits. + : ... note: In instance 't.b' + 22 | o = ~i; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_dpi_2exparg_bad.v:12:53: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's NOT generates 32 bits. - : ... note: In instance 't.a' - 12 | task dpix_twice(input int i, output [2:0] o); o = ~i; endtask - | ^ +%Warning-WIDTHTRUNC: t/t_dpi_2exparg_bad.v:13:7: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's NOT generates 32 bits. + : ... note: In instance 't.a' + 13 | o = ~i; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_dpi_2exparg_bad.v:19:9: Duplicate declaration of DPI function with different signature: 'dpix_twice' - 19 | task dpix_twice(input int i, output [63:0] o); o = ~i; endtask - | ^~~~~~~~~~ +%Error: t/t_dpi_2exparg_bad.v:21:8: Duplicate declaration of DPI function with different signature: 'dpix_twice' + 21 | task dpix_twice(input int i, output [63:0] o); + | ^~~~~~~~~~ : ... New signature: void dpix_twice (int, svLogicVecVal* /* logic[63:0] */ ) - t/t_dpi_2exparg_bad.v:12:9: ... Original signature: void dpix_twice (int, svLogicVecVal* /* logic[2:0] */ ) - 12 | task dpix_twice(input int i, output [2:0] o); o = ~i; endtask - | ^~~~~~~~~~ + t/t_dpi_2exparg_bad.v:12:8: ... Original signature: void dpix_twice (int, svLogicVecVal* /* logic[2:0] */ ) + 12 | task dpix_twice(input int i, output [2:0] o); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_2exparg_bad.v b/test_regress/t/t_dpi_2exparg_bad.v index 4771911e8..723a47537 100644 --- a/test_regress/t/t_dpi_2exparg_bad.v +++ b/test_regress/t/t_dpi_2exparg_bad.v @@ -7,24 +7,28 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module a; - import "DPI-C" task dpii_twice; // Legal - export "DPI-C" task dpix_twice; // Bad - task dpix_twice(input int i, output [2:0] o); o = ~i; endtask - initial dpii_twice(); + import "DPI-C" task dpii_twice; // Legal + export "DPI-C" task dpix_twice; // Bad + task dpix_twice(input int i, output [2:0] o); + o = ~i; + endtask + initial dpii_twice(); endmodule module b; - import "DPI-C" task dpii_twice; // Legal - export "DPI-C" task dpix_twice; // Bad - task dpix_twice(input int i, output [63:0] o); o = ~i; endtask - initial dpii_twice(); + import "DPI-C" task dpii_twice; // Legal + export "DPI-C" task dpix_twice; // Bad + task dpix_twice(input int i, output [63:0] o); + o = ~i; + endtask + initial dpii_twice(); endmodule module t; - a a(); - b b(); + a a (); + b b (); - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index 8b22d6e09..7cf487322 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -24,73 +24,68 @@ // Define the width of registers and size of memory we use -`define REG_WIDTH 8 -`define MEM_SIZE 256 +`define REG_WIDTH 8 +`define MEM_SIZE 256 // Top module defines the accessors and instantiates a sub-module with // substantive content. -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - `include "t_dpi_accessors_macros_inc.vh" - `include "t_dpi_accessors_inc.vh" + `include "t_dpi_accessors_macros_inc.vh" + `include "t_dpi_accessors_inc.vh" - // Put the serious stuff in a sub-module, so we can check hierarchical - // access works OK. - test_sub i_test_sub (.clk (clk)); + // Put the serious stuff in a sub-module, so we can check hierarchical + // access works OK. + test_sub i_test_sub (.clk(clk)); -endmodule // t +endmodule // t // A sub-module with all sorts of goodies we would like to access -module test_sub (/*AUTOARG*/ - // Inputs - clk - ); +module test_sub ( + input clk +); - input clk; + integer i; // General counter - integer i; // General counter + // Elements we would like to access from outside + reg a; + reg [`REG_WIDTH - 1:0] b; + reg [`REG_WIDTH - 1:0] mem[`MEM_SIZE - 1:0]; + wire c; + wire [`REG_WIDTH - 1:0] d; + reg [`REG_WIDTH - 1:0] e; + reg [`REG_WIDTH - 1:0] f; - // Elements we would like to access from outside - reg a; - reg [`REG_WIDTH - 1:0] b; - reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; - wire c; - wire [`REG_WIDTH - 1:0] d; - reg [`REG_WIDTH - 1:0] e; - reg [`REG_WIDTH - 1:0] f; + // Drive our wires from our registers + assign c = ~a; + assign d = ~b; - // Drive our wires from our registers - assign c = ~a; - assign d = ~b; + // Initial values for registers and array + initial begin + a = 0; + b = `REG_WIDTH'h0; - // Initial values for registers and array - initial begin - a = 0; - b = `REG_WIDTH'h0; + for (i = 0; i < `MEM_SIZE; i++) begin + mem[i] = i[`REG_WIDTH-1:0]; + end - for (i = 0; i < `MEM_SIZE; i++) begin - mem[i] = i [`REG_WIDTH - 1:0]; - end + e = 0; + f = 0; + end - e = 0; - f = 0; - end + // Wipe out one memory cell in turn on the positive clock edge, restoring + // the previous element. We toggle the wipeout value. + always @(posedge clk) begin + mem[b] <= {`REG_WIDTH{a}}; + mem[b-1] <= b - 1; + a <= ~a; + b <= b + 1; + end - // Wipe out one memory cell in turn on the positive clock edge, restoring - // the previous element. We toggle the wipeout value. - always @(posedge clk) begin - mem[b] <= {`REG_WIDTH {a}}; - mem[b - 1] <= b - 1; - a <= ~a; - b <= b + 1; - end - -endmodule // test_sub +endmodule // test_sub diff --git a/test_regress/t/t_dpi_arg_inout_type.v b/test_regress/t/t_dpi_arg_inout_type.v index c09b4559b..2d8a085a3 100644 --- a/test_regress/t/t_dpi_arg_inout_type.v +++ b/test_regress/t/t_dpi_arg_inout_type.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -26,1050 +27,1048 @@ `define NULL null `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); `ifdef VERILATOR - wire _unused = &{1'b0, clk}; + wire _unused = &{1'b0, clk}; `endif - // Legal inout argument types for DPI functions + // Legal inout argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - typedef byte byte_t; - typedef byte unsigned byte_unsigned_t; - typedef shortint shortint_t; - typedef shortint unsigned shortint_unsigned_t; - typedef int int_t; - typedef int unsigned int_unsigned_t; - typedef longint longint_t; - typedef longint unsigned longint_unsigned_t; + // Basic types as per IEEE 1800-2023 35.5.6 + typedef byte byte_t; + typedef byte unsigned byte_unsigned_t; + typedef shortint shortint_t; + typedef shortint unsigned shortint_unsigned_t; + typedef int int_t; + typedef int unsigned int_unsigned_t; + typedef longint longint_t; + typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME - typedef time time_t; + typedef time time_t; `endif `ifndef NO_INTEGER - typedef integer integer_t; + typedef integer integer_t; `endif - typedef real real_t; + typedef real real_t; `ifndef NO_SHORTREAL - typedef shortreal shortreal_t; + typedef shortreal shortreal_t; `endif - typedef chandle chandle_t; - typedef string string_t; - typedef bit bit_t; - typedef logic logic_t; + typedef chandle chandle_t; + typedef string string_t; + typedef bit bit_t; + typedef logic logic_t; - // 2-state packed structures - typedef struct packed { bit x; } struct_2_state_1; - typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; - typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; - typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; - typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; - typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; + // 2-state packed structures + typedef struct packed { bit x; } struct_2_state_1; + typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; + typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; + typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; + typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; + typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; - // 2-state packed unions - typedef union packed { bit x; bit y; } union_2_state_1; - typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; - typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; - typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; - typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; - typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; + // 2-state packed unions + typedef union packed { bit x; bit y; } union_2_state_1; + typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; + typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; + typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; + typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; + typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; - // 4-state packed structures - typedef struct packed { logic x; } struct_4_state_1; - typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; - typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; - typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; - typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; - typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; + // 4-state packed structures + typedef struct packed { logic x; } struct_4_state_1; + typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; + typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; + typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; + typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; + typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; - // 4-state packed unions - typedef union packed { logic x; bit y; } union_4_state_1; - typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; - typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; - typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; - typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; - typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; + // 4-state packed unions + typedef union packed { logic x; bit y; } union_4_state_1; + typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; + typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; + typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; + typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; + typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - import "DPI-C" function void i_byte (inout byte x); - import "DPI-C" function void i_byte_unsigned (inout byte unsigned x); - import "DPI-C" function void i_shortint (inout shortint x); - import "DPI-C" function void i_shortint_unsigned (inout shortint unsigned x); - import "DPI-C" function void i_int (inout int x); - import "DPI-C" function void i_int_unsigned (inout int unsigned x); - import "DPI-C" function void i_longint (inout longint x); - import "DPI-C" function void i_longint_unsigned (inout longint unsigned x); + // Basic types as per IEEE 1800-2023 35.5.6 + import "DPI-C" function void i_byte (inout byte x); + import "DPI-C" function void i_byte_unsigned (inout byte unsigned x); + import "DPI-C" function void i_shortint (inout shortint x); + import "DPI-C" function void i_shortint_unsigned (inout shortint unsigned x); + import "DPI-C" function void i_int (inout int x); + import "DPI-C" function void i_int_unsigned (inout int unsigned x); + import "DPI-C" function void i_longint (inout longint x); + import "DPI-C" function void i_longint_unsigned (inout longint unsigned x); `ifndef NO_TIME - import "DPI-C" function void i_time (inout time x); + import "DPI-C" function void i_time (inout time x); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer (inout integer x); + import "DPI-C" function void i_integer (inout integer x); `endif - import "DPI-C" function void i_real (inout real x); + import "DPI-C" function void i_real (inout real x); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal (inout shortreal x); + import "DPI-C" function void i_shortreal (inout shortreal x); `endif - import "DPI-C" function void i_chandle (inout chandle x); - import "DPI-C" function void i_string (inout string x); - import "DPI-C" function void i_bit (inout bit x); - import "DPI-C" function void i_logic (inout logic x); + import "DPI-C" function void i_chandle (inout chandle x); + import "DPI-C" function void i_string (inout string x); + import "DPI-C" function void i_bit (inout bit x); + import "DPI-C" function void i_logic (inout logic x); - // Basic types via typedef - import "DPI-C" function void i_byte_t (inout byte_t x); - import "DPI-C" function void i_byte_unsigned_t (inout byte_unsigned_t x); - import "DPI-C" function void i_shortint_t (inout shortint_t x); - import "DPI-C" function void i_shortint_unsigned_t (inout shortint_unsigned_t x); - import "DPI-C" function void i_int_t (inout int_t x); - import "DPI-C" function void i_int_unsigned_t (inout int_unsigned_t x); - import "DPI-C" function void i_longint_t (inout longint_t x); - import "DPI-C" function void i_longint_unsigned_t (inout longint_unsigned_t x); + // Basic types via typedef + import "DPI-C" function void i_byte_t (inout byte_t x); + import "DPI-C" function void i_byte_unsigned_t (inout byte_unsigned_t x); + import "DPI-C" function void i_shortint_t (inout shortint_t x); + import "DPI-C" function void i_shortint_unsigned_t (inout shortint_unsigned_t x); + import "DPI-C" function void i_int_t (inout int_t x); + import "DPI-C" function void i_int_unsigned_t (inout int_unsigned_t x); + import "DPI-C" function void i_longint_t (inout longint_t x); + import "DPI-C" function void i_longint_unsigned_t (inout longint_unsigned_t x); `ifndef NO_TIME - import "DPI-C" function void i_time_t (inout time_t x); + import "DPI-C" function void i_time_t (inout time_t x); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_t (inout integer_t x); + import "DPI-C" function void i_integer_t (inout integer_t x); `endif - import "DPI-C" function void i_real_t (inout real_t x); + import "DPI-C" function void i_real_t (inout real_t x); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_t (inout shortreal_t x); + import "DPI-C" function void i_shortreal_t (inout shortreal_t x); `endif - import "DPI-C" function void i_chandle_t (inout chandle_t x); - import "DPI-C" function void i_string_t (inout string_t x); - import "DPI-C" function void i_bit_t (inout bit_t x); - import "DPI-C" function void i_logic_t (inout logic_t x); + import "DPI-C" function void i_chandle_t (inout chandle_t x); + import "DPI-C" function void i_string_t (inout string_t x); + import "DPI-C" function void i_bit_t (inout bit_t x); + import "DPI-C" function void i_logic_t (inout logic_t x); - // 2-state packed arrays - import "DPI-C" function void i_array_2_state_1 (inout bit [ 0:0] x); - import "DPI-C" function void i_array_2_state_32 (inout bit [ 31:0] x); - import "DPI-C" function void i_array_2_state_33 (inout bit [ 32:0] x); - import "DPI-C" function void i_array_2_state_64 (inout bit [ 63:0] x); - import "DPI-C" function void i_array_2_state_65 (inout bit [ 64:0] x); - import "DPI-C" function void i_array_2_state_128(inout bit [127:0] x); + // 2-state packed arrays + import "DPI-C" function void i_array_2_state_1 (inout bit [ 0:0] x); + import "DPI-C" function void i_array_2_state_32 (inout bit [ 31:0] x); + import "DPI-C" function void i_array_2_state_33 (inout bit [ 32:0] x); + import "DPI-C" function void i_array_2_state_64 (inout bit [ 63:0] x); + import "DPI-C" function void i_array_2_state_65 (inout bit [ 64:0] x); + import "DPI-C" function void i_array_2_state_128(inout bit [127:0] x); - // 2-state packed structures - import "DPI-C" function void i_struct_2_state_1 (inout struct_2_state_1 x); - import "DPI-C" function void i_struct_2_state_32 (inout struct_2_state_32 x); - import "DPI-C" function void i_struct_2_state_33 (inout struct_2_state_33 x); - import "DPI-C" function void i_struct_2_state_64 (inout struct_2_state_64 x); - import "DPI-C" function void i_struct_2_state_65 (inout struct_2_state_65 x); - import "DPI-C" function void i_struct_2_state_128 (inout struct_2_state_128 x); + // 2-state packed structures + import "DPI-C" function void i_struct_2_state_1 (inout struct_2_state_1 x); + import "DPI-C" function void i_struct_2_state_32 (inout struct_2_state_32 x); + import "DPI-C" function void i_struct_2_state_33 (inout struct_2_state_33 x); + import "DPI-C" function void i_struct_2_state_64 (inout struct_2_state_64 x); + import "DPI-C" function void i_struct_2_state_65 (inout struct_2_state_65 x); + import "DPI-C" function void i_struct_2_state_128 (inout struct_2_state_128 x); - // 2-state packed unions - import "DPI-C" function void i_union_2_state_1 (inout union_2_state_1 x); - import "DPI-C" function void i_union_2_state_32 (inout union_2_state_32 x); - import "DPI-C" function void i_union_2_state_33 (inout union_2_state_33 x); - import "DPI-C" function void i_union_2_state_64 (inout union_2_state_64 x); - import "DPI-C" function void i_union_2_state_65 (inout union_2_state_65 x); - import "DPI-C" function void i_union_2_state_128 (inout union_2_state_128 x); + // 2-state packed unions + import "DPI-C" function void i_union_2_state_1 (inout union_2_state_1 x); + import "DPI-C" function void i_union_2_state_32 (inout union_2_state_32 x); + import "DPI-C" function void i_union_2_state_33 (inout union_2_state_33 x); + import "DPI-C" function void i_union_2_state_64 (inout union_2_state_64 x); + import "DPI-C" function void i_union_2_state_65 (inout union_2_state_65 x); + import "DPI-C" function void i_union_2_state_128 (inout union_2_state_128 x); - // 4-state packed arrays - import "DPI-C" function void i_array_4_state_1 (inout logic [ 0:0] x); - import "DPI-C" function void i_array_4_state_32 (inout logic [ 31:0] x); - import "DPI-C" function void i_array_4_state_33 (inout logic [ 32:0] x); - import "DPI-C" function void i_array_4_state_64 (inout logic [ 63:0] x); - import "DPI-C" function void i_array_4_state_65 (inout logic [ 64:0] x); - import "DPI-C" function void i_array_4_state_128(inout logic [127:0] x); + // 4-state packed arrays + import "DPI-C" function void i_array_4_state_1 (inout logic [ 0:0] x); + import "DPI-C" function void i_array_4_state_32 (inout logic [ 31:0] x); + import "DPI-C" function void i_array_4_state_33 (inout logic [ 32:0] x); + import "DPI-C" function void i_array_4_state_64 (inout logic [ 63:0] x); + import "DPI-C" function void i_array_4_state_65 (inout logic [ 64:0] x); + import "DPI-C" function void i_array_4_state_128(inout logic [127:0] x); - // 4-state packed structures - import "DPI-C" function void i_struct_4_state_1 (inout struct_4_state_1 x); - import "DPI-C" function void i_struct_4_state_32 (inout struct_4_state_32 x); - import "DPI-C" function void i_struct_4_state_33 (inout struct_4_state_33 x); - import "DPI-C" function void i_struct_4_state_64 (inout struct_4_state_64 x); - import "DPI-C" function void i_struct_4_state_65 (inout struct_4_state_65 x); - import "DPI-C" function void i_struct_4_state_128 (inout struct_4_state_128 x); + // 4-state packed structures + import "DPI-C" function void i_struct_4_state_1 (inout struct_4_state_1 x); + import "DPI-C" function void i_struct_4_state_32 (inout struct_4_state_32 x); + import "DPI-C" function void i_struct_4_state_33 (inout struct_4_state_33 x); + import "DPI-C" function void i_struct_4_state_64 (inout struct_4_state_64 x); + import "DPI-C" function void i_struct_4_state_65 (inout struct_4_state_65 x); + import "DPI-C" function void i_struct_4_state_128 (inout struct_4_state_128 x); - // 4-state packed unions - import "DPI-C" function void i_union_4_state_1 (inout union_4_state_1 x); - import "DPI-C" function void i_union_4_state_32 (inout union_4_state_32 x); - import "DPI-C" function void i_union_4_state_33 (inout union_4_state_33 x); - import "DPI-C" function void i_union_4_state_64 (inout union_4_state_64 x); - import "DPI-C" function void i_union_4_state_65 (inout union_4_state_65 x); - import "DPI-C" function void i_union_4_state_128 (inout union_4_state_128 x); + // 4-state packed unions + import "DPI-C" function void i_union_4_state_1 (inout union_4_state_1 x); + import "DPI-C" function void i_union_4_state_32 (inout union_4_state_32 x); + import "DPI-C" function void i_union_4_state_33 (inout union_4_state_33 x); + import "DPI-C" function void i_union_4_state_64 (inout union_4_state_64 x); + import "DPI-C" function void i_union_4_state_65 (inout union_4_state_65 x); + import "DPI-C" function void i_union_4_state_128 (inout union_4_state_128 x); - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - export "DPI-C" function e_byte; - export "DPI-C" function e_byte_unsigned; - export "DPI-C" function e_shortint; - export "DPI-C" function e_shortint_unsigned; - export "DPI-C" function e_int; - export "DPI-C" function e_int_unsigned; - export "DPI-C" function e_longint; - export "DPI-C" function e_longint_unsigned; + // Basic types as per IEEE 1800-2023 35.5.6 + export "DPI-C" function e_byte; + export "DPI-C" function e_byte_unsigned; + export "DPI-C" function e_shortint; + export "DPI-C" function e_shortint_unsigned; + export "DPI-C" function e_int; + export "DPI-C" function e_int_unsigned; + export "DPI-C" function e_longint; + export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME - export "DPI-C" function e_time; + export "DPI-C" function e_time; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer; + export "DPI-C" function e_integer; `endif - export "DPI-C" function e_real; + export "DPI-C" function e_real; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal; + export "DPI-C" function e_shortreal; `endif - export "DPI-C" function e_chandle; - export "DPI-C" function e_string; - export "DPI-C" function e_bit; - export "DPI-C" function e_logic; + export "DPI-C" function e_chandle; + export "DPI-C" function e_string; + export "DPI-C" function e_bit; + export "DPI-C" function e_logic; - // Basic types via typedef - export "DPI-C" function e_byte_t; - export "DPI-C" function e_byte_unsigned_t; - export "DPI-C" function e_shortint_t; - export "DPI-C" function e_shortint_unsigned_t; - export "DPI-C" function e_int_t; - export "DPI-C" function e_int_unsigned_t; - export "DPI-C" function e_longint_t; - export "DPI-C" function e_longint_unsigned_t; + // Basic types via typedef + export "DPI-C" function e_byte_t; + export "DPI-C" function e_byte_unsigned_t; + export "DPI-C" function e_shortint_t; + export "DPI-C" function e_shortint_unsigned_t; + export "DPI-C" function e_int_t; + export "DPI-C" function e_int_unsigned_t; + export "DPI-C" function e_longint_t; + export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME - export "DPI-C" function e_time_t; + export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_t; + export "DPI-C" function e_integer_t; `endif - export "DPI-C" function e_real_t; + export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_t; + export "DPI-C" function e_shortreal_t; `endif - export "DPI-C" function e_chandle_t; - export "DPI-C" function e_string_t; - export "DPI-C" function e_bit_t; - export "DPI-C" function e_logic_t; + export "DPI-C" function e_chandle_t; + export "DPI-C" function e_string_t; + export "DPI-C" function e_bit_t; + export "DPI-C" function e_logic_t; - // 2-state packed arrays - export "DPI-C" function e_array_2_state_1; - export "DPI-C" function e_array_2_state_32; - export "DPI-C" function e_array_2_state_33; - export "DPI-C" function e_array_2_state_64; - export "DPI-C" function e_array_2_state_65; - export "DPI-C" function e_array_2_state_128; + // 2-state packed arrays + export "DPI-C" function e_array_2_state_1; + export "DPI-C" function e_array_2_state_32; + export "DPI-C" function e_array_2_state_33; + export "DPI-C" function e_array_2_state_64; + export "DPI-C" function e_array_2_state_65; + export "DPI-C" function e_array_2_state_128; - // 2-state packed structures - export "DPI-C" function e_struct_2_state_1; - export "DPI-C" function e_struct_2_state_32; - export "DPI-C" function e_struct_2_state_33; - export "DPI-C" function e_struct_2_state_64; - export "DPI-C" function e_struct_2_state_65; - export "DPI-C" function e_struct_2_state_128; + // 2-state packed structures + export "DPI-C" function e_struct_2_state_1; + export "DPI-C" function e_struct_2_state_32; + export "DPI-C" function e_struct_2_state_33; + export "DPI-C" function e_struct_2_state_64; + export "DPI-C" function e_struct_2_state_65; + export "DPI-C" function e_struct_2_state_128; - // 2-state packed unions - export "DPI-C" function e_union_2_state_1; - export "DPI-C" function e_union_2_state_32; - export "DPI-C" function e_union_2_state_33; - export "DPI-C" function e_union_2_state_64; - export "DPI-C" function e_union_2_state_65; - export "DPI-C" function e_union_2_state_128; + // 2-state packed unions + export "DPI-C" function e_union_2_state_1; + export "DPI-C" function e_union_2_state_32; + export "DPI-C" function e_union_2_state_33; + export "DPI-C" function e_union_2_state_64; + export "DPI-C" function e_union_2_state_65; + export "DPI-C" function e_union_2_state_128; - // 4-state packed arrays - export "DPI-C" function e_array_4_state_1; - export "DPI-C" function e_array_4_state_32; - export "DPI-C" function e_array_4_state_33; - export "DPI-C" function e_array_4_state_64; - export "DPI-C" function e_array_4_state_65; - export "DPI-C" function e_array_4_state_128; + // 4-state packed arrays + export "DPI-C" function e_array_4_state_1; + export "DPI-C" function e_array_4_state_32; + export "DPI-C" function e_array_4_state_33; + export "DPI-C" function e_array_4_state_64; + export "DPI-C" function e_array_4_state_65; + export "DPI-C" function e_array_4_state_128; - // 4-state packed structures - export "DPI-C" function e_struct_4_state_1; - export "DPI-C" function e_struct_4_state_32; - export "DPI-C" function e_struct_4_state_33; - export "DPI-C" function e_struct_4_state_64; - export "DPI-C" function e_struct_4_state_65; - export "DPI-C" function e_struct_4_state_128; + // 4-state packed structures + export "DPI-C" function e_struct_4_state_1; + export "DPI-C" function e_struct_4_state_32; + export "DPI-C" function e_struct_4_state_33; + export "DPI-C" function e_struct_4_state_64; + export "DPI-C" function e_struct_4_state_65; + export "DPI-C" function e_struct_4_state_128; - // 4-state packed unions - export "DPI-C" function e_union_4_state_1; - export "DPI-C" function e_union_4_state_32; - export "DPI-C" function e_union_4_state_33; - export "DPI-C" function e_union_4_state_64; - export "DPI-C" function e_union_4_state_65; - export "DPI-C" function e_union_4_state_128; + // 4-state packed unions + export "DPI-C" function e_union_4_state_1; + export "DPI-C" function e_union_4_state_32; + export "DPI-C" function e_union_4_state_33; + export "DPI-C" function e_union_4_state_64; + export "DPI-C" function e_union_4_state_65; + export "DPI-C" function e_union_4_state_128; - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - byte n_byte = 0; - function void e_byte(inout byte x); - if (x !== 8'd10 + n_byte) $stop; - x += 8'd100; - n_byte++; - endfunction + // Basic types as per IEEE 1800-2023 35.5.6 + byte n_byte = 0; + function void e_byte(inout byte x); + if (x !== 8'd10 + n_byte) $stop; + x += 8'd100; + n_byte++; + endfunction - byte n_byte_unsigned = 0; - function void e_byte_unsigned(inout byte unsigned x); - if (x !== 8'd20 + n_byte_unsigned) $stop; - x += 8'd200; - n_byte_unsigned++; - endfunction + byte n_byte_unsigned = 0; + function void e_byte_unsigned(inout byte unsigned x); + if (x !== 8'd20 + n_byte_unsigned) $stop; + x += 8'd200; + n_byte_unsigned++; + endfunction - shortint n_shortint = 0; - function void e_shortint(inout shortint x); - if (x !== 16'd30 + n_shortint) $stop; - x += 16'd300; - n_shortint++; - endfunction + shortint n_shortint = 0; + function void e_shortint(inout shortint x); + if (x !== 16'd30 + n_shortint) $stop; + x += 16'd300; + n_shortint++; + endfunction - shortint n_shortint_unsigned = 0; - function void e_shortint_unsigned(inout shortint unsigned x); - if (x !== 16'd40 + n_shortint_unsigned) $stop; - x += 16'd400; - n_shortint_unsigned++; - endfunction + shortint n_shortint_unsigned = 0; + function void e_shortint_unsigned(inout shortint unsigned x); + if (x !== 16'd40 + n_shortint_unsigned) $stop; + x += 16'd400; + n_shortint_unsigned++; + endfunction - int n_int = 0; - function void e_int(inout int x); - if (x !== 32'd50 + n_int) $stop; - x += 32'd500; - n_int++; - endfunction + int n_int = 0; + function void e_int(inout int x); + if (x !== 32'd50 + n_int) $stop; + x += 32'd500; + n_int++; + endfunction - int n_int_unsigned = 0; - function void e_int_unsigned(inout int unsigned x); - if (x !== 32'd60 + n_int_unsigned) $stop; - x += 32'd600; - n_int_unsigned++; - endfunction + int n_int_unsigned = 0; + function void e_int_unsigned(inout int unsigned x); + if (x !== 32'd60 + n_int_unsigned) $stop; + x += 32'd600; + n_int_unsigned++; + endfunction - longint n_longint = 0; - function void e_longint(inout longint x); - if (x !== 64'd70 + n_longint) $stop; - x += 64'd700; - n_longint++; - endfunction + longint n_longint = 0; + function void e_longint(inout longint x); + if (x !== 64'd70 + n_longint) $stop; + x += 64'd700; + n_longint++; + endfunction - longint n_longint_unsigned = 0; - function void e_longint_unsigned(inout longint unsigned x); - if (x !== 64'd80 + n_longint_unsigned) $stop; - x += 64'd800; - n_longint_unsigned++; - endfunction + longint n_longint_unsigned = 0; + function void e_longint_unsigned(inout longint unsigned x); + if (x !== 64'd80 + n_longint_unsigned) $stop; + x += 64'd800; + n_longint_unsigned++; + endfunction `ifndef NO_TIME - longint n_time = 0; - function void e_time(inout time x); - if (x !== 64'd90 + n_time) $stop; - x += 64'd900; - n_time++; - endfunction + longint n_time = 0; + function void e_time(inout time x); + if (x !== 64'd90 + n_time) $stop; + x += 64'd900; + n_time++; + endfunction `endif `ifndef NO_INTEGER - int n_integer = 0; - function void e_integer(inout integer x); - if (x !== 32'd100 + n_integer) $stop; - x += 32'd1000; - n_integer++; - endfunction + int n_integer = 0; + function void e_integer(inout integer x); + if (x !== 32'd100 + n_integer) $stop; + x += 32'd1000; + n_integer++; + endfunction `endif - int n_real = 0; - function void e_real(inout real x); - if (x != real'(2*n_real + 1) / 2.0) $stop; - x += 100.0; - n_real++; - endfunction + int n_real = 0; + function void e_real(inout real x); + if (x != real'(2*n_real + 1) / 2.0) $stop; + x += 100.0; + n_real++; + endfunction `ifndef NO_SHORTREAL - int n_shortreal = 0; - function void e_shortreal(inout shortreal x); - if (x != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; - x += 200.0; - n_shortreal++; - endfunction + int n_shortreal = 0; + function void e_shortreal(inout shortreal x); + if (x != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; + x += 200.0; + n_shortreal++; + endfunction `endif - int n_chandle = 0; - function void e_chandle(inout chandle x); - $display("e_chandle %1d", n_chandle); - if (!n_chandle[0]) begin - if (x === `NULL) $stop; + int n_chandle = 0; + function void e_chandle(inout chandle x); + $display("e_chandle %1d", n_chandle); + if (!n_chandle[0]) begin + if (x === `NULL) $stop; + end else begin + if (x !== `NULL) $stop; + end + x = `NULL; + n_chandle++; + endfunction + + int n_string = 0; + function void e_string(inout string x); + $display("e_string %1d", n_string); + if (!n_string[0]) begin + if (x != "Good") $stop; + x = "Hello"; + end else begin + if (x != "Bye") $stop; + x = "World"; + end + n_string++; + endfunction + + int n_bit = 0; + function void e_bit(inout bit x); + $display("e_bit %1d", n_bit); + if (x !== n_bit[0]) $stop; + x = ~x; + n_bit++; + endfunction + + int n_logic = 0; + function void e_logic(inout logic x); + $display("e_logic %1d", n_logic); + if (x !== ~n_logic[0]) $stop; + x = ~x; + n_logic++; + endfunction + + // Basic types via typedefs + byte_t n_byte_t = 0; + function void e_byte_t(inout byte_t x); + if (x !== 8'd10 + n_byte_t) $stop; + x += 8'd101; + n_byte_t += 2; + endfunction + + byte n_byte_unsigned_t = 0; + function void e_byte_unsigned_t(inout byte_unsigned_t x); + if (x !== 8'd20 + n_byte_unsigned_t) $stop; + x += 8'd202; + n_byte_unsigned_t += 2; + endfunction + + shortint_t n_shortint_t = 0; + function void e_shortint_t(inout shortint_t x); + if (x !== 16'd30 + n_shortint_t) $stop; + x += 16'd303; + n_shortint_t += 2; + endfunction + + shortint n_shortint_unsigned_t = 0; + function void e_shortint_unsigned_t(inout shortint_unsigned_t x); + if (x !== 16'd40 + n_shortint_unsigned_t) $stop; + x += 16'd404; + n_shortint_unsigned_t += 2; + endfunction + + int_t n_int_t = 0; + function void e_int_t(inout int_t x); + if (x !== 32'd50 + n_int_t) $stop; + x += 32'd505; + n_int_t += 2; + endfunction + + int n_int_unsigned_t = 0; + function void e_int_unsigned_t(inout int_unsigned_t x); + if (x !== 32'd60 + n_int_unsigned_t) $stop; + x += 32'd606; + n_int_unsigned_t += 2; + endfunction + + longint_t n_longint_t = 0; + function void e_longint_t(inout longint_t x); + if (x !== 64'd70 + n_longint_t) $stop; + x += 64'd707; + n_longint_t += 2; + endfunction + + longint n_longint_unsigned_t = 0; + function void e_longint_unsigned_t(inout longint_unsigned_t x); + if (x !== 64'd80 + n_longint_unsigned_t) $stop; + x += 64'd808; + n_longint_unsigned_t += 2; + endfunction + +`ifndef NO_TIME + longint n_time_t = 0; + function void e_time_t(inout time_t x); + if (x !== 64'd90 + n_time_t) $stop; + x += 64'd909; + n_time_t += 2; + endfunction +`endif + +`ifndef NO_INTEGER + int n_integer_t = 0; + function void e_integer_t(inout integer_t x); + if (x !== 32'd100 + n_integer_t) $stop; + x += 32'd1001; + n_integer_t += 2; + endfunction +`endif + + int n_real_t = 0; + function void e_real_t(inout real_t x); + if (x != real'(2*n_real_t + 1) / 2.0) $stop; + x += 111.0; + n_real_t += 2; + endfunction + +`ifndef NO_SHORTREAL + int n_shortreal_t = 0; + function void e_shortreal_t(inout shortreal_t x); + if (x != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; + x += 222.0; + n_shortreal_t += 2; + endfunction +`endif + + int n_chandle_t = 0; + function void e_chandle_t(inout chandle_t x); + $display("e_chandle_t %1d", n_chandle_t); + if (!n_chandle_t[0]) begin + if (x !== `NULL) $stop; + end else begin + if (x === `NULL) $stop; + end + x = `NULL; + n_chandle_t++; + endfunction + + int n_string_t = 0; + function void e_string_t(inout string_t x); + $display("e_string_t %1d", n_string_t); + if (!n_string_t[0]) begin + if (x != "Bye") $stop; + x = "World"; + end else begin + if (x != "Good") $stop; + x = "Hello"; + end + n_string_t++; + endfunction + + int n_bit_t = 0; + function void e_bit_t(inout bit_t x); + $display("e_bit_t %1d", n_bit_t); + if (x !== n_bit_t[0]) $stop; + x = ~x; + n_bit_t++; + endfunction + + int n_logic_t = 0; + function void e_logic_t(inout logic_t x); + $display("e_logic_t %1d", n_logic_t); + if (x !== ~n_logic_t[0]) $stop; + x = ~x; + n_logic_t++; + endfunction + + // 2-state packed arrays + int n_array_2_state_1 = 0; + function void e_array_2_state_1(inout bit [ 0:0] x); + $display("e_array_2_state_1 %1d", n_array_2_state_1); + if (x !== n_array_2_state_1[0]) $stop; + x = ~x; + n_array_2_state_1++; + endfunction + + int n_array_2_state_32 = 0; + function void e_array_2_state_32(inout bit [31:0] x); + $display("e_array_2_state_32 %1d", n_array_2_state_32); + if (x !== ~32'd0 >> n_array_2_state_32) $stop; + x <<= n_array_2_state_32; + n_array_2_state_32++; + endfunction + + int n_array_2_state_33 = 0; + function void e_array_2_state_33(inout bit [32:0] x); + $display("e_array_2_state_33 %1d", n_array_2_state_33); + if (x !== ~33'd0 >> n_array_2_state_33) $stop; + x <<= n_array_2_state_33; + n_array_2_state_33++; + endfunction + + int n_array_2_state_64 = 0; + function void e_array_2_state_64(inout bit [63:0] x); + $display("e_array_2_state_64 %1d", n_array_2_state_64); + if (x !== ~64'd0 >> n_array_2_state_64) $stop; + x <<= n_array_2_state_64; + n_array_2_state_64++; + endfunction + + int n_array_2_state_65 = 0; + function void e_array_2_state_65(inout bit [64:0] x); + $display("e_array_2_state_65 %1d", n_array_2_state_65); + if (x !== ~65'd0 >> n_array_2_state_65) $stop; + x <<= n_array_2_state_65; + n_array_2_state_65++; + endfunction + + int n_array_2_state_128 = 0; + function void e_array_2_state_128(inout bit [127:0] x); + $display("e_array_2_state_128 %1d", n_array_2_state_128); + if (x !== ~128'd0 >> n_array_2_state_128) $stop; + x <<= n_array_2_state_128; + n_array_2_state_128++; + endfunction + + // 2-state packed structures + int n_struct_2_state_1 = 0; + function void e_struct_2_state_1(inout struct_2_state_1 x); + $display("e_struct_2_state_1 %1d", n_struct_2_state_1); + if (x !== n_struct_2_state_1[0]) $stop; + x = ~x; + n_struct_2_state_1++; + endfunction + + int n_struct_2_state_32 = 0; + function void e_struct_2_state_32(inout struct_2_state_32 x); + $display("e_struct_2_state_32 %1d", n_struct_2_state_32); + if (x !== ~32'd0 >> n_struct_2_state_32) $stop; + x <<= n_struct_2_state_32; + n_struct_2_state_32++; + endfunction + + int n_struct_2_state_33 = 0; + function void e_struct_2_state_33(inout struct_2_state_33 x); + $display("e_struct_2_state_33 %1d", n_struct_2_state_33); + if (x !== ~33'd0 >> n_struct_2_state_33) $stop; + x <<= n_struct_2_state_33; + n_struct_2_state_33++; + endfunction + + int n_struct_2_state_64 = 0; + function void e_struct_2_state_64(inout struct_2_state_64 x); + $display("e_struct_2_state_64 %1d", n_struct_2_state_64); + if (x !== ~64'd0 >> n_struct_2_state_64) $stop; + x <<= n_struct_2_state_64; + n_struct_2_state_64++; + endfunction + + int n_struct_2_state_65 = 0; + function void e_struct_2_state_65(inout struct_2_state_65 x); + $display("e_struct_2_state_65 %1d", n_struct_2_state_65); + if (x !== ~65'd0 >> n_struct_2_state_65) $stop; + x <<= n_struct_2_state_65; + n_struct_2_state_65++; + endfunction + + int n_struct_2_state_128 = 0; + function void e_struct_2_state_128(inout struct_2_state_128 x); + $display("e_struct_2_state_128 %1d", n_struct_2_state_128); + if (x !== ~128'd0 >> n_struct_2_state_128) $stop; + x <<= n_struct_2_state_128; + n_struct_2_state_128++; + endfunction + + // 2-state packed unions + int n_union_2_state_1 = 0; + function void e_union_2_state_1(inout union_2_state_1 x); + $display("e_union_2_state_1 %1d", n_union_2_state_1); + if (x !== n_union_2_state_1[0]) $stop; + x = ~x; + n_union_2_state_1++; + endfunction + + int n_union_2_state_32 = 0; + function void e_union_2_state_32(inout union_2_state_32 x); + $display("e_union_2_state_32 %1d", n_union_2_state_32); + if (x !== ~32'd0 >> n_union_2_state_32) $stop; + x <<= n_union_2_state_32; + n_union_2_state_32++; + endfunction + + int n_union_2_state_33 = 0; + function void e_union_2_state_33(inout union_2_state_33 x); + $display("e_union_2_state_33 %1d", n_union_2_state_33); + if (x !== ~33'd0 >> n_union_2_state_33) $stop; + x <<= n_union_2_state_33; + n_union_2_state_33++; + endfunction + + int n_union_2_state_64 = 0; + function void e_union_2_state_64(inout union_2_state_64 x); + $display("e_union_2_state_64 %1d", n_union_2_state_64); + if (x !== ~64'd0 >> n_union_2_state_64) $stop; + x <<= n_union_2_state_64; + n_union_2_state_64++; + endfunction + + int n_union_2_state_65 = 0; + function void e_union_2_state_65(inout union_2_state_65 x); + $display("e_union_2_state_65 %1d", n_union_2_state_65); + if (x !== ~65'd0 >> n_union_2_state_65) $stop; + x <<= n_union_2_state_65; + n_union_2_state_65++; + endfunction + + int n_union_2_state_128 = 0; + function void e_union_2_state_128(inout union_2_state_128 x); + $display("e_union_2_state_128 %1d", n_union_2_state_128); + if (x !== ~128'd0 >> n_union_2_state_128) $stop; + x <<= n_union_2_state_128; + n_union_2_state_128++; + endfunction + + // 4-state packed arrays + int n_array_4_state_1 = 0; + function void e_array_4_state_1(inout logic [ 0:0] x); + $display("e_array_4_state_1 %1d", n_array_4_state_1); + if (x !== n_array_4_state_1[0]) $stop; + x = ~x; + n_array_4_state_1++; + endfunction + + int n_array_4_state_32 = 0; + function void e_array_4_state_32(inout logic [31:0] x); + $display("e_array_4_state_32 %1d", n_array_4_state_32); + if (x !== ~32'd0 >> n_array_4_state_32) $stop; + x <<= n_array_4_state_32; + n_array_4_state_32++; + endfunction + + int n_array_4_state_33 = 0; + function void e_array_4_state_33(inout logic [32:0] x); + $display("e_array_4_state_33 %1d", n_array_4_state_33); + if (x !== ~33'd0 >> n_array_4_state_33) $stop; + x <<= n_array_4_state_33; + n_array_4_state_33++; + endfunction + + int n_array_4_state_64 = 0; + function void e_array_4_state_64(inout logic [63:0] x); + $display("e_array_4_state_64 %1d", n_array_4_state_64); + if (x !== ~64'd0 >> n_array_4_state_64) $stop; + x <<= n_array_4_state_64; + n_array_4_state_64++; + endfunction + + int n_array_4_state_65 = 0; + function void e_array_4_state_65(inout logic [64:0] x); + $display("e_array_4_state_65 %1d", n_array_4_state_65); + if (x !== ~65'd0 >> n_array_4_state_65) $stop; + x <<= n_array_4_state_65; + n_array_4_state_65++; + endfunction + + int n_array_4_state_128 = 0; + function void e_array_4_state_128(inout logic [127:0] x); + $display("e_array_4_state_128 %1d", n_array_4_state_128); + if (x !== ~128'd0 >> n_array_4_state_128) $stop; + x <<= n_array_4_state_128; + n_array_4_state_128++; + endfunction + + // 4-state packed structures + int n_struct_4_state_1 = 0; + function void e_struct_4_state_1(inout struct_4_state_1 x); + $display("e_struct_4_state_1 %1d", n_struct_4_state_1); + if (x !== n_struct_4_state_1[0]) $stop; + x = ~x; + n_struct_4_state_1++; + endfunction + + int n_struct_4_state_32 = 0; + function void e_struct_4_state_32(inout struct_4_state_32 x); + $display("e_struct_4_state_32 %1d", n_struct_4_state_32); + if (x !== ~32'd0 >> n_struct_4_state_32) $stop; + x <<= n_struct_4_state_32; + n_struct_4_state_32++; + endfunction + + int n_struct_4_state_33 = 0; + function void e_struct_4_state_33(inout struct_4_state_33 x); + $display("e_struct_4_state_33 %1d", n_struct_4_state_33); + if (x !== ~33'd0 >> n_struct_4_state_33) $stop; + x <<= n_struct_4_state_33; + n_struct_4_state_33++; + endfunction + + int n_struct_4_state_64 = 0; + function void e_struct_4_state_64(inout struct_4_state_64 x); + $display("e_struct_4_state_64 %1d", n_struct_4_state_64); + if (x !== ~64'd0 >> n_struct_4_state_64) $stop; + x <<= n_struct_4_state_64; + n_struct_4_state_64++; + endfunction + + int n_struct_4_state_65 = 0; + function void e_struct_4_state_65(inout struct_4_state_65 x); + $display("e_struct_4_state_65 %1d", n_struct_4_state_65); + if (x !== ~65'd0 >> n_struct_4_state_65) $stop; + x <<= n_struct_4_state_65; + n_struct_4_state_65++; + endfunction + + int n_struct_4_state_128 = 0; + function void e_struct_4_state_128(inout struct_4_state_128 x); + $display("e_struct_4_state_128 %1d", n_struct_4_state_128); + if (x !== ~128'd0 >> n_struct_4_state_128) $stop; + x <<= n_struct_4_state_128; + n_struct_4_state_128++; + endfunction + + // 4-state packed unions + int n_union_4_state_1 = 0; + function void e_union_4_state_1(inout union_4_state_1 x); + $display("e_union_4_state_1 %1d", n_union_4_state_1); + if (x !== n_union_4_state_1[0]) $stop; + x = ~x; + n_union_4_state_1++; + endfunction + + int n_union_4_state_32 = 0; + function void e_union_4_state_32(inout union_4_state_32 x); + $display("e_union_4_state_32 %1d", n_union_4_state_32); + if (x !== ~32'd0 >> n_union_4_state_32) $stop; + x <<= n_union_4_state_32; + n_union_4_state_32++; + endfunction + + int n_union_4_state_33 = 0; + function void e_union_4_state_33(inout union_4_state_33 x); + $display("e_union_4_state_33 %1d", n_union_4_state_33); + if (x !== ~33'd0 >> n_union_4_state_33) $stop; + x <<= n_union_4_state_33; + n_union_4_state_33++; + endfunction + + int n_union_4_state_64 = 0; + function void e_union_4_state_64(inout union_4_state_64 x); + $display("e_union_4_state_64 %1d", n_union_4_state_64); + if (x !== ~64'd0 >> n_union_4_state_64) $stop; + x <<= n_union_4_state_64; + n_union_4_state_64++; + endfunction + + int n_union_4_state_65 = 0; + function void e_union_4_state_65(inout union_4_state_65 x); + $display("e_union_4_state_65 %1d", n_union_4_state_65); + if (x !== ~65'd0 >> n_union_4_state_65) $stop; + x <<= n_union_4_state_65; + n_union_4_state_65++; + endfunction + + int n_union_4_state_128 = 0; + function void e_union_4_state_128(inout union_4_state_128 x); + $display("e_union_4_state_128 %1d", n_union_4_state_128); + if (x !== ~128'd0 >> n_union_4_state_128) $stop; + x <<= n_union_4_state_128; + n_union_4_state_128++; + endfunction + + //====================================================================== + // Invoke all functions 3 times (they have side effects) + //====================================================================== + + import "DPI-C" context function void check_exports(); + + initial begin + for (int i = 0 ; i < 3; i++) begin + // Check the imports + + byte x_byte; + byte unsigned x_byte_unsigned; + shortint x_shortint; + shortint unsigned x_shortint_unsigned; + int x_int; + int unsigned x_int_unsigned; + longint x_longint; + longint unsigned x_longint_unsigned; +`ifndef NO_TIME + time x_time; +`endif +`ifndef NO_INTEGER + integer x_integer; +`endif + real x_real; +`ifndef NO_SHORTREAL + shortreal x_shortreal; +`endif + chandle x_chandle; + string x_string; + bit x_bit; + logic x_logic; + + byte_t x_byte_t; + byte_unsigned_t x_byte_unsigned_t; + shortint_t x_shortint_t; + shortint_unsigned_t x_shortint_unsigned_t; + int_t x_int_t; + int_unsigned_t x_int_unsigned_t; + longint_t x_longint_t; + longint_unsigned_t x_longint_unsigned_t; +`ifndef NO_TIME + time_t x_time_t; +`endif +`ifndef NO_INTEGER + integer_t x_integer_t; +`endif + real_t x_real_t; +`ifndef NO_SHORTREAL + shortreal_t x_shortreal_t; +`endif + chandle_t x_chandle_t; + string_t x_string_t; + bit_t x_bit_t; + logic_t x_logic_t; + + bit [ 0:0] x_bit_1; + bit [ 31:0] x_bit_32; + bit [ 32:0] x_bit_33; + bit [ 63:0] x_bit_64; + bit [ 64:0] x_bit_65; + bit [127:0] x_bit_128; + + struct_2_state_1 x_struct_2_state_1; + struct_2_state_32 x_struct_2_state_32; + struct_2_state_33 x_struct_2_state_33; + struct_2_state_64 x_struct_2_state_64; + struct_2_state_65 x_struct_2_state_65; + struct_2_state_128 x_struct_2_state_128; + + union_2_state_1 x_union_2_state_1; + union_2_state_32 x_union_2_state_32; + union_2_state_33 x_union_2_state_33; + union_2_state_64 x_union_2_state_64; + union_2_state_65 x_union_2_state_65; + union_2_state_128 x_union_2_state_128; + + logic [ 0:0] x_logic_1; + logic [ 31:0] x_logic_32; + logic [ 32:0] x_logic_33; + logic [ 63:0] x_logic_64; + logic [ 64:0] x_logic_65; + logic [127:0] x_logic_128; + + struct_4_state_1 x_struct_4_state_1; + struct_4_state_32 x_struct_4_state_32; + struct_4_state_33 x_struct_4_state_33; + struct_4_state_64 x_struct_4_state_64; + struct_4_state_65 x_struct_4_state_65; + struct_4_state_128 x_struct_4_state_128; + + union_4_state_1 x_union_4_state_1; + union_4_state_32 x_union_4_state_32; + union_4_state_33 x_union_4_state_33; + union_4_state_64 x_union_4_state_64; + union_4_state_65 x_union_4_state_65; + union_4_state_128 x_union_4_state_128; + + // Basic types as per IEEE 1800-2023 35.5.6 + x_byte = 8'd10 - 8'(i); i_byte(x_byte); if (x_byte !== 8'd110 - 8'(i)) $stop; + x_byte_unsigned = 8'd20 - 8'(i); i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd220 - 8'(i)) $stop; + x_shortint = 16'd30 - 16'(i); i_shortint(x_shortint); if (x_shortint !== 16'd330 - 16'(i)) $stop; + x_shortint_unsigned = 16'd40 - 16'(i); i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd440 - 16'(i)) $stop; + x_int = 32'd50 - 32'(i); i_int(x_int); if (x_int !== 32'd550 - 32'(i)) $stop; + x_int_unsigned = 32'd60 - 32'(i); i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd660 - 32'(i)) $stop; + x_longint = 64'd70 - 64'(i); i_longint(x_longint); if (x_longint !== 64'd770 - 64'(i)) $stop; + x_longint_unsigned = 64'd80 - 64'(i); i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd880 - 64'(i)) $stop; +`ifndef NO_TIME + x_time = 64'd90 - 64'(i); i_time(x_time); if (x_time !== 64'd990 - 64'(i)) $stop; +`endif +`ifndef NO_INTEGER + x_integer = 32'd100- 32'(i); i_integer(x_integer); if (x_integer !== 32'd1100- 32'(i)) $stop; +`endif + x_real = -1.0*i - 0.50; i_real(x_real); if (x_real != -100.0 + -1.0*i - 0.50) $stop; +`ifndef NO_SHORTREAL + x_shortreal = -1.0*i - 0.25; i_shortreal(x_shortreal); if (x_shortreal != -200.0 + -1.0*i - 0.25) $stop; +`endif + if (~i[0]) begin + x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; + x_string = "Hello"; i_string(x_string); if (x_string != "Good") $stop; end else begin - if (x !== `NULL) $stop; + x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle === `NULL) $stop; + x_string = "World"; i_string(x_string); if (x_string != "Bye" ) $stop; end - x = `NULL; - n_chandle++; - endfunction + x_bit = ~i[0]; i_bit(x_bit); if (x_bit !== i[0]) $stop; + x_logic = i[0]; i_logic(x_logic); if (x_logic !== ~i[0]) $stop; - int n_string = 0; - function void e_string(inout string x); - $display("e_string %1d", n_string); - if (!n_string[0]) begin - if (x != "Good") $stop; - x = "Hello"; + // Basic types via typedefs + x_byte_t = 8'd10 - 8'(2*i); i_byte_t(x_byte_t); if (x_byte_t !== 8'd111 - 8'(2*i)) $stop; + x_byte_unsigned_t = 8'd20 - 8'(2*i); i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd222 - 8'(2*i)) $stop; + x_shortint_t = 16'd30 - 16'(2*i); i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd333 - 16'(2*i)) $stop; + x_shortint_unsigned_t = 16'd40 - 16'(2*i); i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd444 - 16'(2*i)) $stop; + x_int_t = 32'd50 - 32'(2*i); i_int_t(x_int_t); if (x_int_t !== 32'd555 - 32'(2*i)) $stop; + x_int_unsigned_t = 32'd60 - 32'(2*i); i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd666 - 32'(2*i)) $stop; + x_longint_t = 64'd70 - 64'(2*i); i_longint_t(x_longint_t); if (x_longint_t !== 64'd777 - 64'(2*i)) $stop; + x_longint_unsigned_t = 64'd80 - 64'(2*i); i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd888 - 64'(2*i)) $stop; +`ifndef NO_TIME + x_time_t = 64'd90 - 64'(2*i); i_time_t(x_time_t); if (x_time_t !== 64'd999 - 64'(2*i)) $stop; +`endif +`ifndef NO_INTEGER + x_integer_t = 32'd100- 32'(2*i); i_integer_t(x_integer_t); if (x_integer_t !== 32'd1101- 32'(2*i)) $stop; +`endif + x_real_t = -1.0*(2*i) - 0.50; i_real_t(x_real_t); if (x_real_t != -111.0 + -1.0*(2*i) - 0.50) $stop; +`ifndef NO_SHORTREAL + x_shortreal_t = -1.0*(2*i) - 0.25; i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -222.0 + -1.0*(2*i) - 0.25) $stop; +`endif + if (~i[0]) begin + x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; + x_string_t = "World"; i_string_t(x_string_t); if (x_string_t != "Bye") $stop; end else begin - if (x != "Bye") $stop; - x = "World"; + x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; + x_string_t = "Hello"; i_string_t(x_string_t); if (x_string_t != "Good") $stop; end - n_string++; - endfunction - - int n_bit = 0; - function void e_bit(inout bit x); - $display("e_bit %1d", n_bit); - if (x !== n_bit[0]) $stop; - x = ~x; - n_bit++; - endfunction - - int n_logic = 0; - function void e_logic(inout logic x); - $display("e_logic %1d", n_logic); - if (x !== ~n_logic[0]) $stop; - x = ~x; - n_logic++; - endfunction - - // Basic types via typedefs - byte_t n_byte_t = 0; - function void e_byte_t(inout byte_t x); - if (x !== 8'd10 + n_byte_t) $stop; - x += 8'd101; - n_byte_t += 2; - endfunction - - byte n_byte_unsigned_t = 0; - function void e_byte_unsigned_t(inout byte_unsigned_t x); - if (x !== 8'd20 + n_byte_unsigned_t) $stop; - x += 8'd202; - n_byte_unsigned_t += 2; - endfunction - - shortint_t n_shortint_t = 0; - function void e_shortint_t(inout shortint_t x); - if (x !== 16'd30 + n_shortint_t) $stop; - x += 16'd303; - n_shortint_t += 2; - endfunction - - shortint n_shortint_unsigned_t = 0; - function void e_shortint_unsigned_t(inout shortint_unsigned_t x); - if (x !== 16'd40 + n_shortint_unsigned_t) $stop; - x += 16'd404; - n_shortint_unsigned_t += 2; - endfunction - - int_t n_int_t = 0; - function void e_int_t(inout int_t x); - if (x !== 32'd50 + n_int_t) $stop; - x += 32'd505; - n_int_t += 2; - endfunction - - int n_int_unsigned_t = 0; - function void e_int_unsigned_t(inout int_unsigned_t x); - if (x !== 32'd60 + n_int_unsigned_t) $stop; - x += 32'd606; - n_int_unsigned_t += 2; - endfunction - - longint_t n_longint_t = 0; - function void e_longint_t(inout longint_t x); - if (x !== 64'd70 + n_longint_t) $stop; - x += 64'd707; - n_longint_t += 2; - endfunction - - longint n_longint_unsigned_t = 0; - function void e_longint_unsigned_t(inout longint_unsigned_t x); - if (x !== 64'd80 + n_longint_unsigned_t) $stop; - x += 64'd808; - n_longint_unsigned_t += 2; - endfunction - -`ifndef NO_TIME - longint n_time_t = 0; - function void e_time_t(inout time_t x); - if (x !== 64'd90 + n_time_t) $stop; - x += 64'd909; - n_time_t += 2; - endfunction -`endif - -`ifndef NO_INTEGER - int n_integer_t = 0; - function void e_integer_t(inout integer_t x); - if (x !== 32'd100 + n_integer_t) $stop; - x += 32'd1001; - n_integer_t += 2; - endfunction -`endif - - int n_real_t = 0; - function void e_real_t(inout real_t x); - if (x != real'(2*n_real_t + 1) / 2.0) $stop; - x += 111.0; - n_real_t += 2; - endfunction - -`ifndef NO_SHORTREAL - int n_shortreal_t = 0; - function void e_shortreal_t(inout shortreal_t x); - if (x != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; - x += 222.0; - n_shortreal_t += 2; - endfunction -`endif - - int n_chandle_t = 0; - function void e_chandle_t(inout chandle_t x); - $display("e_chandle_t %1d", n_chandle_t); - if (!n_chandle_t[0]) begin - if (x !== `NULL) $stop; - end else begin - if (x === `NULL) $stop; - end - x = `NULL; - n_chandle_t++; - endfunction - - int n_string_t = 0; - function void e_string_t(inout string_t x); - $display("e_string_t %1d", n_string_t); - if (!n_string_t[0]) begin - if (x != "Bye") $stop; - x = "World"; - end else begin - if (x != "Good") $stop; - x = "Hello"; - end - n_string_t++; - endfunction - - int n_bit_t = 0; - function void e_bit_t(inout bit_t x); - $display("e_bit_t %1d", n_bit_t); - if (x !== n_bit_t[0]) $stop; - x = ~x; - n_bit_t++; - endfunction - - int n_logic_t = 0; - function void e_logic_t(inout logic_t x); - $display("e_logic_t %1d", n_logic_t); - if (x !== ~n_logic_t[0]) $stop; - x = ~x; - n_logic_t++; - endfunction - - // 2-state packed arrays - int n_array_2_state_1 = 0; - function void e_array_2_state_1(inout bit [ 0:0] x); - $display("e_array_2_state_1 %1d", n_array_2_state_1); - if (x !== n_array_2_state_1[0]) $stop; - x = ~x; - n_array_2_state_1++; - endfunction - - int n_array_2_state_32 = 0; - function void e_array_2_state_32(inout bit [31:0] x); - $display("e_array_2_state_32 %1d", n_array_2_state_32); - if (x !== ~32'd0 >> n_array_2_state_32) $stop; - x <<= n_array_2_state_32; - n_array_2_state_32++; - endfunction - - int n_array_2_state_33 = 0; - function void e_array_2_state_33(inout bit [32:0] x); - $display("e_array_2_state_33 %1d", n_array_2_state_33); - if (x !== ~33'd0 >> n_array_2_state_33) $stop; - x <<= n_array_2_state_33; - n_array_2_state_33++; - endfunction - - int n_array_2_state_64 = 0; - function void e_array_2_state_64(inout bit [63:0] x); - $display("e_array_2_state_64 %1d", n_array_2_state_64); - if (x !== ~64'd0 >> n_array_2_state_64) $stop; - x <<= n_array_2_state_64; - n_array_2_state_64++; - endfunction - - int n_array_2_state_65 = 0; - function void e_array_2_state_65(inout bit [64:0] x); - $display("e_array_2_state_65 %1d", n_array_2_state_65); - if (x !== ~65'd0 >> n_array_2_state_65) $stop; - x <<= n_array_2_state_65; - n_array_2_state_65++; - endfunction - - int n_array_2_state_128 = 0; - function void e_array_2_state_128(inout bit [127:0] x); - $display("e_array_2_state_128 %1d", n_array_2_state_128); - if (x !== ~128'd0 >> n_array_2_state_128) $stop; - x <<= n_array_2_state_128; - n_array_2_state_128++; - endfunction - - // 2-state packed structures - int n_struct_2_state_1 = 0; - function void e_struct_2_state_1(inout struct_2_state_1 x); - $display("e_struct_2_state_1 %1d", n_struct_2_state_1); - if (x !== n_struct_2_state_1[0]) $stop; - x = ~x; - n_struct_2_state_1++; - endfunction - - int n_struct_2_state_32 = 0; - function void e_struct_2_state_32(inout struct_2_state_32 x); - $display("e_struct_2_state_32 %1d", n_struct_2_state_32); - if (x !== ~32'd0 >> n_struct_2_state_32) $stop; - x <<= n_struct_2_state_32; - n_struct_2_state_32++; - endfunction - - int n_struct_2_state_33 = 0; - function void e_struct_2_state_33(inout struct_2_state_33 x); - $display("e_struct_2_state_33 %1d", n_struct_2_state_33); - if (x !== ~33'd0 >> n_struct_2_state_33) $stop; - x <<= n_struct_2_state_33; - n_struct_2_state_33++; - endfunction - - int n_struct_2_state_64 = 0; - function void e_struct_2_state_64(inout struct_2_state_64 x); - $display("e_struct_2_state_64 %1d", n_struct_2_state_64); - if (x !== ~64'd0 >> n_struct_2_state_64) $stop; - x <<= n_struct_2_state_64; - n_struct_2_state_64++; - endfunction - - int n_struct_2_state_65 = 0; - function void e_struct_2_state_65(inout struct_2_state_65 x); - $display("e_struct_2_state_65 %1d", n_struct_2_state_65); - if (x !== ~65'd0 >> n_struct_2_state_65) $stop; - x <<= n_struct_2_state_65; - n_struct_2_state_65++; - endfunction - - int n_struct_2_state_128 = 0; - function void e_struct_2_state_128(inout struct_2_state_128 x); - $display("e_struct_2_state_128 %1d", n_struct_2_state_128); - if (x !== ~128'd0 >> n_struct_2_state_128) $stop; - x <<= n_struct_2_state_128; - n_struct_2_state_128++; - endfunction - - // 2-state packed unions - int n_union_2_state_1 = 0; - function void e_union_2_state_1(inout union_2_state_1 x); - $display("e_union_2_state_1 %1d", n_union_2_state_1); - if (x !== n_union_2_state_1[0]) $stop; - x = ~x; - n_union_2_state_1++; - endfunction - - int n_union_2_state_32 = 0; - function void e_union_2_state_32(inout union_2_state_32 x); - $display("e_union_2_state_32 %1d", n_union_2_state_32); - if (x !== ~32'd0 >> n_union_2_state_32) $stop; - x <<= n_union_2_state_32; - n_union_2_state_32++; - endfunction - - int n_union_2_state_33 = 0; - function void e_union_2_state_33(inout union_2_state_33 x); - $display("e_union_2_state_33 %1d", n_union_2_state_33); - if (x !== ~33'd0 >> n_union_2_state_33) $stop; - x <<= n_union_2_state_33; - n_union_2_state_33++; - endfunction - - int n_union_2_state_64 = 0; - function void e_union_2_state_64(inout union_2_state_64 x); - $display("e_union_2_state_64 %1d", n_union_2_state_64); - if (x !== ~64'd0 >> n_union_2_state_64) $stop; - x <<= n_union_2_state_64; - n_union_2_state_64++; - endfunction - - int n_union_2_state_65 = 0; - function void e_union_2_state_65(inout union_2_state_65 x); - $display("e_union_2_state_65 %1d", n_union_2_state_65); - if (x !== ~65'd0 >> n_union_2_state_65) $stop; - x <<= n_union_2_state_65; - n_union_2_state_65++; - endfunction - - int n_union_2_state_128 = 0; - function void e_union_2_state_128(inout union_2_state_128 x); - $display("e_union_2_state_128 %1d", n_union_2_state_128); - if (x !== ~128'd0 >> n_union_2_state_128) $stop; - x <<= n_union_2_state_128; - n_union_2_state_128++; - endfunction - - // 4-state packed arrays - int n_array_4_state_1 = 0; - function void e_array_4_state_1(inout logic [ 0:0] x); - $display("e_array_4_state_1 %1d", n_array_4_state_1); - if (x !== n_array_4_state_1[0]) $stop; - x = ~x; - n_array_4_state_1++; - endfunction - - int n_array_4_state_32 = 0; - function void e_array_4_state_32(inout logic [31:0] x); - $display("e_array_4_state_32 %1d", n_array_4_state_32); - if (x !== ~32'd0 >> n_array_4_state_32) $stop; - x <<= n_array_4_state_32; - n_array_4_state_32++; - endfunction - - int n_array_4_state_33 = 0; - function void e_array_4_state_33(inout logic [32:0] x); - $display("e_array_4_state_33 %1d", n_array_4_state_33); - if (x !== ~33'd0 >> n_array_4_state_33) $stop; - x <<= n_array_4_state_33; - n_array_4_state_33++; - endfunction - - int n_array_4_state_64 = 0; - function void e_array_4_state_64(inout logic [63:0] x); - $display("e_array_4_state_64 %1d", n_array_4_state_64); - if (x !== ~64'd0 >> n_array_4_state_64) $stop; - x <<= n_array_4_state_64; - n_array_4_state_64++; - endfunction - - int n_array_4_state_65 = 0; - function void e_array_4_state_65(inout logic [64:0] x); - $display("e_array_4_state_65 %1d", n_array_4_state_65); - if (x !== ~65'd0 >> n_array_4_state_65) $stop; - x <<= n_array_4_state_65; - n_array_4_state_65++; - endfunction - - int n_array_4_state_128 = 0; - function void e_array_4_state_128(inout logic [127:0] x); - $display("e_array_4_state_128 %1d", n_array_4_state_128); - if (x !== ~128'd0 >> n_array_4_state_128) $stop; - x <<= n_array_4_state_128; - n_array_4_state_128++; - endfunction - - // 4-state packed structures - int n_struct_4_state_1 = 0; - function void e_struct_4_state_1(inout struct_4_state_1 x); - $display("e_struct_4_state_1 %1d", n_struct_4_state_1); - if (x !== n_struct_4_state_1[0]) $stop; - x = ~x; - n_struct_4_state_1++; - endfunction - - int n_struct_4_state_32 = 0; - function void e_struct_4_state_32(inout struct_4_state_32 x); - $display("e_struct_4_state_32 %1d", n_struct_4_state_32); - if (x !== ~32'd0 >> n_struct_4_state_32) $stop; - x <<= n_struct_4_state_32; - n_struct_4_state_32++; - endfunction - - int n_struct_4_state_33 = 0; - function void e_struct_4_state_33(inout struct_4_state_33 x); - $display("e_struct_4_state_33 %1d", n_struct_4_state_33); - if (x !== ~33'd0 >> n_struct_4_state_33) $stop; - x <<= n_struct_4_state_33; - n_struct_4_state_33++; - endfunction - - int n_struct_4_state_64 = 0; - function void e_struct_4_state_64(inout struct_4_state_64 x); - $display("e_struct_4_state_64 %1d", n_struct_4_state_64); - if (x !== ~64'd0 >> n_struct_4_state_64) $stop; - x <<= n_struct_4_state_64; - n_struct_4_state_64++; - endfunction - - int n_struct_4_state_65 = 0; - function void e_struct_4_state_65(inout struct_4_state_65 x); - $display("e_struct_4_state_65 %1d", n_struct_4_state_65); - if (x !== ~65'd0 >> n_struct_4_state_65) $stop; - x <<= n_struct_4_state_65; - n_struct_4_state_65++; - endfunction - - int n_struct_4_state_128 = 0; - function void e_struct_4_state_128(inout struct_4_state_128 x); - $display("e_struct_4_state_128 %1d", n_struct_4_state_128); - if (x !== ~128'd0 >> n_struct_4_state_128) $stop; - x <<= n_struct_4_state_128; - n_struct_4_state_128++; - endfunction - - // 4-state packed unions - int n_union_4_state_1 = 0; - function void e_union_4_state_1(inout union_4_state_1 x); - $display("e_union_4_state_1 %1d", n_union_4_state_1); - if (x !== n_union_4_state_1[0]) $stop; - x = ~x; - n_union_4_state_1++; - endfunction - - int n_union_4_state_32 = 0; - function void e_union_4_state_32(inout union_4_state_32 x); - $display("e_union_4_state_32 %1d", n_union_4_state_32); - if (x !== ~32'd0 >> n_union_4_state_32) $stop; - x <<= n_union_4_state_32; - n_union_4_state_32++; - endfunction - - int n_union_4_state_33 = 0; - function void e_union_4_state_33(inout union_4_state_33 x); - $display("e_union_4_state_33 %1d", n_union_4_state_33); - if (x !== ~33'd0 >> n_union_4_state_33) $stop; - x <<= n_union_4_state_33; - n_union_4_state_33++; - endfunction - - int n_union_4_state_64 = 0; - function void e_union_4_state_64(inout union_4_state_64 x); - $display("e_union_4_state_64 %1d", n_union_4_state_64); - if (x !== ~64'd0 >> n_union_4_state_64) $stop; - x <<= n_union_4_state_64; - n_union_4_state_64++; - endfunction - - int n_union_4_state_65 = 0; - function void e_union_4_state_65(inout union_4_state_65 x); - $display("e_union_4_state_65 %1d", n_union_4_state_65); - if (x !== ~65'd0 >> n_union_4_state_65) $stop; - x <<= n_union_4_state_65; - n_union_4_state_65++; - endfunction - - int n_union_4_state_128 = 0; - function void e_union_4_state_128(inout union_4_state_128 x); - $display("e_union_4_state_128 %1d", n_union_4_state_128); - if (x !== ~128'd0 >> n_union_4_state_128) $stop; - x <<= n_union_4_state_128; - n_union_4_state_128++; - endfunction - - //====================================================================== - // Invoke all functions 3 times (they have side effects) - //====================================================================== - - import "DPI-C" context function void check_exports(); - - initial begin - for (int i = 0 ; i < 3; i++) begin - // Check the imports - - byte x_byte; - byte unsigned x_byte_unsigned; - shortint x_shortint; - shortint unsigned x_shortint_unsigned; - int x_int; - int unsigned x_int_unsigned; - longint x_longint; - longint unsigned x_longint_unsigned; -`ifndef NO_TIME - time x_time; -`endif -`ifndef NO_INTEGER - integer x_integer; -`endif - real x_real; -`ifndef NO_SHORTREAL - shortreal x_shortreal; -`endif - chandle x_chandle; - string x_string; - bit x_bit; - logic x_logic; - - byte_t x_byte_t; - byte_unsigned_t x_byte_unsigned_t; - shortint_t x_shortint_t; - shortint_unsigned_t x_shortint_unsigned_t; - int_t x_int_t; - int_unsigned_t x_int_unsigned_t; - longint_t x_longint_t; - longint_unsigned_t x_longint_unsigned_t; -`ifndef NO_TIME - time_t x_time_t; -`endif -`ifndef NO_INTEGER - integer_t x_integer_t; -`endif - real_t x_real_t; -`ifndef NO_SHORTREAL - shortreal_t x_shortreal_t; -`endif - chandle_t x_chandle_t; - string_t x_string_t; - bit_t x_bit_t; - logic_t x_logic_t; - - bit [ 0:0] x_bit_1; - bit [ 31:0] x_bit_32; - bit [ 32:0] x_bit_33; - bit [ 63:0] x_bit_64; - bit [ 64:0] x_bit_65; - bit [127:0] x_bit_128; - - struct_2_state_1 x_struct_2_state_1; - struct_2_state_32 x_struct_2_state_32; - struct_2_state_33 x_struct_2_state_33; - struct_2_state_64 x_struct_2_state_64; - struct_2_state_65 x_struct_2_state_65; - struct_2_state_128 x_struct_2_state_128; - - union_2_state_1 x_union_2_state_1; - union_2_state_32 x_union_2_state_32; - union_2_state_33 x_union_2_state_33; - union_2_state_64 x_union_2_state_64; - union_2_state_65 x_union_2_state_65; - union_2_state_128 x_union_2_state_128; - - logic [ 0:0] x_logic_1; - logic [ 31:0] x_logic_32; - logic [ 32:0] x_logic_33; - logic [ 63:0] x_logic_64; - logic [ 64:0] x_logic_65; - logic [127:0] x_logic_128; - - struct_4_state_1 x_struct_4_state_1; - struct_4_state_32 x_struct_4_state_32; - struct_4_state_33 x_struct_4_state_33; - struct_4_state_64 x_struct_4_state_64; - struct_4_state_65 x_struct_4_state_65; - struct_4_state_128 x_struct_4_state_128; - - union_4_state_1 x_union_4_state_1; - union_4_state_32 x_union_4_state_32; - union_4_state_33 x_union_4_state_33; - union_4_state_64 x_union_4_state_64; - union_4_state_65 x_union_4_state_65; - union_4_state_128 x_union_4_state_128; - - // Basic types as per IEEE 1800-2023 35.5.6 - x_byte = 8'd10 - 8'(i); i_byte(x_byte); if (x_byte !== 8'd110 - 8'(i)) $stop; - x_byte_unsigned = 8'd20 - 8'(i); i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd220 - 8'(i)) $stop; - x_shortint = 16'd30 - 16'(i); i_shortint(x_shortint); if (x_shortint !== 16'd330 - 16'(i)) $stop; - x_shortint_unsigned = 16'd40 - 16'(i); i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd440 - 16'(i)) $stop; - x_int = 32'd50 - 32'(i); i_int(x_int); if (x_int !== 32'd550 - 32'(i)) $stop; - x_int_unsigned = 32'd60 - 32'(i); i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd660 - 32'(i)) $stop; - x_longint = 64'd70 - 64'(i); i_longint(x_longint); if (x_longint !== 64'd770 - 64'(i)) $stop; - x_longint_unsigned = 64'd80 - 64'(i); i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd880 - 64'(i)) $stop; -`ifndef NO_TIME - x_time = 64'd90 - 64'(i); i_time(x_time); if (x_time !== 64'd990 - 64'(i)) $stop; -`endif -`ifndef NO_INTEGER - x_integer = 32'd100- 32'(i); i_integer(x_integer); if (x_integer !== 32'd1100- 32'(i)) $stop; -`endif - x_real = -1.0*i - 0.50; i_real(x_real); if (x_real != -100.0 + -1.0*i - 0.50) $stop; -`ifndef NO_SHORTREAL - x_shortreal = -1.0*i - 0.25; i_shortreal(x_shortreal); if (x_shortreal != -200.0 + -1.0*i - 0.25) $stop; -`endif - if (~i[0]) begin - x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; - x_string = "Hello"; i_string(x_string); if (x_string != "Good") $stop; - end else begin - x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle === `NULL) $stop; - x_string = "World"; i_string(x_string); if (x_string != "Bye" ) $stop; - end - x_bit = ~i[0]; i_bit(x_bit); if (x_bit !== i[0]) $stop; - x_logic = i[0]; i_logic(x_logic); if (x_logic !== ~i[0]) $stop; - - // Basic types via typedefs - x_byte_t = 8'd10 - 8'(2*i); i_byte_t(x_byte_t); if (x_byte_t !== 8'd111 - 8'(2*i)) $stop; - x_byte_unsigned_t = 8'd20 - 8'(2*i); i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd222 - 8'(2*i)) $stop; - x_shortint_t = 16'd30 - 16'(2*i); i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd333 - 16'(2*i)) $stop; - x_shortint_unsigned_t = 16'd40 - 16'(2*i); i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd444 - 16'(2*i)) $stop; - x_int_t = 32'd50 - 32'(2*i); i_int_t(x_int_t); if (x_int_t !== 32'd555 - 32'(2*i)) $stop; - x_int_unsigned_t = 32'd60 - 32'(2*i); i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd666 - 32'(2*i)) $stop; - x_longint_t = 64'd70 - 64'(2*i); i_longint_t(x_longint_t); if (x_longint_t !== 64'd777 - 64'(2*i)) $stop; - x_longint_unsigned_t = 64'd80 - 64'(2*i); i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd888 - 64'(2*i)) $stop; -`ifndef NO_TIME - x_time_t = 64'd90 - 64'(2*i); i_time_t(x_time_t); if (x_time_t !== 64'd999 - 64'(2*i)) $stop; -`endif -`ifndef NO_INTEGER - x_integer_t = 32'd100- 32'(2*i); i_integer_t(x_integer_t); if (x_integer_t !== 32'd1101- 32'(2*i)) $stop; -`endif - x_real_t = -1.0*(2*i) - 0.50; i_real_t(x_real_t); if (x_real_t != -111.0 + -1.0*(2*i) - 0.50) $stop; -`ifndef NO_SHORTREAL - x_shortreal_t = -1.0*(2*i) - 0.25; i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -222.0 + -1.0*(2*i) - 0.25) $stop; -`endif - if (~i[0]) begin - x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; - x_string_t = "World"; i_string_t(x_string_t); if (x_string_t != "Bye") $stop; - end else begin - x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; - x_string_t = "Hello"; i_string_t(x_string_t); if (x_string_t != "Good") $stop; - end - x_bit_t = ~i[0]; i_bit_t(x_bit_t); if (x_bit_t !== i[0]) $stop; - x_logic_t = i[0]; i_logic_t(x_logic_t); if (x_logic_t !== ~i[0]) $stop; - - // 2-state packed arrays - x_bit_1 = ~i[0]; i_array_2_state_1(x_bit_1); if (x_bit_1 !== i[0] ) $stop; - x_bit_32 = ~32'd0 << i; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 >> i) $stop; - x_bit_33 = ~33'd0 << i; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 >> i) begin $display("%d %x %0x", i, x_bit_33, ~33'd0 >> i); $stop; end - x_bit_64 = ~64'd0 << i; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 >> i) $stop; - x_bit_65 = ~65'd0 << i; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 >> i) $stop; - x_bit_128 = ~128'd0<< i; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0>> i) $stop; - - // 2-state packed structures - x_struct_2_state_1 = ~i[0]; i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== i[0] ) $stop; - x_struct_2_state_32 = ~32'd0 << i; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 >> i) $stop; - x_struct_2_state_33 = ~33'd0 << i; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 >> i) $stop; - x_struct_2_state_64 = ~64'd0 << i; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 >> i) $stop; - x_struct_2_state_65 = ~65'd0 << i; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 >> i) $stop; - x_struct_2_state_128= ~128'd0<< i; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128!== ~128'd0>> i) $stop; - - // 2-state packed unions - x_union_2_state_1 = ~i[0]; i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== i[0] ) $stop; - x_union_2_state_32 = ~32'd0 << i; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 >> i) $stop; - x_union_2_state_33 = ~33'd0 << i; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 >> i) $stop; - x_union_2_state_64 = ~64'd0 << i; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 >> i) $stop; - x_union_2_state_65 = ~65'd0 << i; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 >> i) $stop; - x_union_2_state_128 = ~128'd0<< i; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0>> i) $stop; - - // 4-state packed arrays - x_logic_1 = ~i[0]; i_array_4_state_1(x_logic_1); if (x_logic_1 !== i[0] ) $stop; - x_logic_32 = ~32'd0 << i; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 >> i) $stop; - x_logic_33 = ~33'd0 << i; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 >> i) $stop; - x_logic_64 = ~64'd0 << i; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 >> i) $stop; - x_logic_65 = ~65'd0 << i; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 >> i) $stop; - x_logic_128 = ~128'd0<< i; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0>> i) $stop; - - // 4-state packed structures - x_struct_4_state_1 = ~i[0]; i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== i[0] ) $stop; - x_struct_4_state_32 = ~32'd0 << i; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 >> i) $stop; - x_struct_4_state_33 = ~33'd0 << i; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 >> i) $stop; - x_struct_4_state_64 = ~64'd0 << i; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 >> i) $stop; - x_struct_4_state_65 = ~65'd0 << i; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 >> i) $stop; - x_struct_4_state_128= ~128'd0<< i; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128!== ~128'd0>> i) $stop; - - // 4-state packed unions - x_union_4_state_1 = ~i[0]; i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== i[0] ) $stop; - x_union_4_state_32 = ~32'd0 << i; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 >> i) $stop; - x_union_4_state_33 = ~33'd0 << i; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 >> i) $stop; - x_union_4_state_64 = ~64'd0 << i; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 >> i) $stop; - x_union_4_state_65 = ~65'd0 << i; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 >> i) $stop; - x_union_4_state_128 = ~128'd0<< i; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0>> i) $stop; - - // Check the exports - check_exports(); - end - - $write("*-* All Finished *-*\n"); - $finish; - end + x_bit_t = ~i[0]; i_bit_t(x_bit_t); if (x_bit_t !== i[0]) $stop; + x_logic_t = i[0]; i_logic_t(x_logic_t); if (x_logic_t !== ~i[0]) $stop; + + // 2-state packed arrays + x_bit_1 = ~i[0]; i_array_2_state_1(x_bit_1); if (x_bit_1 !== i[0] ) $stop; + x_bit_32 = ~32'd0 << i; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 >> i) $stop; + x_bit_33 = ~33'd0 << i; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 >> i) begin $display("%d %x %0x", i, x_bit_33, ~33'd0 >> i); $stop; end + x_bit_64 = ~64'd0 << i; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 >> i) $stop; + x_bit_65 = ~65'd0 << i; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 >> i) $stop; + x_bit_128 = ~128'd0<< i; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0>> i) $stop; + + // 2-state packed structures + x_struct_2_state_1 = ~i[0]; i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== i[0] ) $stop; + x_struct_2_state_32 = ~32'd0 << i; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 >> i) $stop; + x_struct_2_state_33 = ~33'd0 << i; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 >> i) $stop; + x_struct_2_state_64 = ~64'd0 << i; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 >> i) $stop; + x_struct_2_state_65 = ~65'd0 << i; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 >> i) $stop; + x_struct_2_state_128= ~128'd0<< i; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128!== ~128'd0>> i) $stop; + + // 2-state packed unions + x_union_2_state_1 = ~i[0]; i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== i[0] ) $stop; + x_union_2_state_32 = ~32'd0 << i; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 >> i) $stop; + x_union_2_state_33 = ~33'd0 << i; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 >> i) $stop; + x_union_2_state_64 = ~64'd0 << i; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 >> i) $stop; + x_union_2_state_65 = ~65'd0 << i; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 >> i) $stop; + x_union_2_state_128 = ~128'd0<< i; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0>> i) $stop; + + // 4-state packed arrays + x_logic_1 = ~i[0]; i_array_4_state_1(x_logic_1); if (x_logic_1 !== i[0] ) $stop; + x_logic_32 = ~32'd0 << i; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 >> i) $stop; + x_logic_33 = ~33'd0 << i; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 >> i) $stop; + x_logic_64 = ~64'd0 << i; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 >> i) $stop; + x_logic_65 = ~65'd0 << i; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 >> i) $stop; + x_logic_128 = ~128'd0<< i; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0>> i) $stop; + + // 4-state packed structures + x_struct_4_state_1 = ~i[0]; i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== i[0] ) $stop; + x_struct_4_state_32 = ~32'd0 << i; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 >> i) $stop; + x_struct_4_state_33 = ~33'd0 << i; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 >> i) $stop; + x_struct_4_state_64 = ~64'd0 << i; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 >> i) $stop; + x_struct_4_state_65 = ~65'd0 << i; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 >> i) $stop; + x_struct_4_state_128= ~128'd0<< i; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128!== ~128'd0>> i) $stop; + + // 4-state packed unions + x_union_4_state_1 = ~i[0]; i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== i[0] ) $stop; + x_union_4_state_32 = ~32'd0 << i; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 >> i) $stop; + x_union_4_state_33 = ~33'd0 << i; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 >> i) $stop; + x_union_4_state_64 = ~64'd0 << i; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 >> i) $stop; + x_union_4_state_65 = ~65'd0 << i; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 >> i) $stop; + x_union_4_state_128 = ~128'd0<< i; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0>> i) $stop; + + // Check the exports + check_exports(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_arg_inout_unpack.v b/test_regress/t/t_dpi_arg_inout_unpack.v index ef8655245..b42d2a3ce 100644 --- a/test_regress/t/t_dpi_arg_inout_unpack.v +++ b/test_regress/t/t_dpi_arg_inout_unpack.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -34,27 +35,27 @@ `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ - end else begin \ - $display("Mismatch %s expected:%d actual:%d at %d", `"act`", int'(exp), int'(act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ + end else begin \ + $display("Mismatch %s expected:%d actual:%d at %d", `"act`", int'(exp), int'(act), `__LINE__); \ + $stop; \ + end `define CHECK_CHANDLE_VAL(act, exp) if ((act) == (exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ - end else begin \ - $display("Mismatch %s expected:%s but %s at %d", `"act`", \ - (exp) != null ? "null" : "non-null", \ - (act) != null ? "null" : "non-null", `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ + end else begin \ + $display("Mismatch %s expected:%s but %s at %d", `"act`", \ + (exp) != null ? "null" : "non-null", \ + (act) != null ? "null" : "non-null", `__LINE__); \ + $stop; \ + end `define CHECK_STRING_VAL(act, exp) if ((act) == (exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ - end else begin \ - $display("Mismatch %s expected:%s actual:%s at %d", `"act`", (exp), (act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ + end else begin \ + $display("Mismatch %s expected:%s actual:%s at %d", `"act`", (exp), (act), `__LINE__); \ + $stop; \ + end `define UPDATE_VAL(var, val) `CHECK_VAL(var, val); var += 1 @@ -104,11 +105,11 @@ `CHECK_VAL(val[0][0][0], 55) `define CHECK_DOUBLE_VAL(act, exp) if ((act) == (exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display("%s:%f as expected", `"act`", (act)); \ - end else begin \ - $display("Mismatch %s expected:%d actual:%f at %f", `"act`", (exp), (act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display("%s:%f as expected", `"act`", (act)); \ + end else begin \ + $display("Mismatch %s expected:%d actual:%f at %f", `"act`", (exp), (act), `__LINE__); \ + $stop; \ + end `define CHECK_DOUBLE_0D(val) \ `CHECK_DOUBLE_VAL((val), 43.0) @@ -167,1683 +168,1683 @@ module t; - localparam ENABLE_VERBOSE_MESSAGE = 0; + localparam ENABLE_VERBOSE_MESSAGE = 0; - // Legal output argument types for DPI functions + // Legal output argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - typedef byte byte_t; - typedef byte_t byte_array_t[4][3][2]; - typedef byte_t byte_array1_t[1][1][1]; - typedef byte unsigned byte_unsigned_t; - typedef byte_unsigned_t byte_unsigned_array_t[4][3][2]; - typedef byte_unsigned_t byte_unsigned_array1_t[1][1][1]; - typedef shortint shortint_t; - typedef shortint_t shortint_array_t[4][3][2]; - typedef shortint_t shortint_array1_t[1][1][1]; - typedef shortint unsigned shortint_unsigned_t; - typedef shortint_unsigned_t shortint_unsigned_array_t[4][3][2]; - typedef shortint_unsigned_t shortint_unsigned_array1_t[1][1][1]; - typedef int int_t; - typedef int_t int_array_t[4][3][2]; - typedef int_t int_array1_t[1][1][1]; - typedef int unsigned int_unsigned_t; - typedef int_unsigned_t int_unsigned_array_t[4][3][2]; - typedef int_unsigned_t int_unsigned_array1_t[1][1][1]; - typedef longint longint_t; - typedef longint_t longint_array_t[4][3][2]; - typedef longint_t longint_array1_t[1][1][1]; - typedef longint unsigned longint_unsigned_t; - typedef longint_unsigned_t longint_unsigned_array_t[4][3][2]; - typedef longint_unsigned_t longint_unsigned_array1_t[1][1][1]; + typedef byte byte_t; + typedef byte_t byte_array_t[4][3][2]; + typedef byte_t byte_array1_t[1][1][1]; + typedef byte unsigned byte_unsigned_t; + typedef byte_unsigned_t byte_unsigned_array_t[4][3][2]; + typedef byte_unsigned_t byte_unsigned_array1_t[1][1][1]; + typedef shortint shortint_t; + typedef shortint_t shortint_array_t[4][3][2]; + typedef shortint_t shortint_array1_t[1][1][1]; + typedef shortint unsigned shortint_unsigned_t; + typedef shortint_unsigned_t shortint_unsigned_array_t[4][3][2]; + typedef shortint_unsigned_t shortint_unsigned_array1_t[1][1][1]; + typedef int int_t; + typedef int_t int_array_t[4][3][2]; + typedef int_t int_array1_t[1][1][1]; + typedef int unsigned int_unsigned_t; + typedef int_unsigned_t int_unsigned_array_t[4][3][2]; + typedef int_unsigned_t int_unsigned_array1_t[1][1][1]; + typedef longint longint_t; + typedef longint_t longint_array_t[4][3][2]; + typedef longint_t longint_array1_t[1][1][1]; + typedef longint unsigned longint_unsigned_t; + typedef longint_unsigned_t longint_unsigned_array_t[4][3][2]; + typedef longint_unsigned_t longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME - typedef time time_t; - typedef time_t time_array_t[4][3][2]; - typedef time_t time_array1_t[1][1][1]; + typedef time time_t; + typedef time_t time_array_t[4][3][2]; + typedef time_t time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER - typedef integer integer_t; - typedef integer_t integer_array_t[4][3][2]; - typedef integer_t integer_array1_t[1][1][1]; + typedef integer integer_t; + typedef integer_t integer_array_t[4][3][2]; + typedef integer_t integer_array1_t[1][1][1]; `endif - typedef real real_t; - typedef real_t real_array_t[4][3][2]; - typedef real_t real_array1_t[1][1][1]; + typedef real real_t; + typedef real_t real_array_t[4][3][2]; + typedef real_t real_array1_t[1][1][1]; `ifndef NO_SHORTREAL - typedef shortreal shortreal_t; - typedef shortreal_t shortreal_array_t[4][3][2]; - typedef shortreal_t shortreal_array1_t[1][1][1]; + typedef shortreal shortreal_t; + typedef shortreal_t shortreal_array_t[4][3][2]; + typedef shortreal_t shortreal_array1_t[1][1][1]; `endif - typedef chandle chandle_t; - typedef chandle_t chandle_array_t[4][3][2]; - typedef chandle_t chandle_array1_t[1][1][1]; - typedef string string_t; - typedef string_t string_array_t[4][3][2]; - typedef string_t string_array1_t[1][1][1]; - typedef bit bit1_t; - typedef bit1_t bit1_array_t[4][3][2]; - typedef bit1_t bit1_array1_t[1][1][1]; - typedef bit [6:0] bit7_t; - typedef bit7_t bit7_array_t[4][3][2]; - typedef bit7_t bit7_array1_t[1][1][1]; - typedef bit [120:0] bit121_t; - typedef bit121_t bit121_array_t[4][3][2]; - typedef bit121_t bit121_array1_t[1][1][1]; - typedef logic logic1_t; - typedef logic1_t logic1_array_t[4][3][2]; - typedef logic1_t logic1_array1_t[1][1][1]; - typedef logic [6:0] logic7_t; - typedef logic7_t logic7_array_t[4][3][2]; - typedef logic7_t logic7_array1_t[1][1][1]; - typedef logic [120:0] logic121_t; - typedef logic121_t logic121_array_t[4][3][2]; - typedef logic121_t logic121_array1_t[1][1][1]; + typedef chandle chandle_t; + typedef chandle_t chandle_array_t[4][3][2]; + typedef chandle_t chandle_array1_t[1][1][1]; + typedef string string_t; + typedef string_t string_array_t[4][3][2]; + typedef string_t string_array1_t[1][1][1]; + typedef bit bit1_t; + typedef bit1_t bit1_array_t[4][3][2]; + typedef bit1_t bit1_array1_t[1][1][1]; + typedef bit [6:0] bit7_t; + typedef bit7_t bit7_array_t[4][3][2]; + typedef bit7_t bit7_array1_t[1][1][1]; + typedef bit [120:0] bit121_t; + typedef bit121_t bit121_array_t[4][3][2]; + typedef bit121_t bit121_array1_t[1][1][1]; + typedef logic logic1_t; + typedef logic1_t logic1_array_t[4][3][2]; + typedef logic1_t logic1_array1_t[1][1][1]; + typedef logic [6:0] logic7_t; + typedef logic7_t logic7_array_t[4][3][2]; + typedef logic7_t logic7_array1_t[1][1][1]; + typedef logic [120:0] logic121_t; + typedef logic121_t logic121_array_t[4][3][2]; + typedef logic121_t logic121_array1_t[1][1][1]; - typedef struct packed { - logic [6:0] val; - } pack_struct_t; - typedef pack_struct_t pack_struct_array_t[4][3][2]; - typedef pack_struct_t pack_struct_array1_t[1][1][1]; + typedef struct packed { + logic [6:0] val; + } pack_struct_t; + typedef pack_struct_t pack_struct_array_t[4][3][2]; + typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT - typedef struct { - logic [120:0] val; - } unpack_struct_t; - typedef unpack_struct_t unpack_struct_array_t[4][3][2]; - typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; + typedef struct { + logic [120:0] val; + } unpack_struct_t; + typedef unpack_struct_t unpack_struct_array_t[4][3][2]; + typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Returns non-null pointer - import "DPI-C" function chandle get_non_null(); + // Returns non-null pointer + import "DPI-C" function chandle get_non_null(); - import "DPI-C" function void i_byte_0d(inout byte_t val); - import "DPI-C" function void i_byte_1d(inout byte_t val[2]); - import "DPI-C" function void i_byte_2d(inout byte_t val[3][2]); - import "DPI-C" function void i_byte_3d(inout byte_array_t val); - import "DPI-C" function void i_byte_1d1(inout byte_t val[1]); - import "DPI-C" function void i_byte_2d1(inout byte_t val[1][1]); - import "DPI-C" function void i_byte_3d1(inout byte_array1_t val); + import "DPI-C" function void i_byte_0d(inout byte_t val); + import "DPI-C" function void i_byte_1d(inout byte_t val[2]); + import "DPI-C" function void i_byte_2d(inout byte_t val[3][2]); + import "DPI-C" function void i_byte_3d(inout byte_array_t val); + import "DPI-C" function void i_byte_1d1(inout byte_t val[1]); + import "DPI-C" function void i_byte_2d1(inout byte_t val[1][1]); + import "DPI-C" function void i_byte_3d1(inout byte_array1_t val); - import "DPI-C" function void i_byte_unsigned_0d(inout byte unsigned val); - import "DPI-C" function void i_byte_unsigned_1d(inout byte unsigned val[2]); - import "DPI-C" function void i_byte_unsigned_2d(inout byte unsigned val[3][2]); - import "DPI-C" function void i_byte_unsigned_3d(inout byte_unsigned_array_t val); - import "DPI-C" function void i_byte_unsigned_1d1(inout byte unsigned val[1]); - import "DPI-C" function void i_byte_unsigned_2d1(inout byte unsigned val[1][1]); - import "DPI-C" function void i_byte_unsigned_3d1(inout byte_unsigned_array1_t val); + import "DPI-C" function void i_byte_unsigned_0d(inout byte unsigned val); + import "DPI-C" function void i_byte_unsigned_1d(inout byte unsigned val[2]); + import "DPI-C" function void i_byte_unsigned_2d(inout byte unsigned val[3][2]); + import "DPI-C" function void i_byte_unsigned_3d(inout byte_unsigned_array_t val); + import "DPI-C" function void i_byte_unsigned_1d1(inout byte unsigned val[1]); + import "DPI-C" function void i_byte_unsigned_2d1(inout byte unsigned val[1][1]); + import "DPI-C" function void i_byte_unsigned_3d1(inout byte_unsigned_array1_t val); - import "DPI-C" function void i_shortint_0d(inout shortint val); - import "DPI-C" function void i_shortint_1d(inout shortint val[2]); - import "DPI-C" function void i_shortint_2d(inout shortint val[3][2]); - import "DPI-C" function void i_shortint_3d(inout shortint_array_t val); - import "DPI-C" function void i_shortint_1d1(inout shortint val[1]); - import "DPI-C" function void i_shortint_2d1(inout shortint val[1][1]); - import "DPI-C" function void i_shortint_3d1(inout shortint_array1_t val); + import "DPI-C" function void i_shortint_0d(inout shortint val); + import "DPI-C" function void i_shortint_1d(inout shortint val[2]); + import "DPI-C" function void i_shortint_2d(inout shortint val[3][2]); + import "DPI-C" function void i_shortint_3d(inout shortint_array_t val); + import "DPI-C" function void i_shortint_1d1(inout shortint val[1]); + import "DPI-C" function void i_shortint_2d1(inout shortint val[1][1]); + import "DPI-C" function void i_shortint_3d1(inout shortint_array1_t val); - import "DPI-C" function void i_shortint_unsigned_0d(inout shortint unsigned val); - import "DPI-C" function void i_shortint_unsigned_1d(inout shortint unsigned val[2]); - import "DPI-C" function void i_shortint_unsigned_2d(inout shortint unsigned val[3][2]); - import "DPI-C" function void i_shortint_unsigned_3d(inout shortint_unsigned_array_t val); - import "DPI-C" function void i_shortint_unsigned_1d1(inout shortint unsigned val[1]); - import "DPI-C" function void i_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); - import "DPI-C" function void i_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); + import "DPI-C" function void i_shortint_unsigned_0d(inout shortint unsigned val); + import "DPI-C" function void i_shortint_unsigned_1d(inout shortint unsigned val[2]); + import "DPI-C" function void i_shortint_unsigned_2d(inout shortint unsigned val[3][2]); + import "DPI-C" function void i_shortint_unsigned_3d(inout shortint_unsigned_array_t val); + import "DPI-C" function void i_shortint_unsigned_1d1(inout shortint unsigned val[1]); + import "DPI-C" function void i_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); + import "DPI-C" function void i_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); - import "DPI-C" function void i_int_0d(inout int val); - import "DPI-C" function void i_int_1d(inout int val[2]); - import "DPI-C" function void i_int_2d(inout int val[3][2]); - import "DPI-C" function void i_int_3d(inout int_array_t val); - import "DPI-C" function void i_int_1d1(inout int val[1]); - import "DPI-C" function void i_int_2d1(inout int val[1][1]); - import "DPI-C" function void i_int_3d1(inout int_array1_t val); + import "DPI-C" function void i_int_0d(inout int val); + import "DPI-C" function void i_int_1d(inout int val[2]); + import "DPI-C" function void i_int_2d(inout int val[3][2]); + import "DPI-C" function void i_int_3d(inout int_array_t val); + import "DPI-C" function void i_int_1d1(inout int val[1]); + import "DPI-C" function void i_int_2d1(inout int val[1][1]); + import "DPI-C" function void i_int_3d1(inout int_array1_t val); - import "DPI-C" function void i_int_unsigned_0d(inout int unsigned val); - import "DPI-C" function void i_int_unsigned_1d(inout int unsigned val[2]); - import "DPI-C" function void i_int_unsigned_2d(inout int unsigned val[3][2]); - import "DPI-C" function void i_int_unsigned_3d(inout int_unsigned_array_t val); - import "DPI-C" function void i_int_unsigned_1d1(inout int unsigned val[1]); - import "DPI-C" function void i_int_unsigned_2d1(inout int unsigned val[1][1]); - import "DPI-C" function void i_int_unsigned_3d1(inout int_unsigned_array1_t val); + import "DPI-C" function void i_int_unsigned_0d(inout int unsigned val); + import "DPI-C" function void i_int_unsigned_1d(inout int unsigned val[2]); + import "DPI-C" function void i_int_unsigned_2d(inout int unsigned val[3][2]); + import "DPI-C" function void i_int_unsigned_3d(inout int_unsigned_array_t val); + import "DPI-C" function void i_int_unsigned_1d1(inout int unsigned val[1]); + import "DPI-C" function void i_int_unsigned_2d1(inout int unsigned val[1][1]); + import "DPI-C" function void i_int_unsigned_3d1(inout int_unsigned_array1_t val); - import "DPI-C" function void i_longint_0d(inout longint val); - import "DPI-C" function void i_longint_1d(inout longint val[2]); - import "DPI-C" function void i_longint_2d(inout longint val[3][2]); - import "DPI-C" function void i_longint_3d(inout longint_array_t val); - import "DPI-C" function void i_longint_1d1(inout longint val[1]); - import "DPI-C" function void i_longint_2d1(inout longint val[1][1]); - import "DPI-C" function void i_longint_3d1(inout longint_array1_t val); + import "DPI-C" function void i_longint_0d(inout longint val); + import "DPI-C" function void i_longint_1d(inout longint val[2]); + import "DPI-C" function void i_longint_2d(inout longint val[3][2]); + import "DPI-C" function void i_longint_3d(inout longint_array_t val); + import "DPI-C" function void i_longint_1d1(inout longint val[1]); + import "DPI-C" function void i_longint_2d1(inout longint val[1][1]); + import "DPI-C" function void i_longint_3d1(inout longint_array1_t val); - import "DPI-C" function void i_longint_unsigned_0d(inout longint unsigned val); - import "DPI-C" function void i_longint_unsigned_1d(inout longint unsigned val[2]); - import "DPI-C" function void i_longint_unsigned_2d(inout longint unsigned val[3][2]); - import "DPI-C" function void i_longint_unsigned_3d(inout longint_unsigned_array_t val); - import "DPI-C" function void i_longint_unsigned_1d1(inout longint unsigned val[1]); - import "DPI-C" function void i_longint_unsigned_2d1(inout longint unsigned val[1][1]); - import "DPI-C" function void i_longint_unsigned_3d1(inout longint_unsigned_array1_t val); + import "DPI-C" function void i_longint_unsigned_0d(inout longint unsigned val); + import "DPI-C" function void i_longint_unsigned_1d(inout longint unsigned val[2]); + import "DPI-C" function void i_longint_unsigned_2d(inout longint unsigned val[3][2]); + import "DPI-C" function void i_longint_unsigned_3d(inout longint_unsigned_array_t val); + import "DPI-C" function void i_longint_unsigned_1d1(inout longint unsigned val[1]); + import "DPI-C" function void i_longint_unsigned_2d1(inout longint unsigned val[1][1]); + import "DPI-C" function void i_longint_unsigned_3d1(inout longint_unsigned_array1_t val); `ifndef NO_TIME - import "DPI-C" function void i_time_0d(inout time val); - import "DPI-C" function void i_time_1d(inout time val[2]); - import "DPI-C" function void i_time_2d(inout time val[3][2]); - import "DPI-C" function void i_time_3d(inout time_array_t val); - import "DPI-C" function void i_time_1d1(inout time val[1]); - import "DPI-C" function void i_time_2d1(inout time val[1][1]); - import "DPI-C" function void i_time_3d1(inout time_array1_t val); + import "DPI-C" function void i_time_0d(inout time val); + import "DPI-C" function void i_time_1d(inout time val[2]); + import "DPI-C" function void i_time_2d(inout time val[3][2]); + import "DPI-C" function void i_time_3d(inout time_array_t val); + import "DPI-C" function void i_time_1d1(inout time val[1]); + import "DPI-C" function void i_time_2d1(inout time val[1][1]); + import "DPI-C" function void i_time_3d1(inout time_array1_t val); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_0d(inout integer val); - import "DPI-C" function void i_integer_1d(inout integer val[2]); - import "DPI-C" function void i_integer_2d(inout integer val[3][2]); - import "DPI-C" function void i_integer_3d(inout integer_array_t val); - import "DPI-C" function void i_integer_1d1(inout integer val[1]); - import "DPI-C" function void i_integer_2d1(inout integer val[1][1]); - import "DPI-C" function void i_integer_3d1(inout integer_array1_t val); + import "DPI-C" function void i_integer_0d(inout integer val); + import "DPI-C" function void i_integer_1d(inout integer val[2]); + import "DPI-C" function void i_integer_2d(inout integer val[3][2]); + import "DPI-C" function void i_integer_3d(inout integer_array_t val); + import "DPI-C" function void i_integer_1d1(inout integer val[1]); + import "DPI-C" function void i_integer_2d1(inout integer val[1][1]); + import "DPI-C" function void i_integer_3d1(inout integer_array1_t val); `endif - import "DPI-C" function void i_real_0d(inout real val); - import "DPI-C" function void i_real_1d(inout real val[2]); - import "DPI-C" function void i_real_2d(inout real val[3][2]); - import "DPI-C" function void i_real_3d(inout real_array_t val); - import "DPI-C" function void i_real_1d1(inout real val[1]); - import "DPI-C" function void i_real_2d1(inout real val[1][1]); - import "DPI-C" function void i_real_3d1(inout real_array1_t val); + import "DPI-C" function void i_real_0d(inout real val); + import "DPI-C" function void i_real_1d(inout real val[2]); + import "DPI-C" function void i_real_2d(inout real val[3][2]); + import "DPI-C" function void i_real_3d(inout real_array_t val); + import "DPI-C" function void i_real_1d1(inout real val[1]); + import "DPI-C" function void i_real_2d1(inout real val[1][1]); + import "DPI-C" function void i_real_3d1(inout real_array1_t val); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_0d(inout shortreal val); - import "DPI-C" function void i_shortreal_1d(inout shortreal val[2]); - import "DPI-C" function void i_shortreal_2d(inout shortreal val[3][2]); - import "DPI-C" function void i_shortreal_3d(inout shortreal_array_t val); - import "DPI-C" function void i_shortreal_1d1(inout shortreal val[1]); - import "DPI-C" function void i_shortreal_2d1(inout shortreal val[1][1]); - import "DPI-C" function void i_shortreal_3d1(inout shortreal_array1_t val); + import "DPI-C" function void i_shortreal_0d(inout shortreal val); + import "DPI-C" function void i_shortreal_1d(inout shortreal val[2]); + import "DPI-C" function void i_shortreal_2d(inout shortreal val[3][2]); + import "DPI-C" function void i_shortreal_3d(inout shortreal_array_t val); + import "DPI-C" function void i_shortreal_1d1(inout shortreal val[1]); + import "DPI-C" function void i_shortreal_2d1(inout shortreal val[1][1]); + import "DPI-C" function void i_shortreal_3d1(inout shortreal_array1_t val); `endif - import "DPI-C" function void i_chandle_0d(inout chandle val); - import "DPI-C" function void i_chandle_1d(inout chandle val[2]); - import "DPI-C" function void i_chandle_2d(inout chandle val[3][2]); - import "DPI-C" function void i_chandle_3d(inout chandle_array_t val); - import "DPI-C" function void i_chandle_1d1(inout chandle val[1]); - import "DPI-C" function void i_chandle_2d1(inout chandle val[1][1]); - import "DPI-C" function void i_chandle_3d1(inout chandle_array1_t val); + import "DPI-C" function void i_chandle_0d(inout chandle val); + import "DPI-C" function void i_chandle_1d(inout chandle val[2]); + import "DPI-C" function void i_chandle_2d(inout chandle val[3][2]); + import "DPI-C" function void i_chandle_3d(inout chandle_array_t val); + import "DPI-C" function void i_chandle_1d1(inout chandle val[1]); + import "DPI-C" function void i_chandle_2d1(inout chandle val[1][1]); + import "DPI-C" function void i_chandle_3d1(inout chandle_array1_t val); - import "DPI-C" function void i_string_0d(inout string val); - import "DPI-C" function void i_string_1d(inout string val[2]); - import "DPI-C" function void i_string_2d(inout string val[3][2]); - import "DPI-C" function void i_string_3d(inout string_array_t val); - import "DPI-C" function void i_string_1d1(inout string val[1]); - import "DPI-C" function void i_string_2d1(inout string val[1][1]); - import "DPI-C" function void i_string_3d1(inout string_array1_t val); + import "DPI-C" function void i_string_0d(inout string val); + import "DPI-C" function void i_string_1d(inout string val[2]); + import "DPI-C" function void i_string_2d(inout string val[3][2]); + import "DPI-C" function void i_string_3d(inout string_array_t val); + import "DPI-C" function void i_string_1d1(inout string val[1]); + import "DPI-C" function void i_string_2d1(inout string val[1][1]); + import "DPI-C" function void i_string_3d1(inout string_array1_t val); - import "DPI-C" function void i_bit1_0d(inout bit val); - import "DPI-C" function void i_bit1_1d(inout bit val[2]); - import "DPI-C" function void i_bit1_2d(inout bit val[3][2]); - import "DPI-C" function void i_bit1_3d(inout bit1_array_t val); - import "DPI-C" function void i_bit1_1d1(inout bit val[1]); - import "DPI-C" function void i_bit1_2d1(inout bit val[1][1]); - import "DPI-C" function void i_bit1_3d1(inout bit1_array1_t val); + import "DPI-C" function void i_bit1_0d(inout bit val); + import "DPI-C" function void i_bit1_1d(inout bit val[2]); + import "DPI-C" function void i_bit1_2d(inout bit val[3][2]); + import "DPI-C" function void i_bit1_3d(inout bit1_array_t val); + import "DPI-C" function void i_bit1_1d1(inout bit val[1]); + import "DPI-C" function void i_bit1_2d1(inout bit val[1][1]); + import "DPI-C" function void i_bit1_3d1(inout bit1_array1_t val); - import "DPI-C" function void i_bit7_0d(inout bit[6:0] val); - import "DPI-C" function void i_bit7_1d(inout bit[6:0] val[2]); - import "DPI-C" function void i_bit7_2d(inout bit[6:0] val[3][2]); - import "DPI-C" function void i_bit7_3d(inout bit7_array_t val); - import "DPI-C" function void i_bit7_1d1(inout bit[6:0] val[1]); - import "DPI-C" function void i_bit7_2d1(inout bit[6:0] val[1][1]); - import "DPI-C" function void i_bit7_3d1(inout bit7_array1_t val); + import "DPI-C" function void i_bit7_0d(inout bit[6:0] val); + import "DPI-C" function void i_bit7_1d(inout bit[6:0] val[2]); + import "DPI-C" function void i_bit7_2d(inout bit[6:0] val[3][2]); + import "DPI-C" function void i_bit7_3d(inout bit7_array_t val); + import "DPI-C" function void i_bit7_1d1(inout bit[6:0] val[1]); + import "DPI-C" function void i_bit7_2d1(inout bit[6:0] val[1][1]); + import "DPI-C" function void i_bit7_3d1(inout bit7_array1_t val); - import "DPI-C" function void i_bit121_0d(inout bit[120:0] val); - import "DPI-C" function void i_bit121_1d(inout bit[120:0] val[2]); - import "DPI-C" function void i_bit121_2d(inout bit[120:0] val[3][2]); - import "DPI-C" function void i_bit121_3d(inout bit121_array_t val); - import "DPI-C" function void i_bit121_1d1(inout bit[120:0] val[1]); - import "DPI-C" function void i_bit121_2d1(inout bit[120:0] val[1][1]); - import "DPI-C" function void i_bit121_3d1(inout bit121_array1_t val); + import "DPI-C" function void i_bit121_0d(inout bit[120:0] val); + import "DPI-C" function void i_bit121_1d(inout bit[120:0] val[2]); + import "DPI-C" function void i_bit121_2d(inout bit[120:0] val[3][2]); + import "DPI-C" function void i_bit121_3d(inout bit121_array_t val); + import "DPI-C" function void i_bit121_1d1(inout bit[120:0] val[1]); + import "DPI-C" function void i_bit121_2d1(inout bit[120:0] val[1][1]); + import "DPI-C" function void i_bit121_3d1(inout bit121_array1_t val); - import "DPI-C" function void i_logic1_0d(inout logic val); - import "DPI-C" function void i_logic1_1d(inout logic val[2]); - import "DPI-C" function void i_logic1_2d(inout logic val[3][2]); - import "DPI-C" function void i_logic1_3d(inout logic1_array_t val); - import "DPI-C" function void i_logic1_1d1(inout logic val[1]); - import "DPI-C" function void i_logic1_2d1(inout logic val[1][1]); - import "DPI-C" function void i_logic1_3d1(inout logic1_array1_t val); + import "DPI-C" function void i_logic1_0d(inout logic val); + import "DPI-C" function void i_logic1_1d(inout logic val[2]); + import "DPI-C" function void i_logic1_2d(inout logic val[3][2]); + import "DPI-C" function void i_logic1_3d(inout logic1_array_t val); + import "DPI-C" function void i_logic1_1d1(inout logic val[1]); + import "DPI-C" function void i_logic1_2d1(inout logic val[1][1]); + import "DPI-C" function void i_logic1_3d1(inout logic1_array1_t val); - import "DPI-C" function void i_logic7_0d(inout logic[6:0] val); - import "DPI-C" function void i_logic7_1d(inout logic[6:0] val[2]); - import "DPI-C" function void i_logic7_2d(inout logic[6:0] val[3][2]); - import "DPI-C" function void i_logic7_3d(inout logic7_array_t val); - import "DPI-C" function void i_logic7_1d1(inout logic[6:0] val[1]); - import "DPI-C" function void i_logic7_2d1(inout logic[6:0] val[1][1]); - import "DPI-C" function void i_logic7_3d1(inout logic7_array1_t val); + import "DPI-C" function void i_logic7_0d(inout logic[6:0] val); + import "DPI-C" function void i_logic7_1d(inout logic[6:0] val[2]); + import "DPI-C" function void i_logic7_2d(inout logic[6:0] val[3][2]); + import "DPI-C" function void i_logic7_3d(inout logic7_array_t val); + import "DPI-C" function void i_logic7_1d1(inout logic[6:0] val[1]); + import "DPI-C" function void i_logic7_2d1(inout logic[6:0] val[1][1]); + import "DPI-C" function void i_logic7_3d1(inout logic7_array1_t val); - import "DPI-C" function void i_logic121_0d(inout logic[120:0] val); - import "DPI-C" function void i_logic121_1d(inout logic[120:0] val[2]); - import "DPI-C" function void i_logic121_2d(inout logic[120:0] val[3][2]); - import "DPI-C" function void i_logic121_3d(inout logic121_array_t val); - import "DPI-C" function void i_logic121_1d1(inout logic[120:0] val[1]); - import "DPI-C" function void i_logic121_2d1(inout logic[120:0] val[1][1]); - import "DPI-C" function void i_logic121_3d1(inout logic121_array1_t val); + import "DPI-C" function void i_logic121_0d(inout logic[120:0] val); + import "DPI-C" function void i_logic121_1d(inout logic[120:0] val[2]); + import "DPI-C" function void i_logic121_2d(inout logic[120:0] val[3][2]); + import "DPI-C" function void i_logic121_3d(inout logic121_array_t val); + import "DPI-C" function void i_logic121_1d1(inout logic[120:0] val[1]); + import "DPI-C" function void i_logic121_2d1(inout logic[120:0] val[1][1]); + import "DPI-C" function void i_logic121_3d1(inout logic121_array1_t val); - import "DPI-C" function void i_pack_struct_0d(inout pack_struct_t val); - import "DPI-C" function void i_pack_struct_1d(inout pack_struct_t val[2]); - import "DPI-C" function void i_pack_struct_2d(inout pack_struct_t val[3][2]); - import "DPI-C" function void i_pack_struct_3d(inout pack_struct_array_t val); - import "DPI-C" function void i_pack_struct_1d1(inout pack_struct_t val[1]); - import "DPI-C" function void i_pack_struct_2d1(inout pack_struct_t val[1][1]); - import "DPI-C" function void i_pack_struct_3d1(inout pack_struct_array1_t val); + import "DPI-C" function void i_pack_struct_0d(inout pack_struct_t val); + import "DPI-C" function void i_pack_struct_1d(inout pack_struct_t val[2]); + import "DPI-C" function void i_pack_struct_2d(inout pack_struct_t val[3][2]); + import "DPI-C" function void i_pack_struct_3d(inout pack_struct_array_t val); + import "DPI-C" function void i_pack_struct_1d1(inout pack_struct_t val[1]); + import "DPI-C" function void i_pack_struct_2d1(inout pack_struct_t val[1][1]); + import "DPI-C" function void i_pack_struct_3d1(inout pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT - import "DPI-C" function void i_unpack_struct_0d(inout unpack_struct_t val); - import "DPI-C" function void i_unpack_struct_1d(inout unpack_struct_t val[2]); - import "DPI-C" function void i_unpack_struct_2d(inout unpack_struct_t val[3][2]); - import "DPI-C" function void i_unpack_struct_3d(inout unpack_struct_array_t val); - import "DPI-C" function void i_unpack_struct_1d1(inout unpack_struct_t val[1]); - import "DPI-C" function void i_unpack_struct_2d1(inout unpack_struct_t val[1][1]); - import "DPI-C" function void i_unpack_struct_3d1(inout unpack_struct_array1_t val); + import "DPI-C" function void i_unpack_struct_0d(inout unpack_struct_t val); + import "DPI-C" function void i_unpack_struct_1d(inout unpack_struct_t val[2]); + import "DPI-C" function void i_unpack_struct_2d(inout unpack_struct_t val[3][2]); + import "DPI-C" function void i_unpack_struct_3d(inout unpack_struct_array_t val); + import "DPI-C" function void i_unpack_struct_1d1(inout unpack_struct_t val[1]); + import "DPI-C" function void i_unpack_struct_2d1(inout unpack_struct_t val[1][1]); + import "DPI-C" function void i_unpack_struct_3d1(inout unpack_struct_array1_t val); `endif - //====================================================================== - // Exports - //====================================================================== - export "DPI-C" function e_byte_0d; - export "DPI-C" function e_byte_1d; - export "DPI-C" function e_byte_2d; - export "DPI-C" function e_byte_3d; - export "DPI-C" function e_byte_1d1; - export "DPI-C" function e_byte_2d1; - export "DPI-C" function e_byte_3d1; + //====================================================================== + // Exports + //====================================================================== + export "DPI-C" function e_byte_0d; + export "DPI-C" function e_byte_1d; + export "DPI-C" function e_byte_2d; + export "DPI-C" function e_byte_3d; + export "DPI-C" function e_byte_1d1; + export "DPI-C" function e_byte_2d1; + export "DPI-C" function e_byte_3d1; - export "DPI-C" function e_byte_unsigned_0d; - export "DPI-C" function e_byte_unsigned_1d; - export "DPI-C" function e_byte_unsigned_2d; - export "DPI-C" function e_byte_unsigned_3d; - export "DPI-C" function e_byte_unsigned_1d1; - export "DPI-C" function e_byte_unsigned_2d1; - export "DPI-C" function e_byte_unsigned_3d1; + export "DPI-C" function e_byte_unsigned_0d; + export "DPI-C" function e_byte_unsigned_1d; + export "DPI-C" function e_byte_unsigned_2d; + export "DPI-C" function e_byte_unsigned_3d; + export "DPI-C" function e_byte_unsigned_1d1; + export "DPI-C" function e_byte_unsigned_2d1; + export "DPI-C" function e_byte_unsigned_3d1; - export "DPI-C" function e_shortint_0d; - export "DPI-C" function e_shortint_1d; - export "DPI-C" function e_shortint_2d; - export "DPI-C" function e_shortint_3d; - export "DPI-C" function e_shortint_1d1; - export "DPI-C" function e_shortint_2d1; - export "DPI-C" function e_shortint_3d1; + export "DPI-C" function e_shortint_0d; + export "DPI-C" function e_shortint_1d; + export "DPI-C" function e_shortint_2d; + export "DPI-C" function e_shortint_3d; + export "DPI-C" function e_shortint_1d1; + export "DPI-C" function e_shortint_2d1; + export "DPI-C" function e_shortint_3d1; - export "DPI-C" function e_shortint_unsigned_0d; - export "DPI-C" function e_shortint_unsigned_1d; - export "DPI-C" function e_shortint_unsigned_2d; - export "DPI-C" function e_shortint_unsigned_3d; - export "DPI-C" function e_shortint_unsigned_1d1; - export "DPI-C" function e_shortint_unsigned_2d1; - export "DPI-C" function e_shortint_unsigned_3d1; + export "DPI-C" function e_shortint_unsigned_0d; + export "DPI-C" function e_shortint_unsigned_1d; + export "DPI-C" function e_shortint_unsigned_2d; + export "DPI-C" function e_shortint_unsigned_3d; + export "DPI-C" function e_shortint_unsigned_1d1; + export "DPI-C" function e_shortint_unsigned_2d1; + export "DPI-C" function e_shortint_unsigned_3d1; - export "DPI-C" function e_int_0d; - export "DPI-C" function e_int_1d; - export "DPI-C" function e_int_2d; - export "DPI-C" function e_int_3d; - export "DPI-C" function e_int_1d1; - export "DPI-C" function e_int_2d1; - export "DPI-C" function e_int_3d1; + export "DPI-C" function e_int_0d; + export "DPI-C" function e_int_1d; + export "DPI-C" function e_int_2d; + export "DPI-C" function e_int_3d; + export "DPI-C" function e_int_1d1; + export "DPI-C" function e_int_2d1; + export "DPI-C" function e_int_3d1; - export "DPI-C" function e_int_unsigned_0d; - export "DPI-C" function e_int_unsigned_1d; - export "DPI-C" function e_int_unsigned_2d; - export "DPI-C" function e_int_unsigned_3d; - export "DPI-C" function e_int_unsigned_1d1; - export "DPI-C" function e_int_unsigned_2d1; - export "DPI-C" function e_int_unsigned_3d1; + export "DPI-C" function e_int_unsigned_0d; + export "DPI-C" function e_int_unsigned_1d; + export "DPI-C" function e_int_unsigned_2d; + export "DPI-C" function e_int_unsigned_3d; + export "DPI-C" function e_int_unsigned_1d1; + export "DPI-C" function e_int_unsigned_2d1; + export "DPI-C" function e_int_unsigned_3d1; - export "DPI-C" function e_longint_0d; - export "DPI-C" function e_longint_1d; - export "DPI-C" function e_longint_2d; - export "DPI-C" function e_longint_3d; - export "DPI-C" function e_longint_1d1; - export "DPI-C" function e_longint_2d1; - export "DPI-C" function e_longint_3d1; + export "DPI-C" function e_longint_0d; + export "DPI-C" function e_longint_1d; + export "DPI-C" function e_longint_2d; + export "DPI-C" function e_longint_3d; + export "DPI-C" function e_longint_1d1; + export "DPI-C" function e_longint_2d1; + export "DPI-C" function e_longint_3d1; - export "DPI-C" function e_longint_unsigned_0d; - export "DPI-C" function e_longint_unsigned_1d; - export "DPI-C" function e_longint_unsigned_2d; - export "DPI-C" function e_longint_unsigned_3d; - export "DPI-C" function e_longint_unsigned_1d1; - export "DPI-C" function e_longint_unsigned_2d1; - export "DPI-C" function e_longint_unsigned_3d1; + export "DPI-C" function e_longint_unsigned_0d; + export "DPI-C" function e_longint_unsigned_1d; + export "DPI-C" function e_longint_unsigned_2d; + export "DPI-C" function e_longint_unsigned_3d; + export "DPI-C" function e_longint_unsigned_1d1; + export "DPI-C" function e_longint_unsigned_2d1; + export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME - export "DPI-C" function e_time_0d; - export "DPI-C" function e_time_1d; - export "DPI-C" function e_time_2d; - export "DPI-C" function e_time_3d; - export "DPI-C" function e_time_1d1; - export "DPI-C" function e_time_2d1; - export "DPI-C" function e_time_3d1; + export "DPI-C" function e_time_0d; + export "DPI-C" function e_time_1d; + export "DPI-C" function e_time_2d; + export "DPI-C" function e_time_3d; + export "DPI-C" function e_time_1d1; + export "DPI-C" function e_time_2d1; + export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_0d; - export "DPI-C" function e_integer_1d; - export "DPI-C" function e_integer_2d; - export "DPI-C" function e_integer_3d; - export "DPI-C" function e_integer_1d1; - export "DPI-C" function e_integer_2d1; - export "DPI-C" function e_integer_3d1; + export "DPI-C" function e_integer_0d; + export "DPI-C" function e_integer_1d; + export "DPI-C" function e_integer_2d; + export "DPI-C" function e_integer_3d; + export "DPI-C" function e_integer_1d1; + export "DPI-C" function e_integer_2d1; + export "DPI-C" function e_integer_3d1; `endif - export "DPI-C" function e_real_0d; - export "DPI-C" function e_real_1d; - export "DPI-C" function e_real_2d; - export "DPI-C" function e_real_3d; - export "DPI-C" function e_real_1d1; - export "DPI-C" function e_real_2d1; - export "DPI-C" function e_real_3d1; + export "DPI-C" function e_real_0d; + export "DPI-C" function e_real_1d; + export "DPI-C" function e_real_2d; + export "DPI-C" function e_real_3d; + export "DPI-C" function e_real_1d1; + export "DPI-C" function e_real_2d1; + export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_0d; - export "DPI-C" function e_shortreal_1d; - export "DPI-C" function e_shortreal_2d; - export "DPI-C" function e_shortreal_3d; - export "DPI-C" function e_shortreal_1d1; - export "DPI-C" function e_shortreal_2d1; - export "DPI-C" function e_shortreal_3d1; + export "DPI-C" function e_shortreal_0d; + export "DPI-C" function e_shortreal_1d; + export "DPI-C" function e_shortreal_2d; + export "DPI-C" function e_shortreal_3d; + export "DPI-C" function e_shortreal_1d1; + export "DPI-C" function e_shortreal_2d1; + export "DPI-C" function e_shortreal_3d1; `endif - export "DPI-C" function e_chandle_0d; - export "DPI-C" function e_chandle_1d; - export "DPI-C" function e_chandle_2d; - export "DPI-C" function e_chandle_3d; - export "DPI-C" function e_chandle_1d1; - export "DPI-C" function e_chandle_2d1; - export "DPI-C" function e_chandle_3d1; + export "DPI-C" function e_chandle_0d; + export "DPI-C" function e_chandle_1d; + export "DPI-C" function e_chandle_2d; + export "DPI-C" function e_chandle_3d; + export "DPI-C" function e_chandle_1d1; + export "DPI-C" function e_chandle_2d1; + export "DPI-C" function e_chandle_3d1; - export "DPI-C" function e_string_0d; - export "DPI-C" function e_string_1d; - export "DPI-C" function e_string_2d; - export "DPI-C" function e_string_3d; - export "DPI-C" function e_string_1d1; - export "DPI-C" function e_string_2d1; - export "DPI-C" function e_string_3d1; + export "DPI-C" function e_string_0d; + export "DPI-C" function e_string_1d; + export "DPI-C" function e_string_2d; + export "DPI-C" function e_string_3d; + export "DPI-C" function e_string_1d1; + export "DPI-C" function e_string_2d1; + export "DPI-C" function e_string_3d1; - export "DPI-C" function e_bit1_0d; - export "DPI-C" function e_bit1_1d; - export "DPI-C" function e_bit1_2d; - export "DPI-C" function e_bit1_3d; - export "DPI-C" function e_bit1_1d1; - export "DPI-C" function e_bit1_2d1; - export "DPI-C" function e_bit1_3d1; + export "DPI-C" function e_bit1_0d; + export "DPI-C" function e_bit1_1d; + export "DPI-C" function e_bit1_2d; + export "DPI-C" function e_bit1_3d; + export "DPI-C" function e_bit1_1d1; + export "DPI-C" function e_bit1_2d1; + export "DPI-C" function e_bit1_3d1; - export "DPI-C" function e_bit7_0d; - export "DPI-C" function e_bit7_1d; - export "DPI-C" function e_bit7_2d; - export "DPI-C" function e_bit7_3d; - export "DPI-C" function e_bit7_1d1; - export "DPI-C" function e_bit7_2d1; - export "DPI-C" function e_bit7_3d1; + export "DPI-C" function e_bit7_0d; + export "DPI-C" function e_bit7_1d; + export "DPI-C" function e_bit7_2d; + export "DPI-C" function e_bit7_3d; + export "DPI-C" function e_bit7_1d1; + export "DPI-C" function e_bit7_2d1; + export "DPI-C" function e_bit7_3d1; - export "DPI-C" function e_bit121_0d; - export "DPI-C" function e_bit121_1d; - export "DPI-C" function e_bit121_2d; - export "DPI-C" function e_bit121_3d; - export "DPI-C" function e_bit121_1d1; - export "DPI-C" function e_bit121_2d1; - export "DPI-C" function e_bit121_3d1; + export "DPI-C" function e_bit121_0d; + export "DPI-C" function e_bit121_1d; + export "DPI-C" function e_bit121_2d; + export "DPI-C" function e_bit121_3d; + export "DPI-C" function e_bit121_1d1; + export "DPI-C" function e_bit121_2d1; + export "DPI-C" function e_bit121_3d1; - export "DPI-C" function e_logic1_0d; - export "DPI-C" function e_logic1_1d; - export "DPI-C" function e_logic1_2d; - export "DPI-C" function e_logic1_3d; - export "DPI-C" function e_logic1_1d1; - export "DPI-C" function e_logic1_2d1; - export "DPI-C" function e_logic1_3d1; + export "DPI-C" function e_logic1_0d; + export "DPI-C" function e_logic1_1d; + export "DPI-C" function e_logic1_2d; + export "DPI-C" function e_logic1_3d; + export "DPI-C" function e_logic1_1d1; + export "DPI-C" function e_logic1_2d1; + export "DPI-C" function e_logic1_3d1; - export "DPI-C" function e_logic7_0d; - export "DPI-C" function e_logic7_1d; - export "DPI-C" function e_logic7_2d; - export "DPI-C" function e_logic7_3d; - export "DPI-C" function e_logic7_1d1; - export "DPI-C" function e_logic7_2d1; - export "DPI-C" function e_logic7_3d1; + export "DPI-C" function e_logic7_0d; + export "DPI-C" function e_logic7_1d; + export "DPI-C" function e_logic7_2d; + export "DPI-C" function e_logic7_3d; + export "DPI-C" function e_logic7_1d1; + export "DPI-C" function e_logic7_2d1; + export "DPI-C" function e_logic7_3d1; - export "DPI-C" function e_logic121_0d; - export "DPI-C" function e_logic121_1d; - export "DPI-C" function e_logic121_2d; - export "DPI-C" function e_logic121_3d; - export "DPI-C" function e_logic121_1d1; - export "DPI-C" function e_logic121_2d1; - export "DPI-C" function e_logic121_3d1; + export "DPI-C" function e_logic121_0d; + export "DPI-C" function e_logic121_1d; + export "DPI-C" function e_logic121_2d; + export "DPI-C" function e_logic121_3d; + export "DPI-C" function e_logic121_1d1; + export "DPI-C" function e_logic121_2d1; + export "DPI-C" function e_logic121_3d1; - export "DPI-C" function e_pack_struct_0d; - export "DPI-C" function e_pack_struct_1d; - export "DPI-C" function e_pack_struct_2d; - export "DPI-C" function e_pack_struct_3d; - export "DPI-C" function e_pack_struct_1d1; - export "DPI-C" function e_pack_struct_2d1; - export "DPI-C" function e_pack_struct_3d1; + export "DPI-C" function e_pack_struct_0d; + export "DPI-C" function e_pack_struct_1d; + export "DPI-C" function e_pack_struct_2d; + export "DPI-C" function e_pack_struct_3d; + export "DPI-C" function e_pack_struct_1d1; + export "DPI-C" function e_pack_struct_2d1; + export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT - export "DPI-C" function e_unpack_struct_0d; - export "DPI-C" function e_unpack_struct_1d; - export "DPI-C" function e_unpack_struct_2d; - export "DPI-C" function e_unpack_struct_3d; - export "DPI-C" function e_unpack_struct_1d1; - export "DPI-C" function e_unpack_struct_2d1; - export "DPI-C" function e_unpack_struct_3d1; + export "DPI-C" function e_unpack_struct_0d; + export "DPI-C" function e_unpack_struct_1d; + export "DPI-C" function e_unpack_struct_2d; + export "DPI-C" function e_unpack_struct_3d; + export "DPI-C" function e_unpack_struct_1d1; + export "DPI-C" function e_unpack_struct_2d1; + export "DPI-C" function e_unpack_struct_3d1; `endif - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - function void e_byte_0d(inout byte val); `UPDATE_0D(val); endfunction - function void e_byte_1d(inout byte val[2]); `UPDATE_1D(val); endfunction - function void e_byte_2d(inout byte val[3][2]); `UPDATE_2D(val); endfunction - function void e_byte_3d(inout byte_array_t val); `UPDATE_3D(val); endfunction - function void e_byte_1d1(inout byte val[1]); `UPDATE_1D1(val); endfunction - function void e_byte_2d1(inout byte val[1][1]); `UPDATE_2D1(val); endfunction - function void e_byte_3d1(inout byte_array1_t val); `UPDATE_3D1(val); endfunction + function void e_byte_0d(inout byte val); `UPDATE_0D(val); endfunction + function void e_byte_1d(inout byte val[2]); `UPDATE_1D(val); endfunction + function void e_byte_2d(inout byte val[3][2]); `UPDATE_2D(val); endfunction + function void e_byte_3d(inout byte_array_t val); `UPDATE_3D(val); endfunction + function void e_byte_1d1(inout byte val[1]); `UPDATE_1D1(val); endfunction + function void e_byte_2d1(inout byte val[1][1]); `UPDATE_2D1(val); endfunction + function void e_byte_3d1(inout byte_array1_t val); `UPDATE_3D1(val); endfunction - function void e_byte_unsigned_0d(inout byte unsigned val); `UPDATE_0D(val); endfunction - function void e_byte_unsigned_1d(inout byte unsigned val[2]); `UPDATE_1D(val); endfunction - function void e_byte_unsigned_2d(inout byte unsigned val[3][2]); `UPDATE_2D(val); endfunction - function void e_byte_unsigned_3d(inout byte_unsigned_array_t val); `UPDATE_3D(val); endfunction - function void e_byte_unsigned_1d1(inout byte unsigned val[1]); `UPDATE_1D1(val); endfunction - function void e_byte_unsigned_2d1(inout byte unsigned val[1][1]); `UPDATE_2D1(val); endfunction - function void e_byte_unsigned_3d1(inout byte_unsigned_array1_t val); `UPDATE_3D1(val); endfunction + function void e_byte_unsigned_0d(inout byte unsigned val); `UPDATE_0D(val); endfunction + function void e_byte_unsigned_1d(inout byte unsigned val[2]); `UPDATE_1D(val); endfunction + function void e_byte_unsigned_2d(inout byte unsigned val[3][2]); `UPDATE_2D(val); endfunction + function void e_byte_unsigned_3d(inout byte_unsigned_array_t val); `UPDATE_3D(val); endfunction + function void e_byte_unsigned_1d1(inout byte unsigned val[1]); `UPDATE_1D1(val); endfunction + function void e_byte_unsigned_2d1(inout byte unsigned val[1][1]); `UPDATE_2D1(val); endfunction + function void e_byte_unsigned_3d1(inout byte_unsigned_array1_t val); `UPDATE_3D1(val); endfunction - function void e_shortint_0d(inout shortint val); `UPDATE_0D(val); endfunction - function void e_shortint_1d(inout shortint val[2]); `UPDATE_1D(val); endfunction - function void e_shortint_2d(inout shortint val[3][2]); `UPDATE_2D(val); endfunction - function void e_shortint_3d(inout shortint_array_t val); `UPDATE_3D(val); endfunction - function void e_shortint_1d1(inout shortint val[1]); `UPDATE_1D1(val); endfunction - function void e_shortint_2d1(inout shortint val[1][1]); `UPDATE_2D1(val); endfunction - function void e_shortint_3d1(inout shortint_array1_t val); `UPDATE_3D1(val); endfunction + function void e_shortint_0d(inout shortint val); `UPDATE_0D(val); endfunction + function void e_shortint_1d(inout shortint val[2]); `UPDATE_1D(val); endfunction + function void e_shortint_2d(inout shortint val[3][2]); `UPDATE_2D(val); endfunction + function void e_shortint_3d(inout shortint_array_t val); `UPDATE_3D(val); endfunction + function void e_shortint_1d1(inout shortint val[1]); `UPDATE_1D1(val); endfunction + function void e_shortint_2d1(inout shortint val[1][1]); `UPDATE_2D1(val); endfunction + function void e_shortint_3d1(inout shortint_array1_t val); `UPDATE_3D1(val); endfunction - function void e_shortint_unsigned_0d(inout shortint unsigned val); `UPDATE_0D(val); endfunction - function void e_shortint_unsigned_1d(inout shortint unsigned val[2]); `UPDATE_1D(val); endfunction - function void e_shortint_unsigned_2d(inout shortint unsigned val[3][2]); `UPDATE_2D(val); endfunction - function void e_shortint_unsigned_3d(inout shortint_unsigned_array_t val); `UPDATE_3D(val); endfunction - function void e_shortint_unsigned_1d1(inout shortint unsigned val[1]); `UPDATE_1D1(val); endfunction - function void e_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); `UPDATE_2D1(val); endfunction - function void e_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction + function void e_shortint_unsigned_0d(inout shortint unsigned val); `UPDATE_0D(val); endfunction + function void e_shortint_unsigned_1d(inout shortint unsigned val[2]); `UPDATE_1D(val); endfunction + function void e_shortint_unsigned_2d(inout shortint unsigned val[3][2]); `UPDATE_2D(val); endfunction + function void e_shortint_unsigned_3d(inout shortint_unsigned_array_t val); `UPDATE_3D(val); endfunction + function void e_shortint_unsigned_1d1(inout shortint unsigned val[1]); `UPDATE_1D1(val); endfunction + function void e_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); `UPDATE_2D1(val); endfunction + function void e_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction - function void e_int_0d(inout int val); `UPDATE_0D(val); endfunction - function void e_int_1d(inout int val[2]); `UPDATE_1D(val); endfunction - function void e_int_2d(inout int val[3][2]); `UPDATE_2D(val); endfunction - function void e_int_3d(inout int_array_t val); `UPDATE_3D(val); endfunction - function void e_int_1d1(inout int val[1]); `UPDATE_1D1(val); endfunction - function void e_int_2d1(inout int val[1][1]); `UPDATE_2D1(val); endfunction - function void e_int_3d1(inout int_array1_t val); `UPDATE_3D1(val); endfunction + function void e_int_0d(inout int val); `UPDATE_0D(val); endfunction + function void e_int_1d(inout int val[2]); `UPDATE_1D(val); endfunction + function void e_int_2d(inout int val[3][2]); `UPDATE_2D(val); endfunction + function void e_int_3d(inout int_array_t val); `UPDATE_3D(val); endfunction + function void e_int_1d1(inout int val[1]); `UPDATE_1D1(val); endfunction + function void e_int_2d1(inout int val[1][1]); `UPDATE_2D1(val); endfunction + function void e_int_3d1(inout int_array1_t val); `UPDATE_3D1(val); endfunction - function void e_int_unsigned_0d(inout int unsigned val); `UPDATE_0D(val); endfunction - function void e_int_unsigned_1d(inout int unsigned val[2]); `UPDATE_1D(val); endfunction - function void e_int_unsigned_2d(inout int unsigned val[3][2]); `UPDATE_2D(val); endfunction - function void e_int_unsigned_3d(inout int_unsigned_array_t val); `UPDATE_3D(val); endfunction - function void e_int_unsigned_1d1(inout int unsigned val[1]); `UPDATE_1D1(val); endfunction - function void e_int_unsigned_2d1(inout int unsigned val[1][1]); `UPDATE_2D1(val); endfunction - function void e_int_unsigned_3d1(inout int_unsigned_array1_t val); `UPDATE_3D1(val); endfunction + function void e_int_unsigned_0d(inout int unsigned val); `UPDATE_0D(val); endfunction + function void e_int_unsigned_1d(inout int unsigned val[2]); `UPDATE_1D(val); endfunction + function void e_int_unsigned_2d(inout int unsigned val[3][2]); `UPDATE_2D(val); endfunction + function void e_int_unsigned_3d(inout int_unsigned_array_t val); `UPDATE_3D(val); endfunction + function void e_int_unsigned_1d1(inout int unsigned val[1]); `UPDATE_1D1(val); endfunction + function void e_int_unsigned_2d1(inout int unsigned val[1][1]); `UPDATE_2D1(val); endfunction + function void e_int_unsigned_3d1(inout int_unsigned_array1_t val); `UPDATE_3D1(val); endfunction - function void e_longint_0d(inout longint val); `UPDATE_0D(val); endfunction - function void e_longint_1d(inout longint val[2]); `UPDATE_1D(val); endfunction - function void e_longint_2d(inout longint val[3][2]); `UPDATE_2D(val); endfunction - function void e_longint_3d(inout longint_array_t val); `UPDATE_3D(val); endfunction - function void e_longint_1d1(inout longint val[1]); `UPDATE_1D1(val); endfunction - function void e_longint_2d1(inout longint val[1][1]); `UPDATE_2D1(val); endfunction - function void e_longint_3d1(inout longint_array1_t val); `UPDATE_3D1(val); endfunction + function void e_longint_0d(inout longint val); `UPDATE_0D(val); endfunction + function void e_longint_1d(inout longint val[2]); `UPDATE_1D(val); endfunction + function void e_longint_2d(inout longint val[3][2]); `UPDATE_2D(val); endfunction + function void e_longint_3d(inout longint_array_t val); `UPDATE_3D(val); endfunction + function void e_longint_1d1(inout longint val[1]); `UPDATE_1D1(val); endfunction + function void e_longint_2d1(inout longint val[1][1]); `UPDATE_2D1(val); endfunction + function void e_longint_3d1(inout longint_array1_t val); `UPDATE_3D1(val); endfunction - function void e_longint_unsigned_0d(inout longint unsigned val); `UPDATE_0D(val); endfunction - function void e_longint_unsigned_1d(inout longint unsigned val[2]); `UPDATE_1D(val); endfunction - function void e_longint_unsigned_2d(inout longint unsigned val[3][2]); `UPDATE_2D(val); endfunction - function void e_longint_unsigned_3d(inout longint_unsigned_array_t val); `UPDATE_3D(val); endfunction - function void e_longint_unsigned_1d1(inout longint unsigned val[1]); `UPDATE_1D1(val); endfunction - function void e_longint_unsigned_2d1(inout longint unsigned val[1][1]); `UPDATE_2D1(val); endfunction - function void e_longint_unsigned_3d1(inout longint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction + function void e_longint_unsigned_0d(inout longint unsigned val); `UPDATE_0D(val); endfunction + function void e_longint_unsigned_1d(inout longint unsigned val[2]); `UPDATE_1D(val); endfunction + function void e_longint_unsigned_2d(inout longint unsigned val[3][2]); `UPDATE_2D(val); endfunction + function void e_longint_unsigned_3d(inout longint_unsigned_array_t val); `UPDATE_3D(val); endfunction + function void e_longint_unsigned_1d1(inout longint unsigned val[1]); `UPDATE_1D1(val); endfunction + function void e_longint_unsigned_2d1(inout longint unsigned val[1][1]); `UPDATE_2D1(val); endfunction + function void e_longint_unsigned_3d1(inout longint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_TIME - function void e_time_0d(inout time val); `UPDATE_0D(val); endfunction - function void e_time_1d(inout time val[2]); `UPDATE_1D(val); endfunction - function void e_time_2d(inout time val[3][2]); `UPDATE_2D(val); endfunction - function void e_time_3d(inout time_array_t val); `UPDATE_3D(val); endfunction - function void e_time_1d1(inout time val[1]); `UPDATE_1D1(val); endfunction - function void e_time_2d1(inout time val[1][1]); `UPDATE_2D1(val); endfunction - function void e_time_3d1(inout time_array1_t val); `UPDATE_3D1(val); endfunction + function void e_time_0d(inout time val); `UPDATE_0D(val); endfunction + function void e_time_1d(inout time val[2]); `UPDATE_1D(val); endfunction + function void e_time_2d(inout time val[3][2]); `UPDATE_2D(val); endfunction + function void e_time_3d(inout time_array_t val); `UPDATE_3D(val); endfunction + function void e_time_1d1(inout time val[1]); `UPDATE_1D1(val); endfunction + function void e_time_2d1(inout time val[1][1]); `UPDATE_2D1(val); endfunction + function void e_time_3d1(inout time_array1_t val); `UPDATE_3D1(val); endfunction `endif `ifndef NO_INTEGER - function void e_integer_0d(inout integer val); `UPDATE_0D(val); endfunction - function void e_integer_1d(inout integer val[2]); `UPDATE_1D(val); endfunction - function void e_integer_2d(inout integer val[3][2]); `UPDATE_2D(val); endfunction - function void e_integer_3d(inout integer_array_t val); `UPDATE_3D(val); endfunction - function void e_integer_1d1(inout integer val[1]); `UPDATE_1D1(val); endfunction - function void e_integer_2d1(inout integer val[1][1]); `UPDATE_2D1(val); endfunction - function void e_integer_3d1(inout integer_array1_t val); `UPDATE_3D1(val); endfunction + function void e_integer_0d(inout integer val); `UPDATE_0D(val); endfunction + function void e_integer_1d(inout integer val[2]); `UPDATE_1D(val); endfunction + function void e_integer_2d(inout integer val[3][2]); `UPDATE_2D(val); endfunction + function void e_integer_3d(inout integer_array_t val); `UPDATE_3D(val); endfunction + function void e_integer_1d1(inout integer val[1]); `UPDATE_1D1(val); endfunction + function void e_integer_2d1(inout integer val[1][1]); `UPDATE_2D1(val); endfunction + function void e_integer_3d1(inout integer_array1_t val); `UPDATE_3D1(val); endfunction `endif - function void e_real_0d(inout real val); `UPDATE_0D(val); endfunction - function void e_real_1d(inout real val[2]); `UPDATE_1D(val); endfunction - function void e_real_2d(inout real val[3][2]); `UPDATE_2D(val); endfunction - function void e_real_3d(inout real_array_t val); `UPDATE_3D(val); endfunction - function void e_real_1d1(inout real val[1]); `UPDATE_1D1(val); endfunction - function void e_real_2d1(inout real val[1][1]); `UPDATE_2D1(val); endfunction - function void e_real_3d1(inout real_array1_t val); `UPDATE_3D1(val); endfunction + function void e_real_0d(inout real val); `UPDATE_0D(val); endfunction + function void e_real_1d(inout real val[2]); `UPDATE_1D(val); endfunction + function void e_real_2d(inout real val[3][2]); `UPDATE_2D(val); endfunction + function void e_real_3d(inout real_array_t val); `UPDATE_3D(val); endfunction + function void e_real_1d1(inout real val[1]); `UPDATE_1D1(val); endfunction + function void e_real_2d1(inout real val[1][1]); `UPDATE_2D1(val); endfunction + function void e_real_3d1(inout real_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_SHORTREAL - function void e_shortreal_0d(inout shortreal val); `UPDATE_0D(val); endfunction - function void e_shortreal_1d(inout shortreal val[2]); `UPDATE_1D(val); endfunction - function void e_shortreal_2d(inout shortreal val[3][2]); `UPDATE_2D(val); endfunction - function void e_shortreal_3d(inout shortreal_array_t val); `UPDATE_3D(val); endfunction - function void e_shortreal_1d1(inout shortreal val[1]); `UPDATE_1D1(val); endfunction - function void e_shortreal_2d1(inout shortreal val[1][1]); `UPDATE_2D1(val); endfunction - function void e_shortreal_3d1(inout shortreal_array1_t val); `UPDATE_3D1(val); endfunction + function void e_shortreal_0d(inout shortreal val); `UPDATE_0D(val); endfunction + function void e_shortreal_1d(inout shortreal val[2]); `UPDATE_1D(val); endfunction + function void e_shortreal_2d(inout shortreal val[3][2]); `UPDATE_2D(val); endfunction + function void e_shortreal_3d(inout shortreal_array_t val); `UPDATE_3D(val); endfunction + function void e_shortreal_1d1(inout shortreal val[1]); `UPDATE_1D1(val); endfunction + function void e_shortreal_2d1(inout shortreal val[1][1]); `UPDATE_2D1(val); endfunction + function void e_shortreal_3d1(inout shortreal_array1_t val); `UPDATE_3D1(val); endfunction `endif - function void e_chandle_0d(inout chandle val); - `CHECK_CHANDLE_VAL(val, get_non_null()); - val = null; - endfunction - function void e_chandle_1d(inout chandle val[2]); - `CHECK_CHANDLE_VAL(val[0], get_non_null()); - `CHECK_CHANDLE_VAL(val[1], get_non_null()); - val[0] = null; - val[1] = null; - endfunction - function void e_chandle_2d(inout chandle val[3][2]); - `CHECK_CHANDLE_VAL(val[0][1], get_non_null()); - `CHECK_CHANDLE_VAL(val[1][1], get_non_null()); - `CHECK_CHANDLE_VAL(val[2][1], get_non_null()); - val[0][1] = null; - val[1][1] = null; - val[2][1] = null; - endfunction - function void e_chandle_3d(inout chandle_array_t val); - `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(val[1][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(val[2][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(val[3][0][0], get_non_null()); - val[0][0][0] = null; - val[1][0][0] = null; - val[2][0][0] = null; - val[3][0][0] = null; - endfunction - function void e_chandle_1d1(inout chandle val[1]); - `CHECK_CHANDLE_VAL(val[0], get_non_null()); - val[0] = null; - endfunction - function void e_chandle_2d1(inout chandle val[1][1]); - `CHECK_CHANDLE_VAL(val[0][0], get_non_null()); - val[0][0] = null; - endfunction - function void e_chandle_3d1(inout chandle_array1_t val); - `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); - val[0][0][0] = null; - endfunction + function void e_chandle_0d(inout chandle val); + `CHECK_CHANDLE_VAL(val, get_non_null()); + val = null; + endfunction + function void e_chandle_1d(inout chandle val[2]); + `CHECK_CHANDLE_VAL(val[0], get_non_null()); + `CHECK_CHANDLE_VAL(val[1], get_non_null()); + val[0] = null; + val[1] = null; + endfunction + function void e_chandle_2d(inout chandle val[3][2]); + `CHECK_CHANDLE_VAL(val[0][1], get_non_null()); + `CHECK_CHANDLE_VAL(val[1][1], get_non_null()); + `CHECK_CHANDLE_VAL(val[2][1], get_non_null()); + val[0][1] = null; + val[1][1] = null; + val[2][1] = null; + endfunction + function void e_chandle_3d(inout chandle_array_t val); + `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(val[1][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(val[2][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(val[3][0][0], get_non_null()); + val[0][0][0] = null; + val[1][0][0] = null; + val[2][0][0] = null; + val[3][0][0] = null; + endfunction + function void e_chandle_1d1(inout chandle val[1]); + `CHECK_CHANDLE_VAL(val[0], get_non_null()); + val[0] = null; + endfunction + function void e_chandle_2d1(inout chandle val[1][1]); + `CHECK_CHANDLE_VAL(val[0][0], get_non_null()); + val[0][0] = null; + endfunction + function void e_chandle_3d1(inout chandle_array1_t val); + `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); + val[0][0][0] = null; + endfunction - function void e_string_0d(inout string val); - `CHECK_STRING_VAL(val, "42"); - val = "43"; - endfunction - function void e_string_1d(inout string val[2]); - `CHECK_STRING_VAL(val[0], "43"); - `CHECK_STRING_VAL(val[1], "44"); - val[0] = "44"; - val[1] = "45"; - endfunction - function void e_string_2d(inout string val[3][2]); - `CHECK_STRING_VAL(val[0][1], "45"); - `CHECK_STRING_VAL(val[1][1], "46"); - `CHECK_STRING_VAL(val[2][1], "47"); - val[0][1] = "46"; - val[1][1] = "47"; - val[2][1] = "48"; - endfunction - function void e_string_3d(inout string_array_t val); - `CHECK_STRING_VAL(val[0][0][0], "48"); - `CHECK_STRING_VAL(val[1][0][0], "49"); - `CHECK_STRING_VAL(val[2][0][0], "50"); - `CHECK_STRING_VAL(val[3][0][0], "51"); - val[0][0][0] = "49"; - val[1][0][0] = "50"; - val[2][0][0] = "51"; - val[3][0][0] = "52"; - endfunction - function void e_string_1d1(inout string val[1]); - `CHECK_STRING_VAL(val[0], "52"); - val[0] = "53"; - endfunction - function void e_string_2d1(inout string val[1][1]); - `CHECK_STRING_VAL(val[0][0], "53"); - val[0][0] = "54"; - endfunction - function void e_string_3d1(inout string_array1_t val); - `CHECK_STRING_VAL(val[0][0][0], "54"); - val[0][0][0] = "55"; - endfunction + function void e_string_0d(inout string val); + `CHECK_STRING_VAL(val, "42"); + val = "43"; + endfunction + function void e_string_1d(inout string val[2]); + `CHECK_STRING_VAL(val[0], "43"); + `CHECK_STRING_VAL(val[1], "44"); + val[0] = "44"; + val[1] = "45"; + endfunction + function void e_string_2d(inout string val[3][2]); + `CHECK_STRING_VAL(val[0][1], "45"); + `CHECK_STRING_VAL(val[1][1], "46"); + `CHECK_STRING_VAL(val[2][1], "47"); + val[0][1] = "46"; + val[1][1] = "47"; + val[2][1] = "48"; + endfunction + function void e_string_3d(inout string_array_t val); + `CHECK_STRING_VAL(val[0][0][0], "48"); + `CHECK_STRING_VAL(val[1][0][0], "49"); + `CHECK_STRING_VAL(val[2][0][0], "50"); + `CHECK_STRING_VAL(val[3][0][0], "51"); + val[0][0][0] = "49"; + val[1][0][0] = "50"; + val[2][0][0] = "51"; + val[3][0][0] = "52"; + endfunction + function void e_string_1d1(inout string val[1]); + `CHECK_STRING_VAL(val[0], "52"); + val[0] = "53"; + endfunction + function void e_string_2d1(inout string val[1][1]); + `CHECK_STRING_VAL(val[0][0], "53"); + val[0][0] = "54"; + endfunction + function void e_string_3d1(inout string_array1_t val); + `CHECK_STRING_VAL(val[0][0][0], "54"); + val[0][0][0] = "55"; + endfunction - function void e_bit1_0d(inout bit val); `UPDATE_0D(val); endfunction - function void e_bit1_1d(inout bit val[2]); `UPDATE_1D(val); endfunction - function void e_bit1_2d(inout bit val[3][2]); `UPDATE_2D(val); endfunction - function void e_bit1_3d(inout bit1_array_t val); `UPDATE_3D(val); endfunction - function void e_bit1_1d1(inout bit val[1]); `UPDATE_1D1(val); endfunction - function void e_bit1_2d1(inout bit val[1][1]); `UPDATE_2D1(val); endfunction - function void e_bit1_3d1(inout bit1_array1_t val); `UPDATE_3D1(val); endfunction + function void e_bit1_0d(inout bit val); `UPDATE_0D(val); endfunction + function void e_bit1_1d(inout bit val[2]); `UPDATE_1D(val); endfunction + function void e_bit1_2d(inout bit val[3][2]); `UPDATE_2D(val); endfunction + function void e_bit1_3d(inout bit1_array_t val); `UPDATE_3D(val); endfunction + function void e_bit1_1d1(inout bit val[1]); `UPDATE_1D1(val); endfunction + function void e_bit1_2d1(inout bit val[1][1]); `UPDATE_2D1(val); endfunction + function void e_bit1_3d1(inout bit1_array1_t val); `UPDATE_3D1(val); endfunction - function void e_bit7_0d(inout bit[6:0] val); `UPDATE_0D(val); endfunction - function void e_bit7_1d(inout bit[6:0] val[2]); `UPDATE_1D(val); endfunction - function void e_bit7_2d(inout bit[6:0] val[3][2]); `UPDATE_2D(val); endfunction - function void e_bit7_3d(inout bit7_array_t val); `UPDATE_3D(val); endfunction - function void e_bit7_1d1(inout bit[6:0] val[1]); `UPDATE_1D1(val); endfunction - function void e_bit7_2d1(inout bit[6:0] val[1][1]); `UPDATE_2D1(val); endfunction - function void e_bit7_3d1(inout bit7_array1_t val); `UPDATE_3D1(val); endfunction + function void e_bit7_0d(inout bit[6:0] val); `UPDATE_0D(val); endfunction + function void e_bit7_1d(inout bit[6:0] val[2]); `UPDATE_1D(val); endfunction + function void e_bit7_2d(inout bit[6:0] val[3][2]); `UPDATE_2D(val); endfunction + function void e_bit7_3d(inout bit7_array_t val); `UPDATE_3D(val); endfunction + function void e_bit7_1d1(inout bit[6:0] val[1]); `UPDATE_1D1(val); endfunction + function void e_bit7_2d1(inout bit[6:0] val[1][1]); `UPDATE_2D1(val); endfunction + function void e_bit7_3d1(inout bit7_array1_t val); `UPDATE_3D1(val); endfunction - function void e_bit121_0d(inout bit[120:0] val); `UPDATE_0D(val); endfunction - function void e_bit121_1d(inout bit[120:0] val[2]); `UPDATE_1D(val); endfunction - function void e_bit121_2d(inout bit[120:0] val[3][2]); `UPDATE_2D(val); endfunction - function void e_bit121_3d(inout bit121_array_t val); `UPDATE_3D(val); endfunction - function void e_bit121_1d1(inout bit[120:0] val[1]); `UPDATE_1D1(val); endfunction - function void e_bit121_2d1(inout bit[120:0] val[1][1]); `UPDATE_2D1(val); endfunction - function void e_bit121_3d1(inout bit121_array1_t val); `UPDATE_3D1(val); endfunction + function void e_bit121_0d(inout bit[120:0] val); `UPDATE_0D(val); endfunction + function void e_bit121_1d(inout bit[120:0] val[2]); `UPDATE_1D(val); endfunction + function void e_bit121_2d(inout bit[120:0] val[3][2]); `UPDATE_2D(val); endfunction + function void e_bit121_3d(inout bit121_array_t val); `UPDATE_3D(val); endfunction + function void e_bit121_1d1(inout bit[120:0] val[1]); `UPDATE_1D1(val); endfunction + function void e_bit121_2d1(inout bit[120:0] val[1][1]); `UPDATE_2D1(val); endfunction + function void e_bit121_3d1(inout bit121_array1_t val); `UPDATE_3D1(val); endfunction - function void e_logic1_0d(inout logic val); `UPDATE_0D(val); endfunction - function void e_logic1_1d(inout logic val[2]); `UPDATE_1D(val); endfunction - function void e_logic1_2d(inout logic val[3][2]); `UPDATE_2D(val); endfunction - function void e_logic1_3d(inout logic1_array_t val); `UPDATE_3D(val); endfunction - function void e_logic1_1d1(inout logic val[1]); `UPDATE_1D1(val); endfunction - function void e_logic1_2d1(inout logic val[1][1]); `UPDATE_2D1(val); endfunction - function void e_logic1_3d1(inout logic1_array1_t val); `UPDATE_3D1(val); endfunction + function void e_logic1_0d(inout logic val); `UPDATE_0D(val); endfunction + function void e_logic1_1d(inout logic val[2]); `UPDATE_1D(val); endfunction + function void e_logic1_2d(inout logic val[3][2]); `UPDATE_2D(val); endfunction + function void e_logic1_3d(inout logic1_array_t val); `UPDATE_3D(val); endfunction + function void e_logic1_1d1(inout logic val[1]); `UPDATE_1D1(val); endfunction + function void e_logic1_2d1(inout logic val[1][1]); `UPDATE_2D1(val); endfunction + function void e_logic1_3d1(inout logic1_array1_t val); `UPDATE_3D1(val); endfunction - function void e_logic7_0d(inout logic[6:0] val); `UPDATE_0D(val); endfunction - function void e_logic7_1d(inout logic[6:0] val[2]); `UPDATE_1D(val); endfunction - function void e_logic7_2d(inout logic[6:0] val[3][2]); `UPDATE_2D(val); endfunction - function void e_logic7_3d(inout logic7_array_t val); `UPDATE_3D(val); endfunction - function void e_logic7_1d1(inout logic[6:0] val[1]); `UPDATE_1D1(val); endfunction - function void e_logic7_2d1(inout logic[6:0] val[1][1]); `UPDATE_2D1(val); endfunction - function void e_logic7_3d1(inout logic7_array1_t val); `UPDATE_3D1(val); endfunction + function void e_logic7_0d(inout logic[6:0] val); `UPDATE_0D(val); endfunction + function void e_logic7_1d(inout logic[6:0] val[2]); `UPDATE_1D(val); endfunction + function void e_logic7_2d(inout logic[6:0] val[3][2]); `UPDATE_2D(val); endfunction + function void e_logic7_3d(inout logic7_array_t val); `UPDATE_3D(val); endfunction + function void e_logic7_1d1(inout logic[6:0] val[1]); `UPDATE_1D1(val); endfunction + function void e_logic7_2d1(inout logic[6:0] val[1][1]); `UPDATE_2D1(val); endfunction + function void e_logic7_3d1(inout logic7_array1_t val); `UPDATE_3D1(val); endfunction - function void e_logic121_0d(inout logic[120:0] val); `UPDATE_0D(val); endfunction - function void e_logic121_1d(inout logic[120:0] val[2]); `UPDATE_1D(val); endfunction - function void e_logic121_2d(inout logic[120:0] val[3][2]); `UPDATE_2D(val); endfunction - function void e_logic121_3d(inout logic121_array_t val); `UPDATE_3D(val); endfunction - function void e_logic121_1d1(inout logic[120:0] val[1]); `UPDATE_1D1(val); endfunction - function void e_logic121_2d1(inout logic[120:0] val[1][1]); `UPDATE_2D1(val); endfunction - function void e_logic121_3d1(inout logic121_array1_t val); `UPDATE_3D1(val); endfunction + function void e_logic121_0d(inout logic[120:0] val); `UPDATE_0D(val); endfunction + function void e_logic121_1d(inout logic[120:0] val[2]); `UPDATE_1D(val); endfunction + function void e_logic121_2d(inout logic[120:0] val[3][2]); `UPDATE_2D(val); endfunction + function void e_logic121_3d(inout logic121_array_t val); `UPDATE_3D(val); endfunction + function void e_logic121_1d1(inout logic[120:0] val[1]); `UPDATE_1D1(val); endfunction + function void e_logic121_2d1(inout logic[120:0] val[1][1]); `UPDATE_2D1(val); endfunction + function void e_logic121_3d1(inout logic121_array1_t val); `UPDATE_3D1(val); endfunction - function void e_pack_struct_0d(inout pack_struct_t val); `UPDATE_0D(val); endfunction - function void e_pack_struct_1d(inout pack_struct_t val[2]); `UPDATE_1D(val); endfunction - function void e_pack_struct_2d(inout pack_struct_t val[3][2]); `UPDATE_2D(val); endfunction - function void e_pack_struct_3d(inout pack_struct_array_t val); `UPDATE_3D(val); endfunction - function void e_pack_struct_1d1(inout pack_struct_t val[1]); `UPDATE_1D1(val); endfunction - function void e_pack_struct_2d1(inout pack_struct_t val[1][1]); `UPDATE_2D1(val); endfunction - function void e_pack_struct_3d1(inout pack_struct_array1_t val); `UPDATE_3D1(val); endfunction + function void e_pack_struct_0d(inout pack_struct_t val); `UPDATE_0D(val); endfunction + function void e_pack_struct_1d(inout pack_struct_t val[2]); `UPDATE_1D(val); endfunction + function void e_pack_struct_2d(inout pack_struct_t val[3][2]); `UPDATE_2D(val); endfunction + function void e_pack_struct_3d(inout pack_struct_array_t val); `UPDATE_3D(val); endfunction + function void e_pack_struct_1d1(inout pack_struct_t val[1]); `UPDATE_1D1(val); endfunction + function void e_pack_struct_2d1(inout pack_struct_t val[1][1]); `UPDATE_2D1(val); endfunction + function void e_pack_struct_3d1(inout pack_struct_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT - function void e_unpack_struct_0d(inout unpack_struct_t val); - `CHECK_VAL(val.val, 42); - val.val = 43; - endfunction - function void e_unpack_struct_1d(inout unpack_struct_t val[2]); - `CHECK_VAL(val[0].val, 43); - `CHECK_VAL(val[1].val, 44); - val[0].val = 44; - val[1].val = 45; - endfunction - function void e_unpack_struct_2d(inout unpack_struct_t val[3][2]); - `CHECK_VAL(val[0][1].val, 45); - `CHECK_VAL(val[1][1].val, 46); - `CHECK_VAL(val[2][1].val, 47); - val[0][1].val = 46; - val[1][1].val = 47; - val[2][1].val = 48; - endfunction - function void e_unpack_struct_3d(inout unpack_struct_array_t val); - `CHECK_VAL(val[0][0][0].val, 48); - `CHECK_VAL(val[1][0][0].val, 49); - `CHECK_VAL(val[2][0][0].val, 50); - `CHECK_VAL(val[3][0][0].val, 51); - val[0][0][0].val = 49; - val[1][0][0].val = 50; - val[2][0][0].val = 51; - val[3][0][0].val = 52; - endfunction - function void e_unpack_struct_1d1(inout unpack_struct_t val[1]); - `CHECK_VAL(val[0].val, 52); - val[0].val = 53; - endfunction - function void e_unpack_struct_2d1(inout unpack_struct_t val[1][1]); - `CHECK_VAL(val[0][0].val, 53); - val[0][0].val = 54; - endfunction - function void e_unpack_struct_3d1(inout unpack_struct_array1_t val); - `CHECK_VAL(val[0][0][0].val, 54); - val[0][0][0].val = 55; - endfunction + function void e_unpack_struct_0d(inout unpack_struct_t val); + `CHECK_VAL(val.val, 42); + val.val = 43; + endfunction + function void e_unpack_struct_1d(inout unpack_struct_t val[2]); + `CHECK_VAL(val[0].val, 43); + `CHECK_VAL(val[1].val, 44); + val[0].val = 44; + val[1].val = 45; + endfunction + function void e_unpack_struct_2d(inout unpack_struct_t val[3][2]); + `CHECK_VAL(val[0][1].val, 45); + `CHECK_VAL(val[1][1].val, 46); + `CHECK_VAL(val[2][1].val, 47); + val[0][1].val = 46; + val[1][1].val = 47; + val[2][1].val = 48; + endfunction + function void e_unpack_struct_3d(inout unpack_struct_array_t val); + `CHECK_VAL(val[0][0][0].val, 48); + `CHECK_VAL(val[1][0][0].val, 49); + `CHECK_VAL(val[2][0][0].val, 50); + `CHECK_VAL(val[3][0][0].val, 51); + val[0][0][0].val = 49; + val[1][0][0].val = 50; + val[2][0][0].val = 51; + val[3][0][0].val = 52; + endfunction + function void e_unpack_struct_1d1(inout unpack_struct_t val[1]); + `CHECK_VAL(val[0].val, 52); + val[0].val = 53; + endfunction + function void e_unpack_struct_2d1(inout unpack_struct_t val[1][1]); + `CHECK_VAL(val[0][0].val, 53); + val[0][0].val = 54; + endfunction + function void e_unpack_struct_3d1(inout unpack_struct_array1_t val); + `CHECK_VAL(val[0][0][0].val, 54); + val[0][0][0].val = 55; + endfunction `endif - //====================================================================== - // Invoke all imported functions - //====================================================================== + //====================================================================== + // Invoke all imported functions + //====================================================================== - import "DPI-C" context function void check_exports(); - initial begin - byte_t byte_array_0d; - byte_t byte_array_1d[2]; - byte_t byte_array_2d[3][2]; - byte_array_t byte_array_3d; - byte_t byte_array_1d1[1]; - byte_t byte_array_2d1[1][1]; - byte_array1_t byte_array_3d1; + import "DPI-C" context function void check_exports(); + initial begin + byte_t byte_array_0d; + byte_t byte_array_1d[2]; + byte_t byte_array_2d[3][2]; + byte_array_t byte_array_3d; + byte_t byte_array_1d1[1]; + byte_t byte_array_2d1[1][1]; + byte_array1_t byte_array_3d1; - byte_unsigned_t byte_unsigned_array_0d; - byte_unsigned_t byte_unsigned_array_1d[2]; - byte_unsigned_t byte_unsigned_array_2d[3][2]; - byte_unsigned_array_t byte_unsigned_array_3d; - byte_unsigned_t byte_unsigned_array_1d1[1]; - byte_unsigned_t byte_unsigned_array_2d1[1][1]; - byte_unsigned_array1_t byte_unsigned_array_3d1; + byte_unsigned_t byte_unsigned_array_0d; + byte_unsigned_t byte_unsigned_array_1d[2]; + byte_unsigned_t byte_unsigned_array_2d[3][2]; + byte_unsigned_array_t byte_unsigned_array_3d; + byte_unsigned_t byte_unsigned_array_1d1[1]; + byte_unsigned_t byte_unsigned_array_2d1[1][1]; + byte_unsigned_array1_t byte_unsigned_array_3d1; - shortint_t shortint_array_0d; - shortint_t shortint_array_1d[2]; - shortint_t shortint_array_2d[3][2]; - shortint_array_t shortint_array_3d; - shortint_t shortint_array_1d1[1]; - shortint_t shortint_array_2d1[1][1]; - shortint_array1_t shortint_array_3d1; + shortint_t shortint_array_0d; + shortint_t shortint_array_1d[2]; + shortint_t shortint_array_2d[3][2]; + shortint_array_t shortint_array_3d; + shortint_t shortint_array_1d1[1]; + shortint_t shortint_array_2d1[1][1]; + shortint_array1_t shortint_array_3d1; - shortint_unsigned_t shortint_unsigned_array_0d; - shortint_unsigned_t shortint_unsigned_array_1d[2]; - shortint_unsigned_t shortint_unsigned_array_2d[3][2]; - shortint_unsigned_array_t shortint_unsigned_array_3d; - shortint_unsigned_t shortint_unsigned_array_1d1[1]; - shortint_unsigned_t shortint_unsigned_array_2d1[1][1]; - shortint_unsigned_array1_t shortint_unsigned_array_3d1; + shortint_unsigned_t shortint_unsigned_array_0d; + shortint_unsigned_t shortint_unsigned_array_1d[2]; + shortint_unsigned_t shortint_unsigned_array_2d[3][2]; + shortint_unsigned_array_t shortint_unsigned_array_3d; + shortint_unsigned_t shortint_unsigned_array_1d1[1]; + shortint_unsigned_t shortint_unsigned_array_2d1[1][1]; + shortint_unsigned_array1_t shortint_unsigned_array_3d1; - int_t int_array_0d; - int_t int_array_1d[2]; - int_t int_array_2d[3][2]; - int_array_t int_array_3d; - int_t int_array_1d1[1]; - int_t int_array_2d1[1][1]; - int_array1_t int_array_3d1; + int_t int_array_0d; + int_t int_array_1d[2]; + int_t int_array_2d[3][2]; + int_array_t int_array_3d; + int_t int_array_1d1[1]; + int_t int_array_2d1[1][1]; + int_array1_t int_array_3d1; - int_unsigned_t int_unsigned_array_0d; - int_unsigned_t int_unsigned_array_1d[2]; - int_unsigned_t int_unsigned_array_2d[3][2]; - int_unsigned_array_t int_unsigned_array_3d; - int_unsigned_t int_unsigned_array_1d1[1]; - int_unsigned_t int_unsigned_array_2d1[1][1]; - int_unsigned_array1_t int_unsigned_array_3d1; + int_unsigned_t int_unsigned_array_0d; + int_unsigned_t int_unsigned_array_1d[2]; + int_unsigned_t int_unsigned_array_2d[3][2]; + int_unsigned_array_t int_unsigned_array_3d; + int_unsigned_t int_unsigned_array_1d1[1]; + int_unsigned_t int_unsigned_array_2d1[1][1]; + int_unsigned_array1_t int_unsigned_array_3d1; - longint_t longint_array_0d; - longint_t longint_array_1d[2]; - longint_t longint_array_2d[3][2]; - longint_array_t longint_array_3d; - longint_t longint_array_1d1[1]; - longint_t longint_array_2d1[1][1]; - longint_array1_t longint_array_3d1; + longint_t longint_array_0d; + longint_t longint_array_1d[2]; + longint_t longint_array_2d[3][2]; + longint_array_t longint_array_3d; + longint_t longint_array_1d1[1]; + longint_t longint_array_2d1[1][1]; + longint_array1_t longint_array_3d1; - longint_unsigned_t longint_unsigned_array_0d; - longint_unsigned_t longint_unsigned_array_1d[2]; - longint_unsigned_t longint_unsigned_array_2d[3][2]; - longint_unsigned_array_t longint_unsigned_array_3d; - longint_unsigned_t longint_unsigned_array_1d1[1]; - longint_unsigned_t longint_unsigned_array_2d1[1][1]; - longint_unsigned_array1_t longint_unsigned_array_3d1; + longint_unsigned_t longint_unsigned_array_0d; + longint_unsigned_t longint_unsigned_array_1d[2]; + longint_unsigned_t longint_unsigned_array_2d[3][2]; + longint_unsigned_array_t longint_unsigned_array_3d; + longint_unsigned_t longint_unsigned_array_1d1[1]; + longint_unsigned_t longint_unsigned_array_2d1[1][1]; + longint_unsigned_array1_t longint_unsigned_array_3d1; `ifndef NO_TIME - time_t time_array_0d; - time_t time_array_1d[2]; - time_t time_array_2d[3][2]; - time_array_t time_array_3d; - time_t time_array_1d1[1]; - time_t time_array_2d1[1][1]; - time_array1_t time_array_3d1; + time_t time_array_0d; + time_t time_array_1d[2]; + time_t time_array_2d[3][2]; + time_array_t time_array_3d; + time_t time_array_1d1[1]; + time_t time_array_2d1[1][1]; + time_array1_t time_array_3d1; `endif `ifndef NO_INTEGER - integer_t integer_array_0d; - integer_t integer_array_1d[2]; - integer_t integer_array_2d[3][2]; - integer_array_t integer_array_3d; - integer_t integer_array_1d1[1]; - integer_t integer_array_2d1[1][1]; - integer_array1_t integer_array_3d1; + integer_t integer_array_0d; + integer_t integer_array_1d[2]; + integer_t integer_array_2d[3][2]; + integer_array_t integer_array_3d; + integer_t integer_array_1d1[1]; + integer_t integer_array_2d1[1][1]; + integer_array1_t integer_array_3d1; `endif - real_t real_array_0d; - real_t real_array_1d[2]; - real_t real_array_2d[3][2]; - real_array_t real_array_3d; - real_t real_array_1d1[1]; - real_t real_array_2d1[1][1]; - real_array1_t real_array_3d1; + real_t real_array_0d; + real_t real_array_1d[2]; + real_t real_array_2d[3][2]; + real_array_t real_array_3d; + real_t real_array_1d1[1]; + real_t real_array_2d1[1][1]; + real_array1_t real_array_3d1; `ifndef NO_SHORTREAL - shortreal_t shortreal_array_0d; - shortreal_t shortreal_array_1d[2]; - shortreal_t shortreal_array_2d[3][2]; - shortreal_array_t shortreal_array_3d; - shortreal_t shortreal_array_1d1[1]; - shortreal_t shortreal_array_2d1[1][1]; - shortreal_array1_t shortreal_array_3d1; + shortreal_t shortreal_array_0d; + shortreal_t shortreal_array_1d[2]; + shortreal_t shortreal_array_2d[3][2]; + shortreal_array_t shortreal_array_3d; + shortreal_t shortreal_array_1d1[1]; + shortreal_t shortreal_array_2d1[1][1]; + shortreal_array1_t shortreal_array_3d1; `endif - chandle_t chandle_array_0d; - chandle_t chandle_array_1d[2]; - chandle_t chandle_array_2d[3][2]; - chandle_array_t chandle_array_3d; - chandle_t chandle_array_1d1[1]; - chandle_t chandle_array_2d1[1][1]; - chandle_array1_t chandle_array_3d1; + chandle_t chandle_array_0d; + chandle_t chandle_array_1d[2]; + chandle_t chandle_array_2d[3][2]; + chandle_array_t chandle_array_3d; + chandle_t chandle_array_1d1[1]; + chandle_t chandle_array_2d1[1][1]; + chandle_array1_t chandle_array_3d1; - string_t string_array_0d; - string_t string_array_1d[2]; - string_t string_array_2d[3][2]; - string_array_t string_array_3d; - string_t string_array_1d1[1]; - string_t string_array_2d1[1][1]; - string_array1_t string_array_3d1; + string_t string_array_0d; + string_t string_array_1d[2]; + string_t string_array_2d[3][2]; + string_array_t string_array_3d; + string_t string_array_1d1[1]; + string_t string_array_2d1[1][1]; + string_array1_t string_array_3d1; - bit1_t bit1_array_0d; - bit1_t bit1_array_1d[2]; - bit1_t bit1_array_2d[3][2]; - bit1_array_t bit1_array_3d; - bit1_t bit1_array_1d1[1]; - bit1_t bit1_array_2d1[1][1]; - bit1_array1_t bit1_array_3d1; + bit1_t bit1_array_0d; + bit1_t bit1_array_1d[2]; + bit1_t bit1_array_2d[3][2]; + bit1_array_t bit1_array_3d; + bit1_t bit1_array_1d1[1]; + bit1_t bit1_array_2d1[1][1]; + bit1_array1_t bit1_array_3d1; - bit7_t bit7_array_0d; - bit7_t bit7_array_1d[2]; - bit7_t bit7_array_2d[3][2]; - bit7_array_t bit7_array_3d; - bit7_t bit7_array_1d1[1]; - bit7_t bit7_array_2d1[1][1]; - bit7_array1_t bit7_array_3d1; + bit7_t bit7_array_0d; + bit7_t bit7_array_1d[2]; + bit7_t bit7_array_2d[3][2]; + bit7_array_t bit7_array_3d; + bit7_t bit7_array_1d1[1]; + bit7_t bit7_array_2d1[1][1]; + bit7_array1_t bit7_array_3d1; - bit121_t bit121_array_0d; - bit121_t bit121_array_1d[2]; - bit121_t bit121_array_2d[3][2]; - bit121_array_t bit121_array_3d; - bit121_t bit121_array_1d1[1]; - bit121_t bit121_array_2d1[1][1]; - bit121_array1_t bit121_array_3d1; + bit121_t bit121_array_0d; + bit121_t bit121_array_1d[2]; + bit121_t bit121_array_2d[3][2]; + bit121_array_t bit121_array_3d; + bit121_t bit121_array_1d1[1]; + bit121_t bit121_array_2d1[1][1]; + bit121_array1_t bit121_array_3d1; - logic1_t logic1_array_0d; - logic1_t logic1_array_1d[2]; - logic1_t logic1_array_2d[3][2]; - logic1_array_t logic1_array_3d; - logic1_t logic1_array_1d1[1]; - logic1_t logic1_array_2d1[1][1]; - logic1_array1_t logic1_array_3d1; + logic1_t logic1_array_0d; + logic1_t logic1_array_1d[2]; + logic1_t logic1_array_2d[3][2]; + logic1_array_t logic1_array_3d; + logic1_t logic1_array_1d1[1]; + logic1_t logic1_array_2d1[1][1]; + logic1_array1_t logic1_array_3d1; - logic7_t logic7_array_0d; - logic7_t logic7_array_1d[2]; - logic7_t logic7_array_2d[3][2]; - logic7_array_t logic7_array_3d; - logic7_t logic7_array_1d1[1]; - logic7_t logic7_array_2d1[1][1]; - logic7_array1_t logic7_array_3d1; + logic7_t logic7_array_0d; + logic7_t logic7_array_1d[2]; + logic7_t logic7_array_2d[3][2]; + logic7_array_t logic7_array_3d; + logic7_t logic7_array_1d1[1]; + logic7_t logic7_array_2d1[1][1]; + logic7_array1_t logic7_array_3d1; - logic121_t logic121_array_0d; - logic121_t logic121_array_1d[2]; - logic121_t logic121_array_2d[3][2]; - logic121_array_t logic121_array_3d; - logic121_t logic121_array_1d1[1]; - logic121_t logic121_array_2d1[1][1]; - logic121_array1_t logic121_array_3d1; + logic121_t logic121_array_0d; + logic121_t logic121_array_1d[2]; + logic121_t logic121_array_2d[3][2]; + logic121_array_t logic121_array_3d; + logic121_t logic121_array_1d1[1]; + logic121_t logic121_array_2d1[1][1]; + logic121_array1_t logic121_array_3d1; - pack_struct_t pack_struct_array_0d; - pack_struct_t pack_struct_array_1d[2]; - pack_struct_t pack_struct_array_2d[3][2]; - pack_struct_array_t pack_struct_array_3d; - pack_struct_t pack_struct_array_1d1[1]; - pack_struct_t pack_struct_array_2d1[1][1]; - pack_struct_array1_t pack_struct_array_3d1; + pack_struct_t pack_struct_array_0d; + pack_struct_t pack_struct_array_1d[2]; + pack_struct_t pack_struct_array_2d[3][2]; + pack_struct_array_t pack_struct_array_3d; + pack_struct_t pack_struct_array_1d1[1]; + pack_struct_t pack_struct_array_2d1[1][1]; + pack_struct_array1_t pack_struct_array_3d1; `ifndef NO_UNPACK_STRUCT - unpack_struct_array_t unpack_struct_array_3d; - unpack_struct_array1_t unpack_struct_array_3d1; + unpack_struct_array_t unpack_struct_array_3d; + unpack_struct_array1_t unpack_struct_array_3d1; `endif - `SET_VALUE_0D(byte_array_0d); - `SET_VALUE_1D(byte_array_1d); - `SET_VALUE_2D(byte_array_2d); - `SET_VALUE_3D(byte_array_3d); + `SET_VALUE_0D(byte_array_0d); + `SET_VALUE_1D(byte_array_1d); + `SET_VALUE_2D(byte_array_2d); + `SET_VALUE_3D(byte_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_byte_0d(byte_array_3d[3][2][1]); - `CHECK_0D(byte_array_3d[3][2][1]); - i_byte_1d(byte_array_3d[2][1]); - `CHECK_1D(byte_array_3d[2][1]); - i_byte_2d(byte_array_3d[1]); - `CHECK_2D(byte_array_3d[1]); + i_byte_0d(byte_array_3d[3][2][1]); + `CHECK_0D(byte_array_3d[3][2][1]); + i_byte_1d(byte_array_3d[2][1]); + `CHECK_1D(byte_array_3d[2][1]); + i_byte_2d(byte_array_3d[1]); + `CHECK_2D(byte_array_3d[1]); `endif - i_byte_0d(byte_array_0d); - `CHECK_0D(byte_array_0d); - i_byte_1d(byte_array_1d); - `CHECK_1D(byte_array_1d); - i_byte_2d(byte_array_2d); - `CHECK_2D(byte_array_2d); - i_byte_3d(byte_array_3d); - `CHECK_3D(byte_array_3d); + i_byte_0d(byte_array_0d); + `CHECK_0D(byte_array_0d); + i_byte_1d(byte_array_1d); + `CHECK_1D(byte_array_1d); + i_byte_2d(byte_array_2d); + `CHECK_2D(byte_array_2d); + i_byte_3d(byte_array_3d); + `CHECK_3D(byte_array_3d); - `SET_VALUE_1D1(byte_array_1d1); - `SET_VALUE_2D1(byte_array_2d1); - `SET_VALUE_3D1(byte_array_3d1); - i_byte_1d1(byte_array_1d1); - `CHECK_1D1(byte_array_1d1); - i_byte_2d1(byte_array_2d1); - `CHECK_2D1(byte_array_2d1); - i_byte_3d1(byte_array_3d1); - `CHECK_3D1(byte_array_3d1); + `SET_VALUE_1D1(byte_array_1d1); + `SET_VALUE_2D1(byte_array_2d1); + `SET_VALUE_3D1(byte_array_3d1); + i_byte_1d1(byte_array_1d1); + `CHECK_1D1(byte_array_1d1); + i_byte_2d1(byte_array_2d1); + `CHECK_2D1(byte_array_2d1); + i_byte_3d1(byte_array_3d1); + `CHECK_3D1(byte_array_3d1); - `SET_VALUE_0D(byte_unsigned_array_0d); - `SET_VALUE_1D(byte_unsigned_array_1d); - `SET_VALUE_2D(byte_unsigned_array_2d); - `SET_VALUE_3D(byte_unsigned_array_3d); + `SET_VALUE_0D(byte_unsigned_array_0d); + `SET_VALUE_1D(byte_unsigned_array_1d); + `SET_VALUE_2D(byte_unsigned_array_2d); + `SET_VALUE_3D(byte_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_byte_unsigned_0d(byte_unsigned_array_3d[3][2][1]); - `CHECK_0D(byte_unsigned_array_3d[3][2][1]); - i_byte_unsigned_1d(byte_unsigned_array_3d[2][1]); - `CHECK_1D(byte_unsigned_array_3d[2][1]); - i_byte_unsigned_2d(byte_unsigned_array_3d[1]); - `CHECK_2D(byte_unsigned_array_3d[1]); + i_byte_unsigned_0d(byte_unsigned_array_3d[3][2][1]); + `CHECK_0D(byte_unsigned_array_3d[3][2][1]); + i_byte_unsigned_1d(byte_unsigned_array_3d[2][1]); + `CHECK_1D(byte_unsigned_array_3d[2][1]); + i_byte_unsigned_2d(byte_unsigned_array_3d[1]); + `CHECK_2D(byte_unsigned_array_3d[1]); `endif - i_byte_unsigned_0d(byte_unsigned_array_0d); - `CHECK_0D(byte_unsigned_array_0d); - i_byte_unsigned_1d(byte_unsigned_array_1d); - `CHECK_1D(byte_unsigned_array_1d); - i_byte_unsigned_2d(byte_unsigned_array_2d); - `CHECK_2D(byte_unsigned_array_2d); - i_byte_unsigned_3d(byte_unsigned_array_3d); - `CHECK_3D(byte_unsigned_array_3d); + i_byte_unsigned_0d(byte_unsigned_array_0d); + `CHECK_0D(byte_unsigned_array_0d); + i_byte_unsigned_1d(byte_unsigned_array_1d); + `CHECK_1D(byte_unsigned_array_1d); + i_byte_unsigned_2d(byte_unsigned_array_2d); + `CHECK_2D(byte_unsigned_array_2d); + i_byte_unsigned_3d(byte_unsigned_array_3d); + `CHECK_3D(byte_unsigned_array_3d); - `SET_VALUE_1D1(byte_unsigned_array_1d1); - `SET_VALUE_2D1(byte_unsigned_array_2d1); - `SET_VALUE_3D1(byte_unsigned_array_3d1); - i_byte_unsigned_1d1(byte_unsigned_array_1d1); - `CHECK_1D1(byte_unsigned_array_1d1); - i_byte_unsigned_2d1(byte_unsigned_array_2d1); - `CHECK_2D1(byte_unsigned_array_2d1); - i_byte_unsigned_3d1(byte_unsigned_array_3d1); - `CHECK_3D1(byte_unsigned_array_3d1); + `SET_VALUE_1D1(byte_unsigned_array_1d1); + `SET_VALUE_2D1(byte_unsigned_array_2d1); + `SET_VALUE_3D1(byte_unsigned_array_3d1); + i_byte_unsigned_1d1(byte_unsigned_array_1d1); + `CHECK_1D1(byte_unsigned_array_1d1); + i_byte_unsigned_2d1(byte_unsigned_array_2d1); + `CHECK_2D1(byte_unsigned_array_2d1); + i_byte_unsigned_3d1(byte_unsigned_array_3d1); + `CHECK_3D1(byte_unsigned_array_3d1); - `SET_VALUE_0D(shortint_array_0d); - `SET_VALUE_1D(shortint_array_1d); - `SET_VALUE_2D(shortint_array_2d); - `SET_VALUE_3D(shortint_array_3d); + `SET_VALUE_0D(shortint_array_0d); + `SET_VALUE_1D(shortint_array_1d); + `SET_VALUE_2D(shortint_array_2d); + `SET_VALUE_3D(shortint_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_shortint_0d(shortint_array_3d[3][2][1]); - `CHECK_0D(shortint_array_3d[3][2][1]); - i_shortint_1d(shortint_array_3d[2][1]); - `CHECK_1D(shortint_array_3d[2][1]); - i_shortint_2d(shortint_array_3d[1]); - `CHECK_2D(shortint_array_3d[1]); + i_shortint_0d(shortint_array_3d[3][2][1]); + `CHECK_0D(shortint_array_3d[3][2][1]); + i_shortint_1d(shortint_array_3d[2][1]); + `CHECK_1D(shortint_array_3d[2][1]); + i_shortint_2d(shortint_array_3d[1]); + `CHECK_2D(shortint_array_3d[1]); `endif - i_shortint_0d(shortint_array_0d); - `CHECK_0D(shortint_array_0d); - i_shortint_1d(shortint_array_1d); - `CHECK_1D(shortint_array_1d); - i_shortint_2d(shortint_array_2d); - `CHECK_2D(shortint_array_2d); - i_shortint_3d(shortint_array_3d); - `CHECK_3D(shortint_array_3d); + i_shortint_0d(shortint_array_0d); + `CHECK_0D(shortint_array_0d); + i_shortint_1d(shortint_array_1d); + `CHECK_1D(shortint_array_1d); + i_shortint_2d(shortint_array_2d); + `CHECK_2D(shortint_array_2d); + i_shortint_3d(shortint_array_3d); + `CHECK_3D(shortint_array_3d); - `SET_VALUE_1D1(shortint_array_1d1); - `SET_VALUE_2D1(shortint_array_2d1); - `SET_VALUE_3D1(shortint_array_3d1); - i_shortint_1d1(shortint_array_1d1); - `CHECK_1D1(shortint_array_1d1); - i_shortint_2d1(shortint_array_2d1); - `CHECK_2D1(shortint_array_2d1); - i_shortint_3d1(shortint_array_3d1); - `CHECK_3D1(shortint_array_3d1); + `SET_VALUE_1D1(shortint_array_1d1); + `SET_VALUE_2D1(shortint_array_2d1); + `SET_VALUE_3D1(shortint_array_3d1); + i_shortint_1d1(shortint_array_1d1); + `CHECK_1D1(shortint_array_1d1); + i_shortint_2d1(shortint_array_2d1); + `CHECK_2D1(shortint_array_2d1); + i_shortint_3d1(shortint_array_3d1); + `CHECK_3D1(shortint_array_3d1); - `SET_VALUE_0D(shortint_unsigned_array_0d); - `SET_VALUE_1D(shortint_unsigned_array_1d); - `SET_VALUE_2D(shortint_unsigned_array_2d); - `SET_VALUE_3D(shortint_unsigned_array_3d); + `SET_VALUE_0D(shortint_unsigned_array_0d); + `SET_VALUE_1D(shortint_unsigned_array_1d); + `SET_VALUE_2D(shortint_unsigned_array_2d); + `SET_VALUE_3D(shortint_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_shortint_unsigned_0d(shortint_unsigned_array_3d[3][2][1]); - `CHECK_0D(shortint_unsigned_array_3d[3][2][1]); - i_shortint_unsigned_1d(shortint_unsigned_array_3d[2][1]); - `CHECK_1D(shortint_unsigned_array_3d[2][1]); - i_shortint_unsigned_2d(shortint_unsigned_array_3d[1]); - `CHECK_2D(shortint_unsigned_array_3d[1]); + i_shortint_unsigned_0d(shortint_unsigned_array_3d[3][2][1]); + `CHECK_0D(shortint_unsigned_array_3d[3][2][1]); + i_shortint_unsigned_1d(shortint_unsigned_array_3d[2][1]); + `CHECK_1D(shortint_unsigned_array_3d[2][1]); + i_shortint_unsigned_2d(shortint_unsigned_array_3d[1]); + `CHECK_2D(shortint_unsigned_array_3d[1]); `endif - i_shortint_unsigned_0d(shortint_unsigned_array_0d); - `CHECK_0D(shortint_unsigned_array_0d); - i_shortint_unsigned_1d(shortint_unsigned_array_1d); - `CHECK_1D(shortint_unsigned_array_1d); - i_shortint_unsigned_2d(shortint_unsigned_array_2d); - `CHECK_2D(shortint_unsigned_array_2d); - i_shortint_unsigned_3d(shortint_unsigned_array_3d); - `CHECK_3D(shortint_unsigned_array_3d); + i_shortint_unsigned_0d(shortint_unsigned_array_0d); + `CHECK_0D(shortint_unsigned_array_0d); + i_shortint_unsigned_1d(shortint_unsigned_array_1d); + `CHECK_1D(shortint_unsigned_array_1d); + i_shortint_unsigned_2d(shortint_unsigned_array_2d); + `CHECK_2D(shortint_unsigned_array_2d); + i_shortint_unsigned_3d(shortint_unsigned_array_3d); + `CHECK_3D(shortint_unsigned_array_3d); - `SET_VALUE_1D1(shortint_unsigned_array_1d1); - `SET_VALUE_2D1(shortint_unsigned_array_2d1); - `SET_VALUE_3D1(shortint_unsigned_array_3d1); - i_shortint_unsigned_1d1(shortint_unsigned_array_1d1); - `CHECK_1D1(shortint_unsigned_array_1d1); - i_shortint_unsigned_2d1(shortint_unsigned_array_2d1); - `CHECK_2D1(shortint_unsigned_array_2d1); - i_shortint_unsigned_3d1(shortint_unsigned_array_3d1); - `CHECK_3D1(shortint_unsigned_array_3d1); + `SET_VALUE_1D1(shortint_unsigned_array_1d1); + `SET_VALUE_2D1(shortint_unsigned_array_2d1); + `SET_VALUE_3D1(shortint_unsigned_array_3d1); + i_shortint_unsigned_1d1(shortint_unsigned_array_1d1); + `CHECK_1D1(shortint_unsigned_array_1d1); + i_shortint_unsigned_2d1(shortint_unsigned_array_2d1); + `CHECK_2D1(shortint_unsigned_array_2d1); + i_shortint_unsigned_3d1(shortint_unsigned_array_3d1); + `CHECK_3D1(shortint_unsigned_array_3d1); - `SET_VALUE_0D(int_array_0d); - `SET_VALUE_1D(int_array_1d); - `SET_VALUE_2D(int_array_2d); - `SET_VALUE_3D(int_array_3d); + `SET_VALUE_0D(int_array_0d); + `SET_VALUE_1D(int_array_1d); + `SET_VALUE_2D(int_array_2d); + `SET_VALUE_3D(int_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_int_0d(int_array_3d[3][2][1]); - `CHECK_0D(int_array_3d[3][2][1]); - i_int_1d(int_array_3d[2][1]); - `CHECK_1D(int_array_3d[2][1]); - i_int_2d(int_array_3d[1]); - `CHECK_2D(int_array_3d[1]); + i_int_0d(int_array_3d[3][2][1]); + `CHECK_0D(int_array_3d[3][2][1]); + i_int_1d(int_array_3d[2][1]); + `CHECK_1D(int_array_3d[2][1]); + i_int_2d(int_array_3d[1]); + `CHECK_2D(int_array_3d[1]); `endif - i_int_0d(int_array_0d); - `CHECK_0D(int_array_0d); - i_int_1d(int_array_1d); - `CHECK_1D(int_array_1d); - i_int_2d(int_array_2d); - `CHECK_2D(int_array_2d); - i_int_3d(int_array_3d); - `CHECK_3D(int_array_3d); + i_int_0d(int_array_0d); + `CHECK_0D(int_array_0d); + i_int_1d(int_array_1d); + `CHECK_1D(int_array_1d); + i_int_2d(int_array_2d); + `CHECK_2D(int_array_2d); + i_int_3d(int_array_3d); + `CHECK_3D(int_array_3d); - `SET_VALUE_1D1(int_array_1d1); - `SET_VALUE_2D1(int_array_2d1); - `SET_VALUE_3D1(int_array_3d1); - i_int_1d1(int_array_1d1); - `CHECK_1D1(int_array_1d1); - i_int_2d1(int_array_2d1); - `CHECK_2D1(int_array_2d1); - i_int_3d1(int_array_3d1); - `CHECK_3D1(int_array_3d1); + `SET_VALUE_1D1(int_array_1d1); + `SET_VALUE_2D1(int_array_2d1); + `SET_VALUE_3D1(int_array_3d1); + i_int_1d1(int_array_1d1); + `CHECK_1D1(int_array_1d1); + i_int_2d1(int_array_2d1); + `CHECK_2D1(int_array_2d1); + i_int_3d1(int_array_3d1); + `CHECK_3D1(int_array_3d1); - `SET_VALUE_0D(int_unsigned_array_0d); - `SET_VALUE_1D(int_unsigned_array_1d); - `SET_VALUE_2D(int_unsigned_array_2d); - `SET_VALUE_3D(int_unsigned_array_3d); + `SET_VALUE_0D(int_unsigned_array_0d); + `SET_VALUE_1D(int_unsigned_array_1d); + `SET_VALUE_2D(int_unsigned_array_2d); + `SET_VALUE_3D(int_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_int_unsigned_0d(int_unsigned_array_3d[3][2][1]); - `CHECK_0D(int_unsigned_array_3d[3][2][1]); - i_int_unsigned_1d(int_unsigned_array_3d[2][1]); - `CHECK_1D(int_unsigned_array_3d[2][1]); - i_int_unsigned_2d(int_unsigned_array_3d[1]); - `CHECK_2D(int_unsigned_array_3d[1]); + i_int_unsigned_0d(int_unsigned_array_3d[3][2][1]); + `CHECK_0D(int_unsigned_array_3d[3][2][1]); + i_int_unsigned_1d(int_unsigned_array_3d[2][1]); + `CHECK_1D(int_unsigned_array_3d[2][1]); + i_int_unsigned_2d(int_unsigned_array_3d[1]); + `CHECK_2D(int_unsigned_array_3d[1]); `endif - i_int_unsigned_0d(int_unsigned_array_0d); - `CHECK_0D(int_unsigned_array_0d); - i_int_unsigned_1d(int_unsigned_array_1d); - `CHECK_1D(int_unsigned_array_1d); - i_int_unsigned_2d(int_unsigned_array_2d); - `CHECK_2D(int_unsigned_array_2d); - i_int_unsigned_3d(int_unsigned_array_3d); - `CHECK_3D(int_unsigned_array_3d); + i_int_unsigned_0d(int_unsigned_array_0d); + `CHECK_0D(int_unsigned_array_0d); + i_int_unsigned_1d(int_unsigned_array_1d); + `CHECK_1D(int_unsigned_array_1d); + i_int_unsigned_2d(int_unsigned_array_2d); + `CHECK_2D(int_unsigned_array_2d); + i_int_unsigned_3d(int_unsigned_array_3d); + `CHECK_3D(int_unsigned_array_3d); - `SET_VALUE_1D1(int_unsigned_array_1d1); - `SET_VALUE_2D1(int_unsigned_array_2d1); - `SET_VALUE_3D1(int_unsigned_array_3d1); - i_int_unsigned_1d1(int_unsigned_array_1d1); - `CHECK_1D1(int_unsigned_array_1d1); - i_int_unsigned_2d1(int_unsigned_array_2d1); - `CHECK_2D1(int_unsigned_array_2d1); - i_int_unsigned_3d1(int_unsigned_array_3d1); - `CHECK_3D1(int_unsigned_array_3d1); + `SET_VALUE_1D1(int_unsigned_array_1d1); + `SET_VALUE_2D1(int_unsigned_array_2d1); + `SET_VALUE_3D1(int_unsigned_array_3d1); + i_int_unsigned_1d1(int_unsigned_array_1d1); + `CHECK_1D1(int_unsigned_array_1d1); + i_int_unsigned_2d1(int_unsigned_array_2d1); + `CHECK_2D1(int_unsigned_array_2d1); + i_int_unsigned_3d1(int_unsigned_array_3d1); + `CHECK_3D1(int_unsigned_array_3d1); - `SET_VALUE_0D(longint_array_0d); - `SET_VALUE_1D(longint_array_1d); - `SET_VALUE_2D(longint_array_2d); - `SET_VALUE_3D(longint_array_3d); + `SET_VALUE_0D(longint_array_0d); + `SET_VALUE_1D(longint_array_1d); + `SET_VALUE_2D(longint_array_2d); + `SET_VALUE_3D(longint_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_longint_0d(longint_array_3d[3][2][1]); - `CHECK_0D(longint_array_3d[3][2][1]); - i_longint_1d(longint_array_3d[2][1]); - `CHECK_1D(longint_array_3d[2][1]); - i_longint_2d(longint_array_3d[1]); - `CHECK_2D(longint_array_3d[1]); + i_longint_0d(longint_array_3d[3][2][1]); + `CHECK_0D(longint_array_3d[3][2][1]); + i_longint_1d(longint_array_3d[2][1]); + `CHECK_1D(longint_array_3d[2][1]); + i_longint_2d(longint_array_3d[1]); + `CHECK_2D(longint_array_3d[1]); `endif - i_longint_0d(longint_array_0d); - `CHECK_0D(longint_array_0d); - i_longint_1d(longint_array_1d); - `CHECK_1D(longint_array_1d); - i_longint_2d(longint_array_2d); - `CHECK_2D(longint_array_2d); - i_longint_3d(longint_array_3d); - `CHECK_3D(longint_array_3d); + i_longint_0d(longint_array_0d); + `CHECK_0D(longint_array_0d); + i_longint_1d(longint_array_1d); + `CHECK_1D(longint_array_1d); + i_longint_2d(longint_array_2d); + `CHECK_2D(longint_array_2d); + i_longint_3d(longint_array_3d); + `CHECK_3D(longint_array_3d); - `SET_VALUE_1D1(longint_array_1d1); - `SET_VALUE_2D1(longint_array_2d1); - `SET_VALUE_3D1(longint_array_3d1); - i_longint_1d1(longint_array_1d1); - `CHECK_1D1(longint_array_1d1); - i_longint_2d1(longint_array_2d1); - `CHECK_2D1(longint_array_2d1); - i_longint_3d1(longint_array_3d1); - `CHECK_3D1(longint_array_3d1); + `SET_VALUE_1D1(longint_array_1d1); + `SET_VALUE_2D1(longint_array_2d1); + `SET_VALUE_3D1(longint_array_3d1); + i_longint_1d1(longint_array_1d1); + `CHECK_1D1(longint_array_1d1); + i_longint_2d1(longint_array_2d1); + `CHECK_2D1(longint_array_2d1); + i_longint_3d1(longint_array_3d1); + `CHECK_3D1(longint_array_3d1); - `SET_VALUE_0D(longint_unsigned_array_0d); - `SET_VALUE_1D(longint_unsigned_array_1d); - `SET_VALUE_2D(longint_unsigned_array_2d); - `SET_VALUE_3D(longint_unsigned_array_3d); + `SET_VALUE_0D(longint_unsigned_array_0d); + `SET_VALUE_1D(longint_unsigned_array_1d); + `SET_VALUE_2D(longint_unsigned_array_2d); + `SET_VALUE_3D(longint_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_longint_unsigned_0d(longint_unsigned_array_3d[3][2][1]); - `CHECK_0D(longint_unsigned_array_3d[3][2][1]); - i_longint_unsigned_1d(longint_unsigned_array_3d[2][1]); - `CHECK_1D(longint_unsigned_array_3d[2][1]); - i_longint_unsigned_2d(longint_unsigned_array_3d[1]); - `CHECK_2D(longint_unsigned_array_3d[1]); + i_longint_unsigned_0d(longint_unsigned_array_3d[3][2][1]); + `CHECK_0D(longint_unsigned_array_3d[3][2][1]); + i_longint_unsigned_1d(longint_unsigned_array_3d[2][1]); + `CHECK_1D(longint_unsigned_array_3d[2][1]); + i_longint_unsigned_2d(longint_unsigned_array_3d[1]); + `CHECK_2D(longint_unsigned_array_3d[1]); `endif - i_longint_unsigned_0d(longint_unsigned_array_0d); - `CHECK_0D(longint_unsigned_array_0d); - i_longint_unsigned_1d(longint_unsigned_array_1d); - `CHECK_1D(longint_unsigned_array_1d); - i_longint_unsigned_2d(longint_unsigned_array_2d); - `CHECK_2D(longint_unsigned_array_2d); - i_longint_unsigned_3d(longint_unsigned_array_3d); - `CHECK_3D(longint_unsigned_array_3d); + i_longint_unsigned_0d(longint_unsigned_array_0d); + `CHECK_0D(longint_unsigned_array_0d); + i_longint_unsigned_1d(longint_unsigned_array_1d); + `CHECK_1D(longint_unsigned_array_1d); + i_longint_unsigned_2d(longint_unsigned_array_2d); + `CHECK_2D(longint_unsigned_array_2d); + i_longint_unsigned_3d(longint_unsigned_array_3d); + `CHECK_3D(longint_unsigned_array_3d); - `SET_VALUE_1D1(longint_unsigned_array_1d1); - `SET_VALUE_2D1(longint_unsigned_array_2d1); - `SET_VALUE_3D1(longint_unsigned_array_3d1); - i_longint_unsigned_1d1(longint_unsigned_array_1d1); - `CHECK_1D1(longint_unsigned_array_1d1); - i_longint_unsigned_2d1(longint_unsigned_array_2d1); - `CHECK_2D1(longint_unsigned_array_2d1); - i_longint_unsigned_3d1(longint_unsigned_array_3d1); - `CHECK_3D1(longint_unsigned_array_3d1); + `SET_VALUE_1D1(longint_unsigned_array_1d1); + `SET_VALUE_2D1(longint_unsigned_array_2d1); + `SET_VALUE_3D1(longint_unsigned_array_3d1); + i_longint_unsigned_1d1(longint_unsigned_array_1d1); + `CHECK_1D1(longint_unsigned_array_1d1); + i_longint_unsigned_2d1(longint_unsigned_array_2d1); + `CHECK_2D1(longint_unsigned_array_2d1); + i_longint_unsigned_3d1(longint_unsigned_array_3d1); + `CHECK_3D1(longint_unsigned_array_3d1); `ifndef NO_TIME - `SET_VALUE_0D(time_array_0d); - `SET_VALUE_1D(time_array_1d); - `SET_VALUE_2D(time_array_2d); - `SET_VALUE_3D(time_array_3d); + `SET_VALUE_0D(time_array_0d); + `SET_VALUE_1D(time_array_1d); + `SET_VALUE_2D(time_array_2d); + `SET_VALUE_3D(time_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_time_0d(time_array_3d[3][2][1]); - `CHECK_0D(time_array_3d[3][2][1]); - i_time_1d(time_array_3d[2][1]); - `CHECK_1D(time_array_3d[2][1]); - i_time_2d(time_array_3d[1]); - `CHECK_2D(time_array_3d[1]); + i_time_0d(time_array_3d[3][2][1]); + `CHECK_0D(time_array_3d[3][2][1]); + i_time_1d(time_array_3d[2][1]); + `CHECK_1D(time_array_3d[2][1]); + i_time_2d(time_array_3d[1]); + `CHECK_2D(time_array_3d[1]); `endif - i_time_0d(time_array_0d); - `CHECK_0D(time_array_0d); - i_time_1d(time_array_1d); - `CHECK_1D(time_array_1d); - i_time_2d(time_array_2d); - `CHECK_2D(time_array_2d); - i_time_3d(time_array_3d); - `CHECK_3D(time_array_3d); + i_time_0d(time_array_0d); + `CHECK_0D(time_array_0d); + i_time_1d(time_array_1d); + `CHECK_1D(time_array_1d); + i_time_2d(time_array_2d); + `CHECK_2D(time_array_2d); + i_time_3d(time_array_3d); + `CHECK_3D(time_array_3d); - `SET_VALUE_1D1(time_array_1d1); - `SET_VALUE_2D1(time_array_2d1); - `SET_VALUE_3D1(time_array_3d1); - i_time_1d1(time_array_1d1); - `CHECK_1D1(time_array_1d1); - i_time_2d1(time_array_2d1); - `CHECK_2D1(time_array_2d1); - i_time_3d1(time_array_3d1); - `CHECK_3D1(time_array_3d1); + `SET_VALUE_1D1(time_array_1d1); + `SET_VALUE_2D1(time_array_2d1); + `SET_VALUE_3D1(time_array_3d1); + i_time_1d1(time_array_1d1); + `CHECK_1D1(time_array_1d1); + i_time_2d1(time_array_2d1); + `CHECK_2D1(time_array_2d1); + i_time_3d1(time_array_3d1); + `CHECK_3D1(time_array_3d1); `endif `ifndef NO_INTEGER - `SET_VALUE_0D(integer_array_0d); - `SET_VALUE_1D(integer_array_1d); - `SET_VALUE_2D(integer_array_2d); - `SET_VALUE_3D(integer_array_3d); + `SET_VALUE_0D(integer_array_0d); + `SET_VALUE_1D(integer_array_1d); + `SET_VALUE_2D(integer_array_2d); + `SET_VALUE_3D(integer_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_integer_0d(integer_array_3d[3][2][1]); - `CHECK_0D(integer_array_3d[3][2][1]); - i_integer_1d(integer_array_3d[2][1]); - `CHECK_1D(integer_array_3d[2][1]); - i_integer_2d(integer_array_3d[1]); - `CHECK_2D(integer_array_3d[1]); + i_integer_0d(integer_array_3d[3][2][1]); + `CHECK_0D(integer_array_3d[3][2][1]); + i_integer_1d(integer_array_3d[2][1]); + `CHECK_1D(integer_array_3d[2][1]); + i_integer_2d(integer_array_3d[1]); + `CHECK_2D(integer_array_3d[1]); `endif - i_integer_0d(integer_array_0d); - `CHECK_0D(integer_array_0d); - i_integer_1d(integer_array_1d); - `CHECK_1D(integer_array_1d); - i_integer_2d(integer_array_2d); - `CHECK_2D(integer_array_2d); - i_integer_3d(integer_array_3d); - `CHECK_3D(integer_array_3d); + i_integer_0d(integer_array_0d); + `CHECK_0D(integer_array_0d); + i_integer_1d(integer_array_1d); + `CHECK_1D(integer_array_1d); + i_integer_2d(integer_array_2d); + `CHECK_2D(integer_array_2d); + i_integer_3d(integer_array_3d); + `CHECK_3D(integer_array_3d); - `SET_VALUE_1D1(integer_array_1d1); - `SET_VALUE_2D1(integer_array_2d1); - `SET_VALUE_3D1(integer_array_3d1); - i_integer_1d1(integer_array_1d1); - `CHECK_1D1(integer_array_1d1); - i_integer_2d1(integer_array_2d1); - `CHECK_2D1(integer_array_2d1); - i_integer_3d1(integer_array_3d1); - `CHECK_3D1(integer_array_3d1); + `SET_VALUE_1D1(integer_array_1d1); + `SET_VALUE_2D1(integer_array_2d1); + `SET_VALUE_3D1(integer_array_3d1); + i_integer_1d1(integer_array_1d1); + `CHECK_1D1(integer_array_1d1); + i_integer_2d1(integer_array_2d1); + `CHECK_2D1(integer_array_2d1); + i_integer_3d1(integer_array_3d1); + `CHECK_3D1(integer_array_3d1); `endif - `SET_VALUE_0D(real_array_0d); - `SET_VALUE_1D(real_array_1d); - `SET_VALUE_2D(real_array_2d); - `SET_VALUE_3D(real_array_3d); + `SET_VALUE_0D(real_array_0d); + `SET_VALUE_1D(real_array_1d); + `SET_VALUE_2D(real_array_2d); + `SET_VALUE_3D(real_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_real_0d(real_array_3d[3][2][1]); - `CHECK_DOUBLE_0D(real_array_3d[3][2][1]); - i_real_1d(real_array_3d[2][1]); - `CHECK_DOUBLE_1D(real_array_3d[2][1]); - i_real_2d(real_array_3d[1]); - `CHECK_DOUBLE_2D(real_array_3d[1]); + i_real_0d(real_array_3d[3][2][1]); + `CHECK_DOUBLE_0D(real_array_3d[3][2][1]); + i_real_1d(real_array_3d[2][1]); + `CHECK_DOUBLE_1D(real_array_3d[2][1]); + i_real_2d(real_array_3d[1]); + `CHECK_DOUBLE_2D(real_array_3d[1]); `endif - i_real_0d(real_array_0d); - `CHECK_DOUBLE_0D(real_array_0d); - i_real_1d(real_array_1d); - `CHECK_DOUBLE_1D(real_array_1d); - i_real_2d(real_array_2d); - `CHECK_DOUBLE_2D(real_array_2d); - i_real_3d(real_array_3d); - `CHECK_DOUBLE_3D(real_array_3d); + i_real_0d(real_array_0d); + `CHECK_DOUBLE_0D(real_array_0d); + i_real_1d(real_array_1d); + `CHECK_DOUBLE_1D(real_array_1d); + i_real_2d(real_array_2d); + `CHECK_DOUBLE_2D(real_array_2d); + i_real_3d(real_array_3d); + `CHECK_DOUBLE_3D(real_array_3d); - `SET_VALUE_1D1(real_array_1d1); - `SET_VALUE_2D1(real_array_2d1); - `SET_VALUE_3D1(real_array_3d1); - i_real_1d1(real_array_1d1); - `CHECK_1D1(real_array_1d1); - i_real_2d1(real_array_2d1); - `CHECK_2D1(real_array_2d1); - i_real_3d1(real_array_3d1); - `CHECK_3D1(real_array_3d1); + `SET_VALUE_1D1(real_array_1d1); + `SET_VALUE_2D1(real_array_2d1); + `SET_VALUE_3D1(real_array_3d1); + i_real_1d1(real_array_1d1); + `CHECK_1D1(real_array_1d1); + i_real_2d1(real_array_2d1); + `CHECK_2D1(real_array_2d1); + i_real_3d1(real_array_3d1); + `CHECK_3D1(real_array_3d1); `ifndef NO_SHORTREAL - `SET_VALUE_0D(shortreal_array_0d); - `SET_VALUE_1D(shortreal_array_1d); - `SET_VALUE_2D(shortreal_array_2d); - `SET_VALUE_3D(shortreal_array_3d); + `SET_VALUE_0D(shortreal_array_0d); + `SET_VALUE_1D(shortreal_array_1d); + `SET_VALUE_2D(shortreal_array_2d); + `SET_VALUE_3D(shortreal_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_shortreal_0d(shortreal_array_3d[3][2][1]); - `CHECK_DOUBLE_0D(shortreal_array_3d[3][2][1]); - i_shortreal_1d(shortreal_array_3d[2][1]); - `CHECK_DOUBLE_1D(shortreal_array_3d[2][1]); - i_shortreal_2d(shortreal_array_3d[1]); - `CHECK_DOUBLE_2D(shortreal_array_3d[1]); + i_shortreal_0d(shortreal_array_3d[3][2][1]); + `CHECK_DOUBLE_0D(shortreal_array_3d[3][2][1]); + i_shortreal_1d(shortreal_array_3d[2][1]); + `CHECK_DOUBLE_1D(shortreal_array_3d[2][1]); + i_shortreal_2d(shortreal_array_3d[1]); + `CHECK_DOUBLE_2D(shortreal_array_3d[1]); `endif - i_shortreal_0d(shortreal_array_0d); - `CHECK_DOUBLE_0D(shortreal_array_0d); - i_shortreal_1d(shortreal_array_1d); - `CHECK_DOUBLE_1D(shortreal_array_1d); - i_shortreal_2d(shortreal_array_2d); - `CHECK_DOUBLE_2D(shortreal_array_2d); - i_shortreal_3d(shortreal_array_3d); - `CHECK_DOUBLE_3D(shortreal_array_3d); + i_shortreal_0d(shortreal_array_0d); + `CHECK_DOUBLE_0D(shortreal_array_0d); + i_shortreal_1d(shortreal_array_1d); + `CHECK_DOUBLE_1D(shortreal_array_1d); + i_shortreal_2d(shortreal_array_2d); + `CHECK_DOUBLE_2D(shortreal_array_2d); + i_shortreal_3d(shortreal_array_3d); + `CHECK_DOUBLE_3D(shortreal_array_3d); - `SET_VALUE_1D1(shortreal_array_1d1); - `SET_VALUE_2D1(shortreal_array_2d1); - `SET_VALUE_3D1(shortreal_array_3d1); - i_shortreal_1d1(shortreal_array_1d1); - `CHECK_1D1(shortreal_array_1d1); - i_shortreal_2d1(shortreal_array_2d1); - `CHECK_2D1(shortreal_array_2d1); - i_shortreal_3d1(shortreal_array_3d1); - `CHECK_3D1(shortreal_array_3d1); + `SET_VALUE_1D1(shortreal_array_1d1); + `SET_VALUE_2D1(shortreal_array_2d1); + `SET_VALUE_3D1(shortreal_array_3d1); + i_shortreal_1d1(shortreal_array_1d1); + `CHECK_1D1(shortreal_array_1d1); + i_shortreal_2d1(shortreal_array_2d1); + `CHECK_2D1(shortreal_array_2d1); + i_shortreal_3d1(shortreal_array_3d1); + `CHECK_3D1(shortreal_array_3d1); `endif - for (int i = 0; i < 4; ++i) - for (int j = 0; j < 3; ++j) - for (int k = 0; k < 2; ++k) - chandle_array_3d[i][j][k] = null; + for (int i = 0; i < 4; ++i) + for (int j = 0; j < 3; ++j) + for (int k = 0; k < 2; ++k) + chandle_array_3d[i][j][k] = null; `ifndef NO_INOUT_COMPLEX_TYPE - i_chandle_0d(chandle_array_3d[3][2][1]); - `CHECK_CHANDLE_VAL(chandle_array_3d[3][2][1], get_non_null()); - i_chandle_1d(chandle_array_3d[2][1]); - `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][1], get_non_null()); - i_chandle_2d(chandle_array_3d[1]); - `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[1][1][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[1][2][1], get_non_null()); + i_chandle_0d(chandle_array_3d[3][2][1]); + `CHECK_CHANDLE_VAL(chandle_array_3d[3][2][1], get_non_null()); + i_chandle_1d(chandle_array_3d[2][1]); + `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][1], get_non_null()); + i_chandle_2d(chandle_array_3d[1]); + `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[1][1][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[1][2][1], get_non_null()); `endif - chandle_array_0d = null; - i_chandle_0d(chandle_array_0d); - `CHECK_CHANDLE_VAL(chandle_array_0d, get_non_null()); - chandle_array_1d[0] = null; - chandle_array_1d[1] = null; - i_chandle_1d(chandle_array_1d); - `CHECK_CHANDLE_VAL(chandle_array_1d[0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_1d[1], get_non_null()); - chandle_array_2d[0][1] = null; - chandle_array_2d[1][1] = null; - chandle_array_2d[2][1] = null; - i_chandle_2d(chandle_array_2d); - `CHECK_CHANDLE_VAL(chandle_array_2d[0][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_2d[1][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_2d[2][1], get_non_null()); - i_chandle_3d(chandle_array_3d); - `CHECK_CHANDLE_VAL(chandle_array_3d[0][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[2][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array_3d[3][0][0], get_non_null()); + chandle_array_0d = null; + i_chandle_0d(chandle_array_0d); + `CHECK_CHANDLE_VAL(chandle_array_0d, get_non_null()); + chandle_array_1d[0] = null; + chandle_array_1d[1] = null; + i_chandle_1d(chandle_array_1d); + `CHECK_CHANDLE_VAL(chandle_array_1d[0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_1d[1], get_non_null()); + chandle_array_2d[0][1] = null; + chandle_array_2d[1][1] = null; + chandle_array_2d[2][1] = null; + i_chandle_2d(chandle_array_2d); + `CHECK_CHANDLE_VAL(chandle_array_2d[0][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_2d[1][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_2d[2][1], get_non_null()); + i_chandle_3d(chandle_array_3d); + `CHECK_CHANDLE_VAL(chandle_array_3d[0][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[2][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array_3d[3][0][0], get_non_null()); - chandle_array_1d1[0] = null; - i_chandle_1d1(chandle_array_1d1); - `CHECK_CHANDLE_VAL(chandle_array_1d1[0], get_non_null()); - chandle_array_2d1[0][0] = null; - i_chandle_2d1(chandle_array_2d1); - `CHECK_CHANDLE_VAL(chandle_array_2d1[0][0], get_non_null()); - chandle_array_3d1[0][0][0] = null; - i_chandle_3d1(chandle_array_3d1); - `CHECK_CHANDLE_VAL(chandle_array_3d1[0][0][0], get_non_null()); + chandle_array_1d1[0] = null; + i_chandle_1d1(chandle_array_1d1); + `CHECK_CHANDLE_VAL(chandle_array_1d1[0], get_non_null()); + chandle_array_2d1[0][0] = null; + i_chandle_2d1(chandle_array_2d1); + `CHECK_CHANDLE_VAL(chandle_array_2d1[0][0], get_non_null()); + chandle_array_3d1[0][0][0] = null; + i_chandle_3d1(chandle_array_3d1); + `CHECK_CHANDLE_VAL(chandle_array_3d1[0][0][0], get_non_null()); `ifndef NO_INOUT_COMPLEX_TYPE - string_array_3d[3][2][1] = "42"; - i_string_0d(string_array_3d[3][2][1]); - `CHECK_STRING_VAL(string_array_3d[3][2][1], "43"); + string_array_3d[3][2][1] = "42"; + i_string_0d(string_array_3d[3][2][1]); + `CHECK_STRING_VAL(string_array_3d[3][2][1], "43"); - string_array_3d[2][1][0] = "43"; - string_array_3d[2][1][1] = "44"; - i_string_1d(string_array_3d[2][1]); - `CHECK_STRING_VAL(string_array_3d[2][1][0], "44"); - `CHECK_STRING_VAL(string_array_3d[2][1][1], "45"); + string_array_3d[2][1][0] = "43"; + string_array_3d[2][1][1] = "44"; + i_string_1d(string_array_3d[2][1]); + `CHECK_STRING_VAL(string_array_3d[2][1][0], "44"); + `CHECK_STRING_VAL(string_array_3d[2][1][1], "45"); - string_array_3d[1][0][1] = "45"; - string_array_3d[1][1][1] = "46"; - string_array_3d[1][2][1] = "47"; - i_string_2d(string_array_3d[1]); - `CHECK_STRING_VAL(string_array_3d[1][0][1], "46"); - `CHECK_STRING_VAL(string_array_3d[1][1][1], "47"); - `CHECK_STRING_VAL(string_array_3d[1][2][1], "48"); + string_array_3d[1][0][1] = "45"; + string_array_3d[1][1][1] = "46"; + string_array_3d[1][2][1] = "47"; + i_string_2d(string_array_3d[1]); + `CHECK_STRING_VAL(string_array_3d[1][0][1], "46"); + `CHECK_STRING_VAL(string_array_3d[1][1][1], "47"); + `CHECK_STRING_VAL(string_array_3d[1][2][1], "48"); `endif - string_array_0d = "42"; - i_string_0d(string_array_0d); - `CHECK_STRING_VAL(string_array_0d, "43"); - string_array_1d[0] = "43"; - string_array_1d[1] = "44"; - i_string_1d(string_array_1d); - `CHECK_STRING_VAL(string_array_1d[0], "44"); - `CHECK_STRING_VAL(string_array_1d[1], "45"); + string_array_0d = "42"; + i_string_0d(string_array_0d); + `CHECK_STRING_VAL(string_array_0d, "43"); + string_array_1d[0] = "43"; + string_array_1d[1] = "44"; + i_string_1d(string_array_1d); + `CHECK_STRING_VAL(string_array_1d[0], "44"); + `CHECK_STRING_VAL(string_array_1d[1], "45"); - string_array_2d[0][1] = "45"; - string_array_2d[1][1] = "46"; - string_array_2d[2][1] = "47"; - i_string_2d(string_array_2d); - `CHECK_STRING_VAL(string_array_2d[0][1], "46"); - `CHECK_STRING_VAL(string_array_2d[1][1], "47"); - `CHECK_STRING_VAL(string_array_2d[2][1], "48"); + string_array_2d[0][1] = "45"; + string_array_2d[1][1] = "46"; + string_array_2d[2][1] = "47"; + i_string_2d(string_array_2d); + `CHECK_STRING_VAL(string_array_2d[0][1], "46"); + `CHECK_STRING_VAL(string_array_2d[1][1], "47"); + `CHECK_STRING_VAL(string_array_2d[2][1], "48"); - string_array_3d[0][0][0] = "48"; - string_array_3d[1][0][0] = "49"; - string_array_3d[2][0][0] = "50"; - string_array_3d[3][0][0] = "51"; - i_string_3d(string_array_3d); - `CHECK_STRING_VAL(string_array_3d[0][0][0], "49"); - `CHECK_STRING_VAL(string_array_3d[1][0][0], "50"); - `CHECK_STRING_VAL(string_array_3d[2][0][0], "51"); - `CHECK_STRING_VAL(string_array_3d[3][0][0], "52"); + string_array_3d[0][0][0] = "48"; + string_array_3d[1][0][0] = "49"; + string_array_3d[2][0][0] = "50"; + string_array_3d[3][0][0] = "51"; + i_string_3d(string_array_3d); + `CHECK_STRING_VAL(string_array_3d[0][0][0], "49"); + `CHECK_STRING_VAL(string_array_3d[1][0][0], "50"); + `CHECK_STRING_VAL(string_array_3d[2][0][0], "51"); + `CHECK_STRING_VAL(string_array_3d[3][0][0], "52"); - string_array_1d1[0] = "52"; - i_string_1d1(string_array_1d1); - `CHECK_STRING_VAL(string_array_1d1[0], "53"); - string_array_2d1[0][0] = "53"; - i_string_2d1(string_array_2d1); - `CHECK_STRING_VAL(string_array_2d1[0][0], "54"); - string_array_3d1[0][0][0] = "54"; - i_string_3d1(string_array_3d1); - `CHECK_STRING_VAL(string_array_3d1[0][0][0], "55"); + string_array_1d1[0] = "52"; + i_string_1d1(string_array_1d1); + `CHECK_STRING_VAL(string_array_1d1[0], "53"); + string_array_2d1[0][0] = "53"; + i_string_2d1(string_array_2d1); + `CHECK_STRING_VAL(string_array_2d1[0][0], "54"); + string_array_3d1[0][0][0] = "54"; + i_string_3d1(string_array_3d1); + `CHECK_STRING_VAL(string_array_3d1[0][0][0], "55"); - `SET_VALUE_0D(bit1_array_0d); - `SET_VALUE_1D(bit1_array_1d); - `SET_VALUE_2D(bit1_array_2d); - `SET_VALUE_3D(bit1_array_3d); + `SET_VALUE_0D(bit1_array_0d); + `SET_VALUE_1D(bit1_array_1d); + `SET_VALUE_2D(bit1_array_2d); + `SET_VALUE_3D(bit1_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_bit1_0d(bit1_array_3d[3][2][1]); - `CHECK_0D(bit1_array_3d[3][2][1]); - i_bit1_1d(bit1_array_3d[2][1]); - `CHECK_1D(bit1_array_3d[2][1]); - i_bit1_2d(bit1_array_3d[1]); - `CHECK_2D(bit1_array_3d[1]); + i_bit1_0d(bit1_array_3d[3][2][1]); + `CHECK_0D(bit1_array_3d[3][2][1]); + i_bit1_1d(bit1_array_3d[2][1]); + `CHECK_1D(bit1_array_3d[2][1]); + i_bit1_2d(bit1_array_3d[1]); + `CHECK_2D(bit1_array_3d[1]); `endif - i_bit1_0d(bit1_array_0d); - `CHECK_0D(bit1_array_0d); - i_bit1_1d(bit1_array_1d); - `CHECK_1D(bit1_array_1d); - i_bit1_2d(bit1_array_2d); - `CHECK_2D(bit1_array_2d); - i_bit1_3d(bit1_array_3d); - `CHECK_3D(bit1_array_3d); + i_bit1_0d(bit1_array_0d); + `CHECK_0D(bit1_array_0d); + i_bit1_1d(bit1_array_1d); + `CHECK_1D(bit1_array_1d); + i_bit1_2d(bit1_array_2d); + `CHECK_2D(bit1_array_2d); + i_bit1_3d(bit1_array_3d); + `CHECK_3D(bit1_array_3d); - `SET_VALUE_1D1(bit1_array_1d1); - `SET_VALUE_2D1(bit1_array_2d1); - `SET_VALUE_3D1(bit1_array_3d1); - i_bit1_1d1(bit1_array_1d1); - `CHECK_1D1(bit1_array_1d1); - i_bit1_2d1(bit1_array_2d1); - `CHECK_2D1(bit1_array_2d1); - i_bit1_3d1(bit1_array_3d1); - `CHECK_3D1(bit1_array_3d1); + `SET_VALUE_1D1(bit1_array_1d1); + `SET_VALUE_2D1(bit1_array_2d1); + `SET_VALUE_3D1(bit1_array_3d1); + i_bit1_1d1(bit1_array_1d1); + `CHECK_1D1(bit1_array_1d1); + i_bit1_2d1(bit1_array_2d1); + `CHECK_2D1(bit1_array_2d1); + i_bit1_3d1(bit1_array_3d1); + `CHECK_3D1(bit1_array_3d1); - `SET_VALUE_0D(bit7_array_0d); - `SET_VALUE_1D(bit7_array_1d); - `SET_VALUE_2D(bit7_array_2d); - `SET_VALUE_3D(bit7_array_3d); + `SET_VALUE_0D(bit7_array_0d); + `SET_VALUE_1D(bit7_array_1d); + `SET_VALUE_2D(bit7_array_2d); + `SET_VALUE_3D(bit7_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_bit7_0d(bit7_array_3d[3][2][1]); - `CHECK_0D(bit7_array_3d[3][2][1]); - i_bit7_1d(bit7_array_3d[2][1]); - `CHECK_1D(bit7_array_3d[2][1]); - i_bit7_2d(bit7_array_3d[1]); - `CHECK_2D(bit7_array_3d[1]); + i_bit7_0d(bit7_array_3d[3][2][1]); + `CHECK_0D(bit7_array_3d[3][2][1]); + i_bit7_1d(bit7_array_3d[2][1]); + `CHECK_1D(bit7_array_3d[2][1]); + i_bit7_2d(bit7_array_3d[1]); + `CHECK_2D(bit7_array_3d[1]); `endif - i_bit7_0d(bit7_array_0d); - `CHECK_0D(bit7_array_0d); - i_bit7_1d(bit7_array_1d); - `CHECK_1D(bit7_array_1d); - i_bit7_2d(bit7_array_2d); - `CHECK_2D(bit7_array_2d); - i_bit7_3d(bit7_array_3d); - `CHECK_3D(bit7_array_3d); + i_bit7_0d(bit7_array_0d); + `CHECK_0D(bit7_array_0d); + i_bit7_1d(bit7_array_1d); + `CHECK_1D(bit7_array_1d); + i_bit7_2d(bit7_array_2d); + `CHECK_2D(bit7_array_2d); + i_bit7_3d(bit7_array_3d); + `CHECK_3D(bit7_array_3d); - `SET_VALUE_1D1(bit7_array_1d1); - `SET_VALUE_2D1(bit7_array_2d1); - `SET_VALUE_3D1(bit7_array_3d1); - i_bit7_1d1(bit7_array_1d1); - `CHECK_1D1(bit7_array_1d1); - i_bit7_2d1(bit7_array_2d1); - `CHECK_2D1(bit7_array_2d1); - i_bit7_3d1(bit7_array_3d1); - `CHECK_3D1(bit7_array_3d1); + `SET_VALUE_1D1(bit7_array_1d1); + `SET_VALUE_2D1(bit7_array_2d1); + `SET_VALUE_3D1(bit7_array_3d1); + i_bit7_1d1(bit7_array_1d1); + `CHECK_1D1(bit7_array_1d1); + i_bit7_2d1(bit7_array_2d1); + `CHECK_2D1(bit7_array_2d1); + i_bit7_3d1(bit7_array_3d1); + `CHECK_3D1(bit7_array_3d1); - `SET_VALUE_0D(bit121_array_0d); - `SET_VALUE_1D(bit121_array_1d); - `SET_VALUE_2D(bit121_array_2d); - `SET_VALUE_3D(bit121_array_3d); + `SET_VALUE_0D(bit121_array_0d); + `SET_VALUE_1D(bit121_array_1d); + `SET_VALUE_2D(bit121_array_2d); + `SET_VALUE_3D(bit121_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_bit121_0d(bit121_array_3d[3][2][1]); - `CHECK_0D(bit121_array_3d[3][2][1]); - i_bit121_1d(bit121_array_3d[2][1]); - `CHECK_1D(bit121_array_3d[2][1]); - i_bit121_2d(bit121_array_3d[1]); - `CHECK_2D(bit121_array_3d[1]); + i_bit121_0d(bit121_array_3d[3][2][1]); + `CHECK_0D(bit121_array_3d[3][2][1]); + i_bit121_1d(bit121_array_3d[2][1]); + `CHECK_1D(bit121_array_3d[2][1]); + i_bit121_2d(bit121_array_3d[1]); + `CHECK_2D(bit121_array_3d[1]); `endif - i_bit121_0d(bit121_array_0d); - `CHECK_0D(bit121_array_0d); - i_bit121_1d(bit121_array_1d); - `CHECK_1D(bit121_array_1d); - i_bit121_2d(bit121_array_2d); - `CHECK_2D(bit121_array_2d); - i_bit121_3d(bit121_array_3d); - `CHECK_3D(bit121_array_3d); + i_bit121_0d(bit121_array_0d); + `CHECK_0D(bit121_array_0d); + i_bit121_1d(bit121_array_1d); + `CHECK_1D(bit121_array_1d); + i_bit121_2d(bit121_array_2d); + `CHECK_2D(bit121_array_2d); + i_bit121_3d(bit121_array_3d); + `CHECK_3D(bit121_array_3d); - `SET_VALUE_1D1(bit121_array_1d1); - `SET_VALUE_2D1(bit121_array_2d1); - `SET_VALUE_3D1(bit121_array_3d1); - i_bit121_1d1(bit121_array_1d1); - `CHECK_1D1(bit121_array_1d1); - i_bit121_2d1(bit121_array_2d1); - `CHECK_2D1(bit121_array_2d1); - i_bit121_3d1(bit121_array_3d1); - `CHECK_3D1(bit121_array_3d1); + `SET_VALUE_1D1(bit121_array_1d1); + `SET_VALUE_2D1(bit121_array_2d1); + `SET_VALUE_3D1(bit121_array_3d1); + i_bit121_1d1(bit121_array_1d1); + `CHECK_1D1(bit121_array_1d1); + i_bit121_2d1(bit121_array_2d1); + `CHECK_2D1(bit121_array_2d1); + i_bit121_3d1(bit121_array_3d1); + `CHECK_3D1(bit121_array_3d1); - `SET_VALUE_0D(logic1_array_0d); - `SET_VALUE_1D(logic1_array_1d); - `SET_VALUE_2D(logic1_array_2d); - `SET_VALUE_3D(logic1_array_3d); + `SET_VALUE_0D(logic1_array_0d); + `SET_VALUE_1D(logic1_array_1d); + `SET_VALUE_2D(logic1_array_2d); + `SET_VALUE_3D(logic1_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_logic1_0d(logic1_array_3d[3][2][1]); - `CHECK_0D(logic1_array_3d[3][2][1]); - i_logic1_1d(logic1_array_3d[2][1]); - `CHECK_1D(logic1_array_3d[2][1]); - i_logic1_2d(logic1_array_3d[1]); - `CHECK_2D(logic1_array_3d[1]); + i_logic1_0d(logic1_array_3d[3][2][1]); + `CHECK_0D(logic1_array_3d[3][2][1]); + i_logic1_1d(logic1_array_3d[2][1]); + `CHECK_1D(logic1_array_3d[2][1]); + i_logic1_2d(logic1_array_3d[1]); + `CHECK_2D(logic1_array_3d[1]); `endif - i_logic1_0d(logic1_array_0d); - `CHECK_0D(logic1_array_0d); - i_logic1_1d(logic1_array_1d); - `CHECK_1D(logic1_array_1d); - i_logic1_2d(logic1_array_2d); - `CHECK_2D(logic1_array_2d); - i_logic1_3d(logic1_array_3d); - `CHECK_3D(logic1_array_3d); + i_logic1_0d(logic1_array_0d); + `CHECK_0D(logic1_array_0d); + i_logic1_1d(logic1_array_1d); + `CHECK_1D(logic1_array_1d); + i_logic1_2d(logic1_array_2d); + `CHECK_2D(logic1_array_2d); + i_logic1_3d(logic1_array_3d); + `CHECK_3D(logic1_array_3d); - `SET_VALUE_1D1(logic1_array_1d1); - `SET_VALUE_2D1(logic1_array_2d1); - `SET_VALUE_3D1(logic1_array_3d1); - i_logic1_1d1(logic1_array_1d1); - `CHECK_1D1(logic1_array_1d1); - i_logic1_2d1(logic1_array_2d1); - `CHECK_2D1(logic1_array_2d1); - i_logic1_3d1(logic1_array_3d1); - `CHECK_3D1(logic1_array_3d1); + `SET_VALUE_1D1(logic1_array_1d1); + `SET_VALUE_2D1(logic1_array_2d1); + `SET_VALUE_3D1(logic1_array_3d1); + i_logic1_1d1(logic1_array_1d1); + `CHECK_1D1(logic1_array_1d1); + i_logic1_2d1(logic1_array_2d1); + `CHECK_2D1(logic1_array_2d1); + i_logic1_3d1(logic1_array_3d1); + `CHECK_3D1(logic1_array_3d1); - `SET_VALUE_0D(logic7_array_0d); - `SET_VALUE_1D(logic7_array_1d); - `SET_VALUE_2D(logic7_array_2d); - `SET_VALUE_3D(logic7_array_3d); + `SET_VALUE_0D(logic7_array_0d); + `SET_VALUE_1D(logic7_array_1d); + `SET_VALUE_2D(logic7_array_2d); + `SET_VALUE_3D(logic7_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_logic7_0d(logic7_array_3d[3][2][1]); - `CHECK_0D(logic7_array_3d[3][2][1]); - i_logic7_1d(logic7_array_3d[2][1]); - `CHECK_1D(logic7_array_3d[2][1]); - i_logic7_2d(logic7_array_3d[1]); - `CHECK_2D(logic7_array_3d[1]); + i_logic7_0d(logic7_array_3d[3][2][1]); + `CHECK_0D(logic7_array_3d[3][2][1]); + i_logic7_1d(logic7_array_3d[2][1]); + `CHECK_1D(logic7_array_3d[2][1]); + i_logic7_2d(logic7_array_3d[1]); + `CHECK_2D(logic7_array_3d[1]); `endif - i_logic7_0d(logic7_array_0d); - `CHECK_0D(logic7_array_0d); - i_logic7_1d(logic7_array_1d); - `CHECK_1D(logic7_array_1d); - i_logic7_2d(logic7_array_2d); - `CHECK_2D(logic7_array_2d); - i_logic7_3d(logic7_array_3d); - `CHECK_3D(logic7_array_3d); + i_logic7_0d(logic7_array_0d); + `CHECK_0D(logic7_array_0d); + i_logic7_1d(logic7_array_1d); + `CHECK_1D(logic7_array_1d); + i_logic7_2d(logic7_array_2d); + `CHECK_2D(logic7_array_2d); + i_logic7_3d(logic7_array_3d); + `CHECK_3D(logic7_array_3d); - `SET_VALUE_1D1(logic7_array_1d1); - `SET_VALUE_2D1(logic7_array_2d1); - `SET_VALUE_3D1(logic7_array_3d1); - i_logic7_1d1(logic7_array_1d1); - `CHECK_1D1(logic7_array_1d1); - i_logic7_2d1(logic7_array_2d1); - `CHECK_2D1(logic7_array_2d1); - i_logic7_3d1(logic7_array_3d1); - `CHECK_3D1(logic7_array_3d1); + `SET_VALUE_1D1(logic7_array_1d1); + `SET_VALUE_2D1(logic7_array_2d1); + `SET_VALUE_3D1(logic7_array_3d1); + i_logic7_1d1(logic7_array_1d1); + `CHECK_1D1(logic7_array_1d1); + i_logic7_2d1(logic7_array_2d1); + `CHECK_2D1(logic7_array_2d1); + i_logic7_3d1(logic7_array_3d1); + `CHECK_3D1(logic7_array_3d1); - `SET_VALUE_0D(logic121_array_0d); - `SET_VALUE_1D(logic121_array_1d); - `SET_VALUE_2D(logic121_array_2d); - `SET_VALUE_3D(logic121_array_3d); + `SET_VALUE_0D(logic121_array_0d); + `SET_VALUE_1D(logic121_array_1d); + `SET_VALUE_2D(logic121_array_2d); + `SET_VALUE_3D(logic121_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_logic121_0d(logic121_array_3d[3][2][1]); - `CHECK_0D(logic121_array_3d[3][2][1]); - i_logic121_1d(logic121_array_3d[2][1]); - `CHECK_1D(logic121_array_3d[2][1]); - i_logic121_2d(logic121_array_3d[1]); - `CHECK_2D(logic121_array_3d[1]); + i_logic121_0d(logic121_array_3d[3][2][1]); + `CHECK_0D(logic121_array_3d[3][2][1]); + i_logic121_1d(logic121_array_3d[2][1]); + `CHECK_1D(logic121_array_3d[2][1]); + i_logic121_2d(logic121_array_3d[1]); + `CHECK_2D(logic121_array_3d[1]); `endif - i_logic121_0d(logic121_array_0d); - `CHECK_0D(logic121_array_0d); - i_logic121_1d(logic121_array_1d); - `CHECK_1D(logic121_array_1d); - i_logic121_2d(logic121_array_2d); - `CHECK_2D(logic121_array_2d); - i_logic121_3d(logic121_array_3d); - `CHECK_3D(logic121_array_3d); + i_logic121_0d(logic121_array_0d); + `CHECK_0D(logic121_array_0d); + i_logic121_1d(logic121_array_1d); + `CHECK_1D(logic121_array_1d); + i_logic121_2d(logic121_array_2d); + `CHECK_2D(logic121_array_2d); + i_logic121_3d(logic121_array_3d); + `CHECK_3D(logic121_array_3d); - `SET_VALUE_1D1(logic121_array_1d1); - `SET_VALUE_2D1(logic121_array_2d1); - `SET_VALUE_3D1(logic121_array_3d1); - i_logic121_1d1(logic121_array_1d1); - `CHECK_1D1(logic121_array_1d1); - i_logic121_2d1(logic121_array_2d1); - `CHECK_2D1(logic121_array_2d1); - i_logic121_3d1(logic121_array_3d1); - `CHECK_3D1(logic121_array_3d1); + `SET_VALUE_1D1(logic121_array_1d1); + `SET_VALUE_2D1(logic121_array_2d1); + `SET_VALUE_3D1(logic121_array_3d1); + i_logic121_1d1(logic121_array_1d1); + `CHECK_1D1(logic121_array_1d1); + i_logic121_2d1(logic121_array_2d1); + `CHECK_2D1(logic121_array_2d1); + i_logic121_3d1(logic121_array_3d1); + `CHECK_3D1(logic121_array_3d1); - `SET_VALUE_0D(pack_struct_array_0d); - `SET_VALUE_1D(pack_struct_array_1d); - `SET_VALUE_2D(pack_struct_array_2d); - `SET_VALUE_3D(pack_struct_array_3d); + `SET_VALUE_0D(pack_struct_array_0d); + `SET_VALUE_1D(pack_struct_array_1d); + `SET_VALUE_2D(pack_struct_array_2d); + `SET_VALUE_3D(pack_struct_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE - i_pack_struct_0d(pack_struct_array_3d[3][2][1]); - `CHECK_0D(pack_struct_array_3d[3][2][1]); - i_pack_struct_1d(pack_struct_array_3d[2][1]); - `CHECK_1D(pack_struct_array_3d[2][1]); - i_pack_struct_2d(pack_struct_array_3d[1]); - `CHECK_2D(pack_struct_array_3d[1]); + i_pack_struct_0d(pack_struct_array_3d[3][2][1]); + `CHECK_0D(pack_struct_array_3d[3][2][1]); + i_pack_struct_1d(pack_struct_array_3d[2][1]); + `CHECK_1D(pack_struct_array_3d[2][1]); + i_pack_struct_2d(pack_struct_array_3d[1]); + `CHECK_2D(pack_struct_array_3d[1]); `endif - i_pack_struct_0d(pack_struct_array_0d); - `CHECK_0D(pack_struct_array_0d); - i_pack_struct_1d(pack_struct_array_1d); - `CHECK_1D(pack_struct_array_1d); - i_pack_struct_2d(pack_struct_array_2d); - `CHECK_2D(pack_struct_array_2d); - i_pack_struct_3d(pack_struct_array_3d); - `CHECK_3D(pack_struct_array_3d); + i_pack_struct_0d(pack_struct_array_0d); + `CHECK_0D(pack_struct_array_0d); + i_pack_struct_1d(pack_struct_array_1d); + `CHECK_1D(pack_struct_array_1d); + i_pack_struct_2d(pack_struct_array_2d); + `CHECK_2D(pack_struct_array_2d); + i_pack_struct_3d(pack_struct_array_3d); + `CHECK_3D(pack_struct_array_3d); - `SET_VALUE_1D1(pack_struct_array_1d1); - `SET_VALUE_2D1(pack_struct_array_2d1); - `SET_VALUE_3D1(pack_struct_array_3d1); - i_pack_struct_1d1(pack_struct_array_1d1); - `CHECK_1D1(pack_struct_array_1d1); - i_pack_struct_2d1(pack_struct_array_2d1); - `CHECK_2D1(pack_struct_array_2d1); - i_pack_struct_3d1(pack_struct_array_3d1); - `CHECK_3D1(pack_struct_array_3d1); + `SET_VALUE_1D1(pack_struct_array_1d1); + `SET_VALUE_2D1(pack_struct_array_2d1); + `SET_VALUE_3D1(pack_struct_array_3d1); + i_pack_struct_1d1(pack_struct_array_1d1); + `CHECK_1D1(pack_struct_array_1d1); + i_pack_struct_2d1(pack_struct_array_2d1); + `CHECK_2D1(pack_struct_array_2d1); + i_pack_struct_3d1(pack_struct_array_3d1); + `CHECK_3D1(pack_struct_array_3d1); `ifndef NO_UNPACK_STRUCT - unpack_struct_array_3d[3][2][1].val = 42; - i_unpack_struct_0d(unpack_struct_array_3d[3][2][1]); - `CHECK_VAL(unpack_struct_array_3d[3][2][1].val, 43); + unpack_struct_array_3d[3][2][1].val = 42; + i_unpack_struct_0d(unpack_struct_array_3d[3][2][1]); + `CHECK_VAL(unpack_struct_array_3d[3][2][1].val, 43); - unpack_struct_array_3d[2][1][0].val = 43; - unpack_struct_array_3d[2][1][1].val = 44; - i_unpack_struct_1d(unpack_struct_array_3d[2][1]); - `CHECK_VAL(unpack_struct_array_3d[2][1][0].val, 44); - `CHECK_VAL(unpack_struct_array_3d[2][1][1].val, 45); + unpack_struct_array_3d[2][1][0].val = 43; + unpack_struct_array_3d[2][1][1].val = 44; + i_unpack_struct_1d(unpack_struct_array_3d[2][1]); + `CHECK_VAL(unpack_struct_array_3d[2][1][0].val, 44); + `CHECK_VAL(unpack_struct_array_3d[2][1][1].val, 45); - unpack_struct_array_3d[1][0][1].val = 45; - unpack_struct_array_3d[1][1][1].val = 46; - unpack_struct_array_3d[1][2][1].val = 47; - i_unpack_struct_2d(unpack_struct_array_3d[1]); - `CHECK_VAL(unpack_struct_array_3d[1][0][1].val, 46); - `CHECK_VAL(unpack_struct_array_3d[1][1][1].val, 47); - `CHECK_VAL(unpack_struct_array_3d[1][2][1].val, 48); + unpack_struct_array_3d[1][0][1].val = 45; + unpack_struct_array_3d[1][1][1].val = 46; + unpack_struct_array_3d[1][2][1].val = 47; + i_unpack_struct_2d(unpack_struct_array_3d[1]); + `CHECK_VAL(unpack_struct_array_3d[1][0][1].val, 46); + `CHECK_VAL(unpack_struct_array_3d[1][1][1].val, 47); + `CHECK_VAL(unpack_struct_array_3d[1][2][1].val, 48); - unpack_struct_array_3d[0][0][0].val = 48; - unpack_struct_array_3d[1][0][0].val = 49; - unpack_struct_array_3d[2][0][0].val = 50; - unpack_struct_array_3d[3][0][0].val = 51; - i_unpack_struct_3d(unpack_struct_array_3d); - `CHECK_VAL(unpack_struct_array_3d[0][0][0].val, 49); - `CHECK_VAL(unpack_struct_array_3d[1][0][0].val, 50); - `CHECK_VAL(unpack_struct_array_3d[2][0][0].val, 51); - `CHECK_VAL(unpack_struct_array_3d[3][0][0].val, 52); + unpack_struct_array_3d[0][0][0].val = 48; + unpack_struct_array_3d[1][0][0].val = 49; + unpack_struct_array_3d[2][0][0].val = 50; + unpack_struct_array_3d[3][0][0].val = 51; + i_unpack_struct_3d(unpack_struct_array_3d); + `CHECK_VAL(unpack_struct_array_3d[0][0][0].val, 49); + `CHECK_VAL(unpack_struct_array_3d[1][0][0].val, 50); + `CHECK_VAL(unpack_struct_array_3d[2][0][0].val, 51); + `CHECK_VAL(unpack_struct_array_3d[3][0][0].val, 52); - unpack_struct_array_3d1[0][0][0].val = 52; - i_unpack_struct_1d1(unpack_struct_array_3d1[0][0]); - `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 53); - unpack_struct_array_3d1[0][0][0].val = 53; - i_unpack_struct_2d1(unpack_struct_array_3d1[0]); - `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 54); - unpack_struct_array_3d1[0][0][0].val = 54; - i_unpack_struct_3d1(unpack_struct_array_3d1); - `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 55); + unpack_struct_array_3d1[0][0][0].val = 52; + i_unpack_struct_1d1(unpack_struct_array_3d1[0][0]); + `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 53); + unpack_struct_array_3d1[0][0][0].val = 53; + i_unpack_struct_2d1(unpack_struct_array_3d1[0]); + `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 54); + unpack_struct_array_3d1[0][0][0].val = 54; + i_unpack_struct_3d1(unpack_struct_array_3d1); + `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 55); `endif - check_exports(); - $write("*-* All Finished *-*\n"); - $finish; - end + check_exports(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_arg_input_type.v b/test_regress/t/t_dpi_arg_input_type.v index 116149725..723061d03 100644 --- a/test_regress/t/t_dpi_arg_input_type.v +++ b/test_regress/t/t_dpi_arg_input_type.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -27,891 +28,891 @@ `endif module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; `ifdef VERILATOR - wire _unused = &{1'b0, clk}; + wire _unused = &{1'b0, clk}; `endif - // Legal input argument types for DPI functions + // Legal input argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - typedef byte byte_t; - typedef byte unsigned byte_unsigned_t; - typedef shortint shortint_t; - typedef shortint unsigned shortint_unsigned_t; - typedef int int_t; - typedef int unsigned int_unsigned_t; - typedef longint longint_t; - typedef longint unsigned longint_unsigned_t; + // Basic types as per IEEE 1800-2023 35.5.6 + typedef byte byte_t; + typedef byte unsigned byte_unsigned_t; + typedef shortint shortint_t; + typedef shortint unsigned shortint_unsigned_t; + typedef int int_t; + typedef int unsigned int_unsigned_t; + typedef longint longint_t; + typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME - typedef time time_t; + typedef time time_t; `endif `ifndef NO_INTEGER - typedef integer integer_t; + typedef integer integer_t; `endif - typedef real real_t; + typedef real real_t; `ifndef NO_SHORTREAL - typedef shortreal shortreal_t; + typedef shortreal shortreal_t; `endif - typedef chandle chandle_t; - typedef string string_t; - typedef bit bit_t; - typedef logic logic_t; + typedef chandle chandle_t; + typedef string string_t; + typedef bit bit_t; + typedef logic logic_t; - // 2-state packed structures - typedef struct packed { bit x; } struct_2_state_1; - typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; - typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; - typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; - typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; - typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; + // 2-state packed structures + typedef struct packed { bit x; } struct_2_state_1; + typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; + typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; + typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; + typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; + typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; - // 2-state packed unions - typedef union packed { bit x; bit y; } union_2_state_1; - typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; - typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; - typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; - typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; - typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; + // 2-state packed unions + typedef union packed { bit x; bit y; } union_2_state_1; + typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; + typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; + typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; + typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; + typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; - // 4-state packed structures - typedef struct packed { logic x; } struct_4_state_1; - typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; - typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; - typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; - typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; - typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; + // 4-state packed structures + typedef struct packed { logic x; } struct_4_state_1; + typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; + typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; + typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; + typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; + typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; - // 4-state packed unions - typedef union packed { logic x; bit y; } union_4_state_1; - typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; - typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; - typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; - typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; - typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; + // 4-state packed unions + typedef union packed { logic x; bit y; } union_4_state_1; + typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; + typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; + typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; + typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; + typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - import "DPI-C" function void i_byte (input byte i); - import "DPI-C" function void i_byte_unsigned (input byte unsigned i); - import "DPI-C" function void i_shortint (input shortint i); - import "DPI-C" function void i_shortint_unsigned (input shortint unsigned i); - import "DPI-C" function void i_int (input int i); - import "DPI-C" function void i_int_unsigned (input int unsigned i); - import "DPI-C" function void i_longint (input longint i); - import "DPI-C" function void i_longint_unsigned (input longint unsigned i); + // Basic types as per IEEE 1800-2023 35.5.6 + import "DPI-C" function void i_byte (input byte i); + import "DPI-C" function void i_byte_unsigned (input byte unsigned i); + import "DPI-C" function void i_shortint (input shortint i); + import "DPI-C" function void i_shortint_unsigned (input shortint unsigned i); + import "DPI-C" function void i_int (input int i); + import "DPI-C" function void i_int_unsigned (input int unsigned i); + import "DPI-C" function void i_longint (input longint i); + import "DPI-C" function void i_longint_unsigned (input longint unsigned i); `ifndef NO_TIME - import "DPI-C" function void i_time (input time i); + import "DPI-C" function void i_time (input time i); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer (input integer i); + import "DPI-C" function void i_integer (input integer i); `endif - import "DPI-C" function void i_real (input real i); + import "DPI-C" function void i_real (input real i); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal (input shortreal i); + import "DPI-C" function void i_shortreal (input shortreal i); `endif - import "DPI-C" function void i_chandle (input chandle i); - import "DPI-C" function void i_string (input string i); - import "DPI-C" function void i_bit (input bit i); - import "DPI-C" function void i_logic (input logic i); + import "DPI-C" function void i_chandle (input chandle i); + import "DPI-C" function void i_string (input string i); + import "DPI-C" function void i_bit (input bit i); + import "DPI-C" function void i_logic (input logic i); - // Basic types via typedef - import "DPI-C" function void i_byte_t (input byte_t i); - import "DPI-C" function void i_byte_unsigned_t (input byte_unsigned_t i); - import "DPI-C" function void i_shortint_t (input shortint_t i); - import "DPI-C" function void i_shortint_unsigned_t (input shortint_unsigned_t i); - import "DPI-C" function void i_int_t (input int_t i); - import "DPI-C" function void i_int_unsigned_t (input int_unsigned_t i); - import "DPI-C" function void i_longint_t (input longint_t i); - import "DPI-C" function void i_longint_unsigned_t (input longint_unsigned_t i); + // Basic types via typedef + import "DPI-C" function void i_byte_t (input byte_t i); + import "DPI-C" function void i_byte_unsigned_t (input byte_unsigned_t i); + import "DPI-C" function void i_shortint_t (input shortint_t i); + import "DPI-C" function void i_shortint_unsigned_t (input shortint_unsigned_t i); + import "DPI-C" function void i_int_t (input int_t i); + import "DPI-C" function void i_int_unsigned_t (input int_unsigned_t i); + import "DPI-C" function void i_longint_t (input longint_t i); + import "DPI-C" function void i_longint_unsigned_t (input longint_unsigned_t i); `ifndef NO_TIME - import "DPI-C" function void i_time_t (input time_t i); + import "DPI-C" function void i_time_t (input time_t i); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_t (input integer_t i); + import "DPI-C" function void i_integer_t (input integer_t i); `endif - import "DPI-C" function void i_real_t (input real_t i); + import "DPI-C" function void i_real_t (input real_t i); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_t (input shortreal_t i); + import "DPI-C" function void i_shortreal_t (input shortreal_t i); `endif - import "DPI-C" function void i_chandle_t (input chandle_t i); - import "DPI-C" function void i_string_t (input string_t i); - import "DPI-C" function void i_bit_t (input bit_t i); - import "DPI-C" function void i_logic_t (input logic_t i); + import "DPI-C" function void i_chandle_t (input chandle_t i); + import "DPI-C" function void i_string_t (input string_t i); + import "DPI-C" function void i_bit_t (input bit_t i); + import "DPI-C" function void i_logic_t (input logic_t i); - // 2-state packed arrays - import "DPI-C" function void i_array_2_state_1 (input bit [ 0:0] i); - import "DPI-C" function void i_array_2_state_32 (input bit [ 31:0] i); - import "DPI-C" function void i_array_2_state_33 (input bit [ 32:0] i); - import "DPI-C" function void i_array_2_state_64 (input bit [ 63:0] i); - import "DPI-C" function void i_array_2_state_65 (input bit [ 64:0] i); - import "DPI-C" function void i_array_2_state_128(input bit [127:0] i); + // 2-state packed arrays + import "DPI-C" function void i_array_2_state_1 (input bit [ 0:0] i); + import "DPI-C" function void i_array_2_state_32 (input bit [ 31:0] i); + import "DPI-C" function void i_array_2_state_33 (input bit [ 32:0] i); + import "DPI-C" function void i_array_2_state_64 (input bit [ 63:0] i); + import "DPI-C" function void i_array_2_state_65 (input bit [ 64:0] i); + import "DPI-C" function void i_array_2_state_128(input bit [127:0] i); - // 2-state packed structures - import "DPI-C" function void i_struct_2_state_1 (input struct_2_state_1 i); - import "DPI-C" function void i_struct_2_state_32 (input struct_2_state_32 i); - import "DPI-C" function void i_struct_2_state_33 (input struct_2_state_33 i); - import "DPI-C" function void i_struct_2_state_64 (input struct_2_state_64 i); - import "DPI-C" function void i_struct_2_state_65 (input struct_2_state_65 i); - import "DPI-C" function void i_struct_2_state_128 (input struct_2_state_128 i); + // 2-state packed structures + import "DPI-C" function void i_struct_2_state_1 (input struct_2_state_1 i); + import "DPI-C" function void i_struct_2_state_32 (input struct_2_state_32 i); + import "DPI-C" function void i_struct_2_state_33 (input struct_2_state_33 i); + import "DPI-C" function void i_struct_2_state_64 (input struct_2_state_64 i); + import "DPI-C" function void i_struct_2_state_65 (input struct_2_state_65 i); + import "DPI-C" function void i_struct_2_state_128 (input struct_2_state_128 i); - // 2-state packed unions - import "DPI-C" function void i_union_2_state_1 (input union_2_state_1 i); - import "DPI-C" function void i_union_2_state_32 (input union_2_state_32 i); - import "DPI-C" function void i_union_2_state_33 (input union_2_state_33 i); - import "DPI-C" function void i_union_2_state_64 (input union_2_state_64 i); - import "DPI-C" function void i_union_2_state_65 (input union_2_state_65 i); - import "DPI-C" function void i_union_2_state_128(input union_2_state_128 i); + // 2-state packed unions + import "DPI-C" function void i_union_2_state_1 (input union_2_state_1 i); + import "DPI-C" function void i_union_2_state_32 (input union_2_state_32 i); + import "DPI-C" function void i_union_2_state_33 (input union_2_state_33 i); + import "DPI-C" function void i_union_2_state_64 (input union_2_state_64 i); + import "DPI-C" function void i_union_2_state_65 (input union_2_state_65 i); + import "DPI-C" function void i_union_2_state_128(input union_2_state_128 i); - // 4-state packed arrays - import "DPI-C" function void i_array_4_state_1 (input logic [ 0:0] i); - import "DPI-C" function void i_array_4_state_32 (input logic [ 31:0] i); - import "DPI-C" function void i_array_4_state_33 (input logic [ 32:0] i); - import "DPI-C" function void i_array_4_state_64 (input logic [ 63:0] i); - import "DPI-C" function void i_array_4_state_65 (input logic [ 64:0] i); - import "DPI-C" function void i_array_4_state_128(input logic [127:0] i); + // 4-state packed arrays + import "DPI-C" function void i_array_4_state_1 (input logic [ 0:0] i); + import "DPI-C" function void i_array_4_state_32 (input logic [ 31:0] i); + import "DPI-C" function void i_array_4_state_33 (input logic [ 32:0] i); + import "DPI-C" function void i_array_4_state_64 (input logic [ 63:0] i); + import "DPI-C" function void i_array_4_state_65 (input logic [ 64:0] i); + import "DPI-C" function void i_array_4_state_128(input logic [127:0] i); - // 4-state packed structures - import "DPI-C" function void i_struct_4_state_1 (input struct_4_state_1 i); - import "DPI-C" function void i_struct_4_state_32 (input struct_4_state_32 i); - import "DPI-C" function void i_struct_4_state_33 (input struct_4_state_33 i); - import "DPI-C" function void i_struct_4_state_64 (input struct_4_state_64 i); - import "DPI-C" function void i_struct_4_state_65 (input struct_4_state_65 i); - import "DPI-C" function void i_struct_4_state_128 (input struct_4_state_128 i); + // 4-state packed structures + import "DPI-C" function void i_struct_4_state_1 (input struct_4_state_1 i); + import "DPI-C" function void i_struct_4_state_32 (input struct_4_state_32 i); + import "DPI-C" function void i_struct_4_state_33 (input struct_4_state_33 i); + import "DPI-C" function void i_struct_4_state_64 (input struct_4_state_64 i); + import "DPI-C" function void i_struct_4_state_65 (input struct_4_state_65 i); + import "DPI-C" function void i_struct_4_state_128 (input struct_4_state_128 i); - // 4-state packed unions - import "DPI-C" function void i_union_4_state_1 (input union_4_state_1 i); - import "DPI-C" function void i_union_4_state_32 (input union_4_state_32 i); - import "DPI-C" function void i_union_4_state_33 (input union_4_state_33 i); - import "DPI-C" function void i_union_4_state_64 (input union_4_state_64 i); - import "DPI-C" function void i_union_4_state_65 (input union_4_state_65 i); - import "DPI-C" function void i_union_4_state_128(input union_4_state_128 i); + // 4-state packed unions + import "DPI-C" function void i_union_4_state_1 (input union_4_state_1 i); + import "DPI-C" function void i_union_4_state_32 (input union_4_state_32 i); + import "DPI-C" function void i_union_4_state_33 (input union_4_state_33 i); + import "DPI-C" function void i_union_4_state_64 (input union_4_state_64 i); + import "DPI-C" function void i_union_4_state_65 (input union_4_state_65 i); + import "DPI-C" function void i_union_4_state_128(input union_4_state_128 i); - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - export "DPI-C" function e_byte; - export "DPI-C" function e_byte_unsigned; - export "DPI-C" function e_shortint; - export "DPI-C" function e_shortint_unsigned; - export "DPI-C" function e_int; - export "DPI-C" function e_int_unsigned; - export "DPI-C" function e_longint; - export "DPI-C" function e_longint_unsigned; + // Basic types as per IEEE 1800-2023 35.5.6 + export "DPI-C" function e_byte; + export "DPI-C" function e_byte_unsigned; + export "DPI-C" function e_shortint; + export "DPI-C" function e_shortint_unsigned; + export "DPI-C" function e_int; + export "DPI-C" function e_int_unsigned; + export "DPI-C" function e_longint; + export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME - export "DPI-C" function e_time; + export "DPI-C" function e_time; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer; + export "DPI-C" function e_integer; `endif - export "DPI-C" function e_real; + export "DPI-C" function e_real; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal; + export "DPI-C" function e_shortreal; `endif - export "DPI-C" function e_chandle; - export "DPI-C" function e_string; - export "DPI-C" function e_bit; - export "DPI-C" function e_logic; + export "DPI-C" function e_chandle; + export "DPI-C" function e_string; + export "DPI-C" function e_bit; + export "DPI-C" function e_logic; - // Basic types via typedef - export "DPI-C" function e_byte_t; - export "DPI-C" function e_byte_unsigned_t; - export "DPI-C" function e_shortint_t; - export "DPI-C" function e_shortint_unsigned_t; - export "DPI-C" function e_int_t; - export "DPI-C" function e_int_unsigned_t; - export "DPI-C" function e_longint_t; - export "DPI-C" function e_longint_unsigned_t; + // Basic types via typedef + export "DPI-C" function e_byte_t; + export "DPI-C" function e_byte_unsigned_t; + export "DPI-C" function e_shortint_t; + export "DPI-C" function e_shortint_unsigned_t; + export "DPI-C" function e_int_t; + export "DPI-C" function e_int_unsigned_t; + export "DPI-C" function e_longint_t; + export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME - export "DPI-C" function e_time_t; + export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_t; + export "DPI-C" function e_integer_t; `endif - export "DPI-C" function e_real_t; + export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_t; + export "DPI-C" function e_shortreal_t; `endif - export "DPI-C" function e_chandle_t; - export "DPI-C" function e_string_t; - export "DPI-C" function e_bit_t; - export "DPI-C" function e_logic_t; + export "DPI-C" function e_chandle_t; + export "DPI-C" function e_string_t; + export "DPI-C" function e_bit_t; + export "DPI-C" function e_logic_t; - // 2-state packed arrays - export "DPI-C" function e_array_2_state_1; - export "DPI-C" function e_array_2_state_32; - export "DPI-C" function e_array_2_state_33; - export "DPI-C" function e_array_2_state_64; - export "DPI-C" function e_array_2_state_65; - export "DPI-C" function e_array_2_state_128; + // 2-state packed arrays + export "DPI-C" function e_array_2_state_1; + export "DPI-C" function e_array_2_state_32; + export "DPI-C" function e_array_2_state_33; + export "DPI-C" function e_array_2_state_64; + export "DPI-C" function e_array_2_state_65; + export "DPI-C" function e_array_2_state_128; - // 2-state packed structures - export "DPI-C" function e_struct_2_state_1; - export "DPI-C" function e_struct_2_state_32; - export "DPI-C" function e_struct_2_state_33; - export "DPI-C" function e_struct_2_state_64; - export "DPI-C" function e_struct_2_state_65; - export "DPI-C" function e_struct_2_state_128; + // 2-state packed structures + export "DPI-C" function e_struct_2_state_1; + export "DPI-C" function e_struct_2_state_32; + export "DPI-C" function e_struct_2_state_33; + export "DPI-C" function e_struct_2_state_64; + export "DPI-C" function e_struct_2_state_65; + export "DPI-C" function e_struct_2_state_128; - // 2-state packed unions - export "DPI-C" function e_union_2_state_1; - export "DPI-C" function e_union_2_state_32; - export "DPI-C" function e_union_2_state_33; - export "DPI-C" function e_union_2_state_64; - export "DPI-C" function e_union_2_state_65; - export "DPI-C" function e_union_2_state_128; + // 2-state packed unions + export "DPI-C" function e_union_2_state_1; + export "DPI-C" function e_union_2_state_32; + export "DPI-C" function e_union_2_state_33; + export "DPI-C" function e_union_2_state_64; + export "DPI-C" function e_union_2_state_65; + export "DPI-C" function e_union_2_state_128; - // 4-state packed arrays - export "DPI-C" function e_array_4_state_1; - export "DPI-C" function e_array_4_state_32; - export "DPI-C" function e_array_4_state_33; - export "DPI-C" function e_array_4_state_64; - export "DPI-C" function e_array_4_state_65; - export "DPI-C" function e_array_4_state_128; + // 4-state packed arrays + export "DPI-C" function e_array_4_state_1; + export "DPI-C" function e_array_4_state_32; + export "DPI-C" function e_array_4_state_33; + export "DPI-C" function e_array_4_state_64; + export "DPI-C" function e_array_4_state_65; + export "DPI-C" function e_array_4_state_128; - // 4-state packed structures - export "DPI-C" function e_struct_4_state_1; - export "DPI-C" function e_struct_4_state_32; - export "DPI-C" function e_struct_4_state_33; - export "DPI-C" function e_struct_4_state_64; - export "DPI-C" function e_struct_4_state_65; - export "DPI-C" function e_struct_4_state_128; + // 4-state packed structures + export "DPI-C" function e_struct_4_state_1; + export "DPI-C" function e_struct_4_state_32; + export "DPI-C" function e_struct_4_state_33; + export "DPI-C" function e_struct_4_state_64; + export "DPI-C" function e_struct_4_state_65; + export "DPI-C" function e_struct_4_state_128; - // 4-state packed unions - export "DPI-C" function e_union_4_state_1; - export "DPI-C" function e_union_4_state_32; - export "DPI-C" function e_union_4_state_33; - export "DPI-C" function e_union_4_state_64; - export "DPI-C" function e_union_4_state_65; - export "DPI-C" function e_union_4_state_128; + // 4-state packed unions + export "DPI-C" function e_union_4_state_1; + export "DPI-C" function e_union_4_state_32; + export "DPI-C" function e_union_4_state_33; + export "DPI-C" function e_union_4_state_64; + export "DPI-C" function e_union_4_state_65; + export "DPI-C" function e_union_4_state_128; - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - byte n_byte = 0; - function void e_byte(input byte i); - if (i !== 8'd10 + n_byte) $stop; - n_byte++; - endfunction + // Basic types as per IEEE 1800-2023 35.5.6 + byte n_byte = 0; + function void e_byte(input byte i); + if (i !== 8'd10 + n_byte) $stop; + n_byte++; + endfunction - byte n_byte_unsigned = 0; - function void e_byte_unsigned(input byte unsigned i); - if (i !== 8'd20 + n_byte_unsigned) $stop; - n_byte_unsigned++; - endfunction + byte n_byte_unsigned = 0; + function void e_byte_unsigned(input byte unsigned i); + if (i !== 8'd20 + n_byte_unsigned) $stop; + n_byte_unsigned++; + endfunction - shortint n_shortint = 0; - function void e_shortint(input shortint i); - if (i !== 16'd30 + n_shortint) $stop; - n_shortint++; - endfunction + shortint n_shortint = 0; + function void e_shortint(input shortint i); + if (i !== 16'd30 + n_shortint) $stop; + n_shortint++; + endfunction - shortint n_shortint_unsigned = 0; - function void e_shortint_unsigned(input shortint unsigned i); - if (i !== 16'd40 + n_shortint_unsigned) $stop; - n_shortint_unsigned++; - endfunction + shortint n_shortint_unsigned = 0; + function void e_shortint_unsigned(input shortint unsigned i); + if (i !== 16'd40 + n_shortint_unsigned) $stop; + n_shortint_unsigned++; + endfunction - int n_int = 0; - function void e_int(input int i); - if (i !== 32'd50 + n_int) $stop; - n_int++; - endfunction + int n_int = 0; + function void e_int(input int i); + if (i !== 32'd50 + n_int) $stop; + n_int++; + endfunction - int n_int_unsigned = 0; - function void e_int_unsigned(input int unsigned i); - if (i !== 32'd60 + n_int_unsigned) $stop; - n_int_unsigned++; - endfunction + int n_int_unsigned = 0; + function void e_int_unsigned(input int unsigned i); + if (i !== 32'd60 + n_int_unsigned) $stop; + n_int_unsigned++; + endfunction - longint n_longint = 0; - function void e_longint(input longint i); - if (i !== 64'd70 + n_longint) $stop; - n_longint++; - endfunction + longint n_longint = 0; + function void e_longint(input longint i); + if (i !== 64'd70 + n_longint) $stop; + n_longint++; + endfunction - longint n_longint_unsigned = 0; - function void e_longint_unsigned(input longint unsigned i); - if (i !== 64'd80 + n_longint_unsigned) $stop; - n_longint_unsigned++; - endfunction + longint n_longint_unsigned = 0; + function void e_longint_unsigned(input longint unsigned i); + if (i !== 64'd80 + n_longint_unsigned) $stop; + n_longint_unsigned++; + endfunction `ifndef NO_TIME - longint n_time = 0; - function void e_time(input time i); - if (i !== 64'd90 + n_time) $stop; - n_time++; - endfunction + longint n_time = 0; + function void e_time(input time i); + if (i !== 64'd90 + n_time) $stop; + n_time++; + endfunction `endif `ifndef NO_INTEGER - int n_integer = 0; - function void e_integer(input integer i); - if (i !== 32'd100 + n_integer) $stop; - n_integer++; - endfunction + int n_integer = 0; + function void e_integer(input integer i); + if (i !== 32'd100 + n_integer) $stop; + n_integer++; + endfunction `endif - int n_real = 0; - function void e_real(input real i); - if (i != real'(2*n_real + 1) / 2.0) $stop; - n_real++; - endfunction + int n_real = 0; + function void e_real(input real i); + if (i != real'(2*n_real + 1) / 2.0) $stop; + n_real++; + endfunction `ifndef NO_SHORTREAL - int n_shortreal = 0; - function void e_shortreal(input shortreal i); - if (i != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; - n_shortreal++; - endfunction + int n_shortreal = 0; + function void e_shortreal(input shortreal i); + if (i != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; + n_shortreal++; + endfunction `endif - int n_chandle = 0; - function void e_chandle(input chandle i); - $display("e_chandle %1d", n_chandle); - if (!n_chandle[0]) begin - if (i !== `NULL) $stop; + int n_chandle = 0; + function void e_chandle(input chandle i); + $display("e_chandle %1d", n_chandle); + if (!n_chandle[0]) begin + if (i !== `NULL) $stop; + end else begin + if (i === `NULL) $stop; + end + n_chandle++; + endfunction + + int n_string = 0; + function void e_string(input string i); + $display("e_string %1d", n_string); + if (!n_string[0]) begin + if (i != "Hello") $stop; + end else begin + if (i != "World") $stop; + end + n_string++; + endfunction + + int n_bit = 0; + function void e_bit(input bit i); + $display("e_bit %1d", n_bit); + if (i !== n_bit[0]) $stop; + n_bit++; + endfunction + + int n_logic = 0; + function void e_logic(input logic i); + $display("e_logic %1d", n_logic); + if (i !== ~n_logic[0]) $stop; + n_logic++; + endfunction + + // Basic types via typedefs + byte_t n_byte_t = 0; + function void e_byte_t(input byte_t i); + if (i !== 8'd10 + n_byte_t) $stop; + n_byte_t += 2; + endfunction + + byte n_byte_unsigned_t = 0; + function void e_byte_unsigned_t(input byte_unsigned_t i); + if (i !== 8'd20 + n_byte_unsigned_t) $stop; + n_byte_unsigned_t += 2; + endfunction + + shortint_t n_shortint_t = 0; + function void e_shortint_t(input shortint_t i); + if (i !== 16'd30 + n_shortint_t) $stop; + n_shortint_t += 2; + endfunction + + shortint n_shortint_unsigned_t = 0; + function void e_shortint_unsigned_t(input shortint_unsigned_t i); + if (i !== 16'd40 + n_shortint_unsigned_t) $stop; + n_shortint_unsigned_t += 2; + endfunction + + int_t n_int_t = 0; + function void e_int_t(input int_t i); + if (i !== 32'd50 + n_int_t) $stop; + n_int_t += 2; + endfunction + + int n_int_unsigned_t = 0; + function void e_int_unsigned_t(input int_unsigned_t i); + if (i !== 32'd60 + n_int_unsigned_t) $stop; + n_int_unsigned_t += 2; + endfunction + + longint_t n_longint_t = 0; + function void e_longint_t(input longint_t i); + if (i !== 64'd70 + n_longint_t) $stop; + n_longint_t += 2; + endfunction + + longint n_longint_unsigned_t = 0; + function void e_longint_unsigned_t(input longint_unsigned_t i); + if (i !== 64'd80 + n_longint_unsigned_t) $stop; + n_longint_unsigned_t += 2; + endfunction + +`ifndef NO_TIME + longint n_time_t = 0; + function void e_time_t(input time_t i); + if (i !== 64'd90 + n_time_t) $stop; + n_time_t += 2; + endfunction +`endif + +`ifndef NO_INTEGER + int n_integer_t = 0; + function void e_integer_t(input integer_t i); + if (i !== 32'd100 + n_integer_t) $stop; + n_integer_t += 2; + endfunction +`endif + + int n_real_t = 0; + function void e_real_t(input real_t i); + if (i != real'(2*n_real_t + 1) / 2.0) $stop; + n_real_t += 2; + endfunction + +`ifndef NO_SHORTREAL + int n_shortreal_t = 0; + function void e_shortreal_t(input shortreal_t i); + if (i != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; + n_shortreal_t += 2; + endfunction +`endif + + int n_chandle_t = 0; + function void e_chandle_t(input chandle_t i); + $display("e_chandle_t %1d", n_chandle_t); + if (!n_chandle_t[0]) begin + if (i === `NULL) $stop; + end else begin + if (i !== `NULL) $stop; + end + n_chandle_t++; + endfunction + + int n_string_t = 0; + function void e_string_t(input string_t i); + $display("e_string_t %1d", n_string_t); + if (!n_string_t[0]) begin + if (i != "World") $stop; + end else begin + if (i != "Hello") $stop; + end + n_string_t++; + endfunction + + int n_bit_t = 0; + function void e_bit_t(input bit_t i); + $display("e_bit_t %1d", n_bit_t); + if (i !== n_bit_t[0]) $stop; + n_bit_t++; + endfunction + + int n_logic_t = 0; + function void e_logic_t(input logic_t i); + $display("e_logic_t %1d", n_logic_t); + if (i !== ~n_logic_t[0]) $stop; + n_logic_t++; + endfunction + + // 2-state packed arrays + int n_array_2_state_1 = 0; + function void e_array_2_state_1(input bit [ 0:0] i); + $display("e_array_2_state_1 %1d", n_array_2_state_1); + if (i !== n_array_2_state_1[0]) $stop; + n_array_2_state_1++; + endfunction + + int n_array_2_state_32 = 0; + function void e_array_2_state_32(input bit [31:0] i); + $display("e_array_2_state_32 %1d", n_array_2_state_32); + if (i !== ~32'd0 >> n_array_2_state_32) $stop; + n_array_2_state_32++; + endfunction + + int n_array_2_state_33 = 0; + function void e_array_2_state_33(input bit [32:0] i); + $display("e_array_2_state_33 %1d", n_array_2_state_33); + if (i !== ~33'd0 >> n_array_2_state_33) $stop; + n_array_2_state_33++; + endfunction + + int n_array_2_state_64 = 0; + function void e_array_2_state_64(input bit [63:0] i); + $display("e_array_2_state_64 %1d", n_array_2_state_64); + if (i !== ~64'd0 >> n_array_2_state_64) $stop; + n_array_2_state_64++; + endfunction + + int n_array_2_state_65 = 0; + function void e_array_2_state_65(input bit [64:0] i); + $display("e_array_2_state_65 %1d", n_array_2_state_65); + if (i !== ~65'd0 >> n_array_2_state_65) $stop; + n_array_2_state_65++; + endfunction + + int n_array_2_state_128 = 0; + function void e_array_2_state_128(input bit [127:0] i); + $display("e_array_2_state_128 %1d", n_array_2_state_128); + if (i !== ~128'd0 >> n_array_2_state_128) $stop; + n_array_2_state_128++; + endfunction + + // 2-state packed structures + int n_struct_2_state_1 = 0; + function void e_struct_2_state_1(input struct_2_state_1 i); + $display("e_struct_2_state_1 %1d", n_struct_2_state_1); + if (i !== n_struct_2_state_1[0]) $stop; + n_struct_2_state_1++; + endfunction + + int n_struct_2_state_32 = 0; + function void e_struct_2_state_32(input struct_2_state_32 i); + $display("e_struct_2_state_32 %1d", n_struct_2_state_32); + if (i !== ~32'd0 >> n_struct_2_state_32) $stop; + n_struct_2_state_32++; + endfunction + + int n_struct_2_state_33 = 0; + function void e_struct_2_state_33(input struct_2_state_33 i); + $display("e_struct_2_state_33 %1d", n_struct_2_state_33); + if (i !== ~33'd0 >> n_struct_2_state_33) $stop; + n_struct_2_state_33++; + endfunction + + int n_struct_2_state_64 = 0; + function void e_struct_2_state_64(input struct_2_state_64 i); + $display("e_struct_2_state_64 %1d", n_struct_2_state_64); + if (i !== ~64'd0 >> n_struct_2_state_64) $stop; + n_struct_2_state_64++; + endfunction + + int n_struct_2_state_65 = 0; + function void e_struct_2_state_65(input struct_2_state_65 i); + $display("e_struct_2_state_65 %1d", n_struct_2_state_65); + if (i !== ~65'd0 >> n_struct_2_state_65) $stop; + n_struct_2_state_65++; + endfunction + + int n_struct_2_state_128 = 0; + function void e_struct_2_state_128(input struct_2_state_128 i); + $display("e_struct_2_state_128 %1d", n_struct_2_state_128); + if (i !== ~128'd0 >> n_struct_2_state_128) $stop; + n_struct_2_state_128++; + endfunction + + // 2-state packed unions + int n_union_2_state_1 = 0; + function void e_union_2_state_1(input union_2_state_1 i); + $display("e_union_2_state_1 %1d", n_union_2_state_1); + if (i !== n_union_2_state_1[0]) $stop; + n_union_2_state_1++; + endfunction + + int n_union_2_state_32 = 0; + function void e_union_2_state_32(input union_2_state_32 i); + $display("e_union_2_state_32 %1d", n_union_2_state_32); + if (i !== ~32'd0 >> n_union_2_state_32) $stop; + n_union_2_state_32++; + endfunction + + int n_union_2_state_33 = 0; + function void e_union_2_state_33(input union_2_state_33 i); + $display("e_union_2_state_33 %1d", n_union_2_state_33); + if (i !== ~33'd0 >> n_union_2_state_33) $stop; + n_union_2_state_33++; + endfunction + + int n_union_2_state_64 = 0; + function void e_union_2_state_64(input union_2_state_64 i); + $display("e_union_2_state_64 %1d", n_union_2_state_64); + if (i !== ~64'd0 >> n_union_2_state_64) $stop; + n_union_2_state_64++; + endfunction + + int n_union_2_state_65 = 0; + function void e_union_2_state_65(input union_2_state_65 i); + $display("e_union_2_state_65 %1d", n_union_2_state_65); + if (i !== ~65'd0 >> n_union_2_state_65) $stop; + n_union_2_state_65++; + endfunction + + int n_union_2_state_128 = 0; + function void e_union_2_state_128(input union_2_state_128 i); + $display("e_union_2_state_128 %1d", n_union_2_state_128); + if (i !== ~128'd0 >> n_union_2_state_128) $stop; + n_union_2_state_128++; + endfunction + + // 4-state packed arrays + int n_array_4_state_1 = 0; + function void e_array_4_state_1(input logic [ 0:0] i); + $display("e_array_4_state_1 %1d", n_array_4_state_1); + if (i !== n_array_4_state_1[0]) $stop; + n_array_4_state_1++; + endfunction + + int n_array_4_state_32 = 0; + function void e_array_4_state_32(input logic [31:0] i); + $display("e_array_4_state_32 %1d", n_array_4_state_32); + if (i !== ~32'd0 >> n_array_4_state_32) $stop; + n_array_4_state_32++; + endfunction + + int n_array_4_state_33 = 0; + function void e_array_4_state_33(input logic [32:0] i); + $display("e_array_4_state_33 %1d", n_array_4_state_33); + if (i !== ~33'd0 >> n_array_4_state_33) $stop; + n_array_4_state_33++; + endfunction + + int n_array_4_state_64 = 0; + function void e_array_4_state_64(input logic [63:0] i); + $display("e_array_4_state_64 %1d", n_array_4_state_64); + if (i !== ~64'd0 >> n_array_4_state_64) $stop; + n_array_4_state_64++; + endfunction + + int n_array_4_state_65 = 0; + function void e_array_4_state_65(input logic [64:0] i); + $display("e_array_4_state_65 %1d", n_array_4_state_65); + if (i !== ~65'd0 >> n_array_4_state_65) $stop; + n_array_4_state_65++; + endfunction + + int n_array_4_state_128 = 0; + function void e_array_4_state_128(input logic [127:0] i); + $display("e_array_4_state_128 %1d", n_array_4_state_128); + if (i !== ~128'd0 >> n_array_4_state_128) $stop; + n_array_4_state_128++; + endfunction + + // 4-state packed structures + int n_struct_4_state_1 = 0; + function void e_struct_4_state_1(input struct_4_state_1 i); + $display("e_struct_4_state_1 %1d", n_struct_4_state_1); + if (i !== n_struct_4_state_1[0]) $stop; + n_struct_4_state_1++; + endfunction + + int n_struct_4_state_32 = 0; + function void e_struct_4_state_32(input struct_4_state_32 i); + $display("e_struct_4_state_32 %1d", n_struct_4_state_32); + if (i !== ~32'd0 >> n_struct_4_state_32) $stop; + n_struct_4_state_32++; + endfunction + + int n_struct_4_state_33 = 0; + function void e_struct_4_state_33(input struct_4_state_33 i); + $display("e_struct_4_state_33 %1d", n_struct_4_state_33); + if (i !== ~33'd0 >> n_struct_4_state_33) $stop; + n_struct_4_state_33++; + endfunction + + int n_struct_4_state_64 = 0; + function void e_struct_4_state_64(input struct_4_state_64 i); + $display("e_struct_4_state_64 %1d", n_struct_4_state_64); + if (i !== ~64'd0 >> n_struct_4_state_64) $stop; + n_struct_4_state_64++; + endfunction + + int n_struct_4_state_65 = 0; + function void e_struct_4_state_65(input struct_4_state_65 i); + $display("e_struct_4_state_65 %1d", n_struct_4_state_65); + if (i !== ~65'd0 >> n_struct_4_state_65) $stop; + n_struct_4_state_65++; + endfunction + + int n_struct_4_state_128 = 0; + function void e_struct_4_state_128(input struct_4_state_128 i); + $display("e_struct_4_state_128 %1d", n_struct_4_state_128); + if (i !== ~128'd0 >> n_struct_4_state_128) $stop; + n_struct_4_state_128++; + endfunction + + // 4-state packed unions + int n_union_4_state_1 = 0; + function void e_union_4_state_1(input union_4_state_1 i); + $display("e_union_4_state_1 %1d", n_union_4_state_1); + if (i !== n_union_4_state_1[0]) $stop; + n_union_4_state_1++; + endfunction + + int n_union_4_state_32 = 0; + function void e_union_4_state_32(input union_4_state_32 i); + $display("e_union_4_state_32 %1d", n_union_4_state_32); + if (i !== ~32'd0 >> n_union_4_state_32) $stop; + n_union_4_state_32++; + endfunction + + int n_union_4_state_33 = 0; + function void e_union_4_state_33(input union_4_state_33 i); + $display("e_union_4_state_33 %1d", n_union_4_state_33); + if (i !== ~33'd0 >> n_union_4_state_33) $stop; + n_union_4_state_33++; + endfunction + + int n_union_4_state_64 = 0; + function void e_union_4_state_64(input union_4_state_64 i); + $display("e_union_4_state_64 %1d", n_union_4_state_64); + if (i !== ~64'd0 >> n_union_4_state_64) $stop; + n_union_4_state_64++; + endfunction + + int n_union_4_state_65 = 0; + function void e_union_4_state_65(input union_4_state_65 i); + $display("e_union_4_state_65 %1d", n_union_4_state_65); + if (i !== ~65'd0 >> n_union_4_state_65) $stop; + n_union_4_state_65++; + endfunction + + int n_union_4_state_128 = 0; + function void e_union_4_state_128(input union_4_state_128 i); + $display("e_union_4_state_128 %1d", n_union_4_state_128); + if (i !== ~128'd0 >> n_union_4_state_128) $stop; + n_union_4_state_128++; + endfunction + + //====================================================================== + // Invoke all functions 3 times (they have side effects) + //====================================================================== + + import "DPI-C" context function void check_exports(); + + initial begin + for (int i = 0 ; i < 3; i++) begin + // Check the imports + + // Basic types as per IEEE 1800-2023 35.5.6 + i_byte( 8'd10 - 8'(i)); + i_byte_unsigned( 8'd20 - 8'(i)); + i_shortint( 16'd30 - 16'(i)); + i_shortint_unsigned( 16'd40 - 16'(i)); + i_int( 32'd50 - 32'(i)); + i_int_unsigned( 32'd60 - 32'(i)); + i_longint( 64'd70 - 64'(i)); + i_longint_unsigned( 64'd80 - 64'(i)); +`ifndef NO_TIME + i_time( 64'd90 - 64'(i)); +`endif +`ifndef NO_INTEGER + i_integer( 32'd100- 32'(i)); +`endif + i_real( -1.0*i - 0.50); +`ifndef NO_SHORTREAL + i_shortreal( -1.0*i - 0.25); +`endif + if (~i[0]) begin + i_chandle(`NULL); + i_string("World"); end else begin - if (i === `NULL) $stop; + i_chandle(`NULL); + i_string("Hello"); end - n_chandle++; - endfunction - - int n_string = 0; - function void e_string(input string i); - $display("e_string %1d", n_string); - if (!n_string[0]) begin - if (i != "Hello") $stop; - end else begin - if (i != "World") $stop; - end - n_string++; - endfunction - - int n_bit = 0; - function void e_bit(input bit i); - $display("e_bit %1d", n_bit); - if (i !== n_bit[0]) $stop; - n_bit++; - endfunction - - int n_logic = 0; - function void e_logic(input logic i); - $display("e_logic %1d", n_logic); - if (i !== ~n_logic[0]) $stop; - n_logic++; - endfunction - - // Basic types via typedefs - byte_t n_byte_t = 0; - function void e_byte_t(input byte_t i); - if (i !== 8'd10 + n_byte_t) $stop; - n_byte_t += 2; - endfunction - - byte n_byte_unsigned_t = 0; - function void e_byte_unsigned_t(input byte_unsigned_t i); - if (i !== 8'd20 + n_byte_unsigned_t) $stop; - n_byte_unsigned_t += 2; - endfunction - - shortint_t n_shortint_t = 0; - function void e_shortint_t(input shortint_t i); - if (i !== 16'd30 + n_shortint_t) $stop; - n_shortint_t += 2; - endfunction - - shortint n_shortint_unsigned_t = 0; - function void e_shortint_unsigned_t(input shortint_unsigned_t i); - if (i !== 16'd40 + n_shortint_unsigned_t) $stop; - n_shortint_unsigned_t += 2; - endfunction - - int_t n_int_t = 0; - function void e_int_t(input int_t i); - if (i !== 32'd50 + n_int_t) $stop; - n_int_t += 2; - endfunction - - int n_int_unsigned_t = 0; - function void e_int_unsigned_t(input int_unsigned_t i); - if (i !== 32'd60 + n_int_unsigned_t) $stop; - n_int_unsigned_t += 2; - endfunction - - longint_t n_longint_t = 0; - function void e_longint_t(input longint_t i); - if (i !== 64'd70 + n_longint_t) $stop; - n_longint_t += 2; - endfunction - - longint n_longint_unsigned_t = 0; - function void e_longint_unsigned_t(input longint_unsigned_t i); - if (i !== 64'd80 + n_longint_unsigned_t) $stop; - n_longint_unsigned_t += 2; - endfunction + i_bit(~i[0]); + i_logic(i[0]); + // Basic types via typedefs + i_byte_t( 8'd10 - 8'(2*i)); + i_byte_unsigned_t( 8'd20 - 8'(2*i)); + i_shortint_t( 16'd30 - 16'(2*i)); + i_shortint_unsigned_t( 16'd40 - 16'(2*i)); + i_int_t( 32'd50 - 32'(2*i)); + i_int_unsigned_t( 32'd60 - 32'(2*i)); + i_longint_t( 64'd70 - 64'(2*i)); + i_longint_unsigned_t( 64'd80 - 64'(2*i)); `ifndef NO_TIME - longint n_time_t = 0; - function void e_time_t(input time_t i); - if (i !== 64'd90 + n_time_t) $stop; - n_time_t += 2; - endfunction -`endif - -`ifndef NO_INTEGER - int n_integer_t = 0; - function void e_integer_t(input integer_t i); - if (i !== 32'd100 + n_integer_t) $stop; - n_integer_t += 2; - endfunction -`endif - - int n_real_t = 0; - function void e_real_t(input real_t i); - if (i != real'(2*n_real_t + 1) / 2.0) $stop; - n_real_t += 2; - endfunction - -`ifndef NO_SHORTREAL - int n_shortreal_t = 0; - function void e_shortreal_t(input shortreal_t i); - if (i != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; - n_shortreal_t += 2; - endfunction -`endif - - int n_chandle_t = 0; - function void e_chandle_t(input chandle_t i); - $display("e_chandle_t %1d", n_chandle_t); - if (!n_chandle_t[0]) begin - if (i === `NULL) $stop; - end else begin - if (i !== `NULL) $stop; - end - n_chandle_t++; - endfunction - - int n_string_t = 0; - function void e_string_t(input string_t i); - $display("e_string_t %1d", n_string_t); - if (!n_string_t[0]) begin - if (i != "World") $stop; - end else begin - if (i != "Hello") $stop; - end - n_string_t++; - endfunction - - int n_bit_t = 0; - function void e_bit_t(input bit_t i); - $display("e_bit_t %1d", n_bit_t); - if (i !== n_bit_t[0]) $stop; - n_bit_t++; - endfunction - - int n_logic_t = 0; - function void e_logic_t(input logic_t i); - $display("e_logic_t %1d", n_logic_t); - if (i !== ~n_logic_t[0]) $stop; - n_logic_t++; - endfunction - - // 2-state packed arrays - int n_array_2_state_1 = 0; - function void e_array_2_state_1(input bit [ 0:0] i); - $display("e_array_2_state_1 %1d", n_array_2_state_1); - if (i !== n_array_2_state_1[0]) $stop; - n_array_2_state_1++; - endfunction - - int n_array_2_state_32 = 0; - function void e_array_2_state_32(input bit [31:0] i); - $display("e_array_2_state_32 %1d", n_array_2_state_32); - if (i !== ~32'd0 >> n_array_2_state_32) $stop; - n_array_2_state_32++; - endfunction - - int n_array_2_state_33 = 0; - function void e_array_2_state_33(input bit [32:0] i); - $display("e_array_2_state_33 %1d", n_array_2_state_33); - if (i !== ~33'd0 >> n_array_2_state_33) $stop; - n_array_2_state_33++; - endfunction - - int n_array_2_state_64 = 0; - function void e_array_2_state_64(input bit [63:0] i); - $display("e_array_2_state_64 %1d", n_array_2_state_64); - if (i !== ~64'd0 >> n_array_2_state_64) $stop; - n_array_2_state_64++; - endfunction - - int n_array_2_state_65 = 0; - function void e_array_2_state_65(input bit [64:0] i); - $display("e_array_2_state_65 %1d", n_array_2_state_65); - if (i !== ~65'd0 >> n_array_2_state_65) $stop; - n_array_2_state_65++; - endfunction - - int n_array_2_state_128 = 0; - function void e_array_2_state_128(input bit [127:0] i); - $display("e_array_2_state_128 %1d", n_array_2_state_128); - if (i !== ~128'd0 >> n_array_2_state_128) $stop; - n_array_2_state_128++; - endfunction - - // 2-state packed structures - int n_struct_2_state_1 = 0; - function void e_struct_2_state_1(input struct_2_state_1 i); - $display("e_struct_2_state_1 %1d", n_struct_2_state_1); - if (i !== n_struct_2_state_1[0]) $stop; - n_struct_2_state_1++; - endfunction - - int n_struct_2_state_32 = 0; - function void e_struct_2_state_32(input struct_2_state_32 i); - $display("e_struct_2_state_32 %1d", n_struct_2_state_32); - if (i !== ~32'd0 >> n_struct_2_state_32) $stop; - n_struct_2_state_32++; - endfunction - - int n_struct_2_state_33 = 0; - function void e_struct_2_state_33(input struct_2_state_33 i); - $display("e_struct_2_state_33 %1d", n_struct_2_state_33); - if (i !== ~33'd0 >> n_struct_2_state_33) $stop; - n_struct_2_state_33++; - endfunction - - int n_struct_2_state_64 = 0; - function void e_struct_2_state_64(input struct_2_state_64 i); - $display("e_struct_2_state_64 %1d", n_struct_2_state_64); - if (i !== ~64'd0 >> n_struct_2_state_64) $stop; - n_struct_2_state_64++; - endfunction - - int n_struct_2_state_65 = 0; - function void e_struct_2_state_65(input struct_2_state_65 i); - $display("e_struct_2_state_65 %1d", n_struct_2_state_65); - if (i !== ~65'd0 >> n_struct_2_state_65) $stop; - n_struct_2_state_65++; - endfunction - - int n_struct_2_state_128 = 0; - function void e_struct_2_state_128(input struct_2_state_128 i); - $display("e_struct_2_state_128 %1d", n_struct_2_state_128); - if (i !== ~128'd0 >> n_struct_2_state_128) $stop; - n_struct_2_state_128++; - endfunction - - // 2-state packed unions - int n_union_2_state_1 = 0; - function void e_union_2_state_1(input union_2_state_1 i); - $display("e_union_2_state_1 %1d", n_union_2_state_1); - if (i !== n_union_2_state_1[0]) $stop; - n_union_2_state_1++; - endfunction - - int n_union_2_state_32 = 0; - function void e_union_2_state_32(input union_2_state_32 i); - $display("e_union_2_state_32 %1d", n_union_2_state_32); - if (i !== ~32'd0 >> n_union_2_state_32) $stop; - n_union_2_state_32++; - endfunction - - int n_union_2_state_33 = 0; - function void e_union_2_state_33(input union_2_state_33 i); - $display("e_union_2_state_33 %1d", n_union_2_state_33); - if (i !== ~33'd0 >> n_union_2_state_33) $stop; - n_union_2_state_33++; - endfunction - - int n_union_2_state_64 = 0; - function void e_union_2_state_64(input union_2_state_64 i); - $display("e_union_2_state_64 %1d", n_union_2_state_64); - if (i !== ~64'd0 >> n_union_2_state_64) $stop; - n_union_2_state_64++; - endfunction - - int n_union_2_state_65 = 0; - function void e_union_2_state_65(input union_2_state_65 i); - $display("e_union_2_state_65 %1d", n_union_2_state_65); - if (i !== ~65'd0 >> n_union_2_state_65) $stop; - n_union_2_state_65++; - endfunction - - int n_union_2_state_128 = 0; - function void e_union_2_state_128(input union_2_state_128 i); - $display("e_union_2_state_128 %1d", n_union_2_state_128); - if (i !== ~128'd0 >> n_union_2_state_128) $stop; - n_union_2_state_128++; - endfunction - - // 4-state packed arrays - int n_array_4_state_1 = 0; - function void e_array_4_state_1(input logic [ 0:0] i); - $display("e_array_4_state_1 %1d", n_array_4_state_1); - if (i !== n_array_4_state_1[0]) $stop; - n_array_4_state_1++; - endfunction - - int n_array_4_state_32 = 0; - function void e_array_4_state_32(input logic [31:0] i); - $display("e_array_4_state_32 %1d", n_array_4_state_32); - if (i !== ~32'd0 >> n_array_4_state_32) $stop; - n_array_4_state_32++; - endfunction - - int n_array_4_state_33 = 0; - function void e_array_4_state_33(input logic [32:0] i); - $display("e_array_4_state_33 %1d", n_array_4_state_33); - if (i !== ~33'd0 >> n_array_4_state_33) $stop; - n_array_4_state_33++; - endfunction - - int n_array_4_state_64 = 0; - function void e_array_4_state_64(input logic [63:0] i); - $display("e_array_4_state_64 %1d", n_array_4_state_64); - if (i !== ~64'd0 >> n_array_4_state_64) $stop; - n_array_4_state_64++; - endfunction - - int n_array_4_state_65 = 0; - function void e_array_4_state_65(input logic [64:0] i); - $display("e_array_4_state_65 %1d", n_array_4_state_65); - if (i !== ~65'd0 >> n_array_4_state_65) $stop; - n_array_4_state_65++; - endfunction - - int n_array_4_state_128 = 0; - function void e_array_4_state_128(input logic [127:0] i); - $display("e_array_4_state_128 %1d", n_array_4_state_128); - if (i !== ~128'd0 >> n_array_4_state_128) $stop; - n_array_4_state_128++; - endfunction - - // 4-state packed structures - int n_struct_4_state_1 = 0; - function void e_struct_4_state_1(input struct_4_state_1 i); - $display("e_struct_4_state_1 %1d", n_struct_4_state_1); - if (i !== n_struct_4_state_1[0]) $stop; - n_struct_4_state_1++; - endfunction - - int n_struct_4_state_32 = 0; - function void e_struct_4_state_32(input struct_4_state_32 i); - $display("e_struct_4_state_32 %1d", n_struct_4_state_32); - if (i !== ~32'd0 >> n_struct_4_state_32) $stop; - n_struct_4_state_32++; - endfunction - - int n_struct_4_state_33 = 0; - function void e_struct_4_state_33(input struct_4_state_33 i); - $display("e_struct_4_state_33 %1d", n_struct_4_state_33); - if (i !== ~33'd0 >> n_struct_4_state_33) $stop; - n_struct_4_state_33++; - endfunction - - int n_struct_4_state_64 = 0; - function void e_struct_4_state_64(input struct_4_state_64 i); - $display("e_struct_4_state_64 %1d", n_struct_4_state_64); - if (i !== ~64'd0 >> n_struct_4_state_64) $stop; - n_struct_4_state_64++; - endfunction - - int n_struct_4_state_65 = 0; - function void e_struct_4_state_65(input struct_4_state_65 i); - $display("e_struct_4_state_65 %1d", n_struct_4_state_65); - if (i !== ~65'd0 >> n_struct_4_state_65) $stop; - n_struct_4_state_65++; - endfunction - - int n_struct_4_state_128 = 0; - function void e_struct_4_state_128(input struct_4_state_128 i); - $display("e_struct_4_state_128 %1d", n_struct_4_state_128); - if (i !== ~128'd0 >> n_struct_4_state_128) $stop; - n_struct_4_state_128++; - endfunction - - // 4-state packed unions - int n_union_4_state_1 = 0; - function void e_union_4_state_1(input union_4_state_1 i); - $display("e_union_4_state_1 %1d", n_union_4_state_1); - if (i !== n_union_4_state_1[0]) $stop; - n_union_4_state_1++; - endfunction - - int n_union_4_state_32 = 0; - function void e_union_4_state_32(input union_4_state_32 i); - $display("e_union_4_state_32 %1d", n_union_4_state_32); - if (i !== ~32'd0 >> n_union_4_state_32) $stop; - n_union_4_state_32++; - endfunction - - int n_union_4_state_33 = 0; - function void e_union_4_state_33(input union_4_state_33 i); - $display("e_union_4_state_33 %1d", n_union_4_state_33); - if (i !== ~33'd0 >> n_union_4_state_33) $stop; - n_union_4_state_33++; - endfunction - - int n_union_4_state_64 = 0; - function void e_union_4_state_64(input union_4_state_64 i); - $display("e_union_4_state_64 %1d", n_union_4_state_64); - if (i !== ~64'd0 >> n_union_4_state_64) $stop; - n_union_4_state_64++; - endfunction - - int n_union_4_state_65 = 0; - function void e_union_4_state_65(input union_4_state_65 i); - $display("e_union_4_state_65 %1d", n_union_4_state_65); - if (i !== ~65'd0 >> n_union_4_state_65) $stop; - n_union_4_state_65++; - endfunction - - int n_union_4_state_128 = 0; - function void e_union_4_state_128(input union_4_state_128 i); - $display("e_union_4_state_128 %1d", n_union_4_state_128); - if (i !== ~128'd0 >> n_union_4_state_128) $stop; - n_union_4_state_128++; - endfunction - - //====================================================================== - // Invoke all functions 3 times (they have side effects) - //====================================================================== - - import "DPI-C" context function void check_exports(); - - initial begin - for (int i = 0 ; i < 3; i++) begin - // Check the imports - - // Basic types as per IEEE 1800-2023 35.5.6 - i_byte( 8'd10 - 8'(i)); - i_byte_unsigned( 8'd20 - 8'(i)); - i_shortint( 16'd30 - 16'(i)); - i_shortint_unsigned( 16'd40 - 16'(i)); - i_int( 32'd50 - 32'(i)); - i_int_unsigned( 32'd60 - 32'(i)); - i_longint( 64'd70 - 64'(i)); - i_longint_unsigned( 64'd80 - 64'(i)); -`ifndef NO_TIME - i_time( 64'd90 - 64'(i)); + i_time_t( 64'd90 - 64'(2*i)); `endif `ifndef NO_INTEGER - i_integer( 32'd100- 32'(i)); + i_integer_t( 32'd100- 32'(2*i)); `endif - i_real( -1.0*i - 0.50); + i_real_t( -1.0*(2*i) - 0.50); `ifndef NO_SHORTREAL - i_shortreal( -1.0*i - 0.25); + i_shortreal_t( -1.0*(2*i) - 0.25); `endif - if (~i[0]) begin - i_chandle(`NULL); - i_string("World"); - end else begin - i_chandle(`NULL); - i_string("Hello"); - end - i_bit(~i[0]); - i_logic(i[0]); - - // Basic types via typedefs - i_byte_t( 8'd10 - 8'(2*i)); - i_byte_unsigned_t( 8'd20 - 8'(2*i)); - i_shortint_t( 16'd30 - 16'(2*i)); - i_shortint_unsigned_t( 16'd40 - 16'(2*i)); - i_int_t( 32'd50 - 32'(2*i)); - i_int_unsigned_t( 32'd60 - 32'(2*i)); - i_longint_t( 64'd70 - 64'(2*i)); - i_longint_unsigned_t( 64'd80 - 64'(2*i)); -`ifndef NO_TIME - i_time_t( 64'd90 - 64'(2*i)); -`endif -`ifndef NO_INTEGER - i_integer_t( 32'd100- 32'(2*i)); -`endif - i_real_t( -1.0*(2*i) - 0.50); -`ifndef NO_SHORTREAL - i_shortreal_t( -1.0*(2*i) - 0.25); -`endif - if (~i[0]) begin - i_chandle_t(`NULL); - i_string_t("World"); - end else begin - i_chandle_t(`NULL); - i_string_t("Hello"); - end - i_bit_t(~i[0]); - i_logic_t(i[0]); - - // 2-state packed arrays - i_array_2_state_1(~i[0]); - i_array_2_state_32(~32'd0 << i); - i_array_2_state_33(~33'd0 << i); - i_array_2_state_64(~64'd0 << i); - i_array_2_state_65(~65'd0 << i); - i_array_2_state_128(~128'd0 << i); - - // 2-state packed structures - i_struct_2_state_1(~i[0]); - i_struct_2_state_32(~32'd0 << i); - i_struct_2_state_33(~33'd0 << i); - i_struct_2_state_64(~64'd0 << i); - i_struct_2_state_65(~65'd0 << i); - i_struct_2_state_128(~128'd0 << i); - - // 2-state packed unions - i_union_2_state_1(~i[0]); - i_union_2_state_32(~32'd0 << i); - i_union_2_state_33(~33'd0 << i); - i_union_2_state_64(~64'd0 << i); - i_union_2_state_65(~65'd0 << i); - i_union_2_state_128(~128'd0 << i); - - // 4-state packed arrays - i_array_4_state_1(~i[0]); - i_array_4_state_32(~32'd0 << i); - i_array_4_state_33(~33'd0 << i); - i_array_4_state_64(~64'd0 << i); - i_array_4_state_65(~65'd0 << i); - i_array_4_state_128(~128'd0 << i); - - // 4-state packed structures - i_struct_4_state_1(~i[0]); - i_struct_4_state_32(~32'd0 << i); - i_struct_4_state_33(~33'd0 << i); - i_struct_4_state_64(~64'd0 << i); - i_struct_4_state_65(~65'd0 << i); - i_struct_4_state_128(~128'd0 << i); - - // 4-state packed unions - i_union_4_state_1(~i[0]); - i_union_4_state_32(~32'd0 << i); - i_union_4_state_33(~33'd0 << i); - i_union_4_state_64(~64'd0 << i); - i_union_4_state_65(~65'd0 << i); - i_union_4_state_128(~128'd0 << i); - - // Check the exports - check_exports(); + if (~i[0]) begin + i_chandle_t(`NULL); + i_string_t("World"); + end else begin + i_chandle_t(`NULL); + i_string_t("Hello"); end + i_bit_t(~i[0]); + i_logic_t(i[0]); - $write("*-* All Finished *-*\n"); - $finish; - end + // 2-state packed arrays + i_array_2_state_1(~i[0]); + i_array_2_state_32(~32'd0 << i); + i_array_2_state_33(~33'd0 << i); + i_array_2_state_64(~64'd0 << i); + i_array_2_state_65(~65'd0 << i); + i_array_2_state_128(~128'd0 << i); + + // 2-state packed structures + i_struct_2_state_1(~i[0]); + i_struct_2_state_32(~32'd0 << i); + i_struct_2_state_33(~33'd0 << i); + i_struct_2_state_64(~64'd0 << i); + i_struct_2_state_65(~65'd0 << i); + i_struct_2_state_128(~128'd0 << i); + + // 2-state packed unions + i_union_2_state_1(~i[0]); + i_union_2_state_32(~32'd0 << i); + i_union_2_state_33(~33'd0 << i); + i_union_2_state_64(~64'd0 << i); + i_union_2_state_65(~65'd0 << i); + i_union_2_state_128(~128'd0 << i); + + // 4-state packed arrays + i_array_4_state_1(~i[0]); + i_array_4_state_32(~32'd0 << i); + i_array_4_state_33(~33'd0 << i); + i_array_4_state_64(~64'd0 << i); + i_array_4_state_65(~65'd0 << i); + i_array_4_state_128(~128'd0 << i); + + // 4-state packed structures + i_struct_4_state_1(~i[0]); + i_struct_4_state_32(~32'd0 << i); + i_struct_4_state_33(~33'd0 << i); + i_struct_4_state_64(~64'd0 << i); + i_struct_4_state_65(~65'd0 << i); + i_struct_4_state_128(~128'd0 << i); + + // 4-state packed unions + i_union_4_state_1(~i[0]); + i_union_4_state_32(~32'd0 << i); + i_union_4_state_33(~33'd0 << i); + i_union_4_state_64(~64'd0 << i); + i_union_4_state_65(~65'd0 << i); + i_union_4_state_128(~128'd0 << i); + + // Check the exports + check_exports(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_arg_input_unpack.v b/test_regress/t/t_dpi_arg_input_unpack.v index 854990f23..25e96b57e 100644 --- a/test_regress/t/t_dpi_arg_input_unpack.v +++ b/test_regress/t/t_dpi_arg_input_unpack.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -33,12 +34,12 @@ `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ - end else begin \ - $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ - int'(exp), int'(act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ + end else begin \ + $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ + int'(exp), int'(act), `__LINE__); \ + $stop; \ + end `define CHECK_0D(val) \ `CHECK_VAL((val), 42) @@ -72,1204 +73,1204 @@ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ module t; - localparam ENABLE_VERBOSE_MESSAGE = 0; + localparam ENABLE_VERBOSE_MESSAGE = 0; - // Legal input argument types for DPI functions + // Legal input argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - typedef byte byte_array_t[4][3][2]; - typedef byte byte_array1_t[1][1][1]; - typedef byte unsigned byte_unsigned_array_t[4][3][2]; - typedef byte unsigned byte_unsigned_array1_t[1][1][1]; - typedef shortint shortint_array_t[4][3][2]; - typedef shortint shortint_array1_t[1][1][1]; - typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; - typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; - typedef int int_array_t[4][3][2]; - typedef int int_array1_t[1][1][1]; - typedef int unsigned int_unsigned_array_t[4][3][2]; - typedef int unsigned int_unsigned_array1_t[1][1][1]; - typedef longint longint_array_t[4][3][2]; - typedef longint longint_array1_t[1][1][1]; - typedef longint unsigned longint_unsigned_array_t[4][3][2]; - typedef longint unsigned longint_unsigned_array1_t[1][1][1]; + typedef byte byte_array_t[4][3][2]; + typedef byte byte_array1_t[1][1][1]; + typedef byte unsigned byte_unsigned_array_t[4][3][2]; + typedef byte unsigned byte_unsigned_array1_t[1][1][1]; + typedef shortint shortint_array_t[4][3][2]; + typedef shortint shortint_array1_t[1][1][1]; + typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; + typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; + typedef int int_array_t[4][3][2]; + typedef int int_array1_t[1][1][1]; + typedef int unsigned int_unsigned_array_t[4][3][2]; + typedef int unsigned int_unsigned_array1_t[1][1][1]; + typedef longint longint_array_t[4][3][2]; + typedef longint longint_array1_t[1][1][1]; + typedef longint unsigned longint_unsigned_array_t[4][3][2]; + typedef longint unsigned longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME - typedef time time_array_t[4][3][2]; - typedef time time_array1_t[1][1][1]; + typedef time time_array_t[4][3][2]; + typedef time time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER - typedef integer integer_array_t[4][3][2]; - typedef integer integer_array1_t[1][1][1]; + typedef integer integer_array_t[4][3][2]; + typedef integer integer_array1_t[1][1][1]; `endif - typedef real real_array_t[4][3][2]; - typedef real real_array1_t[1][1][1]; + typedef real real_array_t[4][3][2]; + typedef real real_array1_t[1][1][1]; `ifndef NO_SHORTREAL - typedef shortreal shortreal_array_t[4][3][2]; - typedef shortreal shortreal_array1_t[1][1][1]; + typedef shortreal shortreal_array_t[4][3][2]; + typedef shortreal shortreal_array1_t[1][1][1]; `endif - typedef chandle chandle_array_t[4][3][2]; - typedef chandle chandle_array1_t[1][1][1]; - typedef string string_array_t[4][3][2]; - typedef string string_array1_t[1][1][1]; - typedef bit bit1_array_t[4][3][2]; - typedef bit bit1_array1_t[1][1][1]; - typedef bit [6:0] bit7_array_t[4][3][2]; - typedef bit [6:0] bit7_array1_t[1][1][1]; - typedef bit [120:0] bit121_array_t[4][3][2]; - typedef bit [120:0] bit121_array1_t[1][1][1]; - typedef logic logic1_array_t[4][3][2]; - typedef logic logic1_array1_t[1][1][1]; - typedef logic [6:0] logic7_array_t[4][3][2]; - typedef logic [6:0] logic7_array1_t[1][1][1]; - typedef logic [120:0] logic121_array_t[4][3][2]; - typedef logic [120:0] logic121_array1_t[1][1][1]; + typedef chandle chandle_array_t[4][3][2]; + typedef chandle chandle_array1_t[1][1][1]; + typedef string string_array_t[4][3][2]; + typedef string string_array1_t[1][1][1]; + typedef bit bit1_array_t[4][3][2]; + typedef bit bit1_array1_t[1][1][1]; + typedef bit [6:0] bit7_array_t[4][3][2]; + typedef bit [6:0] bit7_array1_t[1][1][1]; + typedef bit [120:0] bit121_array_t[4][3][2]; + typedef bit [120:0] bit121_array1_t[1][1][1]; + typedef logic logic1_array_t[4][3][2]; + typedef logic logic1_array1_t[1][1][1]; + typedef logic [6:0] logic7_array_t[4][3][2]; + typedef logic [6:0] logic7_array1_t[1][1][1]; + typedef logic [120:0] logic121_array_t[4][3][2]; + typedef logic [120:0] logic121_array1_t[1][1][1]; - typedef struct packed { - logic [6:0] val; - } pack_struct_t; - typedef pack_struct_t pack_struct_array_t[4][3][2]; - typedef pack_struct_t pack_struct_array1_t[1][1][1]; + typedef struct packed { + logic [6:0] val; + } pack_struct_t; + typedef pack_struct_t pack_struct_array_t[4][3][2]; + typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT - typedef struct { - logic [120:0] val; - } unpack_struct_t; - typedef unpack_struct_t unpack_struct_array_t[4][3][2]; - typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; + typedef struct { + logic [120:0] val; + } unpack_struct_t; + typedef unpack_struct_t unpack_struct_array_t[4][3][2]; + typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Returns non-null pointer - import "DPI-C" function chandle get_non_null(); + // Returns non-null pointer + import "DPI-C" function chandle get_non_null(); - import "DPI-C" function void i_byte_0d(input byte val); - import "DPI-C" function void i_byte_1d(input byte val[2]); - import "DPI-C" function void i_byte_2d(input byte val[3][2]); - import "DPI-C" function void i_byte_3d(input byte_array_t val); - import "DPI-C" function void i_byte_1d1(input byte val[1]); - import "DPI-C" function void i_byte_2d1(input byte val[1][1]); - import "DPI-C" function void i_byte_3d1(input byte_array1_t val); + import "DPI-C" function void i_byte_0d(input byte val); + import "DPI-C" function void i_byte_1d(input byte val[2]); + import "DPI-C" function void i_byte_2d(input byte val[3][2]); + import "DPI-C" function void i_byte_3d(input byte_array_t val); + import "DPI-C" function void i_byte_1d1(input byte val[1]); + import "DPI-C" function void i_byte_2d1(input byte val[1][1]); + import "DPI-C" function void i_byte_3d1(input byte_array1_t val); - import "DPI-C" function void i_byte_unsigned_0d(input byte unsigned val); - import "DPI-C" function void i_byte_unsigned_1d(input byte unsigned val[2]); - import "DPI-C" function void i_byte_unsigned_2d(input byte unsigned val[3][2]); - import "DPI-C" function void i_byte_unsigned_3d(input byte_unsigned_array_t val); - import "DPI-C" function void i_byte_unsigned_1d1(input byte unsigned val[1]); - import "DPI-C" function void i_byte_unsigned_2d1(input byte unsigned val[1][1]); - import "DPI-C" function void i_byte_unsigned_3d1(input byte_unsigned_array1_t val); + import "DPI-C" function void i_byte_unsigned_0d(input byte unsigned val); + import "DPI-C" function void i_byte_unsigned_1d(input byte unsigned val[2]); + import "DPI-C" function void i_byte_unsigned_2d(input byte unsigned val[3][2]); + import "DPI-C" function void i_byte_unsigned_3d(input byte_unsigned_array_t val); + import "DPI-C" function void i_byte_unsigned_1d1(input byte unsigned val[1]); + import "DPI-C" function void i_byte_unsigned_2d1(input byte unsigned val[1][1]); + import "DPI-C" function void i_byte_unsigned_3d1(input byte_unsigned_array1_t val); - import "DPI-C" function void i_shortint_0d(input shortint val); - import "DPI-C" function void i_shortint_1d(input shortint val[2]); - import "DPI-C" function void i_shortint_2d(input shortint val[3][2]); - import "DPI-C" function void i_shortint_3d(input shortint_array_t val); - import "DPI-C" function void i_shortint_1d1(input shortint val[1]); - import "DPI-C" function void i_shortint_2d1(input shortint val[1][1]); - import "DPI-C" function void i_shortint_3d1(input shortint_array1_t val); + import "DPI-C" function void i_shortint_0d(input shortint val); + import "DPI-C" function void i_shortint_1d(input shortint val[2]); + import "DPI-C" function void i_shortint_2d(input shortint val[3][2]); + import "DPI-C" function void i_shortint_3d(input shortint_array_t val); + import "DPI-C" function void i_shortint_1d1(input shortint val[1]); + import "DPI-C" function void i_shortint_2d1(input shortint val[1][1]); + import "DPI-C" function void i_shortint_3d1(input shortint_array1_t val); - import "DPI-C" function void i_shortint_unsigned_0d(input shortint unsigned val); - import "DPI-C" function void i_shortint_unsigned_1d(input shortint unsigned val[2]); - import "DPI-C" function void i_shortint_unsigned_2d(input shortint unsigned val[3][2]); - import "DPI-C" function void i_shortint_unsigned_3d(input shortint_unsigned_array_t val); - import "DPI-C" function void i_shortint_unsigned_1d1(input shortint unsigned val[1]); - import "DPI-C" function void i_shortint_unsigned_2d1(input shortint unsigned val[1][1]); - import "DPI-C" function void i_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); + import "DPI-C" function void i_shortint_unsigned_0d(input shortint unsigned val); + import "DPI-C" function void i_shortint_unsigned_1d(input shortint unsigned val[2]); + import "DPI-C" function void i_shortint_unsigned_2d(input shortint unsigned val[3][2]); + import "DPI-C" function void i_shortint_unsigned_3d(input shortint_unsigned_array_t val); + import "DPI-C" function void i_shortint_unsigned_1d1(input shortint unsigned val[1]); + import "DPI-C" function void i_shortint_unsigned_2d1(input shortint unsigned val[1][1]); + import "DPI-C" function void i_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); - import "DPI-C" function void i_int_0d(input int val); - import "DPI-C" function void i_int_1d(input int val[2]); - import "DPI-C" function void i_int_2d(input int val[3][2]); - import "DPI-C" function void i_int_3d(input int_array_t val); - import "DPI-C" function void i_int_1d1(input int val[1]); - import "DPI-C" function void i_int_2d1(input int val[1][1]); - import "DPI-C" function void i_int_3d1(input int_array1_t val); + import "DPI-C" function void i_int_0d(input int val); + import "DPI-C" function void i_int_1d(input int val[2]); + import "DPI-C" function void i_int_2d(input int val[3][2]); + import "DPI-C" function void i_int_3d(input int_array_t val); + import "DPI-C" function void i_int_1d1(input int val[1]); + import "DPI-C" function void i_int_2d1(input int val[1][1]); + import "DPI-C" function void i_int_3d1(input int_array1_t val); - import "DPI-C" function void i_int_unsigned_0d(input int unsigned val); - import "DPI-C" function void i_int_unsigned_1d(input int unsigned val[2]); - import "DPI-C" function void i_int_unsigned_2d(input int unsigned val[3][2]); - import "DPI-C" function void i_int_unsigned_3d(input int_unsigned_array_t val); - import "DPI-C" function void i_int_unsigned_1d1(input int unsigned val[1]); - import "DPI-C" function void i_int_unsigned_2d1(input int unsigned val[1][1]); - import "DPI-C" function void i_int_unsigned_3d1(input int_unsigned_array1_t val); + import "DPI-C" function void i_int_unsigned_0d(input int unsigned val); + import "DPI-C" function void i_int_unsigned_1d(input int unsigned val[2]); + import "DPI-C" function void i_int_unsigned_2d(input int unsigned val[3][2]); + import "DPI-C" function void i_int_unsigned_3d(input int_unsigned_array_t val); + import "DPI-C" function void i_int_unsigned_1d1(input int unsigned val[1]); + import "DPI-C" function void i_int_unsigned_2d1(input int unsigned val[1][1]); + import "DPI-C" function void i_int_unsigned_3d1(input int_unsigned_array1_t val); - import "DPI-C" function void i_longint_0d(input longint val); - import "DPI-C" function void i_longint_1d(input longint val[2]); - import "DPI-C" function void i_longint_2d(input longint val[3][2]); - import "DPI-C" function void i_longint_3d(input longint_array_t val); - import "DPI-C" function void i_longint_1d1(input longint val[1]); - import "DPI-C" function void i_longint_2d1(input longint val[1][1]); - import "DPI-C" function void i_longint_3d1(input longint_array1_t val); + import "DPI-C" function void i_longint_0d(input longint val); + import "DPI-C" function void i_longint_1d(input longint val[2]); + import "DPI-C" function void i_longint_2d(input longint val[3][2]); + import "DPI-C" function void i_longint_3d(input longint_array_t val); + import "DPI-C" function void i_longint_1d1(input longint val[1]); + import "DPI-C" function void i_longint_2d1(input longint val[1][1]); + import "DPI-C" function void i_longint_3d1(input longint_array1_t val); - import "DPI-C" function void i_longint_unsigned_0d(input longint unsigned val); - import "DPI-C" function void i_longint_unsigned_1d(input longint unsigned val[2]); - import "DPI-C" function void i_longint_unsigned_2d(input longint unsigned val[3][2]); - import "DPI-C" function void i_longint_unsigned_3d(input longint_unsigned_array_t val); - import "DPI-C" function void i_longint_unsigned_1d1(input longint unsigned val[1]); - import "DPI-C" function void i_longint_unsigned_2d1(input longint unsigned val[1][1]); - import "DPI-C" function void i_longint_unsigned_3d1(input longint_unsigned_array1_t val); + import "DPI-C" function void i_longint_unsigned_0d(input longint unsigned val); + import "DPI-C" function void i_longint_unsigned_1d(input longint unsigned val[2]); + import "DPI-C" function void i_longint_unsigned_2d(input longint unsigned val[3][2]); + import "DPI-C" function void i_longint_unsigned_3d(input longint_unsigned_array_t val); + import "DPI-C" function void i_longint_unsigned_1d1(input longint unsigned val[1]); + import "DPI-C" function void i_longint_unsigned_2d1(input longint unsigned val[1][1]); + import "DPI-C" function void i_longint_unsigned_3d1(input longint_unsigned_array1_t val); `ifndef NO_TIME - import "DPI-C" function void i_time_0d(input time val); - import "DPI-C" function void i_time_1d(input time val[2]); - import "DPI-C" function void i_time_2d(input time val[3][2]); - import "DPI-C" function void i_time_3d(input time_array_t val); - import "DPI-C" function void i_time_1d1(input time val[1]); - import "DPI-C" function void i_time_2d1(input time val[1][1]); - import "DPI-C" function void i_time_3d1(input time_array1_t val); + import "DPI-C" function void i_time_0d(input time val); + import "DPI-C" function void i_time_1d(input time val[2]); + import "DPI-C" function void i_time_2d(input time val[3][2]); + import "DPI-C" function void i_time_3d(input time_array_t val); + import "DPI-C" function void i_time_1d1(input time val[1]); + import "DPI-C" function void i_time_2d1(input time val[1][1]); + import "DPI-C" function void i_time_3d1(input time_array1_t val); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_0d(input integer val); - import "DPI-C" function void i_integer_1d(input integer val[2]); - import "DPI-C" function void i_integer_2d(input integer val[3][2]); - import "DPI-C" function void i_integer_3d(input integer_array_t val); - import "DPI-C" function void i_integer_1d1(input integer val[1]); - import "DPI-C" function void i_integer_2d1(input integer val[1][1]); - import "DPI-C" function void i_integer_3d1(input integer_array1_t val); + import "DPI-C" function void i_integer_0d(input integer val); + import "DPI-C" function void i_integer_1d(input integer val[2]); + import "DPI-C" function void i_integer_2d(input integer val[3][2]); + import "DPI-C" function void i_integer_3d(input integer_array_t val); + import "DPI-C" function void i_integer_1d1(input integer val[1]); + import "DPI-C" function void i_integer_2d1(input integer val[1][1]); + import "DPI-C" function void i_integer_3d1(input integer_array1_t val); `endif - import "DPI-C" function void i_real_0d(input real val); - import "DPI-C" function void i_real_1d(input real val[2]); - import "DPI-C" function void i_real_2d(input real val[3][2]); - import "DPI-C" function void i_real_3d(input real_array_t val); - import "DPI-C" function void i_real_1d1(input real val[1]); - import "DPI-C" function void i_real_2d1(input real val[1][1]); - import "DPI-C" function void i_real_3d1(input real_array1_t val); + import "DPI-C" function void i_real_0d(input real val); + import "DPI-C" function void i_real_1d(input real val[2]); + import "DPI-C" function void i_real_2d(input real val[3][2]); + import "DPI-C" function void i_real_3d(input real_array_t val); + import "DPI-C" function void i_real_1d1(input real val[1]); + import "DPI-C" function void i_real_2d1(input real val[1][1]); + import "DPI-C" function void i_real_3d1(input real_array1_t val); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_0d(input shortreal val); - import "DPI-C" function void i_shortreal_1d(input shortreal val[2]); - import "DPI-C" function void i_shortreal_2d(input shortreal val[3][2]); - import "DPI-C" function void i_shortreal_3d(input shortreal_array_t val); - import "DPI-C" function void i_shortreal_1d1(input shortreal val[1]); - import "DPI-C" function void i_shortreal_2d1(input shortreal val[1][1]); - import "DPI-C" function void i_shortreal_3d1(input shortreal_array1_t val); + import "DPI-C" function void i_shortreal_0d(input shortreal val); + import "DPI-C" function void i_shortreal_1d(input shortreal val[2]); + import "DPI-C" function void i_shortreal_2d(input shortreal val[3][2]); + import "DPI-C" function void i_shortreal_3d(input shortreal_array_t val); + import "DPI-C" function void i_shortreal_1d1(input shortreal val[1]); + import "DPI-C" function void i_shortreal_2d1(input shortreal val[1][1]); + import "DPI-C" function void i_shortreal_3d1(input shortreal_array1_t val); `endif - import "DPI-C" function void i_chandle_0d(input chandle val); - import "DPI-C" function void i_chandle_1d(input chandle val[2]); - import "DPI-C" function void i_chandle_2d(input chandle val[3][2]); - import "DPI-C" function void i_chandle_3d(input chandle_array_t val); - import "DPI-C" function void i_chandle_1d1(input chandle val[1]); - import "DPI-C" function void i_chandle_2d1(input chandle val[1][1]); - import "DPI-C" function void i_chandle_3d1(input chandle_array1_t val); + import "DPI-C" function void i_chandle_0d(input chandle val); + import "DPI-C" function void i_chandle_1d(input chandle val[2]); + import "DPI-C" function void i_chandle_2d(input chandle val[3][2]); + import "DPI-C" function void i_chandle_3d(input chandle_array_t val); + import "DPI-C" function void i_chandle_1d1(input chandle val[1]); + import "DPI-C" function void i_chandle_2d1(input chandle val[1][1]); + import "DPI-C" function void i_chandle_3d1(input chandle_array1_t val); - import "DPI-C" function void i_string_0d(input string val); - import "DPI-C" function void i_string_1d(input string val[2]); - import "DPI-C" function void i_string_2d(input string val[3][2]); - import "DPI-C" function void i_string_3d(input string_array_t val); - import "DPI-C" function void i_string_1d1(input string val[1]); - import "DPI-C" function void i_string_2d1(input string val[1][1]); - import "DPI-C" function void i_string_3d1(input string_array1_t val); + import "DPI-C" function void i_string_0d(input string val); + import "DPI-C" function void i_string_1d(input string val[2]); + import "DPI-C" function void i_string_2d(input string val[3][2]); + import "DPI-C" function void i_string_3d(input string_array_t val); + import "DPI-C" function void i_string_1d1(input string val[1]); + import "DPI-C" function void i_string_2d1(input string val[1][1]); + import "DPI-C" function void i_string_3d1(input string_array1_t val); - import "DPI-C" function void i_bit1_0d(input bit val); - import "DPI-C" function void i_bit1_1d(input bit val[2]); - import "DPI-C" function void i_bit1_2d(input bit val[3][2]); - import "DPI-C" function void i_bit1_3d(input bit1_array_t val); - import "DPI-C" function void i_bit1_1d1(input bit val[1]); - import "DPI-C" function void i_bit1_2d1(input bit val[1][1]); - import "DPI-C" function void i_bit1_3d1(input bit1_array1_t val); + import "DPI-C" function void i_bit1_0d(input bit val); + import "DPI-C" function void i_bit1_1d(input bit val[2]); + import "DPI-C" function void i_bit1_2d(input bit val[3][2]); + import "DPI-C" function void i_bit1_3d(input bit1_array_t val); + import "DPI-C" function void i_bit1_1d1(input bit val[1]); + import "DPI-C" function void i_bit1_2d1(input bit val[1][1]); + import "DPI-C" function void i_bit1_3d1(input bit1_array1_t val); - import "DPI-C" function void i_bit7_0d(input bit[6:0] val); - import "DPI-C" function void i_bit7_1d(input bit[6:0] val[2]); - import "DPI-C" function void i_bit7_2d(input bit[6:0] val[3][2]); - import "DPI-C" function void i_bit7_3d(input bit7_array_t val); - import "DPI-C" function void i_bit7_1d1(input bit[6:0] val[1]); - import "DPI-C" function void i_bit7_2d1(input bit[6:0] val[1][1]); - import "DPI-C" function void i_bit7_3d1(input bit7_array1_t val); + import "DPI-C" function void i_bit7_0d(input bit[6:0] val); + import "DPI-C" function void i_bit7_1d(input bit[6:0] val[2]); + import "DPI-C" function void i_bit7_2d(input bit[6:0] val[3][2]); + import "DPI-C" function void i_bit7_3d(input bit7_array_t val); + import "DPI-C" function void i_bit7_1d1(input bit[6:0] val[1]); + import "DPI-C" function void i_bit7_2d1(input bit[6:0] val[1][1]); + import "DPI-C" function void i_bit7_3d1(input bit7_array1_t val); - import "DPI-C" function void i_bit121_0d(input bit[120:0] val); - import "DPI-C" function void i_bit121_1d(input bit[120:0] val[2]); - import "DPI-C" function void i_bit121_2d(input bit[120:0] val[3][2]); - import "DPI-C" function void i_bit121_3d(input bit121_array_t val); - import "DPI-C" function void i_bit121_1d1(input bit[120:0] val[1]); - import "DPI-C" function void i_bit121_2d1(input bit[120:0] val[1][1]); - import "DPI-C" function void i_bit121_3d1(input bit121_array1_t val); + import "DPI-C" function void i_bit121_0d(input bit[120:0] val); + import "DPI-C" function void i_bit121_1d(input bit[120:0] val[2]); + import "DPI-C" function void i_bit121_2d(input bit[120:0] val[3][2]); + import "DPI-C" function void i_bit121_3d(input bit121_array_t val); + import "DPI-C" function void i_bit121_1d1(input bit[120:0] val[1]); + import "DPI-C" function void i_bit121_2d1(input bit[120:0] val[1][1]); + import "DPI-C" function void i_bit121_3d1(input bit121_array1_t val); - import "DPI-C" function void i_logic1_0d(input logic val); - import "DPI-C" function void i_logic1_1d(input logic val[2]); - import "DPI-C" function void i_logic1_2d(input logic val[3][2]); - import "DPI-C" function void i_logic1_3d(input logic1_array_t val); - import "DPI-C" function void i_logic1_1d1(input logic val[1]); - import "DPI-C" function void i_logic1_2d1(input logic val[1][1]); - import "DPI-C" function void i_logic1_3d1(input logic1_array1_t val); + import "DPI-C" function void i_logic1_0d(input logic val); + import "DPI-C" function void i_logic1_1d(input logic val[2]); + import "DPI-C" function void i_logic1_2d(input logic val[3][2]); + import "DPI-C" function void i_logic1_3d(input logic1_array_t val); + import "DPI-C" function void i_logic1_1d1(input logic val[1]); + import "DPI-C" function void i_logic1_2d1(input logic val[1][1]); + import "DPI-C" function void i_logic1_3d1(input logic1_array1_t val); - import "DPI-C" function void i_logic7_0d(input logic[6:0] val); - import "DPI-C" function void i_logic7_1d(input logic[6:0] val[2]); - import "DPI-C" function void i_logic7_2d(input logic[6:0] val[3][2]); - import "DPI-C" function void i_logic7_3d(input logic7_array_t val); - import "DPI-C" function void i_logic7_1d1(input logic[6:0] val[1]); - import "DPI-C" function void i_logic7_2d1(input logic[6:0] val[1][1]); - import "DPI-C" function void i_logic7_3d1(input logic7_array1_t val); + import "DPI-C" function void i_logic7_0d(input logic[6:0] val); + import "DPI-C" function void i_logic7_1d(input logic[6:0] val[2]); + import "DPI-C" function void i_logic7_2d(input logic[6:0] val[3][2]); + import "DPI-C" function void i_logic7_3d(input logic7_array_t val); + import "DPI-C" function void i_logic7_1d1(input logic[6:0] val[1]); + import "DPI-C" function void i_logic7_2d1(input logic[6:0] val[1][1]); + import "DPI-C" function void i_logic7_3d1(input logic7_array1_t val); - import "DPI-C" function void i_logic121_0d(input logic[120:0] val); - import "DPI-C" function void i_logic121_1d(input logic[120:0] val[2]); - import "DPI-C" function void i_logic121_2d(input logic[120:0] val[3][2]); - import "DPI-C" function void i_logic121_3d(input logic121_array_t val); - import "DPI-C" function void i_logic121_1d1(input logic[120:0] val[1]); - import "DPI-C" function void i_logic121_2d1(input logic[120:0] val[1][1]); - import "DPI-C" function void i_logic121_3d1(input logic121_array1_t val); + import "DPI-C" function void i_logic121_0d(input logic[120:0] val); + import "DPI-C" function void i_logic121_1d(input logic[120:0] val[2]); + import "DPI-C" function void i_logic121_2d(input logic[120:0] val[3][2]); + import "DPI-C" function void i_logic121_3d(input logic121_array_t val); + import "DPI-C" function void i_logic121_1d1(input logic[120:0] val[1]); + import "DPI-C" function void i_logic121_2d1(input logic[120:0] val[1][1]); + import "DPI-C" function void i_logic121_3d1(input logic121_array1_t val); - import "DPI-C" function void i_pack_struct_0d(input pack_struct_t val); - import "DPI-C" function void i_pack_struct_1d(input pack_struct_t val[2]); - import "DPI-C" function void i_pack_struct_2d(input pack_struct_t val[3][2]); - import "DPI-C" function void i_pack_struct_3d(input pack_struct_array_t val); - import "DPI-C" function void i_pack_struct_1d1(input pack_struct_t val[1]); - import "DPI-C" function void i_pack_struct_2d1(input pack_struct_t val[1][1]); - import "DPI-C" function void i_pack_struct_3d1(input pack_struct_array1_t val); + import "DPI-C" function void i_pack_struct_0d(input pack_struct_t val); + import "DPI-C" function void i_pack_struct_1d(input pack_struct_t val[2]); + import "DPI-C" function void i_pack_struct_2d(input pack_struct_t val[3][2]); + import "DPI-C" function void i_pack_struct_3d(input pack_struct_array_t val); + import "DPI-C" function void i_pack_struct_1d1(input pack_struct_t val[1]); + import "DPI-C" function void i_pack_struct_2d1(input pack_struct_t val[1][1]); + import "DPI-C" function void i_pack_struct_3d1(input pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT - import "DPI-C" function void i_unpack_struct_0d(input unpack_struct_t val); - import "DPI-C" function void i_unpack_struct_1d(input unpack_struct_t val[2]); - import "DPI-C" function void i_unpack_struct_2d(input unpack_struct_t val[3][2]); - import "DPI-C" function void i_unpack_struct_3d(input unpack_struct_array_t val); - import "DPI-C" function void i_unpack_struct_1d1(input unpack_struct_t val[1]); - import "DPI-C" function void i_unpack_struct_2d1(input unpack_struct_t val[1][1]); - import "DPI-C" function void i_unpack_struct_3d1(input unpack_struct_array1_t val); + import "DPI-C" function void i_unpack_struct_0d(input unpack_struct_t val); + import "DPI-C" function void i_unpack_struct_1d(input unpack_struct_t val[2]); + import "DPI-C" function void i_unpack_struct_2d(input unpack_struct_t val[3][2]); + import "DPI-C" function void i_unpack_struct_3d(input unpack_struct_array_t val); + import "DPI-C" function void i_unpack_struct_1d1(input unpack_struct_t val[1]); + import "DPI-C" function void i_unpack_struct_2d1(input unpack_struct_t val[1][1]); + import "DPI-C" function void i_unpack_struct_3d1(input unpack_struct_array1_t val); `endif - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - export "DPI-C" function e_byte_0d; - export "DPI-C" function e_byte_1d; - export "DPI-C" function e_byte_2d; - export "DPI-C" function e_byte_3d; - export "DPI-C" function e_byte_1d1; - export "DPI-C" function e_byte_2d1; - export "DPI-C" function e_byte_3d1; + export "DPI-C" function e_byte_0d; + export "DPI-C" function e_byte_1d; + export "DPI-C" function e_byte_2d; + export "DPI-C" function e_byte_3d; + export "DPI-C" function e_byte_1d1; + export "DPI-C" function e_byte_2d1; + export "DPI-C" function e_byte_3d1; - export "DPI-C" function e_byte_unsigned_0d; - export "DPI-C" function e_byte_unsigned_1d; - export "DPI-C" function e_byte_unsigned_2d; - export "DPI-C" function e_byte_unsigned_3d; - export "DPI-C" function e_byte_unsigned_1d1; - export "DPI-C" function e_byte_unsigned_2d1; - export "DPI-C" function e_byte_unsigned_3d1; + export "DPI-C" function e_byte_unsigned_0d; + export "DPI-C" function e_byte_unsigned_1d; + export "DPI-C" function e_byte_unsigned_2d; + export "DPI-C" function e_byte_unsigned_3d; + export "DPI-C" function e_byte_unsigned_1d1; + export "DPI-C" function e_byte_unsigned_2d1; + export "DPI-C" function e_byte_unsigned_3d1; - export "DPI-C" function e_shortint_0d; - export "DPI-C" function e_shortint_1d; - export "DPI-C" function e_shortint_2d; - export "DPI-C" function e_shortint_3d; - export "DPI-C" function e_shortint_1d1; - export "DPI-C" function e_shortint_2d1; - export "DPI-C" function e_shortint_3d1; + export "DPI-C" function e_shortint_0d; + export "DPI-C" function e_shortint_1d; + export "DPI-C" function e_shortint_2d; + export "DPI-C" function e_shortint_3d; + export "DPI-C" function e_shortint_1d1; + export "DPI-C" function e_shortint_2d1; + export "DPI-C" function e_shortint_3d1; - export "DPI-C" function e_shortint_unsigned_0d; - export "DPI-C" function e_shortint_unsigned_1d; - export "DPI-C" function e_shortint_unsigned_2d; - export "DPI-C" function e_shortint_unsigned_3d; - export "DPI-C" function e_shortint_unsigned_1d1; - export "DPI-C" function e_shortint_unsigned_2d1; - export "DPI-C" function e_shortint_unsigned_3d1; + export "DPI-C" function e_shortint_unsigned_0d; + export "DPI-C" function e_shortint_unsigned_1d; + export "DPI-C" function e_shortint_unsigned_2d; + export "DPI-C" function e_shortint_unsigned_3d; + export "DPI-C" function e_shortint_unsigned_1d1; + export "DPI-C" function e_shortint_unsigned_2d1; + export "DPI-C" function e_shortint_unsigned_3d1; - export "DPI-C" function e_int_0d; - export "DPI-C" function e_int_1d; - export "DPI-C" function e_int_2d; - export "DPI-C" function e_int_3d; - export "DPI-C" function e_int_1d1; - export "DPI-C" function e_int_2d1; - export "DPI-C" function e_int_3d1; + export "DPI-C" function e_int_0d; + export "DPI-C" function e_int_1d; + export "DPI-C" function e_int_2d; + export "DPI-C" function e_int_3d; + export "DPI-C" function e_int_1d1; + export "DPI-C" function e_int_2d1; + export "DPI-C" function e_int_3d1; - export "DPI-C" function e_int_unsigned_0d; - export "DPI-C" function e_int_unsigned_1d; - export "DPI-C" function e_int_unsigned_2d; - export "DPI-C" function e_int_unsigned_3d; - export "DPI-C" function e_int_unsigned_1d1; - export "DPI-C" function e_int_unsigned_2d1; - export "DPI-C" function e_int_unsigned_3d1; + export "DPI-C" function e_int_unsigned_0d; + export "DPI-C" function e_int_unsigned_1d; + export "DPI-C" function e_int_unsigned_2d; + export "DPI-C" function e_int_unsigned_3d; + export "DPI-C" function e_int_unsigned_1d1; + export "DPI-C" function e_int_unsigned_2d1; + export "DPI-C" function e_int_unsigned_3d1; - export "DPI-C" function e_longint_0d; - export "DPI-C" function e_longint_1d; - export "DPI-C" function e_longint_2d; - export "DPI-C" function e_longint_3d; - export "DPI-C" function e_longint_1d1; - export "DPI-C" function e_longint_2d1; - export "DPI-C" function e_longint_3d1; + export "DPI-C" function e_longint_0d; + export "DPI-C" function e_longint_1d; + export "DPI-C" function e_longint_2d; + export "DPI-C" function e_longint_3d; + export "DPI-C" function e_longint_1d1; + export "DPI-C" function e_longint_2d1; + export "DPI-C" function e_longint_3d1; - export "DPI-C" function e_longint_unsigned_0d; - export "DPI-C" function e_longint_unsigned_1d; - export "DPI-C" function e_longint_unsigned_2d; - export "DPI-C" function e_longint_unsigned_3d; - export "DPI-C" function e_longint_unsigned_1d1; - export "DPI-C" function e_longint_unsigned_2d1; - export "DPI-C" function e_longint_unsigned_3d1; + export "DPI-C" function e_longint_unsigned_0d; + export "DPI-C" function e_longint_unsigned_1d; + export "DPI-C" function e_longint_unsigned_2d; + export "DPI-C" function e_longint_unsigned_3d; + export "DPI-C" function e_longint_unsigned_1d1; + export "DPI-C" function e_longint_unsigned_2d1; + export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME - export "DPI-C" function e_time_0d; - export "DPI-C" function e_time_1d; - export "DPI-C" function e_time_2d; - export "DPI-C" function e_time_3d; - export "DPI-C" function e_time_1d1; - export "DPI-C" function e_time_2d1; - export "DPI-C" function e_time_3d1; + export "DPI-C" function e_time_0d; + export "DPI-C" function e_time_1d; + export "DPI-C" function e_time_2d; + export "DPI-C" function e_time_3d; + export "DPI-C" function e_time_1d1; + export "DPI-C" function e_time_2d1; + export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_0d; - export "DPI-C" function e_integer_1d; - export "DPI-C" function e_integer_2d; - export "DPI-C" function e_integer_3d; - export "DPI-C" function e_integer_1d1; - export "DPI-C" function e_integer_2d1; - export "DPI-C" function e_integer_3d1; + export "DPI-C" function e_integer_0d; + export "DPI-C" function e_integer_1d; + export "DPI-C" function e_integer_2d; + export "DPI-C" function e_integer_3d; + export "DPI-C" function e_integer_1d1; + export "DPI-C" function e_integer_2d1; + export "DPI-C" function e_integer_3d1; `endif - export "DPI-C" function e_real_0d; - export "DPI-C" function e_real_1d; - export "DPI-C" function e_real_2d; - export "DPI-C" function e_real_3d; - export "DPI-C" function e_real_1d1; - export "DPI-C" function e_real_2d1; - export "DPI-C" function e_real_3d1; + export "DPI-C" function e_real_0d; + export "DPI-C" function e_real_1d; + export "DPI-C" function e_real_2d; + export "DPI-C" function e_real_3d; + export "DPI-C" function e_real_1d1; + export "DPI-C" function e_real_2d1; + export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_0d; - export "DPI-C" function e_shortreal_1d; - export "DPI-C" function e_shortreal_2d; - export "DPI-C" function e_shortreal_3d; - export "DPI-C" function e_shortreal_1d1; - export "DPI-C" function e_shortreal_2d1; - export "DPI-C" function e_shortreal_3d1; + export "DPI-C" function e_shortreal_0d; + export "DPI-C" function e_shortreal_1d; + export "DPI-C" function e_shortreal_2d; + export "DPI-C" function e_shortreal_3d; + export "DPI-C" function e_shortreal_1d1; + export "DPI-C" function e_shortreal_2d1; + export "DPI-C" function e_shortreal_3d1; `endif - export "DPI-C" function e_chandle_0d; - export "DPI-C" function e_chandle_1d; - export "DPI-C" function e_chandle_2d; - export "DPI-C" function e_chandle_3d; - export "DPI-C" function e_chandle_1d1; - export "DPI-C" function e_chandle_2d1; - export "DPI-C" function e_chandle_3d1; + export "DPI-C" function e_chandle_0d; + export "DPI-C" function e_chandle_1d; + export "DPI-C" function e_chandle_2d; + export "DPI-C" function e_chandle_3d; + export "DPI-C" function e_chandle_1d1; + export "DPI-C" function e_chandle_2d1; + export "DPI-C" function e_chandle_3d1; - export "DPI-C" function e_string_0d; - export "DPI-C" function e_string_1d; - export "DPI-C" function e_string_2d; - export "DPI-C" function e_string_3d; - export "DPI-C" function e_string_1d1; - export "DPI-C" function e_string_2d1; - export "DPI-C" function e_string_3d1; + export "DPI-C" function e_string_0d; + export "DPI-C" function e_string_1d; + export "DPI-C" function e_string_2d; + export "DPI-C" function e_string_3d; + export "DPI-C" function e_string_1d1; + export "DPI-C" function e_string_2d1; + export "DPI-C" function e_string_3d1; - export "DPI-C" function e_bit1_0d; - export "DPI-C" function e_bit1_1d; - export "DPI-C" function e_bit1_2d; - export "DPI-C" function e_bit1_3d; - export "DPI-C" function e_bit1_1d1; - export "DPI-C" function e_bit1_2d1; - export "DPI-C" function e_bit1_3d1; + export "DPI-C" function e_bit1_0d; + export "DPI-C" function e_bit1_1d; + export "DPI-C" function e_bit1_2d; + export "DPI-C" function e_bit1_3d; + export "DPI-C" function e_bit1_1d1; + export "DPI-C" function e_bit1_2d1; + export "DPI-C" function e_bit1_3d1; - export "DPI-C" function e_bit7_0d; - export "DPI-C" function e_bit7_1d; - export "DPI-C" function e_bit7_2d; - export "DPI-C" function e_bit7_3d; - export "DPI-C" function e_bit7_1d1; - export "DPI-C" function e_bit7_2d1; - export "DPI-C" function e_bit7_3d1; + export "DPI-C" function e_bit7_0d; + export "DPI-C" function e_bit7_1d; + export "DPI-C" function e_bit7_2d; + export "DPI-C" function e_bit7_3d; + export "DPI-C" function e_bit7_1d1; + export "DPI-C" function e_bit7_2d1; + export "DPI-C" function e_bit7_3d1; - export "DPI-C" function e_bit121_0d; - export "DPI-C" function e_bit121_1d; - export "DPI-C" function e_bit121_2d; - export "DPI-C" function e_bit121_3d; - export "DPI-C" function e_bit121_1d1; - export "DPI-C" function e_bit121_2d1; - export "DPI-C" function e_bit121_3d1; + export "DPI-C" function e_bit121_0d; + export "DPI-C" function e_bit121_1d; + export "DPI-C" function e_bit121_2d; + export "DPI-C" function e_bit121_3d; + export "DPI-C" function e_bit121_1d1; + export "DPI-C" function e_bit121_2d1; + export "DPI-C" function e_bit121_3d1; - export "DPI-C" function e_logic1_0d; - export "DPI-C" function e_logic1_1d; - export "DPI-C" function e_logic1_2d; - export "DPI-C" function e_logic1_3d; - export "DPI-C" function e_logic1_1d1; - export "DPI-C" function e_logic1_2d1; - export "DPI-C" function e_logic1_3d1; + export "DPI-C" function e_logic1_0d; + export "DPI-C" function e_logic1_1d; + export "DPI-C" function e_logic1_2d; + export "DPI-C" function e_logic1_3d; + export "DPI-C" function e_logic1_1d1; + export "DPI-C" function e_logic1_2d1; + export "DPI-C" function e_logic1_3d1; - export "DPI-C" function e_logic7_0d; - export "DPI-C" function e_logic7_1d; - export "DPI-C" function e_logic7_2d; - export "DPI-C" function e_logic7_3d; - export "DPI-C" function e_logic7_1d1; - export "DPI-C" function e_logic7_2d1; - export "DPI-C" function e_logic7_3d1; + export "DPI-C" function e_logic7_0d; + export "DPI-C" function e_logic7_1d; + export "DPI-C" function e_logic7_2d; + export "DPI-C" function e_logic7_3d; + export "DPI-C" function e_logic7_1d1; + export "DPI-C" function e_logic7_2d1; + export "DPI-C" function e_logic7_3d1; - export "DPI-C" function e_logic121_0d; - export "DPI-C" function e_logic121_1d; - export "DPI-C" function e_logic121_2d; - export "DPI-C" function e_logic121_3d; - export "DPI-C" function e_logic121_1d1; - export "DPI-C" function e_logic121_2d1; - export "DPI-C" function e_logic121_3d1; + export "DPI-C" function e_logic121_0d; + export "DPI-C" function e_logic121_1d; + export "DPI-C" function e_logic121_2d; + export "DPI-C" function e_logic121_3d; + export "DPI-C" function e_logic121_1d1; + export "DPI-C" function e_logic121_2d1; + export "DPI-C" function e_logic121_3d1; - export "DPI-C" function e_pack_struct_0d; - export "DPI-C" function e_pack_struct_1d; - export "DPI-C" function e_pack_struct_2d; - export "DPI-C" function e_pack_struct_3d; - export "DPI-C" function e_pack_struct_1d1; - export "DPI-C" function e_pack_struct_2d1; - export "DPI-C" function e_pack_struct_3d1; + export "DPI-C" function e_pack_struct_0d; + export "DPI-C" function e_pack_struct_1d; + export "DPI-C" function e_pack_struct_2d; + export "DPI-C" function e_pack_struct_3d; + export "DPI-C" function e_pack_struct_1d1; + export "DPI-C" function e_pack_struct_2d1; + export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT - export "DPI-C" function e_unpack_struct_0d; - export "DPI-C" function e_unpack_struct_1d; - export "DPI-C" function e_unpack_struct_2d; - export "DPI-C" function e_unpack_struct_3d; - export "DPI-C" function e_unpack_struct_1d1; - export "DPI-C" function e_unpack_struct_2d1; - export "DPI-C" function e_unpack_struct_3d1; + export "DPI-C" function e_unpack_struct_0d; + export "DPI-C" function e_unpack_struct_1d; + export "DPI-C" function e_unpack_struct_2d; + export "DPI-C" function e_unpack_struct_3d; + export "DPI-C" function e_unpack_struct_1d1; + export "DPI-C" function e_unpack_struct_2d1; + export "DPI-C" function e_unpack_struct_3d1; `endif - //====================================================================== - // Definitions of exported functions - //====================================================================== - function void e_byte_0d(input byte val); `CHECK_0D(val); endfunction - function void e_byte_1d(input byte val[2]); `CHECK_1D(val); endfunction - function void e_byte_2d(input byte val[3][2]); `CHECK_2D(val); endfunction - function void e_byte_3d(input byte_array_t val); `CHECK_3D(val); endfunction - function void e_byte_1d1(input byte val[1]); `CHECK_1D1(val); endfunction - function void e_byte_2d1(input byte val[1][1]); `CHECK_2D1(val); endfunction - function void e_byte_3d1(input byte_array1_t val); `CHECK_3D1(val); endfunction + //====================================================================== + // Definitions of exported functions + //====================================================================== + function void e_byte_0d(input byte val); `CHECK_0D(val); endfunction + function void e_byte_1d(input byte val[2]); `CHECK_1D(val); endfunction + function void e_byte_2d(input byte val[3][2]); `CHECK_2D(val); endfunction + function void e_byte_3d(input byte_array_t val); `CHECK_3D(val); endfunction + function void e_byte_1d1(input byte val[1]); `CHECK_1D1(val); endfunction + function void e_byte_2d1(input byte val[1][1]); `CHECK_2D1(val); endfunction + function void e_byte_3d1(input byte_array1_t val); `CHECK_3D1(val); endfunction - function void e_byte_unsigned_0d(input byte unsigned val); `CHECK_0D(val); endfunction - function void e_byte_unsigned_1d(input byte unsigned val[2]); `CHECK_1D(val); endfunction - function void e_byte_unsigned_2d(input byte unsigned val[3][2]); `CHECK_2D(val); endfunction - function void e_byte_unsigned_3d(input byte_unsigned_array_t val); `CHECK_3D(val); endfunction - function void e_byte_unsigned_1d1(input byte unsigned val[1]); `CHECK_1D1(val); endfunction - function void e_byte_unsigned_2d1(input byte unsigned val[1][1]); `CHECK_2D1(val); endfunction - function void e_byte_unsigned_3d1(input byte_unsigned_array1_t val); `CHECK_3D1(val); endfunction + function void e_byte_unsigned_0d(input byte unsigned val); `CHECK_0D(val); endfunction + function void e_byte_unsigned_1d(input byte unsigned val[2]); `CHECK_1D(val); endfunction + function void e_byte_unsigned_2d(input byte unsigned val[3][2]); `CHECK_2D(val); endfunction + function void e_byte_unsigned_3d(input byte_unsigned_array_t val); `CHECK_3D(val); endfunction + function void e_byte_unsigned_1d1(input byte unsigned val[1]); `CHECK_1D1(val); endfunction + function void e_byte_unsigned_2d1(input byte unsigned val[1][1]); `CHECK_2D1(val); endfunction + function void e_byte_unsigned_3d1(input byte_unsigned_array1_t val); `CHECK_3D1(val); endfunction - function void e_shortint_0d(input shortint val); `CHECK_0D(val); endfunction - function void e_shortint_1d(input shortint val[2]); `CHECK_1D(val); endfunction - function void e_shortint_2d(input shortint val[3][2]); `CHECK_2D(val); endfunction - function void e_shortint_3d(input shortint_array_t val); `CHECK_3D(val); endfunction - function void e_shortint_1d1(input shortint val[1]); `CHECK_1D1(val); endfunction - function void e_shortint_2d1(input shortint val[1][1]); `CHECK_2D1(val); endfunction - function void e_shortint_3d1(input shortint_array1_t val); `CHECK_3D1(val); endfunction + function void e_shortint_0d(input shortint val); `CHECK_0D(val); endfunction + function void e_shortint_1d(input shortint val[2]); `CHECK_1D(val); endfunction + function void e_shortint_2d(input shortint val[3][2]); `CHECK_2D(val); endfunction + function void e_shortint_3d(input shortint_array_t val); `CHECK_3D(val); endfunction + function void e_shortint_1d1(input shortint val[1]); `CHECK_1D1(val); endfunction + function void e_shortint_2d1(input shortint val[1][1]); `CHECK_2D1(val); endfunction + function void e_shortint_3d1(input shortint_array1_t val); `CHECK_3D1(val); endfunction - function void e_shortint_unsigned_0d(input shortint unsigned val); `CHECK_0D(val); endfunction - function void e_shortint_unsigned_1d(input shortint unsigned val[2]); `CHECK_1D(val); endfunction - function void e_shortint_unsigned_2d(input shortint unsigned val[3][2]); `CHECK_2D(val); endfunction - function void e_shortint_unsigned_3d(input shortint_unsigned_array_t val); `CHECK_3D(val); endfunction - function void e_shortint_unsigned_1d1(input shortint unsigned val[1]); `CHECK_1D1(val); endfunction - function void e_shortint_unsigned_2d1(input shortint unsigned val[1][1]); `CHECK_2D1(val); endfunction - function void e_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); `CHECK_3D1(val); endfunction + function void e_shortint_unsigned_0d(input shortint unsigned val); `CHECK_0D(val); endfunction + function void e_shortint_unsigned_1d(input shortint unsigned val[2]); `CHECK_1D(val); endfunction + function void e_shortint_unsigned_2d(input shortint unsigned val[3][2]); `CHECK_2D(val); endfunction + function void e_shortint_unsigned_3d(input shortint_unsigned_array_t val); `CHECK_3D(val); endfunction + function void e_shortint_unsigned_1d1(input shortint unsigned val[1]); `CHECK_1D1(val); endfunction + function void e_shortint_unsigned_2d1(input shortint unsigned val[1][1]); `CHECK_2D1(val); endfunction + function void e_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); `CHECK_3D1(val); endfunction - function void e_int_0d(input int val); `CHECK_0D(val); endfunction - function void e_int_1d(input int val[2]); `CHECK_1D(val); endfunction - function void e_int_2d(input int val[3][2]); `CHECK_2D(val); endfunction - function void e_int_3d(input int_array_t val); `CHECK_3D(val); endfunction - function void e_int_1d1(input int val[1]); `CHECK_1D1(val); endfunction - function void e_int_2d1(input int val[1][1]); `CHECK_2D1(val); endfunction - function void e_int_3d1(input int_array1_t val); `CHECK_3D1(val); endfunction + function void e_int_0d(input int val); `CHECK_0D(val); endfunction + function void e_int_1d(input int val[2]); `CHECK_1D(val); endfunction + function void e_int_2d(input int val[3][2]); `CHECK_2D(val); endfunction + function void e_int_3d(input int_array_t val); `CHECK_3D(val); endfunction + function void e_int_1d1(input int val[1]); `CHECK_1D1(val); endfunction + function void e_int_2d1(input int val[1][1]); `CHECK_2D1(val); endfunction + function void e_int_3d1(input int_array1_t val); `CHECK_3D1(val); endfunction - function void e_int_unsigned_0d(input int unsigned val); `CHECK_0D(val); endfunction - function void e_int_unsigned_1d(input int unsigned val[2]); `CHECK_1D(val); endfunction - function void e_int_unsigned_2d(input int unsigned val[3][2]); `CHECK_2D(val); endfunction - function void e_int_unsigned_3d(input int_unsigned_array_t val); `CHECK_3D(val); endfunction - function void e_int_unsigned_1d1(input int unsigned val[1]); `CHECK_1D1(val); endfunction - function void e_int_unsigned_2d1(input int unsigned val[1][1]); `CHECK_2D1(val); endfunction - function void e_int_unsigned_3d1(input int_unsigned_array1_t val); `CHECK_3D1(val); endfunction + function void e_int_unsigned_0d(input int unsigned val); `CHECK_0D(val); endfunction + function void e_int_unsigned_1d(input int unsigned val[2]); `CHECK_1D(val); endfunction + function void e_int_unsigned_2d(input int unsigned val[3][2]); `CHECK_2D(val); endfunction + function void e_int_unsigned_3d(input int_unsigned_array_t val); `CHECK_3D(val); endfunction + function void e_int_unsigned_1d1(input int unsigned val[1]); `CHECK_1D1(val); endfunction + function void e_int_unsigned_2d1(input int unsigned val[1][1]); `CHECK_2D1(val); endfunction + function void e_int_unsigned_3d1(input int_unsigned_array1_t val); `CHECK_3D1(val); endfunction - function void e_longint_0d(input longint val); `CHECK_0D(val); endfunction - function void e_longint_1d(input longint val[2]); `CHECK_1D(val); endfunction - function void e_longint_2d(input longint val[3][2]); `CHECK_2D(val); endfunction - function void e_longint_3d(input longint_array_t val); `CHECK_3D(val); endfunction - function void e_longint_1d1(input longint val[1]); `CHECK_1D1(val); endfunction - function void e_longint_2d1(input longint val[1][1]); `CHECK_2D1(val); endfunction - function void e_longint_3d1(input longint_array1_t val); `CHECK_3D1(val); endfunction + function void e_longint_0d(input longint val); `CHECK_0D(val); endfunction + function void e_longint_1d(input longint val[2]); `CHECK_1D(val); endfunction + function void e_longint_2d(input longint val[3][2]); `CHECK_2D(val); endfunction + function void e_longint_3d(input longint_array_t val); `CHECK_3D(val); endfunction + function void e_longint_1d1(input longint val[1]); `CHECK_1D1(val); endfunction + function void e_longint_2d1(input longint val[1][1]); `CHECK_2D1(val); endfunction + function void e_longint_3d1(input longint_array1_t val); `CHECK_3D1(val); endfunction - function void e_longint_unsigned_0d(input longint unsigned val); `CHECK_0D(val); endfunction - function void e_longint_unsigned_1d(input longint unsigned val[2]); `CHECK_1D(val); endfunction - function void e_longint_unsigned_2d(input longint unsigned val[3][2]); `CHECK_2D(val); endfunction - function void e_longint_unsigned_3d(input longint_unsigned_array_t val); `CHECK_3D(val); endfunction - function void e_longint_unsigned_1d1(input longint unsigned val[1]); `CHECK_1D1(val); endfunction - function void e_longint_unsigned_2d1(input longint unsigned val[1][1]); `CHECK_2D1(val); endfunction - function void e_longint_unsigned_3d1(input longint_unsigned_array1_t val); `CHECK_3D1(val); endfunction + function void e_longint_unsigned_0d(input longint unsigned val); `CHECK_0D(val); endfunction + function void e_longint_unsigned_1d(input longint unsigned val[2]); `CHECK_1D(val); endfunction + function void e_longint_unsigned_2d(input longint unsigned val[3][2]); `CHECK_2D(val); endfunction + function void e_longint_unsigned_3d(input longint_unsigned_array_t val); `CHECK_3D(val); endfunction + function void e_longint_unsigned_1d1(input longint unsigned val[1]); `CHECK_1D1(val); endfunction + function void e_longint_unsigned_2d1(input longint unsigned val[1][1]); `CHECK_2D1(val); endfunction + function void e_longint_unsigned_3d1(input longint_unsigned_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_TIME - function void e_time_0d(input time val); `CHECK_0D(val); endfunction - function void e_time_1d(input time val[2]); `CHECK_1D(val); endfunction - function void e_time_2d(input time val[3][2]); `CHECK_2D(val); endfunction - function void e_time_3d(input time_array_t val); `CHECK_3D(val); endfunction - function void e_time_1d1(input time val[1]); `CHECK_1D1(val); endfunction - function void e_time_2d1(input time val[1][1]); `CHECK_2D1(val); endfunction - function void e_time_3d1(input time_array1_t val); `CHECK_3D1(val); endfunction + function void e_time_0d(input time val); `CHECK_0D(val); endfunction + function void e_time_1d(input time val[2]); `CHECK_1D(val); endfunction + function void e_time_2d(input time val[3][2]); `CHECK_2D(val); endfunction + function void e_time_3d(input time_array_t val); `CHECK_3D(val); endfunction + function void e_time_1d1(input time val[1]); `CHECK_1D1(val); endfunction + function void e_time_2d1(input time val[1][1]); `CHECK_2D1(val); endfunction + function void e_time_3d1(input time_array1_t val); `CHECK_3D1(val); endfunction `endif `ifndef NO_INTEGER - function void e_integer_0d(input integer val); `CHECK_0D(val); endfunction - function void e_integer_1d(input integer val[2]); `CHECK_1D(val); endfunction - function void e_integer_2d(input integer val[3][2]); `CHECK_2D(val); endfunction - function void e_integer_3d(input integer_array_t val); `CHECK_3D(val); endfunction - function void e_integer_1d1(input integer val[1]); `CHECK_1D1(val); endfunction - function void e_integer_2d1(input integer val[1][1]); `CHECK_2D1(val); endfunction - function void e_integer_3d1(input integer_array1_t val); `CHECK_3D1(val); endfunction + function void e_integer_0d(input integer val); `CHECK_0D(val); endfunction + function void e_integer_1d(input integer val[2]); `CHECK_1D(val); endfunction + function void e_integer_2d(input integer val[3][2]); `CHECK_2D(val); endfunction + function void e_integer_3d(input integer_array_t val); `CHECK_3D(val); endfunction + function void e_integer_1d1(input integer val[1]); `CHECK_1D1(val); endfunction + function void e_integer_2d1(input integer val[1][1]); `CHECK_2D1(val); endfunction + function void e_integer_3d1(input integer_array1_t val); `CHECK_3D1(val); endfunction `endif - function void e_real_0d(input real val); `CHECK_0D(val); endfunction - function void e_real_1d(input real val[2]); `CHECK_1D(val); endfunction - function void e_real_2d(input real val[3][2]); `CHECK_2D(val); endfunction - function void e_real_3d(input real_array_t val); `CHECK_3D(val); endfunction - function void e_real_1d1(input real val[1]); `CHECK_1D1(val); endfunction - function void e_real_2d1(input real val[1][1]); `CHECK_2D1(val); endfunction - function void e_real_3d1(input real_array1_t val); `CHECK_3D1(val); endfunction + function void e_real_0d(input real val); `CHECK_0D(val); endfunction + function void e_real_1d(input real val[2]); `CHECK_1D(val); endfunction + function void e_real_2d(input real val[3][2]); `CHECK_2D(val); endfunction + function void e_real_3d(input real_array_t val); `CHECK_3D(val); endfunction + function void e_real_1d1(input real val[1]); `CHECK_1D1(val); endfunction + function void e_real_2d1(input real val[1][1]); `CHECK_2D1(val); endfunction + function void e_real_3d1(input real_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_SHORTREAL - function void e_shortreal_0d(input shortreal val); `CHECK_0D(val); endfunction - function void e_shortreal_1d(input shortreal val[2]); `CHECK_1D(val); endfunction - function void e_shortreal_2d(input shortreal val[3][2]); `CHECK_2D(val); endfunction - function void e_shortreal_3d(input shortreal_array_t val); `CHECK_3D(val); endfunction - function void e_shortreal_1d1(input shortreal val[1]); `CHECK_1D1(val); endfunction - function void e_shortreal_2d1(input shortreal val[1][1]); `CHECK_2D1(val); endfunction - function void e_shortreal_3d1(input shortreal_array1_t val); `CHECK_3D1(val); endfunction + function void e_shortreal_0d(input shortreal val); `CHECK_0D(val); endfunction + function void e_shortreal_1d(input shortreal val[2]); `CHECK_1D(val); endfunction + function void e_shortreal_2d(input shortreal val[3][2]); `CHECK_2D(val); endfunction + function void e_shortreal_3d(input shortreal_array_t val); `CHECK_3D(val); endfunction + function void e_shortreal_1d1(input shortreal val[1]); `CHECK_1D1(val); endfunction + function void e_shortreal_2d1(input shortreal val[1][1]); `CHECK_2D1(val); endfunction + function void e_shortreal_3d1(input shortreal_array1_t val); `CHECK_3D1(val); endfunction `endif - function void e_chandle_0d(input chandle val); - if (val == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_1d(input chandle val[2]); - if (val[0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[1] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_2d(input chandle val[3][2]); - if (val[0][1] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[1][1] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[2][1] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_3d(input chandle_array_t val); - if (val[0][0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[1][0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[2][0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - if (val[3][0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_1d1(input chandle val[1]); - if (val[0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_2d1(input chandle val[1][1]); - if (val[0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction - function void e_chandle_3d1(input chandle_array1_t val); - if (val[0][0][0] == null) begin - $display("Mismatch non null is expected, but not."); - $stop; - end - endfunction + function void e_chandle_0d(input chandle val); + if (val == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_1d(input chandle val[2]); + if (val[0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[1] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_2d(input chandle val[3][2]); + if (val[0][1] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[1][1] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[2][1] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_3d(input chandle_array_t val); + if (val[0][0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[1][0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[2][0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + if (val[3][0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_1d1(input chandle val[1]); + if (val[0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_2d1(input chandle val[1][1]); + if (val[0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction + function void e_chandle_3d1(input chandle_array1_t val); + if (val[0][0][0] == null) begin + $display("Mismatch non null is expected, but not."); + $stop; + end + endfunction - function void e_string_0d(input string val); - if (val != "42") begin - $display("Mismatch expected:%s actual:%s", "42", val); - $stop; - end - endfunction - function void e_string_1d(input string val[2]); - if (val[0] != "43") begin - $display("Mismatch expected:%s actual:%s", "43", val[0]); - $stop; - end - if (val[1] != "44") begin - $display("Mismatch expected:%s actual:%s", "44", val[1]); - $stop; - end - endfunction - function void e_string_2d(input string val[3][2]); - if (val[0][1] != "45") begin - $display("Mismatch expected:%s actual:%s", "45", val[0][1]); - $stop; - end - if (val[1][1] != "46") begin - $display("Mismatch expected:%s actual:%s", "46", val[1][1]); - $stop; - end - if (val[2][1] != "47") begin - $display("Mismatch expected:%s actual:%s", "47", val[2][1]); - $stop; - end - endfunction - function void e_string_3d(input string_array_t val); - if (val[0][0][0] != "48") begin - $display("Mismatch expected:%s actual:%s", "48", val[0][0][0]); - $stop; - end - if (val[1][0][0] != "49") begin - $display("Mismatch expected:%s actual:%s", "49", val[1][0][0]); - $stop; - end - if (val[2][0][0] != "50") begin - $display("Mismatch expected:%s actual:%s", "50", val[2][0][0]); - $stop; - end - if (val[3][0][0] != "51") begin - $display("Mismatch expected:%s actual:%s", "51", val[3][0][0]); - $stop; - end - endfunction - function void e_string_1d1(input string val[1]); - if (val[0] != "52") begin - $display("Mismatch expected:%s actual:%s", "52", val[0]); - $stop; - end - endfunction - function void e_string_2d1(input string val[1][1]); - if (val[0][0] != "53") begin - $display("Mismatch expected:%s actual:%s", "53", val[0][0]); - $stop; - end - endfunction - function void e_string_3d1(input string_array1_t val); - if (val[0][0][0] != "54") begin - $display("Mismatch expected:%s actual:%s", "54", val[0][0][0]); - $stop; - end - endfunction + function void e_string_0d(input string val); + if (val != "42") begin + $display("Mismatch expected:%s actual:%s", "42", val); + $stop; + end + endfunction + function void e_string_1d(input string val[2]); + if (val[0] != "43") begin + $display("Mismatch expected:%s actual:%s", "43", val[0]); + $stop; + end + if (val[1] != "44") begin + $display("Mismatch expected:%s actual:%s", "44", val[1]); + $stop; + end + endfunction + function void e_string_2d(input string val[3][2]); + if (val[0][1] != "45") begin + $display("Mismatch expected:%s actual:%s", "45", val[0][1]); + $stop; + end + if (val[1][1] != "46") begin + $display("Mismatch expected:%s actual:%s", "46", val[1][1]); + $stop; + end + if (val[2][1] != "47") begin + $display("Mismatch expected:%s actual:%s", "47", val[2][1]); + $stop; + end + endfunction + function void e_string_3d(input string_array_t val); + if (val[0][0][0] != "48") begin + $display("Mismatch expected:%s actual:%s", "48", val[0][0][0]); + $stop; + end + if (val[1][0][0] != "49") begin + $display("Mismatch expected:%s actual:%s", "49", val[1][0][0]); + $stop; + end + if (val[2][0][0] != "50") begin + $display("Mismatch expected:%s actual:%s", "50", val[2][0][0]); + $stop; + end + if (val[3][0][0] != "51") begin + $display("Mismatch expected:%s actual:%s", "51", val[3][0][0]); + $stop; + end + endfunction + function void e_string_1d1(input string val[1]); + if (val[0] != "52") begin + $display("Mismatch expected:%s actual:%s", "52", val[0]); + $stop; + end + endfunction + function void e_string_2d1(input string val[1][1]); + if (val[0][0] != "53") begin + $display("Mismatch expected:%s actual:%s", "53", val[0][0]); + $stop; + end + endfunction + function void e_string_3d1(input string_array1_t val); + if (val[0][0][0] != "54") begin + $display("Mismatch expected:%s actual:%s", "54", val[0][0][0]); + $stop; + end + endfunction - function void e_bit1_0d(input bit val); `CHECK_0D(val); endfunction - function void e_bit1_1d(input bit val[2]); `CHECK_1D(val); endfunction - function void e_bit1_2d(input bit val[3][2]); `CHECK_2D(val); endfunction - function void e_bit1_3d(input bit1_array_t val); `CHECK_3D(val); endfunction - function void e_bit1_1d1(input bit val[1]); `CHECK_1D1(val); endfunction - function void e_bit1_2d1(input bit val[1][1]); `CHECK_2D1(val); endfunction - function void e_bit1_3d1(input bit1_array1_t val); `CHECK_3D1(val); endfunction + function void e_bit1_0d(input bit val); `CHECK_0D(val); endfunction + function void e_bit1_1d(input bit val[2]); `CHECK_1D(val); endfunction + function void e_bit1_2d(input bit val[3][2]); `CHECK_2D(val); endfunction + function void e_bit1_3d(input bit1_array_t val); `CHECK_3D(val); endfunction + function void e_bit1_1d1(input bit val[1]); `CHECK_1D1(val); endfunction + function void e_bit1_2d1(input bit val[1][1]); `CHECK_2D1(val); endfunction + function void e_bit1_3d1(input bit1_array1_t val); `CHECK_3D1(val); endfunction - function void e_bit7_0d(input bit[6:0] val); `CHECK_0D(val); endfunction - function void e_bit7_1d(input bit[6:0] val[2]); `CHECK_1D(val); endfunction - function void e_bit7_2d(input bit[6:0] val[3][2]); `CHECK_2D(val); endfunction - function void e_bit7_3d(input bit7_array_t val); `CHECK_3D(val); endfunction - function void e_bit7_1d1(input bit[6:0] val[1]); `CHECK_1D1(val); endfunction - function void e_bit7_2d1(input bit[6:0] val[1][1]); `CHECK_2D1(val); endfunction - function void e_bit7_3d1(input bit7_array1_t val); `CHECK_3D1(val); endfunction + function void e_bit7_0d(input bit[6:0] val); `CHECK_0D(val); endfunction + function void e_bit7_1d(input bit[6:0] val[2]); `CHECK_1D(val); endfunction + function void e_bit7_2d(input bit[6:0] val[3][2]); `CHECK_2D(val); endfunction + function void e_bit7_3d(input bit7_array_t val); `CHECK_3D(val); endfunction + function void e_bit7_1d1(input bit[6:0] val[1]); `CHECK_1D1(val); endfunction + function void e_bit7_2d1(input bit[6:0] val[1][1]); `CHECK_2D1(val); endfunction + function void e_bit7_3d1(input bit7_array1_t val); `CHECK_3D1(val); endfunction - function void e_bit121_0d(input bit[120:0] val); `CHECK_0D(val); endfunction - function void e_bit121_1d(input bit[120:0] val[2]); `CHECK_1D(val); endfunction - function void e_bit121_2d(input bit[120:0] val[3][2]); `CHECK_2D(val); endfunction - function void e_bit121_3d(input bit121_array_t val); `CHECK_3D(val); endfunction - function void e_bit121_1d1(input bit[120:0] val[1]); `CHECK_1D1(val); endfunction - function void e_bit121_2d1(input bit[120:0] val[1][1]); `CHECK_2D1(val); endfunction - function void e_bit121_3d1(input bit121_array1_t val); `CHECK_3D1(val); endfunction + function void e_bit121_0d(input bit[120:0] val); `CHECK_0D(val); endfunction + function void e_bit121_1d(input bit[120:0] val[2]); `CHECK_1D(val); endfunction + function void e_bit121_2d(input bit[120:0] val[3][2]); `CHECK_2D(val); endfunction + function void e_bit121_3d(input bit121_array_t val); `CHECK_3D(val); endfunction + function void e_bit121_1d1(input bit[120:0] val[1]); `CHECK_1D1(val); endfunction + function void e_bit121_2d1(input bit[120:0] val[1][1]); `CHECK_2D1(val); endfunction + function void e_bit121_3d1(input bit121_array1_t val); `CHECK_3D1(val); endfunction - function void e_logic1_0d(input logic val); `CHECK_0D(val); endfunction - function void e_logic1_1d(input logic val[2]); `CHECK_1D(val); endfunction - function void e_logic1_2d(input logic val[3][2]); `CHECK_2D(val); endfunction - function void e_logic1_3d(input logic1_array_t val); `CHECK_3D(val); endfunction - function void e_logic1_1d1(input logic val[1]); `CHECK_1D1(val); endfunction - function void e_logic1_2d1(input logic val[1][1]); `CHECK_2D1(val); endfunction - function void e_logic1_3d1(input logic1_array1_t val); `CHECK_3D1(val); endfunction + function void e_logic1_0d(input logic val); `CHECK_0D(val); endfunction + function void e_logic1_1d(input logic val[2]); `CHECK_1D(val); endfunction + function void e_logic1_2d(input logic val[3][2]); `CHECK_2D(val); endfunction + function void e_logic1_3d(input logic1_array_t val); `CHECK_3D(val); endfunction + function void e_logic1_1d1(input logic val[1]); `CHECK_1D1(val); endfunction + function void e_logic1_2d1(input logic val[1][1]); `CHECK_2D1(val); endfunction + function void e_logic1_3d1(input logic1_array1_t val); `CHECK_3D1(val); endfunction - function void e_logic7_0d(input logic[6:0] val); `CHECK_0D(val); endfunction - function void e_logic7_1d(input logic[6:0] val[2]); `CHECK_1D(val); endfunction - function void e_logic7_2d(input logic[6:0] val[3][2]); `CHECK_2D(val); endfunction - function void e_logic7_3d(input logic7_array_t val); `CHECK_3D(val); endfunction - function void e_logic7_1d1(input logic[6:0] val[1]); `CHECK_1D1(val); endfunction - function void e_logic7_2d1(input logic[6:0] val[1][1]); `CHECK_2D1(val); endfunction - function void e_logic7_3d1(input logic7_array1_t val); `CHECK_3D1(val); endfunction + function void e_logic7_0d(input logic[6:0] val); `CHECK_0D(val); endfunction + function void e_logic7_1d(input logic[6:0] val[2]); `CHECK_1D(val); endfunction + function void e_logic7_2d(input logic[6:0] val[3][2]); `CHECK_2D(val); endfunction + function void e_logic7_3d(input logic7_array_t val); `CHECK_3D(val); endfunction + function void e_logic7_1d1(input logic[6:0] val[1]); `CHECK_1D1(val); endfunction + function void e_logic7_2d1(input logic[6:0] val[1][1]); `CHECK_2D1(val); endfunction + function void e_logic7_3d1(input logic7_array1_t val); `CHECK_3D1(val); endfunction - function void e_logic121_0d(input logic[120:0] val); `CHECK_0D(val); endfunction - function void e_logic121_1d(input logic[120:0] val[2]); `CHECK_1D(val); endfunction - function void e_logic121_2d(input logic[120:0] val[3][2]); `CHECK_2D(val); endfunction - function void e_logic121_3d(input logic121_array_t val); `CHECK_3D(val); endfunction - function void e_logic121_1d1(input logic[120:0] val[1]); `CHECK_1D1(val); endfunction - function void e_logic121_2d1(input logic[120:0] val[1][1]); `CHECK_2D1(val); endfunction - function void e_logic121_3d1(input logic121_array1_t val); `CHECK_3D1(val); endfunction + function void e_logic121_0d(input logic[120:0] val); `CHECK_0D(val); endfunction + function void e_logic121_1d(input logic[120:0] val[2]); `CHECK_1D(val); endfunction + function void e_logic121_2d(input logic[120:0] val[3][2]); `CHECK_2D(val); endfunction + function void e_logic121_3d(input logic121_array_t val); `CHECK_3D(val); endfunction + function void e_logic121_1d1(input logic[120:0] val[1]); `CHECK_1D1(val); endfunction + function void e_logic121_2d1(input logic[120:0] val[1][1]); `CHECK_2D1(val); endfunction + function void e_logic121_3d1(input logic121_array1_t val); `CHECK_3D1(val); endfunction - function void e_pack_struct_0d(input pack_struct_t val); `CHECK_0D(val); endfunction - function void e_pack_struct_1d(input pack_struct_t val[2]); `CHECK_1D(val); endfunction - function void e_pack_struct_2d(input pack_struct_t val[3][2]); `CHECK_2D(val); endfunction - function void e_pack_struct_3d(input pack_struct_array_t val); `CHECK_3D(val); endfunction - function void e_pack_struct_1d1(input pack_struct_t val[1]); `CHECK_1D1(val); endfunction - function void e_pack_struct_2d1(input pack_struct_t val[1][1]); `CHECK_2D1(val); endfunction - function void e_pack_struct_3d1(input pack_struct_array1_t val); `CHECK_3D1(val); endfunction + function void e_pack_struct_0d(input pack_struct_t val); `CHECK_0D(val); endfunction + function void e_pack_struct_1d(input pack_struct_t val[2]); `CHECK_1D(val); endfunction + function void e_pack_struct_2d(input pack_struct_t val[3][2]); `CHECK_2D(val); endfunction + function void e_pack_struct_3d(input pack_struct_array_t val); `CHECK_3D(val); endfunction + function void e_pack_struct_1d1(input pack_struct_t val[1]); `CHECK_1D1(val); endfunction + function void e_pack_struct_2d1(input pack_struct_t val[1][1]); `CHECK_2D1(val); endfunction + function void e_pack_struct_3d1(input pack_struct_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT - function void e_unpack_struct_0d(input unpack_struct_t val); - if (val.val != 42) begin - $display("Mismatch expected:%s actual:%s", "42", val.val); - $stop; - end - endfunction - function void e_unpack_struct_1d(input unpack_struct_t val[2]); - if (val[0].val != 43) begin - $display("Mismatch expected:%s actual:%s", "43", val[0].val); - $stop; - end - if (val[1].val != 44) begin - $display("Mismatch expected:%s actual:%s", "44", val[1].val); - $stop; - end - endfunction - function void e_unpack_struct_2d(input unpack_struct_t val[3][2]); - if (val[0][1].val != 45) begin - $display("Mismatch expected:%s actual:%s", "45", val[0][1].val); - $stop; - end - if (val[1][1].val != 46) begin - $display("Mismatch expected:%s actual:%s", "46", val[1][1].val); - $stop; - end - if (val[2][1].val != 47) begin - $display("Mismatch expected:%s actual:%s", "47", val[2][1].val); - $stop; - end - endfunction - function void e_unpack_struct_3d(input unpack_struct_array_t val); - if (val[0][0][0].val != 48) begin - $display("Mismatch expected:%s actual:%s", "48", val[0][0][0].val); - $stop; - end - if (val[1][0][0].val != 49) begin - $display("Mismatch expected:%s actual:%s", "49", val[1][0][0].val); - $stop; - end - if (val[2][0][0].val != 50) begin - $display("Mismatch expected:%s actual:%s", "50", val[2][0][0].val); - $stop; - end - if (val[3][0][0].val != 51) begin - $display("Mismatch expected:%s actual:%s", "51", val[3][0][0].val); - $stop; - end - endfunction - function void e_unpack_struct_1d1(input unpack_struct_t val[1]); - if (val[0].val != 52) begin - $display("Mismatch expected:%s actual:%s", "52", val[0].val); - $stop; - end - endfunction - function void e_unpack_struct_2d1(input unpack_struct_t val[1][1]); - if (val[0][0].val != 53) begin - $display("Mismatch expected:%s actual:%s", "53", val[0][0].val); - $stop; - end - endfunction - function void e_unpack_struct_3d1(input unpack_struct_array1_t val); - if (val[0][0][0].val != 54) begin - $display("Mismatch expected:%s actual:%s", "54", val[0][0][0].val); - $stop; - end - endfunction + function void e_unpack_struct_0d(input unpack_struct_t val); + if (val.val != 42) begin + $display("Mismatch expected:%s actual:%s", "42", val.val); + $stop; + end + endfunction + function void e_unpack_struct_1d(input unpack_struct_t val[2]); + if (val[0].val != 43) begin + $display("Mismatch expected:%s actual:%s", "43", val[0].val); + $stop; + end + if (val[1].val != 44) begin + $display("Mismatch expected:%s actual:%s", "44", val[1].val); + $stop; + end + endfunction + function void e_unpack_struct_2d(input unpack_struct_t val[3][2]); + if (val[0][1].val != 45) begin + $display("Mismatch expected:%s actual:%s", "45", val[0][1].val); + $stop; + end + if (val[1][1].val != 46) begin + $display("Mismatch expected:%s actual:%s", "46", val[1][1].val); + $stop; + end + if (val[2][1].val != 47) begin + $display("Mismatch expected:%s actual:%s", "47", val[2][1].val); + $stop; + end + endfunction + function void e_unpack_struct_3d(input unpack_struct_array_t val); + if (val[0][0][0].val != 48) begin + $display("Mismatch expected:%s actual:%s", "48", val[0][0][0].val); + $stop; + end + if (val[1][0][0].val != 49) begin + $display("Mismatch expected:%s actual:%s", "49", val[1][0][0].val); + $stop; + end + if (val[2][0][0].val != 50) begin + $display("Mismatch expected:%s actual:%s", "50", val[2][0][0].val); + $stop; + end + if (val[3][0][0].val != 51) begin + $display("Mismatch expected:%s actual:%s", "51", val[3][0][0].val); + $stop; + end + endfunction + function void e_unpack_struct_1d1(input unpack_struct_t val[1]); + if (val[0].val != 52) begin + $display("Mismatch expected:%s actual:%s", "52", val[0].val); + $stop; + end + endfunction + function void e_unpack_struct_2d1(input unpack_struct_t val[1][1]); + if (val[0][0].val != 53) begin + $display("Mismatch expected:%s actual:%s", "53", val[0][0].val); + $stop; + end + endfunction + function void e_unpack_struct_3d1(input unpack_struct_array1_t val); + if (val[0][0][0].val != 54) begin + $display("Mismatch expected:%s actual:%s", "54", val[0][0][0].val); + $stop; + end + endfunction `endif - //====================================================================== - // Invoke all imported functions - //====================================================================== + //====================================================================== + // Invoke all imported functions + //====================================================================== - import "DPI-C" context function void check_exports(); + import "DPI-C" context function void check_exports(); - initial begin - byte_array_t byte_array; - byte_array1_t byte_array1; - byte_unsigned_array_t byte_unsigned_array; - byte_unsigned_array1_t byte_unsigned_array1; - shortint_array_t shortint_array; - shortint_array1_t shortint_array1; - shortint_unsigned_array_t shortint_unsigned_array; - shortint_unsigned_array1_t shortint_unsigned_array1; - int_array_t int_array; - int_array1_t int_array1; - int_unsigned_array_t int_unsigned_array; - int_unsigned_array1_t int_unsigned_array1; - longint_array_t longint_array; - longint_array1_t longint_array1; - longint_unsigned_array_t longint_unsigned_array; - longint_unsigned_array1_t longint_unsigned_array1; + initial begin + byte_array_t byte_array; + byte_array1_t byte_array1; + byte_unsigned_array_t byte_unsigned_array; + byte_unsigned_array1_t byte_unsigned_array1; + shortint_array_t shortint_array; + shortint_array1_t shortint_array1; + shortint_unsigned_array_t shortint_unsigned_array; + shortint_unsigned_array1_t shortint_unsigned_array1; + int_array_t int_array; + int_array1_t int_array1; + int_unsigned_array_t int_unsigned_array; + int_unsigned_array1_t int_unsigned_array1; + longint_array_t longint_array; + longint_array1_t longint_array1; + longint_unsigned_array_t longint_unsigned_array; + longint_unsigned_array1_t longint_unsigned_array1; `ifndef NO_TIME - time_array_t time_array; - time_array1_t time_array1; + time_array_t time_array; + time_array1_t time_array1; `endif `ifndef NO_INTEGER - integer_array_t integer_array; - integer_array1_t integer_array1; + integer_array_t integer_array; + integer_array1_t integer_array1; `endif - real_array_t real_array; - real_array1_t real_array1; + real_array_t real_array; + real_array1_t real_array1; `ifndef NO_SHORTREAL - shortreal_array_t shortreal_array; - shortreal_array1_t shortreal_array1; + shortreal_array_t shortreal_array; + shortreal_array1_t shortreal_array1; `endif - chandle_array_t chandle_array; - chandle_array1_t chandle_array1; - string_array_t string_array; - string_array1_t string_array1; - bit1_array_t bit1_array; - bit1_array1_t bit1_array1; - bit7_array_t bit7_array; - bit7_array1_t bit7_array1; - bit121_array_t bit121_array; - bit121_array1_t bit121_array1; - logic1_array_t logic1_array; - logic1_array1_t logic1_array1; - logic7_array_t logic7_array; - logic7_array1_t logic7_array1; - logic121_array_t logic121_array; - logic121_array1_t logic121_array1; - pack_struct_array_t pack_struct_array; - pack_struct_array1_t pack_struct_array1; + chandle_array_t chandle_array; + chandle_array1_t chandle_array1; + string_array_t string_array; + string_array1_t string_array1; + bit1_array_t bit1_array; + bit1_array1_t bit1_array1; + bit7_array_t bit7_array; + bit7_array1_t bit7_array1; + bit121_array_t bit121_array; + bit121_array1_t bit121_array1; + logic1_array_t logic1_array; + logic1_array1_t logic1_array1; + logic7_array_t logic7_array; + logic7_array1_t logic7_array1; + logic121_array_t logic121_array; + logic121_array1_t logic121_array1; + pack_struct_array_t pack_struct_array; + pack_struct_array1_t pack_struct_array1; `ifndef NO_UNPACK_STRUCT - unpack_struct_array_t unpack_struct_array; - unpack_struct_array1_t unpack_struct_array1; + unpack_struct_array_t unpack_struct_array; + unpack_struct_array1_t unpack_struct_array1; `endif - `SET_VALUES(byte_array); - i_byte_0d(byte_array[3][2][1]); - i_byte_1d(byte_array[2][1]); - i_byte_2d(byte_array[1]); - i_byte_3d(byte_array); + `SET_VALUES(byte_array); + i_byte_0d(byte_array[3][2][1]); + i_byte_1d(byte_array[2][1]); + i_byte_2d(byte_array[1]); + i_byte_3d(byte_array); - byte_array1[0][0][0] = 52; - i_byte_1d1(byte_array1[0][0]); - byte_array1[0][0][0] = 53; - i_byte_2d1(byte_array1[0]); - byte_array1[0][0][0] = 54; - i_byte_3d1(byte_array1); + byte_array1[0][0][0] = 52; + i_byte_1d1(byte_array1[0][0]); + byte_array1[0][0][0] = 53; + i_byte_2d1(byte_array1[0]); + byte_array1[0][0][0] = 54; + i_byte_3d1(byte_array1); - `SET_VALUES(byte_unsigned_array); - i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); - i_byte_unsigned_1d(byte_unsigned_array[2][1]); - i_byte_unsigned_2d(byte_unsigned_array[1]); - i_byte_unsigned_3d(byte_unsigned_array); + `SET_VALUES(byte_unsigned_array); + i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); + i_byte_unsigned_1d(byte_unsigned_array[2][1]); + i_byte_unsigned_2d(byte_unsigned_array[1]); + i_byte_unsigned_3d(byte_unsigned_array); - byte_unsigned_array1[0][0][0] = 52; - i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); - byte_unsigned_array1[0][0][0] = 53; - i_byte_unsigned_2d1(byte_unsigned_array1[0]); - byte_unsigned_array1[0][0][0] = 54; - i_byte_unsigned_3d1(byte_unsigned_array1); + byte_unsigned_array1[0][0][0] = 52; + i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); + byte_unsigned_array1[0][0][0] = 53; + i_byte_unsigned_2d1(byte_unsigned_array1[0]); + byte_unsigned_array1[0][0][0] = 54; + i_byte_unsigned_3d1(byte_unsigned_array1); - `SET_VALUES(shortint_array); - i_shortint_0d(shortint_array[3][2][1]); - i_shortint_1d(shortint_array[2][1]); - i_shortint_2d(shortint_array[1]); - i_shortint_3d(shortint_array); + `SET_VALUES(shortint_array); + i_shortint_0d(shortint_array[3][2][1]); + i_shortint_1d(shortint_array[2][1]); + i_shortint_2d(shortint_array[1]); + i_shortint_3d(shortint_array); - shortint_array1[0][0][0] = 52; - i_shortint_1d1(shortint_array1[0][0]); - shortint_array1[0][0][0] = 53; - i_shortint_2d1(shortint_array1[0]); - shortint_array1[0][0][0] = 54; - i_shortint_3d1(shortint_array1); + shortint_array1[0][0][0] = 52; + i_shortint_1d1(shortint_array1[0][0]); + shortint_array1[0][0][0] = 53; + i_shortint_2d1(shortint_array1[0]); + shortint_array1[0][0][0] = 54; + i_shortint_3d1(shortint_array1); - `SET_VALUES(shortint_unsigned_array); - i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); - i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); - i_shortint_unsigned_2d(shortint_unsigned_array[1]); - i_shortint_unsigned_3d(shortint_unsigned_array); + `SET_VALUES(shortint_unsigned_array); + i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); + i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); + i_shortint_unsigned_2d(shortint_unsigned_array[1]); + i_shortint_unsigned_3d(shortint_unsigned_array); - shortint_unsigned_array1[0][0][0] = 52; - i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); - shortint_unsigned_array1[0][0][0] = 53; - i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); - shortint_unsigned_array1[0][0][0] = 54; - i_shortint_unsigned_3d1(shortint_unsigned_array1); + shortint_unsigned_array1[0][0][0] = 52; + i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); + shortint_unsigned_array1[0][0][0] = 53; + i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); + shortint_unsigned_array1[0][0][0] = 54; + i_shortint_unsigned_3d1(shortint_unsigned_array1); - `SET_VALUES(int_array); - i_int_0d(int_array[3][2][1]); - i_int_1d(int_array[2][1]); - i_int_2d(int_array[1]); - i_int_3d(int_array); + `SET_VALUES(int_array); + i_int_0d(int_array[3][2][1]); + i_int_1d(int_array[2][1]); + i_int_2d(int_array[1]); + i_int_3d(int_array); - int_array1[0][0][0] = 52; - i_int_1d1(int_array1[0][0]); - int_array1[0][0][0] = 53; - i_int_2d1(int_array1[0]); - int_array1[0][0][0] = 54; - i_int_3d1(int_array1); + int_array1[0][0][0] = 52; + i_int_1d1(int_array1[0][0]); + int_array1[0][0][0] = 53; + i_int_2d1(int_array1[0]); + int_array1[0][0][0] = 54; + i_int_3d1(int_array1); - `SET_VALUES(int_unsigned_array); - i_int_unsigned_0d(int_unsigned_array[3][2][1]); - i_int_unsigned_1d(int_unsigned_array[2][1]); - i_int_unsigned_2d(int_unsigned_array[1]); - i_int_unsigned_3d(int_unsigned_array); + `SET_VALUES(int_unsigned_array); + i_int_unsigned_0d(int_unsigned_array[3][2][1]); + i_int_unsigned_1d(int_unsigned_array[2][1]); + i_int_unsigned_2d(int_unsigned_array[1]); + i_int_unsigned_3d(int_unsigned_array); - int_unsigned_array1[0][0][0] = 52; - i_int_unsigned_1d1(int_unsigned_array1[0][0]); - int_unsigned_array1[0][0][0] = 53; - i_int_unsigned_2d1(int_unsigned_array1[0]); - int_unsigned_array1[0][0][0] = 54; - i_int_unsigned_3d1(int_unsigned_array1); + int_unsigned_array1[0][0][0] = 52; + i_int_unsigned_1d1(int_unsigned_array1[0][0]); + int_unsigned_array1[0][0][0] = 53; + i_int_unsigned_2d1(int_unsigned_array1[0]); + int_unsigned_array1[0][0][0] = 54; + i_int_unsigned_3d1(int_unsigned_array1); - `SET_VALUES(longint_array); - i_longint_0d(longint_array[3][2][1]); - i_longint_1d(longint_array[2][1]); - i_longint_2d(longint_array[1]); - i_longint_3d(longint_array); + `SET_VALUES(longint_array); + i_longint_0d(longint_array[3][2][1]); + i_longint_1d(longint_array[2][1]); + i_longint_2d(longint_array[1]); + i_longint_3d(longint_array); - longint_array1[0][0][0] = 52; - i_longint_1d1(longint_array1[0][0]); - longint_array1[0][0][0] = 53; - i_longint_2d1(longint_array1[0]); - longint_array1[0][0][0] = 54; - i_longint_3d1(longint_array1); + longint_array1[0][0][0] = 52; + i_longint_1d1(longint_array1[0][0]); + longint_array1[0][0][0] = 53; + i_longint_2d1(longint_array1[0]); + longint_array1[0][0][0] = 54; + i_longint_3d1(longint_array1); - `SET_VALUES(longint_unsigned_array); - i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); - i_longint_unsigned_1d(longint_unsigned_array[2][1]); - i_longint_unsigned_2d(longint_unsigned_array[1]); - i_longint_unsigned_3d(longint_unsigned_array); + `SET_VALUES(longint_unsigned_array); + i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); + i_longint_unsigned_1d(longint_unsigned_array[2][1]); + i_longint_unsigned_2d(longint_unsigned_array[1]); + i_longint_unsigned_3d(longint_unsigned_array); - longint_unsigned_array1[0][0][0] = 52; - i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); - longint_unsigned_array1[0][0][0] = 53; - i_longint_unsigned_2d1(longint_unsigned_array1[0]); - longint_unsigned_array1[0][0][0] = 54; - i_longint_unsigned_3d1(longint_unsigned_array1); + longint_unsigned_array1[0][0][0] = 52; + i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); + longint_unsigned_array1[0][0][0] = 53; + i_longint_unsigned_2d1(longint_unsigned_array1[0]); + longint_unsigned_array1[0][0][0] = 54; + i_longint_unsigned_3d1(longint_unsigned_array1); `ifndef NO_TIME - `SET_VALUES(time_array); - i_time_0d(time_array[3][2][1]); - i_time_1d(time_array[2][1]); - i_time_2d(time_array[1]); - i_time_3d(time_array); + `SET_VALUES(time_array); + i_time_0d(time_array[3][2][1]); + i_time_1d(time_array[2][1]); + i_time_2d(time_array[1]); + i_time_3d(time_array); - time_array1[0][0][0] = 52; - i_time_1d1(time_array1[0][0]); - time_array1[0][0][0] = 53; - i_time_2d1(time_array1[0]); - time_array1[0][0][0] = 54; - i_time_3d1(time_array1); + time_array1[0][0][0] = 52; + i_time_1d1(time_array1[0][0]); + time_array1[0][0][0] = 53; + i_time_2d1(time_array1[0]); + time_array1[0][0][0] = 54; + i_time_3d1(time_array1); `endif `ifndef NO_INTEGER - `SET_VALUES(integer_array); - i_integer_0d(integer_array[3][2][1]); - i_integer_1d(integer_array[2][1]); - i_integer_2d(integer_array[1]); - i_integer_3d(integer_array); + `SET_VALUES(integer_array); + i_integer_0d(integer_array[3][2][1]); + i_integer_1d(integer_array[2][1]); + i_integer_2d(integer_array[1]); + i_integer_3d(integer_array); - integer_array1[0][0][0] = 52; - i_integer_1d1(integer_array1[0][0]); - integer_array1[0][0][0] = 53; - i_integer_2d1(integer_array1[0]); - integer_array1[0][0][0] = 54; - i_integer_3d1(integer_array1); + integer_array1[0][0][0] = 52; + i_integer_1d1(integer_array1[0][0]); + integer_array1[0][0][0] = 53; + i_integer_2d1(integer_array1[0]); + integer_array1[0][0][0] = 54; + i_integer_3d1(integer_array1); `endif - `SET_VALUES(real_array); - i_real_0d(real_array[3][2][1]); - i_real_1d(real_array[2][1]); - i_real_2d(real_array[1]); - i_real_3d(real_array); + `SET_VALUES(real_array); + i_real_0d(real_array[3][2][1]); + i_real_1d(real_array[2][1]); + i_real_2d(real_array[1]); + i_real_3d(real_array); - real_array1[0][0][0] = 52; - i_real_1d1(real_array1[0][0]); - real_array1[0][0][0] = 53; - i_real_2d1(real_array1[0]); - real_array1[0][0][0] = 54; - i_real_3d1(real_array1); + real_array1[0][0][0] = 52; + i_real_1d1(real_array1[0][0]); + real_array1[0][0][0] = 53; + i_real_2d1(real_array1[0]); + real_array1[0][0][0] = 54; + i_real_3d1(real_array1); `ifndef NO_SHORTREAL - `SET_VALUES(shortreal_array); - i_shortreal_0d(shortreal_array[3][2][1]); - i_shortreal_1d(shortreal_array[2][1]); - i_shortreal_2d(shortreal_array[1]); - i_shortreal_3d(shortreal_array); + `SET_VALUES(shortreal_array); + i_shortreal_0d(shortreal_array[3][2][1]); + i_shortreal_1d(shortreal_array[2][1]); + i_shortreal_2d(shortreal_array[1]); + i_shortreal_3d(shortreal_array); - shortreal_array1[0][0][0] = 52; - i_shortreal_1d1(shotreal_array1[0][0]); - shortreal_array1[0][0][0] = 53; - i_shortreal_2d1(shotreal_array1[0]); - shortreal_array1[0][0][0] = 54; - i_shortreal_3d1(shotreal_array1); + shortreal_array1[0][0][0] = 52; + i_shortreal_1d1(shotreal_array1[0][0]); + shortreal_array1[0][0][0] = 53; + i_shortreal_2d1(shotreal_array1[0]); + shortreal_array1[0][0][0] = 54; + i_shortreal_3d1(shotreal_array1); `endif - for (int i = 0; i < 4; ++i) - for (int j = 0; j < 3; ++j) - for (int k = 0; k < 2; ++k) - chandle_array[i][j][k] = null; + for (int i = 0; i < 4; ++i) + for (int j = 0; j < 3; ++j) + for (int k = 0; k < 2; ++k) + chandle_array[i][j][k] = null; - chandle_array[3][2][1] = get_non_null(); - i_chandle_0d(chandle_array[3][2][1]); - chandle_array[2][1][0] = get_non_null(); - chandle_array[2][1][1] = get_non_null(); - i_chandle_1d(chandle_array[2][1]); - chandle_array[1][0][1] = get_non_null(); - chandle_array[1][1][1] = get_non_null(); - chandle_array[1][2][1] = get_non_null(); - i_chandle_2d(chandle_array[1]); - chandle_array[0][0][0] = get_non_null(); - chandle_array[1][0][0] = get_non_null(); - chandle_array[2][0][0] = get_non_null(); - chandle_array[3][0][0] = get_non_null(); - i_chandle_3d(chandle_array); + chandle_array[3][2][1] = get_non_null(); + i_chandle_0d(chandle_array[3][2][1]); + chandle_array[2][1][0] = get_non_null(); + chandle_array[2][1][1] = get_non_null(); + i_chandle_1d(chandle_array[2][1]); + chandle_array[1][0][1] = get_non_null(); + chandle_array[1][1][1] = get_non_null(); + chandle_array[1][2][1] = get_non_null(); + i_chandle_2d(chandle_array[1]); + chandle_array[0][0][0] = get_non_null(); + chandle_array[1][0][0] = get_non_null(); + chandle_array[2][0][0] = get_non_null(); + chandle_array[3][0][0] = get_non_null(); + i_chandle_3d(chandle_array); - chandle_array1[0][0][0] = get_non_null(); - i_chandle_1d1(chandle_array1[0][0]); - chandle_array1[0][0][0] = get_non_null(); - i_chandle_2d1(chandle_array1[0]); - chandle_array1[0][0][0] = get_non_null(); - i_chandle_3d1(chandle_array1); + chandle_array1[0][0][0] = get_non_null(); + i_chandle_1d1(chandle_array1[0][0]); + chandle_array1[0][0][0] = get_non_null(); + i_chandle_2d1(chandle_array1[0]); + chandle_array1[0][0][0] = get_non_null(); + i_chandle_3d1(chandle_array1); - string_array[3][2][1] = "42"; - string_array[2][1][0] = "43"; string_array[2][1][1] = "44"; - string_array[1][0][1] = "45"; string_array[1][1][1] = "46"; string_array[1][2][1] = "47"; - string_array[0][0][0] = "48"; string_array[1][0][0] = "49"; string_array[2][0][0] = "50"; string_array[3][0][0] = "51"; - i_string_0d(string_array[3][2][1]); - i_string_1d(string_array[2][1]); - i_string_2d(string_array[1]); - i_string_3d(string_array); + string_array[3][2][1] = "42"; + string_array[2][1][0] = "43"; string_array[2][1][1] = "44"; + string_array[1][0][1] = "45"; string_array[1][1][1] = "46"; string_array[1][2][1] = "47"; + string_array[0][0][0] = "48"; string_array[1][0][0] = "49"; string_array[2][0][0] = "50"; string_array[3][0][0] = "51"; + i_string_0d(string_array[3][2][1]); + i_string_1d(string_array[2][1]); + i_string_2d(string_array[1]); + i_string_3d(string_array); - string_array1[0][0][0] = "52"; - i_string_1d1(string_array1[0][0]); - string_array1[0][0][0] = "53"; - i_string_2d1(string_array1[0]); - string_array1[0][0][0] = "54"; - i_string_3d1(string_array1); + string_array1[0][0][0] = "52"; + i_string_1d1(string_array1[0][0]); + string_array1[0][0][0] = "53"; + i_string_2d1(string_array1[0]); + string_array1[0][0][0] = "54"; + i_string_3d1(string_array1); - `SET_VALUES(bit1_array); - i_bit1_0d(bit1_array[3][2][1]); - i_bit1_1d(bit1_array[2][1]); - i_bit1_2d(bit1_array[1]); - i_bit1_3d(bit1_array); + `SET_VALUES(bit1_array); + i_bit1_0d(bit1_array[3][2][1]); + i_bit1_1d(bit1_array[2][1]); + i_bit1_2d(bit1_array[1]); + i_bit1_3d(bit1_array); - bit1_array1[0][0][0] = 1'(52); - i_bit1_1d1(bit1_array1[0][0]); - bit1_array1[0][0][0] = 1'(53); - i_bit1_2d1(bit1_array1[0]); - bit1_array1[0][0][0] = 1'(54); - i_bit1_3d1(bit1_array1); + bit1_array1[0][0][0] = 1'(52); + i_bit1_1d1(bit1_array1[0][0]); + bit1_array1[0][0][0] = 1'(53); + i_bit1_2d1(bit1_array1[0]); + bit1_array1[0][0][0] = 1'(54); + i_bit1_3d1(bit1_array1); - `SET_VALUES(bit7_array); - i_bit7_0d(bit7_array[3][2][1]); - i_bit7_1d(bit7_array[2][1]); - i_bit7_2d(bit7_array[1]); - i_bit7_3d(bit7_array); + `SET_VALUES(bit7_array); + i_bit7_0d(bit7_array[3][2][1]); + i_bit7_1d(bit7_array[2][1]); + i_bit7_2d(bit7_array[1]); + i_bit7_3d(bit7_array); - bit7_array1[0][0][0] = 52; - i_bit7_1d1(bit7_array1[0][0]); - bit7_array1[0][0][0] = 53; - i_bit7_2d1(bit7_array1[0]); - bit7_array1[0][0][0] = 54; - i_bit7_3d1(bit7_array1); + bit7_array1[0][0][0] = 52; + i_bit7_1d1(bit7_array1[0][0]); + bit7_array1[0][0][0] = 53; + i_bit7_2d1(bit7_array1[0]); + bit7_array1[0][0][0] = 54; + i_bit7_3d1(bit7_array1); - `SET_VALUES(bit121_array); - i_bit121_0d(bit121_array[3][2][1]); - i_bit121_1d(bit121_array[2][1]); - i_bit121_2d(bit121_array[1]); - i_bit121_3d(bit121_array); + `SET_VALUES(bit121_array); + i_bit121_0d(bit121_array[3][2][1]); + i_bit121_1d(bit121_array[2][1]); + i_bit121_2d(bit121_array[1]); + i_bit121_3d(bit121_array); - bit121_array1[0][0][0] = 52; - i_bit121_1d1(bit121_array1[0][0]); - bit121_array1[0][0][0] = 53; - i_bit121_2d1(bit121_array1[0]); - bit121_array1[0][0][0] = 54; - i_bit121_3d1(bit121_array1); + bit121_array1[0][0][0] = 52; + i_bit121_1d1(bit121_array1[0][0]); + bit121_array1[0][0][0] = 53; + i_bit121_2d1(bit121_array1[0]); + bit121_array1[0][0][0] = 54; + i_bit121_3d1(bit121_array1); - `SET_VALUES(logic1_array); - i_logic1_0d(logic1_array[3][2][1]); - i_logic1_1d(logic1_array[2][1]); - i_logic1_2d(logic1_array[1]); - i_logic1_3d(logic1_array); + `SET_VALUES(logic1_array); + i_logic1_0d(logic1_array[3][2][1]); + i_logic1_1d(logic1_array[2][1]); + i_logic1_2d(logic1_array[1]); + i_logic1_3d(logic1_array); - logic1_array1[0][0][0] = 1'(52); - i_logic1_1d1(logic1_array1[0][0]); - logic1_array1[0][0][0] = 1'(53); - i_logic1_2d1(logic1_array1[0]); - logic1_array1[0][0][0] = 1'(54); - i_logic1_3d1(logic1_array1); + logic1_array1[0][0][0] = 1'(52); + i_logic1_1d1(logic1_array1[0][0]); + logic1_array1[0][0][0] = 1'(53); + i_logic1_2d1(logic1_array1[0]); + logic1_array1[0][0][0] = 1'(54); + i_logic1_3d1(logic1_array1); - `SET_VALUES(logic7_array); - i_logic7_0d(logic7_array[3][2][1]); - i_logic7_1d(logic7_array[2][1]); - i_logic7_2d(logic7_array[1]); - i_logic7_3d(logic7_array); + `SET_VALUES(logic7_array); + i_logic7_0d(logic7_array[3][2][1]); + i_logic7_1d(logic7_array[2][1]); + i_logic7_2d(logic7_array[1]); + i_logic7_3d(logic7_array); - logic7_array1[0][0][0] = 52; - i_logic7_1d1(logic7_array1[0][0]); - logic7_array1[0][0][0] = 53; - i_logic7_2d1(logic7_array1[0]); - logic7_array1[0][0][0] = 54; - i_logic7_3d1(logic7_array1); + logic7_array1[0][0][0] = 52; + i_logic7_1d1(logic7_array1[0][0]); + logic7_array1[0][0][0] = 53; + i_logic7_2d1(logic7_array1[0]); + logic7_array1[0][0][0] = 54; + i_logic7_3d1(logic7_array1); - `SET_VALUES(logic121_array); - i_logic121_0d(logic121_array[3][2][1]); - i_logic121_1d(logic121_array[2][1]); - i_logic121_2d(logic121_array[1]); - i_logic121_3d(logic121_array); + `SET_VALUES(logic121_array); + i_logic121_0d(logic121_array[3][2][1]); + i_logic121_1d(logic121_array[2][1]); + i_logic121_2d(logic121_array[1]); + i_logic121_3d(logic121_array); - logic121_array1[0][0][0] = 52; - i_logic121_1d1(logic121_array1[0][0]); - logic121_array1[0][0][0] = 53; - i_logic121_2d1(logic121_array1[0]); - logic121_array1[0][0][0] = 54; - i_logic121_3d1(logic121_array1); + logic121_array1[0][0][0] = 52; + i_logic121_1d1(logic121_array1[0][0]); + logic121_array1[0][0][0] = 53; + i_logic121_2d1(logic121_array1[0]); + logic121_array1[0][0][0] = 54; + i_logic121_3d1(logic121_array1); - `SET_VALUES(pack_struct_array); - i_pack_struct_0d(pack_struct_array[3][2][1]); - i_pack_struct_1d(pack_struct_array[2][1]); - i_pack_struct_2d(pack_struct_array[1]); - i_pack_struct_3d(pack_struct_array); + `SET_VALUES(pack_struct_array); + i_pack_struct_0d(pack_struct_array[3][2][1]); + i_pack_struct_1d(pack_struct_array[2][1]); + i_pack_struct_2d(pack_struct_array[1]); + i_pack_struct_3d(pack_struct_array); - pack_struct_array1[0][0][0] = 52; - i_pack_struct_1d1(pack_struct_array1[0][0]); - pack_struct_array1[0][0][0] = 53; - i_pack_struct_2d1(pack_struct_array1[0]); - pack_struct_array1[0][0][0] = 54; - i_pack_struct_3d1(pack_struct_array1); + pack_struct_array1[0][0][0] = 52; + i_pack_struct_1d1(pack_struct_array1[0][0]); + pack_struct_array1[0][0][0] = 53; + i_pack_struct_2d1(pack_struct_array1[0]); + pack_struct_array1[0][0][0] = 54; + i_pack_struct_3d1(pack_struct_array1); `ifndef NO_UNPACK_STRUCT - unpack_struct_array[3][2][1].val = 42; - unpack_struct_array[2][1][0].val = 43; - unpack_struct_array[2][1][1].val = 44; + unpack_struct_array[3][2][1].val = 42; + unpack_struct_array[2][1][0].val = 43; + unpack_struct_array[2][1][1].val = 44; - unpack_struct_array[1][0][1].val = 45; - unpack_struct_array[1][1][1].val = 46; - unpack_struct_array[1][2][1].val = 47; + unpack_struct_array[1][0][1].val = 45; + unpack_struct_array[1][1][1].val = 46; + unpack_struct_array[1][2][1].val = 47; - unpack_struct_array[0][0][0].val = 48; - unpack_struct_array[1][0][0].val = 49; - unpack_struct_array[2][0][0].val = 50; - unpack_struct_array[3][0][0].val = 51; - i_unpack_struct_0d(unpack_struct_array[3][2][1]); - i_unpack_struct_1d(unpack_struct_array[2][1]); - i_unpack_struct_2d(unpack_struct_array[1]); - i_unpack_struct_3d(unpack_struct_array); + unpack_struct_array[0][0][0].val = 48; + unpack_struct_array[1][0][0].val = 49; + unpack_struct_array[2][0][0].val = 50; + unpack_struct_array[3][0][0].val = 51; + i_unpack_struct_0d(unpack_struct_array[3][2][1]); + i_unpack_struct_1d(unpack_struct_array[2][1]); + i_unpack_struct_2d(unpack_struct_array[1]); + i_unpack_struct_3d(unpack_struct_array); - unpack_struct_array1[0][0][0].val = 52; - i_unpack_struct_1d1(unpack_struct_array1[0][0]); - unpack_struct_array1[0][0][0].val = 53; - i_unpack_struct_2d1(unpack_struct_array1[0]); - unpack_struct_array1[0][0][0].val = 54; - i_unpack_struct_3d1(unpack_struct_array1); + unpack_struct_array1[0][0][0].val = 52; + i_unpack_struct_1d1(unpack_struct_array1[0][0]); + unpack_struct_array1[0][0][0].val = 53; + i_unpack_struct_2d1(unpack_struct_array1[0]); + unpack_struct_array1[0][0][0].val = 54; + i_unpack_struct_3d1(unpack_struct_array1); `endif - check_exports(); + check_exports(); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_arg_output_type.v b/test_regress/t/t_dpi_arg_output_type.v index bc930b283..832c540ee 100644 --- a/test_regress/t/t_dpi_arg_output_type.v +++ b/test_regress/t/t_dpi_arg_output_type.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -26,964 +27,962 @@ `define NULL null `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); `ifdef VERILATOR - wire _unused = &{1'b0, clk}; + wire _unused = &{1'b0, clk}; `endif - // Legal output argument types for DPI functions + // Legal output argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - typedef byte byte_t; - typedef byte unsigned byte_unsigned_t; - typedef shortint shortint_t; - typedef shortint unsigned shortint_unsigned_t; - typedef int int_t; - typedef int unsigned int_unsigned_t; - typedef longint longint_t; - typedef longint unsigned longint_unsigned_t; + // Basic types as per IEEE 1800-2023 35.5.6 + typedef byte byte_t; + typedef byte unsigned byte_unsigned_t; + typedef shortint shortint_t; + typedef shortint unsigned shortint_unsigned_t; + typedef int int_t; + typedef int unsigned int_unsigned_t; + typedef longint longint_t; + typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME - typedef time time_t; + typedef time time_t; `endif `ifndef NO_INTEGER - typedef integer integer_t; + typedef integer integer_t; `endif - typedef real real_t; + typedef real real_t; `ifndef NO_SHORTREAL - typedef shortreal shortreal_t; + typedef shortreal shortreal_t; `endif - typedef chandle chandle_t; - typedef string string_t; - typedef bit bit_t; - typedef logic logic_t; + typedef chandle chandle_t; + typedef string string_t; + typedef bit bit_t; + typedef logic logic_t; - // 2-state packed structures - typedef struct packed { bit x; } struct_2_state_1; - typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; - typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; - typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; - typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; - typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; + // 2-state packed structures + typedef struct packed { bit x; } struct_2_state_1; + typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; + typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; + typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; + typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; + typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; - // 2-state packed unions - typedef union packed { bit x; bit y; } union_2_state_1; - typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; - typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; - typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; - typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; - typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; + // 2-state packed unions + typedef union packed { bit x; bit y; } union_2_state_1; + typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; + typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; + typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; + typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; + typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; - // 4-state packed structures - typedef struct packed { logic x; } struct_4_state_1; - typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; - typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; - typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; - typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; - typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; + // 4-state packed structures + typedef struct packed { logic x; } struct_4_state_1; + typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; + typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; + typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; + typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; + typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; - // 4-state packed unions - typedef union packed { logic x; bit y; } union_4_state_1; - typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; - typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; - typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; - typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; - typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; + // 4-state packed unions + typedef union packed { logic x; bit y; } union_4_state_1; + typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; + typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; + typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; + typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; + typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - import "DPI-C" function void i_byte (output byte o); - import "DPI-C" function void i_byte_unsigned (output byte unsigned o); - import "DPI-C" function void i_shortint (output shortint o); - import "DPI-C" function void i_shortint_unsigned (output shortint unsigned o); - import "DPI-C" function void i_int (output int o); - import "DPI-C" function void i_int_unsigned (output int unsigned o); - import "DPI-C" function void i_longint (output longint o); - import "DPI-C" function void i_longint_unsigned (output longint unsigned o); + // Basic types as per IEEE 1800-2023 35.5.6 + import "DPI-C" function void i_byte (output byte o); + import "DPI-C" function void i_byte_unsigned (output byte unsigned o); + import "DPI-C" function void i_shortint (output shortint o); + import "DPI-C" function void i_shortint_unsigned (output shortint unsigned o); + import "DPI-C" function void i_int (output int o); + import "DPI-C" function void i_int_unsigned (output int unsigned o); + import "DPI-C" function void i_longint (output longint o); + import "DPI-C" function void i_longint_unsigned (output longint unsigned o); `ifndef NO_TIME - import "DPI-C" function void i_time (output time o); + import "DPI-C" function void i_time (output time o); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer (output integer o); + import "DPI-C" function void i_integer (output integer o); `endif - import "DPI-C" function void i_real (output real o); + import "DPI-C" function void i_real (output real o); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal (output shortreal o); + import "DPI-C" function void i_shortreal (output shortreal o); `endif - import "DPI-C" function void i_chandle (output chandle o); - import "DPI-C" function void i_string (output string o); - import "DPI-C" function void i_bit (output bit o); - import "DPI-C" function void i_logic (output logic o); + import "DPI-C" function void i_chandle (output chandle o); + import "DPI-C" function void i_string (output string o); + import "DPI-C" function void i_bit (output bit o); + import "DPI-C" function void i_logic (output logic o); - // Basic types via typedef - import "DPI-C" function void i_byte_t (output byte_t o); - import "DPI-C" function void i_byte_unsigned_t (output byte_unsigned_t o); - import "DPI-C" function void i_shortint_t (output shortint_t o); - import "DPI-C" function void i_shortint_unsigned_t (output shortint_unsigned_t o); - import "DPI-C" function void i_int_t (output int_t o); - import "DPI-C" function void i_int_unsigned_t (output int_unsigned_t o); - import "DPI-C" function void i_longint_t (output longint_t o); - import "DPI-C" function void i_longint_unsigned_t (output longint_unsigned_t o); + // Basic types via typedef + import "DPI-C" function void i_byte_t (output byte_t o); + import "DPI-C" function void i_byte_unsigned_t (output byte_unsigned_t o); + import "DPI-C" function void i_shortint_t (output shortint_t o); + import "DPI-C" function void i_shortint_unsigned_t (output shortint_unsigned_t o); + import "DPI-C" function void i_int_t (output int_t o); + import "DPI-C" function void i_int_unsigned_t (output int_unsigned_t o); + import "DPI-C" function void i_longint_t (output longint_t o); + import "DPI-C" function void i_longint_unsigned_t (output longint_unsigned_t o); `ifndef NO_TIME - import "DPI-C" function void i_time_t (output time_t o); + import "DPI-C" function void i_time_t (output time_t o); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_t (output integer_t o); + import "DPI-C" function void i_integer_t (output integer_t o); `endif - import "DPI-C" function void i_real_t (output real_t o); + import "DPI-C" function void i_real_t (output real_t o); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_t (output shortreal_t o); + import "DPI-C" function void i_shortreal_t (output shortreal_t o); `endif - import "DPI-C" function void i_chandle_t (output chandle_t o); - import "DPI-C" function void i_string_t (output string_t o); - import "DPI-C" function void i_bit_t (output bit_t o); - import "DPI-C" function void i_logic_t (output logic_t o); + import "DPI-C" function void i_chandle_t (output chandle_t o); + import "DPI-C" function void i_string_t (output string_t o); + import "DPI-C" function void i_bit_t (output bit_t o); + import "DPI-C" function void i_logic_t (output logic_t o); - // 2-state packed arrays - import "DPI-C" function void i_array_2_state_1 (output bit [ 0:0] o); - import "DPI-C" function void i_array_2_state_32 (output bit [ 31:0] o); - import "DPI-C" function void i_array_2_state_33 (output bit [ 32:0] o); - import "DPI-C" function void i_array_2_state_64 (output bit [ 63:0] o); - import "DPI-C" function void i_array_2_state_65 (output bit [ 64:0] o); - import "DPI-C" function void i_array_2_state_128(output bit [127:0] o); + // 2-state packed arrays + import "DPI-C" function void i_array_2_state_1 (output bit [ 0:0] o); + import "DPI-C" function void i_array_2_state_32 (output bit [ 31:0] o); + import "DPI-C" function void i_array_2_state_33 (output bit [ 32:0] o); + import "DPI-C" function void i_array_2_state_64 (output bit [ 63:0] o); + import "DPI-C" function void i_array_2_state_65 (output bit [ 64:0] o); + import "DPI-C" function void i_array_2_state_128(output bit [127:0] o); - // 2-state packed structures - import "DPI-C" function void i_struct_2_state_1 (output struct_2_state_1 o); - import "DPI-C" function void i_struct_2_state_32 (output struct_2_state_32 o); - import "DPI-C" function void i_struct_2_state_33 (output struct_2_state_33 o); - import "DPI-C" function void i_struct_2_state_64 (output struct_2_state_64 o); - import "DPI-C" function void i_struct_2_state_65 (output struct_2_state_65 o); - import "DPI-C" function void i_struct_2_state_128 (output struct_2_state_128 o); + // 2-state packed structures + import "DPI-C" function void i_struct_2_state_1 (output struct_2_state_1 o); + import "DPI-C" function void i_struct_2_state_32 (output struct_2_state_32 o); + import "DPI-C" function void i_struct_2_state_33 (output struct_2_state_33 o); + import "DPI-C" function void i_struct_2_state_64 (output struct_2_state_64 o); + import "DPI-C" function void i_struct_2_state_65 (output struct_2_state_65 o); + import "DPI-C" function void i_struct_2_state_128 (output struct_2_state_128 o); - // 2-state packed unions - import "DPI-C" function void i_union_2_state_1 (output union_2_state_1 o); - import "DPI-C" function void i_union_2_state_32 (output union_2_state_32 o); - import "DPI-C" function void i_union_2_state_33 (output union_2_state_33 o); - import "DPI-C" function void i_union_2_state_64 (output union_2_state_64 o); - import "DPI-C" function void i_union_2_state_65 (output union_2_state_65 o); - import "DPI-C" function void i_union_2_state_128 (output union_2_state_128 o); + // 2-state packed unions + import "DPI-C" function void i_union_2_state_1 (output union_2_state_1 o); + import "DPI-C" function void i_union_2_state_32 (output union_2_state_32 o); + import "DPI-C" function void i_union_2_state_33 (output union_2_state_33 o); + import "DPI-C" function void i_union_2_state_64 (output union_2_state_64 o); + import "DPI-C" function void i_union_2_state_65 (output union_2_state_65 o); + import "DPI-C" function void i_union_2_state_128 (output union_2_state_128 o); - // 4-state packed arrays - import "DPI-C" function void i_array_4_state_1 (output logic [ 0:0] o); - import "DPI-C" function void i_array_4_state_32 (output logic [ 31:0] o); - import "DPI-C" function void i_array_4_state_33 (output logic [ 32:0] o); - import "DPI-C" function void i_array_4_state_64 (output logic [ 63:0] o); - import "DPI-C" function void i_array_4_state_65 (output logic [ 64:0] o); - import "DPI-C" function void i_array_4_state_128(output logic [127:0] o); + // 4-state packed arrays + import "DPI-C" function void i_array_4_state_1 (output logic [ 0:0] o); + import "DPI-C" function void i_array_4_state_32 (output logic [ 31:0] o); + import "DPI-C" function void i_array_4_state_33 (output logic [ 32:0] o); + import "DPI-C" function void i_array_4_state_64 (output logic [ 63:0] o); + import "DPI-C" function void i_array_4_state_65 (output logic [ 64:0] o); + import "DPI-C" function void i_array_4_state_128(output logic [127:0] o); - // 4-state packed structures - import "DPI-C" function void i_struct_4_state_1 (output struct_4_state_1 o); - import "DPI-C" function void i_struct_4_state_32 (output struct_4_state_32 o); - import "DPI-C" function void i_struct_4_state_33 (output struct_4_state_33 o); - import "DPI-C" function void i_struct_4_state_64 (output struct_4_state_64 o); - import "DPI-C" function void i_struct_4_state_65 (output struct_4_state_65 o); - import "DPI-C" function void i_struct_4_state_128 (output struct_4_state_128 o); + // 4-state packed structures + import "DPI-C" function void i_struct_4_state_1 (output struct_4_state_1 o); + import "DPI-C" function void i_struct_4_state_32 (output struct_4_state_32 o); + import "DPI-C" function void i_struct_4_state_33 (output struct_4_state_33 o); + import "DPI-C" function void i_struct_4_state_64 (output struct_4_state_64 o); + import "DPI-C" function void i_struct_4_state_65 (output struct_4_state_65 o); + import "DPI-C" function void i_struct_4_state_128 (output struct_4_state_128 o); - // 4-state packed unions - import "DPI-C" function void i_union_4_state_1 (output union_4_state_1 o); - import "DPI-C" function void i_union_4_state_32 (output union_4_state_32 o); - import "DPI-C" function void i_union_4_state_33 (output union_4_state_33 o); - import "DPI-C" function void i_union_4_state_64 (output union_4_state_64 o); - import "DPI-C" function void i_union_4_state_65 (output union_4_state_65 o); - import "DPI-C" function void i_union_4_state_128 (output union_4_state_128 o); + // 4-state packed unions + import "DPI-C" function void i_union_4_state_1 (output union_4_state_1 o); + import "DPI-C" function void i_union_4_state_32 (output union_4_state_32 o); + import "DPI-C" function void i_union_4_state_33 (output union_4_state_33 o); + import "DPI-C" function void i_union_4_state_64 (output union_4_state_64 o); + import "DPI-C" function void i_union_4_state_65 (output union_4_state_65 o); + import "DPI-C" function void i_union_4_state_128 (output union_4_state_128 o); - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - export "DPI-C" function e_byte; - export "DPI-C" function e_byte_unsigned; - export "DPI-C" function e_shortint; - export "DPI-C" function e_shortint_unsigned; - export "DPI-C" function e_int; - export "DPI-C" function e_int_unsigned; - export "DPI-C" function e_longint; - export "DPI-C" function e_longint_unsigned; + // Basic types as per IEEE 1800-2023 35.5.6 + export "DPI-C" function e_byte; + export "DPI-C" function e_byte_unsigned; + export "DPI-C" function e_shortint; + export "DPI-C" function e_shortint_unsigned; + export "DPI-C" function e_int; + export "DPI-C" function e_int_unsigned; + export "DPI-C" function e_longint; + export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME - export "DPI-C" function e_time; + export "DPI-C" function e_time; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer; + export "DPI-C" function e_integer; `endif - export "DPI-C" function e_real; + export "DPI-C" function e_real; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal; + export "DPI-C" function e_shortreal; `endif - export "DPI-C" function e_chandle; - export "DPI-C" function e_string; - export "DPI-C" function e_bit; - export "DPI-C" function e_logic; + export "DPI-C" function e_chandle; + export "DPI-C" function e_string; + export "DPI-C" function e_bit; + export "DPI-C" function e_logic; - // Basic types via typedef - export "DPI-C" function e_byte_t; - export "DPI-C" function e_byte_unsigned_t; - export "DPI-C" function e_shortint_t; - export "DPI-C" function e_shortint_unsigned_t; - export "DPI-C" function e_int_t; - export "DPI-C" function e_int_unsigned_t; - export "DPI-C" function e_longint_t; - export "DPI-C" function e_longint_unsigned_t; + // Basic types via typedef + export "DPI-C" function e_byte_t; + export "DPI-C" function e_byte_unsigned_t; + export "DPI-C" function e_shortint_t; + export "DPI-C" function e_shortint_unsigned_t; + export "DPI-C" function e_int_t; + export "DPI-C" function e_int_unsigned_t; + export "DPI-C" function e_longint_t; + export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME - export "DPI-C" function e_time_t; + export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_t; + export "DPI-C" function e_integer_t; `endif - export "DPI-C" function e_real_t; + export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_t; + export "DPI-C" function e_shortreal_t; `endif - export "DPI-C" function e_chandle_t; - export "DPI-C" function e_string_t; - export "DPI-C" function e_bit_t; - export "DPI-C" function e_logic_t; + export "DPI-C" function e_chandle_t; + export "DPI-C" function e_string_t; + export "DPI-C" function e_bit_t; + export "DPI-C" function e_logic_t; - // 2-state packed arrays - export "DPI-C" function e_array_2_state_1; - export "DPI-C" function e_array_2_state_32; - export "DPI-C" function e_array_2_state_33; - export "DPI-C" function e_array_2_state_64; - export "DPI-C" function e_array_2_state_65; - export "DPI-C" function e_array_2_state_128; + // 2-state packed arrays + export "DPI-C" function e_array_2_state_1; + export "DPI-C" function e_array_2_state_32; + export "DPI-C" function e_array_2_state_33; + export "DPI-C" function e_array_2_state_64; + export "DPI-C" function e_array_2_state_65; + export "DPI-C" function e_array_2_state_128; - // 2-state packed structures - export "DPI-C" function e_struct_2_state_1; - export "DPI-C" function e_struct_2_state_32; - export "DPI-C" function e_struct_2_state_33; - export "DPI-C" function e_struct_2_state_64; - export "DPI-C" function e_struct_2_state_65; - export "DPI-C" function e_struct_2_state_128; + // 2-state packed structures + export "DPI-C" function e_struct_2_state_1; + export "DPI-C" function e_struct_2_state_32; + export "DPI-C" function e_struct_2_state_33; + export "DPI-C" function e_struct_2_state_64; + export "DPI-C" function e_struct_2_state_65; + export "DPI-C" function e_struct_2_state_128; - // 2-state packed unions - export "DPI-C" function e_union_2_state_1; - export "DPI-C" function e_union_2_state_32; - export "DPI-C" function e_union_2_state_33; - export "DPI-C" function e_union_2_state_64; - export "DPI-C" function e_union_2_state_65; - export "DPI-C" function e_union_2_state_128; + // 2-state packed unions + export "DPI-C" function e_union_2_state_1; + export "DPI-C" function e_union_2_state_32; + export "DPI-C" function e_union_2_state_33; + export "DPI-C" function e_union_2_state_64; + export "DPI-C" function e_union_2_state_65; + export "DPI-C" function e_union_2_state_128; - // 4-state packed arrays - export "DPI-C" function e_array_4_state_1; - export "DPI-C" function e_array_4_state_32; - export "DPI-C" function e_array_4_state_33; - export "DPI-C" function e_array_4_state_64; - export "DPI-C" function e_array_4_state_65; - export "DPI-C" function e_array_4_state_128; + // 4-state packed arrays + export "DPI-C" function e_array_4_state_1; + export "DPI-C" function e_array_4_state_32; + export "DPI-C" function e_array_4_state_33; + export "DPI-C" function e_array_4_state_64; + export "DPI-C" function e_array_4_state_65; + export "DPI-C" function e_array_4_state_128; - // 4-state packed structures - export "DPI-C" function e_struct_4_state_1; - export "DPI-C" function e_struct_4_state_32; - export "DPI-C" function e_struct_4_state_33; - export "DPI-C" function e_struct_4_state_64; - export "DPI-C" function e_struct_4_state_65; - export "DPI-C" function e_struct_4_state_128; + // 4-state packed structures + export "DPI-C" function e_struct_4_state_1; + export "DPI-C" function e_struct_4_state_32; + export "DPI-C" function e_struct_4_state_33; + export "DPI-C" function e_struct_4_state_64; + export "DPI-C" function e_struct_4_state_65; + export "DPI-C" function e_struct_4_state_128; - // 4-state packed unions - export "DPI-C" function e_union_4_state_1; - export "DPI-C" function e_union_4_state_32; - export "DPI-C" function e_union_4_state_33; - export "DPI-C" function e_union_4_state_64; - export "DPI-C" function e_union_4_state_65; - export "DPI-C" function e_union_4_state_128; + // 4-state packed unions + export "DPI-C" function e_union_4_state_1; + export "DPI-C" function e_union_4_state_32; + export "DPI-C" function e_union_4_state_33; + export "DPI-C" function e_union_4_state_64; + export "DPI-C" function e_union_4_state_65; + export "DPI-C" function e_union_4_state_128; - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.6 - byte n_byte = 0; - function void e_byte(output byte o); - o = 8'd10 + n_byte; - n_byte++; - endfunction + // Basic types as per IEEE 1800-2023 35.5.6 + byte n_byte = 0; + function void e_byte(output byte o); + o = 8'd10 + n_byte; + n_byte++; + endfunction - byte n_byte_unsigned = 0; - function void e_byte_unsigned(output byte unsigned o); - o = 8'd20 + n_byte_unsigned; - n_byte_unsigned++; - endfunction + byte n_byte_unsigned = 0; + function void e_byte_unsigned(output byte unsigned o); + o = 8'd20 + n_byte_unsigned; + n_byte_unsigned++; + endfunction - shortint n_shortint = 0; - function void e_shortint(output shortint o); - o = 16'd30 + n_shortint; - n_shortint++; - endfunction + shortint n_shortint = 0; + function void e_shortint(output shortint o); + o = 16'd30 + n_shortint; + n_shortint++; + endfunction - shortint n_shortint_unsigned = 0; - function void e_shortint_unsigned(output shortint unsigned o); - o = 16'd40 + n_shortint_unsigned; - n_shortint_unsigned++; - endfunction + shortint n_shortint_unsigned = 0; + function void e_shortint_unsigned(output shortint unsigned o); + o = 16'd40 + n_shortint_unsigned; + n_shortint_unsigned++; + endfunction - int n_int = 0; - function void e_int(output int o); - o = 32'd50 + n_int; - n_int++; - endfunction + int n_int = 0; + function void e_int(output int o); + o = 32'd50 + n_int; + n_int++; + endfunction - int n_int_unsigned = 0; - function void e_int_unsigned(output int unsigned o); - o = 32'd60 + n_int_unsigned; - n_int_unsigned++; - endfunction + int n_int_unsigned = 0; + function void e_int_unsigned(output int unsigned o); + o = 32'd60 + n_int_unsigned; + n_int_unsigned++; + endfunction - longint n_longint = 0; - function void e_longint(output longint o); - o = 64'd70 + n_longint; - n_longint++; - endfunction + longint n_longint = 0; + function void e_longint(output longint o); + o = 64'd70 + n_longint; + n_longint++; + endfunction - longint n_longint_unsigned = 0; - function void e_longint_unsigned(output longint unsigned o); - o = 64'd80 + n_longint_unsigned; - n_longint_unsigned++; - endfunction + longint n_longint_unsigned = 0; + function void e_longint_unsigned(output longint unsigned o); + o = 64'd80 + n_longint_unsigned; + n_longint_unsigned++; + endfunction `ifndef NO_TIME - longint n_time = 0; - function void e_time(output time o); - o = 64'd90 + n_time; - n_time++; - endfunction + longint n_time = 0; + function void e_time(output time o); + o = 64'd90 + n_time; + n_time++; + endfunction `endif `ifndef NO_INTEGER - int n_integer = 0; - function void e_integer(output integer o); - o = 32'd100 + n_integer; - n_integer++; - endfunction + int n_integer = 0; + function void e_integer(output integer o); + o = 32'd100 + n_integer; + n_integer++; + endfunction `endif - int n_real = 0; - function void e_real(output real o); - o = real'(2*n_real + 1) / 2.0; - n_real++; - endfunction + int n_real = 0; + function void e_real(output real o); + o = real'(2*n_real + 1) / 2.0; + n_real++; + endfunction `ifndef NO_SHORTREAL - int n_shortreal = 0; - function void e_shortreal(output shortreal o); - o = shortreal'(4*n_shortreal + 1) / 4.0; - n_shortreal++; - endfunction + int n_shortreal = 0; + function void e_shortreal(output shortreal o); + o = shortreal'(4*n_shortreal + 1) / 4.0; + n_shortreal++; + endfunction `endif - int n_chandle = 0; - function void e_chandle(output chandle o); - $display("e_chandle %1d", n_chandle); - o = `NULL; - n_chandle++; - endfunction + int n_chandle = 0; + function void e_chandle(output chandle o); + $display("e_chandle %1d", n_chandle); + o = `NULL; + n_chandle++; + endfunction - int n_string = 0; - function void e_string(output string o); - $display("e_string %1d", n_string); - o = n_string[0] ? "World" : "Hello"; - n_string++; - endfunction + int n_string = 0; + function void e_string(output string o); + $display("e_string %1d", n_string); + o = n_string[0] ? "World" : "Hello"; + n_string++; + endfunction - int n_bit = 0; - function void e_bit(output bit o); - $display("e_bit %1d", n_bit); - o = n_bit[0]; - n_bit++; - endfunction + int n_bit = 0; + function void e_bit(output bit o); + $display("e_bit %1d", n_bit); + o = n_bit[0]; + n_bit++; + endfunction - int n_logic = 0; - function void e_logic(output logic o); - $display("e_logic %1d", n_logic); - o = ~n_logic[0]; - n_logic++; - endfunction + int n_logic = 0; + function void e_logic(output logic o); + $display("e_logic %1d", n_logic); + o = ~n_logic[0]; + n_logic++; + endfunction - // Basic types via typedefs - byte_t n_byte_t = 0; - function void e_byte_t(output byte_t o); - o = 8'd10 + n_byte_t; - n_byte_t += 2; - endfunction + // Basic types via typedefs + byte_t n_byte_t = 0; + function void e_byte_t(output byte_t o); + o = 8'd10 + n_byte_t; + n_byte_t += 2; + endfunction - byte n_byte_unsigned_t = 0; - function void e_byte_unsigned_t(output byte_unsigned_t o); - o = 8'd20 + n_byte_unsigned_t; - n_byte_unsigned_t += 2; - endfunction + byte n_byte_unsigned_t = 0; + function void e_byte_unsigned_t(output byte_unsigned_t o); + o = 8'd20 + n_byte_unsigned_t; + n_byte_unsigned_t += 2; + endfunction - shortint_t n_shortint_t = 0; - function void e_shortint_t(output shortint_t o); - o = 16'd30 + n_shortint_t; - n_shortint_t += 2; - endfunction + shortint_t n_shortint_t = 0; + function void e_shortint_t(output shortint_t o); + o = 16'd30 + n_shortint_t; + n_shortint_t += 2; + endfunction - shortint n_shortint_unsigned_t = 0; - function void e_shortint_unsigned_t(output shortint_unsigned_t o); - o = 16'd40 + n_shortint_unsigned_t; - n_shortint_unsigned_t += 2; - endfunction + shortint n_shortint_unsigned_t = 0; + function void e_shortint_unsigned_t(output shortint_unsigned_t o); + o = 16'd40 + n_shortint_unsigned_t; + n_shortint_unsigned_t += 2; + endfunction - int_t n_int_t = 0; - function void e_int_t(output int_t o); - o = 32'd50 + n_int_t; - n_int_t += 2; - endfunction + int_t n_int_t = 0; + function void e_int_t(output int_t o); + o = 32'd50 + n_int_t; + n_int_t += 2; + endfunction - int n_int_unsigned_t = 0; - function void e_int_unsigned_t(output int_unsigned_t o); - o = 32'd60 + n_int_unsigned_t; - n_int_unsigned_t += 2; - endfunction + int n_int_unsigned_t = 0; + function void e_int_unsigned_t(output int_unsigned_t o); + o = 32'd60 + n_int_unsigned_t; + n_int_unsigned_t += 2; + endfunction - longint_t n_longint_t = 0; - function void e_longint_t(output longint_t o); - o = 64'd70 + n_longint_t; - n_longint_t += 2; - endfunction + longint_t n_longint_t = 0; + function void e_longint_t(output longint_t o); + o = 64'd70 + n_longint_t; + n_longint_t += 2; + endfunction - longint n_longint_unsigned_t = 0; - function void e_longint_unsigned_t(output longint_unsigned_t o); - o = 64'd80 + n_longint_unsigned_t; - n_longint_unsigned_t += 2; - endfunction + longint n_longint_unsigned_t = 0; + function void e_longint_unsigned_t(output longint_unsigned_t o); + o = 64'd80 + n_longint_unsigned_t; + n_longint_unsigned_t += 2; + endfunction `ifndef NO_TIME - longint n_time_t = 0; - function void e_time_t(output time_t o); - o = 64'd90 + n_time_t; - n_time_t += 2; - endfunction + longint n_time_t = 0; + function void e_time_t(output time_t o); + o = 64'd90 + n_time_t; + n_time_t += 2; + endfunction `endif `ifndef NO_INTEGER - int n_integer_t = 0; - function void e_integer_t(output integer o); - o = 32'd100 + n_integer_t; - n_integer_t += 2; - endfunction + int n_integer_t = 0; + function void e_integer_t(output integer o); + o = 32'd100 + n_integer_t; + n_integer_t += 2; + endfunction `endif - int n_real_t = 0; - function void e_real_t(output real_t o); - o = real'(2*n_real_t + 1) / 2.0; - n_real_t += 2; - endfunction + int n_real_t = 0; + function void e_real_t(output real_t o); + o = real'(2*n_real_t + 1) / 2.0; + n_real_t += 2; + endfunction `ifndef NO_SHORTREAL - int n_shortreal_t = 0; - function void e_shortreal_t(output shortreal_t o); - o = shortreal'(4*n_shortreal_t + 1) / 4.0; - n_shortreal_t += 2; - endfunction + int n_shortreal_t = 0; + function void e_shortreal_t(output shortreal_t o); + o = shortreal'(4*n_shortreal_t + 1) / 4.0; + n_shortreal_t += 2; + endfunction `endif - int n_chandle_t = 0; - function void e_chandle_t(output chandle_t o); - $display("e_chandle_t %1d", n_chandle_t); - o = `NULL; - n_chandle_t++; - endfunction + int n_chandle_t = 0; + function void e_chandle_t(output chandle_t o); + $display("e_chandle_t %1d", n_chandle_t); + o = `NULL; + n_chandle_t++; + endfunction - int n_string_t = 0; - function void e_string_t(output string_t o); - $display("e_string_t %1d", n_string_t); - o = n_string_t[0] ? "World" : "Hello"; - n_string_t++; - endfunction + int n_string_t = 0; + function void e_string_t(output string_t o); + $display("e_string_t %1d", n_string_t); + o = n_string_t[0] ? "World" : "Hello"; + n_string_t++; + endfunction - int n_bit_t = 0; - function void e_bit_t(output bit_t o); - $display("e_bit_t %1d", n_bit_t); - o = n_bit_t[0]; - n_bit_t++; - endfunction + int n_bit_t = 0; + function void e_bit_t(output bit_t o); + $display("e_bit_t %1d", n_bit_t); + o = n_bit_t[0]; + n_bit_t++; + endfunction - int n_logic_t = 0; - function void e_logic_t(output logic_t o); - $display("e_logic_t %1d", n_logic_t); - o = ~n_logic_t[0]; - n_logic_t++; - endfunction + int n_logic_t = 0; + function void e_logic_t(output logic_t o); + $display("e_logic_t %1d", n_logic_t); + o = ~n_logic_t[0]; + n_logic_t++; + endfunction - // 2-state packed arrays - int n_array_2_state_1 = 0; - function void e_array_2_state_1(output bit [ 0:0] o); - $display("e_array_2_state_1 %1d", n_array_2_state_1); - o = n_array_2_state_1[0]; - n_array_2_state_1++; - endfunction + // 2-state packed arrays + int n_array_2_state_1 = 0; + function void e_array_2_state_1(output bit [ 0:0] o); + $display("e_array_2_state_1 %1d", n_array_2_state_1); + o = n_array_2_state_1[0]; + n_array_2_state_1++; + endfunction - int n_array_2_state_32 = 0; - function void e_array_2_state_32(output bit [31:0] o); - $display("e_array_2_state_32 %1d", n_array_2_state_32); - o = ~32'd0 >> n_array_2_state_32; - n_array_2_state_32++; - endfunction + int n_array_2_state_32 = 0; + function void e_array_2_state_32(output bit [31:0] o); + $display("e_array_2_state_32 %1d", n_array_2_state_32); + o = ~32'd0 >> n_array_2_state_32; + n_array_2_state_32++; + endfunction - int n_array_2_state_33 = 0; - function void e_array_2_state_33(output bit [32:0] o); - $display("e_array_2_state_33 %1d", n_array_2_state_33); - o = ~33'd0 >> n_array_2_state_33; - n_array_2_state_33++; - endfunction + int n_array_2_state_33 = 0; + function void e_array_2_state_33(output bit [32:0] o); + $display("e_array_2_state_33 %1d", n_array_2_state_33); + o = ~33'd0 >> n_array_2_state_33; + n_array_2_state_33++; + endfunction - int n_array_2_state_64 = 0; - function void e_array_2_state_64(output bit [63:0] o); - $display("e_array_2_state_64 %1d", n_array_2_state_64); - o = ~64'd0 >> n_array_2_state_64; - n_array_2_state_64++; - endfunction + int n_array_2_state_64 = 0; + function void e_array_2_state_64(output bit [63:0] o); + $display("e_array_2_state_64 %1d", n_array_2_state_64); + o = ~64'd0 >> n_array_2_state_64; + n_array_2_state_64++; + endfunction - int n_array_2_state_65 = 0; - function void e_array_2_state_65(output bit [64:0] o); - $display("e_array_2_state_65 %1d", n_array_2_state_65); - o = ~65'd0 >> n_array_2_state_65; - n_array_2_state_65++; - endfunction + int n_array_2_state_65 = 0; + function void e_array_2_state_65(output bit [64:0] o); + $display("e_array_2_state_65 %1d", n_array_2_state_65); + o = ~65'd0 >> n_array_2_state_65; + n_array_2_state_65++; + endfunction - int n_array_2_state_128 = 0; - function void e_array_2_state_128(output bit [127:0] o); - $display("e_array_2_state_128 %1d", n_array_2_state_128); - o = ~128'd0 >> n_array_2_state_128; - n_array_2_state_128++; - endfunction + int n_array_2_state_128 = 0; + function void e_array_2_state_128(output bit [127:0] o); + $display("e_array_2_state_128 %1d", n_array_2_state_128); + o = ~128'd0 >> n_array_2_state_128; + n_array_2_state_128++; + endfunction - // 2-state packed structures - int n_struct_2_state_1 = 0; - function void e_struct_2_state_1(output struct_2_state_1 o); - $display("e_struct_2_state_1 %1d", n_struct_2_state_1); - o = n_struct_2_state_1[0]; - n_struct_2_state_1++; - endfunction + // 2-state packed structures + int n_struct_2_state_1 = 0; + function void e_struct_2_state_1(output struct_2_state_1 o); + $display("e_struct_2_state_1 %1d", n_struct_2_state_1); + o = n_struct_2_state_1[0]; + n_struct_2_state_1++; + endfunction - int n_struct_2_state_32 = 0; - function void e_struct_2_state_32(output struct_2_state_32 o); - $display("e_struct_2_state_32 %1d", n_struct_2_state_32); - o = ~32'd0 >> n_struct_2_state_32; - n_struct_2_state_32++; - endfunction + int n_struct_2_state_32 = 0; + function void e_struct_2_state_32(output struct_2_state_32 o); + $display("e_struct_2_state_32 %1d", n_struct_2_state_32); + o = ~32'd0 >> n_struct_2_state_32; + n_struct_2_state_32++; + endfunction - int n_struct_2_state_33 = 0; - function void e_struct_2_state_33(output struct_2_state_33 o); - $display("e_struct_2_state_33 %1d", n_struct_2_state_33); - o = ~33'd0 >> n_struct_2_state_33; - n_struct_2_state_33++; - endfunction + int n_struct_2_state_33 = 0; + function void e_struct_2_state_33(output struct_2_state_33 o); + $display("e_struct_2_state_33 %1d", n_struct_2_state_33); + o = ~33'd0 >> n_struct_2_state_33; + n_struct_2_state_33++; + endfunction - int n_struct_2_state_64 = 0; - function void e_struct_2_state_64(output struct_2_state_64 o); - $display("e_struct_2_state_64 %1d", n_struct_2_state_64); - o = ~64'd0 >> n_struct_2_state_64; - n_struct_2_state_64++; - endfunction + int n_struct_2_state_64 = 0; + function void e_struct_2_state_64(output struct_2_state_64 o); + $display("e_struct_2_state_64 %1d", n_struct_2_state_64); + o = ~64'd0 >> n_struct_2_state_64; + n_struct_2_state_64++; + endfunction - int n_struct_2_state_65 = 0; - function void e_struct_2_state_65(output struct_2_state_65 o); - $display("e_struct_2_state_65 %1d", n_struct_2_state_65); - o = ~65'd0 >> n_struct_2_state_65; - n_struct_2_state_65++; - endfunction + int n_struct_2_state_65 = 0; + function void e_struct_2_state_65(output struct_2_state_65 o); + $display("e_struct_2_state_65 %1d", n_struct_2_state_65); + o = ~65'd0 >> n_struct_2_state_65; + n_struct_2_state_65++; + endfunction - int n_struct_2_state_128 = 0; - function void e_struct_2_state_128(output struct_2_state_128 o); - $display("e_struct_2_state_128 %1d", n_struct_2_state_128); - o = ~128'd0 >> n_struct_2_state_128; - n_struct_2_state_128++; - endfunction + int n_struct_2_state_128 = 0; + function void e_struct_2_state_128(output struct_2_state_128 o); + $display("e_struct_2_state_128 %1d", n_struct_2_state_128); + o = ~128'd0 >> n_struct_2_state_128; + n_struct_2_state_128++; + endfunction - // 2-state packed unions - int n_union_2_state_1 = 0; - function void e_union_2_state_1(output union_2_state_1 o); - $display("e_union_2_state_1 %1d", n_union_2_state_1); - o = n_union_2_state_1[0]; - n_union_2_state_1++; - endfunction + // 2-state packed unions + int n_union_2_state_1 = 0; + function void e_union_2_state_1(output union_2_state_1 o); + $display("e_union_2_state_1 %1d", n_union_2_state_1); + o = n_union_2_state_1[0]; + n_union_2_state_1++; + endfunction - int n_union_2_state_32 = 0; - function void e_union_2_state_32(output union_2_state_32 o); - $display("e_union_2_state_32 %1d", n_union_2_state_32); - o = ~32'd0 >> n_union_2_state_32; - n_union_2_state_32++; - endfunction + int n_union_2_state_32 = 0; + function void e_union_2_state_32(output union_2_state_32 o); + $display("e_union_2_state_32 %1d", n_union_2_state_32); + o = ~32'd0 >> n_union_2_state_32; + n_union_2_state_32++; + endfunction - int n_union_2_state_33 = 0; - function void e_union_2_state_33(output union_2_state_33 o); - $display("e_union_2_state_33 %1d", n_union_2_state_33); - o = ~33'd0 >> n_union_2_state_33; - n_union_2_state_33++; - endfunction + int n_union_2_state_33 = 0; + function void e_union_2_state_33(output union_2_state_33 o); + $display("e_union_2_state_33 %1d", n_union_2_state_33); + o = ~33'd0 >> n_union_2_state_33; + n_union_2_state_33++; + endfunction - int n_union_2_state_64 = 0; - function void e_union_2_state_64(output union_2_state_64 o); - $display("e_union_2_state_64 %1d", n_union_2_state_64); - o = ~64'd0 >> n_union_2_state_64; - n_union_2_state_64++; - endfunction + int n_union_2_state_64 = 0; + function void e_union_2_state_64(output union_2_state_64 o); + $display("e_union_2_state_64 %1d", n_union_2_state_64); + o = ~64'd0 >> n_union_2_state_64; + n_union_2_state_64++; + endfunction - int n_union_2_state_65 = 0; - function void e_union_2_state_65(output union_2_state_65 o); - $display("e_union_2_state_65 %1d", n_union_2_state_65); - o = ~65'd0 >> n_union_2_state_65; - n_union_2_state_65++; - endfunction + int n_union_2_state_65 = 0; + function void e_union_2_state_65(output union_2_state_65 o); + $display("e_union_2_state_65 %1d", n_union_2_state_65); + o = ~65'd0 >> n_union_2_state_65; + n_union_2_state_65++; + endfunction - int n_union_2_state_128 = 0; - function void e_union_2_state_128(output union_2_state_128 o); - $display("e_union_2_state_128 %1d", n_union_2_state_128); - o = ~128'd0 >> n_union_2_state_128; - n_union_2_state_128++; - endfunction + int n_union_2_state_128 = 0; + function void e_union_2_state_128(output union_2_state_128 o); + $display("e_union_2_state_128 %1d", n_union_2_state_128); + o = ~128'd0 >> n_union_2_state_128; + n_union_2_state_128++; + endfunction - // 4-state packed arrays - int n_array_4_state_1 = 0; - function void e_array_4_state_1(output logic [ 0:0] o); - $display("e_array_4_state_1 %1d", n_array_4_state_1); - o = n_array_4_state_1[0]; - n_array_4_state_1++; - endfunction + // 4-state packed arrays + int n_array_4_state_1 = 0; + function void e_array_4_state_1(output logic [ 0:0] o); + $display("e_array_4_state_1 %1d", n_array_4_state_1); + o = n_array_4_state_1[0]; + n_array_4_state_1++; + endfunction - int n_array_4_state_32 = 0; - function void e_array_4_state_32(output logic [31:0] o); - $display("e_array_4_state_32 %1d", n_array_4_state_32); - o = ~32'd0 >> n_array_4_state_32; - n_array_4_state_32++; - endfunction + int n_array_4_state_32 = 0; + function void e_array_4_state_32(output logic [31:0] o); + $display("e_array_4_state_32 %1d", n_array_4_state_32); + o = ~32'd0 >> n_array_4_state_32; + n_array_4_state_32++; + endfunction - int n_array_4_state_33 = 0; - function void e_array_4_state_33(output logic [32:0] o); - $display("e_array_4_state_33 %1d", n_array_4_state_33); - o = ~33'd0 >> n_array_4_state_33; - n_array_4_state_33++; - endfunction + int n_array_4_state_33 = 0; + function void e_array_4_state_33(output logic [32:0] o); + $display("e_array_4_state_33 %1d", n_array_4_state_33); + o = ~33'd0 >> n_array_4_state_33; + n_array_4_state_33++; + endfunction - int n_array_4_state_64 = 0; - function void e_array_4_state_64(output logic [63:0] o); - $display("e_array_4_state_64 %1d", n_array_4_state_64); - o = ~64'd0 >> n_array_4_state_64; - n_array_4_state_64++; - endfunction + int n_array_4_state_64 = 0; + function void e_array_4_state_64(output logic [63:0] o); + $display("e_array_4_state_64 %1d", n_array_4_state_64); + o = ~64'd0 >> n_array_4_state_64; + n_array_4_state_64++; + endfunction - int n_array_4_state_65 = 0; - function void e_array_4_state_65(output logic [64:0] o); - $display("e_array_4_state_65 %1d", n_array_4_state_65); - o = ~65'd0 >> n_array_4_state_65; - n_array_4_state_65++; - endfunction + int n_array_4_state_65 = 0; + function void e_array_4_state_65(output logic [64:0] o); + $display("e_array_4_state_65 %1d", n_array_4_state_65); + o = ~65'd0 >> n_array_4_state_65; + n_array_4_state_65++; + endfunction - int n_array_4_state_128 = 0; - function void e_array_4_state_128(output logic [127:0] o); - $display("e_array_4_state_128 %1d", n_array_4_state_128); - o = ~128'd0 >> n_array_4_state_128; - n_array_4_state_128++; - endfunction + int n_array_4_state_128 = 0; + function void e_array_4_state_128(output logic [127:0] o); + $display("e_array_4_state_128 %1d", n_array_4_state_128); + o = ~128'd0 >> n_array_4_state_128; + n_array_4_state_128++; + endfunction - // 4-state packed structures - int n_struct_4_state_1 = 0; - function void e_struct_4_state_1(output struct_4_state_1 o); - $display("e_struct_4_state_1 %1d", n_struct_4_state_1); - o = n_struct_4_state_1[0]; - n_struct_4_state_1++; - endfunction + // 4-state packed structures + int n_struct_4_state_1 = 0; + function void e_struct_4_state_1(output struct_4_state_1 o); + $display("e_struct_4_state_1 %1d", n_struct_4_state_1); + o = n_struct_4_state_1[0]; + n_struct_4_state_1++; + endfunction - int n_struct_4_state_32 = 0; - function void e_struct_4_state_32(output struct_4_state_32 o); - $display("e_struct_4_state_32 %1d", n_struct_4_state_32); - o = ~32'd0 >> n_struct_4_state_32; - n_struct_4_state_32++; - endfunction + int n_struct_4_state_32 = 0; + function void e_struct_4_state_32(output struct_4_state_32 o); + $display("e_struct_4_state_32 %1d", n_struct_4_state_32); + o = ~32'd0 >> n_struct_4_state_32; + n_struct_4_state_32++; + endfunction - int n_struct_4_state_33 = 0; - function void e_struct_4_state_33(output struct_4_state_33 o); - $display("e_struct_4_state_33 %1d", n_struct_4_state_33); - o = ~33'd0 >> n_struct_4_state_33; - n_struct_4_state_33++; - endfunction + int n_struct_4_state_33 = 0; + function void e_struct_4_state_33(output struct_4_state_33 o); + $display("e_struct_4_state_33 %1d", n_struct_4_state_33); + o = ~33'd0 >> n_struct_4_state_33; + n_struct_4_state_33++; + endfunction - int n_struct_4_state_64 = 0; - function void e_struct_4_state_64(output struct_4_state_64 o); - $display("e_struct_4_state_64 %1d", n_struct_4_state_64); - o = ~64'd0 >> n_struct_4_state_64; - n_struct_4_state_64++; - endfunction + int n_struct_4_state_64 = 0; + function void e_struct_4_state_64(output struct_4_state_64 o); + $display("e_struct_4_state_64 %1d", n_struct_4_state_64); + o = ~64'd0 >> n_struct_4_state_64; + n_struct_4_state_64++; + endfunction - int n_struct_4_state_65 = 0; - function void e_struct_4_state_65(output struct_4_state_65 o); - $display("e_struct_4_state_65 %1d", n_struct_4_state_65); - o = ~65'd0 >> n_struct_4_state_65; - n_struct_4_state_65++; - endfunction + int n_struct_4_state_65 = 0; + function void e_struct_4_state_65(output struct_4_state_65 o); + $display("e_struct_4_state_65 %1d", n_struct_4_state_65); + o = ~65'd0 >> n_struct_4_state_65; + n_struct_4_state_65++; + endfunction - int n_struct_4_state_128 = 0; - function void e_struct_4_state_128(output struct_4_state_128 o); - $display("e_struct_4_state_128 %1d", n_struct_4_state_128); - o = ~128'd0 >> n_struct_4_state_128; - n_struct_4_state_128++; - endfunction + int n_struct_4_state_128 = 0; + function void e_struct_4_state_128(output struct_4_state_128 o); + $display("e_struct_4_state_128 %1d", n_struct_4_state_128); + o = ~128'd0 >> n_struct_4_state_128; + n_struct_4_state_128++; + endfunction - // 4-state packed unions - int n_union_4_state_1 = 0; - function void e_union_4_state_1(output union_4_state_1 o); - $display("e_union_4_state_1 %1d", n_union_4_state_1); - o = n_union_4_state_1[0]; - n_union_4_state_1++; - endfunction + // 4-state packed unions + int n_union_4_state_1 = 0; + function void e_union_4_state_1(output union_4_state_1 o); + $display("e_union_4_state_1 %1d", n_union_4_state_1); + o = n_union_4_state_1[0]; + n_union_4_state_1++; + endfunction - int n_union_4_state_32 = 0; - function void e_union_4_state_32(output union_4_state_32 o); - $display("e_union_4_state_32 %1d", n_union_4_state_32); - o = ~32'd0 >> n_union_4_state_32; - n_union_4_state_32++; - endfunction + int n_union_4_state_32 = 0; + function void e_union_4_state_32(output union_4_state_32 o); + $display("e_union_4_state_32 %1d", n_union_4_state_32); + o = ~32'd0 >> n_union_4_state_32; + n_union_4_state_32++; + endfunction - int n_union_4_state_33 = 0; - function void e_union_4_state_33(output union_4_state_33 o); - $display("e_union_4_state_33 %1d", n_union_4_state_33); - o = ~33'd0 >> n_union_4_state_33; - n_union_4_state_33++; - endfunction + int n_union_4_state_33 = 0; + function void e_union_4_state_33(output union_4_state_33 o); + $display("e_union_4_state_33 %1d", n_union_4_state_33); + o = ~33'd0 >> n_union_4_state_33; + n_union_4_state_33++; + endfunction - int n_union_4_state_64 = 0; - function void e_union_4_state_64(output union_4_state_64 o); - $display("e_union_4_state_64 %1d", n_union_4_state_64); - o = ~64'd0 >> n_union_4_state_64; - n_union_4_state_64++; - endfunction + int n_union_4_state_64 = 0; + function void e_union_4_state_64(output union_4_state_64 o); + $display("e_union_4_state_64 %1d", n_union_4_state_64); + o = ~64'd0 >> n_union_4_state_64; + n_union_4_state_64++; + endfunction - int n_union_4_state_65 = 0; - function void e_union_4_state_65(output union_4_state_65 o); - $display("e_union_4_state_65 %1d", n_union_4_state_65); - o = ~65'd0 >> n_union_4_state_65; - n_union_4_state_65++; - endfunction + int n_union_4_state_65 = 0; + function void e_union_4_state_65(output union_4_state_65 o); + $display("e_union_4_state_65 %1d", n_union_4_state_65); + o = ~65'd0 >> n_union_4_state_65; + n_union_4_state_65++; + endfunction - int n_union_4_state_128 = 0; - function void e_union_4_state_128(output union_4_state_128 o); - $display("e_union_4_state_128 %1d", n_union_4_state_128); - o = ~128'd0 >> n_union_4_state_128; - n_union_4_state_128++; - endfunction + int n_union_4_state_128 = 0; + function void e_union_4_state_128(output union_4_state_128 o); + $display("e_union_4_state_128 %1d", n_union_4_state_128); + o = ~128'd0 >> n_union_4_state_128; + n_union_4_state_128++; + endfunction - //====================================================================== - // Invoke all functions 3 times (they have side effects) - //====================================================================== + //====================================================================== + // Invoke all functions 3 times (they have side effects) + //====================================================================== - import "DPI-C" context function void check_exports(); + import "DPI-C" context function void check_exports(); - initial begin - for (int i = 0 ; i < 3; i++) begin - // Check the imports + initial begin + for (int i = 0 ; i < 3; i++) begin + // Check the imports - byte x_byte; - byte unsigned x_byte_unsigned; - shortint x_shortint; - shortint unsigned x_shortint_unsigned; - int x_int; - int unsigned x_int_unsigned; - longint x_longint; - longint unsigned x_longint_unsigned; + byte x_byte; + byte unsigned x_byte_unsigned; + shortint x_shortint; + shortint unsigned x_shortint_unsigned; + int x_int; + int unsigned x_int_unsigned; + longint x_longint; + longint unsigned x_longint_unsigned; `ifndef NO_TIME - time x_time; + time x_time; `endif `ifndef NO_INTEGER - integer x_integer; + integer x_integer; `endif - real x_real; + real x_real; `ifndef NO_SHORTREAL - shortreal x_shortreal; + shortreal x_shortreal; `endif - chandle x_chandle; - string x_string; - bit x_bit; - logic x_logic; + chandle x_chandle; + string x_string; + bit x_bit; + logic x_logic; - byte_t x_byte_t; - byte_unsigned_t x_byte_unsigned_t; - shortint_t x_shortint_t; - shortint_unsigned_t x_shortint_unsigned_t; - int_t x_int_t; - int_unsigned_t x_int_unsigned_t; - longint_t x_longint_t; - longint_unsigned_t x_longint_unsigned_t; + byte_t x_byte_t; + byte_unsigned_t x_byte_unsigned_t; + shortint_t x_shortint_t; + shortint_unsigned_t x_shortint_unsigned_t; + int_t x_int_t; + int_unsigned_t x_int_unsigned_t; + longint_t x_longint_t; + longint_unsigned_t x_longint_unsigned_t; `ifndef NO_TIME - time_t x_time_t; + time_t x_time_t; `endif `ifndef NO_INTEGER - integer_t x_integer_t; + integer_t x_integer_t; `endif - real_t x_real_t; + real_t x_real_t; `ifndef NO_SHORTREAL - shortreal_t x_shortreal_t; + shortreal_t x_shortreal_t; `endif - chandle_t x_chandle_t; - string_t x_string_t; - bit_t x_bit_t; - logic_t x_logic_t; + chandle_t x_chandle_t; + string_t x_string_t; + bit_t x_bit_t; + logic_t x_logic_t; - bit [ 0:0] x_bit_1; - bit [ 31:0] x_bit_32; - bit [ 32:0] x_bit_33; - bit [ 63:0] x_bit_64; - bit [ 64:0] x_bit_65; - bit [127:0] x_bit_128; + bit [ 0:0] x_bit_1; + bit [ 31:0] x_bit_32; + bit [ 32:0] x_bit_33; + bit [ 63:0] x_bit_64; + bit [ 64:0] x_bit_65; + bit [127:0] x_bit_128; - struct_2_state_1 x_struct_2_state_1; - struct_2_state_32 x_struct_2_state_32; - struct_2_state_33 x_struct_2_state_33; - struct_2_state_64 x_struct_2_state_64; - struct_2_state_65 x_struct_2_state_65; - struct_2_state_128 x_struct_2_state_128; + struct_2_state_1 x_struct_2_state_1; + struct_2_state_32 x_struct_2_state_32; + struct_2_state_33 x_struct_2_state_33; + struct_2_state_64 x_struct_2_state_64; + struct_2_state_65 x_struct_2_state_65; + struct_2_state_128 x_struct_2_state_128; - union_2_state_1 x_union_2_state_1; - union_2_state_32 x_union_2_state_32; - union_2_state_33 x_union_2_state_33; - union_2_state_64 x_union_2_state_64; - union_2_state_65 x_union_2_state_65; - union_2_state_128 x_union_2_state_128; + union_2_state_1 x_union_2_state_1; + union_2_state_32 x_union_2_state_32; + union_2_state_33 x_union_2_state_33; + union_2_state_64 x_union_2_state_64; + union_2_state_65 x_union_2_state_65; + union_2_state_128 x_union_2_state_128; - logic [ 0:0] x_logic_1; - logic [ 31:0] x_logic_32; - logic [ 32:0] x_logic_33; - logic [ 63:0] x_logic_64; - logic [ 64:0] x_logic_65; - logic [127:0] x_logic_128; + logic [ 0:0] x_logic_1; + logic [ 31:0] x_logic_32; + logic [ 32:0] x_logic_33; + logic [ 63:0] x_logic_64; + logic [ 64:0] x_logic_65; + logic [127:0] x_logic_128; - struct_4_state_1 x_struct_4_state_1; - struct_4_state_32 x_struct_4_state_32; - struct_4_state_33 x_struct_4_state_33; - struct_4_state_64 x_struct_4_state_64; - struct_4_state_65 x_struct_4_state_65; - struct_4_state_128 x_struct_4_state_128; + struct_4_state_1 x_struct_4_state_1; + struct_4_state_32 x_struct_4_state_32; + struct_4_state_33 x_struct_4_state_33; + struct_4_state_64 x_struct_4_state_64; + struct_4_state_65 x_struct_4_state_65; + struct_4_state_128 x_struct_4_state_128; - union_4_state_1 x_union_4_state_1; - union_4_state_32 x_union_4_state_32; - union_4_state_33 x_union_4_state_33; - union_4_state_64 x_union_4_state_64; - union_4_state_65 x_union_4_state_65; - union_4_state_128 x_union_4_state_128; + union_4_state_1 x_union_4_state_1; + union_4_state_32 x_union_4_state_32; + union_4_state_33 x_union_4_state_33; + union_4_state_64 x_union_4_state_64; + union_4_state_65 x_union_4_state_65; + union_4_state_128 x_union_4_state_128; - // Basic types as per IEEE 1800-2023 35.5.6 - i_byte(x_byte); if (x_byte !== 8'd10 - 8'(i)) $stop; - i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd20 - 8'(i)) $stop; - i_shortint(x_shortint); if (x_shortint !== 16'd30 - 16'(i)) $stop; - i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd40 - 16'(i)) $stop; - i_int(x_int); if (x_int !== 32'd50 - 32'(i)) $stop; - i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd60 - 32'(i)) $stop; - i_longint(x_longint); if (x_longint !== 64'd70 - 64'(i)) $stop; - i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd80 - 64'(i)) $stop; + // Basic types as per IEEE 1800-2023 35.5.6 + i_byte(x_byte); if (x_byte !== 8'd10 - 8'(i)) $stop; + i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd20 - 8'(i)) $stop; + i_shortint(x_shortint); if (x_shortint !== 16'd30 - 16'(i)) $stop; + i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd40 - 16'(i)) $stop; + i_int(x_int); if (x_int !== 32'd50 - 32'(i)) $stop; + i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd60 - 32'(i)) $stop; + i_longint(x_longint); if (x_longint !== 64'd70 - 64'(i)) $stop; + i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd80 - 64'(i)) $stop; `ifndef NO_TIME - i_time(x_time); if (x_time !== 64'd90 - 64'(i)) $stop; + i_time(x_time); if (x_time !== 64'd90 - 64'(i)) $stop; `endif `ifndef NO_INTEGER - i_integer(x_integer); if (x_integer !== 32'd100- 32'(i)) $stop; + i_integer(x_integer); if (x_integer !== 32'd100- 32'(i)) $stop; `endif - i_real(x_real); if (x_real != -1.0*i - 0.5 ) $stop; + i_real(x_real); if (x_real != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL - i_shortreal(x_shortreal); if (x_shortreal != -1.0*i - 0.25) $stop; + i_shortreal(x_shortreal); if (x_shortreal != -1.0*i - 0.25) $stop; `endif - if (~i[0]) begin - i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; - i_string(x_string); if (x_string != "World") $stop; - end else begin - i_chandle(x_chandle); if (x_chandle === `NULL) $stop; - i_string(x_string); if (x_string != "Hello") $stop; - end - i_bit(x_bit); if (x_bit !== ~i[0]) $stop; - i_logic(x_logic); if (x_logic !== i[0]) $stop; - - // Basic types via typedefs - i_byte_t(x_byte_t); if (x_byte_t !== 8'd10 - 8'(2*i)) $stop; - i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd20 - 8'(2*i)) $stop; - i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd30 - 16'(2*i)) $stop; - i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd40 - 16'(2*i)) $stop; - i_int_t(x_int_t); if (x_int_t !== 32'd50 - 32'(2*i)) $stop; - i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd60 - 32'(2*i)) $stop; - i_longint_t(x_longint_t); if (x_longint_t !== 64'd70 - 64'(2*i)) $stop; - i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd80 - 64'(2*i)) $stop; -`ifndef NO_TIME - i_time_t(x_time_t); if (x_time_t !== 64'd90 - 64'(2*i)) $stop; -`endif -`ifndef NO_INTEGER - i_integer_t(x_integer_t); if (x_integer_t !== 32'd100- 32'(2*i)) $stop; -`endif - i_real_t(x_real_t); if (x_real_t != -1.0*(2*i) - 0.5 ) $stop; -`ifndef NO_SHORTREAL - i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -1.0*(2*i) - 0.25) $stop; -`endif - if (~i[0]) begin - i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; - i_string_t(x_string_t); if (x_string_t != "World") $stop; - end else begin - i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; - i_string_t(x_string_t); if (x_string_t != "Hello") $stop; - end - i_bit_t(x_bit_t); if (x_bit_t !== ~i[0]) $stop; - i_logic_t(x_logic_t); if (x_logic_t !== i[0]) $stop; - - // 2-state packed arrays - i_array_2_state_1(x_bit_1); if (x_bit_1 !== ~i[0] ) $stop; - i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 << i) $stop; - i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 << i) $stop; - i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 << i) $stop; - i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 << i) $stop; - i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0<< i) $stop; - - // 2-state packed structures - i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== ~i[0] ) $stop; - i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 << i) $stop; - i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 << i) $stop; - i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 << i) $stop; - i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 << i) $stop; - i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128 !== ~128'd0<< i) $stop; - - // 2-state packed unions - i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== ~i[0] ) $stop; - i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 << i) $stop; - i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 << i) $stop; - i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 << i) $stop; - i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 << i) $stop; - i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0<< i) $stop; - - // 4-state packed arrays - i_array_4_state_1(x_logic_1); if (x_logic_1 !== ~i[0] ) $stop; - i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 << i) $stop; - i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 << i) $stop; - i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 << i) $stop; - i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 << i) $stop; - i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0<< i) $stop; - - // 4-state packed structures - i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== ~i[0] ) $stop; - i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 << i) $stop; - i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 << i) $stop; - i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 << i) $stop; - i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 << i) $stop; - i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128 !== ~128'd0<< i) $stop; - - // 4-state packed unions - i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== ~i[0] ) $stop; - i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 << i) $stop; - i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 << i) $stop; - i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 << i) $stop; - i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 << i) $stop; - i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0<< i) $stop; - - // Check the exports - check_exports(); + if (~i[0]) begin + i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; + i_string(x_string); if (x_string != "World") $stop; + end else begin + i_chandle(x_chandle); if (x_chandle === `NULL) $stop; + i_string(x_string); if (x_string != "Hello") $stop; end + i_bit(x_bit); if (x_bit !== ~i[0]) $stop; + i_logic(x_logic); if (x_logic !== i[0]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + // Basic types via typedefs + i_byte_t(x_byte_t); if (x_byte_t !== 8'd10 - 8'(2*i)) $stop; + i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd20 - 8'(2*i)) $stop; + i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd30 - 16'(2*i)) $stop; + i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd40 - 16'(2*i)) $stop; + i_int_t(x_int_t); if (x_int_t !== 32'd50 - 32'(2*i)) $stop; + i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd60 - 32'(2*i)) $stop; + i_longint_t(x_longint_t); if (x_longint_t !== 64'd70 - 64'(2*i)) $stop; + i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd80 - 64'(2*i)) $stop; +`ifndef NO_TIME + i_time_t(x_time_t); if (x_time_t !== 64'd90 - 64'(2*i)) $stop; +`endif +`ifndef NO_INTEGER + i_integer_t(x_integer_t); if (x_integer_t !== 32'd100- 32'(2*i)) $stop; +`endif + i_real_t(x_real_t); if (x_real_t != -1.0*(2*i) - 0.5 ) $stop; +`ifndef NO_SHORTREAL + i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -1.0*(2*i) - 0.25) $stop; +`endif + if (~i[0]) begin + i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; + i_string_t(x_string_t); if (x_string_t != "World") $stop; + end else begin + i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; + i_string_t(x_string_t); if (x_string_t != "Hello") $stop; + end + i_bit_t(x_bit_t); if (x_bit_t !== ~i[0]) $stop; + i_logic_t(x_logic_t); if (x_logic_t !== i[0]) $stop; + + // 2-state packed arrays + i_array_2_state_1(x_bit_1); if (x_bit_1 !== ~i[0] ) $stop; + i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 << i) $stop; + i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 << i) $stop; + i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 << i) $stop; + i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 << i) $stop; + i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0<< i) $stop; + + // 2-state packed structures + i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== ~i[0] ) $stop; + i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 << i) $stop; + i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 << i) $stop; + i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 << i) $stop; + i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 << i) $stop; + i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128 !== ~128'd0<< i) $stop; + + // 2-state packed unions + i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== ~i[0] ) $stop; + i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 << i) $stop; + i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 << i) $stop; + i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 << i) $stop; + i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 << i) $stop; + i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0<< i) $stop; + + // 4-state packed arrays + i_array_4_state_1(x_logic_1); if (x_logic_1 !== ~i[0] ) $stop; + i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 << i) $stop; + i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 << i) $stop; + i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 << i) $stop; + i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 << i) $stop; + i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0<< i) $stop; + + // 4-state packed structures + i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== ~i[0] ) $stop; + i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 << i) $stop; + i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 << i) $stop; + i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 << i) $stop; + i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 << i) $stop; + i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128 !== ~128'd0<< i) $stop; + + // 4-state packed unions + i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== ~i[0] ) $stop; + i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 << i) $stop; + i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 << i) $stop; + i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 << i) $stop; + i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 << i) $stop; + i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0<< i) $stop; + + // Check the exports + check_exports(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_arg_output_unpack.v b/test_regress/t/t_dpi_arg_output_unpack.v index a513fab83..f9d0acdaf 100644 --- a/test_regress/t/t_dpi_arg_output_unpack.v +++ b/test_regress/t/t_dpi_arg_output_unpack.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -32,13 +33,13 @@ `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ - end else begin \ - $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ - int'(exp), \ - int'(act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ + end else begin \ + $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ + int'(exp), \ + int'(act), `__LINE__); \ + $stop; \ + end `define CHECK_0D(val) \ `CHECK_VAL((val), 42) @@ -63,20 +64,20 @@ `CHECK_VAL(val[0][0][0], 54) `define CHECK_CHANDLE_VAL(act, exp) if ((act) == (exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ - end else begin \ - $display("Mismatch %s expected:%s but %s at %d", `"act`", \ - (exp) ? "null" : "non-null", (act) ? "null" : "non-null", `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ + end else begin \ + $display("Mismatch %s expected:%s but %s at %d", `"act`", \ + (exp) ? "null" : "non-null", (act) ? "null" : "non-null", `__LINE__); \ + $stop; \ + end `define CHECK_STRING_VAL(act, exp) if ((act) == (exp)) begin \ - if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ - end else begin \ - $display("Mismatch %s expected:%s actual:%s at %d", \ - `"act`", (exp), (act), `__LINE__); \ - $stop; \ - end + if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ + end else begin \ + $display("Mismatch %s expected:%s actual:%s at %d", \ + `"act`", (exp), (act), `__LINE__); \ + $stop; \ + end `define SET_VALUES(val) \ val[3][2][1] = 42; \ @@ -86,1182 +87,1182 @@ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 module t; - localparam ENABLE_VERBOSE_MESSAGE = 0; + localparam ENABLE_VERBOSE_MESSAGE = 0; - // Legal output argument types for DPI functions + // Legal output argument types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - typedef byte byte_array_t[4][3][2]; - typedef byte byte_array1_t[1][1][1]; - typedef byte unsigned byte_unsigned_array_t[4][3][2]; - typedef byte unsigned byte_unsigned_array1_t[1][1][1]; - typedef shortint shortint_array_t[4][3][2]; - typedef shortint shortint_array1_t[1][1][1]; - typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; - typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; - typedef int int_array_t[4][3][2]; - typedef int int_array1_t[1][1][1]; - typedef int unsigned int_unsigned_array_t[4][3][2]; - typedef int unsigned int_unsigned_array1_t[1][1][1]; - typedef longint longint_array_t[4][3][2]; - typedef longint longint_array1_t[1][1][1]; - typedef longint unsigned longint_unsigned_array_t[4][3][2]; - typedef longint unsigned longint_unsigned_array1_t[1][1][1]; + typedef byte byte_array_t[4][3][2]; + typedef byte byte_array1_t[1][1][1]; + typedef byte unsigned byte_unsigned_array_t[4][3][2]; + typedef byte unsigned byte_unsigned_array1_t[1][1][1]; + typedef shortint shortint_array_t[4][3][2]; + typedef shortint shortint_array1_t[1][1][1]; + typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; + typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; + typedef int int_array_t[4][3][2]; + typedef int int_array1_t[1][1][1]; + typedef int unsigned int_unsigned_array_t[4][3][2]; + typedef int unsigned int_unsigned_array1_t[1][1][1]; + typedef longint longint_array_t[4][3][2]; + typedef longint longint_array1_t[1][1][1]; + typedef longint unsigned longint_unsigned_array_t[4][3][2]; + typedef longint unsigned longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME - typedef time time_array_t[4][3][2]; - typedef time time_array1_t[1][1][1]; + typedef time time_array_t[4][3][2]; + typedef time time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER - typedef integer integer_array_t[4][3][2]; - typedef integer integer_array1_t[1][1][1]; + typedef integer integer_array_t[4][3][2]; + typedef integer integer_array1_t[1][1][1]; `endif - typedef real real_array_t[4][3][2]; - typedef real real_array1_t[1][1][1]; + typedef real real_array_t[4][3][2]; + typedef real real_array1_t[1][1][1]; `ifndef NO_SHORTREAL - typedef shortreal shortreal_array_t[4][3][2]; - typedef shortreal shortreal_array1_t[1][1][1]; + typedef shortreal shortreal_array_t[4][3][2]; + typedef shortreal shortreal_array1_t[1][1][1]; `endif - typedef chandle chandle_array_t[4][3][2]; - typedef chandle chandle_array1_t[1][1][1]; - typedef string string_array_t[4][3][2]; - typedef string string_array1_t[1][1][1]; - typedef bit bit1_array_t[4][3][2]; - typedef bit bit1_array1_t[1][1][1]; - typedef bit [6:0] bit7_array_t[4][3][2]; - typedef bit [6:0] bit7_array1_t[1][1][1]; - typedef bit [120:0] bit121_array_t[4][3][2]; - typedef bit [120:0] bit121_array1_t[1][1][1]; - typedef logic logic1_array_t[4][3][2]; - typedef logic logic1_array1_t[1][1][1]; - typedef logic [6:0] logic7_array_t[4][3][2]; - typedef logic [6:0] logic7_array1_t[1][1][1]; - typedef logic [120:0] logic121_array_t[4][3][2]; - typedef logic [120:0] logic121_array1_t[1][1][1]; + typedef chandle chandle_array_t[4][3][2]; + typedef chandle chandle_array1_t[1][1][1]; + typedef string string_array_t[4][3][2]; + typedef string string_array1_t[1][1][1]; + typedef bit bit1_array_t[4][3][2]; + typedef bit bit1_array1_t[1][1][1]; + typedef bit [6:0] bit7_array_t[4][3][2]; + typedef bit [6:0] bit7_array1_t[1][1][1]; + typedef bit [120:0] bit121_array_t[4][3][2]; + typedef bit [120:0] bit121_array1_t[1][1][1]; + typedef logic logic1_array_t[4][3][2]; + typedef logic logic1_array1_t[1][1][1]; + typedef logic [6:0] logic7_array_t[4][3][2]; + typedef logic [6:0] logic7_array1_t[1][1][1]; + typedef logic [120:0] logic121_array_t[4][3][2]; + typedef logic [120:0] logic121_array1_t[1][1][1]; - typedef struct packed { - logic [6:0] val; - } pack_struct_t; - typedef pack_struct_t pack_struct_array_t[4][3][2]; - typedef pack_struct_t pack_struct_array1_t[1][1][1]; + typedef struct packed { + logic [6:0] val; + } pack_struct_t; + typedef pack_struct_t pack_struct_array_t[4][3][2]; + typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT - typedef struct { - logic [120:0] val; - } unpack_struct_t; - typedef unpack_struct_t unpack_struct_array_t[4][3][2]; - typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; + typedef struct { + logic [120:0] val; + } unpack_struct_t; + typedef unpack_struct_t unpack_struct_array_t[4][3][2]; + typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Returns non-null pointer - import "DPI-C" function chandle get_non_null(); + // Returns non-null pointer + import "DPI-C" function chandle get_non_null(); - import "DPI-C" function void i_byte_0d(output byte val); - import "DPI-C" function void i_byte_1d(output byte val[2]); - import "DPI-C" function void i_byte_2d(output byte val[3][2]); - import "DPI-C" function void i_byte_3d(output byte_array_t val); - import "DPI-C" function void i_byte_1d1(output byte val[1]); - import "DPI-C" function void i_byte_2d1(output byte val[1][1]); - import "DPI-C" function void i_byte_3d1(output byte_array1_t val); + import "DPI-C" function void i_byte_0d(output byte val); + import "DPI-C" function void i_byte_1d(output byte val[2]); + import "DPI-C" function void i_byte_2d(output byte val[3][2]); + import "DPI-C" function void i_byte_3d(output byte_array_t val); + import "DPI-C" function void i_byte_1d1(output byte val[1]); + import "DPI-C" function void i_byte_2d1(output byte val[1][1]); + import "DPI-C" function void i_byte_3d1(output byte_array1_t val); - import "DPI-C" function void i_byte_unsigned_0d(output byte unsigned val); - import "DPI-C" function void i_byte_unsigned_1d(output byte unsigned val[2]); - import "DPI-C" function void i_byte_unsigned_2d(output byte unsigned val[3][2]); - import "DPI-C" function void i_byte_unsigned_3d(output byte_unsigned_array_t val); - import "DPI-C" function void i_byte_unsigned_1d1(output byte unsigned val[1]); - import "DPI-C" function void i_byte_unsigned_2d1(output byte unsigned val[1][1]); - import "DPI-C" function void i_byte_unsigned_3d1(output byte_unsigned_array1_t val); + import "DPI-C" function void i_byte_unsigned_0d(output byte unsigned val); + import "DPI-C" function void i_byte_unsigned_1d(output byte unsigned val[2]); + import "DPI-C" function void i_byte_unsigned_2d(output byte unsigned val[3][2]); + import "DPI-C" function void i_byte_unsigned_3d(output byte_unsigned_array_t val); + import "DPI-C" function void i_byte_unsigned_1d1(output byte unsigned val[1]); + import "DPI-C" function void i_byte_unsigned_2d1(output byte unsigned val[1][1]); + import "DPI-C" function void i_byte_unsigned_3d1(output byte_unsigned_array1_t val); - import "DPI-C" function void i_shortint_0d(output shortint val); - import "DPI-C" function void i_shortint_1d(output shortint val[2]); - import "DPI-C" function void i_shortint_2d(output shortint val[3][2]); - import "DPI-C" function void i_shortint_3d(output shortint_array_t val); - import "DPI-C" function void i_shortint_1d1(output shortint val[1]); - import "DPI-C" function void i_shortint_2d1(output shortint val[1][1]); - import "DPI-C" function void i_shortint_3d1(output shortint_array1_t val); + import "DPI-C" function void i_shortint_0d(output shortint val); + import "DPI-C" function void i_shortint_1d(output shortint val[2]); + import "DPI-C" function void i_shortint_2d(output shortint val[3][2]); + import "DPI-C" function void i_shortint_3d(output shortint_array_t val); + import "DPI-C" function void i_shortint_1d1(output shortint val[1]); + import "DPI-C" function void i_shortint_2d1(output shortint val[1][1]); + import "DPI-C" function void i_shortint_3d1(output shortint_array1_t val); - import "DPI-C" function void i_shortint_unsigned_0d(output shortint unsigned val); - import "DPI-C" function void i_shortint_unsigned_1d(output shortint unsigned val[2]); - import "DPI-C" function void i_shortint_unsigned_2d(output shortint unsigned val[3][2]); - import "DPI-C" function void i_shortint_unsigned_3d(output shortint_unsigned_array_t val); - import "DPI-C" function void i_shortint_unsigned_1d1(output shortint unsigned val[1]); - import "DPI-C" function void i_shortint_unsigned_2d1(output shortint unsigned val[1][1]); - import "DPI-C" function void i_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); + import "DPI-C" function void i_shortint_unsigned_0d(output shortint unsigned val); + import "DPI-C" function void i_shortint_unsigned_1d(output shortint unsigned val[2]); + import "DPI-C" function void i_shortint_unsigned_2d(output shortint unsigned val[3][2]); + import "DPI-C" function void i_shortint_unsigned_3d(output shortint_unsigned_array_t val); + import "DPI-C" function void i_shortint_unsigned_1d1(output shortint unsigned val[1]); + import "DPI-C" function void i_shortint_unsigned_2d1(output shortint unsigned val[1][1]); + import "DPI-C" function void i_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); - import "DPI-C" function void i_int_0d(output int val); - import "DPI-C" function void i_int_1d(output int val[2]); - import "DPI-C" function void i_int_2d(output int val[3][2]); - import "DPI-C" function void i_int_3d(output int_array_t val); - import "DPI-C" function void i_int_1d1(output int val[1]); - import "DPI-C" function void i_int_2d1(output int val[1][1]); - import "DPI-C" function void i_int_3d1(output int_array1_t val); + import "DPI-C" function void i_int_0d(output int val); + import "DPI-C" function void i_int_1d(output int val[2]); + import "DPI-C" function void i_int_2d(output int val[3][2]); + import "DPI-C" function void i_int_3d(output int_array_t val); + import "DPI-C" function void i_int_1d1(output int val[1]); + import "DPI-C" function void i_int_2d1(output int val[1][1]); + import "DPI-C" function void i_int_3d1(output int_array1_t val); - import "DPI-C" function void i_int_unsigned_0d(output int unsigned val); - import "DPI-C" function void i_int_unsigned_1d(output int unsigned val[2]); - import "DPI-C" function void i_int_unsigned_2d(output int unsigned val[3][2]); - import "DPI-C" function void i_int_unsigned_3d(output int_unsigned_array_t val); - import "DPI-C" function void i_int_unsigned_1d1(output int unsigned val[1]); - import "DPI-C" function void i_int_unsigned_2d1(output int unsigned val[1][1]); - import "DPI-C" function void i_int_unsigned_3d1(output int_unsigned_array1_t val); + import "DPI-C" function void i_int_unsigned_0d(output int unsigned val); + import "DPI-C" function void i_int_unsigned_1d(output int unsigned val[2]); + import "DPI-C" function void i_int_unsigned_2d(output int unsigned val[3][2]); + import "DPI-C" function void i_int_unsigned_3d(output int_unsigned_array_t val); + import "DPI-C" function void i_int_unsigned_1d1(output int unsigned val[1]); + import "DPI-C" function void i_int_unsigned_2d1(output int unsigned val[1][1]); + import "DPI-C" function void i_int_unsigned_3d1(output int_unsigned_array1_t val); - import "DPI-C" function void i_longint_0d(output longint val); - import "DPI-C" function void i_longint_1d(output longint val[2]); - import "DPI-C" function void i_longint_2d(output longint val[3][2]); - import "DPI-C" function void i_longint_3d(output longint_array_t val); - import "DPI-C" function void i_longint_1d1(output longint val[1]); - import "DPI-C" function void i_longint_2d1(output longint val[1][1]); - import "DPI-C" function void i_longint_3d1(output longint_array1_t val); + import "DPI-C" function void i_longint_0d(output longint val); + import "DPI-C" function void i_longint_1d(output longint val[2]); + import "DPI-C" function void i_longint_2d(output longint val[3][2]); + import "DPI-C" function void i_longint_3d(output longint_array_t val); + import "DPI-C" function void i_longint_1d1(output longint val[1]); + import "DPI-C" function void i_longint_2d1(output longint val[1][1]); + import "DPI-C" function void i_longint_3d1(output longint_array1_t val); - import "DPI-C" function void i_longint_unsigned_0d(output longint unsigned val); - import "DPI-C" function void i_longint_unsigned_1d(output longint unsigned val[2]); - import "DPI-C" function void i_longint_unsigned_2d(output longint unsigned val[3][2]); - import "DPI-C" function void i_longint_unsigned_3d(output longint_unsigned_array_t val); - import "DPI-C" function void i_longint_unsigned_1d1(output longint unsigned val[1]); - import "DPI-C" function void i_longint_unsigned_2d1(output longint unsigned val[1][1]); - import "DPI-C" function void i_longint_unsigned_3d1(output longint_unsigned_array1_t val); + import "DPI-C" function void i_longint_unsigned_0d(output longint unsigned val); + import "DPI-C" function void i_longint_unsigned_1d(output longint unsigned val[2]); + import "DPI-C" function void i_longint_unsigned_2d(output longint unsigned val[3][2]); + import "DPI-C" function void i_longint_unsigned_3d(output longint_unsigned_array_t val); + import "DPI-C" function void i_longint_unsigned_1d1(output longint unsigned val[1]); + import "DPI-C" function void i_longint_unsigned_2d1(output longint unsigned val[1][1]); + import "DPI-C" function void i_longint_unsigned_3d1(output longint_unsigned_array1_t val); `ifndef NO_TIME - import "DPI-C" function void i_time_0d(output time val); - import "DPI-C" function void i_time_1d(output time val[2]); - import "DPI-C" function void i_time_2d(output time val[3][2]); - import "DPI-C" function void i_time_3d(output time_array_t val); - import "DPI-C" function void i_time_1d1(output time val[1]); - import "DPI-C" function void i_time_2d1(output time val[1][1]); - import "DPI-C" function void i_time_3d1(output time_array1_t val); + import "DPI-C" function void i_time_0d(output time val); + import "DPI-C" function void i_time_1d(output time val[2]); + import "DPI-C" function void i_time_2d(output time val[3][2]); + import "DPI-C" function void i_time_3d(output time_array_t val); + import "DPI-C" function void i_time_1d1(output time val[1]); + import "DPI-C" function void i_time_2d1(output time val[1][1]); + import "DPI-C" function void i_time_3d1(output time_array1_t val); `endif `ifndef NO_INTEGER - import "DPI-C" function void i_integer_0d(output integer val); - import "DPI-C" function void i_integer_1d(output integer val[2]); - import "DPI-C" function void i_integer_2d(output integer val[3][2]); - import "DPI-C" function void i_integer_3d(output integer_array_t val); - import "DPI-C" function void i_integer_1d1(output integer val[1]); - import "DPI-C" function void i_integer_2d1(output integer val[1][1]); - import "DPI-C" function void i_integer_3d1(output integer_array1_t val); + import "DPI-C" function void i_integer_0d(output integer val); + import "DPI-C" function void i_integer_1d(output integer val[2]); + import "DPI-C" function void i_integer_2d(output integer val[3][2]); + import "DPI-C" function void i_integer_3d(output integer_array_t val); + import "DPI-C" function void i_integer_1d1(output integer val[1]); + import "DPI-C" function void i_integer_2d1(output integer val[1][1]); + import "DPI-C" function void i_integer_3d1(output integer_array1_t val); `endif - import "DPI-C" function void i_real_0d(output real val); - import "DPI-C" function void i_real_1d(output real val[2]); - import "DPI-C" function void i_real_2d(output real val[3][2]); - import "DPI-C" function void i_real_3d(output real_array_t val); - import "DPI-C" function void i_real_1d1(output real val[1]); - import "DPI-C" function void i_real_2d1(output real val[1][1]); - import "DPI-C" function void i_real_3d1(output real_array1_t val); + import "DPI-C" function void i_real_0d(output real val); + import "DPI-C" function void i_real_1d(output real val[2]); + import "DPI-C" function void i_real_2d(output real val[3][2]); + import "DPI-C" function void i_real_3d(output real_array_t val); + import "DPI-C" function void i_real_1d1(output real val[1]); + import "DPI-C" function void i_real_2d1(output real val[1][1]); + import "DPI-C" function void i_real_3d1(output real_array1_t val); `ifndef NO_SHORTREAL - import "DPI-C" function void i_shortreal_0d(output shortreal val); - import "DPI-C" function void i_shortreal_1d(output shortreal val[2]); - import "DPI-C" function void i_shortreal_2d(output shortreal val[3][2]); - import "DPI-C" function void i_shortreal_3d(output shortreal_array_t val); - import "DPI-C" function void i_shortreal_1d1(output shortreal val[1]); - import "DPI-C" function void i_shortreal_2d1(output shortreal val[1][1]); - import "DPI-C" function void i_shortreal_3d1(output shortreal_array1_t val); + import "DPI-C" function void i_shortreal_0d(output shortreal val); + import "DPI-C" function void i_shortreal_1d(output shortreal val[2]); + import "DPI-C" function void i_shortreal_2d(output shortreal val[3][2]); + import "DPI-C" function void i_shortreal_3d(output shortreal_array_t val); + import "DPI-C" function void i_shortreal_1d1(output shortreal val[1]); + import "DPI-C" function void i_shortreal_2d1(output shortreal val[1][1]); + import "DPI-C" function void i_shortreal_3d1(output shortreal_array1_t val); `endif - import "DPI-C" function void i_chandle_0d(output chandle val); - import "DPI-C" function void i_chandle_1d(output chandle val[2]); - import "DPI-C" function void i_chandle_2d(output chandle val[3][2]); - import "DPI-C" function void i_chandle_3d(output chandle_array_t val); - import "DPI-C" function void i_chandle_1d1(output chandle val[1]); - import "DPI-C" function void i_chandle_2d1(output chandle val[1][1]); - import "DPI-C" function void i_chandle_3d1(output chandle_array1_t val); + import "DPI-C" function void i_chandle_0d(output chandle val); + import "DPI-C" function void i_chandle_1d(output chandle val[2]); + import "DPI-C" function void i_chandle_2d(output chandle val[3][2]); + import "DPI-C" function void i_chandle_3d(output chandle_array_t val); + import "DPI-C" function void i_chandle_1d1(output chandle val[1]); + import "DPI-C" function void i_chandle_2d1(output chandle val[1][1]); + import "DPI-C" function void i_chandle_3d1(output chandle_array1_t val); - import "DPI-C" function void i_string_0d(output string val); - import "DPI-C" function void i_string_1d(output string val[2]); - import "DPI-C" function void i_string_2d(output string val[3][2]); - import "DPI-C" function void i_string_3d(output string_array_t val); - import "DPI-C" function void i_string_1d1(output string val[1]); - import "DPI-C" function void i_string_2d1(output string val[1][1]); - import "DPI-C" function void i_string_3d1(output string_array1_t val); + import "DPI-C" function void i_string_0d(output string val); + import "DPI-C" function void i_string_1d(output string val[2]); + import "DPI-C" function void i_string_2d(output string val[3][2]); + import "DPI-C" function void i_string_3d(output string_array_t val); + import "DPI-C" function void i_string_1d1(output string val[1]); + import "DPI-C" function void i_string_2d1(output string val[1][1]); + import "DPI-C" function void i_string_3d1(output string_array1_t val); - import "DPI-C" function void i_bit1_0d(output bit val); - import "DPI-C" function void i_bit1_1d(output bit val[2]); - import "DPI-C" function void i_bit1_2d(output bit val[3][2]); - import "DPI-C" function void i_bit1_3d(output bit1_array_t val); - import "DPI-C" function void i_bit1_1d1(output bit val[1]); - import "DPI-C" function void i_bit1_2d1(output bit val[1][1]); - import "DPI-C" function void i_bit1_3d1(output bit1_array1_t val); + import "DPI-C" function void i_bit1_0d(output bit val); + import "DPI-C" function void i_bit1_1d(output bit val[2]); + import "DPI-C" function void i_bit1_2d(output bit val[3][2]); + import "DPI-C" function void i_bit1_3d(output bit1_array_t val); + import "DPI-C" function void i_bit1_1d1(output bit val[1]); + import "DPI-C" function void i_bit1_2d1(output bit val[1][1]); + import "DPI-C" function void i_bit1_3d1(output bit1_array1_t val); - import "DPI-C" function void i_bit7_0d(output bit[6:0] val); - import "DPI-C" function void i_bit7_1d(output bit[6:0] val[2]); - import "DPI-C" function void i_bit7_2d(output bit[6:0] val[3][2]); - import "DPI-C" function void i_bit7_3d(output bit7_array_t val); - import "DPI-C" function void i_bit7_1d1(output bit[6:0] val[1]); - import "DPI-C" function void i_bit7_2d1(output bit[6:0] val[1][1]); - import "DPI-C" function void i_bit7_3d1(output bit7_array1_t val); + import "DPI-C" function void i_bit7_0d(output bit[6:0] val); + import "DPI-C" function void i_bit7_1d(output bit[6:0] val[2]); + import "DPI-C" function void i_bit7_2d(output bit[6:0] val[3][2]); + import "DPI-C" function void i_bit7_3d(output bit7_array_t val); + import "DPI-C" function void i_bit7_1d1(output bit[6:0] val[1]); + import "DPI-C" function void i_bit7_2d1(output bit[6:0] val[1][1]); + import "DPI-C" function void i_bit7_3d1(output bit7_array1_t val); - import "DPI-C" function void i_bit121_0d(output bit[120:0] val); - import "DPI-C" function void i_bit121_1d(output bit[120:0] val[2]); - import "DPI-C" function void i_bit121_2d(output bit[120:0] val[3][2]); - import "DPI-C" function void i_bit121_3d(output bit121_array_t val); - import "DPI-C" function void i_bit121_1d1(output bit[120:0] val[1]); - import "DPI-C" function void i_bit121_2d1(output bit[120:0] val[1][1]); - import "DPI-C" function void i_bit121_3d1(output bit121_array1_t val); + import "DPI-C" function void i_bit121_0d(output bit[120:0] val); + import "DPI-C" function void i_bit121_1d(output bit[120:0] val[2]); + import "DPI-C" function void i_bit121_2d(output bit[120:0] val[3][2]); + import "DPI-C" function void i_bit121_3d(output bit121_array_t val); + import "DPI-C" function void i_bit121_1d1(output bit[120:0] val[1]); + import "DPI-C" function void i_bit121_2d1(output bit[120:0] val[1][1]); + import "DPI-C" function void i_bit121_3d1(output bit121_array1_t val); - import "DPI-C" function void i_logic1_0d(output logic val); - import "DPI-C" function void i_logic1_1d(output logic val[2]); - import "DPI-C" function void i_logic1_2d(output logic val[3][2]); - import "DPI-C" function void i_logic1_3d(output logic1_array_t val); - import "DPI-C" function void i_logic1_1d1(output logic val[1]); - import "DPI-C" function void i_logic1_2d1(output logic val[1][1]); - import "DPI-C" function void i_logic1_3d1(output logic1_array1_t val); + import "DPI-C" function void i_logic1_0d(output logic val); + import "DPI-C" function void i_logic1_1d(output logic val[2]); + import "DPI-C" function void i_logic1_2d(output logic val[3][2]); + import "DPI-C" function void i_logic1_3d(output logic1_array_t val); + import "DPI-C" function void i_logic1_1d1(output logic val[1]); + import "DPI-C" function void i_logic1_2d1(output logic val[1][1]); + import "DPI-C" function void i_logic1_3d1(output logic1_array1_t val); - import "DPI-C" function void i_logic7_0d(output logic[6:0] val); - import "DPI-C" function void i_logic7_1d(output logic[6:0] val[2]); - import "DPI-C" function void i_logic7_2d(output logic[6:0] val[3][2]); - import "DPI-C" function void i_logic7_3d(output logic7_array_t val); - import "DPI-C" function void i_logic7_1d1(output logic[6:0] val[1]); - import "DPI-C" function void i_logic7_2d1(output logic[6:0] val[1][1]); - import "DPI-C" function void i_logic7_3d1(output logic7_array1_t val); + import "DPI-C" function void i_logic7_0d(output logic[6:0] val); + import "DPI-C" function void i_logic7_1d(output logic[6:0] val[2]); + import "DPI-C" function void i_logic7_2d(output logic[6:0] val[3][2]); + import "DPI-C" function void i_logic7_3d(output logic7_array_t val); + import "DPI-C" function void i_logic7_1d1(output logic[6:0] val[1]); + import "DPI-C" function void i_logic7_2d1(output logic[6:0] val[1][1]); + import "DPI-C" function void i_logic7_3d1(output logic7_array1_t val); - import "DPI-C" function void i_logic121_0d(output logic[120:0] val); - import "DPI-C" function void i_logic121_1d(output logic[120:0] val[2]); - import "DPI-C" function void i_logic121_2d(output logic[120:0] val[3][2]); - import "DPI-C" function void i_logic121_3d(output logic121_array_t val); - import "DPI-C" function void i_logic121_1d1(output logic[120:0] val[1]); - import "DPI-C" function void i_logic121_2d1(output logic[120:0] val[1][1]); - import "DPI-C" function void i_logic121_3d1(output logic121_array1_t val); + import "DPI-C" function void i_logic121_0d(output logic[120:0] val); + import "DPI-C" function void i_logic121_1d(output logic[120:0] val[2]); + import "DPI-C" function void i_logic121_2d(output logic[120:0] val[3][2]); + import "DPI-C" function void i_logic121_3d(output logic121_array_t val); + import "DPI-C" function void i_logic121_1d1(output logic[120:0] val[1]); + import "DPI-C" function void i_logic121_2d1(output logic[120:0] val[1][1]); + import "DPI-C" function void i_logic121_3d1(output logic121_array1_t val); - import "DPI-C" function void i_pack_struct_0d(output pack_struct_t val); - import "DPI-C" function void i_pack_struct_1d(output pack_struct_t val[2]); - import "DPI-C" function void i_pack_struct_2d(output pack_struct_t val[3][2]); - import "DPI-C" function void i_pack_struct_3d(output pack_struct_array_t val); - import "DPI-C" function void i_pack_struct_1d1(output pack_struct_t val[1]); - import "DPI-C" function void i_pack_struct_2d1(output pack_struct_t val[1][1]); - import "DPI-C" function void i_pack_struct_3d1(output pack_struct_array1_t val); + import "DPI-C" function void i_pack_struct_0d(output pack_struct_t val); + import "DPI-C" function void i_pack_struct_1d(output pack_struct_t val[2]); + import "DPI-C" function void i_pack_struct_2d(output pack_struct_t val[3][2]); + import "DPI-C" function void i_pack_struct_3d(output pack_struct_array_t val); + import "DPI-C" function void i_pack_struct_1d1(output pack_struct_t val[1]); + import "DPI-C" function void i_pack_struct_2d1(output pack_struct_t val[1][1]); + import "DPI-C" function void i_pack_struct_3d1(output pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT - import "DPI-C" function void i_unpack_struct_0d(output unpack_struct_t val); - import "DPI-C" function void i_unpack_struct_1d(output unpack_struct_t val[2]); - import "DPI-C" function void i_unpack_struct_2d(output unpack_struct_t val[3][2]); - import "DPI-C" function void i_unpack_struct_3d(output unpack_struct_array_t val); - import "DPI-C" function void i_unpack_struct_1d1(output unpack_struct_t val[1]); - import "DPI-C" function void i_unpack_struct_2d1(output unpack_struct_t val[1][1]); - import "DPI-C" function void i_unpack_struct_3d1(output unpack_struct_array1_t val); + import "DPI-C" function void i_unpack_struct_0d(output unpack_struct_t val); + import "DPI-C" function void i_unpack_struct_1d(output unpack_struct_t val[2]); + import "DPI-C" function void i_unpack_struct_2d(output unpack_struct_t val[3][2]); + import "DPI-C" function void i_unpack_struct_3d(output unpack_struct_array_t val); + import "DPI-C" function void i_unpack_struct_1d1(output unpack_struct_t val[1]); + import "DPI-C" function void i_unpack_struct_2d1(output unpack_struct_t val[1][1]); + import "DPI-C" function void i_unpack_struct_3d1(output unpack_struct_array1_t val); `endif - //====================================================================== - // Exports - //====================================================================== - export "DPI-C" function e_byte_0d; - export "DPI-C" function e_byte_1d; - export "DPI-C" function e_byte_2d; - export "DPI-C" function e_byte_3d; - export "DPI-C" function e_byte_1d1; - export "DPI-C" function e_byte_2d1; - export "DPI-C" function e_byte_3d1; + //====================================================================== + // Exports + //====================================================================== + export "DPI-C" function e_byte_0d; + export "DPI-C" function e_byte_1d; + export "DPI-C" function e_byte_2d; + export "DPI-C" function e_byte_3d; + export "DPI-C" function e_byte_1d1; + export "DPI-C" function e_byte_2d1; + export "DPI-C" function e_byte_3d1; - export "DPI-C" function e_byte_unsigned_0d; - export "DPI-C" function e_byte_unsigned_1d; - export "DPI-C" function e_byte_unsigned_2d; - export "DPI-C" function e_byte_unsigned_3d; - export "DPI-C" function e_byte_unsigned_1d1; - export "DPI-C" function e_byte_unsigned_2d1; - export "DPI-C" function e_byte_unsigned_3d1; + export "DPI-C" function e_byte_unsigned_0d; + export "DPI-C" function e_byte_unsigned_1d; + export "DPI-C" function e_byte_unsigned_2d; + export "DPI-C" function e_byte_unsigned_3d; + export "DPI-C" function e_byte_unsigned_1d1; + export "DPI-C" function e_byte_unsigned_2d1; + export "DPI-C" function e_byte_unsigned_3d1; - export "DPI-C" function e_shortint_0d; - export "DPI-C" function e_shortint_1d; - export "DPI-C" function e_shortint_2d; - export "DPI-C" function e_shortint_3d; - export "DPI-C" function e_shortint_1d1; - export "DPI-C" function e_shortint_2d1; - export "DPI-C" function e_shortint_3d1; + export "DPI-C" function e_shortint_0d; + export "DPI-C" function e_shortint_1d; + export "DPI-C" function e_shortint_2d; + export "DPI-C" function e_shortint_3d; + export "DPI-C" function e_shortint_1d1; + export "DPI-C" function e_shortint_2d1; + export "DPI-C" function e_shortint_3d1; - export "DPI-C" function e_shortint_unsigned_0d; - export "DPI-C" function e_shortint_unsigned_1d; - export "DPI-C" function e_shortint_unsigned_2d; - export "DPI-C" function e_shortint_unsigned_3d; - export "DPI-C" function e_shortint_unsigned_1d1; - export "DPI-C" function e_shortint_unsigned_2d1; - export "DPI-C" function e_shortint_unsigned_3d1; + export "DPI-C" function e_shortint_unsigned_0d; + export "DPI-C" function e_shortint_unsigned_1d; + export "DPI-C" function e_shortint_unsigned_2d; + export "DPI-C" function e_shortint_unsigned_3d; + export "DPI-C" function e_shortint_unsigned_1d1; + export "DPI-C" function e_shortint_unsigned_2d1; + export "DPI-C" function e_shortint_unsigned_3d1; - export "DPI-C" function e_int_0d; - export "DPI-C" function e_int_1d; - export "DPI-C" function e_int_2d; - export "DPI-C" function e_int_3d; - export "DPI-C" function e_int_1d1; - export "DPI-C" function e_int_2d1; - export "DPI-C" function e_int_3d1; + export "DPI-C" function e_int_0d; + export "DPI-C" function e_int_1d; + export "DPI-C" function e_int_2d; + export "DPI-C" function e_int_3d; + export "DPI-C" function e_int_1d1; + export "DPI-C" function e_int_2d1; + export "DPI-C" function e_int_3d1; - export "DPI-C" function e_int_unsigned_0d; - export "DPI-C" function e_int_unsigned_1d; - export "DPI-C" function e_int_unsigned_2d; - export "DPI-C" function e_int_unsigned_3d; - export "DPI-C" function e_int_unsigned_1d1; - export "DPI-C" function e_int_unsigned_2d1; - export "DPI-C" function e_int_unsigned_3d1; + export "DPI-C" function e_int_unsigned_0d; + export "DPI-C" function e_int_unsigned_1d; + export "DPI-C" function e_int_unsigned_2d; + export "DPI-C" function e_int_unsigned_3d; + export "DPI-C" function e_int_unsigned_1d1; + export "DPI-C" function e_int_unsigned_2d1; + export "DPI-C" function e_int_unsigned_3d1; - export "DPI-C" function e_longint_0d; - export "DPI-C" function e_longint_1d; - export "DPI-C" function e_longint_2d; - export "DPI-C" function e_longint_3d; - export "DPI-C" function e_longint_1d1; - export "DPI-C" function e_longint_2d1; - export "DPI-C" function e_longint_3d1; + export "DPI-C" function e_longint_0d; + export "DPI-C" function e_longint_1d; + export "DPI-C" function e_longint_2d; + export "DPI-C" function e_longint_3d; + export "DPI-C" function e_longint_1d1; + export "DPI-C" function e_longint_2d1; + export "DPI-C" function e_longint_3d1; - export "DPI-C" function e_longint_unsigned_0d; - export "DPI-C" function e_longint_unsigned_1d; - export "DPI-C" function e_longint_unsigned_2d; - export "DPI-C" function e_longint_unsigned_3d; - export "DPI-C" function e_longint_unsigned_1d1; - export "DPI-C" function e_longint_unsigned_2d1; - export "DPI-C" function e_longint_unsigned_3d1; + export "DPI-C" function e_longint_unsigned_0d; + export "DPI-C" function e_longint_unsigned_1d; + export "DPI-C" function e_longint_unsigned_2d; + export "DPI-C" function e_longint_unsigned_3d; + export "DPI-C" function e_longint_unsigned_1d1; + export "DPI-C" function e_longint_unsigned_2d1; + export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME - export "DPI-C" function e_time_0d; - export "DPI-C" function e_time_1d; - export "DPI-C" function e_time_2d; - export "DPI-C" function e_time_3d; - export "DPI-C" function e_time_1d1; - export "DPI-C" function e_time_2d1; - export "DPI-C" function e_time_3d1; + export "DPI-C" function e_time_0d; + export "DPI-C" function e_time_1d; + export "DPI-C" function e_time_2d; + export "DPI-C" function e_time_3d; + export "DPI-C" function e_time_1d1; + export "DPI-C" function e_time_2d1; + export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER - export "DPI-C" function e_integer_0d; - export "DPI-C" function e_integer_1d; - export "DPI-C" function e_integer_2d; - export "DPI-C" function e_integer_3d; - export "DPI-C" function e_integer_1d1; - export "DPI-C" function e_integer_2d1; - export "DPI-C" function e_integer_3d1; + export "DPI-C" function e_integer_0d; + export "DPI-C" function e_integer_1d; + export "DPI-C" function e_integer_2d; + export "DPI-C" function e_integer_3d; + export "DPI-C" function e_integer_1d1; + export "DPI-C" function e_integer_2d1; + export "DPI-C" function e_integer_3d1; `endif - export "DPI-C" function e_real_0d; - export "DPI-C" function e_real_1d; - export "DPI-C" function e_real_2d; - export "DPI-C" function e_real_3d; - export "DPI-C" function e_real_1d1; - export "DPI-C" function e_real_2d1; - export "DPI-C" function e_real_3d1; + export "DPI-C" function e_real_0d; + export "DPI-C" function e_real_1d; + export "DPI-C" function e_real_2d; + export "DPI-C" function e_real_3d; + export "DPI-C" function e_real_1d1; + export "DPI-C" function e_real_2d1; + export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_0d; - export "DPI-C" function e_shortreal_1d; - export "DPI-C" function e_shortreal_2d; - export "DPI-C" function e_shortreal_3d; - export "DPI-C" function e_shortreal_1d1; - export "DPI-C" function e_shortreal_2d1; - export "DPI-C" function e_shortreal_3d1; + export "DPI-C" function e_shortreal_0d; + export "DPI-C" function e_shortreal_1d; + export "DPI-C" function e_shortreal_2d; + export "DPI-C" function e_shortreal_3d; + export "DPI-C" function e_shortreal_1d1; + export "DPI-C" function e_shortreal_2d1; + export "DPI-C" function e_shortreal_3d1; `endif - export "DPI-C" function e_chandle_0d; - export "DPI-C" function e_chandle_1d; - export "DPI-C" function e_chandle_2d; - export "DPI-C" function e_chandle_3d; - export "DPI-C" function e_chandle_1d1; - export "DPI-C" function e_chandle_2d1; - export "DPI-C" function e_chandle_3d1; + export "DPI-C" function e_chandle_0d; + export "DPI-C" function e_chandle_1d; + export "DPI-C" function e_chandle_2d; + export "DPI-C" function e_chandle_3d; + export "DPI-C" function e_chandle_1d1; + export "DPI-C" function e_chandle_2d1; + export "DPI-C" function e_chandle_3d1; - export "DPI-C" function e_string_0d; - export "DPI-C" function e_string_1d; - export "DPI-C" function e_string_2d; - export "DPI-C" function e_string_3d; - export "DPI-C" function e_string_1d1; - export "DPI-C" function e_string_2d1; - export "DPI-C" function e_string_3d1; + export "DPI-C" function e_string_0d; + export "DPI-C" function e_string_1d; + export "DPI-C" function e_string_2d; + export "DPI-C" function e_string_3d; + export "DPI-C" function e_string_1d1; + export "DPI-C" function e_string_2d1; + export "DPI-C" function e_string_3d1; - export "DPI-C" function e_bit1_0d; - export "DPI-C" function e_bit1_1d; - export "DPI-C" function e_bit1_2d; - export "DPI-C" function e_bit1_3d; - export "DPI-C" function e_bit1_1d1; - export "DPI-C" function e_bit1_2d1; - export "DPI-C" function e_bit1_3d1; + export "DPI-C" function e_bit1_0d; + export "DPI-C" function e_bit1_1d; + export "DPI-C" function e_bit1_2d; + export "DPI-C" function e_bit1_3d; + export "DPI-C" function e_bit1_1d1; + export "DPI-C" function e_bit1_2d1; + export "DPI-C" function e_bit1_3d1; - export "DPI-C" function e_bit7_0d; - export "DPI-C" function e_bit7_1d; - export "DPI-C" function e_bit7_2d; - export "DPI-C" function e_bit7_3d; - export "DPI-C" function e_bit7_1d1; - export "DPI-C" function e_bit7_2d1; - export "DPI-C" function e_bit7_3d1; + export "DPI-C" function e_bit7_0d; + export "DPI-C" function e_bit7_1d; + export "DPI-C" function e_bit7_2d; + export "DPI-C" function e_bit7_3d; + export "DPI-C" function e_bit7_1d1; + export "DPI-C" function e_bit7_2d1; + export "DPI-C" function e_bit7_3d1; - export "DPI-C" function e_bit121_0d; - export "DPI-C" function e_bit121_1d; - export "DPI-C" function e_bit121_2d; - export "DPI-C" function e_bit121_3d; - export "DPI-C" function e_bit121_1d1; - export "DPI-C" function e_bit121_2d1; - export "DPI-C" function e_bit121_3d1; + export "DPI-C" function e_bit121_0d; + export "DPI-C" function e_bit121_1d; + export "DPI-C" function e_bit121_2d; + export "DPI-C" function e_bit121_3d; + export "DPI-C" function e_bit121_1d1; + export "DPI-C" function e_bit121_2d1; + export "DPI-C" function e_bit121_3d1; - export "DPI-C" function e_logic1_0d; - export "DPI-C" function e_logic1_1d; - export "DPI-C" function e_logic1_2d; - export "DPI-C" function e_logic1_3d; - export "DPI-C" function e_logic1_1d1; - export "DPI-C" function e_logic1_2d1; - export "DPI-C" function e_logic1_3d1; + export "DPI-C" function e_logic1_0d; + export "DPI-C" function e_logic1_1d; + export "DPI-C" function e_logic1_2d; + export "DPI-C" function e_logic1_3d; + export "DPI-C" function e_logic1_1d1; + export "DPI-C" function e_logic1_2d1; + export "DPI-C" function e_logic1_3d1; - export "DPI-C" function e_logic7_0d; - export "DPI-C" function e_logic7_1d; - export "DPI-C" function e_logic7_2d; - export "DPI-C" function e_logic7_3d; - export "DPI-C" function e_logic7_1d1; - export "DPI-C" function e_logic7_2d1; - export "DPI-C" function e_logic7_3d1; + export "DPI-C" function e_logic7_0d; + export "DPI-C" function e_logic7_1d; + export "DPI-C" function e_logic7_2d; + export "DPI-C" function e_logic7_3d; + export "DPI-C" function e_logic7_1d1; + export "DPI-C" function e_logic7_2d1; + export "DPI-C" function e_logic7_3d1; - export "DPI-C" function e_logic121_0d; - export "DPI-C" function e_logic121_1d; - export "DPI-C" function e_logic121_2d; - export "DPI-C" function e_logic121_3d; - export "DPI-C" function e_logic121_1d1; - export "DPI-C" function e_logic121_2d1; - export "DPI-C" function e_logic121_3d1; + export "DPI-C" function e_logic121_0d; + export "DPI-C" function e_logic121_1d; + export "DPI-C" function e_logic121_2d; + export "DPI-C" function e_logic121_3d; + export "DPI-C" function e_logic121_1d1; + export "DPI-C" function e_logic121_2d1; + export "DPI-C" function e_logic121_3d1; - export "DPI-C" function e_pack_struct_0d; - export "DPI-C" function e_pack_struct_1d; - export "DPI-C" function e_pack_struct_2d; - export "DPI-C" function e_pack_struct_3d; - export "DPI-C" function e_pack_struct_1d1; - export "DPI-C" function e_pack_struct_2d1; - export "DPI-C" function e_pack_struct_3d1; + export "DPI-C" function e_pack_struct_0d; + export "DPI-C" function e_pack_struct_1d; + export "DPI-C" function e_pack_struct_2d; + export "DPI-C" function e_pack_struct_3d; + export "DPI-C" function e_pack_struct_1d1; + export "DPI-C" function e_pack_struct_2d1; + export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT - export "DPI-C" function e_unpack_struct_0d; - export "DPI-C" function e_unpack_struct_1d; - export "DPI-C" function e_unpack_struct_2d; - export "DPI-C" function e_unpack_struct_3d; - export "DPI-C" function e_unpack_struct_1d1; - export "DPI-C" function e_unpack_struct_2d1; - export "DPI-C" function e_unpack_struct_3d1; + export "DPI-C" function e_unpack_struct_0d; + export "DPI-C" function e_unpack_struct_1d; + export "DPI-C" function e_unpack_struct_2d; + export "DPI-C" function e_unpack_struct_3d; + export "DPI-C" function e_unpack_struct_1d1; + export "DPI-C" function e_unpack_struct_2d1; + export "DPI-C" function e_unpack_struct_3d1; `endif - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== `define SET_0D(val) \ - /* verilator lint_off WIDTH */ \ - val = 42 \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val = 42 \ + /* verilator lint_on WIDTH */ `define SET_1D(val) \ - /* verilator lint_off WIDTH */ \ - val[0] = 43; val[1] = 44 \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0] = 43; val[1] = 44 \ + /* verilator lint_on WIDTH */ `define SET_2D(val) \ - /* verilator lint_off WIDTH */ \ - val[0][1] = 45; val[1][1] = 46; val[2][1] = 47 \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0][1] = 45; val[1][1] = 46; val[2][1] = 47 \ + /* verilator lint_on WIDTH */ `define SET_3D(val) \ - /* verilator lint_off WIDTH */ \ - val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ + /* verilator lint_on WIDTH */ `define SET_1D1(val) \ - /* verilator lint_off WIDTH */ \ - val[0] = 52; \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0] = 52; \ + /* verilator lint_on WIDTH */ `define SET_2D1(val) \ - /* verilator lint_off WIDTH */ \ - val[0][0] = 53; \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0][0] = 53; \ + /* verilator lint_on WIDTH */ `define SET_3D1(val) \ - /* verilator lint_off WIDTH */ \ - val[0][0][0] = 54; \ - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ \ + val[0][0][0] = 54; \ + /* verilator lint_on WIDTH */ - function void e_byte_0d(output byte val); `SET_0D(val); endfunction - function void e_byte_1d(output byte val[2]); `SET_1D(val); endfunction - function void e_byte_2d(output byte val[3][2]); `SET_2D(val); endfunction - function void e_byte_3d(output byte_array_t val); `SET_3D(val); endfunction - function void e_byte_1d1(output byte val[1]); `SET_1D1(val); endfunction - function void e_byte_2d1(output byte val[1][1]); `SET_2D1(val); endfunction - function void e_byte_3d1(output byte_array1_t val); `SET_3D1(val); endfunction + function void e_byte_0d(output byte val); `SET_0D(val); endfunction + function void e_byte_1d(output byte val[2]); `SET_1D(val); endfunction + function void e_byte_2d(output byte val[3][2]); `SET_2D(val); endfunction + function void e_byte_3d(output byte_array_t val); `SET_3D(val); endfunction + function void e_byte_1d1(output byte val[1]); `SET_1D1(val); endfunction + function void e_byte_2d1(output byte val[1][1]); `SET_2D1(val); endfunction + function void e_byte_3d1(output byte_array1_t val); `SET_3D1(val); endfunction - function void e_byte_unsigned_0d(output byte unsigned val); `SET_0D(val); endfunction - function void e_byte_unsigned_1d(output byte unsigned val[2]); `SET_1D(val); endfunction - function void e_byte_unsigned_2d(output byte unsigned val[3][2]); `SET_2D(val); endfunction - function void e_byte_unsigned_3d(output byte_unsigned_array_t val); `SET_3D(val); endfunction - function void e_byte_unsigned_1d1(output byte unsigned val[1]); `SET_1D1(val); endfunction - function void e_byte_unsigned_2d1(output byte unsigned val[1][1]); `SET_2D1(val); endfunction - function void e_byte_unsigned_3d1(output byte_unsigned_array1_t val); `SET_3D1(val); endfunction + function void e_byte_unsigned_0d(output byte unsigned val); `SET_0D(val); endfunction + function void e_byte_unsigned_1d(output byte unsigned val[2]); `SET_1D(val); endfunction + function void e_byte_unsigned_2d(output byte unsigned val[3][2]); `SET_2D(val); endfunction + function void e_byte_unsigned_3d(output byte_unsigned_array_t val); `SET_3D(val); endfunction + function void e_byte_unsigned_1d1(output byte unsigned val[1]); `SET_1D1(val); endfunction + function void e_byte_unsigned_2d1(output byte unsigned val[1][1]); `SET_2D1(val); endfunction + function void e_byte_unsigned_3d1(output byte_unsigned_array1_t val); `SET_3D1(val); endfunction - function void e_shortint_0d(output shortint val); `SET_0D(val); endfunction - function void e_shortint_1d(output shortint val[2]); `SET_1D(val); endfunction - function void e_shortint_2d(output shortint val[3][2]); `SET_2D(val); endfunction - function void e_shortint_3d(output shortint_array_t val); `SET_3D(val); endfunction - function void e_shortint_1d1(output shortint val[1]); `SET_1D1(val); endfunction - function void e_shortint_2d1(output shortint val[1][1]); `SET_2D1(val); endfunction - function void e_shortint_3d1(output shortint_array1_t val); `SET_3D1(val); endfunction + function void e_shortint_0d(output shortint val); `SET_0D(val); endfunction + function void e_shortint_1d(output shortint val[2]); `SET_1D(val); endfunction + function void e_shortint_2d(output shortint val[3][2]); `SET_2D(val); endfunction + function void e_shortint_3d(output shortint_array_t val); `SET_3D(val); endfunction + function void e_shortint_1d1(output shortint val[1]); `SET_1D1(val); endfunction + function void e_shortint_2d1(output shortint val[1][1]); `SET_2D1(val); endfunction + function void e_shortint_3d1(output shortint_array1_t val); `SET_3D1(val); endfunction - function void e_shortint_unsigned_0d(output shortint unsigned val); `SET_0D(val); endfunction - function void e_shortint_unsigned_1d(output shortint unsigned val[2]); `SET_1D(val); endfunction - function void e_shortint_unsigned_2d(output shortint unsigned val[3][2]); `SET_2D(val); endfunction - function void e_shortint_unsigned_3d(output shortint_unsigned_array_t val); `SET_3D(val); endfunction - function void e_shortint_unsigned_1d1(output shortint unsigned val[1]); `SET_1D1(val); endfunction - function void e_shortint_unsigned_2d1(output shortint unsigned val[1][1]); `SET_2D1(val); endfunction - function void e_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); `SET_3D1(val); endfunction + function void e_shortint_unsigned_0d(output shortint unsigned val); `SET_0D(val); endfunction + function void e_shortint_unsigned_1d(output shortint unsigned val[2]); `SET_1D(val); endfunction + function void e_shortint_unsigned_2d(output shortint unsigned val[3][2]); `SET_2D(val); endfunction + function void e_shortint_unsigned_3d(output shortint_unsigned_array_t val); `SET_3D(val); endfunction + function void e_shortint_unsigned_1d1(output shortint unsigned val[1]); `SET_1D1(val); endfunction + function void e_shortint_unsigned_2d1(output shortint unsigned val[1][1]); `SET_2D1(val); endfunction + function void e_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); `SET_3D1(val); endfunction - function void e_int_0d(output int val); `SET_0D(val); endfunction - function void e_int_1d(output int val[2]); `SET_1D(val); endfunction - function void e_int_2d(output int val[3][2]); `SET_2D(val); endfunction - function void e_int_3d(output int_array_t val); `SET_3D(val); endfunction - function void e_int_1d1(output int val[1]); `SET_1D1(val); endfunction - function void e_int_2d1(output int val[1][1]); `SET_2D1(val); endfunction - function void e_int_3d1(output int_array1_t val); `SET_3D1(val); endfunction + function void e_int_0d(output int val); `SET_0D(val); endfunction + function void e_int_1d(output int val[2]); `SET_1D(val); endfunction + function void e_int_2d(output int val[3][2]); `SET_2D(val); endfunction + function void e_int_3d(output int_array_t val); `SET_3D(val); endfunction + function void e_int_1d1(output int val[1]); `SET_1D1(val); endfunction + function void e_int_2d1(output int val[1][1]); `SET_2D1(val); endfunction + function void e_int_3d1(output int_array1_t val); `SET_3D1(val); endfunction - function void e_int_unsigned_0d(output int unsigned val); `SET_0D(val); endfunction - function void e_int_unsigned_1d(output int unsigned val[2]); `SET_1D(val); endfunction - function void e_int_unsigned_2d(output int unsigned val[3][2]); `SET_2D(val); endfunction - function void e_int_unsigned_3d(output int_unsigned_array_t val); `SET_3D(val); endfunction - function void e_int_unsigned_1d1(output int unsigned val[1]); `SET_1D1(val); endfunction - function void e_int_unsigned_2d1(output int unsigned val[1][1]); `SET_2D1(val); endfunction - function void e_int_unsigned_3d1(output int_unsigned_array1_t val); `SET_3D1(val); endfunction + function void e_int_unsigned_0d(output int unsigned val); `SET_0D(val); endfunction + function void e_int_unsigned_1d(output int unsigned val[2]); `SET_1D(val); endfunction + function void e_int_unsigned_2d(output int unsigned val[3][2]); `SET_2D(val); endfunction + function void e_int_unsigned_3d(output int_unsigned_array_t val); `SET_3D(val); endfunction + function void e_int_unsigned_1d1(output int unsigned val[1]); `SET_1D1(val); endfunction + function void e_int_unsigned_2d1(output int unsigned val[1][1]); `SET_2D1(val); endfunction + function void e_int_unsigned_3d1(output int_unsigned_array1_t val); `SET_3D1(val); endfunction - function void e_longint_0d(output longint val); `SET_0D(val); endfunction - function void e_longint_1d(output longint val[2]); `SET_1D(val); endfunction - function void e_longint_2d(output longint val[3][2]); `SET_2D(val); endfunction - function void e_longint_3d(output longint_array_t val); `SET_3D(val); endfunction - function void e_longint_1d1(output longint val[1]); `SET_1D1(val); endfunction - function void e_longint_2d1(output longint val[1][1]); `SET_2D1(val); endfunction - function void e_longint_3d1(output longint_array1_t val); `SET_3D1(val); endfunction + function void e_longint_0d(output longint val); `SET_0D(val); endfunction + function void e_longint_1d(output longint val[2]); `SET_1D(val); endfunction + function void e_longint_2d(output longint val[3][2]); `SET_2D(val); endfunction + function void e_longint_3d(output longint_array_t val); `SET_3D(val); endfunction + function void e_longint_1d1(output longint val[1]); `SET_1D1(val); endfunction + function void e_longint_2d1(output longint val[1][1]); `SET_2D1(val); endfunction + function void e_longint_3d1(output longint_array1_t val); `SET_3D1(val); endfunction - function void e_longint_unsigned_0d(output longint unsigned val); `SET_0D(val); endfunction - function void e_longint_unsigned_1d(output longint unsigned val[2]); `SET_1D(val); endfunction - function void e_longint_unsigned_2d(output longint unsigned val[3][2]); `SET_2D(val); endfunction - function void e_longint_unsigned_3d(output longint_unsigned_array_t val); `SET_3D(val); endfunction - function void e_longint_unsigned_1d1(output longint unsigned val[1]); `SET_1D1(val); endfunction - function void e_longint_unsigned_2d1(output longint unsigned val[1][1]); `SET_2D1(val); endfunction - function void e_longint_unsigned_3d1(output longint_unsigned_array1_t val); `SET_3D1(val); endfunction + function void e_longint_unsigned_0d(output longint unsigned val); `SET_0D(val); endfunction + function void e_longint_unsigned_1d(output longint unsigned val[2]); `SET_1D(val); endfunction + function void e_longint_unsigned_2d(output longint unsigned val[3][2]); `SET_2D(val); endfunction + function void e_longint_unsigned_3d(output longint_unsigned_array_t val); `SET_3D(val); endfunction + function void e_longint_unsigned_1d1(output longint unsigned val[1]); `SET_1D1(val); endfunction + function void e_longint_unsigned_2d1(output longint unsigned val[1][1]); `SET_2D1(val); endfunction + function void e_longint_unsigned_3d1(output longint_unsigned_array1_t val); `SET_3D1(val); endfunction `ifndef NO_TIME - function void e_time_0d(output time val); `SET_0D(val); endfunction - function void e_time_1d(output time val[2]); `SET_1D(val); endfunction - function void e_time_2d(output time val[3][2]); `SET_2D(val); endfunction - function void e_time_3d(output time_array_t val); `SET_3D(val); endfunction - function void e_time_1d1(output time val[1]); `SET_1D1(val); endfunction - function void e_time_2d1(output time val[1][1]); `SET_2D1(val); endfunction - function void e_time_3d1(output time_array1_t val); `SET_3D1(val); endfunction + function void e_time_0d(output time val); `SET_0D(val); endfunction + function void e_time_1d(output time val[2]); `SET_1D(val); endfunction + function void e_time_2d(output time val[3][2]); `SET_2D(val); endfunction + function void e_time_3d(output time_array_t val); `SET_3D(val); endfunction + function void e_time_1d1(output time val[1]); `SET_1D1(val); endfunction + function void e_time_2d1(output time val[1][1]); `SET_2D1(val); endfunction + function void e_time_3d1(output time_array1_t val); `SET_3D1(val); endfunction `endif `ifndef NO_INTEGER - function void e_integer_0d(output integer val); `SET_0D(val); endfunction - function void e_integer_1d(output integer val[2]); `SET_1D(val); endfunction - function void e_integer_2d(output integer val[3][2]); `SET_2D(val); endfunction - function void e_integer_3d(output integer_array_t val); `SET_3D(val); endfunction - function void e_integer_1d1(output integer val[1]); `SET_1D1(val); endfunction - function void e_integer_2d1(output integer val[1][1]); `SET_2D1(val); endfunction - function void e_integer_3d1(output integer_array1_t val); `SET_3D1(val); endfunction + function void e_integer_0d(output integer val); `SET_0D(val); endfunction + function void e_integer_1d(output integer val[2]); `SET_1D(val); endfunction + function void e_integer_2d(output integer val[3][2]); `SET_2D(val); endfunction + function void e_integer_3d(output integer_array_t val); `SET_3D(val); endfunction + function void e_integer_1d1(output integer val[1]); `SET_1D1(val); endfunction + function void e_integer_2d1(output integer val[1][1]); `SET_2D1(val); endfunction + function void e_integer_3d1(output integer_array1_t val); `SET_3D1(val); endfunction `endif - function void e_real_0d(output real val); `SET_0D(val); endfunction - function void e_real_1d(output real val[2]); `SET_1D(val); endfunction - function void e_real_2d(output real val[3][2]); `SET_2D(val); endfunction - function void e_real_3d(output real_array_t val); `SET_3D(val); endfunction - function void e_real_1d1(output real val[1]); `SET_1D1(val); endfunction - function void e_real_2d1(output real val[1][1]); `SET_2D1(val); endfunction - function void e_real_3d1(output real_array1_t val); `SET_3D1(val); endfunction + function void e_real_0d(output real val); `SET_0D(val); endfunction + function void e_real_1d(output real val[2]); `SET_1D(val); endfunction + function void e_real_2d(output real val[3][2]); `SET_2D(val); endfunction + function void e_real_3d(output real_array_t val); `SET_3D(val); endfunction + function void e_real_1d1(output real val[1]); `SET_1D1(val); endfunction + function void e_real_2d1(output real val[1][1]); `SET_2D1(val); endfunction + function void e_real_3d1(output real_array1_t val); `SET_3D1(val); endfunction `ifndef NO_SHORTREAL - function void e_shortreal_0d(output shortreal val); `SET_0D(val); endfunction - function void e_shortreal_1d(output shortreal val[2]); `SET_1D(val); endfunction - function void e_shortreal_2d(output shortreal val[3][2]); `SET_2D(val); endfunction - function void e_shortreal_3d(output shortreal_array_t val); `SET_3D(val); endfunction - function void e_shortreal_1d1(output shortreal val[1]); `SET_1D1(val); endfunction - function void e_shortreal_2d1(output shortreal val[1][1]); `SET_2D1(val); endfunction - function void e_shortreal_3d1(output shortreal_array1_t val); `SET_3D1(val); endfunction + function void e_shortreal_0d(output shortreal val); `SET_0D(val); endfunction + function void e_shortreal_1d(output shortreal val[2]); `SET_1D(val); endfunction + function void e_shortreal_2d(output shortreal val[3][2]); `SET_2D(val); endfunction + function void e_shortreal_3d(output shortreal_array_t val); `SET_3D(val); endfunction + function void e_shortreal_1d1(output shortreal val[1]); `SET_1D1(val); endfunction + function void e_shortreal_2d1(output shortreal val[1][1]); `SET_2D1(val); endfunction + function void e_shortreal_3d1(output shortreal_array1_t val); `SET_3D1(val); endfunction `endif - function void e_chandle_0d(output chandle val); - val = get_non_null(); - endfunction - function void e_chandle_1d(output chandle val[2]); - val[0] = get_non_null(); - val[1] = get_non_null(); - endfunction - function void e_chandle_2d(output chandle val[3][2]); - val[0][1] = get_non_null(); - val[1][1] = get_non_null(); - val[2][1] = get_non_null(); - endfunction - function void e_chandle_3d(output chandle_array_t val); - val[0][0][0] = get_non_null(); - val[1][0][0] = get_non_null(); - val[2][0][0] = get_non_null(); - val[3][0][0] = get_non_null(); - endfunction - function void e_chandle_1d1(output chandle val[1]); - val[0] = get_non_null(); - endfunction - function void e_chandle_2d1(output chandle val[1][1]); - val[0][0] = get_non_null(); - endfunction - function void e_chandle_3d1(output chandle_array1_t val); - val[0][0][0] = get_non_null(); - endfunction + function void e_chandle_0d(output chandle val); + val = get_non_null(); + endfunction + function void e_chandle_1d(output chandle val[2]); + val[0] = get_non_null(); + val[1] = get_non_null(); + endfunction + function void e_chandle_2d(output chandle val[3][2]); + val[0][1] = get_non_null(); + val[1][1] = get_non_null(); + val[2][1] = get_non_null(); + endfunction + function void e_chandle_3d(output chandle_array_t val); + val[0][0][0] = get_non_null(); + val[1][0][0] = get_non_null(); + val[2][0][0] = get_non_null(); + val[3][0][0] = get_non_null(); + endfunction + function void e_chandle_1d1(output chandle val[1]); + val[0] = get_non_null(); + endfunction + function void e_chandle_2d1(output chandle val[1][1]); + val[0][0] = get_non_null(); + endfunction + function void e_chandle_3d1(output chandle_array1_t val); + val[0][0][0] = get_non_null(); + endfunction - function void e_string_0d(output string val); - val = "42"; - endfunction - function void e_string_1d(output string val[2]); - val[0] = "43"; - val[1] = "44"; - endfunction - function void e_string_2d(output string val[3][2]); - val[0][1] = "45"; - val[1][1] = "46"; - val[2][1] = "47"; - endfunction - function void e_string_3d(output string_array_t val); - val[0][0][0] = "48"; - val[1][0][0] = "49"; - val[2][0][0] = "50"; - val[3][0][0] = "51"; - endfunction - function void e_string_1d1(output string val[1]); - val[0] = "52"; - endfunction - function void e_string_2d1(output string val[1][1]); - val[0][0] = "53"; - endfunction - function void e_string_3d1(output string_array1_t val); - val[0][0][0] = "54"; - endfunction + function void e_string_0d(output string val); + val = "42"; + endfunction + function void e_string_1d(output string val[2]); + val[0] = "43"; + val[1] = "44"; + endfunction + function void e_string_2d(output string val[3][2]); + val[0][1] = "45"; + val[1][1] = "46"; + val[2][1] = "47"; + endfunction + function void e_string_3d(output string_array_t val); + val[0][0][0] = "48"; + val[1][0][0] = "49"; + val[2][0][0] = "50"; + val[3][0][0] = "51"; + endfunction + function void e_string_1d1(output string val[1]); + val[0] = "52"; + endfunction + function void e_string_2d1(output string val[1][1]); + val[0][0] = "53"; + endfunction + function void e_string_3d1(output string_array1_t val); + val[0][0][0] = "54"; + endfunction - function void e_bit1_0d(output bit val); `SET_0D(val); endfunction - function void e_bit1_1d(output bit val[2]); `SET_1D(val); endfunction - function void e_bit1_2d(output bit val[3][2]); `SET_2D(val); endfunction - function void e_bit1_3d(output bit1_array_t val); `SET_3D(val); endfunction - function void e_bit1_1d1(output bit val[1]); `SET_1D1(val); endfunction - function void e_bit1_2d1(output bit val[1][1]); `SET_2D1(val); endfunction - function void e_bit1_3d1(output bit1_array1_t val); `SET_3D1(val); endfunction + function void e_bit1_0d(output bit val); `SET_0D(val); endfunction + function void e_bit1_1d(output bit val[2]); `SET_1D(val); endfunction + function void e_bit1_2d(output bit val[3][2]); `SET_2D(val); endfunction + function void e_bit1_3d(output bit1_array_t val); `SET_3D(val); endfunction + function void e_bit1_1d1(output bit val[1]); `SET_1D1(val); endfunction + function void e_bit1_2d1(output bit val[1][1]); `SET_2D1(val); endfunction + function void e_bit1_3d1(output bit1_array1_t val); `SET_3D1(val); endfunction - function void e_bit7_0d(output bit[6:0] val); `SET_0D(val); endfunction - function void e_bit7_1d(output bit[6:0] val[2]); `SET_1D(val); endfunction - function void e_bit7_2d(output bit[6:0] val[3][2]); `SET_2D(val); endfunction - function void e_bit7_3d(output bit7_array_t val); `SET_3D(val); endfunction - function void e_bit7_1d1(output bit[6:0] val[1]); `SET_1D1(val); endfunction - function void e_bit7_2d1(output bit[6:0] val[1][1]); `SET_2D1(val); endfunction - function void e_bit7_3d1(output bit7_array1_t val); `SET_3D1(val); endfunction + function void e_bit7_0d(output bit[6:0] val); `SET_0D(val); endfunction + function void e_bit7_1d(output bit[6:0] val[2]); `SET_1D(val); endfunction + function void e_bit7_2d(output bit[6:0] val[3][2]); `SET_2D(val); endfunction + function void e_bit7_3d(output bit7_array_t val); `SET_3D(val); endfunction + function void e_bit7_1d1(output bit[6:0] val[1]); `SET_1D1(val); endfunction + function void e_bit7_2d1(output bit[6:0] val[1][1]); `SET_2D1(val); endfunction + function void e_bit7_3d1(output bit7_array1_t val); `SET_3D1(val); endfunction - function void e_bit121_0d(output bit[120:0] val); `SET_0D(val); endfunction - function void e_bit121_1d(output bit[120:0] val[2]); `SET_1D(val); endfunction - function void e_bit121_2d(output bit[120:0] val[3][2]); `SET_2D(val); endfunction - function void e_bit121_3d(output bit121_array_t val); `SET_3D(val); endfunction - function void e_bit121_1d1(output bit[120:0] val[1]); `SET_1D1(val); endfunction - function void e_bit121_2d1(output bit[120:0] val[1][1]); `SET_2D1(val); endfunction - function void e_bit121_3d1(output bit121_array1_t val); `SET_3D1(val); endfunction + function void e_bit121_0d(output bit[120:0] val); `SET_0D(val); endfunction + function void e_bit121_1d(output bit[120:0] val[2]); `SET_1D(val); endfunction + function void e_bit121_2d(output bit[120:0] val[3][2]); `SET_2D(val); endfunction + function void e_bit121_3d(output bit121_array_t val); `SET_3D(val); endfunction + function void e_bit121_1d1(output bit[120:0] val[1]); `SET_1D1(val); endfunction + function void e_bit121_2d1(output bit[120:0] val[1][1]); `SET_2D1(val); endfunction + function void e_bit121_3d1(output bit121_array1_t val); `SET_3D1(val); endfunction - function void e_logic1_0d(output logic val); `SET_0D(val); endfunction - function void e_logic1_1d(output logic val[2]); `SET_1D(val); endfunction - function void e_logic1_2d(output logic val[3][2]); `SET_2D(val); endfunction - function void e_logic1_3d(output logic1_array_t val); `SET_3D(val); endfunction - function void e_logic1_1d1(output logic val[1]); `SET_1D1(val); endfunction - function void e_logic1_2d1(output logic val[1][1]); `SET_2D1(val); endfunction - function void e_logic1_3d1(output logic1_array1_t val); `SET_3D1(val); endfunction + function void e_logic1_0d(output logic val); `SET_0D(val); endfunction + function void e_logic1_1d(output logic val[2]); `SET_1D(val); endfunction + function void e_logic1_2d(output logic val[3][2]); `SET_2D(val); endfunction + function void e_logic1_3d(output logic1_array_t val); `SET_3D(val); endfunction + function void e_logic1_1d1(output logic val[1]); `SET_1D1(val); endfunction + function void e_logic1_2d1(output logic val[1][1]); `SET_2D1(val); endfunction + function void e_logic1_3d1(output logic1_array1_t val); `SET_3D1(val); endfunction - function void e_logic7_0d(output logic[6:0] val); `SET_0D(val); endfunction - function void e_logic7_1d(output logic[6:0] val[2]); `SET_1D(val); endfunction - function void e_logic7_2d(output logic[6:0] val[3][2]); `SET_2D(val); endfunction - function void e_logic7_3d(output logic7_array_t val); `SET_3D(val); endfunction - function void e_logic7_1d1(output logic[6:0] val[1]); `SET_1D1(val); endfunction - function void e_logic7_2d1(output logic[6:0] val[1][1]); `SET_2D1(val); endfunction - function void e_logic7_3d1(output logic7_array1_t val); `SET_3D1(val); endfunction + function void e_logic7_0d(output logic[6:0] val); `SET_0D(val); endfunction + function void e_logic7_1d(output logic[6:0] val[2]); `SET_1D(val); endfunction + function void e_logic7_2d(output logic[6:0] val[3][2]); `SET_2D(val); endfunction + function void e_logic7_3d(output logic7_array_t val); `SET_3D(val); endfunction + function void e_logic7_1d1(output logic[6:0] val[1]); `SET_1D1(val); endfunction + function void e_logic7_2d1(output logic[6:0] val[1][1]); `SET_2D1(val); endfunction + function void e_logic7_3d1(output logic7_array1_t val); `SET_3D1(val); endfunction - function void e_logic121_0d(output logic[120:0] val); `SET_0D(val); endfunction - function void e_logic121_1d(output logic[120:0] val[2]); `SET_1D(val); endfunction - function void e_logic121_2d(output logic[120:0] val[3][2]); `SET_2D(val); endfunction - function void e_logic121_3d(output logic121_array_t val); `SET_3D(val); endfunction - function void e_logic121_1d1(output logic[120:0] val[1]); `SET_1D1(val); endfunction - function void e_logic121_2d1(output logic[120:0] val[1][1]); `SET_2D1(val); endfunction - function void e_logic121_3d1(output logic121_array1_t val); `SET_3D1(val); endfunction + function void e_logic121_0d(output logic[120:0] val); `SET_0D(val); endfunction + function void e_logic121_1d(output logic[120:0] val[2]); `SET_1D(val); endfunction + function void e_logic121_2d(output logic[120:0] val[3][2]); `SET_2D(val); endfunction + function void e_logic121_3d(output logic121_array_t val); `SET_3D(val); endfunction + function void e_logic121_1d1(output logic[120:0] val[1]); `SET_1D1(val); endfunction + function void e_logic121_2d1(output logic[120:0] val[1][1]); `SET_2D1(val); endfunction + function void e_logic121_3d1(output logic121_array1_t val); `SET_3D1(val); endfunction - function void e_pack_struct_0d(output pack_struct_t val); `SET_0D(val); endfunction - function void e_pack_struct_1d(output pack_struct_t val[2]); `SET_1D(val); endfunction - function void e_pack_struct_2d(output pack_struct_t val[3][2]); `SET_2D(val); endfunction - function void e_pack_struct_3d(output pack_struct_array_t val); `SET_3D(val); endfunction - function void e_pack_struct_1d1(output pack_struct_t val[1]); `SET_1D1(val); endfunction - function void e_pack_struct_2d1(output pack_struct_t val[1][1]); `SET_2D1(val); endfunction - function void e_pack_struct_3d1(output pack_struct_array1_t val); `SET_3D1(val); endfunction + function void e_pack_struct_0d(output pack_struct_t val); `SET_0D(val); endfunction + function void e_pack_struct_1d(output pack_struct_t val[2]); `SET_1D(val); endfunction + function void e_pack_struct_2d(output pack_struct_t val[3][2]); `SET_2D(val); endfunction + function void e_pack_struct_3d(output pack_struct_array_t val); `SET_3D(val); endfunction + function void e_pack_struct_1d1(output pack_struct_t val[1]); `SET_1D1(val); endfunction + function void e_pack_struct_2d1(output pack_struct_t val[1][1]); `SET_2D1(val); endfunction + function void e_pack_struct_3d1(output pack_struct_array1_t val); `SET_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT - function void e_unpack_struct_0d(output unpack_struct_t val); - val.val = 42; - endfunction - function void e_unpack_struct_1d(output unpack_struct_t val[2]); - val[0].val = 43; - val[1].val = 44; - endfunction - function void e_unpack_struct_2d(output unpack_struct_t val[3][2]); - val[0][1].val = 45; - val[1][1].val = 46; - val[2][1].val = 47; - endfunction - function void e_unpack_struct_3d(output unpack_struct_array_t val); - val[0][0][0].val = 48; - val[1][0][0].val = 49; - val[2][0][0].val = 50; - val[3][0][0].val = 51; - endfunction - function void e_unpack_struct_1d1(output unpack_struct_t val[1]); - val[0].val = 52; - endfunction - function void e_unpack_struct_2d1(output unpack_struct_t val[1][1]); - val[0][0].val = 53; - endfunction - function void e_unpack_struct_3d1(output unpack_struct_array1_t val); - val[0][0][0].val = 54; - endfunction + function void e_unpack_struct_0d(output unpack_struct_t val); + val.val = 42; + endfunction + function void e_unpack_struct_1d(output unpack_struct_t val[2]); + val[0].val = 43; + val[1].val = 44; + endfunction + function void e_unpack_struct_2d(output unpack_struct_t val[3][2]); + val[0][1].val = 45; + val[1][1].val = 46; + val[2][1].val = 47; + endfunction + function void e_unpack_struct_3d(output unpack_struct_array_t val); + val[0][0][0].val = 48; + val[1][0][0].val = 49; + val[2][0][0].val = 50; + val[3][0][0].val = 51; + endfunction + function void e_unpack_struct_1d1(output unpack_struct_t val[1]); + val[0].val = 52; + endfunction + function void e_unpack_struct_2d1(output unpack_struct_t val[1][1]); + val[0][0].val = 53; + endfunction + function void e_unpack_struct_3d1(output unpack_struct_array1_t val); + val[0][0][0].val = 54; + endfunction `endif - //====================================================================== - // Invoke all imported functions - //====================================================================== + //====================================================================== + // Invoke all imported functions + //====================================================================== - import "DPI-C" context function void check_exports(); + import "DPI-C" context function void check_exports(); - initial begin - byte_array_t byte_array; - byte_array1_t byte_array1; - byte_unsigned_array_t byte_unsigned_array; - byte_unsigned_array1_t byte_unsigned_array1; - shortint_array_t shortint_array; - shortint_array1_t shortint_array1; - shortint_unsigned_array_t shortint_unsigned_array; - shortint_unsigned_array1_t shortint_unsigned_array1; - int_array_t int_array; - int_array1_t int_array1; - int_unsigned_array_t int_unsigned_array; - int_unsigned_array1_t int_unsigned_array1; - longint_array_t longint_array; - longint_array1_t longint_array1; - longint_unsigned_array_t longint_unsigned_array; - longint_unsigned_array1_t longint_unsigned_array1; + initial begin + byte_array_t byte_array; + byte_array1_t byte_array1; + byte_unsigned_array_t byte_unsigned_array; + byte_unsigned_array1_t byte_unsigned_array1; + shortint_array_t shortint_array; + shortint_array1_t shortint_array1; + shortint_unsigned_array_t shortint_unsigned_array; + shortint_unsigned_array1_t shortint_unsigned_array1; + int_array_t int_array; + int_array1_t int_array1; + int_unsigned_array_t int_unsigned_array; + int_unsigned_array1_t int_unsigned_array1; + longint_array_t longint_array; + longint_array1_t longint_array1; + longint_unsigned_array_t longint_unsigned_array; + longint_unsigned_array1_t longint_unsigned_array1; `ifndef NO_TIME - time_array_t time_array; - time_array1_t time_array1; + time_array_t time_array; + time_array1_t time_array1; `endif `ifndef NO_INTEGER - integer_array_t integer_array; - integer_array1_t integer_array1; + integer_array_t integer_array; + integer_array1_t integer_array1; `endif - real_array_t real_array; - real_array1_t real_array1; + real_array_t real_array; + real_array1_t real_array1; `ifndef NO_SHORTREAL - shortreal_array_t shortreal_array; - shortreal_array1_t shortreal_array1; + shortreal_array_t shortreal_array; + shortreal_array1_t shortreal_array1; `endif - chandle_array_t chandle_array; - chandle_array1_t chandle_array1; - string_array_t string_array; - string_array1_t string_array1; - bit1_array_t bit1_array; - bit1_array1_t bit1_array1; - bit7_array_t bit7_array; - bit7_array1_t bit7_array1; - bit121_array_t bit121_array; - bit121_array1_t bit121_array1; - logic1_array_t logic1_array; - logic1_array1_t logic1_array1; - logic7_array_t logic7_array; - logic7_array1_t logic7_array1; - logic121_array_t logic121_array; - logic121_array1_t logic121_array1; - pack_struct_array_t pack_struct_array; - pack_struct_array1_t pack_struct_array1; + chandle_array_t chandle_array; + chandle_array1_t chandle_array1; + string_array_t string_array; + string_array1_t string_array1; + bit1_array_t bit1_array; + bit1_array1_t bit1_array1; + bit7_array_t bit7_array; + bit7_array1_t bit7_array1; + bit121_array_t bit121_array; + bit121_array1_t bit121_array1; + logic1_array_t logic1_array; + logic1_array1_t logic1_array1; + logic7_array_t logic7_array; + logic7_array1_t logic7_array1; + logic121_array_t logic121_array; + logic121_array1_t logic121_array1; + pack_struct_array_t pack_struct_array; + pack_struct_array1_t pack_struct_array1; `ifndef NO_UNPACK_STRUCT - unpack_struct_array_t unpack_struct_array; - unpack_struct_array1_t unpack_struct_array1; + unpack_struct_array_t unpack_struct_array; + unpack_struct_array1_t unpack_struct_array1; `endif - i_byte_0d(byte_array[3][2][1]); - `CHECK_0D(byte_array[3][2][1]); - i_byte_1d(byte_array[2][1]); - `CHECK_1D(byte_array[2][1]); - i_byte_2d(byte_array[1]); - `CHECK_2D(byte_array[1]); - i_byte_3d(byte_array); - `CHECK_3D(byte_array); + i_byte_0d(byte_array[3][2][1]); + `CHECK_0D(byte_array[3][2][1]); + i_byte_1d(byte_array[2][1]); + `CHECK_1D(byte_array[2][1]); + i_byte_2d(byte_array[1]); + `CHECK_2D(byte_array[1]); + i_byte_3d(byte_array); + `CHECK_3D(byte_array); - i_byte_1d1(byte_array1[0][0]); - `CHECK_1D1(byte_array1[0][0]); - i_byte_2d1(byte_array1[0]); - `CHECK_2D1(byte_array1[0]); - i_byte_3d1(byte_array1); - `CHECK_3D1(byte_array1); + i_byte_1d1(byte_array1[0][0]); + `CHECK_1D1(byte_array1[0][0]); + i_byte_2d1(byte_array1[0]); + `CHECK_2D1(byte_array1[0]); + i_byte_3d1(byte_array1); + `CHECK_3D1(byte_array1); - i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); - `CHECK_0D(byte_unsigned_array[3][2][1]); - i_byte_unsigned_1d(byte_unsigned_array[2][1]); - `CHECK_1D(byte_unsigned_array[2][1]); - i_byte_unsigned_2d(byte_unsigned_array[1]); - `CHECK_2D(byte_unsigned_array[1]); - i_byte_unsigned_3d(byte_unsigned_array); - `CHECK_3D(byte_unsigned_array); + i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); + `CHECK_0D(byte_unsigned_array[3][2][1]); + i_byte_unsigned_1d(byte_unsigned_array[2][1]); + `CHECK_1D(byte_unsigned_array[2][1]); + i_byte_unsigned_2d(byte_unsigned_array[1]); + `CHECK_2D(byte_unsigned_array[1]); + i_byte_unsigned_3d(byte_unsigned_array); + `CHECK_3D(byte_unsigned_array); - i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); - `CHECK_1D1(byte_unsigned_array1[0][0]); - i_byte_unsigned_2d1(byte_unsigned_array1[0]); - `CHECK_2D1(byte_unsigned_array1[0]); - i_byte_unsigned_3d1(byte_unsigned_array1); - `CHECK_3D1(byte_unsigned_array1); + i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); + `CHECK_1D1(byte_unsigned_array1[0][0]); + i_byte_unsigned_2d1(byte_unsigned_array1[0]); + `CHECK_2D1(byte_unsigned_array1[0]); + i_byte_unsigned_3d1(byte_unsigned_array1); + `CHECK_3D1(byte_unsigned_array1); - i_shortint_0d(shortint_array[3][2][1]); - `CHECK_0D(shortint_array[3][2][1]); - i_shortint_1d(shortint_array[2][1]); - `CHECK_1D(shortint_array[2][1]); - i_shortint_2d(shortint_array[1]); - `CHECK_2D(shortint_array[1]); - i_shortint_3d(shortint_array); - `CHECK_3D(shortint_array); + i_shortint_0d(shortint_array[3][2][1]); + `CHECK_0D(shortint_array[3][2][1]); + i_shortint_1d(shortint_array[2][1]); + `CHECK_1D(shortint_array[2][1]); + i_shortint_2d(shortint_array[1]); + `CHECK_2D(shortint_array[1]); + i_shortint_3d(shortint_array); + `CHECK_3D(shortint_array); - i_shortint_1d1(shortint_array1[0][0]); - `CHECK_1D1(shortint_array1[0][0]); - i_shortint_2d1(shortint_array1[0]); - `CHECK_2D1(shortint_array1[0]); - i_shortint_3d1(shortint_array1); - `CHECK_3D1(shortint_array1); + i_shortint_1d1(shortint_array1[0][0]); + `CHECK_1D1(shortint_array1[0][0]); + i_shortint_2d1(shortint_array1[0]); + `CHECK_2D1(shortint_array1[0]); + i_shortint_3d1(shortint_array1); + `CHECK_3D1(shortint_array1); - i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); - `CHECK_0D(shortint_unsigned_array[3][2][1]); - i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); - `CHECK_1D(shortint_unsigned_array[2][1]); - i_shortint_unsigned_2d(shortint_unsigned_array[1]); - `CHECK_2D(shortint_unsigned_array[1]); - i_shortint_unsigned_3d(shortint_unsigned_array); - `CHECK_3D(shortint_unsigned_array); + i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); + `CHECK_0D(shortint_unsigned_array[3][2][1]); + i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); + `CHECK_1D(shortint_unsigned_array[2][1]); + i_shortint_unsigned_2d(shortint_unsigned_array[1]); + `CHECK_2D(shortint_unsigned_array[1]); + i_shortint_unsigned_3d(shortint_unsigned_array); + `CHECK_3D(shortint_unsigned_array); - i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); - `CHECK_1D1(shortint_unsigned_array1[0][0]); - i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); - `CHECK_2D1(shortint_unsigned_array1[0]); - i_shortint_unsigned_3d1(shortint_unsigned_array1); - `CHECK_3D1(shortint_unsigned_array1); + i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); + `CHECK_1D1(shortint_unsigned_array1[0][0]); + i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); + `CHECK_2D1(shortint_unsigned_array1[0]); + i_shortint_unsigned_3d1(shortint_unsigned_array1); + `CHECK_3D1(shortint_unsigned_array1); - i_int_0d(int_array[3][2][1]); - `CHECK_0D(int_array[3][2][1]); - i_int_1d(int_array[2][1]); - `CHECK_1D(int_array[2][1]); - i_int_2d(int_array[1]); - `CHECK_2D(int_array[1]); - i_int_3d(int_array); - `CHECK_3D(int_array); + i_int_0d(int_array[3][2][1]); + `CHECK_0D(int_array[3][2][1]); + i_int_1d(int_array[2][1]); + `CHECK_1D(int_array[2][1]); + i_int_2d(int_array[1]); + `CHECK_2D(int_array[1]); + i_int_3d(int_array); + `CHECK_3D(int_array); - i_int_1d1(int_array1[0][0]); - `CHECK_1D1(int_array1[0][0]); - i_int_2d1(int_array1[0]); - `CHECK_2D1(int_array1[0]); - i_int_3d1(int_array1); - `CHECK_3D1(int_array1); + i_int_1d1(int_array1[0][0]); + `CHECK_1D1(int_array1[0][0]); + i_int_2d1(int_array1[0]); + `CHECK_2D1(int_array1[0]); + i_int_3d1(int_array1); + `CHECK_3D1(int_array1); - i_int_unsigned_0d(int_unsigned_array[3][2][1]); - `CHECK_0D(int_unsigned_array[3][2][1]); - i_int_unsigned_1d(int_unsigned_array[2][1]); - `CHECK_1D(int_unsigned_array[2][1]); - i_int_unsigned_2d(int_unsigned_array[1]); - `CHECK_2D(int_unsigned_array[1]); - i_int_unsigned_3d(int_unsigned_array); - `CHECK_3D(int_unsigned_array); + i_int_unsigned_0d(int_unsigned_array[3][2][1]); + `CHECK_0D(int_unsigned_array[3][2][1]); + i_int_unsigned_1d(int_unsigned_array[2][1]); + `CHECK_1D(int_unsigned_array[2][1]); + i_int_unsigned_2d(int_unsigned_array[1]); + `CHECK_2D(int_unsigned_array[1]); + i_int_unsigned_3d(int_unsigned_array); + `CHECK_3D(int_unsigned_array); - i_int_unsigned_1d1(int_unsigned_array1[0][0]); - `CHECK_1D1(int_unsigned_array1[0][0]); - i_int_unsigned_2d1(int_unsigned_array1[0]); - `CHECK_2D1(int_unsigned_array1[0]); - i_int_unsigned_3d1(int_unsigned_array1); - `CHECK_3D1(int_unsigned_array1); + i_int_unsigned_1d1(int_unsigned_array1[0][0]); + `CHECK_1D1(int_unsigned_array1[0][0]); + i_int_unsigned_2d1(int_unsigned_array1[0]); + `CHECK_2D1(int_unsigned_array1[0]); + i_int_unsigned_3d1(int_unsigned_array1); + `CHECK_3D1(int_unsigned_array1); - i_longint_0d(longint_array[3][2][1]); - `CHECK_0D(longint_array[3][2][1]); - i_longint_1d(longint_array[2][1]); - `CHECK_1D(longint_array[2][1]); - i_longint_2d(longint_array[1]); - `CHECK_2D(longint_array[1]); - i_longint_3d(longint_array); - `CHECK_3D(longint_array); + i_longint_0d(longint_array[3][2][1]); + `CHECK_0D(longint_array[3][2][1]); + i_longint_1d(longint_array[2][1]); + `CHECK_1D(longint_array[2][1]); + i_longint_2d(longint_array[1]); + `CHECK_2D(longint_array[1]); + i_longint_3d(longint_array); + `CHECK_3D(longint_array); - i_longint_1d1(longint_array1[0][0]); - `CHECK_1D1(longint_array1[0][0]); - i_longint_2d1(longint_array1[0]); - `CHECK_2D1(longint_array1[0]); - i_longint_3d1(longint_array1); - `CHECK_3D1(longint_array1); + i_longint_1d1(longint_array1[0][0]); + `CHECK_1D1(longint_array1[0][0]); + i_longint_2d1(longint_array1[0]); + `CHECK_2D1(longint_array1[0]); + i_longint_3d1(longint_array1); + `CHECK_3D1(longint_array1); - i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); - `CHECK_0D(longint_unsigned_array[3][2][1]); - i_longint_unsigned_1d(longint_unsigned_array[2][1]); - `CHECK_1D(longint_unsigned_array[2][1]); - i_longint_unsigned_2d(longint_unsigned_array[1]); - `CHECK_2D(longint_unsigned_array[1]); - i_longint_unsigned_3d(longint_unsigned_array); - `CHECK_3D(longint_unsigned_array); + i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); + `CHECK_0D(longint_unsigned_array[3][2][1]); + i_longint_unsigned_1d(longint_unsigned_array[2][1]); + `CHECK_1D(longint_unsigned_array[2][1]); + i_longint_unsigned_2d(longint_unsigned_array[1]); + `CHECK_2D(longint_unsigned_array[1]); + i_longint_unsigned_3d(longint_unsigned_array); + `CHECK_3D(longint_unsigned_array); - i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); - `CHECK_1D1(longint_unsigned_array1[0][0]); - i_longint_unsigned_2d1(longint_unsigned_array1[0]); - `CHECK_2D1(longint_unsigned_array1[0]); - i_longint_unsigned_3d1(longint_unsigned_array1); - `CHECK_3D1(longint_unsigned_array1); + i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); + `CHECK_1D1(longint_unsigned_array1[0][0]); + i_longint_unsigned_2d1(longint_unsigned_array1[0]); + `CHECK_2D1(longint_unsigned_array1[0]); + i_longint_unsigned_3d1(longint_unsigned_array1); + `CHECK_3D1(longint_unsigned_array1); `ifndef NO_TIME - i_time_0d(time_array[3][2][1]); - `CHECK_0D(time_array[3][2][1]); - i_time_1d(time_array[2][1]); - `CHECK_1D(time_array[2][1]); - i_time_2d(time_array[1]); - `CHECK_2D(time_array[1]); - i_time_3d(time_array); - `CHECK_3D(time_array); + i_time_0d(time_array[3][2][1]); + `CHECK_0D(time_array[3][2][1]); + i_time_1d(time_array[2][1]); + `CHECK_1D(time_array[2][1]); + i_time_2d(time_array[1]); + `CHECK_2D(time_array[1]); + i_time_3d(time_array); + `CHECK_3D(time_array); - i_time_1d1(time_array1[0][0]); - `CHECK_1D1(time_array1[0][0]); - i_time_2d1(time_array1[0]); - `CHECK_2D1(time_array1[0]); - i_time_3d1(time_array1); - `CHECK_3D1(time_array1); + i_time_1d1(time_array1[0][0]); + `CHECK_1D1(time_array1[0][0]); + i_time_2d1(time_array1[0]); + `CHECK_2D1(time_array1[0]); + i_time_3d1(time_array1); + `CHECK_3D1(time_array1); `endif `ifndef NO_INTEGER - i_integer_0d(integer_array[3][2][1]); - `CHECK_0D(integer_array[3][2][1]); - i_integer_1d(integer_array[2][1]); - `CHECK_1D(integer_array[2][1]); - i_integer_2d(integer_array[1]); - `CHECK_2D(integer_array[1]); - i_integer_3d(integer_array); - `CHECK_3D(integer_array); + i_integer_0d(integer_array[3][2][1]); + `CHECK_0D(integer_array[3][2][1]); + i_integer_1d(integer_array[2][1]); + `CHECK_1D(integer_array[2][1]); + i_integer_2d(integer_array[1]); + `CHECK_2D(integer_array[1]); + i_integer_3d(integer_array); + `CHECK_3D(integer_array); - i_integer_1d1(integer_array1[0][0]); - `CHECK_1D1(integer_array1[0][0]); - i_integer_2d1(integer_array1[0]); - `CHECK_2D1(integer_array1[0]); - i_integer_3d1(integer_array1); - `CHECK_3D1(integer_array1); + i_integer_1d1(integer_array1[0][0]); + `CHECK_1D1(integer_array1[0][0]); + i_integer_2d1(integer_array1[0]); + `CHECK_2D1(integer_array1[0]); + i_integer_3d1(integer_array1); + `CHECK_3D1(integer_array1); `endif - i_real_0d(real_array[3][2][1]); - `CHECK_0D(real_array[3][2][1]); - i_real_1d(real_array[2][1]); - `CHECK_1D(real_array[2][1]); - i_real_2d(real_array[1]); - `CHECK_2D(real_array[1]); - i_real_3d(real_array); - `CHECK_3D(real_array); + i_real_0d(real_array[3][2][1]); + `CHECK_0D(real_array[3][2][1]); + i_real_1d(real_array[2][1]); + `CHECK_1D(real_array[2][1]); + i_real_2d(real_array[1]); + `CHECK_2D(real_array[1]); + i_real_3d(real_array); + `CHECK_3D(real_array); - i_real_1d1(real_array1[0][0]); - `CHECK_1D1(real_array1[0][0]); - i_real_2d1(real_array1[0]); - `CHECK_2D1(real_array1[0]); - i_real_3d1(real_array1); - `CHECK_3D1(real_array1); + i_real_1d1(real_array1[0][0]); + `CHECK_1D1(real_array1[0][0]); + i_real_2d1(real_array1[0]); + `CHECK_2D1(real_array1[0]); + i_real_3d1(real_array1); + `CHECK_3D1(real_array1); `ifndef NO_SHORTREAL - i_shortreal_0d(shortreal_array[3][2][1]); - `CHECK_0D(shortreal_array[3][2][1]); - i_shortreal_1d(shortreal_array[2][1]); - `CHECK_1D(shortreal_array[2][1]); - i_shortreal_2d(shortreal_array[1]); - `CHECK_2D(shortreal_array[1]); - i_shortreal_3d(shortreal_array); - `CHECK_3D(shortreal_array); + i_shortreal_0d(shortreal_array[3][2][1]); + `CHECK_0D(shortreal_array[3][2][1]); + i_shortreal_1d(shortreal_array[2][1]); + `CHECK_1D(shortreal_array[2][1]); + i_shortreal_2d(shortreal_array[1]); + `CHECK_2D(shortreal_array[1]); + i_shortreal_3d(shortreal_array); + `CHECK_3D(shortreal_array); - i_shortreal_1d1(shortreal_array1[0][0]); - `CHECK_1D1(shortreal_array1[0][0]); - i_shortreal_2d1(shortreal_array1[0]); - `CHECK_2D1(shortreal_array1[0]); - i_shortreal_3d1(shortreal_array1); - `CHECK_3D1(shortreal_array1); + i_shortreal_1d1(shortreal_array1[0][0]); + `CHECK_1D1(shortreal_array1[0][0]); + i_shortreal_2d1(shortreal_array1[0]); + `CHECK_2D1(shortreal_array1[0]); + i_shortreal_3d1(shortreal_array1); + `CHECK_3D1(shortreal_array1); `endif - for (int i = 0; i < 4; ++i) - for (int j = 0; j < 3; ++j) - for (int k = 0; k < 2; ++k) - chandle_array[i][j][k] = null; - i_chandle_0d(chandle_array[3][2][1]); - `CHECK_CHANDLE_VAL(chandle_array[3][2][1], get_non_null()); - i_chandle_1d(chandle_array[2][1]); - `CHECK_CHANDLE_VAL(chandle_array[2][1][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[2][1][1], get_non_null()); - i_chandle_2d(chandle_array[1]); - `CHECK_CHANDLE_VAL(chandle_array[1][0][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[1][1][1], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[1][2][1], get_non_null()); - i_chandle_3d(chandle_array); - `CHECK_CHANDLE_VAL(chandle_array[0][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[1][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[2][0][0], get_non_null()); - `CHECK_CHANDLE_VAL(chandle_array[3][0][0], get_non_null()); + for (int i = 0; i < 4; ++i) + for (int j = 0; j < 3; ++j) + for (int k = 0; k < 2; ++k) + chandle_array[i][j][k] = null; + i_chandle_0d(chandle_array[3][2][1]); + `CHECK_CHANDLE_VAL(chandle_array[3][2][1], get_non_null()); + i_chandle_1d(chandle_array[2][1]); + `CHECK_CHANDLE_VAL(chandle_array[2][1][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[2][1][1], get_non_null()); + i_chandle_2d(chandle_array[1]); + `CHECK_CHANDLE_VAL(chandle_array[1][0][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[1][1][1], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[1][2][1], get_non_null()); + i_chandle_3d(chandle_array); + `CHECK_CHANDLE_VAL(chandle_array[0][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[1][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[2][0][0], get_non_null()); + `CHECK_CHANDLE_VAL(chandle_array[3][0][0], get_non_null()); - i_chandle_1d1(chandle_array1[0][0]); - `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); - i_chandle_2d1(chandle_array1[0]); - `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); - i_chandle_3d1(chandle_array1); - `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); + i_chandle_1d1(chandle_array1[0][0]); + `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); + i_chandle_2d1(chandle_array1[0]); + `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); + i_chandle_3d1(chandle_array1); + `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); - i_string_0d(string_array[3][2][1]); - `CHECK_STRING_VAL(string_array[3][2][1], "42"); - i_string_1d(string_array[2][1]); - `CHECK_STRING_VAL(string_array[2][1][0], "43"); - `CHECK_STRING_VAL(string_array[2][1][1], "44"); - i_string_2d(string_array[1]); - `CHECK_STRING_VAL(string_array[1][0][1], "45"); - `CHECK_STRING_VAL(string_array[1][1][1], "46"); - `CHECK_STRING_VAL(string_array[1][2][1], "47"); - i_string_3d(string_array); - `CHECK_STRING_VAL(string_array[0][0][0], "48"); - `CHECK_STRING_VAL(string_array[1][0][0], "49"); - `CHECK_STRING_VAL(string_array[2][0][0], "50"); - `CHECK_STRING_VAL(string_array[3][0][0], "51"); + i_string_0d(string_array[3][2][1]); + `CHECK_STRING_VAL(string_array[3][2][1], "42"); + i_string_1d(string_array[2][1]); + `CHECK_STRING_VAL(string_array[2][1][0], "43"); + `CHECK_STRING_VAL(string_array[2][1][1], "44"); + i_string_2d(string_array[1]); + `CHECK_STRING_VAL(string_array[1][0][1], "45"); + `CHECK_STRING_VAL(string_array[1][1][1], "46"); + `CHECK_STRING_VAL(string_array[1][2][1], "47"); + i_string_3d(string_array); + `CHECK_STRING_VAL(string_array[0][0][0], "48"); + `CHECK_STRING_VAL(string_array[1][0][0], "49"); + `CHECK_STRING_VAL(string_array[2][0][0], "50"); + `CHECK_STRING_VAL(string_array[3][0][0], "51"); - i_string_1d1(string_array1[0][0]); - `CHECK_STRING_VAL(string_array1[0][0][0], "52"); - i_string_2d1(string_array1[0]); - `CHECK_STRING_VAL(string_array1[0][0][0], "53"); - i_string_3d1(string_array1); - `CHECK_STRING_VAL(string_array1[0][0][0], "54"); + i_string_1d1(string_array1[0][0]); + `CHECK_STRING_VAL(string_array1[0][0][0], "52"); + i_string_2d1(string_array1[0]); + `CHECK_STRING_VAL(string_array1[0][0][0], "53"); + i_string_3d1(string_array1); + `CHECK_STRING_VAL(string_array1[0][0][0], "54"); - i_bit1_0d(bit1_array[3][2][1]); - `CHECK_0D(bit1_array[3][2][1]); - i_bit1_1d(bit1_array[2][1]); - `CHECK_1D(bit1_array[2][1]); - i_bit1_2d(bit1_array[1]); - `CHECK_2D(bit1_array[1]); - i_bit1_3d(bit1_array); - `CHECK_3D(bit1_array); + i_bit1_0d(bit1_array[3][2][1]); + `CHECK_0D(bit1_array[3][2][1]); + i_bit1_1d(bit1_array[2][1]); + `CHECK_1D(bit1_array[2][1]); + i_bit1_2d(bit1_array[1]); + `CHECK_2D(bit1_array[1]); + i_bit1_3d(bit1_array); + `CHECK_3D(bit1_array); - i_bit1_1d1(bit1_array1[0][0]); - `CHECK_1D1(bit1_array1[0][0]); - i_bit1_2d1(bit1_array1[0]); - `CHECK_2D1(bit1_array1[0]); - i_bit1_3d1(bit1_array1); - `CHECK_3D1(bit1_array1); + i_bit1_1d1(bit1_array1[0][0]); + `CHECK_1D1(bit1_array1[0][0]); + i_bit1_2d1(bit1_array1[0]); + `CHECK_2D1(bit1_array1[0]); + i_bit1_3d1(bit1_array1); + `CHECK_3D1(bit1_array1); - i_bit7_0d(bit7_array[3][2][1]); - `CHECK_0D(bit7_array[3][2][1]); - i_bit7_1d(bit7_array[2][1]); - `CHECK_1D(bit7_array[2][1]); - i_bit7_2d(bit7_array[1]); - `CHECK_2D(bit7_array[1]); - i_bit7_3d(bit7_array); - `CHECK_3D(bit7_array); + i_bit7_0d(bit7_array[3][2][1]); + `CHECK_0D(bit7_array[3][2][1]); + i_bit7_1d(bit7_array[2][1]); + `CHECK_1D(bit7_array[2][1]); + i_bit7_2d(bit7_array[1]); + `CHECK_2D(bit7_array[1]); + i_bit7_3d(bit7_array); + `CHECK_3D(bit7_array); - i_bit7_1d1(bit7_array1[0][0]); - `CHECK_1D1(bit7_array1[0][0]); - i_bit7_2d1(bit7_array1[0]); - `CHECK_2D1(bit7_array1[0]); - i_bit7_3d1(bit7_array1); - `CHECK_3D1(bit7_array1); + i_bit7_1d1(bit7_array1[0][0]); + `CHECK_1D1(bit7_array1[0][0]); + i_bit7_2d1(bit7_array1[0]); + `CHECK_2D1(bit7_array1[0]); + i_bit7_3d1(bit7_array1); + `CHECK_3D1(bit7_array1); - i_bit121_0d(bit121_array[3][2][1]); - `CHECK_0D(bit121_array[3][2][1]); - i_bit121_1d(bit121_array[2][1]); - `CHECK_1D(bit121_array[2][1]); - i_bit121_2d(bit121_array[1]); - `CHECK_2D(bit121_array[1]); - i_bit121_3d(bit121_array); - `CHECK_3D(bit121_array); + i_bit121_0d(bit121_array[3][2][1]); + `CHECK_0D(bit121_array[3][2][1]); + i_bit121_1d(bit121_array[2][1]); + `CHECK_1D(bit121_array[2][1]); + i_bit121_2d(bit121_array[1]); + `CHECK_2D(bit121_array[1]); + i_bit121_3d(bit121_array); + `CHECK_3D(bit121_array); - i_bit121_1d1(bit121_array1[0][0]); - `CHECK_1D1(bit121_array1[0][0]); - i_bit121_2d1(bit121_array1[0]); - `CHECK_2D1(bit121_array1[0]); - i_bit121_3d1(bit121_array1); - `CHECK_3D1(bit121_array1); + i_bit121_1d1(bit121_array1[0][0]); + `CHECK_1D1(bit121_array1[0][0]); + i_bit121_2d1(bit121_array1[0]); + `CHECK_2D1(bit121_array1[0]); + i_bit121_3d1(bit121_array1); + `CHECK_3D1(bit121_array1); - i_logic1_0d(logic1_array[3][2][1]); - `CHECK_0D(logic1_array[3][2][1]); - i_logic1_1d(logic1_array[2][1]); - `CHECK_1D(logic1_array[2][1]); - i_logic1_2d(logic1_array[1]); - `CHECK_2D(logic1_array[1]); - i_logic1_3d(logic1_array); - `CHECK_3D(logic1_array); + i_logic1_0d(logic1_array[3][2][1]); + `CHECK_0D(logic1_array[3][2][1]); + i_logic1_1d(logic1_array[2][1]); + `CHECK_1D(logic1_array[2][1]); + i_logic1_2d(logic1_array[1]); + `CHECK_2D(logic1_array[1]); + i_logic1_3d(logic1_array); + `CHECK_3D(logic1_array); - i_logic1_1d1(logic1_array1[0][0]); - `CHECK_1D1(logic1_array1[0][0]); - i_logic1_2d1(logic1_array1[0]); - `CHECK_2D1(logic1_array1[0]); - i_logic1_3d1(logic1_array1); - `CHECK_3D1(logic1_array1); + i_logic1_1d1(logic1_array1[0][0]); + `CHECK_1D1(logic1_array1[0][0]); + i_logic1_2d1(logic1_array1[0]); + `CHECK_2D1(logic1_array1[0]); + i_logic1_3d1(logic1_array1); + `CHECK_3D1(logic1_array1); - i_logic7_0d(logic7_array[3][2][1]); - `CHECK_0D(logic7_array[3][2][1]); - i_logic7_1d(logic7_array[2][1]); - `CHECK_1D(logic7_array[2][1]); - i_logic7_2d(logic7_array[1]); - `CHECK_2D(logic7_array[1]); - i_logic7_3d(logic7_array); - `CHECK_3D(logic7_array); + i_logic7_0d(logic7_array[3][2][1]); + `CHECK_0D(logic7_array[3][2][1]); + i_logic7_1d(logic7_array[2][1]); + `CHECK_1D(logic7_array[2][1]); + i_logic7_2d(logic7_array[1]); + `CHECK_2D(logic7_array[1]); + i_logic7_3d(logic7_array); + `CHECK_3D(logic7_array); - i_logic7_1d1(logic7_array1[0][0]); - `CHECK_1D1(logic7_array1[0][0]); - i_logic7_2d1(logic7_array1[0]); - `CHECK_2D1(logic7_array1[0]); - i_logic7_3d1(logic7_array1); - `CHECK_3D1(logic7_array1); + i_logic7_1d1(logic7_array1[0][0]); + `CHECK_1D1(logic7_array1[0][0]); + i_logic7_2d1(logic7_array1[0]); + `CHECK_2D1(logic7_array1[0]); + i_logic7_3d1(logic7_array1); + `CHECK_3D1(logic7_array1); - i_logic121_0d(logic121_array[3][2][1]); - `CHECK_0D(logic121_array[3][2][1]); - i_logic121_1d(logic121_array[2][1]); - `CHECK_1D(logic121_array[2][1]); - i_logic121_2d(logic121_array[1]); - `CHECK_2D(logic121_array[1]); - i_logic121_3d(logic121_array); - `CHECK_3D(logic121_array); + i_logic121_0d(logic121_array[3][2][1]); + `CHECK_0D(logic121_array[3][2][1]); + i_logic121_1d(logic121_array[2][1]); + `CHECK_1D(logic121_array[2][1]); + i_logic121_2d(logic121_array[1]); + `CHECK_2D(logic121_array[1]); + i_logic121_3d(logic121_array); + `CHECK_3D(logic121_array); - i_logic121_1d1(logic121_array1[0][0]); - `CHECK_1D1(logic121_array1[0][0]); - i_logic121_2d1(logic121_array1[0]); - `CHECK_2D1(logic121_array1[0]); - i_logic121_3d1(logic121_array1); - `CHECK_3D1(logic121_array1); + i_logic121_1d1(logic121_array1[0][0]); + `CHECK_1D1(logic121_array1[0][0]); + i_logic121_2d1(logic121_array1[0]); + `CHECK_2D1(logic121_array1[0]); + i_logic121_3d1(logic121_array1); + `CHECK_3D1(logic121_array1); - i_pack_struct_0d(pack_struct_array[3][2][1]); - `CHECK_0D(pack_struct_array[3][2][1]); - i_pack_struct_1d(pack_struct_array[2][1]); - `CHECK_1D(pack_struct_array[2][1]); - i_pack_struct_2d(pack_struct_array[1]); - `CHECK_2D(pack_struct_array[1]); - i_pack_struct_3d(pack_struct_array); - `CHECK_3D(pack_struct_array); + i_pack_struct_0d(pack_struct_array[3][2][1]); + `CHECK_0D(pack_struct_array[3][2][1]); + i_pack_struct_1d(pack_struct_array[2][1]); + `CHECK_1D(pack_struct_array[2][1]); + i_pack_struct_2d(pack_struct_array[1]); + `CHECK_2D(pack_struct_array[1]); + i_pack_struct_3d(pack_struct_array); + `CHECK_3D(pack_struct_array); - i_pack_struct_1d1(pack_struct_array1[0][0]); - `CHECK_1D1(pack_struct_array1[0][0]); - i_pack_struct_2d1(pack_struct_array1[0]); - `CHECK_2D1(pack_struct_array1[0]); - i_pack_struct_3d1(pack_struct_array1); - `CHECK_3D1(pack_struct_array1); + i_pack_struct_1d1(pack_struct_array1[0][0]); + `CHECK_1D1(pack_struct_array1[0][0]); + i_pack_struct_2d1(pack_struct_array1[0]); + `CHECK_2D1(pack_struct_array1[0]); + i_pack_struct_3d1(pack_struct_array1); + `CHECK_3D1(pack_struct_array1); - `SET_VALUES(pack_struct_array); - i_pack_struct_0d(pack_struct_array[3][2][1]); - i_pack_struct_1d(pack_struct_array[2][1]); - i_pack_struct_2d(pack_struct_array[1]); - i_pack_struct_3d(pack_struct_array); + `SET_VALUES(pack_struct_array); + i_pack_struct_0d(pack_struct_array[3][2][1]); + i_pack_struct_1d(pack_struct_array[2][1]); + i_pack_struct_2d(pack_struct_array[1]); + i_pack_struct_3d(pack_struct_array); `ifndef NO_UNPACK_STRUCT - i_unpack_struct_0d(unpack_struct_array[3][2][1]); - `CHECK_VAL(unpack_struct_array[3][2][1].val, 42); + i_unpack_struct_0d(unpack_struct_array[3][2][1]); + `CHECK_VAL(unpack_struct_array[3][2][1].val, 42); - i_unpack_struct_1d(unpack_struct_array[2][1]); - `CHECK_VAL(unpack_struct_array[2][1][0].val, 43); - `CHECK_VAL(unpack_struct_array[2][1][1].val, 44); + i_unpack_struct_1d(unpack_struct_array[2][1]); + `CHECK_VAL(unpack_struct_array[2][1][0].val, 43); + `CHECK_VAL(unpack_struct_array[2][1][1].val, 44); - i_unpack_struct_2d(unpack_struct_array[1]); - `CHECK_VAL(unpack_struct_array[1][0][1].val, 45); - `CHECK_VAL(unpack_struct_array[1][1][1].val, 46); - `CHECK_VAL(unpack_struct_array[1][2][1].val, 47); + i_unpack_struct_2d(unpack_struct_array[1]); + `CHECK_VAL(unpack_struct_array[1][0][1].val, 45); + `CHECK_VAL(unpack_struct_array[1][1][1].val, 46); + `CHECK_VAL(unpack_struct_array[1][2][1].val, 47); - i_unpack_struct_3d(unpack_struct_array); - `CHECK_VAL(unpack_struct_array[0][0][0].val, 48); - `CHECK_VAL(unpack_struct_array[1][0][0].val, 49); - `CHECK_VAL(unpack_struct_array[2][0][0].val, 50); - `CHECK_VAL(unpack_struct_array[3][0][0].val, 51); + i_unpack_struct_3d(unpack_struct_array); + `CHECK_VAL(unpack_struct_array[0][0][0].val, 48); + `CHECK_VAL(unpack_struct_array[1][0][0].val, 49); + `CHECK_VAL(unpack_struct_array[2][0][0].val, 50); + `CHECK_VAL(unpack_struct_array[3][0][0].val, 51); - i_unpack_struct_1d1(unpack_struct_array1[0][0]); - `CHECK_VAL(unpack_struct_array1[0][0][0].val, 52); - i_unpack_struct_2d1(unpack_struct_array1[0]); - `CHECK_VAL(unpack_struct_array1[0][0][0].val, 53); - i_unpack_struct_3d1(unpack_struct_array1); - `CHECK_VAL(unpack_struct_array1[0][0][0].val, 54); + i_unpack_struct_1d1(unpack_struct_array1[0][0]); + `CHECK_VAL(unpack_struct_array1[0][0][0].val, 52); + i_unpack_struct_2d1(unpack_struct_array1[0]); + `CHECK_VAL(unpack_struct_array1[0][0][0].val, 53); + i_unpack_struct_3d1(unpack_struct_array1); + `CHECK_VAL(unpack_struct_array1[0][0][0].val, 54); `endif - check_exports(); - $write("*-* All Finished *-*\n"); - $finish; - end + check_exports(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_argtype_bad.out b/test_regress/t/t_dpi_argtype_bad.out index b6818d72d..f40089f41 100644 --- a/test_regress/t/t_dpi_argtype_bad.out +++ b/test_regress/t/t_dpi_argtype_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_dpi_argtype_bad.v:13:41: Unsupported: DPI argument of type REFDTYPE 'foo_t' +%Error-UNSUPPORTED: t/t_dpi_argtype_bad.v:16:40: Unsupported: DPI argument of type REFDTYPE 'foo_t' : ... For best portability, use bit, byte, int, or longint - 13 | import "DPI-C" task dpix_twice(foo_t arg); - | ^~~ + 16 | import "DPI-C" task dpix_twice(foo_t arg); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_dpi_argtype_bad.v b/test_regress/t/t_dpi_argtype_bad.v index f940448b4..f0afe58e8 100644 --- a/test_regress/t/t_dpi_argtype_bad.v +++ b/test_regress/t/t_dpi_argtype_bad.v @@ -8,10 +8,13 @@ module t; - typedef struct { string a; string b; } foo_t; + typedef struct { + string a; + string b; + } foo_t; - import "DPI-C" task dpix_twice(foo_t arg); - initial begin - $stop; - end + import "DPI-C" task dpix_twice(foo_t arg); + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_binary.v b/test_regress/t/t_dpi_binary.v index 5349afbea..31b5b490f 100644 --- a/test_regress/t/t_dpi_binary.v +++ b/test_regress/t/t_dpi_binary.v @@ -8,12 +8,12 @@ module t; - initial begin - // All Finished is in dpic_final - $finish; - end + initial begin + // All Finished is in dpic_final + $finish; + end - import "DPI-C" context function void dpic_final(); - final dpic_final(); + import "DPI-C" context function void dpic_final(); + final dpic_final(); endmodule diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v index 1b61b4b1e..5a489e48f 100644 --- a/test_regress/t/t_dpi_context.v +++ b/test_regress/t/t_dpi_context.v @@ -8,79 +8,79 @@ module t; - sub a (.inst(1)); - sub b (.inst(2)); + sub a (.inst(1)); + sub b (.inst(2)); - initial begin - a.test1; - b.test1; - a.test2; - b.test2; + initial begin + a.test1; + b.test1; + a.test2; + b.test2; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end - import "DPI-C" context function void dpic_final(); - final dpic_final(); + import "DPI-C" context function void dpic_final(); + final dpic_final(); endmodule module sub (input integer inst); - import "DPI-C" context function int dpic_line(); - import "DPI-C" context function int dpic_save(int value); - import "DPI-C" context function int dpic_restore(); - import "DPI-C" context function int unsigned dpic_getcontext(); - import "DPI-C" context function int unsigned dpic_get1(); + import "DPI-C" context function int dpic_line(); + import "DPI-C" context function int dpic_save(int value); + import "DPI-C" context function int dpic_restore(); + import "DPI-C" context function int unsigned dpic_getcontext(); + import "DPI-C" context function int unsigned dpic_get1(); - int result; + int result; - // Exports here are only to cover the export dumper of Verilated::internalsDump - export "DPI-C" function dpix_void; - function void dpix_void; - endfunction - export "DPI-C" function dpix_result; - function int dpix_result; - return result; - endfunction + // Exports here are only to cover the export dumper of Verilated::internalsDump + export "DPI-C" function dpix_void; + function void dpix_void; + endfunction + export "DPI-C" function dpix_result; + function int dpix_result; + return result; + endfunction - task test1; - // Check line numbering + task test1; + // Check line numbering `ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test - result = dpic_line(); if (!result) $stop; + result = dpic_line(); if (!result) $stop; `else - result = dpic_line(); if (result !== `__LINE__) $stop; - // - result = dpic_line(); if (result !== `__LINE__) $stop; + result = dpic_line(); if (result !== `__LINE__) $stop; + // + result = dpic_line(); if (result !== `__LINE__) $stop; `endif - // Check save-restore - result = dpic_save(23+inst); - if (result==0) $stop; - endtask + // Check save-restore + result = dpic_save(23+inst); + if (result==0) $stop; + endtask - task test2; - if (dpic_restore() != 23+inst) $stop; - endtask + task test2; + if (dpic_restore() != 23+inst) $stop; + endtask - function automatic int call_dpic_get1; - int res = dpic_get1(); - return res; - endfunction + function automatic int call_dpic_get1; + int res = dpic_get1(); + return res; + endfunction - int unsigned cntxt1; - int unsigned cntxt2; + int unsigned cntxt1; + int unsigned cntxt2; - initial begin - cntxt1 = dpic_getcontext(); - begin : caller_context - // call from a different scope - should still get the context of the function declaration - cntxt2 = dpic_getcontext(); - end - // svContext should be the context of the function declaration, not the context of the function call - if (cntxt1 != cntxt2) $stop; - if (call_dpic_get1() != 1) $stop; - end + initial begin + cntxt1 = dpic_getcontext(); + begin : caller_context + // call from a different scope - should still get the context of the function declaration + cntxt2 = dpic_getcontext(); + end + // svContext should be the context of the function declaration, not the context of the function call + if (cntxt1 != cntxt2) $stop; + if (call_dpic_get1() != 1) $stop; + end endmodule diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v index 61caa63f7..1ca28affe 100644 --- a/test_regress/t/t_dpi_display.v +++ b/test_regress/t/t_dpi_display.v @@ -9,31 +9,31 @@ module t; `ifndef VERILATOR - `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." + `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." `endif - import "DPI-C" context dpii_display_call - = function void \$dpii_display (input string formatted /*verilator sformat*/ ); + import "DPI-C" context dpii_display_call + = function void \$dpii_display (input string formatted /*verilator sformat*/ ); - integer a; + integer a; - initial begin - // Check variable width constant string conversions - $dpii_display(""); - $dpii_display("c"); - $dpii_display("co"); - $dpii_display("cons"); - $dpii_display("constant"); - $dpii_display("constant_value"); + initial begin + // Check variable width constant string conversions + $dpii_display(""); + $dpii_display("c"); + $dpii_display("co"); + $dpii_display("cons"); + $dpii_display("constant"); + $dpii_display("constant_value"); - a = $c("10"); // Don't optimize away "a" - $display ("one10=%x",a); // Check single arg - $dpii_display("one10=%x",a); - $display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg - $dpii_display("Mod=%m 16=%d 10=%x",a,a); + a = $c("10"); // Don't optimize away "a" + $display ("one10=%x",a); // Check single arg + $dpii_display("one10=%x",a); + $display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg + $dpii_display("Mod=%m 16=%d 10=%x",a,a); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_display_bad.out b/test_regress/t/t_dpi_display_bad.out index 778f34166..f55fa2454 100644 --- a/test_regress/t/t_dpi_display_bad.out +++ b/test_regress/t/t_dpi_display_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_dpi_display_bad.v:17:68: /*verilator sformat*/ can only be applied to last argument of a function - 17 | (input string formatted /*verilator sformat*/, input string other_bad ); - | ^~~~~~~~~ +%Error: t/t_dpi_display_bad.v:17:66: /*verilator sformat*/ can only be applied to last argument of a function + 17 | (input string formatted /*verilator sformat*/, input string other_bad ); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_display_bad.v b/test_regress/t/t_dpi_display_bad.v index 8e97f97f7..af003264b 100644 --- a/test_regress/t/t_dpi_display_bad.v +++ b/test_regress/t/t_dpi_display_bad.v @@ -9,16 +9,16 @@ module t; `ifndef VERILATOR - `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." + `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." `endif - import "DPI-C" context dpii_display_call - = function void \$dpii_display - (input string formatted /*verilator sformat*/, input string other_bad ); + import "DPI-C" context dpii_display_call + = function void \$dpii_display + (input string formatted /*verilator sformat*/, input string other_bad ); - initial begin - $dpii_display("hello", "huh"); - $stop; - end + initial begin + $dpii_display("hello", "huh"); + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_dup_bad.out b/test_regress/t/t_dpi_dup_bad.out index 155eee047..f901051f6 100644 --- a/test_regress/t/t_dpi_dup_bad.out +++ b/test_regress/t/t_dpi_dup_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_dpi_dup_bad.v:13:51: Duplicate declaration of DPI function with different signature: 'dpii_fa_bit' - 13 | import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); - | ^~~~~~~~~~ +%Error: t/t_dpi_dup_bad.v:13:50: Duplicate declaration of DPI function with different signature: 'dpii_fa_bit' + 13 | import "DPI-C" pure dpii_fa_bit = function int oth_f_int2( + | ^~~~~~~~~~ : ... New signature: pure int dpii_fa_bit (int, int) - t/t_dpi_dup_bad.v:12:47: ... Original signature: int dpii_fa_bit (int) - 12 | import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); - | ^~~~~~~~~~ + t/t_dpi_dup_bad.v:12:45: ... Original signature: int dpii_fa_bit (int) + 12 | import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_dup_bad.v b/test_regress/t/t_dpi_dup_bad.v index 358f00094..e55ff9959 100644 --- a/test_regress/t/t_dpi_dup_bad.v +++ b/test_regress/t/t_dpi_dup_bad.v @@ -8,12 +8,14 @@ module t; - // Same name w/ different args - import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); - import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); + // Same name w/ different args + import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + import "DPI-C" pure dpii_fa_bit = function int oth_f_int2( + input int i, + input int bad); - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_export.v b/test_regress/t/t_dpi_export.v index 85dc4ebec..7c92126e4 100644 --- a/test_regress/t/t_dpi_export.v +++ b/test_regress/t/t_dpi_export.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_TIME `endif @@ -15,79 +16,79 @@ module t; - sub a (.inst(1)); - sub b (.inst(2)); + sub a (.inst(1)); + sub b (.inst(2)); - // Returns integer line number, or -1 for all ok - import "DPI-C" context function int dpix_run_tests(); + // Returns integer line number, or -1 for all ok + import "DPI-C" context function int dpix_run_tests(); - export "DPI-C" task dpix_t_int; - task dpix_t_int(input int i, output int o); o = ~i; endtask + export "DPI-C" task dpix_t_int; + task dpix_t_int(input int i, output int o); o = ~i; endtask - export "DPI-C" dpix_t_renamed = task dpix_t_ren; - task dpix_t_ren(input int i, output int o); o = i+2; endtask + export "DPI-C" dpix_t_renamed = task dpix_t_ren; + task dpix_t_ren(input int i, output int o); o = i+2; endtask - export "DPI-C" function dpix_int123; - function int dpix_int123(); dpix_int123 = 32'h123; endfunction + export "DPI-C" function dpix_int123; + function int dpix_int123(); dpix_int123 = 32'h123; endfunction - export "DPI-C" function dpix_f_bit; - export "DPI-C" function dpix_f_bit15; - export "DPI-C" function dpix_f_int; - export "DPI-C" function dpix_f_byte; - export "DPI-C" function dpix_f_shortint; - export "DPI-C" function dpix_f_longint; - export "DPI-C" function dpix_f_chandle; + export "DPI-C" function dpix_f_bit; + export "DPI-C" function dpix_f_bit15; + export "DPI-C" function dpix_f_int; + export "DPI-C" function dpix_f_byte; + export "DPI-C" function dpix_f_shortint; + export "DPI-C" function dpix_f_longint; + export "DPI-C" function dpix_f_chandle; - function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction - function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction - function int dpix_f_int (int i); dpix_f_int = ~i; endfunction - function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction - function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction - function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction - function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction + function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction + function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction + function int dpix_f_int (int i); dpix_f_int = ~i; endfunction + function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction + function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction + function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction + function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction - export "DPI-C" task dpix_t_bit48; - task dpix_t_bit48(input bit [47:0] i, output bit [47:0] o); o = ~i; endtask - export "DPI-C" task dpix_t_bit95; - task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask - export "DPI-C" task dpix_t_bit96; - task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit48; + task dpix_t_bit48(input bit [47:0] i, output bit [47:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit95; + task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit96; + task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask - export "DPI-C" task dpix_t_reg; - task dpix_t_reg(input reg i, output reg o); o = ~i; endtask - export "DPI-C" task dpix_t_reg15; - task dpix_t_reg15(input reg [14:0] i, output reg [14:0] o); o = ~i; endtask - export "DPI-C" task dpix_t_reg95; - task dpix_t_reg95(input reg [94:0] i, output reg [94:0] o); o = ~i; endtask - export "DPI-C" task dpix_t_integer; - task dpix_t_integer(input integer i, output integer o); o = ~i; endtask + export "DPI-C" task dpix_t_reg; + task dpix_t_reg(input reg i, output reg o); o = ~i; endtask + export "DPI-C" task dpix_t_reg15; + task dpix_t_reg15(input reg [14:0] i, output reg [14:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_reg95; + task dpix_t_reg95(input reg [94:0] i, output reg [94:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_integer; + task dpix_t_integer(input integer i, output integer o); o = ~i; endtask `ifndef NO_TIME - export "DPI-C" task dpix_t_time; + export "DPI-C" task dpix_t_time; `endif - task dpix_t_time(input time i, output time o); o = ~i; endtask + task dpix_t_time(input time i, output time o); o = ~i; endtask - export "DPI-C" function dpix__under___score; - function int dpix__under___score(input int i); return i + 1; endfunction + export "DPI-C" function dpix__under___score; + function int dpix__under___score(input int i); return i + 1; endfunction - int lineno; + int lineno; - initial begin - lineno = dpix_run_tests(); - if (lineno != -1) begin - $display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno); - $stop; - end + initial begin + lineno = dpix_run_tests(); + if (lineno != -1) begin + $display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub (input int inst); - export "DPI-C" function dpix_sub_inst; + export "DPI-C" function dpix_sub_inst; - function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction + function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction endmodule diff --git a/test_regress/t/t_dpi_export_bad.out b/test_regress/t/t_dpi_export_bad.out index 62ac45b46..b29adba22 100644 --- a/test_regress/t/t_dpi_export_bad.out +++ b/test_regress/t/t_dpi_export_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_dpi_export_bad.v:10:24: Can't find definition of exported task/function: 'dpix_bad_missing' - 10 | export "DPI-C" task dpix_bad_missing; - | ^~~~~~~~~~~~~~~~ +%Error: t/t_dpi_export_bad.v:10:23: Can't find definition of exported task/function: 'dpix_bad_missing' + 10 | export "DPI-C" task dpix_bad_missing; + | ^~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_export_bad.v b/test_regress/t/t_dpi_export_bad.v index 13848a457..0ab51f540 100644 --- a/test_regress/t/t_dpi_export_bad.v +++ b/test_regress/t/t_dpi_export_bad.v @@ -7,5 +7,5 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - export "DPI-C" task dpix_bad_missing; + export "DPI-C" task dpix_bad_missing; endmodule diff --git a/test_regress/t/t_dpi_export_context2_bad.v b/test_regress/t/t_dpi_export_context2_bad.v index 2cb62b1be..c5d2d8733 100644 --- a/test_regress/t/t_dpi_export_context2_bad.v +++ b/test_regress/t/t_dpi_export_context2_bad.v @@ -7,13 +7,13 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - export "DPI-C" task dpix_task; - sub sub (); - task dpix_task(); - $write("Hello in %m\n"); - endtask + export "DPI-C" task dpix_task; + sub sub (); + task dpix_task(); + $write("Hello in %m\n"); + endtask endmodule module sub; - import "DPI-C" task dpii_task; - initial dpii_task; + import "DPI-C" task dpii_task; + initial dpii_task; endmodule diff --git a/test_regress/t/t_dpi_export_context_bad.v b/test_regress/t/t_dpi_export_context_bad.v index 9cb2f98ee..c12cf0a14 100644 --- a/test_regress/t/t_dpi_export_context_bad.v +++ b/test_regress/t/t_dpi_export_context_bad.v @@ -7,8 +7,8 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - export "DPI-C" task dpix_task; - task dpix_task(); - $write("Hello in %m\n"); - endtask + export "DPI-C" task dpix_task; + task dpix_task(); + $write("Hello in %m\n"); + endtask endmodule diff --git a/test_regress/t/t_dpi_imp_gen.v b/test_regress/t/t_dpi_imp_gen.v index 865f7d36b..8ef4d398a 100644 --- a/test_regress/t/t_dpi_imp_gen.v +++ b/test_regress/t/t_dpi_imp_gen.v @@ -6,29 +6,27 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - parameter integer BLKS = 3; + parameter integer BLKS = 3; - generate - for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice + generate + for (genvar blkIdx = 0; blkIdx < BLKS; blkIdx = blkIdx + 1) begin : slice - import "DPI-C" context function void dpi_genvarTest (); + import "DPI-C" context function void dpi_genvarTest(); - initial begin - dpi_genvarTest(); - $display("slice = %0d : %m", blkIdx); - end - end - endgenerate + initial begin + dpi_genvarTest(); + $display("slice = %0d : %m", blkIdx); + end + end + endgenerate - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index 7c9e26140..1afe70db9 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_SHORTREAL `define NO_TIME @@ -18,257 +19,255 @@ `define NO_SHORTREAL `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef struct packed { bit [47:0] lo; bit [47:0] hi; } str_t; - typedef struct packed { int a; int b; } substr_t; + typedef struct packed { bit [47:0] lo; bit [47:0] hi; } str_t; + typedef struct packed { int a; int b; } substr_t; - // Allowed import return types: - // void, byte, shortint, int, longint, real, shortreal, chandle, and string - // Scalar bit and logic - // - // Allowed argument types: - // Same as above plus packed arrays + // Allowed import return types: + // void, byte, shortint, int, longint, real, shortreal, chandle, and string + // Scalar bit and logic + // + // Allowed argument types: + // Same as above plus packed arrays - import "DPI-C" pure function bit dpii_f_bit (input bit i); - import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); - import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); - import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); - import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); - import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); - // Illegal to return > 32 bits, so we use longint - import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); - import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); - import "DPI-C" pure function int dpii_f_int (input int i); - import "DPI-C" pure function byte dpii_f_byte (input byte i); - import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); - import "DPI-C" pure function longint dpii_f_longint (input longint i); - import "DPI-C" pure function chandle dpii_f_chandle (input chandle i); - import "DPI-C" pure function string dpii_f_string (input string i); - import "DPI-C" pure function real dpii_f_real (input real i); + import "DPI-C" pure function bit dpii_f_bit (input bit i); + import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); + import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); + import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); + import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); + import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); + // Illegal to return > 32 bits, so we use longint + import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); + import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); + import "DPI-C" pure function int dpii_f_int (input int i); + import "DPI-C" pure function byte dpii_f_byte (input byte i); + import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); + import "DPI-C" pure function longint dpii_f_longint (input longint i); + import "DPI-C" pure function chandle dpii_f_chandle (input chandle i); + import "DPI-C" pure function string dpii_f_string (input string i); + import "DPI-C" pure function real dpii_f_real (input real i); `ifndef NO_SHORTREAL - import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i); + import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i); `endif - import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o); - import "DPI-C" pure function void dpii_v_int (input int i, output int o); - import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o); - import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o); - import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o); - import "DPI-C" pure function void dpii_v_struct (input str_t i, output str_t o); - import "DPI-C" pure function void dpii_v_substruct(input substr_t i, output int o); - import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o); - import "DPI-C" pure function void dpii_v_string (input string i, inout string o); - import "DPI-C" pure function void dpii_v_real (input real i, output real o); + import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o); + import "DPI-C" pure function void dpii_v_int (input int i, output int o); + import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o); + import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o); + import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o); + import "DPI-C" pure function void dpii_v_struct (input str_t i, output str_t o); + import "DPI-C" pure function void dpii_v_substruct(input substr_t i, output int o); + import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o); + import "DPI-C" pure function void dpii_v_string (input string i, inout string o); + import "DPI-C" pure function void dpii_v_real (input real i, output real o); - import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); - import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); - import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); + import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); + import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); + import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); `ifndef NO_SHORTREAL - import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); + import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); `endif - import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); - import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); - import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); + import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); + import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); + import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); - import "DPI-C" pure function void dpii_v_reg (input reg i, output reg o); - import "DPI-C" pure function void dpii_v_reg15 (input reg [14:0] i, output reg [14:0] o); - import "DPI-C" pure function void dpii_v_reg95 (input reg [94:0] i, output reg [94:0] o); - import "DPI-C" pure function void dpii_v_integer (input integer i, output integer o); + import "DPI-C" pure function void dpii_v_reg (input reg i, output reg o); + import "DPI-C" pure function void dpii_v_reg15 (input reg [14:0] i, output reg [14:0] o); + import "DPI-C" pure function void dpii_v_reg95 (input reg [94:0] i, output reg [94:0] o); + import "DPI-C" pure function void dpii_v_integer (input integer i, output integer o); `ifndef NO_TIME - import "DPI-C" pure function void dpii_v_time (input time i, output time o); + import "DPI-C" pure function void dpii_v_time (input time i, output time o); `endif - import "DPI-C" pure function int dpii_f_strlen(input string i); + import "DPI-C" pure function int dpii_f_strlen(input string i); - import "DPI-C" function string dpii_f_null(); + import "DPI-C" function string dpii_f_null(); - import "DPI-C" function void dpii_f_void(); + import "DPI-C" function void dpii_f_void(); - // Try a task - import "DPI-C" task dpii_t_void(); - import "DPI-C" context task dpii_t_void_context(); + // Try a task + import "DPI-C" task dpii_t_void(); + import "DPI-C" context task dpii_t_void_context(); - import "DPI-C" task dpii_t_int(input int i, output int o); + import "DPI-C" task dpii_t_int(input int i, output int o); - // Try non-pure, aliasing with name - import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); - import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); + // Try non-pure, aliasing with name + import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); - // Check Verilator doesn't convert double underscores - import "DPI-C" pure function int dpii__under___score(input int i); + // Check Verilator doesn't convert double underscores + import "DPI-C" pure function int dpii__under___score(input int i); - bit i_b, o_b; - bit [7:0] i_b8; - bit [8:0] i_b9; - bit [15:0] i_b16; - bit [16:0] i_b17; - bit [31:0] i_b32; - bit [32:0] i_b33, o_b33; - bit [63:0] i_b64, o_b64; - bit [94:0] i_b95, o_b95; - bit [95:0] i_b96, o_b96; + bit i_b, o_b; + bit [7:0] i_b8; + bit [8:0] i_b9; + bit [15:0] i_b16; + bit [16:0] i_b17; + bit [31:0] i_b32; + bit [32:0] i_b33, o_b33; + bit [63:0] i_b64, o_b64; + bit [94:0] i_b95, o_b95; + bit [95:0] i_b96, o_b96; - int i_i, o_i; - byte i_y, o_y; - shortint i_s, o_s; - longint i_l, o_l; - str_t i_t, o_t; - substr_t i_ss; - int o_ss; - int unsigned i_iu, o_iu; - shortint unsigned i_su, o_su; - longint unsigned i_lu, o_lu; - // verilator lint_off UNDRIVEN - chandle i_c, o_c; - string i_n, o_n; - // verilator lint_on UNDRIVEN - real i_d, o_d; + int i_i, o_i; + byte i_y, o_y; + shortint i_s, o_s; + longint i_l, o_l; + str_t i_t, o_t; + substr_t i_ss; + int o_ss; + int unsigned i_iu, o_iu; + shortint unsigned i_su, o_su; + longint unsigned i_lu, o_lu; + // verilator lint_off UNDRIVEN + chandle i_c, o_c; + string i_n, o_n; + // verilator lint_on UNDRIVEN + real i_d, o_d; `ifndef NO_SHORTREAL - shortreal i_f, o_f; + shortreal i_f, o_f; `endif - reg i_r, o_r; - reg [14:0] i_r15, o_r15; - reg [94:0] i_r95, o_r95; - integer i_in, o_in; - time i_tm, o_tm; + reg i_r, o_r; + reg [14:0] i_r15, o_r15; + reg [94:0] i_r95, o_r95; + integer i_in, o_in; + time i_tm, o_tm; - bit [94:0] wide; + bit [94:0] wide; - bit [6*8:1] string6; + bit [6*8:1] string6; - initial begin - wide = 95'h15caff7a73c48afee4ffcb57; + initial begin + wide = 95'h15caff7a73c48afee4ffcb57; - i_b = 1'b1; - i_b8 = {1'b1,wide[8-2:0]}; - i_b9 = {1'b1,wide[9-2:0]}; - i_b16 = {1'b1,wide[16-2:0]}; - i_b17 = {1'b1,wide[17-2:0]}; - i_b32 = {1'b1,wide[32-2:0]}; - i_b33 = {1'b1,wide[33-2:0]}; - i_b64 = {1'b1,wide[64-2:0]}; - i_b95 = {1'b1,wide[95-2:0]}; - i_b96 = {1'b1,wide[96-2:0]}; + i_b = 1'b1; + i_b8 = {1'b1,wide[8-2:0]}; + i_b9 = {1'b1,wide[9-2:0]}; + i_b16 = {1'b1,wide[16-2:0]}; + i_b17 = {1'b1,wide[17-2:0]}; + i_b32 = {1'b1,wide[32-2:0]}; + i_b33 = {1'b1,wide[33-2:0]}; + i_b64 = {1'b1,wide[64-2:0]}; + i_b95 = {1'b1,wide[95-2:0]}; + i_b96 = {1'b1,wide[96-2:0]}; - i_i = {1'b1,wide[32-2:0]}; - i_iu= {1'b1,wide[32-2:0]}; - i_y = {1'b1,wide[8-2:0]}; - i_s = {1'b1,wide[16-2:0]}; - i_su= {1'b1,wide[16-2:0]}; - i_l = {1'b1,wide[64-2:0]}; - i_lu= {1'b1,wide[64-2:0]}; - i_t = {1'b1,wide[95-1:0]}; - i_d = 32.1; + i_i = {1'b1,wide[32-2:0]}; + i_iu= {1'b1,wide[32-2:0]}; + i_y = {1'b1,wide[8-2:0]}; + i_s = {1'b1,wide[16-2:0]}; + i_su= {1'b1,wide[16-2:0]}; + i_l = {1'b1,wide[64-2:0]}; + i_lu= {1'b1,wide[64-2:0]}; + i_t = {1'b1,wide[95-1:0]}; + i_d = 32.1; - i_ss.a = 32'h054321ab; - i_ss.b = 32'h05a43b21; + i_ss.a = 32'h054321ab; + i_ss.b = 32'h05a43b21; `ifndef NO_SHORTREAL - i_f = 30.2; + i_f = 30.2; `endif - i_r = '0; - i_r15 = wide[14:0]; - i_r95 = wide[94:0]; - i_in = -1234; - i_tm = 62; + i_r = '0; + i_r15 = wide[14:0]; + i_r95 = wide[94:0]; + i_in = -1234; + i_tm = 62; - if (dpii_f_bit (i_b) !== ~i_b) $stop; - if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; - if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; - if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; - if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; - if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; + if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; + if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; + if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; + if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; - // These return different sizes, so we need to truncate - // verilator lint_off WIDTH - o_b33 = dpii_f_bit33 (i_b33); - o_b64 = dpii_f_bit64 (i_b64); - // verilator lint_on WIDTH - if (o_b33 !== ~i_b33) $stop; - if (o_b64 !== ~i_b64) $stop; + // These return different sizes, so we need to truncate + // verilator lint_off WIDTH + o_b33 = dpii_f_bit33 (i_b33); + o_b64 = dpii_f_bit64 (i_b64); + // verilator lint_on WIDTH + if (o_b33 !== ~i_b33) $stop; + if (o_b64 !== ~i_b64) $stop; - if (dpii_f_bit (i_b) !== ~i_b) $stop; - if (dpii_f_int (i_i) !== ~i_i) $stop; - if (dpii_f_byte (i_y) !== ~i_y) $stop; - if (dpii_f_shortint (i_s) !== ~i_s) $stop; - if (dpii_f_longint (i_l) !== ~i_l) $stop; - if (dpii_f_chandle (i_c) !== i_c) $stop; - if (dpii_f_string (i_n) != i_n) $stop; - if (dpii_f_real (i_d) != i_d+1.5) $stop; + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_int (i_i) !== ~i_i) $stop; + if (dpii_f_byte (i_y) !== ~i_y) $stop; + if (dpii_f_shortint (i_s) !== ~i_s) $stop; + if (dpii_f_longint (i_l) !== ~i_l) $stop; + if (dpii_f_chandle (i_c) !== i_c) $stop; + if (dpii_f_string (i_n) != i_n) $stop; + if (dpii_f_real (i_d) != i_d+1.5) $stop; `ifndef NO_SHORTREAL - if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; + if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; `endif - dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; - dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; - dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; - dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; - dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; - dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; - dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; - dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; - dpii_v_struct (i_t,o_t); if (o_t !== ~i_t) $stop; - dpii_v_substruct(i_ss,o_ss); if (o_ss !== i_ss.a - i_ss.b) $stop; - dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; - dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; - dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; + dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; + dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; + dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; + dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; + dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; + dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; + dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; + dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; + dpii_v_struct (i_t,o_t); if (o_t !== ~i_t) $stop; + dpii_v_substruct(i_ss,o_ss); if (o_ss !== i_ss.a - i_ss.b) $stop; + dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; + dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; + dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; `ifndef NO_SHORTREAL - dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; + dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; `endif - dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; - dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; - dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; + dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; + dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; + dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; - dpii_v_reg (i_r,o_r); if (o_r !== ~i_r) $stop; - dpii_v_reg15 (i_r15,o_r15); if (o_r15 !== ~i_r15) $stop; - dpii_v_reg95 (i_r95,o_r95); if (o_r95 !== ~i_r95) $stop; - dpii_v_integer (i_in,o_in); if (o_in != ~i_in) $stop; + dpii_v_reg (i_r,o_r); if (o_r !== ~i_r) $stop; + dpii_v_reg15 (i_r15,o_r15); if (o_r15 !== ~i_r15) $stop; + dpii_v_reg95 (i_r95,o_r95); if (o_r95 !== ~i_r95) $stop; + dpii_v_integer (i_in,o_in); if (o_in != ~i_in) $stop; `ifndef NO_TIME - dpii_v_time (i_tm,o_tm); if (o_tm != ~i_tm) $stop; + dpii_v_time (i_tm,o_tm); if (o_tm != ~i_tm) $stop; `endif - if (dpii_f_strlen("") != 0) $stop; - if (dpii_f_strlen("s") != 1) $stop; - if (dpii_f_strlen("st") != 2) $stop; - if (dpii_f_strlen("str") != 3) $stop; - if (dpii_f_strlen("stri") != 4) $stop; - if (dpii_f_strlen("string_l") != 8) $stop; - if (dpii_f_strlen("string_len") != 10) $stop; - string6 = "hello6"; + if (dpii_f_strlen("") != 0) $stop; + if (dpii_f_strlen("s") != 1) $stop; + if (dpii_f_strlen("st") != 2) $stop; + if (dpii_f_strlen("str") != 3) $stop; + if (dpii_f_strlen("stri") != 4) $stop; + if (dpii_f_strlen("string_l") != 8) $stop; + if (dpii_f_strlen("string_len") != 10) $stop; + string6 = "hello6"; `ifdef VERILATOR - string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function + string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function `endif - if (dpii_f_strlen(string6) != 6) $stop; + if (dpii_f_strlen(string6) != 6) $stop; - if (dpii_f_null() != "") $stop; - dpii_f_void(); - dpii_t_void(); - dpii_t_void_context(); + if (dpii_f_null() != "") $stop; + dpii_f_void(); + dpii_t_void(); + dpii_t_void_context(); - i_i = 32'h456789ab; - dpii_t_int(i_i, o_i); if (o_b !== ~i_b) $stop; + i_i = 32'h456789ab; + dpii_t_int(i_i, o_i); if (o_b !== ~i_b) $stop; - // Check alias - if (oth_f_int1(32'd123) !== ~32'd123) $stop; - if (oth_f_int2(32'd124) !== ~32'd124) $stop; + // Check alias + if (oth_f_int1(32'd123) !== ~32'd123) $stop; + if (oth_f_int2(32'd124) !== ~32'd124) $stop; - if (dpii__under___score(32'd60) != 32'd61) $stop; + if (dpii__under___score(32'd60) != 32'd61) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end - always @ (posedge clk) begin - i_b <= ~i_b; - // This once mis-threw a BLKSEQ warning - dpii_v_bit(i_b, o_b); if (o_b !== ~i_b) $stop; - end + always @ (posedge clk) begin + i_b <= ~i_b; + // This once mis-threw a BLKSEQ warning + dpii_v_bit(i_b, o_b); if (o_b !== ~i_b) $stop; + end endmodule diff --git a/test_regress/t/t_dpi_import_mix_bad.out b/test_regress/t/t_dpi_import_mix_bad.out index 161fcf7e9..76808ac16 100644 --- a/test_regress/t/t_dpi_import_mix_bad.out +++ b/test_regress/t/t_dpi_import_mix_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_dpi_import_mix_bad.v:11:32: Cannot mix DPI import, DPI export, class methods, and/or public on same function: 't.foo' - 11 | import "DPI-C" function int foo (int i); - | ^~~ +%Error: t/t_dpi_import_mix_bad.v:11:31: Cannot mix DPI import, DPI export, class methods, and/or public on same function: 't.foo' + 11 | import "DPI-C" function int foo(int i); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_import_mix_bad.v b/test_regress/t/t_dpi_import_mix_bad.v index f00216a6e..f90bf1405 100644 --- a/test_regress/t/t_dpi_import_mix_bad.v +++ b/test_regress/t/t_dpi_import_mix_bad.v @@ -8,11 +8,11 @@ module t; - import "DPI-C" function int foo (int i); - export "DPI-C" function foo; // Bad mix + import "DPI-C" function int foo(int i); + export "DPI-C" function foo; // Bad mix - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_instr_count_large.v b/test_regress/t/t_dpi_instr_count_large.v index 28f23f83a..933d034ed 100644 --- a/test_regress/t/t_dpi_instr_count_large.v +++ b/test_regress/t/t_dpi_instr_count_large.v @@ -5,22 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 -module t(clk); - input clk; - sub_0 sub_0(clk); - sub_1 sub_1(clk); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end +module t ( + input clk +); + sub_0 sub_0 (clk); + sub_1 sub_1 (clk); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule import "DPI-C" context function void dpii_call(); -module sub_0(input clk); /*verilator hier_block*/ - always @(posedge clk) dpii_call(); +module sub_0 ( + input clk +); /*verilator hier_block*/ + always @(posedge clk) dpii_call(); endmodule -module sub_1(input clk); /*verilator hier_block*/ - always @(posedge clk) dpii_call(); +module sub_1 ( + input clk +); /*verilator hier_block*/ + always @(posedge clk) dpii_call(); endmodule diff --git a/test_regress/t/t_dpi_lib.v b/test_regress/t/t_dpi_lib.v index 4a88e6d9a..aacce9f7b 100644 --- a/test_regress/t/t_dpi_lib.v +++ b/test_regress/t/t_dpi_lib.v @@ -8,20 +8,20 @@ module t; - import "DPI-C" function int dpii_failure(); - import "DPI-C" function void dpii_check(); + import "DPI-C" function int dpii_failure(); + import "DPI-C" function void dpii_check(); - initial begin - dpii_check(); + initial begin + dpii_check(); - if (dpii_failure()!=0) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (dpii_failure() != 0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dpi_name_bad.out b/test_regress/t/t_dpi_name_bad.out index f4438446a..785d68f59 100644 --- a/test_regress/t/t_dpi_name_bad.out +++ b/test_regress/t/t_dpi_name_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_dpi_name_bad.v:11:32: DPI function has illegal characters in C identifier name: badly.named - 11 | import "DPI-C" function int \badly.named (int i); - | ^~~~~~~~~~~~ +%Error: t/t_dpi_name_bad.v:11:31: DPI function has illegal characters in C identifier name: badly.named + 11 | import "DPI-C" function int \badly.named (int i); + | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_dpi_name_bad.v:14:17: DPI function has illegal characters in C identifier name: badly.expt - 14 | function int \badly.expt ; return 0; endfunction - | ^~~~~~~~~~~ +%Error: t/t_dpi_name_bad.v:14:16: DPI function has illegal characters in C identifier name: badly.expt + 14 | function int \badly.expt ; + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index a1b4838d5..e7171da12 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -8,13 +8,15 @@ module t; - import "DPI-C" function int \badly.named (int i); + import "DPI-C" function int \badly.named (int i); - export "DPI-C" function \badly.expt ; - function int \badly.expt ; return 0; endfunction + export "DPI-C" function \badly.expt ; + function int \badly.expt ; + return 0; + endfunction - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_open.v b/test_regress/t/t_dpi_open.v index 944c8dd1a..5556d21ec 100644 --- a/test_regress/t/t_dpi_open.v +++ b/test_regress/t/t_dpi_open.v @@ -6,164 +6,165 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; - // verilator lint_off UNUSED - reg i_rl_p0_u1 [-2:2]; - reg o_rl_p0_u1 [-2:2]; - reg [1:-1] i_rl_p1_u1 [-2:2]; - reg [1:-1] o_rl_p1_u1 [-2:2]; - reg [1:-1] i_rl_p1_u2 [-2:2] [-3:3]; - reg [1:-1] o_rl_p1_u2 [-2:2] [-3:3]; - reg [1:-1] i_rl_p1_u3 [-2:2] [-3:3] [-4:4]; - reg [1:-1] o_rl_p1_u3 [-2:2] [-3:3] [-4:4]; + // verilator lint_off UNUSED + reg i_rl_p0_u1 [-2:2]; + reg o_rl_p0_u1 [-2:2]; + reg [1:-1] i_rl_p1_u1 [-2:2]; + reg [1:-1] o_rl_p1_u1 [-2:2]; + reg [1:-1] i_rl_p1_u2 [-2:2] [-3:3]; + reg [1:-1] o_rl_p1_u2 [-2:2] [-3:3]; + reg [1:-1] i_rl_p1_u3 [-2:2] [-3:3] [-4:4]; + reg [1:-1] o_rl_p1_u3 [-2:2] [-3:3] [-4:4]; - reg i_rb_p0_u1 [2:-2]; - reg o_rb_p0_u1 [2:-2]; - reg [1:-1] i_rb_p1_u1 [2:-2]; - reg [1:-1] o_rb_p1_u1 [2:-2]; - reg [1:-1] i_rb_p1_u2 [2:-2] [3:-3]; - reg [1:-1] o_rb_p1_u2 [2:-2] [3:-3]; - reg [1:-1] i_rb_p1_u3 [2:-2] [3:-3] [4:-4]; - reg [1:-1] o_rb_p1_u3 [2:-2] [3:-3] [4:-4]; + reg i_rb_p0_u1 [2:-2]; + reg o_rb_p0_u1 [2:-2]; + reg [1:-1] i_rb_p1_u1 [2:-2]; + reg [1:-1] o_rb_p1_u1 [2:-2]; + reg [1:-1] i_rb_p1_u2 [2:-2] [3:-3]; + reg [1:-1] o_rb_p1_u2 [2:-2] [3:-3]; + reg [1:-1] i_rb_p1_u3 [2:-2] [3:-3] [4:-4]; + reg [1:-1] o_rb_p1_u3 [2:-2] [3:-3] [4:-4]; - reg i_rw_p0_u1 [2:-2]; - reg o_rw_p0_u1 [2:-2]; - reg [95:1] i_rw_p1_u1 [2:-2]; - reg [95:1] o_rw_p1_u1 [2:-2]; - reg [95:1] i_rw_p1_u2 [2:-2] [3:-3]; - reg [95:1] o_rw_p1_u2 [2:-2] [3:-3]; - reg [95:1] i_rw_p1_u3 [2:-2] [3:-3] [4:-4]; - reg [95:1] o_rw_p1_u3 [2:-2] [3:-3] [4:-4]; + reg i_rw_p0_u1 [2:-2]; + reg o_rw_p0_u1 [2:-2]; + reg [95:1] i_rw_p1_u1 [2:-2]; + reg [95:1] o_rw_p1_u1 [2:-2]; + reg [95:1] i_rw_p1_u2 [2:-2] [3:-3]; + reg [95:1] o_rw_p1_u2 [2:-2] [3:-3]; + reg [95:1] i_rw_p1_u3 [2:-2] [3:-3] [4:-4]; + reg [95:1] o_rw_p1_u3 [2:-2] [3:-3] [4:-4]; - bit i_bit [1:0]; - bit o_bit [1:0]; - logic i_logic [1:0]; - logic o_logic [1:0]; - byte i_byte [1:0]; - byte o_byte [1:0]; - integer i_integer [1:0]; - integer o_integer [1:0]; + bit i_bit [1:0]; + bit o_bit [1:0]; + logic i_logic [1:0]; + logic o_logic [1:0]; + byte i_byte [1:0]; + byte o_byte [1:0]; + integer i_integer [1:0]; + integer o_integer [1:0]; - import "DPI-C" function int dpii_failure(); + import "DPI-C" function int dpii_failure(); - import "DPI-C" function void dpii_unused(input reg u []); + import "DPI-C" function void dpii_unused(input reg u []); - // [] on packed arrays is unsupported in VCS & NC, so not supporting this + // [] on packed arrays is unsupported in VCS & NC, so not supporting this - // p is number of packed dimensions, u is number of unpacked dimensions - import "DPI-C" function void dpii_open_p0_u1(input int c,p,u, input reg i [], output reg o []); - import "DPI-C" function void dpii_open_p1_u1(input int c,p,u, input reg [1:-1] i [], output reg [1:-1] o []); - import "DPI-C" function void dpii_open_p1_u2(input int c,p,u, input reg [1:-1] i [] [], output reg [1:-1] o [] []); - import "DPI-C" function void dpii_open_p1_u3(input int c,p,u, input reg [1:-1] i [] [] [], output reg [1:-1] o [] [] []); + // p is number of packed dimensions, u is number of unpacked dimensions + import "DPI-C" function void dpii_open_p0_u1(input int c,p,u, input reg i [], output reg o []); + import "DPI-C" function void dpii_open_p1_u1(input int c,p,u, input reg [1:-1] i [], output reg [1:-1] o []); + import "DPI-C" function void dpii_open_p1_u2(input int c,p,u, input reg [1:-1] i [] [], output reg [1:-1] o [] []); + import "DPI-C" function void dpii_open_p1_u3(input int c,p,u, input reg [1:-1] i [] [] [], output reg [1:-1] o [] [] []); - import "DPI-C" function void dpii_open_pw_u1(input int c,p,u, input reg [95:1] i [], output reg [95:1] o []); - import "DPI-C" function void dpii_open_pw_u2(input int c,p,u, input reg [95:1] i [] [], output reg [95:1] o [] []); - import "DPI-C" function void dpii_open_pw_u3(input int c,p,u, input reg [95:1] i [] [] [], output reg [95:1] o [] [] []); + import "DPI-C" function void dpii_open_pw_u1(input int c,p,u, input reg [95:1] i [], output reg [95:1] o []); + import "DPI-C" function void dpii_open_pw_u2(input int c,p,u, input reg [95:1] i [] [], output reg [95:1] o [] []); + import "DPI-C" function void dpii_open_pw_u3(input int c,p,u, input reg [95:1] i [] [] [], output reg [95:1] o [] [] []); - import "DPI-C" function void dpii_open_bit(input bit i [], output bit o []); - import "DPI-C" function void dpii_open_logic(input logic i [], output logic o []); - import "DPI-C" function void dpii_open_byte(input byte i [], output byte o []); - import "DPI-C" function void dpii_open_integer(input integer i [], output integer o []); + import "DPI-C" function void dpii_open_bit(input bit i [], output bit o []); + import "DPI-C" function void dpii_open_logic(input logic i [], output logic o []); + import "DPI-C" function void dpii_open_byte(input byte i [], output byte o []); + import "DPI-C" function void dpii_open_integer(input integer i [], output integer o []); - int i_int_u1 [2:-2]; - int o_int_u1 [2:-2]; - int i_int_u2 [2:-2] [-3:3]; - int o_int_u2 [2:-2] [-3:3]; - int i_int_u3 [2:-2] [-3:3] [4:-4]; - int o_int_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_open_int_u1(int u, input int i [], output int o []); - import "DPI-C" function void dpii_open_int_u2(int u, input int i [] [], output int o [] []); - import "DPI-C" function void dpii_open_int_u3(int u, input int i [] [] [], output int o [] [] []); + int i_int_u1 [2:-2]; + int o_int_u1 [2:-2]; + int i_int_u2 [2:-2] [-3:3]; + int o_int_u2 [2:-2] [-3:3]; + int i_int_u3 [2:-2] [-3:3] [4:-4]; + int o_int_u3 [2:-2] [-3:3] [4:-4]; + import "DPI-C" function void dpii_open_int_u1(int u, input int i [], output int o []); + import "DPI-C" function void dpii_open_int_u2(int u, input int i [] [], output int o [] []); + import "DPI-C" function void dpii_open_int_u3(int u, input int i [] [] [], output int o [] [] []); - // verilator lint_on UNUSED + // verilator lint_on UNUSED - reg [95:0] crc; + reg [95:0] crc; - initial begin - crc = 96'h8a10a572_5aef0c8d_d70a4497; + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; - for (int a=0; a<2; a=a+1) begin - i_bit[a] = crc[0]; - i_logic[a] = crc[0]; - i_byte[a] = crc[7:0]; - i_integer[a] = crc[31:0]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + for (int a=0; a<2; a=a+1) begin + i_bit[a] = crc[0]; + i_logic[a] = crc[0]; + i_byte[a] = crc[7:0]; + i_integer[a] = crc[31:0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + + dpii_open_bit(i_bit, o_bit); + dpii_open_logic(i_logic, o_logic); + dpii_open_byte(i_byte, o_byte); + dpii_open_integer(i_integer, o_integer); + + for (int a=-2; a<=2; a=a+1) begin + i_rl_p0_u1[a] = crc[0]; + i_rb_p0_u1[a] = crc[0]; + i_rw_p0_u1[a] = crc[0]; + i_rl_p1_u1[a] = crc[2:0]; + i_rb_p1_u1[a] = crc[2:0]; + i_rw_p1_u1[a] = crc[94:0]; + i_int_u1[a] = crc[31:0]; + for (int b=-3; b<=3; b=b+1) begin + i_rl_p1_u2[a][b] = crc[2:0]; + i_rb_p1_u2[a][b] = crc[2:0]; + i_rw_p1_u2[a][b] = crc[94:0]; + i_int_u2[a][b] = crc[31:0]; + for (int c=-4; c<=4; c=c+1) begin + i_rl_p1_u3[a][b][c] = crc[2:0]; + i_rb_p1_u3[a][b][c] = crc[2:0]; + i_rw_p1_u3[a][b][c] = crc[94:0]; + i_int_u3[a][b][c] = crc[31:0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end end + end - dpii_open_bit(i_bit, o_bit); - dpii_open_logic(i_logic, o_logic); - dpii_open_byte(i_byte, o_byte); - dpii_open_integer(i_integer, o_integer); + dpii_open_p0_u1(0,0,1, i_rl_p0_u1, o_rl_p0_u1); + dpii_open_p0_u1(1,0,1, i_rb_p0_u1, o_rb_p0_u1); + dpii_open_p0_u1(2,0,1, i_rw_p0_u1, o_rw_p0_u1); + dpii_open_p1_u1(0,1,1, i_rl_p1_u1, o_rl_p1_u1); + dpii_open_p1_u2(0,1,2, i_rl_p1_u2, o_rl_p1_u2); + dpii_open_p1_u3(0,1,3, i_rl_p1_u3, o_rl_p1_u3); + dpii_open_p1_u1(1,1,1, i_rb_p1_u1, o_rb_p1_u1); + dpii_open_p1_u2(1,1,2, i_rb_p1_u2, o_rb_p1_u2); + dpii_open_p1_u3(1,1,3, i_rb_p1_u3, o_rb_p1_u3); + dpii_open_pw_u1(2,1,1, i_rw_p1_u1, o_rw_p1_u1); + dpii_open_pw_u2(2,1,2, i_rw_p1_u2, o_rw_p1_u2); + dpii_open_pw_u3(2,1,3, i_rw_p1_u3, o_rw_p1_u3); - for (int a=-2; a<=2; a=a+1) begin - i_rl_p0_u1[a] = crc[0]; - i_rb_p0_u1[a] = crc[0]; - i_rw_p0_u1[a] = crc[0]; - i_rl_p1_u1[a] = crc[2:0]; - i_rb_p1_u1[a] = crc[2:0]; - i_rw_p1_u1[a] = crc[94:0]; - i_int_u1[a] = crc[31:0]; - for (int b=-3; b<=3; b=b+1) begin - i_rl_p1_u2[a][b] = crc[2:0]; - i_rb_p1_u2[a][b] = crc[2:0]; - i_rw_p1_u2[a][b] = crc[94:0]; - i_int_u2[a][b] = crc[31:0]; - for (int c=-4; c<=4; c=c+1) begin - i_rl_p1_u3[a][b][c] = crc[2:0]; - i_rb_p1_u3[a][b][c] = crc[2:0]; - i_rw_p1_u3[a][b][c] = crc[94:0]; - i_int_u3[a][b][c] = crc[31:0]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; - end - end + for (int a=-2; a<=2; a=a+1) begin + for (int b=-3; b<=3; b=b+1) begin + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_rw_p1_u3[a][b][c], ~i_rw_p1_u3[a][b][c]); + end end + end - dpii_open_p0_u1(0,0,1, i_rl_p0_u1, o_rl_p0_u1); - dpii_open_p0_u1(1,0,1, i_rb_p0_u1, o_rb_p0_u1); - dpii_open_p0_u1(2,0,1, i_rw_p0_u1, o_rw_p0_u1); - dpii_open_p1_u1(0,1,1, i_rl_p1_u1, o_rl_p1_u1); - dpii_open_p1_u2(0,1,2, i_rl_p1_u2, o_rl_p1_u2); - dpii_open_p1_u3(0,1,3, i_rl_p1_u3, o_rl_p1_u3); - dpii_open_p1_u1(1,1,1, i_rb_p1_u1, o_rb_p1_u1); - dpii_open_p1_u2(1,1,2, i_rb_p1_u2, o_rb_p1_u2); - dpii_open_p1_u3(1,1,3, i_rb_p1_u3, o_rb_p1_u3); - dpii_open_pw_u1(2,1,1, i_rw_p1_u1, o_rw_p1_u1); - dpii_open_pw_u2(2,1,2, i_rw_p1_u2, o_rw_p1_u2); - dpii_open_pw_u3(2,1,3, i_rw_p1_u3, o_rw_p1_u3); + dpii_open_int_u1(1, i_int_u1, o_int_u1); + dpii_open_int_u2(2, i_int_u2, o_int_u2); + dpii_open_int_u3(3, i_int_u3, o_int_u3); + for (int a=-2; a<=2; a=a+1) begin + `checkh(o_int_u1[a], ~i_int_u1[a]); + for (int b=-3; b<=3; b=b+1) begin + `checkh(o_int_u2[a][b], ~i_int_u2[a][b]); + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_int_u3[a][b][c], ~i_int_u3[a][b][c]); + end + end + end - for (int a=-2; a<=2; a=a+1) begin - for (int b=-3; b<=3; b=b+1) begin - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_rw_p1_u3[a][b][c], ~i_rw_p1_u3[a][b][c]); - end - end - end - - dpii_open_int_u1(1, i_int_u1, o_int_u1); - dpii_open_int_u2(2, i_int_u2, o_int_u2); - dpii_open_int_u3(3, i_int_u3, o_int_u3); - for (int a=-2; a<=2; a=a+1) begin - `checkh(o_int_u1[a], ~i_int_u1[a]); - for (int b=-3; b<=3; b=b+1) begin - `checkh(o_int_u2[a][b], ~i_int_u2[a][b]); - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_int_u3[a][b][c], ~i_int_u3[a][b][c]); - end - end - end - - if (dpii_failure()!=0) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dpi_open_elem.v b/test_regress/t/t_dpi_open_elem.v index 4e65ec90a..dd6ce9928 100644 --- a/test_regress/t/t_dpi_open_elem.v +++ b/test_regress/t/t_dpi_open_elem.v @@ -6,114 +6,115 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; - bit i_bit_p0_u1 [2:-2]; - bit o_bit_p0_u1 [2:-2]; - bit q_bit_p0_u1 [2:-2]; - bit i_bit_p0_u2 [2:-2] [-3:3]; - bit o_bit_p0_u2 [2:-2] [-3:3]; - bit q_bit_p0_u2 [2:-2] [-3:3]; - bit i_bit_p0_u3 [2:-2] [-3:3] [4:-4]; - bit o_bit_p0_u3 [2:-2] [-3:3] [4:-4]; - bit q_bit_p0_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_bit_elem_p0_u1 - (int p, int u, input bit i [], output bit o [], output bit q []); - import "DPI-C" function void dpii_bit_elem_p0_u2 - (int p, int u, input bit i [] [], output bit o [] [], output bit q [] []); - import "DPI-C" function void dpii_bit_elem_p0_u3 - (int p, int u, input bit i [] [] [], output bit o [] [] [], output bit q [] [] []); + bit i_bit_p0_u1 [2:-2]; + bit o_bit_p0_u1 [2:-2]; + bit q_bit_p0_u1 [2:-2]; + bit i_bit_p0_u2 [2:-2] [-3:3]; + bit o_bit_p0_u2 [2:-2] [-3:3]; + bit q_bit_p0_u2 [2:-2] [-3:3]; + bit i_bit_p0_u3 [2:-2] [-3:3] [4:-4]; + bit o_bit_p0_u3 [2:-2] [-3:3] [4:-4]; + bit q_bit_p0_u3 [2:-2] [-3:3] [4:-4]; + import "DPI-C" function void dpii_bit_elem_p0_u1 + (int p, int u, input bit i [], output bit o [], output bit q []); + import "DPI-C" function void dpii_bit_elem_p0_u2 + (int p, int u, input bit i [] [], output bit o [] [], output bit q [] []); + import "DPI-C" function void dpii_bit_elem_p0_u3 + (int p, int u, input bit i [] [] [], output bit o [] [] [], output bit q [] [] []); - logic i_logic_p0_u1 [2:-2]; - logic o_logic_p0_u1 [2:-2]; - logic q_logic_p0_u1 [2:-2]; - logic i_logic_p0_u2 [2:-2] [-3:3]; - logic o_logic_p0_u2 [2:-2] [-3:3]; - logic q_logic_p0_u2 [2:-2] [-3:3]; - logic i_logic_p0_u3 [2:-2] [-3:3] [4:-4]; - logic o_logic_p0_u3 [2:-2] [-3:3] [4:-4]; - logic q_logic_p0_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_logic_elem_p0_u1(int p, int u, input logic i [], - output logic o [], output logic q []); - import "DPI-C" function void dpii_logic_elem_p0_u2(int p, int u, input logic i [] [], - output logic o [] [], output logic q [] []); - import "DPI-C" function void dpii_logic_elem_p0_u3(int p, int u, input logic i [] [] [], - output logic o [] [] [], output logic q [] [] []); + logic i_logic_p0_u1 [2:-2]; + logic o_logic_p0_u1 [2:-2]; + logic q_logic_p0_u1 [2:-2]; + logic i_logic_p0_u2 [2:-2] [-3:3]; + logic o_logic_p0_u2 [2:-2] [-3:3]; + logic q_logic_p0_u2 [2:-2] [-3:3]; + logic i_logic_p0_u3 [2:-2] [-3:3] [4:-4]; + logic o_logic_p0_u3 [2:-2] [-3:3] [4:-4]; + logic q_logic_p0_u3 [2:-2] [-3:3] [4:-4]; + import "DPI-C" function void dpii_logic_elem_p0_u1(int p, int u, input logic i [], + output logic o [], output logic q []); + import "DPI-C" function void dpii_logic_elem_p0_u2(int p, int u, input logic i [] [], + output logic o [] [], output logic q [] []); + import "DPI-C" function void dpii_logic_elem_p0_u3(int p, int u, input logic i [] [] [], + output logic o [] [] [], output logic q [] [] []); - import "DPI-C" function int dpii_failure(); + import "DPI-C" function int dpii_failure(); - reg [95:0] crc; + reg [95:0] crc; - initial begin - crc = 96'h8a10a572_5aef0c8d_d70a4497; + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; - begin - for (int a=-2; a<=2; a=a+1) begin - i_bit_p0_u1[a] = crc[0]; - for (int b=-3; b<=3; b=b+1) begin - i_bit_p0_u2[a][b] = crc[0]; - for (int c=-4; c<=4; c=c+1) begin - i_bit_p0_u3[a][b][c] = crc[0]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; - end - end - end - dpii_bit_elem_p0_u1(0, 1, i_bit_p0_u1, o_bit_p0_u1, q_bit_p0_u1); - dpii_bit_elem_p0_u2(0, 2, i_bit_p0_u2, o_bit_p0_u2, q_bit_p0_u2); - dpii_bit_elem_p0_u3(0, 3, i_bit_p0_u3, o_bit_p0_u3, q_bit_p0_u3); - for (int a=-2; a<=2; a=a+1) begin - `checkh(o_bit_p0_u1[a], ~i_bit_p0_u1[a]); - `checkh(q_bit_p0_u1[a], ~i_bit_p0_u1[a]); - for (int b=-3; b<=3; b=b+1) begin - `checkh(o_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); - `checkh(q_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); - `checkh(q_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); - end - end - end + begin + for (int a=-2; a<=2; a=a+1) begin + i_bit_p0_u1[a] = crc[0]; + for (int b=-3; b<=3; b=b+1) begin + i_bit_p0_u2[a][b] = crc[0]; + for (int c=-4; c<=4; c=c+1) begin + i_bit_p0_u3[a][b][c] = crc[0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + end end + dpii_bit_elem_p0_u1(0, 1, i_bit_p0_u1, o_bit_p0_u1, q_bit_p0_u1); + dpii_bit_elem_p0_u2(0, 2, i_bit_p0_u2, o_bit_p0_u2, q_bit_p0_u2); + dpii_bit_elem_p0_u3(0, 3, i_bit_p0_u3, o_bit_p0_u3, q_bit_p0_u3); + for (int a=-2; a<=2; a=a+1) begin + `checkh(o_bit_p0_u1[a], ~i_bit_p0_u1[a]); + `checkh(q_bit_p0_u1[a], ~i_bit_p0_u1[a]); + for (int b=-3; b<=3; b=b+1) begin + `checkh(o_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); + `checkh(q_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); + `checkh(q_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); + end + end + end + end - begin - for (int a=-2; a<=2; a=a+1) begin - i_logic_p0_u1[a] = crc[0]; - for (int b=-3; b<=3; b=b+1) begin - i_logic_p0_u2[a][b] = crc[0]; - for (int c=-4; c<=4; c=c+1) begin - i_logic_p0_u3[a][b][c] = crc[0]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; - end - end - end - dpii_logic_elem_p0_u1(0, 1, i_logic_p0_u1, o_logic_p0_u1, q_logic_p0_u1); - dpii_logic_elem_p0_u2(0, 2, i_logic_p0_u2, o_logic_p0_u2, q_logic_p0_u2); - dpii_logic_elem_p0_u3(0, 3, i_logic_p0_u3, o_logic_p0_u3, q_logic_p0_u3); - for (int a=-2; a<=2; a=a+1) begin - `checkh(o_logic_p0_u1[a], ~i_logic_p0_u1[a]); - `checkh(q_logic_p0_u1[a], ~i_logic_p0_u1[a]); - for (int b=-3; b<=3; b=b+1) begin - `checkh(o_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); - `checkh(q_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); - `checkh(q_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); - end - end - end + begin + for (int a=-2; a<=2; a=a+1) begin + i_logic_p0_u1[a] = crc[0]; + for (int b=-3; b<=3; b=b+1) begin + i_logic_p0_u2[a][b] = crc[0]; + for (int c=-4; c<=4; c=c+1) begin + i_logic_p0_u3[a][b][c] = crc[0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + end end + dpii_logic_elem_p0_u1(0, 1, i_logic_p0_u1, o_logic_p0_u1, q_logic_p0_u1); + dpii_logic_elem_p0_u2(0, 2, i_logic_p0_u2, o_logic_p0_u2, q_logic_p0_u2); + dpii_logic_elem_p0_u3(0, 3, i_logic_p0_u3, o_logic_p0_u3, q_logic_p0_u3); + for (int a=-2; a<=2; a=a+1) begin + `checkh(o_logic_p0_u1[a], ~i_logic_p0_u1[a]); + `checkh(q_logic_p0_u1[a], ~i_logic_p0_u1[a]); + for (int b=-3; b<=3; b=b+1) begin + `checkh(o_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); + `checkh(q_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); + `checkh(q_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); + end + end + end + end - if (dpii_failure()!=0) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dpi_open_oob_bad.v b/test_regress/t/t_dpi_open_oob_bad.v index 36a8a8098..b1a20798d 100644 --- a/test_regress/t/t_dpi_open_oob_bad.v +++ b/test_regress/t/t_dpi_open_oob_bad.v @@ -8,33 +8,33 @@ module t; - import "DPI-C" function void dpii_nullptr(); + import "DPI-C" function void dpii_nullptr(); - // verilator lint_off UNDRIVEN - int i_int_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_int_u3(input int i [] [] []); + // verilator lint_off UNDRIVEN + int i_int_u3[2:-2][-3:3][4:-4]; + import "DPI-C" function void dpii_int_u3(input int i[][][]); - real i_real_u1 [1:0]; - import "DPI-C" function void dpii_real_u1(input real i []); + real i_real_u1[1:0]; + import "DPI-C" function void dpii_real_u1(input real i[]); - bit i_u6 [2][2][2][2][2][2]; - import "DPI-C" function void dpii_bit_u6(input bit i [][][][][][]); + bit i_u6[2][2][2][2][2][2]; + import "DPI-C" function void dpii_bit_u6(input bit i[][][][][][]); - real i_real_u6 [2][2][2][2][2][2]; - import "DPI-C" function void dpii_real_u6(input real i [][][][][][]); + real i_real_u6[2][2][2][2][2][2]; + import "DPI-C" function void dpii_real_u6(input real i[][][][][][]); - initial begin - i_int_u3[0][0][0] = 32'hbad; - i_real_u1[0] = 1.1; - i_u6[0][0][0][0][0][0] = 1'b1; + initial begin + i_int_u3[0][0][0] = 32'hbad; + i_real_u1[0] = 1.1; + i_u6[0][0][0][0][0][0] = 1'b1; - dpii_nullptr(); - dpii_int_u3(i_int_u3); - dpii_real_u1(i_real_u1); - dpii_bit_u6(i_u6); - dpii_real_u6(i_real_u6); - $write("*-* All Finished *-*\n"); - $finish; - end + dpii_nullptr(); + dpii_int_u3(i_int_u3); + dpii_real_u1(i_real_u1); + dpii_bit_u6(i_u6); + dpii_real_u6(i_real_u6); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_open_query.v b/test_regress/t/t_dpi_open_query.v index 3634738e0..a49b18b91 100644 --- a/test_regress/t/t_dpi_open_query.v +++ b/test_regress/t/t_dpi_open_query.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define unless(cond,gotv,expv) do if (!(cond)) `check(gotv, expv); while(0) @@ -38,278 +39,278 @@ module t; - // 1 open dimension - import "DPI-C" function int cSvLeft1( input bit h [], int d); - import "DPI-C" function int cSvRight1( input bit h [], int d); - import "DPI-C" function int cSvLow1( input bit h [], int d); - import "DPI-C" function int cSvHigh1( input bit h [], int d); - import "DPI-C" function int cSvIncrement1( input bit h [], int d); - import "DPI-C" function int cSvSize1( input bit h [], int d); - import "DPI-C" function int cSvDimensions1( input bit h []); + // 1 open dimension + import "DPI-C" function int cSvLeft1( input bit h [], int d); + import "DPI-C" function int cSvRight1( input bit h [], int d); + import "DPI-C" function int cSvLow1( input bit h [], int d); + import "DPI-C" function int cSvHigh1( input bit h [], int d); + import "DPI-C" function int cSvIncrement1( input bit h [], int d); + import "DPI-C" function int cSvSize1( input bit h [], int d); + import "DPI-C" function int cSvDimensions1( input bit h []); - // 2 open dimensions - import "DPI-C" function int cSvLeft2( input bit h [][], int d); - import "DPI-C" function int cSvRight2( input bit h [][], int d); - import "DPI-C" function int cSvLow2( input bit h [][], int d); - import "DPI-C" function int cSvHigh2( input bit h [][], int d); - import "DPI-C" function int cSvIncrement2( input bit h [][], int d); - import "DPI-C" function int cSvSize2( input bit h [][], int d); - import "DPI-C" function int cSvDimensions2( input bit h [][]); + // 2 open dimensions + import "DPI-C" function int cSvLeft2( input bit h [][], int d); + import "DPI-C" function int cSvRight2( input bit h [][], int d); + import "DPI-C" function int cSvLow2( input bit h [][], int d); + import "DPI-C" function int cSvHigh2( input bit h [][], int d); + import "DPI-C" function int cSvIncrement2( input bit h [][], int d); + import "DPI-C" function int cSvSize2( input bit h [][], int d); + import "DPI-C" function int cSvDimensions2( input bit h [][]); - // 3 open dimensions - import "DPI-C" function int cSvLeft3( input bit h [][][], int d); - import "DPI-C" function int cSvRight3( input bit h [][][], int d); - import "DPI-C" function int cSvLow3( input bit h [][][], int d); - import "DPI-C" function int cSvHigh3( input bit h [][][], int d); - import "DPI-C" function int cSvIncrement3( input bit h [][][], int d); - import "DPI-C" function int cSvSize3( input bit h [][][], int d); - import "DPI-C" function int cSvDimensions3( input bit h [][][]); + // 3 open dimensions + import "DPI-C" function int cSvLeft3( input bit h [][][], int d); + import "DPI-C" function int cSvRight3( input bit h [][][], int d); + import "DPI-C" function int cSvLow3( input bit h [][][], int d); + import "DPI-C" function int cSvHigh3( input bit h [][][], int d); + import "DPI-C" function int cSvIncrement3( input bit h [][][], int d); + import "DPI-C" function int cSvSize3( input bit h [][][], int d); + import "DPI-C" function int cSvDimensions3( input bit h [][][]); - // 4 open dimensions - import "DPI-C" function int cSvLeft4( input bit h [][][][], int d); - import "DPI-C" function int cSvRight4( input bit h [][][][], int d); - import "DPI-C" function int cSvLow4( input bit h [][][][], int d); - import "DPI-C" function int cSvHigh4( input bit h [][][][], int d); - import "DPI-C" function int cSvIncrement4( input bit h [][][][], int d); - import "DPI-C" function int cSvSize4( input bit h [][][][], int d); - import "DPI-C" function int cSvDimensions4( input bit h [][][][]); + // 4 open dimensions + import "DPI-C" function int cSvLeft4( input bit h [][][][], int d); + import "DPI-C" function int cSvRight4( input bit h [][][][], int d); + import "DPI-C" function int cSvLow4( input bit h [][][][], int d); + import "DPI-C" function int cSvHigh4( input bit h [][][][], int d); + import "DPI-C" function int cSvIncrement4( input bit h [][][][], int d); + import "DPI-C" function int cSvSize4( input bit h [][][][], int d); + import "DPI-C" function int cSvDimensions4( input bit h [][][][]); - // verilator lint_off UNDRIVEN - bit a1 [1:0]; - bit a2 [1:0][2:0]; - bit a3 [1:0][2:0][3:0]; - bit a4 [1:0][2:0][3:0][4:0]; + // verilator lint_off UNDRIVEN + bit a1 [1:0]; + bit a2 [1:0][2:0]; + bit a3 [1:0][2:0][3:0]; + bit a4 [1:0][2:0][3:0][4:0]; - bit b1 [0:1]; - bit b2 [0:1][0:2]; - bit b3 [0:1][0:2][0:3]; - bit b4 [0:1][0:2][0:3][0:4]; + bit b1 [0:1]; + bit b2 [0:1][0:2]; + bit b3 [0:1][0:2][0:3]; + bit b4 [0:1][0:2][0:3][0:4]; - bit c1 [-1:1]; - bit c2 [-1:1][-2:2]; - bit c3 [-1:1][-2:2][-3:3]; - bit c4 [-1:1][-2:2][-3:3][-4:4]; + bit c1 [-1:1]; + bit c2 [-1:1][-2:2]; + bit c3 [-1:1][-2:2][-3:3]; + bit c4 [-1:1][-2:2][-3:3][-4:4]; `ifndef NO_DYNAMIC - bit d1 []; - bit d2 [][-2:2]; - bit d3 [][-2:2][-3:3]; - bit d4 [][-2:2][-3:3][-4:4]; + bit d1 []; + bit d2 [][-2:2]; + bit d3 [][-2:2][-3:3]; + bit d4 [][-2:2][-3:3][-4:4]; `endif `ifndef NO_QUEUE - bit e1 [$]; + bit e1 [$]; `endif - // verilator lint_on UNDRIVEN + // verilator lint_on UNDRIVEN - initial begin + initial begin `ifndef NO_DYNAMIC - d1 = new[3]; - d2 = new[3]; - d3 = new[3]; - d4 = new[3]; + d1 = new[3]; + d2 = new[3]; + d3 = new[3]; + d4 = new[3]; `endif `ifndef NO_QUEUE - e1.push_back(0); - e1.push_back(0); - e1.push_back(0); + e1.push_back(0); + e1.push_back(0); + e1.push_back(0); `endif - // 1 open dimension - `check(cSvDimensions1(a1), 1); - `check(cSvDimensions1(b1), 1); - `check(cSvDimensions1(c1), 1); + // 1 open dimension + `check(cSvDimensions1(a1), 1); + `check(cSvDimensions1(b1), 1); + `check(cSvDimensions1(c1), 1); `ifndef NO_DYNAMIC - `check(cSvDimensions1(d1), 1); + `check(cSvDimensions1(d1), 1); `endif `ifndef NO_QUEUE - `check(cSvDimensions1(e1), 1); + `check(cSvDimensions1(e1), 1); `endif - for (int d = 0 ; d < 2 ; d++) begin - if (`ONNC && d == 0) continue; + for (int d = 0 ; d < 2 ; d++) begin + if (`ONNC && d == 0) continue; - `check(cSvLeft1(a1, d), d); - `check(cSvRight1(a1, d), 0); - `check(cSvLow1(a1, d), 0); - `check(cSvHigh1(a1, d), d); - `unless(`ONMS && d == 0, cSvIncrement1(a1, d), 1); - `check(cSvSize1(a1, d), d+1); + `check(cSvLeft1(a1, d), d); + `check(cSvRight1(a1, d), 0); + `check(cSvLow1(a1, d), 0); + `check(cSvHigh1(a1, d), d); + `unless(`ONMS && d == 0, cSvIncrement1(a1, d), 1); + `check(cSvSize1(a1, d), d+1); - `check(cSvLeft1(b1, d), 0); - `check(cSvRight1(b1, d), d); - `check(cSvLow1(b1, d), 0); - `check(cSvHigh1(b1, d), d); + `check(cSvLeft1(b1, d), 0); + `check(cSvRight1(b1, d), d); + `check(cSvLow1(b1, d), 0); + `check(cSvHigh1(b1, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement1(b1, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement1(b1, d), d == 0 ? 1 : -1); `endif - `check(cSvSize1(b1, d), d+1); + `check(cSvSize1(b1, d), d+1); - `check(cSvLeft1(c1, d), -d); - `check(cSvRight1(c1, d), d); - `check(cSvLow1(c1, d), -d); - `check(cSvHigh1(c1, d), d); + `check(cSvLeft1(c1, d), -d); + `check(cSvRight1(c1, d), d); + `check(cSvLow1(c1, d), -d); + `check(cSvHigh1(c1, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement1(c1, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement1(c1, d), d == 0 ? 1 : -1); `endif - `check(cSvSize1(c1, d), 2*d+1); + `check(cSvSize1(c1, d), 2*d+1); `ifndef NO_DYNAMIC - `check(cSvLeft1(d1, d), d == 1 ? 0 : -d); - `check(cSvRight1(d1, d), d == 1 ? 2 : d); - `check(cSvLow1(d1, d), d == 1 ? 0 : -d); - `check(cSvHigh1(d1, d), d == 1 ? 2 : d); - `unless(`ONMS && d == 0, cSvIncrement1(d1, d), d == 0 ? 1 : -1); - `check(cSvSize1(d1, d), 2*d+1); + `check(cSvLeft1(d1, d), d == 1 ? 0 : -d); + `check(cSvRight1(d1, d), d == 1 ? 2 : d); + `check(cSvLow1(d1, d), d == 1 ? 0 : -d); + `check(cSvHigh1(d1, d), d == 1 ? 2 : d); + `unless(`ONMS && d == 0, cSvIncrement1(d1, d), d == 0 ? 1 : -1); + `check(cSvSize1(d1, d), 2*d+1); `endif `ifndef NO_QUEUE - `check(cSvLeft1(e1, d), d == 1 ? 0 : -d); - `check(cSvRight1(e1, d), d == 1 ? 2 : d); - `check(cSvLow1(e1, d), d == 1 ? 0 : -d); - `check(cSvHigh1(e1, d), d == 1 ? 2 : d); - `unless(`ONMS && d == 0, cSvIncrement1(e1, d), d == 0 ? 1 : -1); - `check(cSvSize1(e1, d), 2*d+1); + `check(cSvLeft1(e1, d), d == 1 ? 0 : -d); + `check(cSvRight1(e1, d), d == 1 ? 2 : d); + `check(cSvLow1(e1, d), d == 1 ? 0 : -d); + `check(cSvHigh1(e1, d), d == 1 ? 2 : d); + `unless(`ONMS && d == 0, cSvIncrement1(e1, d), d == 0 ? 1 : -1); + `check(cSvSize1(e1, d), 2*d+1); `endif - end + end - // 2 open dimensions - `check(cSvDimensions2(a2), 2); - `check(cSvDimensions2(b2), 2); - `check(cSvDimensions2(c2), 2); + // 2 open dimensions + `check(cSvDimensions2(a2), 2); + `check(cSvDimensions2(b2), 2); + `check(cSvDimensions2(c2), 2); `ifndef NO_DYNAMIC - `check(cSvDimensions2(d2), 2); + `check(cSvDimensions2(d2), 2); `endif - for (int d = 0 ; d < 3 ; d++) begin - if (`ONNC && d == 0) continue; + for (int d = 0 ; d < 3 ; d++) begin + if (`ONNC && d == 0) continue; - `check(cSvLeft2(a2, d), d); - `check(cSvRight2(a2, d), 0); - `check(cSvLow2(a2, d), 0); - `check(cSvHigh2(a2, d), d); - `unless(`ONMS && d == 0, cSvIncrement2(a2, d), 1); - `check(cSvSize2(a2, d), d+1); + `check(cSvLeft2(a2, d), d); + `check(cSvRight2(a2, d), 0); + `check(cSvLow2(a2, d), 0); + `check(cSvHigh2(a2, d), d); + `unless(`ONMS && d == 0, cSvIncrement2(a2, d), 1); + `check(cSvSize2(a2, d), d+1); - `check(cSvLeft2(b2, d), 0); - `check(cSvRight2(b2, d), d); - `check(cSvLow2(b2, d), 0); - `check(cSvHigh2(b2, d), d); + `check(cSvLeft2(b2, d), 0); + `check(cSvRight2(b2, d), d); + `check(cSvLow2(b2, d), 0); + `check(cSvHigh2(b2, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement2(b2, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement2(b2, d), d == 0 ? 1 : -1); `endif - `check(cSvSize2(b2, d), d+1); + `check(cSvSize2(b2, d), d+1); - `check(cSvLeft2(c2, d), -d); - `check(cSvRight2(c2, d), d); - `check(cSvLow2(c2, d), -d); - `check(cSvHigh2(c2, d), d); + `check(cSvLeft2(c2, d), -d); + `check(cSvRight2(c2, d), d); + `check(cSvLow2(c2, d), -d); + `check(cSvHigh2(c2, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement2(c2, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement2(c2, d), d == 0 ? 1 : -1); `endif - `check(cSvSize2(c2, d), 2*d+1); + `check(cSvSize2(c2, d), 2*d+1); `ifndef NO_DYNAMIC - `check(cSvLeft2(d2, d), d == 1 ? 0 : -d); - `check(cSvRight2(d2, d), d == 1 ? 2 : d); - `check(cSvLow2(d2, d), d == 1 ? 0 : -d); - `check(cSvHigh2(d2, d), d == 1 ? 2 : d); - `unless(`ONMS && d == 0, cSvIncrement2(d2, d), d == 0 ? 1 : -1); - `check(cSvSize2(d2, d), 2*d+1); + `check(cSvLeft2(d2, d), d == 1 ? 0 : -d); + `check(cSvRight2(d2, d), d == 1 ? 2 : d); + `check(cSvLow2(d2, d), d == 1 ? 0 : -d); + `check(cSvHigh2(d2, d), d == 1 ? 2 : d); + `unless(`ONMS && d == 0, cSvIncrement2(d2, d), d == 0 ? 1 : -1); + `check(cSvSize2(d2, d), 2*d+1); `endif - end + end - // 3 open dimensions - `check(cSvDimensions3(a3), 3); - `check(cSvDimensions3(b3), 3); - `check(cSvDimensions3(c3), 3); + // 3 open dimensions + `check(cSvDimensions3(a3), 3); + `check(cSvDimensions3(b3), 3); + `check(cSvDimensions3(c3), 3); `ifndef NO_DYNAMIC - `check(cSvDimensions3(d3), 3); + `check(cSvDimensions3(d3), 3); `endif - for (int d = 0 ; d < 4 ; d++) begin - if (`ONNC && d == 0) continue; + for (int d = 0 ; d < 4 ; d++) begin + if (`ONNC && d == 0) continue; - `check(cSvLeft3(a3, d), d); - `check(cSvRight3(a3, d), 0); - `check(cSvLow3(a3, d), 0); - `check(cSvHigh3(a3, d), d); - `unless(`ONMS && d == 0, cSvIncrement3(a3, d), 1); - `check(cSvSize3(a3, d), d+1); + `check(cSvLeft3(a3, d), d); + `check(cSvRight3(a3, d), 0); + `check(cSvLow3(a3, d), 0); + `check(cSvHigh3(a3, d), d); + `unless(`ONMS && d == 0, cSvIncrement3(a3, d), 1); + `check(cSvSize3(a3, d), d+1); - `check(cSvLeft3(b3, d), 0); - `check(cSvRight3(b3, d), d); - `check(cSvLow3(b3, d), 0); - `check(cSvHigh3(b3, d), d); + `check(cSvLeft3(b3, d), 0); + `check(cSvRight3(b3, d), d); + `check(cSvLow3(b3, d), 0); + `check(cSvHigh3(b3, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement3(b3, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement3(b3, d), d == 0 ? 1 : -1); `endif - `check(cSvSize3(b3, d), d+1); + `check(cSvSize3(b3, d), d+1); - `check(cSvLeft3(c3, d), -d); - `check(cSvRight3(c3, d), d); - `check(cSvLow3(c3, d), -d); - `check(cSvHigh3(c3, d), d); + `check(cSvLeft3(c3, d), -d); + `check(cSvRight3(c3, d), d); + `check(cSvLow3(c3, d), -d); + `check(cSvHigh3(c3, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement3(c3, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement3(c3, d), d == 0 ? 1 : -1); `endif - `check(cSvSize3(c3, d), 2*d+1); + `check(cSvSize3(c3, d), 2*d+1); `ifndef NO_DYNAMIC - `check(cSvLeft3(d3, d), d == 1 ? 0 : -d); - `check(cSvRight3(d3, d), d == 1 ? 2 : d); - `check(cSvLow3(d3, d), d == 1 ? 0 : -d); - `check(cSvHigh3(d3, d), d == 1 ? 2 : d); - `unless(`ONMS && d == 0, cSvIncrement3(d3, d), d == 0 ? 1 : -1); - `check(cSvSize3(d3, d), 2*d+1); + `check(cSvLeft3(d3, d), d == 1 ? 0 : -d); + `check(cSvRight3(d3, d), d == 1 ? 2 : d); + `check(cSvLow3(d3, d), d == 1 ? 0 : -d); + `check(cSvHigh3(d3, d), d == 1 ? 2 : d); + `unless(`ONMS && d == 0, cSvIncrement3(d3, d), d == 0 ? 1 : -1); + `check(cSvSize3(d3, d), 2*d+1); `endif - end + end - // 4 open dimension - `check(cSvDimensions4(a4), 4); - `check(cSvDimensions4(b4), 4); - `check(cSvDimensions4(c4), 4); + // 4 open dimension + `check(cSvDimensions4(a4), 4); + `check(cSvDimensions4(b4), 4); + `check(cSvDimensions4(c4), 4); `ifndef NO_DYNAMIC - `check(cSvDimensions4(d4), 4); + `check(cSvDimensions4(d4), 4); `endif - for (int d = 0 ; d < 5 ; d++) begin - if (`ONNC && d == 0) continue; + for (int d = 0 ; d < 5 ; d++) begin + if (`ONNC && d == 0) continue; - `check(cSvLeft4(a4, d), d); - `check(cSvRight4(a4, d), 0); - `check(cSvLow4(a4, d), 0); - `check(cSvHigh4(a4, d), d); - `unless(`ONMS && d == 0, cSvIncrement4(a4, d), 1); - `check(cSvSize4(a4, d), d+1); + `check(cSvLeft4(a4, d), d); + `check(cSvRight4(a4, d), 0); + `check(cSvLow4(a4, d), 0); + `check(cSvHigh4(a4, d), d); + `unless(`ONMS && d == 0, cSvIncrement4(a4, d), 1); + `check(cSvSize4(a4, d), d+1); - `check(cSvLeft4(b4, d), 0); - `check(cSvRight4(b4, d), d); - `check(cSvLow4(b4, d), 0); - `check(cSvHigh4(b4, d), d); + `check(cSvLeft4(b4, d), 0); + `check(cSvRight4(b4, d), d); + `check(cSvLow4(b4, d), 0); + `check(cSvHigh4(b4, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement4(b4, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement4(b4, d), d == 0 ? 1 : -1); `endif - `check(cSvSize4(b4, d), d+1); + `check(cSvSize4(b4, d), d+1); - `check(cSvLeft4(c4, d), -d); - `check(cSvRight4(c4, d), d); - `check(cSvLow4(c4, d), -d); - `check(cSvHigh4(c4, d), d); + `check(cSvLeft4(c4, d), -d); + `check(cSvRight4(c4, d), d); + `check(cSvLow4(c4, d), -d); + `check(cSvHigh4(c4, d), d); `ifndef NC - `unless(`ONMS && d == 0, cSvIncrement4(c4, d), d == 0 ? 1 : -1); + `unless(`ONMS && d == 0, cSvIncrement4(c4, d), d == 0 ? 1 : -1); `endif - `check(cSvSize4(c4, d), 2*d+1); + `check(cSvSize4(c4, d), 2*d+1); `ifndef NO_DYNAMIC - `check(cSvLeft4(d4, d), d == 1 ? 0 : -d); - `check(cSvRight4(d4, d), d == 1 ? 2 : d); - `check(cSvLow4(d4, d), d == 1 ? 0 : -d); - `check(cSvHigh4(d4, d), d == 1 ? 2 : d); - `unless(`ONMS && d == 0, cSvIncrement4(d4, d), d == 0 ? 1 : -1); - `check(cSvSize4(d4, d), 2*d+1); + `check(cSvLeft4(d4, d), d == 1 ? 0 : -d); + `check(cSvRight4(d4, d), d == 1 ? 2 : d); + `check(cSvLow4(d4, d), d == 1 ? 0 : -d); + `check(cSvHigh4(d4, d), d == 1 ? 2 : d); + `unless(`ONMS && d == 0, cSvIncrement4(d4, d), d == 0 ? 1 : -1); + `check(cSvSize4(d4, d), 2*d+1); `endif - end + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_open_vecval.v b/test_regress/t/t_dpi_open_vecval.v index 1b76664a3..494c7d4d4 100644 --- a/test_regress/t/t_dpi_open_vecval.v +++ b/test_regress/t/t_dpi_open_vecval.v @@ -6,152 +6,153 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - `define stop $stop +// verilog_format: off +`define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; - // Note that a packed array is required, otherwise some simulators will return bad - // results using *ElemVecVal() routines instead of scalar *Elem() routines. - bit [0:0] i_bit_p1_u1 [2:-2]; - bit [0:0] o_bit_p1_u1 [2:-2]; - bit [0:0] q_bit_p1_u1 [2:-2]; - bit [60:0] i_bit61_p1_u1 [2:-2]; - bit [60:0] o_bit61_p1_u1 [2:-2]; - bit [60:0] q_bit61_p1_u1 [2:-2]; - bit [91:0] i_bit92_p1_u1 [2:-2]; - bit [91:0] o_bit92_p1_u1 [2:-2]; - bit [91:0] q_bit92_p1_u1 [2:-2]; - bit [11:0] i_bit12_p1_u2 [2:-2] [-3:3]; - bit [11:0] o_bit12_p1_u2 [2:-2] [-3:3]; - bit [11:0] q_bit12_p1_u2 [2:-2] [-3:3]; - bit [29:1] i_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; - bit [29:1] o_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; - bit [29:1] q_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_bit_vecval_p1_u1 - (int bits, int p, int u, input bit [0:0] i [], output bit [0:0] o [], output bit [0:0] q []); - import "DPI-C" function void dpii_bit61_vecval_p1_u1 - (int bits, int p, int u, input bit [60:0] i [], output bit [60:0] o [], output bit [60:0] q []); - import "DPI-C" function void dpii_bit92_vecval_p1_u1 - (int bits, int p, int u, input bit [91:0] i [], output bit [91:0] o [], output bit [91:0] q []); - import "DPI-C" function void dpii_bit12_vecval_p1_u2 - (int bits, int p, int u, input bit [11:0] i [] [], output bit [11:0] o [] [], output bit [11:0] q [] []); - import "DPI-C" function void dpii_bit29_vecval_p1_u3 - (int bits, int p, int u, input bit [29:1] i [] [] [], output bit [29:1] o [] [] [], output bit [29:1] q [] [] []); + // Note that a packed array is required, otherwise some simulators will return bad + // results using *ElemVecVal() routines instead of scalar *Elem() routines. + bit [0:0] i_bit_p1_u1 [2:-2]; + bit [0:0] o_bit_p1_u1 [2:-2]; + bit [0:0] q_bit_p1_u1 [2:-2]; + bit [60:0] i_bit61_p1_u1 [2:-2]; + bit [60:0] o_bit61_p1_u1 [2:-2]; + bit [60:0] q_bit61_p1_u1 [2:-2]; + bit [91:0] i_bit92_p1_u1 [2:-2]; + bit [91:0] o_bit92_p1_u1 [2:-2]; + bit [91:0] q_bit92_p1_u1 [2:-2]; + bit [11:0] i_bit12_p1_u2 [2:-2] [-3:3]; + bit [11:0] o_bit12_p1_u2 [2:-2] [-3:3]; + bit [11:0] q_bit12_p1_u2 [2:-2] [-3:3]; + bit [29:1] i_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; + bit [29:1] o_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; + bit [29:1] q_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; + import "DPI-C" function void dpii_bit_vecval_p1_u1 + (int bits, int p, int u, input bit [0:0] i [], output bit [0:0] o [], output bit [0:0] q []); + import "DPI-C" function void dpii_bit61_vecval_p1_u1 + (int bits, int p, int u, input bit [60:0] i [], output bit [60:0] o [], output bit [60:0] q []); + import "DPI-C" function void dpii_bit92_vecval_p1_u1 + (int bits, int p, int u, input bit [91:0] i [], output bit [91:0] o [], output bit [91:0] q []); + import "DPI-C" function void dpii_bit12_vecval_p1_u2 + (int bits, int p, int u, input bit [11:0] i [] [], output bit [11:0] o [] [], output bit [11:0] q [] []); + import "DPI-C" function void dpii_bit29_vecval_p1_u3 + (int bits, int p, int u, input bit [29:1] i [] [] [], output bit [29:1] o [] [] [], output bit [29:1] q [] [] []); - logic [0:0] i_logic_p1_u1 [2:-2]; - logic [0:0] o_logic_p1_u1 [2:-2]; - logic [0:0] q_logic_p1_u1 [2:-2]; - logic [60:0] i_logic61_p1_u1 [2:-2]; - logic [60:0] o_logic61_p1_u1 [2:-2]; - logic [60:0] q_logic61_p1_u1 [2:-2]; - logic [91:0] i_logic92_p1_u1 [2:-2]; - logic [91:0] o_logic92_p1_u1 [2:-2]; - logic [91:0] q_logic92_p1_u1 [2:-2]; - logic [11:0] i_logic12_p1_u2 [2:-2] [-3:3]; - logic [11:0] o_logic12_p1_u2 [2:-2] [-3:3]; - logic [11:0] q_logic12_p1_u2 [2:-2] [-3:3]; - logic [29:1] i_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; - logic [29:1] o_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; - logic [29:1] q_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; - import "DPI-C" function void dpii_logic_vecval_p1_u1 - (int logics, int p, int u, input logic [0:0] i [], output logic [0:0] o [], output logic [0:0] q []); - import "DPI-C" function void dpii_logic61_vecval_p1_u1 - (int logics, int p, int u, input logic [60:0] i [], output logic [60:0] o [], output logic [60:0] q []); - import "DPI-C" function void dpii_logic92_vecval_p1_u1 - (int logics, int p, int u, input logic [91:0] i [], output logic [91:0] o [], output logic [91:0] q []); - import "DPI-C" function void dpii_logic12_vecval_p1_u2 - (int logics, int p, int u, input logic [11:0] i [] [], output logic [11:0] o [] [], output logic [11:0] q [] []); - import "DPI-C" function void dpii_logic29_vecval_p1_u3 - (int logics, int p, int u, input logic [29:1] i [] [] [], output logic [29:1] o [] [] [], output logic [29:1] q [] [] []); + logic [0:0] i_logic_p1_u1 [2:-2]; + logic [0:0] o_logic_p1_u1 [2:-2]; + logic [0:0] q_logic_p1_u1 [2:-2]; + logic [60:0] i_logic61_p1_u1 [2:-2]; + logic [60:0] o_logic61_p1_u1 [2:-2]; + logic [60:0] q_logic61_p1_u1 [2:-2]; + logic [91:0] i_logic92_p1_u1 [2:-2]; + logic [91:0] o_logic92_p1_u1 [2:-2]; + logic [91:0] q_logic92_p1_u1 [2:-2]; + logic [11:0] i_logic12_p1_u2 [2:-2] [-3:3]; + logic [11:0] o_logic12_p1_u2 [2:-2] [-3:3]; + logic [11:0] q_logic12_p1_u2 [2:-2] [-3:3]; + logic [29:1] i_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; + logic [29:1] o_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; + logic [29:1] q_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; + import "DPI-C" function void dpii_logic_vecval_p1_u1 + (int logics, int p, int u, input logic [0:0] i [], output logic [0:0] o [], output logic [0:0] q []); + import "DPI-C" function void dpii_logic61_vecval_p1_u1 + (int logics, int p, int u, input logic [60:0] i [], output logic [60:0] o [], output logic [60:0] q []); + import "DPI-C" function void dpii_logic92_vecval_p1_u1 + (int logics, int p, int u, input logic [91:0] i [], output logic [91:0] o [], output logic [91:0] q []); + import "DPI-C" function void dpii_logic12_vecval_p1_u2 + (int logics, int p, int u, input logic [11:0] i [] [], output logic [11:0] o [] [], output logic [11:0] q [] []); + import "DPI-C" function void dpii_logic29_vecval_p1_u3 + (int logics, int p, int u, input logic [29:1] i [] [] [], output logic [29:1] o [] [] [], output logic [29:1] q [] [] []); - import "DPI-C" function int dpii_failure(); + import "DPI-C" function int dpii_failure(); - reg [95:0] crc; + reg [95:0] crc; - initial begin - crc = 96'h8a10a572_5aef0c8d_d70a4497; + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; - begin - for (int a=-2; a<=2; a=a+1) begin - i_bit_p1_u1[a] = crc[0]; - i_bit61_p1_u1[a] = crc[60:0]; - i_bit92_p1_u1[a] = crc[91:0]; - for (int b=-3; b<=3; b=b+1) begin - i_bit12_p1_u2[a][b] = crc[11:0]; - for (int c=-4; c<=4; c=c+1) begin - i_bit29_p1_u3[a][b][c] = crc[29:1]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; - end - end - end - dpii_bit_vecval_p1_u1(1, 1, 1, i_bit_p1_u1, o_bit_p1_u1, q_bit_p1_u1); - dpii_bit61_vecval_p1_u1(61, 1, 1, i_bit61_p1_u1, o_bit61_p1_u1, q_bit61_p1_u1); - dpii_bit92_vecval_p1_u1(92, 1, 1, i_bit92_p1_u1, o_bit92_p1_u1, q_bit92_p1_u1); - dpii_bit12_vecval_p1_u2(12, 1, 2, i_bit12_p1_u2, o_bit12_p1_u2, q_bit12_p1_u2); - dpii_bit29_vecval_p1_u3(29, 1, 3, i_bit29_p1_u3, o_bit29_p1_u3, q_bit29_p1_u3); - for (int a=-2; a<=2; a=a+1) begin - `checkh(o_bit_p1_u1[a], ~i_bit_p1_u1[a]); - `checkh(q_bit_p1_u1[a], ~i_bit_p1_u1[a]); - `checkh(o_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); - `checkh(q_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); - `checkh(o_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); - `checkh(q_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); - for (int b=-3; b<=3; b=b+1) begin - `checkh(o_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); - `checkh(q_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); - `checkh(q_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); - end - end - end + begin + for (int a=-2; a<=2; a=a+1) begin + i_bit_p1_u1[a] = crc[0]; + i_bit61_p1_u1[a] = crc[60:0]; + i_bit92_p1_u1[a] = crc[91:0]; + for (int b=-3; b<=3; b=b+1) begin + i_bit12_p1_u2[a][b] = crc[11:0]; + for (int c=-4; c<=4; c=c+1) begin + i_bit29_p1_u3[a][b][c] = crc[29:1]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + end end + dpii_bit_vecval_p1_u1(1, 1, 1, i_bit_p1_u1, o_bit_p1_u1, q_bit_p1_u1); + dpii_bit61_vecval_p1_u1(61, 1, 1, i_bit61_p1_u1, o_bit61_p1_u1, q_bit61_p1_u1); + dpii_bit92_vecval_p1_u1(92, 1, 1, i_bit92_p1_u1, o_bit92_p1_u1, q_bit92_p1_u1); + dpii_bit12_vecval_p1_u2(12, 1, 2, i_bit12_p1_u2, o_bit12_p1_u2, q_bit12_p1_u2); + dpii_bit29_vecval_p1_u3(29, 1, 3, i_bit29_p1_u3, o_bit29_p1_u3, q_bit29_p1_u3); + for (int a=-2; a<=2; a=a+1) begin + `checkh(o_bit_p1_u1[a], ~i_bit_p1_u1[a]); + `checkh(q_bit_p1_u1[a], ~i_bit_p1_u1[a]); + `checkh(o_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); + `checkh(q_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); + `checkh(o_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); + `checkh(q_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); + for (int b=-3; b<=3; b=b+1) begin + `checkh(o_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); + `checkh(q_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); + `checkh(q_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); + end + end + end + end - begin - for (int a=-2; a<=2; a=a+1) begin - i_logic_p1_u1[a] = crc[0]; - i_logic61_p1_u1[a] = crc[60:0]; - i_logic92_p1_u1[a] = crc[91:0]; - for (int b=-3; b<=3; b=b+1) begin - i_logic12_p1_u2[a][b] = crc[11:0]; - for (int c=-4; c<=4; c=c+1) begin - i_logic29_p1_u3[a][b][c] = crc[29:1]; - crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; - end - end - end - dpii_logic_vecval_p1_u1(1, 1, 1, i_logic_p1_u1, o_logic_p1_u1, q_logic_p1_u1); - dpii_logic61_vecval_p1_u1(61, 1, 1, i_logic61_p1_u1, o_logic61_p1_u1, q_logic61_p1_u1); - dpii_logic92_vecval_p1_u1(92, 1, 1, i_logic92_p1_u1, o_logic92_p1_u1, q_logic92_p1_u1); - dpii_logic12_vecval_p1_u2(12, 1, 2, i_logic12_p1_u2, o_logic12_p1_u2, q_logic12_p1_u2); - dpii_logic29_vecval_p1_u3(29, 1, 3, i_logic29_p1_u3, o_logic29_p1_u3, q_logic29_p1_u3); - for (int a=-2; a<=2; a=a+1) begin - `checkh(o_logic_p1_u1[a], ~i_logic_p1_u1[a]); - `checkh(q_logic_p1_u1[a], ~i_logic_p1_u1[a]); - `checkh(o_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); - `checkh(q_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); - `checkh(o_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); - `checkh(q_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); - for (int b=-3; b<=3; b=b+1) begin - `checkh(o_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); - `checkh(q_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); - for (int c=-4; c<=4; c=c+1) begin - `checkh(o_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); - `checkh(q_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); - end - end - end + begin + for (int a=-2; a<=2; a=a+1) begin + i_logic_p1_u1[a] = crc[0]; + i_logic61_p1_u1[a] = crc[60:0]; + i_logic92_p1_u1[a] = crc[91:0]; + for (int b=-3; b<=3; b=b+1) begin + i_logic12_p1_u2[a][b] = crc[11:0]; + for (int c=-4; c<=4; c=c+1) begin + i_logic29_p1_u3[a][b][c] = crc[29:1]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + end end + dpii_logic_vecval_p1_u1(1, 1, 1, i_logic_p1_u1, o_logic_p1_u1, q_logic_p1_u1); + dpii_logic61_vecval_p1_u1(61, 1, 1, i_logic61_p1_u1, o_logic61_p1_u1, q_logic61_p1_u1); + dpii_logic92_vecval_p1_u1(92, 1, 1, i_logic92_p1_u1, o_logic92_p1_u1, q_logic92_p1_u1); + dpii_logic12_vecval_p1_u2(12, 1, 2, i_logic12_p1_u2, o_logic12_p1_u2, q_logic12_p1_u2); + dpii_logic29_vecval_p1_u3(29, 1, 3, i_logic29_p1_u3, o_logic29_p1_u3, q_logic29_p1_u3); + for (int a=-2; a<=2; a=a+1) begin + `checkh(o_logic_p1_u1[a], ~i_logic_p1_u1[a]); + `checkh(q_logic_p1_u1[a], ~i_logic_p1_u1[a]); + `checkh(o_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); + `checkh(q_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); + `checkh(o_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); + `checkh(q_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); + for (int b=-3; b<=3; b=b+1) begin + `checkh(o_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); + `checkh(q_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); + `checkh(q_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); + end + end + end + end - if (dpii_failure()!=0) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dpi_openfirst.v b/test_regress/t/t_dpi_openfirst.v index 9c645cc9e..cb07627d3 100644 --- a/test_regress/t/t_dpi_openfirst.v +++ b/test_regress/t/t_dpi_openfirst.v @@ -6,42 +6,47 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VERILATOR `define stop $stop `else `define stop `endif `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - int i_i [2:0]; - int o_i [2:0]; + int i_i[2:0]; + int o_i[2:0]; - import "DPI-C" function int dpii_failure(); - import "DPI-C" function void dpii_open_i(input int i [], output int o []); + import "DPI-C" function int dpii_failure(); + import "DPI-C" function void dpii_open_i( + input int i[], + output int o[] + ); - reg [95:0] crc; + reg [95:0] crc; - initial begin - crc = 96'h8a10a572_5aef0c8d_d70a4497; + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; - i_i[0] = crc[31:0]; - i_i[1] = crc[63:32]; - i_i[2] = crc[95:64]; - dpii_open_i(i_i, o_i); - `checkh(o_i[0], ~i_i[0]); - `checkh(o_i[1], ~i_i[1]); - `checkh(o_i[2], ~i_i[2]); + i_i[0] = crc[31:0]; + i_i[1] = crc[63:32]; + i_i[2] = crc[95:64]; + dpii_open_i(i_i, o_i); + `checkh(o_i[0], ~i_i[0]); + `checkh(o_i[1], ~i_i[1]); + `checkh(o_i[2], ~i_i[2]); - if (dpii_failure()!=0) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (dpii_failure() != 0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_dpi_qw.v b/test_regress/t/t_dpi_qw.v index efb48fb8b..2ae0e5a69 100644 --- a/test_regress/t/t_dpi_qw.v +++ b/test_regress/t/t_dpi_qw.v @@ -8,35 +8,37 @@ module t; - wire [39:0] out; - sub a(.value(out)); + wire [39:0] out; + sub a (.value(out)); - import "DPI-C" context function void poke_value(input int i); + import "DPI-C" context function void poke_value(input int i); - initial begin - poke_value(32'hdeadbeef); - if (out !== 40'hdeadbeef) begin - $display("[%0t] %%Error: t_dpi_qw: failed", $time); - $stop; - end + initial begin + poke_value(32'hdeadbeef); + if (out !== 40'hdeadbeef) begin + $display("[%0t] %%Error: t_dpi_qw: failed", $time); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub(value); - parameter WIDTH = 40; +module sub ( + value +); + parameter WIDTH = 40; - output [WIDTH-1:0] value; + output [WIDTH-1:0] value; - reg [WIDTH-1:0] value; + reg [WIDTH-1:0] value; - task set_value(input bit [WIDTH-1:0] v); - value = v; - endtask + task set_value(input bit [WIDTH-1:0] v); + value = v; + endtask - export "DPI-C" task set_value; + export "DPI-C" task set_value; endmodule diff --git a/test_regress/t/t_dpi_result_type.v b/test_regress/t/t_dpi_result_type.v index 2b4ce783d..b41d47fe2 100644 --- a/test_regress/t/t_dpi_result_type.v +++ b/test_regress/t/t_dpi_result_type.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_REAL_EXPORT `endif @@ -27,494 +28,492 @@ `define NULL null `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk + ); `ifdef VERILATOR - wire _unused = &{1'b0, clk}; + wire _unused = &{1'b0, clk}; `endif - // Legal result types for DPI functions + // Legal result types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.5 - typedef byte byte_t; - typedef byte unsigned byte_unsigned_t; - typedef shortint shortint_t; - typedef shortint unsigned shortint_unsigned_t; - typedef int int_t; - typedef int unsigned int_unsigned_t; - typedef longint longint_t; - typedef longint unsigned longint_unsigned_t; - typedef real real_t; + // Basic types as per IEEE 1800-2023 35.5.5 + typedef byte byte_t; + typedef byte unsigned byte_unsigned_t; + typedef shortint shortint_t; + typedef shortint unsigned shortint_unsigned_t; + typedef int int_t; + typedef int unsigned int_unsigned_t; + typedef longint longint_t; + typedef longint unsigned longint_unsigned_t; + typedef real real_t; `ifndef NO_SHORTREAL - typedef shortreal shortreal_t; + typedef shortreal shortreal_t; `endif - typedef chandle chandle_t; - typedef string string_t; - typedef bit bit_t; - typedef logic logic_t; + typedef chandle chandle_t; + typedef string string_t; + typedef bit bit_t; + typedef logic logic_t; - // 2-state packed structures of width <= 32 - typedef struct packed { bit x; } struct_2_state_1; - typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; + // 2-state packed structures of width <= 32 + typedef struct packed { bit x; } struct_2_state_1; + typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; - // 2-state packed unions of width <= 32 - typedef union packed { bit x; bit y; } union_2_state_1; - typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; + // 2-state packed unions of width <= 32 + typedef union packed { bit x; bit y; } union_2_state_1; + typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.5 - import "DPI-C" function void i_void (); - import "DPI-C" function byte i_byte (); - import "DPI-C" function byte unsigned i_byte_unsigned (); - import "DPI-C" function shortint i_shortint (); - import "DPI-C" function shortint unsigned i_shortint_unsigned (); - import "DPI-C" function int i_int (); - import "DPI-C" function int unsigned i_int_unsigned (); - import "DPI-C" function longint i_longint (); - import "DPI-C" function longint unsigned i_longint_unsigned (); - import "DPI-C" function real i_real (); + // Basic types as per IEEE 1800-2023 35.5.5 + import "DPI-C" function void i_void (); + import "DPI-C" function byte i_byte (); + import "DPI-C" function byte unsigned i_byte_unsigned (); + import "DPI-C" function shortint i_shortint (); + import "DPI-C" function shortint unsigned i_shortint_unsigned (); + import "DPI-C" function int i_int (); + import "DPI-C" function int unsigned i_int_unsigned (); + import "DPI-C" function longint i_longint (); + import "DPI-C" function longint unsigned i_longint_unsigned (); + import "DPI-C" function real i_real (); `ifndef NO_SHORTREAL - import "DPI-C" function shortreal i_shortreal (); + import "DPI-C" function shortreal i_shortreal (); `endif - import "DPI-C" function chandle i_chandle (); - import "DPI-C" function string i_string (); - import "DPI-C" function bit i_bit (); - import "DPI-C" function logic i_logic (); + import "DPI-C" function chandle i_chandle (); + import "DPI-C" function string i_string (); + import "DPI-C" function bit i_bit (); + import "DPI-C" function logic i_logic (); - // Basic types via typedef - import "DPI-C" function byte_t i_byte_t (); - import "DPI-C" function byte_unsigned_t i_byte_unsigned_t (); - import "DPI-C" function shortint_t i_shortint_t (); - import "DPI-C" function shortint_unsigned_t i_shortint_unsigned_t (); - import "DPI-C" function int_t i_int_t (); - import "DPI-C" function int_unsigned_t i_int_unsigned_t (); - import "DPI-C" function longint_t i_longint_t (); - import "DPI-C" function longint_unsigned_t i_longint_unsigned_t (); - import "DPI-C" function real_t i_real_t (); + // Basic types via typedef + import "DPI-C" function byte_t i_byte_t (); + import "DPI-C" function byte_unsigned_t i_byte_unsigned_t (); + import "DPI-C" function shortint_t i_shortint_t (); + import "DPI-C" function shortint_unsigned_t i_shortint_unsigned_t (); + import "DPI-C" function int_t i_int_t (); + import "DPI-C" function int_unsigned_t i_int_unsigned_t (); + import "DPI-C" function longint_t i_longint_t (); + import "DPI-C" function longint_unsigned_t i_longint_unsigned_t (); + import "DPI-C" function real_t i_real_t (); `ifndef NO_SHORTREAL - import "DPI-C" function shortreal_t i_shortreal_t (); + import "DPI-C" function shortreal_t i_shortreal_t (); `endif - import "DPI-C" function chandle_t i_chandle_t (); - import "DPI-C" function string_t i_string_t (); - import "DPI-C" function bit_t i_bit_t (); - import "DPI-C" function logic_t i_logic_t (); + import "DPI-C" function chandle_t i_chandle_t (); + import "DPI-C" function string_t i_string_t (); + import "DPI-C" function bit_t i_bit_t (); + import "DPI-C" function logic_t i_logic_t (); `ifndef NO_ARRAY - // 2-state packed arrays of width <= 32 - import "DPI-C" function bit [ 0:0] i_array_2_state_1 (); - import "DPI-C" function bit [31:0] i_array_2_state_32 (); + // 2-state packed arrays of width <= 32 + import "DPI-C" function bit [ 0:0] i_array_2_state_1 (); + import "DPI-C" function bit [31:0] i_array_2_state_32 (); `endif `ifndef NO_STRUCT_OR_UNION - // 2-state packed structures of width <= 32 - import "DPI-C" function struct_2_state_1 i_struct_2_state_1 (); - import "DPI-C" function struct_2_state_32 i_struct_2_state_32(); + // 2-state packed structures of width <= 32 + import "DPI-C" function struct_2_state_1 i_struct_2_state_1 (); + import "DPI-C" function struct_2_state_32 i_struct_2_state_32(); - // 2-state packed unions of width <= 32 - import "DPI-C" function union_2_state_1 i_union_2_state_1 (); - import "DPI-C" function union_2_state_32 i_union_2_state_32(); + // 2-state packed unions of width <= 32 + import "DPI-C" function union_2_state_1 i_union_2_state_1 (); + import "DPI-C" function union_2_state_32 i_union_2_state_32(); `endif - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - // Basic types as per IEEE 1800-2023 35.5.5 - export "DPI-C" function e_void; - export "DPI-C" function e_byte; - export "DPI-C" function e_byte_unsigned; - export "DPI-C" function e_shortint; - export "DPI-C" function e_shortint_unsigned; - export "DPI-C" function e_int; - export "DPI-C" function e_int_unsigned; - export "DPI-C" function e_longint; - export "DPI-C" function e_longint_unsigned; + // Basic types as per IEEE 1800-2023 35.5.5 + export "DPI-C" function e_void; + export "DPI-C" function e_byte; + export "DPI-C" function e_byte_unsigned; + export "DPI-C" function e_shortint; + export "DPI-C" function e_shortint_unsigned; + export "DPI-C" function e_int; + export "DPI-C" function e_int_unsigned; + export "DPI-C" function e_longint; + export "DPI-C" function e_longint_unsigned; `ifndef NO_REAL_EXPORT - export "DPI-C" function e_real; + export "DPI-C" function e_real; `endif `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal; + export "DPI-C" function e_shortreal; `endif - export "DPI-C" function e_chandle; - export "DPI-C" function e_string; - export "DPI-C" function e_bit; - export "DPI-C" function e_logic; + export "DPI-C" function e_chandle; + export "DPI-C" function e_string; + export "DPI-C" function e_bit; + export "DPI-C" function e_logic; - // Basic types via typedef - export "DPI-C" function e_byte_t; - export "DPI-C" function e_byte_unsigned_t; - export "DPI-C" function e_shortint_t; - export "DPI-C" function e_shortint_unsigned_t; - export "DPI-C" function e_int_t; - export "DPI-C" function e_int_unsigned_t; - export "DPI-C" function e_longint_t; - export "DPI-C" function e_longint_unsigned_t; + // Basic types via typedef + export "DPI-C" function e_byte_t; + export "DPI-C" function e_byte_unsigned_t; + export "DPI-C" function e_shortint_t; + export "DPI-C" function e_shortint_unsigned_t; + export "DPI-C" function e_int_t; + export "DPI-C" function e_int_unsigned_t; + export "DPI-C" function e_longint_t; + export "DPI-C" function e_longint_unsigned_t; `ifndef NO_REAL_EXPORT - export "DPI-C" function e_real_t; + export "DPI-C" function e_real_t; `endif `ifndef NO_SHORTREAL - export "DPI-C" function e_shortreal_t; + export "DPI-C" function e_shortreal_t; `endif - export "DPI-C" function e_chandle_t; - export "DPI-C" function e_string_t; - export "DPI-C" function e_bit_t; - export "DPI-C" function e_logic_t; + export "DPI-C" function e_chandle_t; + export "DPI-C" function e_string_t; + export "DPI-C" function e_bit_t; + export "DPI-C" function e_logic_t; `ifndef NO_ARRAY - // 2-state packed arrays of width <= 32 - export "DPI-C" function e_array_2_state_1; - export "DPI-C" function e_array_2_state_32; + // 2-state packed arrays of width <= 32 + export "DPI-C" function e_array_2_state_1; + export "DPI-C" function e_array_2_state_32; `endif `ifndef NO_STRUCT_OR_UNION - // 2-state packed structures of width <= 32 - export "DPI-C" function e_struct_2_state_1; - export "DPI-C" function e_struct_2_state_32; + // 2-state packed structures of width <= 32 + export "DPI-C" function e_struct_2_state_1; + export "DPI-C" function e_struct_2_state_32; - // 2-state packed unions of width <= 32 - export "DPI-C" function e_union_2_state_1; - export "DPI-C" function e_union_2_state_32; + // 2-state packed unions of width <= 32 + export "DPI-C" function e_union_2_state_1; + export "DPI-C" function e_union_2_state_32; `endif - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - // Static variables (Note: Verilator strangely assumes everything inside - // a function is automatic, which is exactly the opposite of the standard - // see IEEE 1800-2023 13.3.1 and 13.4.2 + // Static variables (Note: Verilator strangely assumes everything inside + // a function is automatic, which is exactly the opposite of the standard + // see IEEE 1800-2023 13.3.1 and 13.4.2 - // Basic types as per IEEE 1800-2023 35.5.5 - int n_void = 0; - function void e_void(); - $display("e_void %1d", n_void); - n_void++; - endfunction + // Basic types as per IEEE 1800-2023 35.5.5 + int n_void = 0; + function void e_void(); + $display("e_void %1d", n_void); + n_void++; + endfunction - byte n_byte = 0; - function byte e_byte(); - e_byte = 8'd10 + n_byte; - n_byte++; - endfunction + byte n_byte = 0; + function byte e_byte(); + e_byte = 8'd10 + n_byte; + n_byte++; + endfunction - byte n_byte_unsigned = 0; - function byte unsigned e_byte_unsigned(); - e_byte_unsigned = 8'd20 + n_byte_unsigned; - n_byte_unsigned++; - endfunction + byte n_byte_unsigned = 0; + function byte unsigned e_byte_unsigned(); + e_byte_unsigned = 8'd20 + n_byte_unsigned; + n_byte_unsigned++; + endfunction - shortint n_shortint = 0; - function shortint e_shortint(); - e_shortint = 16'd30 + n_shortint; - n_shortint++; - endfunction + shortint n_shortint = 0; + function shortint e_shortint(); + e_shortint = 16'd30 + n_shortint; + n_shortint++; + endfunction - shortint n_shortint_unsigned = 0; - function shortint unsigned e_shortint_unsigned(); - e_shortint_unsigned = 16'd40 + n_shortint_unsigned; - n_shortint_unsigned++; - endfunction + shortint n_shortint_unsigned = 0; + function shortint unsigned e_shortint_unsigned(); + e_shortint_unsigned = 16'd40 + n_shortint_unsigned; + n_shortint_unsigned++; + endfunction - int n_int = 0; - function int e_int(); - e_int = 32'd50 + n_int; - n_int++; - endfunction + int n_int = 0; + function int e_int(); + e_int = 32'd50 + n_int; + n_int++; + endfunction - int n_int_unsigned = 0; - function int unsigned e_int_unsigned(); - e_int_unsigned = 32'd60 + n_int_unsigned; - n_int_unsigned++; - endfunction + int n_int_unsigned = 0; + function int unsigned e_int_unsigned(); + e_int_unsigned = 32'd60 + n_int_unsigned; + n_int_unsigned++; + endfunction - longint n_longint = 0; - function longint e_longint(); - e_longint = 64'd70 + n_longint; - n_longint++; - endfunction + longint n_longint = 0; + function longint e_longint(); + e_longint = 64'd70 + n_longint; + n_longint++; + endfunction - longint n_longint_unsigned = 0; - function longint unsigned e_longint_unsigned(); - e_longint_unsigned = 64'd80 + n_longint_unsigned; - n_longint_unsigned++; - endfunction + longint n_longint_unsigned = 0; + function longint unsigned e_longint_unsigned(); + e_longint_unsigned = 64'd80 + n_longint_unsigned; + n_longint_unsigned++; + endfunction `ifndef NO_REAL_EXPORT - int n_real = 0; - function real e_real(); - e_real = real'(2*n_real + 1) / 2.0; - n_real++; - endfunction + int n_real = 0; + function real e_real(); + e_real = real'(2*n_real + 1) / 2.0; + n_real++; + endfunction `endif `ifndef NO_SHORTREAL - int n_shortreal = 0; - function shortreal e_shortreal(); - e_shortreal = shortreal'(4*n_shortreal + 1)/ 4.0; - n_shortreal++; - endfunction + int n_shortreal = 0; + function shortreal e_shortreal(); + e_shortreal = shortreal'(4*n_shortreal + 1)/ 4.0; + n_shortreal++; + endfunction `endif - int n_chandle = 0; - function chandle e_chandle(); - $display("e_chandle %1d", n_chandle); - e_chandle = `NULL; - n_chandle++; - endfunction + int n_chandle = 0; + function chandle e_chandle(); + $display("e_chandle %1d", n_chandle); + e_chandle = `NULL; + n_chandle++; + endfunction - int n_string = 0; - function string e_string(); - $display("e_string %1d", n_string); - e_string = n_string[0] ? "World" : "Hello"; - n_string++; - endfunction + int n_string = 0; + function string e_string(); + $display("e_string %1d", n_string); + e_string = n_string[0] ? "World" : "Hello"; + n_string++; + endfunction - int n_bit = 0; - function bit e_bit(); - $display("e_bit %1d", n_bit); - e_bit = n_bit[0]; - n_bit++; - endfunction + int n_bit = 0; + function bit e_bit(); + $display("e_bit %1d", n_bit); + e_bit = n_bit[0]; + n_bit++; + endfunction - int n_logic = 0; - function logic e_logic(); - $display("e_logic %1d", n_logic); - e_logic = ~n_logic[0]; - n_logic++; - endfunction + int n_logic = 0; + function logic e_logic(); + $display("e_logic %1d", n_logic); + e_logic = ~n_logic[0]; + n_logic++; + endfunction - // Basic types via typedefs - byte_t n_byte_t = 0; - function byte_t e_byte_t(); - e_byte_t = 8'd10 + n_byte_t; - n_byte_t += 2; - endfunction + // Basic types via typedefs + byte_t n_byte_t = 0; + function byte_t e_byte_t(); + e_byte_t = 8'd10 + n_byte_t; + n_byte_t += 2; + endfunction - byte n_byte_unsigned_t = 0; - function byte_unsigned_t e_byte_unsigned_t(); - e_byte_unsigned_t = 8'd20 + n_byte_unsigned_t; - n_byte_unsigned_t += 2; - endfunction + byte n_byte_unsigned_t = 0; + function byte_unsigned_t e_byte_unsigned_t(); + e_byte_unsigned_t = 8'd20 + n_byte_unsigned_t; + n_byte_unsigned_t += 2; + endfunction - shortint_t n_shortint_t = 0; - function shortint_t e_shortint_t(); - e_shortint_t = 16'd30 + n_shortint_t; - n_shortint_t += 2; - endfunction + shortint_t n_shortint_t = 0; + function shortint_t e_shortint_t(); + e_shortint_t = 16'd30 + n_shortint_t; + n_shortint_t += 2; + endfunction - shortint n_shortint_unsigned_t = 0; - function shortint_unsigned_t e_shortint_unsigned_t(); - e_shortint_unsigned_t = 16'd40 + n_shortint_unsigned_t; - n_shortint_unsigned_t += 2; - endfunction + shortint n_shortint_unsigned_t = 0; + function shortint_unsigned_t e_shortint_unsigned_t(); + e_shortint_unsigned_t = 16'd40 + n_shortint_unsigned_t; + n_shortint_unsigned_t += 2; + endfunction - int_t n_int_t = 0; - function int_t e_int_t(); - e_int_t = 32'd50 + n_int_t; - n_int_t += 2; - endfunction + int_t n_int_t = 0; + function int_t e_int_t(); + e_int_t = 32'd50 + n_int_t; + n_int_t += 2; + endfunction - int n_int_unsigned_t = 0; - function int_unsigned_t e_int_unsigned_t(); - e_int_unsigned_t = 32'd60 + n_int_unsigned_t; - n_int_unsigned_t += 2; - endfunction + int n_int_unsigned_t = 0; + function int_unsigned_t e_int_unsigned_t(); + e_int_unsigned_t = 32'd60 + n_int_unsigned_t; + n_int_unsigned_t += 2; + endfunction - longint_t n_longint_t = 0; - function longint_t e_longint_t(); - e_longint_t = 64'd70 + n_longint_t; - n_longint_t += 2; - endfunction + longint_t n_longint_t = 0; + function longint_t e_longint_t(); + e_longint_t = 64'd70 + n_longint_t; + n_longint_t += 2; + endfunction - longint n_longint_unsigned_t = 0; - function longint_unsigned_t e_longint_unsigned_t(); - e_longint_unsigned_t = 64'd80 + n_longint_unsigned_t; - n_longint_unsigned_t += 2; - endfunction + longint n_longint_unsigned_t = 0; + function longint_unsigned_t e_longint_unsigned_t(); + e_longint_unsigned_t = 64'd80 + n_longint_unsigned_t; + n_longint_unsigned_t += 2; + endfunction `ifndef NO_REAL_EXPORT - int n_real_t = 0; - function real_t e_real_t(); - e_real_t = real'(2*n_real_t + 1) / 2.0; - n_real_t += 2; - endfunction + int n_real_t = 0; + function real_t e_real_t(); + e_real_t = real'(2*n_real_t + 1) / 2.0; + n_real_t += 2; + endfunction `endif `ifndef NO_SHORTREAL - int n_shortreal_t = 0; - function shortreal_t e_shortreal_t(); - e_shortreal_t = shortreal'(4*n_shortreal_t + 1)/ 4.0; - n_shortreal_t += 2; - endfunction + int n_shortreal_t = 0; + function shortreal_t e_shortreal_t(); + e_shortreal_t = shortreal'(4*n_shortreal_t + 1)/ 4.0; + n_shortreal_t += 2; + endfunction `endif - int n_chandle_t = 0; - function chandle_t e_chandle_t(); - $display("e_chandle_t %1d", n_chandle_t); - e_chandle_t = `NULL; - n_chandle_t++; - endfunction + int n_chandle_t = 0; + function chandle_t e_chandle_t(); + $display("e_chandle_t %1d", n_chandle_t); + e_chandle_t = `NULL; + n_chandle_t++; + endfunction - int n_string_t = 0; - function string_t e_string_t(); - $display("e_string_t %1d", n_string_t); - e_string_t = n_string_t[0] ? "World" : "Hello"; - n_string_t++; - endfunction + int n_string_t = 0; + function string_t e_string_t(); + $display("e_string_t %1d", n_string_t); + e_string_t = n_string_t[0] ? "World" : "Hello"; + n_string_t++; + endfunction - int n_bit_t = 0; - function bit_t e_bit_t(); - $display("e_bit_t %1d", n_bit_t); - e_bit_t = n_bit_t[0]; - n_bit_t++; - endfunction + int n_bit_t = 0; + function bit_t e_bit_t(); + $display("e_bit_t %1d", n_bit_t); + e_bit_t = n_bit_t[0]; + n_bit_t++; + endfunction - int n_logic_t = 0; - function logic_t e_logic_t(); - $display("e_logic_t %1d", n_logic_t); - e_logic_t = ~n_logic_t[0]; - n_logic_t++; - endfunction + int n_logic_t = 0; + function logic_t e_logic_t(); + $display("e_logic_t %1d", n_logic_t); + e_logic_t = ~n_logic_t[0]; + n_logic_t++; + endfunction `ifndef NO_ARRAY - // 2-state packed arrays of width <= 32 - int n_array_2_state_1 = 0; - function bit [ 0:0] e_array_2_state_1(); - $display("e_array_2_state_1 %1d", n_array_2_state_1); - e_array_2_state_1 = n_array_2_state_1[0]; - n_array_2_state_1++; - endfunction + // 2-state packed arrays of width <= 32 + int n_array_2_state_1 = 0; + function bit [ 0:0] e_array_2_state_1(); + $display("e_array_2_state_1 %1d", n_array_2_state_1); + e_array_2_state_1 = n_array_2_state_1[0]; + n_array_2_state_1++; + endfunction - int n_array_2_state_32 = 0; - function bit [31:0] e_array_2_state_32(); - $display("e_array_2_state_32 %1d", n_array_2_state_32); - e_array_2_state_32 = ~32'd0 >> n_array_2_state_32; - n_array_2_state_32++; - endfunction + int n_array_2_state_32 = 0; + function bit [31:0] e_array_2_state_32(); + $display("e_array_2_state_32 %1d", n_array_2_state_32); + e_array_2_state_32 = ~32'd0 >> n_array_2_state_32; + n_array_2_state_32++; + endfunction `endif `ifndef NO_STRUCT_OR_UNION - // 2-state packed structures of width <= 32 - int n_struct_2_state_1 = 0; - function struct_2_state_1 e_struct_2_state_1(); - $display("e_struct_2_state_1 %1d", n_struct_2_state_1); - e_struct_2_state_1 = n_struct_2_state_1[0]; - n_struct_2_state_1++; - endfunction + // 2-state packed structures of width <= 32 + int n_struct_2_state_1 = 0; + function struct_2_state_1 e_struct_2_state_1(); + $display("e_struct_2_state_1 %1d", n_struct_2_state_1); + e_struct_2_state_1 = n_struct_2_state_1[0]; + n_struct_2_state_1++; + endfunction - int n_struct_2_state_32 = 0; - function struct_2_state_32 e_struct_2_state_32(); - $display("e_struct_2_state_32 %1d", n_struct_2_state_32); - e_struct_2_state_32 = ~32'd0 >> n_struct_2_state_32; - n_struct_2_state_32++; - endfunction + int n_struct_2_state_32 = 0; + function struct_2_state_32 e_struct_2_state_32(); + $display("e_struct_2_state_32 %1d", n_struct_2_state_32); + e_struct_2_state_32 = ~32'd0 >> n_struct_2_state_32; + n_struct_2_state_32++; + endfunction - // 2-state packed unions of width <= 32 - int n_union_2_state_1 = 0; - function union_2_state_1 e_union_2_state_1(); - $display("e_union_2_state_1 %1d", n_union_2_state_1); - e_union_2_state_1 = n_union_2_state_1[0]; - n_union_2_state_1++; - endfunction + // 2-state packed unions of width <= 32 + int n_union_2_state_1 = 0; + function union_2_state_1 e_union_2_state_1(); + $display("e_union_2_state_1 %1d", n_union_2_state_1); + e_union_2_state_1 = n_union_2_state_1[0]; + n_union_2_state_1++; + endfunction - int n_union_2_state_32 = 0; - function union_2_state_32 e_union_2_state_32(); - $display("e_union_2_state_32 %1d", n_union_2_state_32); - e_union_2_state_32 = ~32'd0 >> n_union_2_state_32; - n_union_2_state_32++; - endfunction + int n_union_2_state_32 = 0; + function union_2_state_32 e_union_2_state_32(); + $display("e_union_2_state_32 %1d", n_union_2_state_32); + e_union_2_state_32 = ~32'd0 >> n_union_2_state_32; + n_union_2_state_32++; + endfunction `endif - //====================================================================== - // Invoke all functions 3 times (they have side effects) - //====================================================================== + //====================================================================== + // Invoke all functions 3 times (they have side effects) + //====================================================================== - import "DPI-C" context function void check_exports(); + import "DPI-C" context function void check_exports(); - initial begin - for (int i = 0 ; i < 3; i++) begin - // Check the imports + initial begin + for (int i = 0 ; i < 3; i++) begin + // Check the imports - // Basic types as per IEEE 1800-2023 35.5.5 - i_void(); - if (i_byte() !== 8'd10 - 8'(i)) $stop; - if (i_byte_unsigned() !== 8'd20 - 8'(i)) $stop; - if (i_shortint() !== 16'd30 - 16'(i)) $stop; - if (i_shortint_unsigned() !== 16'd40 - 16'(i)) $stop; - if (i_int() !== 32'd50 - 32'(i)) $stop; - if (i_int_unsigned() !== 32'd60 - 32'(i)) $stop; - if (i_longint() !== 64'd70 - 64'(i)) $stop; - if (i_longint_unsigned() !== 64'd80 - 64'(i)) $stop; - if (i_real() != -1.0*i - 0.5 ) $stop; + // Basic types as per IEEE 1800-2023 35.5.5 + i_void(); + if (i_byte() !== 8'd10 - 8'(i)) $stop; + if (i_byte_unsigned() !== 8'd20 - 8'(i)) $stop; + if (i_shortint() !== 16'd30 - 16'(i)) $stop; + if (i_shortint_unsigned() !== 16'd40 - 16'(i)) $stop; + if (i_int() !== 32'd50 - 32'(i)) $stop; + if (i_int_unsigned() !== 32'd60 - 32'(i)) $stop; + if (i_longint() !== 64'd70 - 64'(i)) $stop; + if (i_longint_unsigned() !== 64'd80 - 64'(i)) $stop; + if (i_real() != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL - if (i_shortreal() != -1.0*i - 0.25) $stop; + if (i_shortreal() != -1.0*i - 0.25) $stop; `endif - if (~i[0]) begin - if (i_chandle() !== `NULL) $stop; - if (i_string() != "World") $stop; - end else begin - if (i_chandle() === `NULL) $stop; - if (i_string() != "Hello") $stop; - end - if (i_bit() !== ~i[0]) $stop; - if (i_logic() !== i[0]) $stop; - - // Basic types via typedefs - if (i_byte_t() !== 8'd10 - 8'(2*i)) $stop; - if (i_byte_unsigned_t() !== 8'd20 - 8'(2*i)) $stop; - if (i_shortint_t() !== 16'd30 - 16'(2*i)) $stop; - if (i_shortint_unsigned_t() !== 16'd40 - 16'(2*i)) $stop; - if (i_int_t() !== 32'd50 - 32'(2*i)) $stop; - if (i_int_unsigned_t() !== 32'd60 - 32'(2*i)) $stop; - if (i_longint_t() !== 64'd70 - 64'(2*i)) $stop; - if (i_longint_unsigned_t() !== 64'd80 - 64'(2*i)) $stop; - if (i_real_t() != -1.0*(2*i) - 0.5 ) $stop; -`ifndef NO_SHORTREAL - if (i_shortreal_t() != -1.0*(2*i) - 0.25) $stop; -`endif - if (~i[0]) begin - if (i_chandle_t() !== `NULL) $stop; - if (i_string_t() != "World") $stop; - end else begin - if (i_chandle_t() === `NULL) $stop; - if (i_string_t() != "Hello") $stop; - end - if (i_bit_t() !== ~i[0]) $stop; - if (i_logic_t() !== i[0]) $stop; - -`ifndef NO_ARRAY - // 2-state packed arrays of width <= 32 - if (i_array_2_state_1() !== ~i[0] ) $stop; - if (i_array_2_state_32() !== ~32'd0 << i) $stop; -`endif - -`ifndef NO_STRUCT_OR_UNION - // 2-state packed structures of width <= 32 - if (i_struct_2_state_1() !== ~i[0] ) $stop; - if (i_struct_2_state_32() !== ~32'd0 << i) $stop; - - // 2-state packed unions of width <= 32 - if (i_union_2_state_1() !== ~i[0] ) $stop; - if (i_union_2_state_32() !== ~32'd0 << i) $stop; -`endif - - // Check the exports - check_exports(); + if (~i[0]) begin + if (i_chandle() !== `NULL) $stop; + if (i_string() != "World") $stop; + end else begin + if (i_chandle() === `NULL) $stop; + if (i_string() != "Hello") $stop; end + if (i_bit() !== ~i[0]) $stop; + if (i_logic() !== i[0]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + // Basic types via typedefs + if (i_byte_t() !== 8'd10 - 8'(2*i)) $stop; + if (i_byte_unsigned_t() !== 8'd20 - 8'(2*i)) $stop; + if (i_shortint_t() !== 16'd30 - 16'(2*i)) $stop; + if (i_shortint_unsigned_t() !== 16'd40 - 16'(2*i)) $stop; + if (i_int_t() !== 32'd50 - 32'(2*i)) $stop; + if (i_int_unsigned_t() !== 32'd60 - 32'(2*i)) $stop; + if (i_longint_t() !== 64'd70 - 64'(2*i)) $stop; + if (i_longint_unsigned_t() !== 64'd80 - 64'(2*i)) $stop; + if (i_real_t() != -1.0*(2*i) - 0.5 ) $stop; +`ifndef NO_SHORTREAL + if (i_shortreal_t() != -1.0*(2*i) - 0.25) $stop; +`endif + if (~i[0]) begin + if (i_chandle_t() !== `NULL) $stop; + if (i_string_t() != "World") $stop; + end else begin + if (i_chandle_t() === `NULL) $stop; + if (i_string_t() != "Hello") $stop; + end + if (i_bit_t() !== ~i[0]) $stop; + if (i_logic_t() !== i[0]) $stop; + +`ifndef NO_ARRAY + // 2-state packed arrays of width <= 32 + if (i_array_2_state_1() !== ~i[0] ) $stop; + if (i_array_2_state_32() !== ~32'd0 << i) $stop; +`endif + +`ifndef NO_STRUCT_OR_UNION + // 2-state packed structures of width <= 32 + if (i_struct_2_state_1() !== ~i[0] ) $stop; + if (i_struct_2_state_32() !== ~32'd0 << i) $stop; + + // 2-state packed unions of width <= 32 + if (i_union_2_state_1() !== ~i[0] ) $stop; + if (i_union_2_state_32() !== ~32'd0 << i) $stop; +`endif + + // Check the exports + check_exports(); + end + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_result_type_bad.out b/test_regress/t/t_dpi_result_type_bad.out index 5c1d8e279..67c1b0158 100644 --- a/test_regress/t/t_dpi_result_type_bad.out +++ b/test_regress/t/t_dpi_result_type_bad.out @@ -1,400 +1,400 @@ -%Error: t/t_dpi_result_type_bad.v:79:40: DPI function may not return a > 32 bits wide type other than basic types. +%Error: t/t_dpi_result_type_bad.v:80:39: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 79 | import "DPI-C" function bit [ 32:0] i_array_2_state_33(); - | ^~~~~~~~~~~~~~~~~~ + 80 | import "DPI-C" function bit [ 32:0] i_array_2_state_33(); + | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_dpi_result_type_bad.v:80:40: DPI function may not return a > 32 bits wide type other than basic types. +%Error: t/t_dpi_result_type_bad.v:81:39: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 80 | import "DPI-C" function bit [ 63:0] i_array_2_state_64(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:81:40: DPI function may not return a > 32 bits wide type other than basic types. + 81 | import "DPI-C" function bit [ 63:0] i_array_2_state_64(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:82:39: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 81 | import "DPI-C" function bit [ 64:0] i_array_2_state_65(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:82:40: DPI function may not return a > 32 bits wide type other than basic types. + 82 | import "DPI-C" function bit [ 64:0] i_array_2_state_65(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:83:39: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 82 | import "DPI-C" function bit [127:0] i_array_2_state_128(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:85:48: DPI function may not return a > 32 bits wide type other than basic types. + 83 | import "DPI-C" function bit [127:0] i_array_2_state_128(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:86:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 85 | import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:86:48: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 86 | import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:87:48: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 87 | import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:88:48: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 88 | import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:91:47: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 91 | import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:92:47: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 92 | import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:93:47: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 93 | import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:94:47: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 94 | import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); + 86 | import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:97:46: DPI function may not return a > 32 bits wide type other than basic types. +%Error: t/t_dpi_result_type_bad.v:87:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 97 | import "DPI-C" function union_2_state_33 i_union_2_state_33(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:98:46: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 98 | import "DPI-C" function union_2_state_64 i_union_2_state_64(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:99:46: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 99 | import "DPI-C" function union_2_state_65 i_union_2_state_65(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:100:46: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 100 | import "DPI-C" function union_2_state_128 i_union_2_state_128(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:103:36: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 103 | import "DPI-C" function integer i_integer(); - | ^~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:106:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 106 | import "DPI-C" function logic [ 0:0] i_array_4_state_1(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:107:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 107 | import "DPI-C" function logic [ 1:0] i_array_4_state_2(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:108:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 108 | import "DPI-C" function logic [ 7:0] i_array_4_state_8(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:109:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 109 | import "DPI-C" function logic [ 8:0] i_array_4_state_9(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:110:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 110 | import "DPI-C" function logic [ 15:0] i_array_4_state_16(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:111:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 111 | import "DPI-C" function logic [ 16:0] i_array_4_state_17(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:112:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 112 | import "DPI-C" function logic [ 31:0] i_array_4_state_32(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:113:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 113 | import "DPI-C" function logic [ 32:0] i_array_4_state_33(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:114:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 114 | import "DPI-C" function logic [ 63:0] i_array_4_state_64(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:115:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 115 | import "DPI-C" function logic [ 64:0] i_array_4_state_65(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:116:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 116 | import "DPI-C" function logic [127:0] i_array_4_state_128(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:119:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 119 | import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:120:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 120 | import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:121:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 121 | import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:122:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 122 | import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:123:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 123 | import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:124:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 124 | import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:125:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 125 | import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:126:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 126 | import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:127:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 127 | import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:128:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 128 | import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:129:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 129 | import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:132:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 132 | import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:133:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 133 | import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:134:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 134 | import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:135:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 135 | import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:136:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 136 | import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:137:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 137 | import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:138:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 138 | import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:139:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 139 | import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:140:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 140 | import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:141:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 141 | import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:142:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 142 | import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); + 87 | import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:145:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 145 | import "DPI-C" function union_4_state_1 i_union_4_state_1(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:146:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 146 | import "DPI-C" function union_4_state_2 i_union_4_state_2(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:147:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 147 | import "DPI-C" function union_4_state_8 i_union_4_state_8(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:148:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 148 | import "DPI-C" function union_4_state_9 i_union_4_state_9(); - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:149:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 149 | import "DPI-C" function union_4_state_16 i_union_4_state_16(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:150:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 150 | import "DPI-C" function union_4_state_17 i_union_4_state_17(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:151:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 151 | import "DPI-C" function union_4_state_32 i_union_4_state_32(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:152:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 152 | import "DPI-C" function union_4_state_33 i_union_4_state_33(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:153:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 153 | import "DPI-C" function union_4_state_64 i_union_4_state_64(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:154:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 154 | import "DPI-C" function union_4_state_65 i_union_4_state_65(); - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:155:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 155 | import "DPI-C" function union_4_state_128 i_union_4_state_128(); +%Error: t/t_dpi_result_type_bad.v:88:47: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 88 | import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:89:47: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 89 | import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:92:46: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 92 | import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:245:25: DPI function may not return a > 32 bits wide type other than basic types. +%Error: t/t_dpi_result_type_bad.v:93:46: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 93 | import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:94:46: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 94 | import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:95:46: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 95 | import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:98:45: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 98 | import "DPI-C" function union_2_state_33 i_union_2_state_33(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:99:45: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 99 | import "DPI-C" function union_2_state_64 i_union_2_state_64(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:100:45: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 245 | function bit [ 32:0] e_array_2_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:246:25: DPI function may not return a > 32 bits wide type other than basic types. + 100 | import "DPI-C" function union_2_state_65 i_union_2_state_65(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:101:45: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 246 | function bit [ 63:0] e_array_2_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:247:25: DPI function may not return a > 32 bits wide type other than basic types. + 101 | import "DPI-C" function union_2_state_128 i_union_2_state_128(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:104:35: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 104 | import "DPI-C" function integer i_integer(); + | ^~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:107:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 107 | import "DPI-C" function logic [ 0:0] i_array_4_state_1(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:108:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 108 | import "DPI-C" function logic [ 1:0] i_array_4_state_2(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:109:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 109 | import "DPI-C" function logic [ 7:0] i_array_4_state_8(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:110:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 110 | import "DPI-C" function logic [ 8:0] i_array_4_state_9(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:111:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 111 | import "DPI-C" function logic [ 15:0] i_array_4_state_16(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:112:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 112 | import "DPI-C" function logic [ 16:0] i_array_4_state_17(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:113:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 113 | import "DPI-C" function logic [ 31:0] i_array_4_state_32(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:114:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 114 | import "DPI-C" function logic [ 32:0] i_array_4_state_33(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:115:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 115 | import "DPI-C" function logic [ 63:0] i_array_4_state_64(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:116:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 116 | import "DPI-C" function logic [ 64:0] i_array_4_state_65(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:117:41: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 117 | import "DPI-C" function logic [127:0] i_array_4_state_128(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:120:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 120 | import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:121:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 121 | import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:122:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 122 | import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:123:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 123 | import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:124:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 124 | import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:125:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 125 | import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:126:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 126 | import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:127:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 127 | import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:128:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 128 | import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:129:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 129 | import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:130:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 130 | import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:133:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 133 | import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:134:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 134 | import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:135:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 135 | import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:136:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 136 | import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:137:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 137 | import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:138:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 138 | import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:139:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 139 | import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:140:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 140 | import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:141:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 141 | import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:142:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 142 | import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:143:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 143 | import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:146:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 146 | import "DPI-C" function union_4_state_1 i_union_4_state_1(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:147:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 147 | import "DPI-C" function union_4_state_2 i_union_4_state_2(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:148:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 148 | import "DPI-C" function union_4_state_8 i_union_4_state_8(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:149:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 149 | import "DPI-C" function union_4_state_9 i_union_4_state_9(); + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:150:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 150 | import "DPI-C" function union_4_state_16 i_union_4_state_16(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:151:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 151 | import "DPI-C" function union_4_state_17 i_union_4_state_17(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:152:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 152 | import "DPI-C" function union_4_state_32 i_union_4_state_32(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:153:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 153 | import "DPI-C" function union_4_state_33 i_union_4_state_33(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:154:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 154 | import "DPI-C" function union_4_state_64 i_union_4_state_64(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:155:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 155 | import "DPI-C" function union_4_state_65 i_union_4_state_65(); + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:156:45: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 156 | import "DPI-C" function union_4_state_128 i_union_4_state_128(); + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:246:24: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 247 | function bit [ 64:0] e_array_2_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:248:25: DPI function may not return a > 32 bits wide type other than basic types. + 246 | function bit [ 32:0] e_array_2_state_33(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:247:24: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 248 | function bit [127:0] e_array_2_state_128(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:251:33: DPI function may not return a > 32 bits wide type other than basic types. + 247 | function bit [ 63:0] e_array_2_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:248:24: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 251 | function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:252:33: DPI function may not return a > 32 bits wide type other than basic types. + 248 | function bit [ 64:0] e_array_2_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:249:24: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 252 | function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:253:33: DPI function may not return a > 32 bits wide type other than basic types. + 249 | function bit [127:0] e_array_2_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:252:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 253 | function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:254:33: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 254 | function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:257:32: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 257 | function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:258:32: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 258 | function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:259:32: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 259 | function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:260:32: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 260 | function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction + 252 | function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:263:31: DPI function may not return a > 32 bits wide type other than basic types. +%Error: t/t_dpi_result_type_bad.v:253:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? - 263 | function union_2_state_33 e_union_2_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:264:31: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 264 | function union_2_state_64 e_union_2_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:265:31: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 265 | function union_2_state_65 e_union_2_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:266:31: DPI function may not return a > 32 bits wide type other than basic types. - : ... Suggest make it an output argument instead? - 266 | function union_2_state_128 e_union_2_state_128(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:269:21: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 269 | function integer e_integer(); return 0; endfunction - | ^~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:272:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 272 | function logic [ 0:0] e_array_4_state_1(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:273:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 273 | function logic [ 1:0] e_array_4_state_2(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:274:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 274 | function logic [ 7:0] e_array_4_state_8(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:275:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 275 | function logic [ 8:0] e_array_4_state_9(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:276:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 276 | function logic [ 15:0] e_array_4_state_16(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:277:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 277 | function logic [ 16:0] e_array_4_state_17(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:278:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 278 | function logic [ 31:0] e_array_4_state_32(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:279:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 279 | function logic [ 32:0] e_array_4_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:280:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 280 | function logic [ 63:0] e_array_4_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:281:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 281 | function logic [ 64:0] e_array_4_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:282:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 282 | function logic [127:0] e_array_4_state_128(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:285:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 285 | function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:286:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 286 | function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:287:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 287 | function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:288:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 288 | function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:289:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 289 | function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:290:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 290 | function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:291:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 291 | function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:292:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 292 | function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:293:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 293 | function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:294:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 294 | function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:295:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 295 | function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:298:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 298 | function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:299:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 299 | function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:300:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 300 | function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:301:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 301 | function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:302:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 302 | function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:303:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 303 | function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:304:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 304 | function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:305:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 305 | function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:306:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 306 | function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:307:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 307 | function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:308:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 308 | function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction + 253 | function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:311:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 311 | function union_4_state_1 e_union_4_state_1(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:312:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 312 | function union_4_state_2 e_union_4_state_2(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:313:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 313 | function union_4_state_8 e_union_4_state_8(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:314:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 314 | function union_4_state_9 e_union_4_state_9(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:315:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 315 | function union_4_state_16 e_union_4_state_16(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:316:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 316 | function union_4_state_17 e_union_4_state_17(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:317:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 317 | function union_4_state_32 e_union_4_state_32(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:318:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 318 | function union_4_state_33 e_union_4_state_33(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:319:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 319 | function union_4_state_64 e_union_4_state_64(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:320:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 320 | function union_4_state_65 e_union_4_state_65(); return 0; endfunction - | ^~~~~~~~~~~~~~~~~~ -%Error: t/t_dpi_result_type_bad.v:321:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) - 321 | function union_4_state_128 e_union_4_state_128(); return 0; endfunction +%Error: t/t_dpi_result_type_bad.v:254:32: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 254 | function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:255:32: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 255 | function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:258:31: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 258 | function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:259:31: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 259 | function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:260:31: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 260 | function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:261:31: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 261 | function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:264:30: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 264 | function union_2_state_33 e_union_2_state_33(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:265:30: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 265 | function union_2_state_64 e_union_2_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:266:30: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 266 | function union_2_state_65 e_union_2_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:267:30: DPI function may not return a > 32 bits wide type other than basic types. + : ... Suggest make it an output argument instead? + 267 | function union_2_state_128 e_union_2_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:270:20: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 270 | function integer e_integer(); return 0; endfunction + | ^~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:273:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 273 | function logic [ 0:0] e_array_4_state_1(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:274:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 274 | function logic [ 1:0] e_array_4_state_2(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:275:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 275 | function logic [ 7:0] e_array_4_state_8(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:276:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 276 | function logic [ 8:0] e_array_4_state_9(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:277:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 277 | function logic [ 15:0] e_array_4_state_16(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:278:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 278 | function logic [ 16:0] e_array_4_state_17(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:279:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 279 | function logic [ 31:0] e_array_4_state_32(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:280:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 280 | function logic [ 32:0] e_array_4_state_33(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:281:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 281 | function logic [ 63:0] e_array_4_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:282:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 282 | function logic [ 64:0] e_array_4_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:283:26: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 283 | function logic [127:0] e_array_4_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:286:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 286 | function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:287:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 287 | function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:288:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 288 | function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:289:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 289 | function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:290:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 290 | function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:291:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 291 | function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:292:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 292 | function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:293:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 293 | function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:294:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 294 | function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:295:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 295 | function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:296:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 296 | function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:299:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 299 | function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:300:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 300 | function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:301:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 301 | function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:302:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 302 | function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:303:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 303 | function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:304:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 304 | function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:305:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 305 | function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:306:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 306 | function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:307:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 307 | function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:308:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 308 | function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:309:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 309 | function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:312:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 312 | function union_4_state_1 e_union_4_state_1(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:313:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 313 | function union_4_state_2 e_union_4_state_2(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:314:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 314 | function union_4_state_8 e_union_4_state_8(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:315:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 315 | function union_4_state_9 e_union_4_state_9(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:316:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 316 | function union_4_state_16 e_union_4_state_16(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:317:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 317 | function union_4_state_17 e_union_4_state_17(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:318:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 318 | function union_4_state_32 e_union_4_state_32(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:319:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 319 | function union_4_state_33 e_union_4_state_33(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:320:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 320 | function union_4_state_64 e_union_4_state_64(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:321:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 321 | function union_4_state_65 e_union_4_state_65(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~ +%Error: t/t_dpi_result_type_bad.v:322:30: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) + 322 | function union_4_state_128 e_union_4_state_128(); return 0; endfunction + | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_result_type_bad.v b/test_regress/t/t_dpi_result_type_bad.v index 28107ed70..ffd67b7c5 100644 --- a/test_regress/t/t_dpi_result_type_bad.v +++ b/test_regress/t/t_dpi_result_type_bad.v @@ -6,317 +6,318 @@ // SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off module t_dpi_result_type_bad; - // Illegal result types for DPI functions + // Illegal result types for DPI functions - //====================================================================== - // Type definitions - //====================================================================== + //====================================================================== + // Type definitions + //====================================================================== - // 2-state packed arrays of width > 32 - typedef bit [ 32:0] array_2_state_33_t; - typedef bit [ 63:0] array_2_state_64_t; - typedef bit [ 64:0] array_2_state_65_t; - typedef bit [127:0] array_2_state_128_t; + // 2-state packed arrays of width > 32 + typedef bit [ 32:0] array_2_state_33_t; + typedef bit [ 63:0] array_2_state_64_t; + typedef bit [ 64:0] array_2_state_65_t; + typedef bit [127:0] array_2_state_128_t; - // 2-state packed structures of width > 32 - typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; - typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; - typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; - typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; + // 2-state packed structures of width > 32 + typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; + typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; + typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; + typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; - // 2-state packed unions of width > 32 - typedef union packed { bit [ 32:0] x; bit [ 32:0] y; } union_2_state_33; - typedef union packed { bit [ 63:0] x; bit [ 63:0] y; } union_2_state_64; - typedef union packed { bit [ 64:0] x; bit [ 64:0] y; } union_2_state_65; - typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; + // 2-state packed unions of width > 32 + typedef union packed { bit [ 32:0] x; bit [ 32:0] y; } union_2_state_33; + typedef union packed { bit [ 63:0] x; bit [ 63:0] y; } union_2_state_64; + typedef union packed { bit [ 64:0] x; bit [ 64:0] y; } union_2_state_65; + typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; - // 4-state packed arrays of any size - typedef logic [ 0:0] array_4_state_1_t; - typedef logic [ 1:0] array_4_state_2_t; - typedef logic [ 7:0] array_4_state_8_t; - typedef logic [ 8:0] array_4_state_9_t; - typedef logic [ 15:0] array_4_state_16_t; - typedef logic [ 16:0] array_4_state_17_t; - typedef logic [ 31:0] array_4_state_32_t; - typedef logic [ 32:0] array_4_state_33_t; - typedef logic [ 63:0] array_4_state_64_t; - typedef logic [ 64:0] array_4_state_65_t; - typedef logic [127:0] array_4_state_128_t; + // 4-state packed arrays of any size + typedef logic [ 0:0] array_4_state_1_t; + typedef logic [ 1:0] array_4_state_2_t; + typedef logic [ 7:0] array_4_state_8_t; + typedef logic [ 8:0] array_4_state_9_t; + typedef logic [ 15:0] array_4_state_16_t; + typedef logic [ 16:0] array_4_state_17_t; + typedef logic [ 31:0] array_4_state_32_t; + typedef logic [ 32:0] array_4_state_33_t; + typedef logic [ 63:0] array_4_state_64_t; + typedef logic [ 64:0] array_4_state_65_t; + typedef logic [127:0] array_4_state_128_t; - // 4-state packed structures of any size - typedef struct packed { logic [ 0:0] x; } struct_4_state_1; - typedef struct packed { logic [ 0:0] x; bit [ 0:0] y; } struct_4_state_2; - typedef struct packed { logic [ 3:0] x; bit [ 3:0] y; } struct_4_state_8; - typedef struct packed { logic [ 3:0] x; bit [ 4:0] y; } struct_4_state_9; - typedef struct packed { logic [ 7:0] x; bit [ 7:0] y; } struct_4_state_16; - typedef struct packed { logic [ 7:0] x; bit [ 8:0] y; } struct_4_state_17; - typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; - typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; - typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; - typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; - typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; + // 4-state packed structures of any size + typedef struct packed { logic [ 0:0] x; } struct_4_state_1; + typedef struct packed { logic [ 0:0] x; bit [ 0:0] y; } struct_4_state_2; + typedef struct packed { logic [ 3:0] x; bit [ 3:0] y; } struct_4_state_8; + typedef struct packed { logic [ 3:0] x; bit [ 4:0] y; } struct_4_state_9; + typedef struct packed { logic [ 7:0] x; bit [ 7:0] y; } struct_4_state_16; + typedef struct packed { logic [ 7:0] x; bit [ 8:0] y; } struct_4_state_17; + typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; + typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; + typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; + typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; + typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; - // 4-state packed unions of any size - typedef union packed { logic [ 0:0] x; bit [ 0:0] y; } union_4_state_1; - typedef union packed { logic [ 1:0] x; bit [ 1:0] y; } union_4_state_2; - typedef union packed { logic [ 7:0] x; bit [ 7:0] y; } union_4_state_8; - typedef union packed { logic [ 8:0] x; bit [ 8:0] y; } union_4_state_9; - typedef union packed { logic [ 15:0] x; bit [ 15:0] y; } union_4_state_16; - typedef union packed { logic [ 16:0] x; bit [ 16:0] y; } union_4_state_17; - typedef union packed { logic [ 31:0] x; bit [ 31:0] y; } union_4_state_32; - typedef union packed { logic [ 32:0] x; bit [ 32:0] y; } union_4_state_33; - typedef union packed { logic [ 63:0] x; bit [ 63:0] y; } union_4_state_64; - typedef union packed { logic [ 64:0] x; bit [ 64:0] y; } union_4_state_65; - typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; + // 4-state packed unions of any size + typedef union packed { logic [ 0:0] x; bit [ 0:0] y; } union_4_state_1; + typedef union packed { logic [ 1:0] x; bit [ 1:0] y; } union_4_state_2; + typedef union packed { logic [ 7:0] x; bit [ 7:0] y; } union_4_state_8; + typedef union packed { logic [ 8:0] x; bit [ 8:0] y; } union_4_state_9; + typedef union packed { logic [ 15:0] x; bit [ 15:0] y; } union_4_state_16; + typedef union packed { logic [ 16:0] x; bit [ 16:0] y; } union_4_state_17; + typedef union packed { logic [ 31:0] x; bit [ 31:0] y; } union_4_state_32; + typedef union packed { logic [ 32:0] x; bit [ 32:0] y; } union_4_state_33; + typedef union packed { logic [ 63:0] x; bit [ 63:0] y; } union_4_state_64; + typedef union packed { logic [ 64:0] x; bit [ 64:0] y; } union_4_state_65; + typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; - //====================================================================== - // Imports - //====================================================================== + //====================================================================== + // Imports + //====================================================================== - // 2-state packed arrays of width > 32 - import "DPI-C" function bit [ 32:0] i_array_2_state_33(); - import "DPI-C" function bit [ 63:0] i_array_2_state_64(); - import "DPI-C" function bit [ 64:0] i_array_2_state_65(); - import "DPI-C" function bit [127:0] i_array_2_state_128(); + // 2-state packed arrays of width > 32 + import "DPI-C" function bit [ 32:0] i_array_2_state_33(); + import "DPI-C" function bit [ 63:0] i_array_2_state_64(); + import "DPI-C" function bit [ 64:0] i_array_2_state_65(); + import "DPI-C" function bit [127:0] i_array_2_state_128(); - // 2-state packed arrays of width > 32 via typedef - import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); - import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); - import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); - import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); + // 2-state packed arrays of width > 32 via typedef + import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); + import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); + import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); + import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); - // 2-state packed structures of width > 32 - import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); - import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); - import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); - import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); + // 2-state packed structures of width > 32 + import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); + import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); + import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); + import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); - // 2-state packed unions of width > 32 - import "DPI-C" function union_2_state_33 i_union_2_state_33(); - import "DPI-C" function union_2_state_64 i_union_2_state_64(); - import "DPI-C" function union_2_state_65 i_union_2_state_65(); - import "DPI-C" function union_2_state_128 i_union_2_state_128(); + // 2-state packed unions of width > 32 + import "DPI-C" function union_2_state_33 i_union_2_state_33(); + import "DPI-C" function union_2_state_64 i_union_2_state_64(); + import "DPI-C" function union_2_state_65 i_union_2_state_65(); + import "DPI-C" function union_2_state_128 i_union_2_state_128(); - // 4-state basic types - import "DPI-C" function integer i_integer(); + // 4-state basic types + import "DPI-C" function integer i_integer(); - // 4-state packed arrays of any size - import "DPI-C" function logic [ 0:0] i_array_4_state_1(); - import "DPI-C" function logic [ 1:0] i_array_4_state_2(); - import "DPI-C" function logic [ 7:0] i_array_4_state_8(); - import "DPI-C" function logic [ 8:0] i_array_4_state_9(); - import "DPI-C" function logic [ 15:0] i_array_4_state_16(); - import "DPI-C" function logic [ 16:0] i_array_4_state_17(); - import "DPI-C" function logic [ 31:0] i_array_4_state_32(); - import "DPI-C" function logic [ 32:0] i_array_4_state_33(); - import "DPI-C" function logic [ 63:0] i_array_4_state_64(); - import "DPI-C" function logic [ 64:0] i_array_4_state_65(); - import "DPI-C" function logic [127:0] i_array_4_state_128(); + // 4-state packed arrays of any size + import "DPI-C" function logic [ 0:0] i_array_4_state_1(); + import "DPI-C" function logic [ 1:0] i_array_4_state_2(); + import "DPI-C" function logic [ 7:0] i_array_4_state_8(); + import "DPI-C" function logic [ 8:0] i_array_4_state_9(); + import "DPI-C" function logic [ 15:0] i_array_4_state_16(); + import "DPI-C" function logic [ 16:0] i_array_4_state_17(); + import "DPI-C" function logic [ 31:0] i_array_4_state_32(); + import "DPI-C" function logic [ 32:0] i_array_4_state_33(); + import "DPI-C" function logic [ 63:0] i_array_4_state_64(); + import "DPI-C" function logic [ 64:0] i_array_4_state_65(); + import "DPI-C" function logic [127:0] i_array_4_state_128(); - // 4-state packed arrays of any size via typedef - import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); - import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); - import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); - import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); - import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); - import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); - import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); - import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); - import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); - import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); - import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); + // 4-state packed arrays of any size via typedef + import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); + import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); + import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); + import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); + import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); + import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); + import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); + import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); + import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); + import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); + import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); - // 4-state packed structures of any size - import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); - import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); - import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); - import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); - import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); - import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); - import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); - import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); - import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); - import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); - import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); + // 4-state packed structures of any size + import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); + import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); + import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); + import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); + import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); + import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); + import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); + import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); + import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); + import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); + import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); - // 4-state packed unions of any size - import "DPI-C" function union_4_state_1 i_union_4_state_1(); - import "DPI-C" function union_4_state_2 i_union_4_state_2(); - import "DPI-C" function union_4_state_8 i_union_4_state_8(); - import "DPI-C" function union_4_state_9 i_union_4_state_9(); - import "DPI-C" function union_4_state_16 i_union_4_state_16(); - import "DPI-C" function union_4_state_17 i_union_4_state_17(); - import "DPI-C" function union_4_state_32 i_union_4_state_32(); - import "DPI-C" function union_4_state_33 i_union_4_state_33(); - import "DPI-C" function union_4_state_64 i_union_4_state_64(); - import "DPI-C" function union_4_state_65 i_union_4_state_65(); - import "DPI-C" function union_4_state_128 i_union_4_state_128(); + // 4-state packed unions of any size + import "DPI-C" function union_4_state_1 i_union_4_state_1(); + import "DPI-C" function union_4_state_2 i_union_4_state_2(); + import "DPI-C" function union_4_state_8 i_union_4_state_8(); + import "DPI-C" function union_4_state_9 i_union_4_state_9(); + import "DPI-C" function union_4_state_16 i_union_4_state_16(); + import "DPI-C" function union_4_state_17 i_union_4_state_17(); + import "DPI-C" function union_4_state_32 i_union_4_state_32(); + import "DPI-C" function union_4_state_33 i_union_4_state_33(); + import "DPI-C" function union_4_state_64 i_union_4_state_64(); + import "DPI-C" function union_4_state_65 i_union_4_state_65(); + import "DPI-C" function union_4_state_128 i_union_4_state_128(); - //====================================================================== - // Exports - //====================================================================== + //====================================================================== + // Exports + //====================================================================== - // 2-state packed arrays of width > 32 - export "DPI-C" function e_array_2_state_33; - export "DPI-C" function e_array_2_state_64; - export "DPI-C" function e_array_2_state_65; - export "DPI-C" function e_array_2_state_128; + // 2-state packed arrays of width > 32 + export "DPI-C" function e_array_2_state_33; + export "DPI-C" function e_array_2_state_64; + export "DPI-C" function e_array_2_state_65; + export "DPI-C" function e_array_2_state_128; - // 2-state packed arrays of width > 32 via typedef - export "DPI-C" function e_array_2_state_33_t; - export "DPI-C" function e_array_2_state_64_t; - export "DPI-C" function e_array_2_state_65_t; - export "DPI-C" function e_array_2_state_128_t; + // 2-state packed arrays of width > 32 via typedef + export "DPI-C" function e_array_2_state_33_t; + export "DPI-C" function e_array_2_state_64_t; + export "DPI-C" function e_array_2_state_65_t; + export "DPI-C" function e_array_2_state_128_t; - // 2-state packed structures of width > 32 - export "DPI-C" function e_struct_2_state_33; - export "DPI-C" function e_struct_2_state_64; - export "DPI-C" function e_struct_2_state_65; - export "DPI-C" function e_struct_2_state_128; + // 2-state packed structures of width > 32 + export "DPI-C" function e_struct_2_state_33; + export "DPI-C" function e_struct_2_state_64; + export "DPI-C" function e_struct_2_state_65; + export "DPI-C" function e_struct_2_state_128; - // 2-state packed unions of width > 32 - export "DPI-C" function e_union_2_state_33; - export "DPI-C" function e_union_2_state_64; - export "DPI-C" function e_union_2_state_65; - export "DPI-C" function e_union_2_state_128; + // 2-state packed unions of width > 32 + export "DPI-C" function e_union_2_state_33; + export "DPI-C" function e_union_2_state_64; + export "DPI-C" function e_union_2_state_65; + export "DPI-C" function e_union_2_state_128; - // 4-state basic types - export "DPI-C" function e_integer; + // 4-state basic types + export "DPI-C" function e_integer; - // 4-state packed arrays of any size - export "DPI-C" function e_array_4_state_1; - export "DPI-C" function e_array_4_state_2; - export "DPI-C" function e_array_4_state_8; - export "DPI-C" function e_array_4_state_9; - export "DPI-C" function e_array_4_state_16; - export "DPI-C" function e_array_4_state_17; - export "DPI-C" function e_array_4_state_32; - export "DPI-C" function e_array_4_state_33; - export "DPI-C" function e_array_4_state_64; - export "DPI-C" function e_array_4_state_65; - export "DPI-C" function e_array_4_state_128; + // 4-state packed arrays of any size + export "DPI-C" function e_array_4_state_1; + export "DPI-C" function e_array_4_state_2; + export "DPI-C" function e_array_4_state_8; + export "DPI-C" function e_array_4_state_9; + export "DPI-C" function e_array_4_state_16; + export "DPI-C" function e_array_4_state_17; + export "DPI-C" function e_array_4_state_32; + export "DPI-C" function e_array_4_state_33; + export "DPI-C" function e_array_4_state_64; + export "DPI-C" function e_array_4_state_65; + export "DPI-C" function e_array_4_state_128; - // 4-state packed arrays of any size via typedef - export "DPI-C" function e_array_4_state_1_t; - export "DPI-C" function e_array_4_state_2_t; - export "DPI-C" function e_array_4_state_8_t; - export "DPI-C" function e_array_4_state_9_t; - export "DPI-C" function e_array_4_state_16_t; - export "DPI-C" function e_array_4_state_17_t; - export "DPI-C" function e_array_4_state_32_t; - export "DPI-C" function e_array_4_state_33_t; - export "DPI-C" function e_array_4_state_64_t; - export "DPI-C" function e_array_4_state_65_t; - export "DPI-C" function e_array_4_state_128_t; + // 4-state packed arrays of any size via typedef + export "DPI-C" function e_array_4_state_1_t; + export "DPI-C" function e_array_4_state_2_t; + export "DPI-C" function e_array_4_state_8_t; + export "DPI-C" function e_array_4_state_9_t; + export "DPI-C" function e_array_4_state_16_t; + export "DPI-C" function e_array_4_state_17_t; + export "DPI-C" function e_array_4_state_32_t; + export "DPI-C" function e_array_4_state_33_t; + export "DPI-C" function e_array_4_state_64_t; + export "DPI-C" function e_array_4_state_65_t; + export "DPI-C" function e_array_4_state_128_t; - // 4-state packed structures of any size - export "DPI-C" function e_struct_4_state_1; - export "DPI-C" function e_struct_4_state_2; - export "DPI-C" function e_struct_4_state_8; - export "DPI-C" function e_struct_4_state_9; - export "DPI-C" function e_struct_4_state_16; - export "DPI-C" function e_struct_4_state_17; - export "DPI-C" function e_struct_4_state_32; - export "DPI-C" function e_struct_4_state_33; - export "DPI-C" function e_struct_4_state_64; - export "DPI-C" function e_struct_4_state_65; - export "DPI-C" function e_struct_4_state_128; + // 4-state packed structures of any size + export "DPI-C" function e_struct_4_state_1; + export "DPI-C" function e_struct_4_state_2; + export "DPI-C" function e_struct_4_state_8; + export "DPI-C" function e_struct_4_state_9; + export "DPI-C" function e_struct_4_state_16; + export "DPI-C" function e_struct_4_state_17; + export "DPI-C" function e_struct_4_state_32; + export "DPI-C" function e_struct_4_state_33; + export "DPI-C" function e_struct_4_state_64; + export "DPI-C" function e_struct_4_state_65; + export "DPI-C" function e_struct_4_state_128; - // 4-state packed unions of any size - export "DPI-C" function e_union_4_state_1; - export "DPI-C" function e_union_4_state_2; - export "DPI-C" function e_union_4_state_8; - export "DPI-C" function e_union_4_state_9; - export "DPI-C" function e_union_4_state_16; - export "DPI-C" function e_union_4_state_17; - export "DPI-C" function e_union_4_state_32; - export "DPI-C" function e_union_4_state_33; - export "DPI-C" function e_union_4_state_64; - export "DPI-C" function e_union_4_state_65; - export "DPI-C" function e_union_4_state_128; + // 4-state packed unions of any size + export "DPI-C" function e_union_4_state_1; + export "DPI-C" function e_union_4_state_2; + export "DPI-C" function e_union_4_state_8; + export "DPI-C" function e_union_4_state_9; + export "DPI-C" function e_union_4_state_16; + export "DPI-C" function e_union_4_state_17; + export "DPI-C" function e_union_4_state_32; + export "DPI-C" function e_union_4_state_33; + export "DPI-C" function e_union_4_state_64; + export "DPI-C" function e_union_4_state_65; + export "DPI-C" function e_union_4_state_128; - //====================================================================== - // Definitions of exported functions - //====================================================================== + //====================================================================== + // Definitions of exported functions + //====================================================================== - // 2-state packed arrays of width > 32 - function bit [ 32:0] e_array_2_state_33(); return 0; endfunction - function bit [ 63:0] e_array_2_state_64(); return 0; endfunction - function bit [ 64:0] e_array_2_state_65(); return 0; endfunction - function bit [127:0] e_array_2_state_128(); return 0; endfunction + // 2-state packed arrays of width > 32 + function bit [ 32:0] e_array_2_state_33(); return 0; endfunction + function bit [ 63:0] e_array_2_state_64(); return 0; endfunction + function bit [ 64:0] e_array_2_state_65(); return 0; endfunction + function bit [127:0] e_array_2_state_128(); return 0; endfunction - // 2-state packed arrays of width > 32 via typedef - function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction - function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction - function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction - function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction + // 2-state packed arrays of width > 32 via typedef + function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction + function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction + function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction + function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction - // 2-state packed structures of width > 32 - function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction - function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction - function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction - function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction + // 2-state packed structures of width > 32 + function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction + function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction + function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction + function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction - // 2-state packed unions of width > 32 - function union_2_state_33 e_union_2_state_33(); return 0; endfunction - function union_2_state_64 e_union_2_state_64(); return 0; endfunction - function union_2_state_65 e_union_2_state_65(); return 0; endfunction - function union_2_state_128 e_union_2_state_128(); return 0; endfunction + // 2-state packed unions of width > 32 + function union_2_state_33 e_union_2_state_33(); return 0; endfunction + function union_2_state_64 e_union_2_state_64(); return 0; endfunction + function union_2_state_65 e_union_2_state_65(); return 0; endfunction + function union_2_state_128 e_union_2_state_128(); return 0; endfunction - // 4-state basic types - function integer e_integer(); return 0; endfunction + // 4-state basic types + function integer e_integer(); return 0; endfunction - // 4-state packed arrays of any size - function logic [ 0:0] e_array_4_state_1(); return 0; endfunction - function logic [ 1:0] e_array_4_state_2(); return 0; endfunction - function logic [ 7:0] e_array_4_state_8(); return 0; endfunction - function logic [ 8:0] e_array_4_state_9(); return 0; endfunction - function logic [ 15:0] e_array_4_state_16(); return 0; endfunction - function logic [ 16:0] e_array_4_state_17(); return 0; endfunction - function logic [ 31:0] e_array_4_state_32(); return 0; endfunction - function logic [ 32:0] e_array_4_state_33(); return 0; endfunction - function logic [ 63:0] e_array_4_state_64(); return 0; endfunction - function logic [ 64:0] e_array_4_state_65(); return 0; endfunction - function logic [127:0] e_array_4_state_128(); return 0; endfunction + // 4-state packed arrays of any size + function logic [ 0:0] e_array_4_state_1(); return 0; endfunction + function logic [ 1:0] e_array_4_state_2(); return 0; endfunction + function logic [ 7:0] e_array_4_state_8(); return 0; endfunction + function logic [ 8:0] e_array_4_state_9(); return 0; endfunction + function logic [ 15:0] e_array_4_state_16(); return 0; endfunction + function logic [ 16:0] e_array_4_state_17(); return 0; endfunction + function logic [ 31:0] e_array_4_state_32(); return 0; endfunction + function logic [ 32:0] e_array_4_state_33(); return 0; endfunction + function logic [ 63:0] e_array_4_state_64(); return 0; endfunction + function logic [ 64:0] e_array_4_state_65(); return 0; endfunction + function logic [127:0] e_array_4_state_128(); return 0; endfunction - // 4-state packed arrays of any size via typedef - function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction - function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction - function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction - function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction - function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction - function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction - function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction - function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction - function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction - function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction - function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction + // 4-state packed arrays of any size via typedef + function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction + function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction + function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction + function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction + function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction + function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction + function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction + function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction + function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction + function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction + function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction - // 4-state packed structures of any size - function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction - function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction - function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction - function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction - function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction - function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction - function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction - function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction - function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction - function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction - function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction + // 4-state packed structures of any size + function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction + function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction + function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction + function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction + function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction + function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction + function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction + function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction + function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction + function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction + function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction - // 4-state packed unions of any size - function union_4_state_1 e_union_4_state_1(); return 0; endfunction - function union_4_state_2 e_union_4_state_2(); return 0; endfunction - function union_4_state_8 e_union_4_state_8(); return 0; endfunction - function union_4_state_9 e_union_4_state_9(); return 0; endfunction - function union_4_state_16 e_union_4_state_16(); return 0; endfunction - function union_4_state_17 e_union_4_state_17(); return 0; endfunction - function union_4_state_32 e_union_4_state_32(); return 0; endfunction - function union_4_state_33 e_union_4_state_33(); return 0; endfunction - function union_4_state_64 e_union_4_state_64(); return 0; endfunction - function union_4_state_65 e_union_4_state_65(); return 0; endfunction - function union_4_state_128 e_union_4_state_128(); return 0; endfunction + // 4-state packed unions of any size + function union_4_state_1 e_union_4_state_1(); return 0; endfunction + function union_4_state_2 e_union_4_state_2(); return 0; endfunction + function union_4_state_8 e_union_4_state_8(); return 0; endfunction + function union_4_state_9 e_union_4_state_9(); return 0; endfunction + function union_4_state_16 e_union_4_state_16(); return 0; endfunction + function union_4_state_17 e_union_4_state_17(); return 0; endfunction + function union_4_state_32 e_union_4_state_32(); return 0; endfunction + function union_4_state_33 e_union_4_state_33(); return 0; endfunction + function union_4_state_64 e_union_4_state_64(); return 0; endfunction + function union_4_state_65 e_union_4_state_65(); return 0; endfunction + function union_4_state_128 e_union_4_state_128(); return 0; endfunction endmodule diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v index 89ef95c72..af88dde19 100644 --- a/test_regress/t/t_dpi_shortcircuit.v +++ b/test_regress/t/t_dpi_shortcircuit.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_SHORTREAL `endif @@ -18,213 +19,213 @@ module t; - // Note these are NOT pure. - import "DPI-C" function void dpii_clear(); - import "DPI-C" function int dpii_count(input int ctr); - import "DPI-C" function bit dpii_inc0(input int ctr); - import "DPI-C" function bit dpii_inc1(input int ctr); - import "DPI-C" function bit dpii_incx(input int ctr, input bit value); + // Note these are NOT pure. + import "DPI-C" function void dpii_clear(); + import "DPI-C" function int dpii_count(input int ctr); + import "DPI-C" function bit dpii_inc0(input int ctr); + import "DPI-C" function bit dpii_inc1(input int ctr); + import "DPI-C" function bit dpii_incx(input int ctr, input bit value); - integer i; - integer j; - bit b; - int errors; + integer i; + integer j; + bit b; + int errors; - task check1(integer line, bit got, bit ex); - if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; - end - endtask - task check(integer line, int got, int ex); - if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; - end - endtask + task check1(integer line, bit got, bit ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask + task check(integer line, int got, int ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask - // Test loop - initial begin - // Spec says && || -> and ?: short circuit, no others do. - // Check both constant & non constants. - dpii_clear(); - check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0); - check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0); - check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0); - check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0); - check1(`__LINE__, (dpii_inc0(10) && 1'b0), 1'b0); - check1(`__LINE__, (dpii_inc0(11) && 1'b1), 1'b0); - check (`__LINE__, dpii_count(0), 0); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 0); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 0); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - check (`__LINE__, dpii_count(10), 1); - check (`__LINE__, dpii_count(11), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0); - check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0); - check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0); - check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0); - check1(`__LINE__, (dpii_inc0(10) & 1'b0), 1'b0); - check1(`__LINE__, (dpii_inc0(11) & 1'b1), 1'b0); - check (`__LINE__, dpii_count(0), 1); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 1); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - check (`__LINE__, dpii_count(10), 1); - check (`__LINE__, dpii_count(11), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1); - check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1); - check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1); - check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0); - check1(`__LINE__, (dpii_inc0(10) || 1'b0), 1'b0); - check1(`__LINE__, (dpii_inc0(11) || 1'b1), 1'b1); - check (`__LINE__, dpii_count(0), 1); - check (`__LINE__, dpii_count(1), 0); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 1); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 0); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 0); - check (`__LINE__, dpii_count(10), 1); - check (`__LINE__, dpii_count(11), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1); - check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1); - check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1); - check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0); - check1(`__LINE__, (dpii_inc0(10) | 1'b0), 1'b0); - check1(`__LINE__, (dpii_inc0(11) | 1'b1), 1'b1); - check (`__LINE__, dpii_count(0), 1); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 1); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - check (`__LINE__, dpii_count(10), 1); - check (`__LINE__, dpii_count(11), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1); - check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0); - check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1); - check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0); - check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1); - check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0); - check (`__LINE__, dpii_count(0), 0); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 0); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 0); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0); - check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0); - check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0); - check (`__LINE__, dpii_count(0), 0); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 0); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 0); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 0); - // - dpii_clear(); - check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0); - check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0); - check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0); - check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0); - check (`__LINE__, dpii_count(0), 1); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 1); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - // - dpii_clear(); - check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0); - check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1); - check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0); - check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1); - check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1); - check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0); - check (`__LINE__, dpii_count(0), 1); - check (`__LINE__, dpii_count(1), 1); - check (`__LINE__, dpii_count(2), 1); - check (`__LINE__, dpii_count(3), 1); - check (`__LINE__, dpii_count(4), 1); - check (`__LINE__, dpii_count(5), 1); - check (`__LINE__, dpii_count(6), 1); - check (`__LINE__, dpii_count(7), 1); - check (`__LINE__, dpii_count(8), 1); - check (`__LINE__, dpii_count(9), 1); - // - // Something a lot more complicated - dpii_clear(); - for (i=0; i<64; i++) begin - b = ( ((dpii_incx(0,i[0]) - && (dpii_incx(1,i[1]) - || dpii_incx(2,i[2]) - | dpii_incx(3,i[3]))) // | not || - || dpii_incx(4,i[4])) - -> dpii_incx(5,i[5])); - end - check (`__LINE__, dpii_count(0), 64); - check (`__LINE__, dpii_count(1), 32); - check (`__LINE__, dpii_count(2), 16); - check (`__LINE__, dpii_count(3), 16); - check (`__LINE__, dpii_count(4), 36); - check (`__LINE__, dpii_count(5), 46); + // Test loop + initial begin + // Spec says && || -> and ?: short circuit, no others do. + // Check both constant & non constants. + dpii_clear(); + check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0); + check1(`__LINE__, (dpii_inc0(10) && 1'b0), 1'b0); + check1(`__LINE__, (dpii_inc0(11) && 1'b1), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 0); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + check (`__LINE__, dpii_count(10), 1); + check (`__LINE__, dpii_count(11), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0); + check1(`__LINE__, (dpii_inc0(10) & 1'b0), 1'b0); + check1(`__LINE__, (dpii_inc0(11) & 1'b1), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + check (`__LINE__, dpii_count(10), 1); + check (`__LINE__, dpii_count(11), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0); + check1(`__LINE__, (dpii_inc0(10) || 1'b0), 1'b0); + check1(`__LINE__, (dpii_inc0(11) || 1'b1), 1'b1); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 0); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 0); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 0); + check (`__LINE__, dpii_count(10), 1); + check (`__LINE__, dpii_count(11), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0); + check1(`__LINE__, (dpii_inc0(10) | 1'b0), 1'b0); + check1(`__LINE__, (dpii_inc0(11) | 1'b1), 1'b1); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + check (`__LINE__, dpii_count(10), 1); + check (`__LINE__, dpii_count(11), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1); + check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1); + check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 0); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0); + check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0); + check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 0); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 0); + // + dpii_clear(); + check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1); + check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + // Something a lot more complicated + dpii_clear(); + for (i=0; i<64; i++) begin + b = ( ((dpii_incx(0,i[0]) + && (dpii_incx(1,i[1]) + || dpii_incx(2,i[2]) + | dpii_incx(3,i[3]))) // | not || + || dpii_incx(4,i[4])) + -> dpii_incx(5,i[5])); + end + check (`__LINE__, dpii_count(0), 64); + check (`__LINE__, dpii_count(1), 32); + check (`__LINE__, dpii_count(2), 16); + check (`__LINE__, dpii_count(3), 16); + check (`__LINE__, dpii_count(4), 36); + check (`__LINE__, dpii_count(5), 46); - if (|errors) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (|errors) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v index 8401d02c6..6c0f02227 100644 --- a/test_regress/t/t_dpi_shortcircuit2.v +++ b/test_regress/t/t_dpi_shortcircuit2.v @@ -6,6 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `ifdef VCS `define NO_SHORTREAL `endif @@ -15,52 +16,54 @@ `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif +// verilog_format: on module t; - // Note these are NOT pure. - import "DPI-C" function void dpii_clear(); - import "DPI-C" function int dpii_count(input int ctr); - import "DPI-C" function bit dpii_inc0(input int ctr); - import "DPI-C" function bit dpii_inc1(input int ctr); - import "DPI-C" function bit dpii_incx(input int ctr, input bit value); + // Note these are NOT pure. + import "DPI-C" function void dpii_clear(); + import "DPI-C" function int dpii_count(input int ctr); + import "DPI-C" function bit dpii_inc0(input int ctr); + import "DPI-C" function bit dpii_inc1(input int ctr); + import "DPI-C" function bit dpii_incx( + input int ctr, + input bit value + ); - integer i; - integer j; - integer k; - bit b; - int errors; + integer i; + integer j; + integer k; + bit b; + int errors; - task check1(integer line, bit got, bit ex); - if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; - end - endtask - task check(integer line, int got, int ex); - if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; - end - endtask + task check1(integer line, bit got, bit ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d", line, got, ex); + errors++; + end + endtask + task check(integer line, int got, int ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d", line, got, ex); + errors++; + end + endtask - // Test loop - initial begin - dpii_clear(); - j = 0; - for (i=0; i<64; i++) begin - if (i[0]) - j = 0; - else - j = {31'b0, dpii_inc1(0)}; - k = k + j; - end - $write("%x\n",k); - check (`__LINE__, dpii_count(0), 32); + // Test loop + initial begin + dpii_clear(); + j = 0; + for (i = 0; i < 64; i++) begin + if (i[0]) j = 0; + else j = {31'b0, dpii_inc1(0)}; + k = k + j; + end + $write("%x\n", k); + check(`__LINE__, dpii_count(0), 32); - if (|errors) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (|errors) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_string.v b/test_regress/t/t_dpi_string.v index eb723c6b1..58b23722a 100644 --- a/test_regress/t/t_dpi_string.v +++ b/test_regress/t/t_dpi_string.v @@ -8,20 +8,20 @@ module t; - import "DPI-C" function int dpii_string(input string DSM_NAME); + import "DPI-C" function int dpii_string(input string DSM_NAME); - generate - begin : DSM - string SOME_STRING; - end - endgenerate + generate + begin : DSM + string SOME_STRING; + end + endgenerate - initial begin - $sformat(DSM.SOME_STRING, "%m"); - if (dpii_string(DSM.SOME_STRING) != 5) $stop; + initial begin + $sformat(DSM.SOME_STRING, "%m"); + if (dpii_string(DSM.SOME_STRING) != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_sys.v b/test_regress/t/t_dpi_sys.v index 232b94e6c..651dca747 100644 --- a/test_regress/t/t_dpi_sys.v +++ b/test_regress/t/t_dpi_sys.v @@ -13,17 +13,17 @@ import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); module t; `ifndef verilator - `error "Only Verilator supports PLI-ish DPI calls." + `error "Only Verilator supports PLI-ish DPI calls." `endif - initial begin - $dpii_sys(1); - if ($dpii_func(2) != 3) $stop; - $dpii_sys(10); - if ($dpii_func(2) != 12) $stop; + initial begin + $dpii_sys(1); + if ($dpii_func(2) != 3) $stop; + $dpii_sys(10); + if ($dpii_func(2) != 12) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_threads.v b/test_regress/t/t_dpi_threads.v index 36b6e3bdd..7d7b10bcc 100644 --- a/test_regress/t/t_dpi_threads.v +++ b/test_regress/t/t_dpi_threads.v @@ -10,54 +10,54 @@ import "DPI-C" dpii_sys_task = function void \$dpii_sys (); import "DPI-C" dpii_failure = function int \$dpii_failure (); module t (clk); - input clk; - integer cyc; - integer failure; + input clk; + integer cyc; + integer failure; - initial cyc = 0; + initial cyc = 0; `ifndef verilator - `error "Only Verilator supports PLI-ish DPI calls." + `error "Only Verilator supports PLI-ish DPI calls." `endif - always @ (posedge clk) begin - if (cyc == 2) begin - failure = $dpii_failure(); - $write("* failure = %0d\n", failure); - if (failure > 0) begin - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; + always @ (posedge clk) begin + if (cyc == 2) begin + failure = $dpii_failure(); + $write("* failure = %0d\n", failure); + if (failure > 0) begin + $stop; end - cyc <= cyc + 1; - end + $write("*-* All Finished *-*\n"); + $finish; + end + cyc <= cyc + 1; + end - // The purpose of this test is to confirm that the DPI-call serialization - // code in V3Partition does ensure that these DPI calls do not run - // concurrently. - // - // Alternatively, the test may be run with "--threads-dpi all" in which case - // it should confirm that the calls do run concurrently and do detect a - // collision (they should, if the test is set up right.) This is - // t_dpi_threads_collide.py. - // - // Q) Is it a risk that the partitioner will merge or serialize these always - // blocks, just by luck, even if the DPI-call serialization code fails? - // - // A) Yes, that's why t_dpi_threads_collide.py also passes - // --no-threads-do-coaren to disable MTask coarsening. This ensures that - // the MTask graph at the end of FixDataHazards (where we resolve DPI - // hazards) is basically the final MTasks graph, and that data hazards - // which persist beyond FixDataHazards should persist in the final - // generated C code. + // The purpose of this test is to confirm that the DPI-call serialization + // code in V3Partition does ensure that these DPI calls do not run + // concurrently. + // + // Alternatively, the test may be run with "--threads-dpi all" in which case + // it should confirm that the calls do run concurrently and do detect a + // collision (they should, if the test is set up right.) This is + // t_dpi_threads_collide.py. + // + // Q) Is it a risk that the partitioner will merge or serialize these always + // blocks, just by luck, even if the DPI-call serialization code fails? + // + // A) Yes, that's why t_dpi_threads_collide.py also passes + // --no-threads-do-coaren to disable MTask coarsening. This ensures that + // the MTask graph at the end of FixDataHazards (where we resolve DPI + // hazards) is basically the final MTasks graph, and that data hazards + // which persist beyond FixDataHazards should persist in the final + // generated C code. - always @ (posedge clk) begin - $dpii_sys(); - end + always @ (posedge clk) begin + $dpii_sys(); + end - always @ (posedge clk) begin - $dpii_sys(); - end + always @ (posedge clk) begin + $dpii_sys(); + end endmodule diff --git a/test_regress/t/t_dpi_type_bad.out b/test_regress/t/t_dpi_type_bad.out index de3df00e1..acf68f947 100644 --- a/test_regress/t/t_dpi_type_bad.out +++ b/test_regress/t/t_dpi_type_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_dpi_type_bad.v:11:4: Unsupported DPI type 'DPI-BAD': Use 'DPI-C' (IEEE 1800-2023 35.5.4) - 11 | import "DPI-BAD" task dpix_twice; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_dpi_type_bad.v:11:3: Unsupported DPI type 'DPI-BAD': Use 'DPI-C' (IEEE 1800-2023 35.5.4) + 11 | import "DPI-BAD" task dpix_twice; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_dpi_type_bad.v b/test_regress/t/t_dpi_type_bad.v index 92529cfd8..61c53ce24 100644 --- a/test_regress/t/t_dpi_type_bad.v +++ b/test_regress/t/t_dpi_type_bad.v @@ -8,8 +8,8 @@ module t; - import "DPI-BAD" task dpix_twice; - initial begin - $stop; - end + import "DPI-BAD" task dpix_twice; + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_dpi_unpack_bad.out b/test_regress/t/t_dpi_unpack_bad.out index 2b2876c9e..7474ee54c 100644 --- a/test_regress/t/t_dpi_unpack_bad.out +++ b/test_regress/t/t_dpi_unpack_bad.out @@ -1,32 +1,32 @@ -%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:21:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]' v.s. 'logic[3:0]') +%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:21:18: Shape of the argument does not match the shape of the parameter ('logic[2:0]' v.s. 'logic[3:0]') : ... note: In instance 't' - 21 | import_func0(sig0); - | ^~~~ + 21 | import_func0(sig0); + | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. +%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:21:5: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. : ... note: In instance 't' - 21 | import_func0(sig0); - | ^~~~~~~~~~~~ + 21 | import_func0(sig0); + | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:23:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2]') +%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:23:18: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2]') : ... note: In instance 't' - 23 | import_func1(sig1); - | ^~~~ -%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:25:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2][0:2]') + 23 | import_func1(sig1); + | ^~~~ +%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:25:18: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2][0:2]') : ... note: In instance 't' - 25 | import_func2(sig1); - | ^~~~ -%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:27:20: Shape of the argument does not match the shape of the parameter ('bit[2:0]' v.s. 'logic[2:0]') + 25 | import_func2(sig1); + | ^~~~ +%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:27:18: Shape of the argument does not match the shape of the parameter ('bit[2:0]' v.s. 'logic[2:0]') : ... note: In instance 't' - 27 | import_func2(sig2); - | ^~~~ -%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:29:24: Argument is not an unpacked array while parameter 'in' is + 27 | import_func2(sig2); + | ^~~~ +%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:29:22: Argument is not an unpacked array while parameter 'in' is : ... note: In instance 't' - 29 | import_func0(sig0[1]); - | ^ -%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits. + 29 | import_func0(sig0[1]); + | ^ +%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:29:5: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits. : ... note: In instance 't' - 29 | import_func0(sig0[1]); - | ^~~~~~~~~~~~ + 29 | import_func0(sig0[1]); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_unpack_bad.v b/test_regress/t/t_dpi_unpack_bad.v index 209d1d379..c21862c13 100644 --- a/test_regress/t/t_dpi_unpack_bad.v +++ b/test_regress/t/t_dpi_unpack_bad.v @@ -8,24 +8,24 @@ module t; - logic [2:0] sig0[3]; - logic [2:0] sig1[3][2]; - bit [2:0] sig2[3][3]; + logic [2:0] sig0[3]; + logic [2:0] sig1[3][2]; + bit [2:0] sig2[3][3]; - import "DPI-C" function void import_func0(input logic [3:0] in [0:2]); - import "DPI-C" function void import_func1(input logic [2:0] in [0:2]); - import "DPI-C" function void import_func2(input logic [2:0] in [0:2][0:2]); + import "DPI-C" function void import_func0(input logic [3:0] in[0:2]); + import "DPI-C" function void import_func1(input logic [2:0] in[0:2]); + import "DPI-C" function void import_func2(input logic [2:0] in[0:2][0:2]); - initial begin - // packed width differs - import_func0(sig0); - // dimension differs - import_func1(sig1); - // unpacked extent differs - import_func2(sig1); - // bit v.s. logic mismatch - import_func2(sig2); - // packed var for unpacked port - import_func0(sig0[1]); - end + initial begin + // packed width differs + import_func0(sig0); + // dimension differs + import_func1(sig1); + // unpacked extent differs + import_func2(sig1); + // bit v.s. logic mismatch + import_func2(sig2); + // packed var for unpacked port + import_func0(sig0[1]); + end endmodule diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v index 50f5983c9..ac19dae9a 100644 --- a/test_regress/t/t_dpi_vams.v +++ b/test_regress/t/t_dpi_vams.v @@ -7,23 +7,26 @@ //`begin_keywords "VAMS-2.3" `begin_keywords "1800+VAMS" -module t (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); +module t ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); - input in; - wreal in; - output out; - wreal out; + input in; + wreal in; + output out; + wreal out; - import "DPI-C" context function void dpii_call(input real in, output real out); + import "DPI-C" context function void dpii_call( + input real in, + output real out + ); - initial begin - dpii_call(in,out); - $finish; - end + initial begin + dpii_call(in, out); + $finish; + end endmodule diff --git a/test_regress/t/t_dpi_var.v b/test_regress/t/t_dpi_var.v index b1675d334..8a0c111c9 100644 --- a/test_regress/t/t_dpi_var.v +++ b/test_regress/t/t_dpi_var.v @@ -7,61 +7,61 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; + integer cyc = 0; - wire monclk = ~clk; + wire monclk = ~clk; - int in; - int in_a; - int in_b; - int fr_a; - int fr_b; - int fr_a2; - int fr_b2; - int fr_chk; - sub sub (.*); + int in; + int in_a; + int in_b; + int fr_a; + int fr_b; + int fr_a2; + int fr_b2; + int fr_chk; + sub sub (.*); - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d in=%x sub.in_a=%x sub.in_b=%x fr_a=%x fr_b=%x fr_a2=%x fr_b2=%x fr_chk=%x\n", - $time, cyc, in, sub.in_a, sub.in_b, fr_a, fr_b, fr_a2, fr_b2, fr_chk); + $write("[%0t] cyc==%0d in=%x sub.in_a=%x sub.in_b=%x fr_a=%x fr_b=%x fr_a2=%x fr_b2=%x fr_chk=%x\n", + $time, cyc, in, sub.in_a, sub.in_b, fr_a, fr_b, fr_a2, fr_b2, fr_chk); `endif - cyc <= cyc + 1; - in <= {in[30:0], in[31]^in[2]^in[0]}; - // The inputs to sub will be updated externally on the neg-edge so these - // don't matter for the result - in_a <= in_a + 1; - in_b <= in_b + 1; - if (cyc==0) begin - // Setup - in <= 32'hd70a4497; - in_a <= 0; - in_b <= 0; - end - else if (cyc<3) begin - end - else if (cyc<10) begin - if (fr_chk != fr_a) $stop; - if (fr_chk != fr_b) $stop; - if (fr_chk != fr_a2) $stop; - if (fr_chk != fr_b2) $stop; - end - else if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + in <= {in[30:0], in[31]^in[2]^in[0]}; + // The inputs to sub will be updated externally on the neg-edge so these + // don't matter for the result + in_a <= in_a + 1; + in_b <= in_b + 1; + if (cyc==0) begin + // Setup + in <= 32'hd70a4497; + in_a <= 0; + in_b <= 0; + end + else if (cyc<3) begin + end + else if (cyc<10) begin + if (fr_chk != fr_a) $stop; + if (fr_chk != fr_b) $stop; + if (fr_chk != fr_a2) $stop; + if (fr_chk != fr_b2) $stop; + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge t.monclk) begin - mon_eval(); - end + always @(posedge t.monclk) begin + mon_eval(); + end endmodule @@ -75,55 +75,55 @@ import "DPI-C" context function void mon_register_done(); import "DPI-C" context function void mon_eval(); module sub (/*AUTOARG*/ - // Outputs - fr_a, fr_b, fr_a2, fr_b2, fr_chk, - // Inputs - in, in_a, in_b - ); + // Outputs + fr_a, fr_b, fr_a2, fr_b2, fr_chk, + // Inputs + in, in_a, in_b + ); `systemc_imp_header void mon_class_name(const char* namep); void mon_register_a(const char* namep, void* sigp, bool isOut, int n, int addend); `verilog - /* verilator lint_off ASSIGNIN */ + /* verilator lint_off ASSIGNIN */ `ifdef ATTRIBUTES // Sensitivity list accepted for backward compatibility but ignored - input int in /*verilator public_flat_rd*/; - input int in_a /*verilator public_flat_rw @(posedge t.monclk)*/; - input int in_b /*verilator public_flat_rw*/; - output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; - output int fr_b /*verilator public_flat_rw*/; + input int in /*verilator public_flat_rd*/; + input int in_a /*verilator public_flat_rw @(posedge t.monclk)*/; + input int in_b /*verilator public_flat_rw*/; + output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; + output int fr_b /*verilator public_flat_rw*/; `else - input int in; - input int in_a; - input int in_b; - output int fr_a; - output int fr_b; + input int in; + input int in_a; + input int in_b; + output int fr_a; + output int fr_b; `endif - output int fr_a2; - output int fr_b2; - output int fr_chk; - /* verilator lint_on ASSIGNIN */ + output int fr_a2; + output int fr_b2; + output int fr_chk; + /* verilator lint_on ASSIGNIN */ - always @* fr_a2 = in_a + 1; - always @* fr_b2 = in_b + 1; - always @* fr_chk = in + 1; + always @* fr_a2 = in_a + 1; + always @* fr_b2 = in_b + 1; + always @* fr_chk = in + 1; - initial begin - // Test the naming - $c("mon_class_name(this->vlNamep);"); - mon_scope_name("%m"); - // Scheme A - pass pointer directly - $c("mon_register_a(\"in\", &", in, ", false, 0, 1);"); - $c("mon_register_a(\"fr_a\", &", fr_a, ", true, 0, 1);"); - $c("mon_register_a(\"in\", &", in, ", false, 1, 0);"); - $c("mon_register_a(\"in_a\", &", in_a, ", true, 1, 0);"); - // Scheme B - use VPIish callbacks to see what signals exist - mon_register_b("in", 0, 2, 1); - mon_register_b("fr_b", 1, 2, 1); - mon_register_b("in", 0, 3, 0); - mon_register_b("in_b", 1, 3, 0); - mon_register_done(); - end + initial begin + // Test the naming + $c("mon_class_name(this->vlNamep);"); + mon_scope_name("%m"); + // Scheme A - pass pointer directly + $c("mon_register_a(\"in\", &", in, ", false, 0, 1);"); + $c("mon_register_a(\"fr_a\", &", fr_a, ", true, 0, 1);"); + $c("mon_register_a(\"in\", &", in, ", false, 1, 0);"); + $c("mon_register_a(\"in_a\", &", in_a, ", true, 1, 0);"); + // Scheme B - use VPIish callbacks to see what signals exist + mon_register_b("in", 0, 2, 1); + mon_register_b("fr_b", 1, 2, 1); + mon_register_b("in", 0, 3, 0); + mon_register_b("in_b", 1, 3, 0); + mon_register_done(); + end endmodule diff --git a/test_regress/t/t_dump.v b/test_regress/t/t_dump.v index 94624910a..d24004b1d 100644 --- a/test_regress/t/t_dump.v +++ b/test_regress/t/t_dump.v @@ -4,153 +4,151 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk + ); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test(/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); + // Outputs + out, + // Inputs + clk, in + ); - // Replace this module with the device under test. - // - // Change the code in the t module to apply values to the inputs and - // merge the output values into the result vector. + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. - input clk; - input [31:0] in; - output reg [31:0] out; + input clk; + input [31:0] in; + output reg [31:0] out; - always @(posedge clk) begin - out <= in; + always @(posedge clk) begin + out <= in; - // Assert control dump test. - $assertoff; - $assertkill; - assert(0); - $asserton; - $assertcontrol(3, 8); - begin : blk - disable blk; - end - end - initial begin - assert_simple_immediate_else: assert(0) else $display("fail"); - assert_simple_immediate_stmt: assert(0) $display("pass"); - assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); + // Assert control dump test. + $assertoff; + $assertkill; + assert(0); + $asserton; + $assertcontrol(3, 8); + begin : blk + disable blk; + end + end + initial begin + assert_simple_immediate_else: assert(0) else $display("fail"); + assert_simple_immediate_stmt: assert(0) $display("pass"); + assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); - assume_simple_immediate: assume(0); - assume_simple_immediate_else: assume(0) else $display("fail"); - assume_simple_immediate_stmt: assume(0) $display("pass"); - assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); - end + assume_simple_immediate: assume(0); + assume_simple_immediate_else: assume(0) else $display("fail"); + assume_simple_immediate_stmt: assume(0) $display("pass"); + assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); + end - assert_observed_deferred_immediate: assert #0 (0); - assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); - assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); - assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); + assert_observed_deferred_immediate: assert #0 (0); + assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); + assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); + assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); - assume_observed_deferred_immediate: assume #0 (0); - assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); - assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); - assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); + assume_observed_deferred_immediate: assume #0 (0); + assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); + assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); + assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); - assert_final_deferred_immediate: assert final (0); - assert_final_deferred_immediate_else: assert final (0) else $display("fail"); - assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); - assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); + assert_final_deferred_immediate: assert final (0); + assert_final_deferred_immediate_else: assert final (0) else $display("fail"); + assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); + assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); - assume_final_deferred_immediate: assume final (0); - assume_final_deferred_immediate_else: assume final (0) else $display("fail"); - assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); - assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); + assume_final_deferred_immediate: assume final (0); + assume_final_deferred_immediate_else: assume final (0) else $display("fail"); + assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); + assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); - property prop(); - @(posedge clk) 0 - endproperty + property prop(); + @(posedge clk) 0 + endproperty - assert_concurrent: assert property (prop); - assert_concurrent_else: assert property(prop) else $display("fail"); - assert_concurrent_stmt: assert property(prop) $display("pass"); - assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); + assert_concurrent: assert property (prop); + assert_concurrent_else: assert property(prop) else $display("fail"); + assert_concurrent_stmt: assert property(prop) $display("pass"); + assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); - assume_concurrent: assume property(prop); - assume_concurrent_else: assume property(prop) else $display("fail"); - assume_concurrent_stmt: assume property(prop) $display("pass"); - assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); + assume_concurrent: assume property(prop); + assume_concurrent_else: assume property(prop) else $display("fail"); + assume_concurrent_stmt: assume property(prop) $display("pass"); + assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); - cover_concurrent: cover property(prop); - cover_concurrent_stmt: cover property(prop) $display("pass"); + cover_concurrent: cover property(prop); + cover_concurrent_stmt: cover property(prop) $display("pass"); - restrict property (prop); + restrict property (prop); - always_ff @(posedge clk) begin - unique0 casez(in) - 1: $display("1a"); - default: $display("1b"); - endcase - priority casez(1'b1) - in[0]: $display("2a"); - default: $display("2b"); - endcase - end + always_ff @(posedge clk) begin + unique0 casez(in) + 1: $display("1a"); + default: $display("1b"); + endcase + priority casez(1'b1) + in[0]: $display("2a"); + default: $display("2b"); + endcase + end endmodule diff --git a/test_regress/t/t_dump_json.out b/test_regress/t/t_dump_json.out index faaed000c..c5ab94f87 100644 --- a/test_regress/t/t_dump_json.out +++ b/test_regress/t/t_dump_json.out @@ -2,432 +2,432 @@ "modulesp": [ {"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - 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{"type":"PARSEREF","name":"crc","addr":"(FF)","loc":"e,45:10,45:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"crc","addr":"(FF)","loc":"e,43:9,43:12","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, - {"type":"ASSIGNDLY","name":"","addr":"(GF)","loc":"e,46:14,46:16","dtypep":"UNLINKED", + {"type":"ASSIGNDLY","name":"","addr":"(GF)","loc":"e,44:13,44:15","dtypep":"UNLINKED", "rhsp": [ - {"type":"CONST","name":"'0","addr":"(HF)","loc":"e,46:17,46:19","dtypep":"(YE)"} + {"type":"CONST","name":"'0","addr":"(HF)","loc":"e,44:16,44:18","dtypep":"(YE)"} ], "lhsp": [ - {"type":"PARSEREF","name":"sum","addr":"(IF)","loc":"e,46:10,46:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"sum","addr":"(IF)","loc":"e,44:9,44:12","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ]} ], "elsesp": [ - {"type":"IF","name":"","addr":"(JF)","loc":"e,48:12,48:14", + {"type":"IF","name":"","addr":"(JF)","loc":"e,46:11,46:13", "condp": [ - {"type":"LT","name":"","addr":"(KF)","loc":"e,48:20,48:21","dtypep":"(YE)", + {"type":"LT","name":"","addr":"(KF)","loc":"e,46:19,46:20","dtypep":"(YE)", "lhsp": [ - {"type":"PARSEREF","name":"cyc","addr":"(LF)","loc":"e,48:16,48:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"cyc","addr":"(LF)","loc":"e,46:15,46:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"CONST","name":"?32?sha","addr":"(MF)","loc":"e,48:22,48:24","dtypep":"(NF)"} + {"type":"CONST","name":"?32?sha","addr":"(MF)","loc":"e,46:21,46:23","dtypep":"(NF)"} ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(OF)","loc":"e,48:26,48:31","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(OF)","loc":"e,46:25,46:30","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"ASSIGNDLY","name":"","addr":"(PF)","loc":"e,49:14,49:16","dtypep":"UNLINKED", + {"type":"ASSIGNDLY","name":"","addr":"(PF)","loc":"e,47:13,47:15","dtypep":"UNLINKED", "rhsp": [ - {"type":"CONST","name":"'0","addr":"(QF)","loc":"e,49:17,49:19","dtypep":"(YE)"} + {"type":"CONST","name":"'0","addr":"(QF)","loc":"e,47:16,47:18","dtypep":"(YE)"} ], "lhsp": [ - {"type":"PARSEREF","name":"sum","addr":"(RF)","loc":"e,49:10,49:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"sum","addr":"(RF)","loc":"e,47:9,47:12","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ]} ], "elsesp": [ - {"type":"IF","name":"","addr":"(SF)","loc":"e,51:12,51:14", + {"type":"IF","name":"","addr":"(SF)","loc":"e,49:11,49:13", "condp": [ - {"type":"LT","name":"","addr":"(TF)","loc":"e,51:20,51:21","dtypep":"(YE)", + {"type":"LT","name":"","addr":"(TF)","loc":"e,49:19,49:20","dtypep":"(YE)", "lhsp": [ - {"type":"PARSEREF","name":"cyc","addr":"(UF)","loc":"e,51:16,51:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"cyc","addr":"(UF)","loc":"e,49:15,49:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"CONST","name":"?32?sh5a","addr":"(VF)","loc":"e,51:22,51:24","dtypep":"(WF)"} + {"type":"CONST","name":"?32?sh5a","addr":"(VF)","loc":"e,49:21,49:23","dtypep":"(WF)"} ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(XF)","loc":"e,51:26,51:31","unnamed":true,"declsp": [],"stmtsp": []} + {"type":"BEGIN","name":"","addr":"(XF)","loc":"e,49:25,49:30","unnamed":true,"declsp": [],"stmtsp": []} ], "elsesp": [ - {"type":"IF","name":"","addr":"(YF)","loc":"e,53:12,53:14", + {"type":"IF","name":"","addr":"(YF)","loc":"e,51:11,51:13", "condp": [ - {"type":"EQ","name":"","addr":"(ZF)","loc":"e,53:20,53:22","dtypep":"(YE)", + {"type":"EQ","name":"","addr":"(ZF)","loc":"e,51:19,51:21","dtypep":"(YE)", "lhsp": [ - {"type":"PARSEREF","name":"cyc","addr":"(AG)","loc":"e,53:16,53:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"cyc","addr":"(AG)","loc":"e,51:15,51:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"CONST","name":"?32?sh63","addr":"(BG)","loc":"e,53:23,53:25","dtypep":"(WF)"} + {"type":"CONST","name":"?32?sh63","addr":"(BG)","loc":"e,51:22,51:24","dtypep":"(WF)"} ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(CG)","loc":"e,53:27,53:32","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(CG)","loc":"e,51:26,51:31","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(DG)","loc":"e,54:10,54:16", + {"type":"DISPLAY","name":"","addr":"(DG)","loc":"e,52:9,52:15", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(EG)","loc":"e,54:10,54:16","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(EG)","loc":"e,52:9,52:15","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"232'h5b2530745d206379633d3d253064206372633d25782073756d3d25780a","addr":"(GG)","loc":"e,54:17,54:49","dtypep":"(HG)"}, - {"type":"TIME","name":"","addr":"(IG)","loc":"e,54:51,54:56","dtypep":"(JG)","timeunit":"NONE"}, - {"type":"PARSEREF","name":"cyc","addr":"(KG)","loc":"e,54:58,54:61","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, - {"type":"PARSEREF","name":"crc","addr":"(LG)","loc":"e,54:63,54:66","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, - {"type":"PARSEREF","name":"sum","addr":"(MG)","loc":"e,54:68,54:71","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"CONST","name":"232'h5b2530745d206379633d3d253064206372633d25782073756d3d25780a","addr":"(GG)","loc":"e,52:16,52:48","dtypep":"(HG)"}, + {"type":"TIME","name":"","addr":"(IG)","loc":"e,52:50,52:55","dtypep":"(JG)","timeunit":"NONE"}, + {"type":"PARSEREF","name":"cyc","addr":"(KG)","loc":"e,52:57,52:60","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, + {"type":"PARSEREF","name":"crc","addr":"(LG)","loc":"e,52:62,52:65","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, + {"type":"PARSEREF","name":"sum","addr":"(MG)","loc":"e,52:67,52:70","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"scopeNamep": []} ],"filep": []}, - {"type":"IF","name":"","addr":"(NG)","loc":"e,55:10,55:12", + {"type":"IF","name":"","addr":"(NG)","loc":"e,53:9,53:11", "condp": [ - {"type":"NEQCASE","name":"","addr":"(OG)","loc":"e,55:18,55:21","dtypep":"(YE)", + {"type":"NEQCASE","name":"","addr":"(OG)","loc":"e,53:17,53:20","dtypep":"(YE)", "lhsp": [ - {"type":"PARSEREF","name":"crc","addr":"(PG)","loc":"e,55:14,55:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"crc","addr":"(PG)","loc":"e,53:13,53:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"CONST","name":"64'hc77bb9b3784ea091","addr":"(QG)","loc":"e,55:22,55:42","dtypep":"(EF)"} + {"type":"CONST","name":"64'hc77bb9b3784ea091","addr":"(QG)","loc":"e,53:21,53:41","dtypep":"(EF)"} ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(RG)","loc":"e,55:44,55:49"} + {"type":"STOP","name":"","addr":"(RG)","loc":"e,53:43,53:48"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(SG)","loc":"e,58:10,58:12", + {"type":"IF","name":"","addr":"(SG)","loc":"e,56:9,56:11", "condp": [ - {"type":"NEQCASE","name":"","addr":"(TG)","loc":"e,58:18,58:21","dtypep":"(YE)", + {"type":"NEQCASE","name":"","addr":"(TG)","loc":"e,56:17,56:20","dtypep":"(YE)", "lhsp": [ - {"type":"PARSEREF","name":"sum","addr":"(UG)","loc":"e,58:14,58:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"sum","addr":"(UG)","loc":"e,56:13,56:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"CONST","name":"64'h4afe43fb79d7b71e","addr":"(VG)","loc":"e,58:22,58:42","dtypep":"(EF)"} + {"type":"CONST","name":"64'h4afe43fb79d7b71e","addr":"(VG)","loc":"e,56:21,56:41","dtypep":"(EF)"} ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(WG)","loc":"e,58:44,58:49"} + {"type":"STOP","name":"","addr":"(WG)","loc":"e,56:43,56:48"} ],"elsesp": []}, - {"type":"DISPLAY","name":"","addr":"(XG)","loc":"e,59:10,59:16", + {"type":"DISPLAY","name":"","addr":"(XG)","loc":"e,57:9,57:15", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(YG)","loc":"e,59:10,59:16","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(YG)","loc":"e,57:9,57:15","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"168'h2a2d2a20416c6c2046696e6973686564202a2d2a0a","addr":"(ZG)","loc":"e,59:17,59:41","dtypep":"(AH)"} + {"type":"CONST","name":"168'h2a2d2a20416c6c2046696e6973686564202a2d2a0a","addr":"(ZG)","loc":"e,57:16,57:40","dtypep":"(AH)"} ],"scopeNamep": []} ],"filep": []}, - {"type":"FINISH","name":"","addr":"(BH)","loc":"e,60:10,60:17"} + {"type":"FINISH","name":"","addr":"(BH)","loc":"e,58:9,58:16"} ]} ],"elsesp": []} ]} @@ -437,821 +437,821 @@ ]} ]} ]}, - {"type":"MODULE","name":"Test","addr":"(SB)","loc":"e,66:8,66:12","origName":"Test","verilogName":"Test","level":2,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"Test","addr":"(SB)","loc":"e,64:8,64:12","origName":"Test","verilogName":"Test","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"PORT","name":"out","addr":"(CH)","loc":"e,68:4,68:7","exprp": []}, - {"type":"PORT","name":"clk","addr":"(DH)","loc":"e,70:4,70:7","exprp": []}, - {"type":"PORT","name":"in","addr":"(EH)","loc":"e,70:9,70:11","exprp": []}, - {"type":"VAR","name":"clk","addr":"(FH)","loc":"e,78:10,78:13","dtypep":"UNLINKED","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", + {"type":"PORT","name":"out","addr":"(CH)","loc":"e,66:3,66:6","exprp": []}, + {"type":"PORT","name":"clk","addr":"(DH)","loc":"e,68:3,68:6","exprp": []}, + {"type":"PORT","name":"in","addr":"(EH)","loc":"e,68:8,68:10","exprp": []}, + {"type":"VAR","name":"clk","addr":"(FH)","loc":"e,76:9,76:12","dtypep":"UNLINKED","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(GH)","loc":"e,78:10,78:13","dtypep":"(GH)","keyword":"LOGIC_IMPLICIT","rangep": []} + {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(GH)","loc":"e,76:9,76:12","dtypep":"(GH)","keyword":"LOGIC_IMPLICIT","rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"in","addr":"(HH)","loc":"e,79:17,79:19","dtypep":"UNLINKED","origName":"in","verilogName":"in","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", + {"type":"VAR","name":"in","addr":"(HH)","loc":"e,77:16,77:18","dtypep":"UNLINKED","origName":"in","verilogName":"in","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(IH)","loc":"e,79:10,79:11","dtypep":"(IH)","keyword":"logic", + {"type":"BASICDTYPE","name":"logic","addr":"(IH)","loc":"e,77:9,77:10","dtypep":"(IH)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(JH)","loc":"e,79:10,79:11", + {"type":"RANGE","name":"","addr":"(JH)","loc":"e,77:9,77:10", "leftp": [ - {"type":"CONST","name":"?32?sh1f","addr":"(KH)","loc":"e,79:11,79:13","dtypep":"(DB)"} + {"type":"CONST","name":"?32?sh1f","addr":"(KH)","loc":"e,77:10,77:12","dtypep":"(DB)"} ], "rightp": [ - {"type":"CONST","name":"?32?sh0","addr":"(LH)","loc":"e,79:14,79:15","dtypep":"(N)"} + {"type":"CONST","name":"?32?sh0","addr":"(LH)","loc":"e,77:13,77:14","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"out","addr":"(MH)","loc":"e,80:22,80:25","dtypep":"UNLINKED","origName":"out","verilogName":"out","direction":"OUTPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", + {"type":"VAR","name":"out","addr":"(MH)","loc":"e,78:21,78:24","dtypep":"UNLINKED","origName":"out","verilogName":"out","direction":"OUTPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(NH)","loc":"e,80:11,80:14","dtypep":"(NH)","keyword":"logic", + {"type":"BASICDTYPE","name":"logic","addr":"(NH)","loc":"e,78:10,78:13","dtypep":"(NH)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(OH)","loc":"e,80:15,80:16", + {"type":"RANGE","name":"","addr":"(OH)","loc":"e,78:14,78:15", "leftp": [ - {"type":"CONST","name":"?32?sh1f","addr":"(PH)","loc":"e,80:16,80:18","dtypep":"(DB)"} + {"type":"CONST","name":"?32?sh1f","addr":"(PH)","loc":"e,78:15,78:17","dtypep":"(DB)"} ], "rightp": [ - {"type":"CONST","name":"?32?sh0","addr":"(QH)","loc":"e,80:19,80:20","dtypep":"(N)"} + {"type":"CONST","name":"?32?sh0","addr":"(QH)","loc":"e,78:18,78:19","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(RH)","loc":"e,82:4,82:10","keyword":"always","sentreep": [], + {"type":"ALWAYS","name":"","addr":"(RH)","loc":"e,80:3,80:9","keyword":"always","sentreep": [], "stmtsp": [ - {"type":"EVENTCONTROL","name":"","addr":"(SH)","loc":"e,82:11,82:12", + {"type":"EVENTCONTROL","name":"","addr":"(SH)","loc":"e,80:10,80:11", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(TH)","loc":"e,82:11,82:12", + {"type":"SENTREE","name":"","addr":"(TH)","loc":"e,80:10,80:11", "sensesp": [ - {"type":"SENITEM","name":"","addr":"(UH)","loc":"e,82:13,82:20","edgeType":"POS", + {"type":"SENITEM","name":"","addr":"(UH)","loc":"e,80:12,80:19","edgeType":"POS", "sensp": [ - {"type":"PARSEREF","name":"clk","addr":"(VH)","loc":"e,82:21,82:24","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"clk","addr":"(VH)","loc":"e,80:20,80:23","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"condp": []} ]} ], "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(WH)","loc":"e,82:26,82:31","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(WH)","loc":"e,80:25,80:30","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"ASSIGNDLY","name":"","addr":"(XH)","loc":"e,83:11,83:13","dtypep":"UNLINKED", + {"type":"ASSIGNDLY","name":"","addr":"(XH)","loc":"e,81:10,81:12","dtypep":"UNLINKED", "rhsp": [ - {"type":"PARSEREF","name":"in","addr":"(YH)","loc":"e,83:14,83:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"in","addr":"(YH)","loc":"e,81:13,81:15","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "lhsp": [ - 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{"type":"BEGIN","name":"cover_concurrent_stmt","addr":"(KR)","loc":"e,141:4,141:25","implied":true,"declsp": [], + {"type":"BEGIN","name":"cover_concurrent_stmt","addr":"(KR)","loc":"e,139:3,139:24","implied":true,"declsp": [], "stmtsp": [ - {"type":"COVER","name":"","addr":"(LR)","loc":"e,141:27,141:32","type":"[CONCURRENT]", + {"type":"COVER","name":"","addr":"(LR)","loc":"e,139:26,139:31","type":"[CONCURRENT]", "propp": [ - {"type":"PROPSPEC","name":"","addr":"(MR)","loc":"e,141:42,141:46","dtypep":"UNLINKED","sensesp": [],"disablep": [], + {"type":"PROPSPEC","name":"","addr":"(MR)","loc":"e,139:41,139:45","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ - {"type":"PARSEREF","name":"prop","addr":"(NR)","loc":"e,141:42,141:46","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"prop","addr":"(NR)","loc":"e,139:41,139:45","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"sentreep": [],"coverincsp": [], "passsp": [ - {"type":"DISPLAY","name":"","addr":"(OR)","loc":"e,141:48,141:56", + {"type":"DISPLAY","name":"","addr":"(OR)","loc":"e,139:47,139:55", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(PR)","loc":"e,141:48,141:56","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(PR)","loc":"e,139:47,139:55","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"32'h70617373","addr":"(QR)","loc":"e,141:57,141:63","dtypep":"(QC)"} + {"type":"CONST","name":"32'h70617373","addr":"(QR)","loc":"e,139:56,139:62","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, - {"type":"RESTRICT","name":"","addr":"(RR)","loc":"e,143:4,143:12","type":"[INTERNAL]","immediate":true, + {"type":"RESTRICT","name":"","addr":"(RR)","loc":"e,141:3,141:11","type":"[INTERNAL]","immediate":true, "propp": [ - {"type":"PROPSPEC","name":"","addr":"(SR)","loc":"e,143:23,143:27","dtypep":"UNLINKED","sensesp": [],"disablep": [], + {"type":"PROPSPEC","name":"","addr":"(SR)","loc":"e,141:22,141:26","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ - {"type":"PARSEREF","name":"prop","addr":"(TR)","loc":"e,143:23,143:27","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"prop","addr":"(TR)","loc":"e,141:22,141:26","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"sentreep": [],"passsp": []}, - {"type":"ALWAYS","name":"","addr":"(UR)","loc":"e,145:4,145:13","keyword":"always_ff","sentreep": [], + {"type":"ALWAYS","name":"","addr":"(UR)","loc":"e,143:3,143:12","keyword":"always_ff","sentreep": [], "stmtsp": [ - {"type":"EVENTCONTROL","name":"","addr":"(VR)","loc":"e,145:14,145:15", + {"type":"EVENTCONTROL","name":"","addr":"(VR)","loc":"e,143:13,143:14", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(WR)","loc":"e,145:14,145:15", + {"type":"SENTREE","name":"","addr":"(WR)","loc":"e,143:13,143:14", "sensesp": [ - {"type":"SENITEM","name":"","addr":"(XR)","loc":"e,145:16,145:23","edgeType":"POS", + {"type":"SENITEM","name":"","addr":"(XR)","loc":"e,143:15,143:22","edgeType":"POS", "sensp": [ - {"type":"PARSEREF","name":"clk","addr":"(YR)","loc":"e,145:24,145:27","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"clk","addr":"(YR)","loc":"e,143:23,143:26","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"condp": []} ]} ], "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(ZR)","loc":"e,145:29,145:34","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(ZR)","loc":"e,143:28,143:33","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"CASE","name":"","addr":"(AS)","loc":"e,146:14,146:19","kwd":"casez","unique0":true, + {"type":"CASE","name":"","addr":"(AS)","loc":"e,144:13,144:18","kwd":"casez","unique0":true, "exprp": [ - {"type":"PARSEREF","name":"in","addr":"(BS)","loc":"e,146:20,146:22","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"in","addr":"(BS)","loc":"e,144:19,144:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "itemsp": [ - {"type":"CASEITEM","name":"","addr":"(CS)","loc":"e,147:9,147:10", + {"type":"CASEITEM","name":"","addr":"(CS)","loc":"e,145:8,145:9", "condsp": [ - {"type":"CONST","name":"?32?sh1","addr":"(DS)","loc":"e,147:8,147:9","dtypep":"(N)"} + {"type":"CONST","name":"?32?sh1","addr":"(DS)","loc":"e,145:7,145:8","dtypep":"(N)"} ], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(ES)","loc":"e,147:11,147:19", + {"type":"DISPLAY","name":"","addr":"(ES)","loc":"e,145:10,145:18", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(FS)","loc":"e,147:11,147:19","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(FS)","loc":"e,145:10,145:18","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"16'h3161","addr":"(GS)","loc":"e,147:20,147:24","dtypep":"(HS)"} + {"type":"CONST","name":"16'h3161","addr":"(GS)","loc":"e,145:19,145:23","dtypep":"(HS)"} ],"scopeNamep": []} ],"filep": []} ]}, - {"type":"CASEITEM","name":"","addr":"(IS)","loc":"e,148:8,148:15","condsp": [], + {"type":"CASEITEM","name":"","addr":"(IS)","loc":"e,146:7,146:14","condsp": [], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(JS)","loc":"e,148:17,148:25", + {"type":"DISPLAY","name":"","addr":"(JS)","loc":"e,146:16,146:24", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(KS)","loc":"e,148:17,148:25","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(KS)","loc":"e,146:16,146:24","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"16'h3162","addr":"(LS)","loc":"e,148:26,148:30","dtypep":"(HS)"} + {"type":"CONST","name":"16'h3162","addr":"(LS)","loc":"e,146:25,146:29","dtypep":"(HS)"} ],"scopeNamep": []} ],"filep": []} ]} ],"notParallelp": []}, - {"type":"CASE","name":"","addr":"(MS)","loc":"e,150:15,150:20","kwd":"casez","priority":true, + {"type":"CASE","name":"","addr":"(MS)","loc":"e,148:14,148:19","kwd":"casez","priority":true, "exprp": [ - {"type":"CONST","name":"1'h1","addr":"(NS)","loc":"e,150:21,150:25","dtypep":"(YE)"} + {"type":"CONST","name":"1'h1","addr":"(NS)","loc":"e,148:20,148:24","dtypep":"(YE)"} ], "itemsp": [ - {"type":"CASEITEM","name":"","addr":"(OS)","loc":"e,151:13,151:14", + {"type":"CASEITEM","name":"","addr":"(OS)","loc":"e,149:12,149:13", "condsp": [ - {"type":"SELBIT","name":"","addr":"(PS)","loc":"e,151:10,151:11","dtypep":"UNLINKED", + {"type":"SELBIT","name":"","addr":"(PS)","loc":"e,149:9,149:10","dtypep":"UNLINKED", "fromp": [ - {"type":"PARSEREF","name":"in","addr":"(QS)","loc":"e,151:8,151:10","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"in","addr":"(QS)","loc":"e,149:7,149:9","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ - {"type":"CONST","name":"?32?sh0","addr":"(RS)","loc":"e,151:11,151:12","dtypep":"(N)"} + {"type":"CONST","name":"?32?sh0","addr":"(RS)","loc":"e,149:10,149:11","dtypep":"(N)"} ],"thsp": [],"attrp": []} ], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(SS)","loc":"e,151:15,151:23", + {"type":"DISPLAY","name":"","addr":"(SS)","loc":"e,149:14,149:22", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(TS)","loc":"e,151:15,151:23","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(TS)","loc":"e,149:14,149:22","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"16'h3261","addr":"(US)","loc":"e,151:24,151:28","dtypep":"(HS)"} + {"type":"CONST","name":"16'h3261","addr":"(US)","loc":"e,149:23,149:27","dtypep":"(HS)"} ],"scopeNamep": []} ],"filep": []} ]}, - {"type":"CASEITEM","name":"","addr":"(VS)","loc":"e,152:8,152:15","condsp": [], + {"type":"CASEITEM","name":"","addr":"(VS)","loc":"e,150:7,150:14","condsp": [], "stmtsp": [ - {"type":"DISPLAY","name":"","addr":"(WS)","loc":"e,152:17,152:25", + {"type":"DISPLAY","name":"","addr":"(WS)","loc":"e,150:16,150:24", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(XS)","loc":"e,152:17,152:25","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(XS)","loc":"e,150:16,150:24","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"16'h3262","addr":"(YS)","loc":"e,152:26,152:30","dtypep":"(HS)"} + {"type":"CONST","name":"16'h3262","addr":"(YS)","loc":"e,150:25,150:29","dtypep":"(HS)"} ],"scopeNamep": []} ],"filep": []} ]} @@ -2309,17 +2309,17 @@ {"type":"BASICDTYPE","name":"logic","addr":"(SBB)","loc":"d,136:16,136:17","dtypep":"(SBB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GDB)","loc":"d,169:14,169:53","dtypep":"(GDB)","keyword":"logic","range":"295:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,169:7,169:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,33:26,33:31","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(NC)","loc":"e,33:25,33:26","dtypep":"(NC)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(EF)","loc":"e,45:17,45:38","dtypep":"(EF)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,54:17,54:49","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,54:51,54:56","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,59:17,59:41","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(HS)","loc":"e,147:20,147:24","dtypep":"(HS)","keyword":"logic","range":"15:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,12:8,12:10","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,16:9,16:11","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,31:25,31:30","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(NC)","loc":"e,31:24,31:25","dtypep":"(NC)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(EF)","loc":"e,43:16,43:37","dtypep":"(EF)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,46:21,46:23","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,49:21,49:23","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,52:16,52:48","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,52:50,52:55","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,57:16,57:40","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(HS)","loc":"e,145:19,145:23","dtypep":"(HS)","keyword":"logic","range":"15:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v index caf299693..308f83ffa 100644 --- a/test_regress/t/t_dynarray.v +++ b/test_regress/t/t_dynarray.v @@ -4,163 +4,163 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - // verilator lint_off UNUSED - integer unused[]; - // verilator lint_on UNUSED + // verilator lint_off UNUSED + integer unused[]; + // verilator lint_on UNUSED - typedef bit [7:0] byte_t; - byte_t a[]; - byte_t b[]; + typedef bit [7:0] byte_t; + byte_t a[]; + byte_t b[]; // wide data array - typedef struct packed { - logic [15:0] header; - logic [223:0] payload; - logic [15:0] checksum; - } pck256_t; + typedef struct packed { + logic [15:0] header; + logic [223:0] payload; + logic [15:0] checksum; + } pck256_t; - pck256_t p256[]; + pck256_t p256[]; - string s[] = { "hello", "sad", "world" }; + string s[] = {"hello", "sad", "world"}; - always @ (posedge clk) begin - cyc <= cyc + 1; - begin - `checkh(a.size, 0); - `checkp(a, "'{}"); + always @(posedge clk) begin + cyc <= cyc + 1; + begin + `checkh(a.size, 0); + `checkp(a, "'{}"); - `checkh(s.size, 3); - `checks(s[0], "hello"); - `checks(s[1], "sad"); - `checks(s[2], "world"); + `checkh(s.size, 3); + `checks(s[0], "hello"); + `checks(s[1], "sad"); + `checks(s[2], "world"); - a = new [3]; - `checkh(a.size, 3); - a[0] = 10; - a[1] = 11; - a[2] = 12; - `checkh(a[0], 10); - `checkh(a[1], 11); - `checkh(a[2], 12); - `checkp(a, "'{'ha, 'hb, 'hc}"); - a.delete; - `checkh(a.size, 0); + a = new[3]; + `checkh(a.size, 3); + a[0] = 10; + a[1] = 11; + a[2] = 12; + `checkh(a[0], 10); + `checkh(a[1], 11); + `checkh(a[2], 12); + `checkp(a, "'{'ha, 'hb, 'hc}"); + a.delete; + `checkh(a.size, 0); - a = '{15, 16}; - `checkh(a.size, 2); - `checkh(a[0], 15); - `checkh(a[1], 16) + a = '{15, 16}; + `checkh(a.size, 2); + `checkh(a[0], 15); + `checkh(a[1], 16) - a = {17, 18}; - `checkh(a.size, 2); - `checkh(a[0], 17); - `checkh(a[1], 18) + a = {17, 18}; + `checkh(a.size, 2); + `checkh(a[0], 17); + `checkh(a[1], 18) - a = '{17}; - `checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern - `checkh(a[0], 17); + a = '{17}; + `checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern + `checkh(a[0], 17); - a = new[2]; - a[0] = 5; - a[1] = 6; - `checkh(a[0], 5); - `checkh(a[1], 6); - a = new[2]; - a[0] = 0; - a[1] = 0; - `checkh(a[0], 0); - `checkh(a[1], 0); + a = new[2]; + a[0] = 5; + a[1] = 6; + `checkh(a[0], 5); + `checkh(a[1], 6); + a = new[2]; + a[0] = 0; + a[1] = 0; + `checkh(a[0], 0); + `checkh(a[1], 0); - a[0] = 5; - a[1] = 6; - `checkh(a[0], 5); - `checkh(a[1], 6); + a[0] = 5; + a[1] = 6; + `checkh(a[0], 5); + `checkh(a[1], 6); - b = new [4](a); - `checkh(b.size, 4); - `checkh(b[0], 5); - `checkh(b[1], 6); - b[2] = 0; - b[3] = 0; - `checkh(b[2], 0); - `checkh(b[3], 0); + b = new[4] (a); + `checkh(b.size, 4); + `checkh(b[0], 5); + `checkh(b[1], 6); + b[2] = 0; + b[3] = 0; + `checkh(b[2], 0); + `checkh(b[3], 0); - a = b; - `checkh(a.size, 4); - `checkh(a[0], 5); - `checkh(a[1], 6); - `checkh(a[2], 0); - `checkh(a[3], 0); + a = b; + `checkh(a.size, 4); + `checkh(a[0], 5); + `checkh(a[1], 6); + `checkh(a[2], 0); + `checkh(a[3], 0); - a = new [0]; - `checkh(a.size, 0); - b = new [4](a); - `checkh(b.size, 4); - b[0] = 0; - b[1] = 0; - b[2] = 0; - b[3] = 0; - `checkh(b[0], 0); - `checkh(b[1], 0); - `checkh(b[2], 0); - `checkh(b[3], 0); + a = new[0]; + `checkh(a.size, 0); + b = new[4] (a); + `checkh(b.size, 4); + b[0] = 0; + b[1] = 0; + b[2] = 0; + b[3] = 0; + `checkh(b[0], 0); + `checkh(b[1], 0); + `checkh(b[2], 0); + `checkh(b[3], 0); - a = new[4] ('{8'd1,8'd2,8'd3,8'd4}); - `checkh(a.size, 4); - `checkh(a[0], 1); - `checkh(a[1], 2); - `checkh(a[2], 3); - `checkh(a[3], 4); + a = new[4] ('{8'd1, 8'd2, 8'd3, 8'd4}); + `checkh(a.size, 4); + `checkh(a[0], 1); + `checkh(a[1], 2); + `checkh(a[2], 3); + `checkh(a[3], 4); - i = 0; - foreach (a[j]) i += int'(a[j]); - `checkh(i, 1 + 2 + 3 + 4); + i = 0; + foreach (a[j]) i += int'(a[j]); + `checkh(i, 1 + 2 + 3 + 4); - // test wide dynamic array - p256 = new [11]; - `checkh(p256.size, 11); - `checkh(p256.size(), 11); + // test wide dynamic array + p256 = new[11]; + `checkh(p256.size, 11); + `checkh(p256.size(), 11); - p256[1].header = 16'hcafe; - p256[1].payload = {14{16'hbabe}}; - p256[1].checksum = 16'hdead; - `checkh(p256[1].header, 16'hcafe); - `checkh(p256[1], {16'hcafe,{14{16'hbabe}},16'hdead}); + p256[1].header = 16'hcafe; + p256[1].payload = {14{16'hbabe}}; + p256[1].checksum = 16'hdead; + `checkh(p256[1].header, 16'hcafe); + `checkh(p256[1], {16'hcafe, {14{16'hbabe}}, 16'hdead}); - //X's: `checkh(p256[0], 'x); + //X's: `checkh(p256[0], 'x); - p256[5] = '1; - `checkh(p256[5], {32{8'hff}}); + p256[5] = '1; + `checkh(p256[5], {32{8'hff}}); - p256[5].header = 16'h2; - `checkh(p256[5], {16'h2,{30{8'hff}}}); + p256[5].header = 16'h2; + `checkh(p256[5], {16'h2, {30{8'hff}}}); - p256[2] = ( p256[5].header == 2 ) ? p256[1] : p256[5]; - `checkh(p256[2], {16'hcafe,{14{16'hbabe}},16'hdead}); + p256[2] = (p256[5].header == 2) ? p256[1] : p256[5]; + `checkh(p256[2], {16'hcafe, {14{16'hbabe}}, 16'hdead}); - p256.delete(); - `checkh(p256.size, 0); + p256.delete(); + `checkh(p256.size, 0); - end + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_bad.out b/test_regress/t/t_dynarray_bad.out index 12748e014..7540a4007 100644 --- a/test_regress/t/t_dynarray_bad.out +++ b/test_regress/t/t_dynarray_bad.out @@ -1,10 +1,10 @@ -%Warning-WIDTHTRUNC: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. - : ... note: In instance 't' - 15 | a = new [s]; - | ^~~ +%Warning-WIDTHTRUNC: t/t_dynarray_bad.v:15:9: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. + : ... note: In instance 't' + 15 | a = new[s]; + | ^~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" - 15 | a = new [s]; - | ^ +%Error: Internal Error: t/t_dynarray_bad.v:15:13: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" + 15 | a = new[s]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_dynarray_bad.v b/test_regress/t/t_dynarray_bad.v index 462ec0697..ad512fc8a 100644 --- a/test_regress/t/t_dynarray_bad.v +++ b/test_regress/t/t_dynarray_bad.v @@ -6,13 +6,13 @@ module t; - integer a[]; + integer a[]; - string s; + string s; - initial begin - s = "str"; - a = new [s]; // Bad - end + initial begin + s = "str"; + a = new[s]; // Bad + end endmodule diff --git a/test_regress/t/t_dynarray_bits.out b/test_regress/t/t_dynarray_bits.out index d01da57a9..64c91f12f 100644 --- a/test_regress/t/t_dynarray_bits.out +++ b/test_regress/t/t_dynarray_bits.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_dynarray_bits.v:12:11: Unsupported: $bits for dynamic array - : ... note: In instance 't' - 12 | if ($bits(a) != 0) $stop; - | ^~~~~ +%Error-UNSUPPORTED: t/t_dynarray_bits.v:12:9: Unsupported: $bits for dynamic array + : ... note: In instance 't' + 12 | if ($bits(a) != 0) $stop; + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Internal Error: t/t_dynarray_bits.v:12:11: ../V3Width.cpp:#: Node has no type - : ... note: In instance 't' - 12 | if ($bits(a) != 0) $stop; - | ^~~~~ +%Error: Internal Error: t/t_dynarray_bits.v:12:9: ../V3Width.cpp:#: Node has no type + : ... note: In instance 't' + 12 | if ($bits(a) != 0) $stop; + | ^~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_dynarray_bits.v b/test_regress/t/t_dynarray_bits.v index d9d8ad9f8..9b174316a 100644 --- a/test_regress/t/t_dynarray_bits.v +++ b/test_regress/t/t_dynarray_bits.v @@ -6,12 +6,12 @@ module t; - integer a[]; + integer a[]; - initial begin - if ($bits(a) != 0) $stop; - a = new [10]; - if ($bits(a) != 10*32) $stop; - end + initial begin + if ($bits(a) != 0) $stop; + a = new[10]; + if ($bits(a) != 10 * 32) $stop; + end endmodule diff --git a/test_regress/t/t_dynarray_cast_write.v b/test_regress/t/t_dynarray_cast_write.v index b7e69e509..c02c75ee6 100644 --- a/test_regress/t/t_dynarray_cast_write.v +++ b/test_regress/t/t_dynarray_cast_write.v @@ -5,35 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 class Foo; - int x = 1; + int x = 1; endclass class Bar extends Foo; - function new; - x = 2; - endfunction + function new; + x = 2; + endfunction endclass module t; - initial begin - automatic int sel_bit = 3; - automatic Bar bar = new; - automatic Foo foo = bar; - automatic Bar bars[] = new[4]; - $cast(bars[0], foo); - if (bars[0].x != 2) $stop; + initial begin + automatic int sel_bit = 3; + automatic Bar bar = new; + automatic Foo foo = bar; + automatic Bar bars[] = new[4]; + $cast(bars[0], foo); + if (bars[0].x != 2) $stop; - $cast(bars[sel_bit[0]], foo); - if (bars[1].x != 2) $stop; + $cast(bars[sel_bit[0]], foo); + if (bars[1].x != 2) $stop; - $cast(bars[bars[0].x], foo); - if (bars[2].x != 2) $stop; + $cast(bars[bars[0].x], foo); + if (bars[2].x != 2) $stop; - $cast(bars[sel_bit[1:0]], foo); - if (bars[3].x != 2) $stop; + $cast(bars[sel_bit[1:0]], foo); + if (bars[3].x != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_concat.v b/test_regress/t/t_dynarray_concat.v index 3333de4b3..49f22cd3c 100644 --- a/test_regress/t/t_dynarray_concat.v +++ b/test_regress/t/t_dynarray_concat.v @@ -4,62 +4,64 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef VERILATOR `define stop $stop `else `define stop `endif `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - int da[][2] = '{}; - int da2[][2] = '{'{1, 2}}; + int da[][2] = '{}; + int da2[][2] = '{'{1, 2}}; - int dd[][] = '{}; - int dd1[][] = '{'{1}}; - int dd2[][] = '{'{1, 2}}; + int dd[][] = '{}; + int dd1[][] = '{'{1}}; + int dd2[][] = '{'{1, 2}}; - int dq[][$] = '{}; - int dq1[][$] = '{'{1}}; - int dq2[][$] = '{'{1, 2}}; + int dq[][$] = '{}; + int dq1[][$] = '{'{1}}; + int dq2[][$] = '{'{1, 2}}; - int qa[$][2] = '{}; - int qa2[$][2] = '{'{1, 2}}; + int qa[$][2] = '{}; + int qa2[$][2] = '{'{1, 2}}; - int qd[$][] = '{}; - int qd1[$][] = '{'{1}}; - int qd2[$][] = '{'{1, 2}}; + int qd[$][] = '{}; + int qd1[$][] = '{'{1}}; + int qd2[$][] = '{'{1, 2}}; - int qq[$][$] = '{}; - int qq1[$][$] = '{'{1}}; - int qq2[$][$] = '{'{1, 2}}; + int qq[$][$] = '{}; + int qq1[$][$] = '{'{1}}; + int qq2[$][$] = '{'{1, 2}}; - initial begin - `checkp(da, "'{}"); - `checkp(da2, "'{'{'h1, 'h2}}"); + initial begin + `checkp(da, "'{}"); + `checkp(da2, "'{'{'h1, 'h2}}"); - `checkp(dd, "'{}"); - `checkp(dd1, "'{'{'h1}}"); - `checkp(dd2, "'{'{'h1, 'h2}}"); + `checkp(dd, "'{}"); + `checkp(dd1, "'{'{'h1}}"); + `checkp(dd2, "'{'{'h1, 'h2}}"); - `checkp(dq, "'{}"); - `checkp(dq1, "'{'{'h1}}"); - `checkp(dq2, "'{'{'h1, 'h2}}"); + `checkp(dq, "'{}"); + `checkp(dq1, "'{'{'h1}}"); + `checkp(dq2, "'{'{'h1, 'h2}}"); - `checkp(qa, "'{}"); - `checkp(qa2, "'{'{'h1, 'h2}}"); + `checkp(qa, "'{}"); + `checkp(qa2, "'{'{'h1, 'h2}}"); - `checkp(qd, "'{}"); - `checkp(qd1, "'{'{'h1}}"); - `checkp(qd2, "'{'{'h1, 'h2}}"); + `checkp(qd, "'{}"); + `checkp(qd1, "'{'{'h1}}"); + `checkp(qd2, "'{'{'h1, 'h2}}"); - `checkp(qq, "'{}"); - `checkp(qq1, "'{'{'h1}}"); - `checkp(qq2, "'{'{'h1, 'h2}}"); + `checkp(qq, "'{}"); + `checkp(qq1, "'{'{'h1}}"); + `checkp(qq2, "'{'{'h1, 'h2}}"); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_init.v b/test_regress/t/t_dynarray_init.v index 9f5439cc9..abc9aafdb 100644 --- a/test_regress/t/t_dynarray_init.v +++ b/test_regress/t/t_dynarray_init.v @@ -4,36 +4,38 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - int a1[] = '{12, 13}; - int a2[] = {14, 15}; - int a3[] = '{16}; - int a4[] = {17}; - int a5[] = {}; + int a1[] = '{12, 13}; + int a2[] = {14, 15}; + int a3[] = '{16}; + int a4[] = {17}; + int a5[] = {}; - initial begin - `checkh(a1.size, 2); - `checkh(a1[0], 12); - `checkh(a1[1], 13); + initial begin + `checkh(a1.size, 2); + `checkh(a1[0], 12); + `checkh(a1[1], 13); - `checkh(a2.size, 2); - `checkh(a2[0], 14); - `checkh(a2[1], 15); + `checkh(a2.size, 2); + `checkh(a2[0], 14); + `checkh(a2[1], 15); - `checkh(a3.size, 1); - `checkh(a3[0], 16); + `checkh(a3.size, 1); + `checkh(a3[0], 16); - `checkh(a4.size, 1); - `checkh(a4[0], 17); + `checkh(a4.size, 1); + `checkh(a4[0], 17); - `checkh(a5.size, 0); + `checkh(a5.size, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_method.v b/test_regress/t/t_dynarray_method.v index 095d9c2fe..ef21fc6ad 100644 --- a/test_regress/t/t_dynarray_method.v +++ b/test_regress/t/t_dynarray_method.v @@ -4,171 +4,178 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - string s[] = { "hello", "sad", "sad", "world" }; + string s[] = {"hello", "sad", "sad", "world"}; - initial begin - int d[]; - int de[]; // Empty - int qv[$]; // Value returns - int qvunused[$]; // Value returns (unused) - int qi[$]; // Index returns - int i; + initial begin + int d[]; + int de[]; // Empty + int qv[$]; // Value returns + int qvunused[$]; // Value returns (unused) + int qi[$]; // Index returns + int i; - d = '{1, 2, 2, 4, 3}; - `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); - d = {1, 2, 2, 4, 3}; - `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); + d = '{1, 2, 2, 4, 3}; + `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); + d = {1, 2, 2, 4, 3}; + `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); - // sort/rsort with clause is the field to use for the sorting - d.sort; - `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - d.sort with (10 - item); - `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - d.sort(x) with (10 - x); - `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - de.sort(x) with (10 - x); - `checkp(de, "'{}"); - d.rsort; - `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - d.rsort with (10 - item); - `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - de.rsort(x) with (10 - x); - `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + // sort/rsort with clause is the field to use for the sorting + d.sort; + `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + d.sort with (10 - item); + `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + d.sort(x) with (10 - x); + `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + de.sort(x) with (10 - x); + `checkp(de, "'{}"); + d.rsort; + `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + d.rsort with (10 - item); + `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + de.rsort(x) with (10 - x); + `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - d = '{2, 2, 4, 1, 3}; - qv = d.unique; - `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); - qv = de.unique; - `checkh(qv.size(), 0); - qi = d.unique_index; qv.sort; - `checkp(qi, "'{'h0, 'h2, 'h3, 'h4}"); - qi = de.unique_index; - `checkh(qi.size(), 0); + d = '{2, 2, 4, 1, 3}; + qv = d.unique; + `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); + qv = de.unique; + `checkh(qv.size(), 0); + qi = d.unique_index; + qv.sort; + `checkp(qi, "'{'h0, 'h2, 'h3, 'h4}"); + qi = de.unique_index; + `checkh(qi.size(), 0); - d.reverse; - `checkp(d, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); - de.reverse; - `checkh(de.size(), 0); - d.shuffle(); d.sort; - `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - de.shuffle(); - `checkh(de.size(), 0); + d.reverse; + `checkp(d, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); + de.reverse; + `checkh(de.size(), 0); + d.shuffle(); + d.sort; + `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + de.shuffle(); + `checkh(de.size(), 0); - // These require an with clause or are illegal - // TODO add a lint check that with clause is provided - qv = d.find with (item == 2); - `checkp(qv, "'{'h2, 'h2}"); - qv = d.find_first with (item == 2); - `checkp(qv, "'{'h2}"); - qv = d.find_last with (item == 2); - `checkp(qv, "'{'h2}"); + // These require an with clause or are illegal + // TODO add a lint check that with clause is provided + qv = d.find with (item == 2); + `checkp(qv, "'{'h2, 'h2}"); + qv = d.find_first with (item == 2); + `checkp(qv, "'{'h2}"); + qv = d.find_last with (item == 2); + `checkp(qv, "'{'h2}"); - qv = d.find with (item == 20); - `checkh(qv.size, 0); - qv = d.find_first with (item == 20); - `checkh(qv.size, 0); - qv = d.find_last with (item == 20); - `checkh(qv.size, 0); + qv = d.find with (item == 20); + `checkh(qv.size, 0); + qv = d.find_first with (item == 20); + `checkh(qv.size, 0); + qv = d.find_last with (item == 20); + `checkh(qv.size, 0); - // Check gate eater with Lambda variable removal - qvunused = d.find with (item == 20); + // Check gate eater with Lambda variable removal + qvunused = d.find with (item == 20); - qi = d.find_index with (item == 2); - qi.sort; `checkp(qi, "'{'h1, 'h2}"); - qi = d.find_first_index with (item == 2); - `checkp(qi, "'{'h1}"); - qi = d.find_last_index with (item == 2); - `checkp(qi, "'{'h2}"); + qi = d.find_index with (item == 2); + qi.sort; + `checkp(qi, "'{'h1, 'h2}"); + qi = d.find_first_index with (item == 2); + `checkp(qi, "'{'h1}"); + qi = d.find_last_index with (item == 2); + `checkp(qi, "'{'h2}"); - i = 2; - qi = d.find_index with (item == i); - qi.sort; `checkp(qi, "'{'h1, 'h2}"); + i = 2; + qi = d.find_index with (item == i); + qi.sort; + `checkp(qi, "'{'h1, 'h2}"); - qi = d.find_index with (item == 20); qi.sort; - `checkh(qi.size, 0); - qi = d.find_first_index with (item == 20); - `checkh(qi.size, 0); - qi = d.find_last_index with (item == 20); - `checkh(qi.size, 0); + qi = d.find_index with (item == 20); + qi.sort; + `checkh(qi.size, 0); + qi = d.find_first_index with (item == 20); + `checkh(qi.size, 0); + qi = d.find_last_index with (item == 20); + `checkh(qi.size, 0); - qi = d.find_index with (item.index == 2); - `checkp(qi, "'{'h2}"); + qi = d.find_index with (item.index == 2); + `checkp(qi, "'{'h2}"); - qv = d.min; - `checkp(qv, "'{'h1}"); - qv = d.max; - `checkp(qv, "'{'h4}"); - qv = de.min; - `checkp(qv, "'{}"); - qv = de.max; - `checkp(qv, "'{}"); + qv = d.min; + `checkp(qv, "'{'h1}"); + qv = d.max; + `checkp(qv, "'{'h4}"); + qv = de.min; + `checkp(qv, "'{}"); + qv = de.max; + `checkp(qv, "'{}"); - // Reduction methods - i = d.sum; - `checkh(i, 32'hc); - i = d.sum with (item + 1); - `checkh(i, 32'h11); - i = d.sum(myi) with (myi + 1); - `checkh(i, 32'h11); - i = d.sum with (1); // unused 'index' - `checkh(i, 32'h5); - i = d.sum(unused) with (1); // unused 'unused' - `checkh(i, 32'h5); + // Reduction methods + i = d.sum; + `checkh(i, 32'hc); + i = d.sum with (item + 1); + `checkh(i, 32'h11); + i = d.sum(myi) with (myi + 1); + `checkh(i, 32'h11); + i = d.sum with (1); // unused 'index' + `checkh(i, 32'h5); + i = d.sum(unused) with (1); // unused 'unused' + `checkh(i, 32'h5); - i = d.product; - `checkh(i, 32'h30); - i = d.product with (item + 1); - `checkh(i, 32'h168); + i = d.product; + `checkh(i, 32'h30); + i = d.product with (item + 1); + `checkh(i, 32'h168); - i = de.sum; - `checkh(i, 32'h0); + i = de.sum; + `checkh(i, 32'h0); - i = de.product; - `checkh(i, 32'h0); + i = de.product; + `checkh(i, 32'h0); - d = '{32'b1100, 32'b1010}; + d = '{32'b1100, 32'b1010}; - i = d.and; - `checkh(i, 32'b1000); - i = d.and with (item + 1); - `checkh(i, 32'b1001); - i = d.or; - `checkh(i, 32'b1110); - i = d.or with (item + 1); - `checkh(i, 32'b1111); - i = d.xor; - `checkh(i, 32'b0110); - i = d.xor with (item + 1); - `checkh(i, 32'b0110); + i = d.and; + `checkh(i, 32'b1000); + i = d.and with (item + 1); + `checkh(i, 32'b1001); + i = d.or; + `checkh(i, 32'b1110); + i = d.or with (item + 1); + `checkh(i, 32'b1111); + i = d.xor; + `checkh(i, 32'b0110); + i = d.xor with (item + 1); + `checkh(i, 32'b0110); - i = de.and; - `checkh(i, 32'b0); - i = de.or; - `checkh(i, 32'b0); - i = de.xor; - `checkh(i, 32'b0); + i = de.and; + `checkh(i, 32'b0); + i = de.or; + `checkh(i, 32'b0); + i = de.xor; + `checkh(i, 32'b0); - `checks(s[1], "sad"); - qi = s.find_first_index with (item == "sad"); - `checkh(qi.size, 1); - `checkh(qi[0], 1); - qi = s.find_last_index with (item == "sad"); - `checkh(qi.size, 1); - `checkh(qi[0], 2); + `checks(s[1], "sad"); + qi = s.find_first_index with (item == "sad"); + `checkh(qi.size, 1); + `checkh(qi[0], 1); + qi = s.find_last_index with (item == "sad"); + `checkh(qi.size, 1); + `checkh(qi[0], 2); - d = '{1, 2}; - de = '{1, 2}; - `checkh(d == de, 1'b1); - `checkh(d != de, 1'b0); + d = '{1, 2}; + de = '{1, 2}; + `checkh(d == de, 1'b1); + `checkh(d != de, 1'b0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_method_bad.out b/test_regress/t/t_dynarray_method_bad.out index 0e0721a68..0bea5d59c 100644 --- a/test_regress/t/t_dynarray_method_bad.out +++ b/test_regress/t/t_dynarray_method_bad.out @@ -1,36 +1,36 @@ -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:19:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:21:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' - 19 | i = s.sum with (item.len); - | ^ + 21 | i = s.sum with (item.len); + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:21:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:23:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' - 21 | i = s.product with (item.len); - | ^ -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:23:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. + 23 | i = s.product with (item.len); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:25:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' - 23 | b = s.sum with (item == "hello"); - | ^ -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:25:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. + 25 | b = s.sum with (item == "hello"); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:27:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' - 25 | b = s.sum with (item == ""); - | ^ -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:27:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. + 27 | b = s.sum with (item == ""); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:29:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' - 27 | b = s.product with (item inside {"hello", "sad"}); - | ^ -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:29:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. + 29 | b = s.product with (item inside {"hello", "sad"}); + | ^ +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:31:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' - 29 | b = s.product with (item inside { "hello", "sad", "world" }); - | ^ -%Error-UNSUPPORTED: t/t_dynarray_method_bad.v:32:13: Unsupported/unknown built-in dynamic array method 'unknown_bad' + 31 | b = s.product with (item inside {"hello", "sad", "world"}); + | ^ +%Error-UNSUPPORTED: t/t_dynarray_method_bad.v:34:11: Unsupported/unknown built-in dynamic array method 'unknown_bad' : ... note: In instance 't' - 32 | b = s.unknown_bad; - | ^~~~~~~~~~~ + 34 | b = s.unknown_bad; + | ^~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:32:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's METHODCALL 'unknown_bad' generates 64 bits. +%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:34:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's METHODCALL 'unknown_bad' generates 64 bits. : ... note: In instance 't' - 32 | b = s.unknown_bad; - | ^ + 34 | b = s.unknown_bad; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_dynarray_method_bad.v b/test_regress/t/t_dynarray_method_bad.v index 4a0d82e41..abecc8c88 100644 --- a/test_regress/t/t_dynarray_method_bad.v +++ b/test_regress/t/t_dynarray_method_bad.v @@ -4,34 +4,36 @@ // SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - string s[] = { "hello", "sad", "sad", "world" }; + string s[] = {"hello", "sad", "sad", "world"}; - initial begin - int i; - bit b; + initial begin + int i; + bit b; - i = s.sum with (item.len); - `checkh(i, 10); - i = s.product with (item.len); - `checkh(i, 24); - b = s.sum with (item == "hello"); - `checkh(b, 1'b1); - b = s.sum with (item == ""); - `checkh(b, 1'b0); - b = s.product with (item inside {"hello", "sad"}); - `checkh(b, 1'b0); - b = s.product with (item inside { "hello", "sad", "world" }); - `checkh(b, 1'b1); + i = s.sum with (item.len); + `checkh(i, 10); + i = s.product with (item.len); + `checkh(i, 24); + b = s.sum with (item == "hello"); + `checkh(b, 1'b1); + b = s.sum with (item == ""); + `checkh(b, 1'b0); + b = s.product with (item inside {"hello", "sad"}); + `checkh(b, 1'b0); + b = s.product with (item inside {"hello", "sad", "world"}); + `checkh(b, 1'b1); - b = s.unknown_bad; + b = s.unknown_bad; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_multid.v b/test_regress/t/t_dynarray_multid.v index f364e399a..dd6205f2e 100644 --- a/test_regress/t/t_dynarray_multid.v +++ b/test_regress/t/t_dynarray_multid.v @@ -4,227 +4,229 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - integer a1 [][]; - integer a2 [2][]; + integer a1[][]; + integer a2[2][]; - integer a3 [][] = '{'{1, 2, 3}, '{4, 5, 6}}; - integer a4 [][] = '{{7, 8, 9}, {10, 11, 12}}; - integer a5 [][] = '{3{'{13, 14}}}; + integer a3[][] = '{'{1, 2, 3}, '{4, 5, 6}}; + integer a4[][] = '{{7, 8, 9}, {10, 11, 12}}; + integer a5[][] = '{3{'{13, 14}}}; - integer aa1 [string][]; - integer wa1 [*][]; - integer qa1 [$][]; - struct { - integer i; - integer a[]; - } s1; + integer aa1[string][]; + integer wa1 [*] []; + integer qa1[$][]; + struct { + integer i; + integer a[]; + } s1; - integer a[] = '{1,2,3}; + integer a[] = '{1, 2, 3}; - logic [7:0][3:0] a6 [][]; + logic [7:0][3:0] a6[][]; - initial begin - `checkh(a1.size, 0); - a1 = new [3]; - `checkh(a1.size, 3); - `checkh($size(a1), 3); - `checkh($high(a1), 2); - `checkh($right(a1), 2); + initial begin + `checkh(a1.size, 0); + a1 = new[3]; + `checkh(a1.size, 3); + `checkh($size(a1), 3); + `checkh($high(a1), 2); + `checkh($right(a1), 2); - foreach (a1[i]) a1[i] = new [i + 1]; + foreach (a1[i]) a1[i] = new[i + 1]; - foreach (a1[i]) begin - `checkh(a1[i].size, i + 1); - `checkh($size(a1[i]), i + 1); - `checkh($high(a1[i]), i); - `checkh($right(a1[i]), i); - end + foreach (a1[i]) begin + `checkh(a1[i].size, i + 1); + `checkh($size(a1[i]), i + 1); + `checkh($high(a1[i]), i); + `checkh($right(a1[i]), i); + end - foreach (a1[i, j]) a1[i][j] = i * 10 + j; + foreach (a1[i, j]) a1[i][j] = i * 10 + j; - `checkh(a1[0][0], 0); - `checkh(a1[1][0], 10); - `checkh(a1[1][1], 11); - `checkh(a1[2][0], 20); - `checkh(a1[2][1], 21); - `checkh(a1[2][2], 22); + `checkh(a1[0][0], 0); + `checkh(a1[1][0], 10); + `checkh(a1[1][1], 11); + `checkh(a1[2][0], 20); + `checkh(a1[2][1], 21); + `checkh(a1[2][2], 22); - `checkh(a1[2].sum, 63); + `checkh(a1[2].sum, 63); - foreach (a1[i]) a1[i].delete; - foreach (a1[i]) begin - `checkh(a1[i].size, 0); - end + foreach (a1[i]) a1[i].delete; + foreach (a1[i]) begin + `checkh(a1[i].size, 0); + end - a1.delete; - `checkh(a1.size, 0); + a1.delete; + `checkh(a1.size, 0); - a1 = new [2]; - `checkh(a1.size, 2); + a1 = new[2]; + `checkh(a1.size, 2); - foreach (a1[i]) a1[i] = new [i + 2]; - foreach (a1[i]) begin - `checkh(a1[i].size, i + 2); - end + foreach (a1[i]) a1[i] = new[i + 2]; + foreach (a1[i]) begin + `checkh(a1[i].size, i + 2); + end - foreach (a2[i]) begin - `checkh(a2[i].size, 0); - end - foreach (a2[i]) a2[i] = new [i + 1]; - foreach (a2[i]) begin - `checkh(a2[i].size, i + 1); - end + foreach (a2[i]) begin + `checkh(a2[i].size, 0); + end + foreach (a2[i]) a2[i] = new[i + 1]; + foreach (a2[i]) begin + `checkh(a2[i].size, i + 1); + end - foreach (a2[i]) a2[i].delete; - foreach (a2[i]) begin - `checkh(a2[i].size, 0); - end + foreach (a2[i]) a2[i].delete; + foreach (a2[i]) begin + `checkh(a2[i].size, 0); + end - `checkh(a3.size, 2); - foreach (a3[i]) begin - `checkh(a3[i].size, 3); - end + `checkh(a3.size, 2); + foreach (a3[i]) begin + `checkh(a3[i].size, 3); + end - `checkh(a3[0][0], 1); - `checkh(a3[0][1], 2); - `checkh(a3[0][2], 3); - `checkh(a3[1][0], 4); - `checkh(a3[1][1], 5); - `checkh(a3[1][2], 6); + `checkh(a3[0][0], 1); + `checkh(a3[0][1], 2); + `checkh(a3[0][2], 3); + `checkh(a3[1][0], 4); + `checkh(a3[1][1], 5); + `checkh(a3[1][2], 6); - `checkh(a4.size, 2); - foreach (a4[i]) begin - `checkh(a4[i].size, 3); - end + `checkh(a4.size, 2); + foreach (a4[i]) begin + `checkh(a4[i].size, 3); + end - `checkh(a4[0][0], 7); - `checkh(a4[0][1], 8); - `checkh(a4[0][2], 9); - `checkh(a4[1][0], 10); - `checkh(a4[1][1], 11); - `checkh(a4[1][2], 12); + `checkh(a4[0][0], 7); + `checkh(a4[0][1], 8); + `checkh(a4[0][2], 9); + `checkh(a4[1][0], 10); + `checkh(a4[1][1], 11); + `checkh(a4[1][2], 12); - `checkh(a5.size, 3); - foreach (a5[i]) begin - `checkh(a5[i].size, 2); - end + `checkh(a5.size, 3); + foreach (a5[i]) begin + `checkh(a5[i].size, 2); + end - `checkh(a5[0][0], 13); - `checkh(a5[0][1], 14); - `checkh(a5[1][0], 13); - `checkh(a5[1][1], 14); - `checkh(a5[2][0], 13); - `checkh(a5[2][1], 14); + `checkh(a5[0][0], 13); + `checkh(a5[0][1], 14); + `checkh(a5[1][0], 13); + `checkh(a5[1][1], 14); + `checkh(a5[2][0], 13); + `checkh(a5[2][1], 14); - a5 = a4; - `checkh(a5.size, 2); - foreach (a5[i]) begin - `checkh(a5[i].size, 3); - end + a5 = a4; + `checkh(a5.size, 2); + foreach (a5[i]) begin + `checkh(a5[i].size, 3); + end - `checkh(a5[0][0], 7); - `checkh(a5[0][1], 8); - `checkh(a5[0][2], 9); - `checkh(a5[1][0], 10); - `checkh(a5[1][1], 11); - `checkh(a5[1][2], 12); + `checkh(a5[0][0], 7); + `checkh(a5[0][1], 8); + `checkh(a5[0][2], 9); + `checkh(a5[1][0], 10); + `checkh(a5[1][1], 11); + `checkh(a5[1][2], 12); - a4 = '{'{15, 16}, '{17, 18}}; + a4 = '{'{15, 16}, '{17, 18}}; - `checkh(a4.size, 2); - foreach (a4[i]) begin - `checkh(a4[i].size, 2); - end + `checkh(a4.size, 2); + foreach (a4[i]) begin + `checkh(a4[i].size, 2); + end - `checkh(a4[0][0], 15); - `checkh(a4[0][1], 16); - `checkh(a4[1][0], 17); - `checkh(a4[1][1], 18); + `checkh(a4[0][0], 15); + `checkh(a4[0][1], 16); + `checkh(a4[1][0], 17); + `checkh(a4[1][1], 18); - a4 = '{{19}, {20}, {21, 22}}; + a4 = '{{19}, {20}, {21, 22}}; - `checkh(a4.size, 3); - `checkh(a4[0].size, 1); - `checkh(a4[1].size, 1); - `checkh(a4[2].size, 2); + `checkh(a4.size, 3); + `checkh(a4[0].size, 1); + `checkh(a4[1].size, 1); + `checkh(a4[2].size, 2); - `checkh(a4[0][0], 19); - `checkh(a4[1][0], 20); - `checkh(a4[2][0], 21); - `checkh(a4[2][1], 22); + `checkh(a4[0][0], 19); + `checkh(a4[1][0], 20); + `checkh(a4[2][0], 21); + `checkh(a4[2][1], 22); - a5 = '{2{a}}; + a5 = '{2{a}}; - `checkh(a5.size, 2); - foreach (a5[i]) begin - `checkh(a5[i].size, 3); - end + `checkh(a5.size, 2); + foreach (a5[i]) begin + `checkh(a5[i].size, 3); + end - `checkh(a5[0][0], 1); - `checkh(a5[0][1], 2); - `checkh(a5[0][2], 3); - `checkh(a5[1][0], 1); - `checkh(a5[1][1], 2); - `checkh(a5[1][2], 3); + `checkh(a5[0][0], 1); + `checkh(a5[0][1], 2); + `checkh(a5[0][2], 3); + `checkh(a5[1][0], 1); + `checkh(a5[1][1], 2); + `checkh(a5[1][2], 3); - a5 = '{}; - `checkh(a5.size, 0); + a5 = '{}; + `checkh(a5.size, 0); - a5 = '{2{'{}}}; + a5 = '{2{'{}}}; - `checkh(a5.size, 2); - foreach (a5[i]) begin - `checkh(a5[i].size, 0); - end + `checkh(a5.size, 2); + foreach (a5[i]) begin + `checkh(a5[i].size, 0); + end - aa1["k1"] = new [3]; - `checkh(aa1["k1"].size, 3); - aa1["k1"].delete; + aa1["k1"] = new[3]; + `checkh(aa1["k1"].size, 3); + aa1["k1"].delete; - wa1[1] = new [3]; - `checkh(wa1[1].size, 3); - wa1[1].delete; + wa1[1] = new[3]; + `checkh(wa1[1].size, 3); + wa1[1].delete; - qa1.push_back(a); - `checkh(qa1[0].size, 3); - qa1[0] = new [4]; - `checkh(qa1[0].size, 4); - qa1[0].delete; + qa1.push_back(a); + `checkh(qa1[0].size, 3); + qa1[0] = new[4]; + `checkh(qa1[0].size, 4); + qa1[0].delete; - qa1[$-1].delete; - `checkh(qa1[$-1].size, 0); + qa1[$-1].delete; + `checkh(qa1[$-1].size, 0); - qa1.delete; - `checkh(qa1.size, 0); - `checkh(qa1[$-1].size, 0); - `checkh(qa1.size, 0); + qa1.delete; + `checkh(qa1.size, 0); + `checkh(qa1[$-1].size, 0); + `checkh(qa1.size, 0); - s1.a = new [4]; - `checkh(s1.a.size, 4); - s1.a.delete; + s1.a = new[4]; + `checkh(s1.a.size, 4); + s1.a.delete; - `checkh($dimensions(a1), 3); - `checkh($dimensions(a2), 3); - `checkh($dimensions(aa1), 3); - `checkh($dimensions(wa1), 3); - `checkh($dimensions(qa1), 3); - `checkh($dimensions(a), 2); - `checkh($dimensions(a6), 4); - `checkh($unpacked_dimensions(a1), 2); - `checkh($unpacked_dimensions(a2), 2); - `checkh($unpacked_dimensions(aa1), 2); - `checkh($unpacked_dimensions(wa1), 2); - `checkh($unpacked_dimensions(qa1), 2); - `checkh($unpacked_dimensions(a), 1); - `checkh($unpacked_dimensions(a6), 2); + `checkh($dimensions(a1), 3); + `checkh($dimensions(a2), 3); + `checkh($dimensions(aa1), 3); + `checkh($dimensions(wa1), 3); + `checkh($dimensions(qa1), 3); + `checkh($dimensions(a), 2); + `checkh($dimensions(a6), 4); + `checkh($unpacked_dimensions(a1), 2); + `checkh($unpacked_dimensions(a2), 2); + `checkh($unpacked_dimensions(aa1), 2); + `checkh($unpacked_dimensions(wa1), 2); + `checkh($unpacked_dimensions(qa1), 2); + `checkh($unpacked_dimensions(a), 1); + `checkh($unpacked_dimensions(a6), 2); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_param.v b/test_regress/t/t_dynarray_param.v index ca6e61b18..3e71148aa 100644 --- a/test_regress/t/t_dynarray_param.v +++ b/test_regress/t/t_dynarray_param.v @@ -4,51 +4,53 @@ // SPDX-FileCopyrightText: 2021 Noam Gallmann // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - localparam int SIZES [3:0] = '{1,2,3,4}; - typedef int calc_sums_t [3:0]; + localparam int SIZES[3:0] = '{1, 2, 3, 4}; + typedef int calc_sums_t[3:0]; - localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); - function automatic calc_sums_t calc_sums_array(int s[3:0], int n); - int sum = 0; - for (int ii = 0; ii < n; ++ii) begin - sum = sum + s[ii]; - calc_sums_array[ii] = sum; - end - endfunction + localparam int SUMS_ARRAY[3:0] = calc_sums_array(SIZES, 4); + function automatic calc_sums_t calc_sums_array(int s[3:0], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_array[ii] = sum; + end + endfunction `ifndef VERILATOR - localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); + localparam int SUMS_DYN[3:0] = calc_sums_dyn(SIZES, 4); `endif - function automatic calc_sums_t calc_sums_dyn(int s[], int n); - int sum = 0; - for (int ii = 0; ii < n; ++ii) begin - sum = sum + s[ii]; - calc_sums_dyn[ii] = sum; - end - endfunction + function automatic calc_sums_t calc_sums_dyn(int s[], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_dyn[ii] = sum; + end + endfunction - initial begin - `checkh(SIZES[0], 4); - `checkh(SIZES[1], 3); - `checkh(SIZES[2], 2); - `checkh(SIZES[3], 1); + initial begin + `checkh(SIZES[0], 4); + `checkh(SIZES[1], 3); + `checkh(SIZES[2], 2); + `checkh(SIZES[3], 1); - `checkh(SUMS_ARRAY[0], 4); - `checkh(SUMS_ARRAY[1], 7); - `checkh(SUMS_ARRAY[2], 9); - `checkh(SUMS_ARRAY[3], 10); + `checkh(SUMS_ARRAY[0], 4); + `checkh(SUMS_ARRAY[1], 7); + `checkh(SUMS_ARRAY[2], 9); + `checkh(SUMS_ARRAY[3], 10); `ifndef VERILATOR - `checkh(SUMS_DYN[0], 1); - `checkh(SUMS_DYN[1], 3); - `checkh(SUMS_DYN[2], 6); - `checkh(SUMS_DYN[3], 10); + `checkh(SUMS_DYN[0], 1); + `checkh(SUMS_DYN[1], 3); + `checkh(SUMS_DYN[2], 6); + `checkh(SUMS_DYN[3], 10); `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_dynarray_unpacked.v b/test_regress/t/t_dynarray_unpacked.v index ace98e6cb..7b5b1ed39 100644 --- a/test_regress/t/t_dynarray_unpacked.v +++ b/test_regress/t/t_dynarray_unpacked.v @@ -4,29 +4,31 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; - byte dyn [][1:0]; + byte dyn[][1:0]; - initial begin - begin - dyn = new [3]; - dyn[0] = '{101, 100}; - dyn[1] = '{111, 110}; - dyn[2] = '{121, 120}; - `checkh(dyn[0][0], 100); - `checkh(dyn[0][1], 101); - `checkh(dyn[1][0], 110); - `checkh(dyn[1][1], 111); - `checkh(dyn[2][0], 120); - `checkh(dyn[2][1], 121); - end + initial begin + begin + dyn = new[3]; + dyn[0] = '{101, 100}; + dyn[1] = '{111, 110}; + dyn[2] = '{121, 120}; + `checkh(dyn[0][0], 100); + `checkh(dyn[0][1], 101); + `checkh(dyn[1][0], 110); + `checkh(dyn[1][1], 111); + `checkh(dyn[2][0], 120); + `checkh(dyn[2][1], 121); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v index fa8a69c5f..62646d054 100644 --- a/test_regress/t/t_embed1.v +++ b/test_regress/t/t_embed1.v @@ -4,107 +4,105 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire bit_in = crc[0]; - wire [30:0] vec_in = crc[31:1]; - wire [123:0] wide_in = {crc[59:0],~crc[63:0]}; + // Take CRC data and apply to testblock inputs + wire bit_in = crc[0]; + wire [30:0] vec_in = crc[31:1]; + wire [123:0] wide_in = {crc[59:0], ~crc[63:0]}; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire exp_bit_out; // From reference of t_embed1_child.v - wire exp_did_init_out; // From reference of t_embed1_child.v - wire [30:0] exp_vec_out; // From reference of t_embed1_child.v - wire [123:0] exp_wide_out; // From reference of t_embed1_child.v - wire got_bit_out; // From test of t_embed1_wrap.v - wire got_did_init_out; // From test of t_embed1_wrap.v - wire [30:0] got_vec_out; // From test of t_embed1_wrap.v - wire [123:0] got_wide_out; // From test of t_embed1_wrap.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire exp_bit_out; // From reference of t_embed1_child.v + wire exp_did_init_out; // From reference of t_embed1_child.v + logic [30:0] exp_vec_out; // From reference of t_embed1_child.v + logic [123:0] exp_wide_out; // From reference of t_embed1_child.v + bit got_bit_out; // From test of t_embed1_wrap.v + bit got_did_init_out; // From test of t_embed1_wrap.v + bit [30:0] got_vec_out; // From test of t_embed1_wrap.v + bit [123:0] got_wide_out; // From test of t_embed1_wrap.v + // End of automatics - // A non-embedded master + // A non-embedded master - /* t_embed1_child AUTO_TEMPLATE( + /* t_embed1_child AUTO_TEMPLATE( .\(.*_out\) (exp_\1[]), .is_ref (1'b1)); */ - t_embed1_child reference - (/*AUTOINST*/ - // Outputs - .bit_out (exp_bit_out), // Templated - .vec_out (exp_vec_out[30:0]), // Templated - .wide_out (exp_wide_out[123:0]), // Templated - .did_init_out (exp_did_init_out), // Templated - // Inputs - .clk (clk), - .bit_in (bit_in), - .vec_in (vec_in[30:0]), - .wide_in (wide_in[123:0]), - .is_ref (1'b1)); // Templated + t_embed1_child reference ( /*AUTOINST*/ + // Outputs + .bit_out (exp_bit_out), // Templated + .vec_out (exp_vec_out[30:0]), // Templated + .wide_out (exp_wide_out[123:0]), // Templated + .did_init_out (exp_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b1)); // Templated - // The embeded comparison + // The embeded comparison - /* t_embed1_wrap AUTO_TEMPLATE( + /* t_embed1_wrap AUTO_TEMPLATE( .\(.*_out\) (got_\1[]), .is_ref (1'b0)); */ - t_embed1_wrap test - (/*AUTOINST*/ - // Outputs - .bit_out (got_bit_out), // Templated - .vec_out (got_vec_out[30:0]), // Templated - .wide_out (got_wide_out[123:0]), // Templated - .did_init_out (got_did_init_out), // Templated - // Inputs - .clk (clk), - .bit_in (bit_in), - .vec_in (vec_in[30:0]), - .wide_in (wide_in[123:0]), - .is_ref (1'b0)); // Templated + t_embed1_wrap test ( /*AUTOINST*/ + // Outputs + .bit_out (got_bit_out), // Templated + .vec_out (got_vec_out[30:0]), // Templated + .wide_out (got_wide_out[123:0]), // Templated + .did_init_out (got_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b0)); // Templated - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, - got_wide_out !== exp_wide_out, - got_vec_out !== exp_vec_out, - got_bit_out !== exp_bit_out, - got_did_init_out !== exp_did_init_out}; + // Aggregate outputs into a single result vector + wire [63:0] result = { + 60'h0, + got_wide_out !== exp_wide_out, + got_vec_out !== exp_vec_out, + got_bit_out !== exp_bit_out, + got_did_init_out !== exp_did_init_out + }; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result, - got_vec_out, exp_vec_out); + $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result, got_vec_out, + exp_vec_out); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + end + else if (cyc < 90) begin + if (result != 64'h0) begin + $display("Bit mismatch, result=%x\n", result); + $stop; end - else if (cyc<10) begin - end - else if (cyc<90) begin - if (result != 64'h0) begin - $display("Bit mismatch, result=%x\n", result); - $stop; - end - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - //Child prints this: $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + //Child prints this: $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v index 0e6be3315..b4acbe1c4 100644 --- a/test_regress/t/t_embed1_child.v +++ b/test_regress/t/t_embed1_child.v @@ -4,43 +4,45 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_embed1_child (/*AUTOARG*/ - // Outputs - bit_out, vec_out, wide_out, did_init_out, - // Inputs - clk, bit_in, vec_in, wide_in, is_ref - ); +module t_embed1_child ( /*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); - input clk; - input bit_in; - output bit_out; - input [30:0] vec_in; - output logic [30:0] vec_out; - input [123:0] wide_in; - output logic [123:0] wide_out; - output did_init_out; + input clk; + input bit_in; + output bit_out; + input [30:0] vec_in; + output logic [30:0] vec_out; + input [123:0] wide_in; + output logic [123:0] wide_out; + output did_init_out; - input is_ref; + input is_ref; - reg did_init; initial did_init = 0; - initial begin - did_init = 1; - end + reg did_init; + initial did_init = 0; + initial begin + did_init = 1; + end - reg did_final; initial did_final = 0; - final begin - did_final = 1; - if (!is_ref) $write("*-* All Finished *-*\n"); - //$finish is in parent - end + reg did_final; + initial did_final = 0; + final begin + did_final = 1; + if (!is_ref) $write("*-* All Finished *-*\n"); + //$finish is in parent + end - // Note async use! - wire bit_out = bit_in; - wire did_init_out = did_init; + // Note async use! + wire bit_out = bit_in; + wire did_init_out = did_init; - always @ (posedge clk) begin - vec_out <= vec_in; - wide_out <= wide_in; - end + always @(posedge clk) begin + vec_out <= vec_in; + wide_out <= wide_in; + end endmodule diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v index e3d5694ac..4c4924951 100644 --- a/test_regress/t/t_embed1_wrap.v +++ b/test_regress/t/t_embed1_wrap.v @@ -5,87 +5,87 @@ // SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ - // Outputs - bit_out, vec_out, wide_out, did_init_out, - // Inputs - clk, bit_in, vec_in, wide_in, is_ref - ); + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); - /*AUTOINOUTMODULE("t_embed1_child")*/ - // Beginning of automatic in/out/inouts (from specific module) - output bit bit_out; - output bit [30:0] vec_out; - output bit [123:0] wide_out; - output bit did_init_out; - input clk; - input bit_in; - input [30:0] vec_in; - input [123:0] wide_in; - input is_ref; - // End of automatics + /*AUTOINOUTMODULE("t_embed1_child")*/ + // Beginning of automatic in/out/inouts (from specific module) + output bit bit_out; + output bit [30:0] vec_out; + output bit [123:0] wide_out; + output bit did_init_out; + input clk; + input bit_in; + input [30:0] vec_in; + input [123:0] wide_in; + input is_ref; + // End of automatics `ifdef verilator - // Import $t_embed_child__initial etc as a DPI function + // Import $t_embed_child__initial etc as a DPI function `endif - //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this - import "DPI-C" context function void t_embed_child_initial(); - import "DPI-C" context function void t_embed_child_final(); - import "DPI-C" context function void t_embed_child_eval(); - import "DPI-C" context function void t_embed_child_io_eval - ( - //TODO we support bit, but not logic - input bit clk, - input bit bit_in, - input bit [30:0] vec_in, - input bit [123:0] wide_in, - input bit is_ref, - output bit bit_out, - output bit [30:0] vec_out, - output bit [123:0] wide_out, - output bit did_init_out); + //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this + import "DPI-C" context function void t_embed_child_initial(); + import "DPI-C" context function void t_embed_child_final(); + import "DPI-C" context function void t_embed_child_eval(); + import "DPI-C" context function void t_embed_child_io_eval + ( + //TODO we support bit, but not logic + input bit clk, + input bit bit_in, + input bit [30:0] vec_in, + input bit [123:0] wide_in, + input bit is_ref, + output bit bit_out, + output bit [30:0] vec_out, + output bit [123:0] wide_out, + output bit did_init_out); - initial begin - // Load all values - t_embed_child_initial(); - end + initial begin + // Load all values + t_embed_child_initial(); + end - // Only if system verilog, and if a "final" block in the code - final begin - t_embed_child_final(); - end + // Only if system verilog, and if a "final" block in the code + final begin + t_embed_child_final(); + end - bit _temp_bit_out; - bit _temp_did_init_out; - bit [30:0] _temp_vec_out; - bit [123:0] _temp_wide_out; - always @* begin - t_embed_child_io_eval( - clk, - bit_in, - vec_in, - wide_in, - is_ref, - _temp_bit_out, - _temp_vec_out, - _temp_wide_out, - _temp_did_init_out - ); - // TODO might eliminate these temporaries - bit_out = _temp_bit_out; - did_init_out = _temp_did_init_out; - end + bit _temp_bit_out; + bit _temp_did_init_out; + bit [30:0] _temp_vec_out; + bit [123:0] _temp_wide_out; + always @* begin + t_embed_child_io_eval( + clk, + bit_in, + vec_in, + wide_in, + is_ref, + _temp_bit_out, + _temp_vec_out, + _temp_wide_out, + _temp_did_init_out + ); + // TODO might eliminate these temporaries + bit_out = _temp_bit_out; + did_init_out = _temp_did_init_out; + end - // Send all variables every cycle, - // or have a sensitivity routine for each? - // How to make sure we call eval at end of variable changes? - // #0 (though not verilator compatible!) + // Send all variables every cycle, + // or have a sensitivity routine for each? + // How to make sure we call eval at end of variable changes? + // #0 (though not verilator compatible!) - // TODO for now, we know what changes when - always @ (posedge clk) begin - vec_out <= _temp_vec_out; - wide_out <= _temp_wide_out; - end + // TODO for now, we know what changes when + always @ (posedge clk) begin + vec_out <= _temp_vec_out; + wide_out <= _temp_wide_out; + end endmodule diff --git a/test_regress/t/t_emit_accessors.v b/test_regress/t/t_emit_accessors.v index d92bd4f1d..eb64f328a 100644 --- a/test_regress/t/t_emit_accessors.v +++ b/test_regress/t/t_emit_accessors.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_emit_accessors( +module t_emit_accessors ( input bit in1, input bit in2, input logic [31:0] in3, @@ -13,7 +13,7 @@ module t_emit_accessors( output logic [31:0] out2, output logic [77:0] out3 ); - assign out1 = in1 & in2; - assign out2 = in3 & in4; - assign out3 = 1; + assign out1 = in1 & in2; + assign out2 = in3 & in4; + assign out3 = 1; endmodule diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index 0e9546b07..c92d5c2dd 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -4,156 +4,157 @@ // SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk + ); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; + // verilog_format: off + bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; - bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d}; + bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d}; - bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06}; + bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06}; - bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; + bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; - bit [9*32-1:0] w9 = {32'hca800ac1, - 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; + bit [9*32-1:0] w9 = {32'hca800ac1, + 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; - bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, - 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; + bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, + 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; - bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, - 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; + bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, + 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; - bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, - 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; + bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, + 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; - bit [17*32-1:0] w17 = {32'hf1e322ac, - 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, - 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; + bit [17*32-1:0] w17 = {32'hf1e322ac, + 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, + 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; - function [7:0] bytehash (input [32*32-1:0] data); - integer i; - bytehash = 0; - for (i=0; i<32*32; ++i) begin - bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; - end - return bytehash; - endfunction + function [7:0] bytehash (input [32*32-1:0] data); + integer i; + bytehash = 0; + for (i=0; i<32*32; ++i) begin + bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; + end + return bytehash; + endfunction - // Aggregate outputs into a single result vector - // verilator lint_off WIDTH - wire [63:0] result = (bytehash(w4) - ^ bytehash(w8m) - ^ bytehash(w8) - ^ bytehash(w8p) - ^ bytehash(w9) - ^ bytehash(w16m) - ^ bytehash(w16) - ^ bytehash(w16p) - ^ bytehash(w17)); - // verilator lint_on WIDTH + // Aggregate outputs into a single result vector + // verilator lint_off WIDTH + wire [63:0] result = (bytehash(w4) + ^ bytehash(w8m) + ^ bytehash(w8) + ^ bytehash(w8p) + ^ bytehash(w9) + ^ bytehash(w16m) + ^ bytehash(w16) + ^ bytehash(w16p) + ^ bytehash(w17)); + // verilator lint_on WIDTH `define EXPECTED_SUM 64'h2bc7c2a98a302891 - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - // verilator lint_off SELRANGE - `checkhw(w4,3,32'h7c709753); - `checkhw(w4,2,32'hbc8f6059); - `checkhw(w4,1,32'h3b0db464); - `checkhw(w4,0,32'h721a8fad); - `checkhw(w8m,7,31'h7146e1bf); - `checkhw(w8m,6,32'ha8549e42); - `checkhw(w8m,5,32'hca6960bd); - `checkhw(w8m,4,32'h191b7f9b); - `checkhw(w8m,3,32'h93d79866); - `checkhw(w8m,2,32'hf4489e2b); - `checkhw(w8m,1,32'h8e9a3236); - `checkhw(w8m,0,32'h1d2a2d1d); - `checkhw(w8,7,32'hc211addc); - `checkhw(w8,6,32'he5d4a057); - `checkhw(w8,5,32'h5cbf88fe); - `checkhw(w8,4,32'h42cf42e2); - `checkhw(w8,3,32'heb584263); - `checkhw(w8,2,32'ha585f118); - `checkhw(w8,1,32'h231531c8); - `checkhw(w8,0,32'hc73f7b06); - `checkhw(w8p,8,1'b1); - `checkhw(w8p,7,32'h096aa54b); - `checkhw(w8p,6,32'h48aae18e); - `checkhw(w8p,5,32'hf9502cea); - `checkhw(w8p,4,32'h518c8b61); - `checkhw(w8p,3,32'h9e8641a2); - `checkhw(w8p,2,32'h0dc0249c); - `checkhw(w8p,1,32'hd421a87a); - `checkhw(w8p,0,32'hb8ee9199); - `checkhw(w9,8,32'hca800ac1); - `checkhw(w9,7,32'h0de4823a); - `checkhw(w9,6,32'ha51663ac); - `checkhw(w9,5,32'h96351446); - `checkhw(w9,4,32'h6b0bbcd5); - `checkhw(w9,3,32'h4a64b530); - `checkhw(w9,2,32'h4967d59a); - `checkhw(w9,1,32'hfcc17292); - `checkhw(w9,0,32'h57926621); - `checkhw(w16m,15,31'h77ad72c7); - `checkhw(w16m,14,32'h73aa9cbb); - `checkhw(w16m,13,32'h7ecf026d); - `checkhw(w16m,12,32'h985a3ed2); - `checkhw(w16m,11,32'hfe961c1d); - `checkhw(w16m,10,32'h7a01df72); - `checkhw(w16m,9,32'h79e13d71); - `checkhw(w16m,8,32'hb69e2e32); - `checkhw(w16m,7,32'h09fcbc45); - `checkhw(w16m,6,32'hcfd738c1); - `checkhw(w16m,5,32'hc197ac7c); - `checkhw(w16m,4,32'hc316d727); - `checkhw(w16m,3,32'h903034e4); - `checkhw(w16m,2,32'h92a047d1); - `checkhw(w16m,1,32'h6a5357af); - `checkhw(w16m,0,32'ha82ce9c8); - // verilator lint_on SELRANGE - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - w4 = w4 >>> 1; - w8m = w8m >>> 1; - w8 = w8 >>> 1; - w8p = w8p >>> 1; - w9 = w9 >>> 1; - w16m = w16m >>> 1; - w16 = w16 >>> 1; - w16p = w16p >>> 1; - w17 = w17 >>> 1; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + // verilator lint_off SELRANGE + `checkhw(w4,3,32'h7c709753); + `checkhw(w4,2,32'hbc8f6059); + `checkhw(w4,1,32'h3b0db464); + `checkhw(w4,0,32'h721a8fad); + `checkhw(w8m,7,31'h7146e1bf); + `checkhw(w8m,6,32'ha8549e42); + `checkhw(w8m,5,32'hca6960bd); + `checkhw(w8m,4,32'h191b7f9b); + `checkhw(w8m,3,32'h93d79866); + `checkhw(w8m,2,32'hf4489e2b); + `checkhw(w8m,1,32'h8e9a3236); + `checkhw(w8m,0,32'h1d2a2d1d); + `checkhw(w8,7,32'hc211addc); + `checkhw(w8,6,32'he5d4a057); + `checkhw(w8,5,32'h5cbf88fe); + `checkhw(w8,4,32'h42cf42e2); + `checkhw(w8,3,32'heb584263); + `checkhw(w8,2,32'ha585f118); + `checkhw(w8,1,32'h231531c8); + `checkhw(w8,0,32'hc73f7b06); + `checkhw(w8p,8,1'b1); + `checkhw(w8p,7,32'h096aa54b); + `checkhw(w8p,6,32'h48aae18e); + `checkhw(w8p,5,32'hf9502cea); + `checkhw(w8p,4,32'h518c8b61); + `checkhw(w8p,3,32'h9e8641a2); + `checkhw(w8p,2,32'h0dc0249c); + `checkhw(w8p,1,32'hd421a87a); + `checkhw(w8p,0,32'hb8ee9199); + `checkhw(w9,8,32'hca800ac1); + `checkhw(w9,7,32'h0de4823a); + `checkhw(w9,6,32'ha51663ac); + `checkhw(w9,5,32'h96351446); + `checkhw(w9,4,32'h6b0bbcd5); + `checkhw(w9,3,32'h4a64b530); + `checkhw(w9,2,32'h4967d59a); + `checkhw(w9,1,32'hfcc17292); + `checkhw(w9,0,32'h57926621); + `checkhw(w16m,15,31'h77ad72c7); + `checkhw(w16m,14,32'h73aa9cbb); + `checkhw(w16m,13,32'h7ecf026d); + `checkhw(w16m,12,32'h985a3ed2); + `checkhw(w16m,11,32'hfe961c1d); + `checkhw(w16m,10,32'h7a01df72); + `checkhw(w16m,9,32'h79e13d71); + `checkhw(w16m,8,32'hb69e2e32); + `checkhw(w16m,7,32'h09fcbc45); + `checkhw(w16m,6,32'hcfd738c1); + `checkhw(w16m,5,32'hc197ac7c); + `checkhw(w16m,4,32'hc316d727); + `checkhw(w16m,3,32'h903034e4); + `checkhw(w16m,2,32'h92a047d1); + `checkhw(w16m,1,32'h6a5357af); + `checkhw(w16m,0,32'ha82ce9c8); + // verilator lint_on SELRANGE + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + w4 = w4 >>> 1; + w8m = w8m >>> 1; + w8 = w8 >>> 1; + w8p = w8p >>> 1; + w9 = w9 >>> 1; + w16m = w16m >>> 1; + w16 = w16 >>> 1; + w16p = w16p >>> 1; + w17 = w17 >>> 1; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v index d942d033b..00c4a12f0 100644 --- a/test_regress/t/t_enum.v +++ b/test_regress/t/t_enum.v @@ -5,98 +5,98 @@ // SPDX-License-Identifier: CC0-1.0 typedef enum logic [4:0] - { - BIT0 = 5'd0, - BIT1 = 5'd1, - BIT2 = 5'd2 - } three_t; + { + BIT0 = 5'd0, + BIT1 = 5'd1, + BIT2 = 5'd2 + } three_t; module t; - localparam FIVE = 5; + localparam FIVE = 5; - enum { e0, - e1, - e3=3, - e5=FIVE, - e10_[2] = 10, - e12, - e20_[5:7] = 25, - e20_z, - e30_[7:5] = 30, - e30_z - } EN; + enum { e0, + e1, + e3=3, + e5=FIVE, + e10_[2] = 10, + e12, + e20_[5:7] = 25, + e20_z, + e30_[7:5] = 30, + e30_z + } EN; - enum { - z5 = e5 - } ZN; + enum { + z5 = e5 + } ZN; - enum int unsigned { - FIVE_INT = 5 - } FI; + enum int unsigned { + FIVE_INT = 5 + } FI; - typedef enum three_t; // Forward - typedef enum [2:0] { ONES=~0 } three_t; - three_t three = ONES; + typedef enum three_t; // Forward + typedef enum [2:0] { ONES=~0 } three_t; + three_t three = ONES; - int array5[z5]; - int array5i[FIVE_INT]; + int array5[z5]; + int array5i[FIVE_INT]; - var logic [ONES:0] sized_based_on_enum; + var logic [ONES:0] sized_based_on_enum; - var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, - QPR={2'b0,2'h3 }, QACK, QRSP } inv; + var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, + QPR={2'b0,2'h3 }, QACK, QRSP } inv; - enum logic [7:0] { - ENARRAY = 6 - } [3:2] enarray; + enum logic [7:0] { + ENARRAY = 6 + } [3:2] enarray; - initial begin - if (e0 !== 0) $stop; - if (e1 !== 1) $stop; - if (e3 !== 3) $stop; - if (e5 !== 5) $stop; - if (e10_0 !== 10) $stop; - if (e10_1 !== 11) $stop; - if (e12 !== 12) $stop; - if (e20_5 !== 25) $stop; - if (e20_6 !== 26) $stop; - if (e20_7 !== 27) $stop; - if (e20_z !== 28) $stop; - if (e30_7 !== 30) $stop; - if (e30_6 !== 31) $stop; - if (e30_5 !== 32) $stop; - if (e30_z !== 33) $stop; + initial begin + if (e0 !== 0) $stop; + if (e1 !== 1) $stop; + if (e3 !== 3) $stop; + if (e5 !== 5) $stop; + if (e10_0 !== 10) $stop; + if (e10_1 !== 11) $stop; + if (e12 !== 12) $stop; + if (e20_5 !== 25) $stop; + if (e20_6 !== 26) $stop; + if (e20_7 !== 27) $stop; + if (e20_z !== 28) $stop; + if (e30_7 !== 30) $stop; + if (e30_6 !== 31) $stop; + if (e30_5 !== 32) $stop; + if (e30_z !== 33) $stop; - if (z5 !== 5) $stop; + if (z5 !== 5) $stop; - if (three != 3'b111) $stop; + if (three != 3'b111) $stop; - if ($bits(sized_based_on_enum) != 8) $stop; - if ($bits(three_t) != 3) $stop; + if ($bits(sized_based_on_enum) != 8) $stop; + if ($bits(three_t) != 3) $stop; - if (FIVE[BIT0] != 1'b1) $stop; - if (FIVE[BIT1] != 1'b0) $stop; - if (FIVE[BIT2] != 1'b1) $stop; + if (FIVE[BIT0] != 1'b1) $stop; + if (FIVE[BIT1] != 1'b0) $stop; + if (FIVE[BIT2] != 1'b1) $stop; - if (QINVALID != 15) $stop; - if (QSEND != 0) $stop; - if (QOP != 1) $stop; - if (QCL != 2) $stop; - if (QPR != 3) $stop; - if (QACK != 4) $stop; - if (QRSP != 5) $stop; + if (QINVALID != 15) $stop; + if (QSEND != 0) $stop; + if (QOP != 1) $stop; + if (QCL != 2) $stop; + if (QPR != 3) $stop; + if (QACK != 4) $stop; + if (QRSP != 5) $stop; - if ($size(array5) != 5) $stop; - if ($size(array5i) != 5) $stop; + if ($size(array5) != 5) $stop; + if ($size(array5i) != 5) $stop; - enarray[2] = ENARRAY; - enarray[3] = ENARRAY; - if (enarray[2] !== ENARRAY) $stop; - if (enarray[3] !== ENARRAY) $stop; + enarray[2] = ENARRAY; + enarray[3] = ENARRAY; + if (enarray[2] !== ENARRAY) $stop; + if (enarray[3] !== ENARRAY) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_bad_cell.out b/test_regress/t/t_enum_bad_cell.out index 95db9e884..5d24ee022 100644 --- a/test_regress/t/t_enum_bad_cell.out +++ b/test_regress/t/t_enum_bad_cell.out @@ -1,9 +1,9 @@ -%Warning-VARHIDDEN: t/t_enum_bad_cell.v:12:14: Declaration of enum value hides declaration in upper scope: s1 - 12 | enum {s0, s1} state; - | ^~ - t/t_enum_bad_cell.v:8:8: ... Location of original declaration - 8 | sub s1(); - | ^~ +%Warning-VARHIDDEN: t/t_enum_bad_cell.v:14:5: Declaration of enum value hides declaration in upper scope: s1 + 14 | s1 + | ^~ + t/t_enum_bad_cell.v:8:7: ... Location of original declaration + 8 | sub s1 (); + | ^~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_enum_bad_cell.v b/test_regress/t/t_enum_bad_cell.v index 64fdc48c5..90ee38f15 100644 --- a/test_regress/t/t_enum_bad_cell.v +++ b/test_regress/t/t_enum_bad_cell.v @@ -5,13 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub s1(); + sub s1 (); endmodule module sub; - enum {s0, s1} state; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + enum { + s0, + s1 + } state; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_bad_dup.out b/test_regress/t/t_enum_bad_dup.out index 34dd352ea..b0289df2b 100644 --- a/test_regress/t/t_enum_bad_dup.out +++ b/test_regress/t/t_enum_bad_dup.out @@ -1,8 +1,8 @@ -%Error: t/t_enum_bad_dup.v:10:19: Duplicate declaration of enum value: DUP_VALUE - 10 | DUP_VALUE = 3 - | ^~~~~~~~~ - t/t_enum_bad_dup.v:9:19: ... Location of original declaration - 9 | typedef enum { DUP_VALUE = 2, - | ^~~~~~~~~ +%Error: t/t_enum_bad_dup.v:11:5: Duplicate declaration of enum value: DUP_VALUE + 11 | DUP_VALUE = 3 + | ^~~~~~~~~ + t/t_enum_bad_dup.v:10:5: ... Location of original declaration + 10 | DUP_VALUE = 2, + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_enum_bad_dup.v b/test_regress/t/t_enum_bad_dup.v index 6986303a3..9c5ef9db5 100644 --- a/test_regress/t/t_enum_bad_dup.v +++ b/test_regress/t/t_enum_bad_dup.v @@ -6,8 +6,9 @@ module t; - typedef enum { DUP_VALUE = 2, - DUP_VALUE = 3 - } dup_t; + typedef enum { + DUP_VALUE = 2, + DUP_VALUE = 3 + } dup_t; endmodule diff --git a/test_regress/t/t_enum_bad_hide.out b/test_regress/t/t_enum_bad_hide.out index 56f69e656..adebf5e7e 100644 --- a/test_regress/t/t_enum_bad_hide.out +++ b/test_regress/t/t_enum_bad_hide.out @@ -1,9 +1,9 @@ -%Warning-VARHIDDEN: t/t_enum_bad_hide.v:11:19: Declaration of enum value hides declaration in upper scope: HIDE_VALUE - 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; - | ^~~~~~~~~~ - t/t_enum_bad_hide.v:7:16: ... Location of original declaration - 7 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; - | ^~~~~~~~~~ +%Warning-VARHIDDEN: t/t_enum_bad_hide.v:11:17: Declaration of enum value hides declaration in upper scope: HIDE_VALUE + 11 | typedef enum {HIDE_VALUE = 0} hide_enum_t; + | ^~~~~~~~~~ + t/t_enum_bad_hide.v:7:15: ... Location of original declaration + 7 | typedef enum {HIDE_VALUE = 0} hide_enum_t; + | ^~~~~~~~~~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_enum_bad_hide.v b/test_regress/t/t_enum_bad_hide.v index fbaf4775c..225cb4b1b 100644 --- a/test_regress/t/t_enum_bad_hide.v +++ b/test_regress/t/t_enum_bad_hide.v @@ -4,10 +4,10 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum { HIDE_VALUE = 0 } hide_enum_t; +typedef enum {HIDE_VALUE = 0} hide_enum_t; module t; - typedef enum { HIDE_VALUE = 0 } hide_enum_t; + typedef enum {HIDE_VALUE = 0} hide_enum_t; endmodule diff --git a/test_regress/t/t_enum_bad_wrap.v b/test_regress/t/t_enum_bad_wrap.v index 2b796c591..eebdc3892 100644 --- a/test_regress/t/t_enum_bad_wrap.v +++ b/test_regress/t/t_enum_bad_wrap.v @@ -6,7 +6,7 @@ module t; - typedef enum [1:0] { + typedef enum [1:0] { PREWRAP = 2'd3, WRAPPED } wrap_t; diff --git a/test_regress/t/t_enum_const_methods.v b/test_regress/t/t_enum_const_methods.v index d67975577..baede21ce 100644 --- a/test_regress/t/t_enum_const_methods.v +++ b/test_regress/t/t_enum_const_methods.v @@ -6,51 +6,51 @@ module t; - typedef enum [1:0] {E0, E1, E2} enm_t; + typedef enum [1:0] {E0, E1, E2} enm_t; - function automatic enm_t get_first(); - enm_t enm; - return enm.first; - endfunction + function automatic enm_t get_first(); + enm_t enm; + return enm.first; + endfunction - localparam enm_t enum_first = get_first(); + localparam enm_t enum_first = get_first(); - function automatic enm_t get_last(); - enm_t enm; - return enm.last; - endfunction + function automatic enm_t get_last(); + enm_t enm; + return enm.last; + endfunction - localparam enm_t enum_last = get_last(); + localparam enm_t enum_last = get_last(); - function automatic enm_t get_second(); - enm_t enm; - enm = enm.first; - return enm.next; - endfunction + function automatic enm_t get_second(); + enm_t enm; + enm = enm.first; + return enm.next; + endfunction - localparam enm_t enum_second = get_second(); + localparam enm_t enum_second = get_second(); - function automatic string get_name(enm_t enm); - return enm.name; - endfunction + function automatic string get_name(enm_t enm); + return enm.name; + endfunction - localparam string e0_name = get_name(E0); + localparam string e0_name = get_name(E0); - function automatic enm_t get_2(); - enm_t enm; - enm = E0; - return enm.next.next; - endfunction + function automatic enm_t get_2(); + enm_t enm; + enm = E0; + return enm.next.next; + endfunction - localparam enm_t enum_2 = get_2(); + localparam enm_t enum_2 = get_2(); - initial begin - if (enum_first != E0) $stop; - if (enum_last != E2) $stop; - if (enum_second != E1) $stop; - if (e0_name != "E0") $stop; - if (enum_2 != E2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (enum_first != E0) $stop; + if (enum_last != E2) $stop; + if (enum_second != E1) $stop; + if (e0_name != "E0") $stop; + if (enum_2 != E2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.out b/test_regress/t/t_enum_enumvalue_struct_bad.out index b582a723a..a19e1d294 100644 --- a/test_regress/t/t_enum_enumvalue_struct_bad.out +++ b/test_regress/t/t_enum_enumvalue_struct_bad.out @@ -1,7 +1,7 @@ -%Error-ENUMVALUE: t/t_enum_enumvalue_struct_bad.v:21:33: Implicit conversion to enum 'MEMBERDTYPE 'a'' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) +%Error-ENUMVALUE: t/t_enum_enumvalue_struct_bad.v:19:32: Implicit conversion to enum 'MEMBERDTYPE 'a'' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast - 21 | localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; - | ^ + 19 | localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; + | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.v b/test_regress/t/t_enum_enumvalue_struct_bad.v index 418d999ed..31de34d34 100644 --- a/test_regress/t/t_enum_enumvalue_struct_bad.v +++ b/test_regress/t/t_enum_enumvalue_struct_bad.v @@ -8,30 +8,28 @@ package Pkg; - typedef enum int unsigned { - MODE10 = 10 - } mode_t; + typedef enum int unsigned {MODE10 = 10} mode_t; - typedef struct packed { - bit u; - mode_t a; - bit b; - } foo_t; + typedef struct packed { + bit u; + mode_t a; + bit b; + } foo_t; - localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; + localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; - localparam foo_t FOO1 = '{a: MODE10, b: 1'b1, u: 1'b1}; + localparam foo_t FOO1 = '{a: MODE10, b: 1'b1, u: 1'b1}; endpackage module t; - initial begin - //if (sum !== `EXPECTED_SUM) $stop; - if (Pkg::FOO0 != {1'b1, 32'd0, 1'b1}) $stop; - if (Pkg::FOO1 != {1'b1, 32'd10, 1'b1}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + //if (sum !== `EXPECTED_SUM) $stop; + if (Pkg::FOO0 != {1'b1, 32'd0, 1'b1}) $stop; + if (Pkg::FOO1 != {1'b1, 32'd10, 1'b1}) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_func.v b/test_regress/t/t_enum_func.v index ec148b28d..f019b2c39 100644 --- a/test_regress/t/t_enum_func.v +++ b/test_regress/t/t_enum_func.v @@ -4,61 +4,62 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum { EN_ZERO, - EN_ONE - } En_t; +typedef enum { + EN_ZERO, + EN_ONE +} En_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // Insure that we can declare a type with a function declaration - function enum integer { - EF_TRUE = 1, - EF_FALSE = 0 } - f_enum_inv ( input a); - f_enum_inv = a ? EF_FALSE : EF_TRUE; - endfunction - initial begin - if (f_enum_inv(1) != 0) $stop; - if (f_enum_inv(0) != 1) $stop; - end + // Insure that we can declare a type with a function declaration + function enum integer {EF_TRUE = 1, EF_FALSE = 0} f_enum_inv(input a); + f_enum_inv = a ? EF_FALSE : EF_TRUE; + endfunction + initial begin + if (f_enum_inv(1) != 0) $stop; + if (f_enum_inv(0) != 1) $stop; + end - En_t a, z; + En_t a, z; - sub sub (/*AUTOINST*/ - // Outputs - .z (z), - // Inputs - .a (a)); + sub sub ( /*AUTOINST*/ + // Outputs + .z(z), + // Inputs + .a(a) + ); - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= EN_ZERO; - end - if (cyc==2) begin - a <= EN_ONE; - if (z != EN_ONE) $stop; - end - if (cyc==3) begin - if (z != EN_ZERO) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a <= EN_ZERO; end - end + if (cyc == 2) begin + a <= EN_ONE; + if (z != EN_ONE) $stop; + end + if (cyc == 3) begin + if (z != EN_ZERO) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module sub (input En_t a, output En_t z); - always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE; +module sub ( + input En_t a, + output En_t z +); + always @* z = (a == EN_ONE) ? EN_ZERO : EN_ONE; endmodule // Local Variables: diff --git a/test_regress/t/t_enum_huge_methods.v b/test_regress/t/t_enum_huge_methods.v index db8e653dd..06e64eef4 100644 --- a/test_regress/t/t_enum_huge_methods.v +++ b/test_regress/t/t_enum_huge_methods.v @@ -4,75 +4,75 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef enum logic [59:0] { - E01 = 60'h1, - ELARGE = 60'h1234_4567_abcd - } my_t; + typedef enum logic [59:0] { + E01 = 60'h1, + ELARGE = 60'h1234_4567_abcd + } my_t; - integer cyc = 0; - my_t e; + integer cyc = 0; + my_t e; - string all; - int i_cast; + string all; + int i_cast; - // Check runtime - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Setup - e <= E01; - end - else if (cyc == 1) begin - `checks(e.name, "E01"); - `checkh(e.next, ELARGE); - `checkh(e.next(0), E01); - `checkh(e.prev(0), E01); - e <= ELARGE; - end - else if (cyc == 3) begin - `checks(e.name, "ELARGE"); - `checkh(e.next, E01); - `checkh(e.prev, E01); - `checkh(e.next(0), ELARGE); - `checkh(e.prev(0), ELARGE); - e <= E01; - end - // - else if (cyc == 10) begin - i_cast <= $cast(e, 60'h1234); - end - else if (cyc == 11) begin - `checkh(i_cast, 0); - i_cast <= $cast(e, 60'h1); - end - else if (cyc == 12) begin - `checkh(i_cast, 1); - i_cast <= $cast(e, 60'h1234_4567_abcd); - end - else if (cyc == 13) begin - `checkh(i_cast, 1); - end - // - else if (cyc == 20) begin - e <= my_t'('h11); // Unknown - end - else if (cyc == 21) begin - `checks(e.name, ""); // Unknown - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Check runtime + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + e <= E01; + end + else if (cyc == 1) begin + `checks(e.name, "E01"); + `checkh(e.next, ELARGE); + `checkh(e.next(0), E01); + `checkh(e.prev(0), E01); + e <= ELARGE; + end + else if (cyc == 3) begin + `checks(e.name, "ELARGE"); + `checkh(e.next, E01); + `checkh(e.prev, E01); + `checkh(e.next(0), ELARGE); + `checkh(e.prev(0), ELARGE); + e <= E01; + end + // + else if (cyc == 10) begin + i_cast <= $cast(e, 60'h1234); + end + else if (cyc == 11) begin + `checkh(i_cast, 0); + i_cast <= $cast(e, 60'h1); + end + else if (cyc == 12) begin + `checkh(i_cast, 1); + i_cast <= $cast(e, 60'h1234_4567_abcd); + end + else if (cyc == 13) begin + `checkh(i_cast, 1); + end + // + else if (cyc == 20) begin + e <= my_t'('h11); // Unknown + end + else if (cyc == 21) begin + `checks(e.name, ""); // Unknown + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_enum_int.v b/test_regress/t/t_enum_int.v index 2048e7254..1e4483731 100644 --- a/test_regress/t/t_enum_int.v +++ b/test_regress/t/t_enum_int.v @@ -4,79 +4,81 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + enum integer { - enum integer { + EP_State_IDLE, + EP_State_CMDSHIFT0, + EP_State_CMDSHIFT13, + EP_State_CMDSHIFT14, + EP_State_CMDSHIFT15, + EP_State_CMDSHIFT16, + EP_State_DWAIT, + EP_State_DSHIFT0, + EP_State_DSHIFT1, + EP_State_DSHIFT15 + } + m_state_xr, m_state2_xr; - EP_State_IDLE , - EP_State_CMDSHIFT0 , - EP_State_CMDSHIFT13 , - EP_State_CMDSHIFT14 , - EP_State_CMDSHIFT15 , - EP_State_CMDSHIFT16 , - EP_State_DWAIT , - EP_State_DSHIFT0 , - EP_State_DSHIFT1 , - EP_State_DSHIFT15 } m_state_xr, m_state2_xr; + // Beginning of automatic ASCII enum decoding + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + always @(m_state_xr) begin + case ({ + m_state_xr + }) + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; + endcase + end + // End of automatics - // Beginning of automatic ASCII enum decoding - reg [79:0] m_stateAscii_xr; // Decode of m_state_xr - always @(m_state_xr) begin - case ({m_state_xr}) - EP_State_IDLE: m_stateAscii_xr = "idle "; - EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; - EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; - EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; - EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; - EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; - EP_State_DWAIT: m_stateAscii_xr = "dwait "; - EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; - EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; - EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; - default: m_stateAscii_xr = "%Error "; - endcase - end - // End of automatics - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - m_state_xr <= EP_State_IDLE; - m_state2_xr <= EP_State_IDLE; - end - if (cyc==2) begin - if (m_stateAscii_xr != "idle ") $stop; - m_state_xr <= EP_State_CMDSHIFT13; - if (m_state2_xr != EP_State_IDLE) $stop; - m_state2_xr <= EP_State_CMDSHIFT13; - end - if (cyc==3) begin - if (m_stateAscii_xr != "cmdshift13") $stop; - m_state_xr <= EP_State_CMDSHIFT16; - if (m_state2_xr != EP_State_CMDSHIFT13) $stop; - m_state2_xr <= EP_State_CMDSHIFT16; - end - if (cyc==4) begin - if (m_stateAscii_xr != "cmdshift16") $stop; - m_state_xr <= EP_State_DWAIT; - if (m_state2_xr != EP_State_CMDSHIFT16) $stop; - m_state2_xr <= EP_State_DWAIT; - end - if (cyc==9) begin - if (m_stateAscii_xr != "dwait ") $stop; - if (m_state2_xr != EP_State_DWAIT) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc == 1) begin + m_state_xr <= EP_State_IDLE; + m_state2_xr <= EP_State_IDLE; end - end + if (cyc == 2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + if (m_state2_xr != EP_State_IDLE) $stop; + m_state2_xr <= EP_State_CMDSHIFT13; + end + if (cyc == 3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + if (m_state2_xr != EP_State_CMDSHIFT13) $stop; + m_state2_xr <= EP_State_CMDSHIFT16; + end + if (cyc == 4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + if (m_state2_xr != EP_State_CMDSHIFT16) $stop; + m_state2_xr <= EP_State_DWAIT; + end + if (cyc == 9) begin + if (m_stateAscii_xr != "dwait ") $stop; + if (m_state2_xr != EP_State_DWAIT) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index 64a73ec09..c8fbb2a16 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -4,54 +4,54 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef enum { - E01 = 'h1, - ELARGE = 'hf00d - } my_t; + typedef enum { + E01 = 'h1, + ELARGE = 'hf00d + } my_t; - integer cyc = 0; - my_t e; + integer cyc = 0; + my_t e; - string all; + string all; - // Check runtime - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - e <= E01; - end - else if (cyc==1) begin - `checks(e.name, "E01"); - `checkh(e.next, ELARGE); - e <= ELARGE; - end - else if (cyc==3) begin - `checks(e.name, "ELARGE"); - `checkh(e.next, E01); - `checkh(e.prev, E01); - e <= E01; - end - else if (cyc==20) begin - e <= my_t'('h11); // Unknown - end - else if (cyc==21) begin - `checks(e.name, ""); // Unknown - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Check runtime + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + e <= E01; + end + else if (cyc == 1) begin + `checks(e.name, "E01"); + `checkh(e.next, ELARGE); + e <= ELARGE; + end + else if (cyc == 3) begin + `checks(e.name, "ELARGE"); + `checkh(e.next, E01); + `checkh(e.prev, E01); + e <= E01; + end + else if (cyc == 20) begin + e <= my_t'('h11); // Unknown + end + else if (cyc == 21) begin + `checks(e.name, ""); // Unknown + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index de05825a5..c2109bffc 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -5,28 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 package our_pkg; - typedef enum logic [8-1:0] { - ADC_IN2IN = 8'h99, - ADC_IMMED = 8'h88, - ADC_INDIR = 8'h86, - ADC_INIDX = 8'h97 - } T_Opcode; + typedef enum logic [8-1:0] { + ADC_IN2IN = 8'h99, + ADC_IMMED = 8'h88, + ADC_INDIR = 8'h86, + ADC_INIDX = 8'h97 + } T_Opcode; endpackage : our_pkg module t; - our our (); + our our (); endmodule module our import our_pkg::*; - (); +(); - T_Opcode IR = ADC_IN2IN; + T_Opcode IR = ADC_IN2IN; - initial begin - $write ("%s (%t)\n", IR.name, $realtime); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("%s (%t)\n", IR.name, $realtime); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_name3.v b/test_regress/t/t_enum_name3.v index ca0d2e0f0..ea48e6612 100644 --- a/test_regress/t/t_enum_name3.v +++ b/test_regress/t/t_enum_name3.v @@ -7,18 +7,19 @@ // bug855 module our; - typedef enum logic {n,N} T_Flg_N; + typedef enum logic { + n, + N + } T_Flg_N; - typedef struct packed { - T_Flg_N N; - } T_PS_Reg; + typedef struct packed {T_Flg_N N;} T_PS_Reg; - T_PS_Reg PS = 1'b1; + T_PS_Reg PS = 1'b1; - initial begin - $write ("P:%s\n", PS.N.name); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("P:%s\n", PS.N.name); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_name_sformatf.v b/test_regress/t/t_enum_name_sformatf.v index 345c0862f..d50cf6e30 100644 --- a/test_regress/t/t_enum_name_sformatf.v +++ b/test_regress/t/t_enum_name_sformatf.v @@ -4,32 +4,35 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) (); - typedef enum logic [1:0] { - FOO = enum_param, - BAR, - BAZ - } enum_t; - enum_t the_enum = enum_t'(1); +module sub #( + parameter int param_a, + parameter bit [1:0] enum_param = '0 +) (); + typedef enum logic [1:0] { + FOO = enum_param, + BAR, + BAZ + } enum_t; + enum_t the_enum = enum_t'(1); - initial $display("%s", the_enum.name()); + initial $display("%s", the_enum.name()); endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - sub #(.param_a(1)) the_sub1(); - sub #(.param_a(2)) the_sub2(); - sub #(.param_a(2), .enum_param(2'd1)) the_sub3(); + sub #(.param_a(1)) the_sub1 (); + sub #(.param_a(2)) the_sub2 (); + sub #( + .param_a(2), + .enum_param(2'd1) + ) the_sub3 (); endmodule diff --git a/test_regress/t/t_enum_overlap_bad.out b/test_regress/t/t_enum_overlap_bad.out index 381685727..1e78e8b12 100644 --- a/test_regress/t/t_enum_overlap_bad.out +++ b/test_regress/t/t_enum_overlap_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_enum_overlap_bad.v:12:11: Overlapping enumeration value: 'e1b' - : ... note: In instance 't' - 12 | e1b=1 - | ^~~ - t/t_enum_overlap_bad.v:10:11: ... Location of original declaration - 10 | e1, - | ^~ +%Error: t/t_enum_overlap_bad.v:13:5: Overlapping enumeration value: 'e1b' + : ... note: In instance 't' + 13 | e1b = 1 + | ^~~ + t/t_enum_overlap_bad.v:11:5: ... Location of original declaration + 11 | e1, + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_enum_overlap_bad.v b/test_regress/t/t_enum_overlap_bad.v index d61197640..831e1ab14 100644 --- a/test_regress/t/t_enum_overlap_bad.v +++ b/test_regress/t/t_enum_overlap_bad.v @@ -6,14 +6,15 @@ module t; - enum { e0, - e1, - e2, - e1b=1 - } BAD1; + enum { + e0, + e1, + e2, + e1b = 1 + } BAD1; - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_enum_param_class.v b/test_regress/t/t_enum_param_class.v index d710a0d33..1318e8bca 100644 --- a/test_regress/t/t_enum_param_class.v +++ b/test_regress/t/t_enum_param_class.v @@ -9,29 +9,30 @@ /// should be handled properly. class ClsParam #( - int A = 0 + int A = 0 ); - typedef enum int { - EN_A = A + 0, - EN_B = A + 1, - EN_C = A + 2 - } enums_t; + typedef enum int { + EN_A = A + 0, + EN_B = A + 1, + EN_C = A + 2 + } enums_t; - int val = EN_C; - function int test(); - return EN_C; - endfunction -endclass; + int val = EN_C; + function int test(); + return EN_C; + endfunction +endclass +; module t; - // localparam ENUM_VAL = ClsParam#(100)::EN_C; // TODO: Unsupported: dotted expressions in parameters - // $info("ENUM_VAL: %0d", ENUM_VAL); + // localparam ENUM_VAL = ClsParam#(100)::EN_C; // TODO: Unsupported: dotted expressions in parameters + // $info("ENUM_VAL: %0d", ENUM_VAL); - ClsParam#(100) cls = new; - initial begin - if (cls.test() != 102) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + ClsParam #(100) cls = new; + initial begin + if (cls.test() != 102) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index 7552280cc..7667bbfbc 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -5,37 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 package p3; - typedef enum logic [2:0] { - ZERO = 3'b0, - ONE = 3'b1 } e3_t /*verilator public*/; - typedef enum logic [2:0] { - TWO = 3'd2, - XES = 3'b?1? } has_x_t /*verilator public*/; + typedef enum logic [2:0] { + ZERO = 3'b0, + ONE = 3'b1 + } e3_t /*verilator public*/; + typedef enum logic [2:0] { + TWO = 3'd2, + XES = 3'b?1? + } has_x_t /*verilator public*/; endpackage package p62; - typedef enum logic [62:0] { - ZERO = '0, - ALLONE = '1 } e62_t /*verilator public*/; + typedef enum logic [62:0] { + ZERO = '0, + ALLONE = '1 + } e62_t /*verilator public*/; endpackage package pw; - typedef enum logic [99:0] { // Too wide for public - WIDE = 100'h123} ewide_t /*verilator public*/; + typedef enum logic [99:0] { // Too wide for public + WIDE = 100'h123 + } ewide_t /*verilator public*/; endpackage module t; - enum integer { - EI_A, - EI_B, - EI_C - } m_state; + enum integer { + EI_A, + EI_B, + EI_C + } m_state; - initial begin - m_state = EI_A; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + m_state = EI_A; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_size.v b/test_regress/t/t_enum_size.v index fb32336cf..0622b70eb 100644 --- a/test_regress/t/t_enum_size.v +++ b/test_regress/t/t_enum_size.v @@ -6,31 +6,42 @@ module t; - // verilator lint_off WIDTH - typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs; + // verilator lint_off WIDTH + typedef enum logic [2:0] { + P = 0, + W = 1'b1, + E, + N, + S + } Dirs; - typedef enum integer {UP=0, UW=1'b1} UNSIZED; - // verilator lint_on WIDTH + typedef enum integer { + UP = 0, + UW = 1'b1 + } UNSIZED; + // verilator lint_on WIDTH - localparam LEN = 3; - localparam COL = 4; + localparam LEN = 3; + localparam COL = 4; - localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P) - ,LEN'(S), LEN'(E), LEN'(W), LEN'(P) - ,LEN'(S), LEN'(N), LEN'(W), LEN'(P) - ,LEN'(S), LEN'(N), LEN'(E), LEN'(P) - ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)}; + // verilog_format: off + localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(E), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(E), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)}; - bit [59:0] SE2 = {N, E, W, P - ,S, E, W, P - ,S, N, W, P - ,S, N, E, P - ,S, N, E, W}; + bit [59:0] SE2 = {N, E, W, P + ,S, E, W, P + ,S, N, W, P + ,S, N, E, P + ,S, N, E, W}; + // verilog_format: on - initial begin - if (SEQ != 60'o32104210431043204321) $stop; - if (SE2 != 60'o32104210431043204321) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (SEQ != 60'o32104210431043204321) $stop; + if (SE2 != 60'o32104210431043204321) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_type_bad.out b/test_regress/t/t_enum_type_bad.out index af755cc3f..ce73b61d2 100644 --- a/test_regress/t/t_enum_type_bad.out +++ b/test_regress/t/t_enum_type_bad.out @@ -1,17 +1,17 @@ -%Error-ENUMVALUE: t/t_enum_type_bad.v:28:11: Implicit conversion to enum 'enum{}t.e_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) - : ... note: In instance 't' +%Error-ENUMVALUE: t/t_enum_type_bad.v:36:9: Implicit conversion to enum 'enum{}t.e_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) + : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast - 28 | e = 1; - | ^ + 36 | e = 1; + | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest -%Error-ENUMVALUE: t/t_enum_type_bad.v:29:11: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) +%Error-ENUMVALUE: t/t_enum_type_bad.v:37:9: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) + : ... note: In instance 't' + : ... Suggest use enum's mnemonic, or static cast + 37 | o = e; + | ^ +%Error-ENUMVALUE: t/t_enum_type_bad.v:43:13: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast - 29 | o = e; - | ^ -%Error-ENUMVALUE: t/t_enum_type_bad.v:35:15: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) - : ... note: In instance 't' - : ... Suggest use enum's mnemonic, or static cast - 35 | o = str.m_e; - | ^~~ + 43 | o = str.m_e; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_enum_type_bad.v b/test_regress/t/t_enum_type_bad.v index 29e4f9c96..0d97c7f03 100644 --- a/test_regress/t/t_enum_type_bad.v +++ b/test_regress/t/t_enum_type_bad.v @@ -6,33 +6,41 @@ module t; - typedef enum {ZERO, ONE, TWO} e_t; + typedef enum { + ZERO, + ONE, + TWO + } e_t; - typedef enum {THREE=3, FOUR, FIVE} o_t; + typedef enum { + THREE = 3, + FOUR, + FIVE + } o_t; - typedef struct packed { - e_t m_e; - o_t m_o; - } struct_t; + typedef struct packed { + e_t m_e; + o_t m_o; + } struct_t; - initial begin - e_t e; - o_t o; - struct_t str; + initial begin + e_t e; + o_t o; + struct_t str; - e = ONE; - e = $random() == 0 ? ONE : TWO; - e = e_t'(1); - e = e; + e = ONE; + e = $random() == 0 ? ONE : TWO; + e = e_t'(1); + e = e; - e = 1; // Bad - o = e; // Bad + e = 1; // Bad + o = e; // Bad - str.m_e = ONE; - str.m_o = THREE; - e = str.m_e; - o = str.m_o; - o = str.m_e; // Bad + str.m_e = ONE; + str.m_o = THREE; + e = str.m_e; + o = str.m_o; + o = str.m_e; // Bad - end + end endmodule diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v index 40d21298c..210c668a5 100644 --- a/test_regress/t/t_enum_type_methods.v +++ b/test_regress/t/t_enum_type_methods.v @@ -4,102 +4,102 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk + ); - typedef enum [3:0] { - E01 = 1, - E03 = 3, - E04 = 4 - } my_t; + typedef enum [3:0] { + E01 = 1, + E03 = 3, + E04 = 4 + } my_t; - integer cyc = 0; - my_t e; + integer cyc = 0; + my_t e; - int arrayfits [e.num]; // Check can use as constant + int arrayfits [e.num]; // Check can use as constant - string all; + string all; - // Check constification - initial begin - e = E03; - `checkh(e.first, E01); - `checkh(e.last, E04); - `checkh(e.last(), E04); + // Check constification + initial begin + e = E03; + `checkh(e.first, E01); + `checkh(e.last, E04); + `checkh(e.last(), E04); + `checkh(e.next, E04); + `checkh(e.next(), E04); + `checkh(e.next(1), E04); + `checkh(e.next(1).next(1), E01); + `checkh(e.next(2), E01); + `checkh(e.next(1).next(1).next(1), E03); + `checkh(e.next(1).next(2), E03); + `checkh(e.next(THREE), E03); + `checkh(e.prev, E01); + `checkh(e.prev(1), E01); + `checkh(e.prev(1).prev(1), E04); + `checkh(e.prev(2), E04); + `checkh(e.num, 3); + `checks(e.name, "E03"); + // + all = ""; + for (my_t e = e.first; e != e.last; e = e.next) begin + all = {all, e.name}; + end + e = e.last; + all = {all, e.name}; + `checks(all, "E01E03E04"); + end + + localparam THREE = 3; + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + e <= E01; + end + else if (cyc==1) begin + `checks(e.name, "E01"); + `checkh(e.next, E03); + `checkh(e.next(1), E03); + `checkh(e.next(2), E04); + `checkh(e.prev, E04); + `checkh(e.prev(1), E04); + `checkh(e.prev(2), E03); + e <= E03; + end + else if (cyc==2) begin + `checks(e.name, "E03"); `checkh(e.next, E04); - `checkh(e.next(), E04); `checkh(e.next(1), E04); - `checkh(e.next(1).next(1), E01); `checkh(e.next(2), E01); - `checkh(e.next(1).next(1).next(1), E03); - `checkh(e.next(1).next(2), E03); - `checkh(e.next(THREE), E03); `checkh(e.prev, E01); `checkh(e.prev(1), E01); - `checkh(e.prev(1).prev(1), E04); `checkh(e.prev(2), E04); - `checkh(e.num, 3); - `checks(e.name, "E03"); - // - all = ""; - for (my_t e = e.first; e != e.last; e = e.next) begin - all = {all, e.name}; - end - e = e.last; - all = {all, e.name}; - `checks(all, "E01E03E04"); - end - - localparam THREE = 3; - - // Check runtime - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - e <= E01; - end - else if (cyc==1) begin - `checks(e.name, "E01"); - `checkh(e.next, E03); - `checkh(e.next(1), E03); - `checkh(e.next(2), E04); - `checkh(e.prev, E04); - `checkh(e.prev(1), E04); - `checkh(e.prev(2), E03); - e <= E03; - end - else if (cyc==2) begin - `checks(e.name, "E03"); - `checkh(e.next, E04); - `checkh(e.next(1), E04); - `checkh(e.next(2), E01); - `checkh(e.prev, E01); - `checkh(e.prev(1), E01); - `checkh(e.prev(2), E04); - e <= E04; - end - else if (cyc==3) begin - `checks(e.name, "E04"); - `checkh(e.next, E01); - `checkh(e.next(1), E01); - `checkh(e.next(2), E03); - `checkh(e.prev, E03); - `checkh(e.prev(1), E03); - `checkh(e.prev(2), E01); - e <= E01; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + e <= E04; + end + else if (cyc==3) begin + `checks(e.name, "E04"); + `checkh(e.next, E01); + `checkh(e.next(1), E01); + `checkh(e.next(2), E03); + `checkh(e.prev, E03); + `checkh(e.prev(1), E03); + `checkh(e.prev(2), E01); + e <= E01; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_enum_type_methods_bad.out b/test_regress/t/t_enum_type_methods_bad.out index 5b492d26c..661115e35 100644 --- a/test_regress/t/t_enum_type_methods_bad.out +++ b/test_regress/t/t_enum_type_methods_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_enum_type_methods_bad.v:24:14: Unsupported: enum next/prev with non-constant argument +%Error-UNSUPPORTED: t/t_enum_type_methods_bad.v:24:12: Unsupported: enum next/prev with non-constant argument : ... note: In instance 't' - 24 | e.next(increment); - | ^~~~~~~~~ + 24 | e.next(increment); + | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_enum_type_methods_bad.v b/test_regress/t/t_enum_type_methods_bad.v index e365800df..ef2e916fa 100644 --- a/test_regress/t/t_enum_type_methods_bad.v +++ b/test_regress/t/t_enum_type_methods_bad.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk, increment - ); - input clk; - input [1:0] increment; + // Inputs + clk, increment + ); + input clk; + input [1:0] increment; - typedef enum [3:0] { - E01 = 1, - E03 = 3, - E04 = 4, - E05 = 5 - } my_t; + typedef enum [3:0] { + E01 = 1, + E03 = 3, + E04 = 4, + E05 = 5 + } my_t; - my_t e; + my_t e; - always @ (posedge clk) begin - e.next(increment); - $finish; - end + always @ (posedge clk) begin + e.next(increment); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_type_nomethod_bad.out b/test_regress/t/t_enum_type_nomethod_bad.out index 5facbff42..f9a610ccf 100644 --- a/test_regress/t/t_enum_type_nomethod_bad.out +++ b/test_regress/t/t_enum_type_nomethod_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_enum_type_nomethod_bad.v:15:9: Unknown built-in enum method 'bad_no_such_method' +%Error: t/t_enum_type_nomethod_bad.v:15:7: Unknown built-in enum method 'bad_no_such_method' : ... note: In instance 't' - 15 | e.bad_no_such_method(); - | ^~~~~~~~~~~~~~~~~~ + 15 | e.bad_no_such_method(); + | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_enum_type_nomethod_bad.v b/test_regress/t/t_enum_type_nomethod_bad.v index 15232b5d1..0f09af078 100644 --- a/test_regress/t/t_enum_type_nomethod_bad.v +++ b/test_regress/t/t_enum_type_nomethod_bad.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - typedef enum [3:0] { - E01 = 1 - } my_t; + typedef enum [3:0] { + E01 = 1 + } my_t; - my_t e; + my_t e; - initial begin - e.bad_no_such_method(); - $stop; - end + initial begin + e.bad_no_such_method(); + $stop; + end endmodule diff --git a/test_regress/t/t_enum_type_pins.v b/test_regress/t/t_enum_type_pins.v index d8ee48e4c..f6b5ac940 100644 --- a/test_regress/t/t_enum_type_pins.v +++ b/test_regress/t/t_enum_type_pins.v @@ -11,6 +11,7 @@ // **** Pin Identifiers **** +// verilog_format: off typedef enum int { PINID_A0 = 32'd0, // MUST BE ZERO! @@ -43,63 +44,62 @@ typedef enum int // - Maximum number of pins - PINID_MAX } t_pinid; +// verilog_format: on +module t ( + input clk +); -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + wire a = clk; + wire b = 1'b0; + reg c; - wire a = clk; - wire b = 1'b0; - reg c; + test test_i ( /*AUTOINST*/ + // Inputs + .clk(clk) + ); - test test_i (/*AUTOINST*/ - // Inputs - .clk (clk)); - - // This is a compile time only test. Immediately finish - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // This is a compile time only test. Immediately finish + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module test (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module test ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - // Use the enumeration size to initialize a dynamic array - t_pinid e; - int myarray1 [] = new [e.num]; + // Use the enumeration size to initialize a dynamic array + t_pinid e; + int myarray1[] = new[e.num]; - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Enumeration has %d members\n", e.num); + $write("Enumeration has %d members\n", e.num); `endif - e = e.first; + e = e.first; - forever begin - myarray1[e] = e.prev; + forever begin + myarray1[e] = e.prev; `ifdef TEST_VERBOSE - $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); + $write("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); `endif - if (e == e.last) begin - break; - end - else begin - e = e.next; - end + if (e == e.last) begin + break; end - end + else begin + e = e.next; + end + end + end endmodule diff --git a/test_regress/t/t_enum_value_assign.v b/test_regress/t/t_enum_value_assign.v index fa71fd4f4..2f8033a7c 100644 --- a/test_regress/t/t_enum_value_assign.v +++ b/test_regress/t/t_enum_value_assign.v @@ -6,34 +6,38 @@ module t; - localparam logic [9:0] V2 = (1 << 2); - localparam logic [9:0] V1 = (1 << 1); - localparam logic [9:0] V0 = (1 << 0); - typedef enum logic [9:0] { - ZERO = '0, - VAL0 = V0, - VAL1 = V1, - VAL01 = V0 | V1 - } enum_t; + localparam logic [9:0] V2 = (1 << 2); + localparam logic [9:0] V1 = (1 << 1); + localparam logic [9:0] V0 = (1 << 0); + typedef enum logic [9:0] { + ZERO = '0, + VAL0 = V0, + VAL1 = V1, + VAL01 = V0 | V1 + } enum_t; - localparam enum_t PARAMVAL1 = VAL1; - localparam enum_t PARAMVAL1CONST = enum_t'(2); + localparam enum_t PARAMVAL1 = VAL1; + localparam enum_t PARAMVAL1CONST = enum_t'(2); - typedef enum {I_ZERO, I_ONE, I_TWO} inte_t; - localparam inte_t I_PARAM = inte_t'(1); + typedef enum { + I_ZERO, + I_ONE, + I_TWO + } inte_t; + localparam inte_t I_PARAM = inte_t'(1); - initial begin - enum_t e; - e = VAL01; - if (e != VAL01) $stop; + initial begin + enum_t e; + e = VAL01; + if (e != VAL01) $stop; - if (PARAMVAL1 != VAL1) $stop; - if (PARAMVAL1CONST != VAL1) $stop; + if (PARAMVAL1 != VAL1) $stop; + if (PARAMVAL1CONST != VAL1) $stop; - if (I_PARAM != I_ONE) $stop; + if (I_PARAM != I_ONE) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_enum_x_bad.out b/test_regress/t/t_enum_x_bad.out index fc848284c..25c10c2f2 100644 --- a/test_regress/t/t_enum_x_bad.out +++ b/test_regress/t/t_enum_x_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_enum_x_bad.v:9:21: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2023 6.19) +%Error: t/t_enum_x_bad.v:9:19: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2023 6.19) : ... note: In instance 't' - 9 | enum bit [1:0] { BADX = 2'b1x } BAD1; - | ^~~~ + 9 | enum bit [1:0] {BADX = 2'b1x} BAD1; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_enum_x_bad.v:12:23: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2023 6.19) - : ... note: In instance 't' - 12 | e1 - | ^~ +%Error: t/t_enum_x_bad.v:13:5: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2023 6.19) + : ... note: In instance 't' + 13 | e1 + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_enum_x_bad.v b/test_regress/t/t_enum_x_bad.v index b3fdaca91..8a851d906 100644 --- a/test_regress/t/t_enum_x_bad.v +++ b/test_regress/t/t_enum_x_bad.v @@ -6,14 +6,15 @@ module t; - enum bit [1:0] { BADX = 2'b1x } BAD1; + enum bit [1:0] {BADX = 2'b1x} BAD1; - enum logic [3:0] { e0 = 4'b1xx1, - e1 - } BAD2; + enum logic [3:0] { + e0 = 4'b1xx1, + e1 + } BAD2; - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_enumeration.v b/test_regress/t/t_enumeration.v index 9af1c18eb..d1ecc4f25 100644 --- a/test_regress/t/t_enumeration.v +++ b/test_regress/t/t_enumeration.v @@ -4,274 +4,272 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +// verilog_format: off +module t ( + input clk +); - input clk; + integer cnt = 0; + integer mod = 0; - integer cnt = 0; - integer mod = 0; + // event counter + always @ (posedge clk) + if (cnt==20) begin + cnt <= 0; + mod <= mod + 1; + end else begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) - if (cnt==20) begin - cnt <= 0; - mod <= mod + 1; - end else begin - cnt <= cnt + 1; - end + // finish report + always @ (posedge clk) + if (mod==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) - if (mod==3) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // anonymous type variable declaration + enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; - // anonymous type variable declaration - enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; + // named type + typedef enum logic {OFF, ON} t_switch; + t_switch switch; - // named type - typedef enum logic {OFF, ON} t_switch; - t_switch switch; + // numbering examples + enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; - // numbering examples - enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.first(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + // if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + end - // test of raibow7 type - always @ (posedge clk) - if (mod==0) begin - // write value to array - if (cnt== 0) begin - rainbow7 <= rainbow7.first(); - // check number - if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end - // if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end - end - else if (cnt== 1) begin - if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 2) begin - if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 3) begin - if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 4) begin - if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 5) begin - if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 6) begin - if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 7) begin - if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - else if (cnt== 8) begin - if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.next(); - end - end else if (mod==1) begin - // write value to array - if (cnt== 0) begin - rainbow7 <= rainbow7.last(); - // check number - if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end - end - else if (cnt== 1) begin - if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 2) begin - if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 3) begin - if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 4) begin - if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 5) begin - if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 6) begin - if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 7) begin - if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - else if (cnt== 8) begin - if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end - if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end - rainbow7 <= rainbow7.prev(); - end - end + // test of t_switch type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + switch <= switch.first(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + // if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 2) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 3) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 2) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 3) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + end - // test of t_switch type - always @ (posedge clk) - if (mod==0) begin - // write value to array - if (cnt== 0) begin - switch <= switch.first(); - // check number - if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end - // if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end - end - else if (cnt== 1) begin - if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end - if (switch !== OFF ) begin $display("%b", switch ); $stop(); end - switch <= switch.next(); - end - else if (cnt== 2) begin - if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end - if (switch !== ON ) begin $display("%b", switch ); $stop(); end - switch <= switch.next(); - end - else if (cnt== 3) begin - if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end - if (switch !== OFF ) begin $display("%b", switch ); $stop(); end - switch <= switch.next(); - end - end else if (mod==1) begin - // write value to array - if (cnt== 0) begin - rainbow7 <= rainbow7.last(); - // check number - if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end - end - else if (cnt== 1) begin - if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end - if (switch !== ON ) begin $display("%b", switch ); $stop(); end - switch <= switch.prev(); - end - else if (cnt== 2) begin - if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end - if (switch !== OFF ) begin $display("%b", switch ); $stop(); end - switch <= switch.prev(); - end - else if (cnt== 3) begin - if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end - if (switch !== ON ) begin $display("%b", switch ); $stop(); end - switch <= switch.prev(); - end - end - - // test of raibow7 type - always @ (posedge clk) - if (mod==0) begin - // write value to array - if (cnt== 0) begin - family <= family.first(); - // check number - if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end - // if (family !== 32'dx ) begin $display("%b", family ); $stop(); end - end - else if (cnt== 1) begin - if (family !== 0 ) begin $display("%b", family ); $stop(); end - if (family !== father ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 2) begin - if (family !== 1 ) begin $display("%b", family ); $stop(); end - if (family !== mother ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 3) begin - if (family !== 2 ) begin $display("%b", family ); $stop(); end - if (family !== son0 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 4) begin - if (family !== 3 ) begin $display("%b", family ); $stop(); end - if (family !== son1 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 5) begin - if (family !== 4 ) begin $display("%b", family ); $stop(); end - if (family !== daughter ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 6) begin - if (family !== 5 ) begin $display("%b", family ); $stop(); end - if (family !== gerbil ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 7) begin - if (family !== 10 ) begin $display("%b", family ); $stop(); end - if (family !== dog0 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 8) begin - if (family !== 11 ) begin $display("%b", family ); $stop(); end - if (family !== dog1 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 9) begin - if (family !== 12 ) begin $display("%b", family ); $stop(); end - if (family !== dog2 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 10) begin - if (family !== 20 ) begin $display("%b", family ); $stop(); end - if (family !== cat3 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 11) begin - if (family !== 21 ) begin $display("%b", family ); $stop(); end - if (family !== cat4 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 12) begin - if (family !== 22 ) begin $display("%b", family ); $stop(); end - if (family !== cat5 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 13) begin - if (family !== 30 ) begin $display("%b", family ); $stop(); end - if (family !== car3 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 14) begin - if (family !== 31 ) begin $display("%b", family ); $stop(); end - if (family !== car2 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - else if (cnt== 15) begin - if (family !== 32 ) begin $display("%b", family ); $stop(); end - if (family !== car1 ) begin $display("%b", family ); $stop(); end - family <= family.next(); - end - end + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + family <= family.first(); + // check number + if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end + // if (family !== 32'dx ) begin $display("%b", family ); $stop(); end + end + else if (cnt== 1) begin + if (family !== 0 ) begin $display("%b", family ); $stop(); end + if (family !== father ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 2) begin + if (family !== 1 ) begin $display("%b", family ); $stop(); end + if (family !== mother ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 3) begin + if (family !== 2 ) begin $display("%b", family ); $stop(); end + if (family !== son0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 4) begin + if (family !== 3 ) begin $display("%b", family ); $stop(); end + if (family !== son1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 5) begin + if (family !== 4 ) begin $display("%b", family ); $stop(); end + if (family !== daughter ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 6) begin + if (family !== 5 ) begin $display("%b", family ); $stop(); end + if (family !== gerbil ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 7) begin + if (family !== 10 ) begin $display("%b", family ); $stop(); end + if (family !== dog0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 8) begin + if (family !== 11 ) begin $display("%b", family ); $stop(); end + if (family !== dog1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 9) begin + if (family !== 12 ) begin $display("%b", family ); $stop(); end + if (family !== dog2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 10) begin + if (family !== 20 ) begin $display("%b", family ); $stop(); end + if (family !== cat3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 11) begin + if (family !== 21 ) begin $display("%b", family ); $stop(); end + if (family !== cat4 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 12) begin + if (family !== 22 ) begin $display("%b", family ); $stop(); end + if (family !== cat5 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 13) begin + if (family !== 30 ) begin $display("%b", family ); $stop(); end + if (family !== car3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 14) begin + if (family !== 31 ) begin $display("%b", family ); $stop(); end + if (family !== car2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 15) begin + if (family !== 32 ) begin $display("%b", family ); $stop(); end + if (family !== car1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + end endmodule diff --git a/test_regress/t/t_eq_wild.v b/test_regress/t/t_eq_wild.v index 3a5f53a10..cb1014dfc 100644 --- a/test_regress/t/t_eq_wild.v +++ b/test_regress/t/t_eq_wild.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 function bit get_1_or_0(bit get_1); - return get_1 ? 1'b1 : 1'b0; + return get_1 ? 1'b1 : 1'b0; endfunction module t; - initial begin - if (get_1_or_0(0) ==? get_1_or_0(1)) $stop; - if (!(get_1_or_0(0) !=? get_1_or_0(1))) $stop; + initial begin + if (get_1_or_0(0) ==? get_1_or_0(1)) $stop; + if (!(get_1_or_0(0) !=? get_1_or_0(1))) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_eq_wild_unsup.out b/test_regress/t/t_eq_wild_unsup.out index 94c1a1f65..139f2b6f2 100644 --- a/test_regress/t/t_eq_wild_unsup.out +++ b/test_regress/t/t_eq_wild_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_eq_wild_unsup.v:13:13: Unsupported: RHS of ==? or !=? is fourstate but not a constant +%Error-UNSUPPORTED: t/t_eq_wild_unsup.v:13:11: Unsupported: RHS of ==? or !=? is fourstate but not a constant : ... note: In instance 't' - 13 | if (1 ==? get_x_or_0(0)) $stop; - | ^~~ + 13 | if (1 ==? get_x_or_0(0)) $stop; + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_eq_wild_unsup.v b/test_regress/t/t_eq_wild_unsup.v index 8530cac45..b1d91a66c 100644 --- a/test_regress/t/t_eq_wild_unsup.v +++ b/test_regress/t/t_eq_wild_unsup.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 function logic get_x_or_0(logic get_x); - return get_x ? 1'bx : 1'b0; + return get_x ? 1'bx : 1'b0; endfunction module t; - initial begin - if (1 ==? get_x_or_0(0)) $stop; + initial begin + if (1 ==? get_x_or_0(0)) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_event.v b/test_regress/t/t_event.v index d434ee958..5fbb287cc 100644 --- a/test_regress/t/t_event.v +++ b/test_regress/t/t_event.v @@ -5,78 +5,76 @@ // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE - `define WRITE_VERBOSE(args) $write args +`define WRITE_VERBOSE(args) $write args `else - `define WRITE_VERBOSE(args) +`define WRITE_VERBOSE(args) `endif -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - event e1; - event e2; - event e3; + event e1; + event e2; + event e3; `ifndef IVERILOG - event ev [3:0]; + event ev[3:0]; `endif - int cyc = 0; + int cyc = 0; - int last_event = 0; - always @(e1) begin - `WRITE_VERBOSE(("[%0t] e1\n", $time)); - if (!e1.triggered) $stop; - last_event[1] = 1; - end + int last_event = 0; + always @(e1) begin + `WRITE_VERBOSE(("[%0t] e1\n", $time)); + if (!e1.triggered) $stop; + last_event[1] = 1; + end - always @(e2) begin - `WRITE_VERBOSE(("[%0t] e2\n", $time)); - if (!e2.triggered) $stop; - last_event[2] = 1; - end + always @(e2) begin + `WRITE_VERBOSE(("[%0t] e2\n", $time)); + if (!e2.triggered) $stop; + last_event[2] = 1; + end - always @(posedge clk) begin - `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); - cyc <= cyc + 1; - case (cyc) - default: begin - // Check no initial or spurious trigger - if (last_event != 0) $stop; - end - // - 10: begin - if (last_event != 0) $stop; - -> e1; - if (!e1.triggered) $stop; - if (e3.triggered) $stop; - -> e3; - if (!e3.triggered) $stop; - end - 11: begin - if (last_event != 32'b10) $stop; - last_event = 0; - if (e3.triggered) $stop; - end - // - 13: begin - if (last_event != 0) $stop; - ->> e2; - if (e2.triggered) $stop; - if (e3.triggered) $stop; - end - 14: begin - if (last_event != 32'b100) $stop; - last_event = 0; - end - // - 99: begin - $write("*-* All Finished *-*\n"); - $finish; - end - endcase - end + always @(posedge clk) begin + `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); + cyc <= cyc + 1; + case (cyc) + default: begin + // Check no initial or spurious trigger + if (last_event != 0) $stop; + end + // + 10: begin + if (last_event != 0) $stop; + ->e1; + if (!e1.triggered) $stop; + if (e3.triggered) $stop; + ->e3; + if (!e3.triggered) $stop; + end + 11: begin + if (last_event != 32'b10) $stop; + last_event = 0; + if (e3.triggered) $stop; + end + // + 13: begin + if (last_event != 0) $stop; + ->>e2; + if (e2.triggered) $stop; + if (e3.triggered) $stop; + end + 14: begin + if (last_event != 32'b100) $stop; + last_event = 0; + end + // + 99: begin + $write("*-* All Finished *-*\n"); + $finish; + end + endcase + end endmodule diff --git a/test_regress/t/t_event_class_fire.out b/test_regress/t/t_event_class_fire.out index a8c183b95..92da8fc18 100644 --- a/test_regress/t/t_event_class_fire.out +++ b/test_regress/t/t_event_class_fire.out @@ -1,5 +1,5 @@ -%Error: Internal Error: t/t_event_class_fire.v:10:7: ../V3Delayed.cpp:#: No active to handle FireEvent +%Error: Internal Error: t/t_event_class_fire.v:10:5: ../V3Delayed.cpp:#: No active to handle FireEvent : ... note: In instance '$unit::Cls' - 10 | ->> e; - | ^~~ + 10 | ->>e; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_event_class_fire.v b/test_regress/t/t_event_class_fire.v index 8a7408b5f..af39bda45 100644 --- a/test_regress/t/t_event_class_fire.v +++ b/test_regress/t/t_event_class_fire.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - event e; - task trig_e(); - ->> e; - endtask + event e; + task trig_e(); + ->>e; + endtask endclass -module top(); - event e; - initial begin - Cls c; - c = new; - c.trig_e(); - wait(e.triggered); - $write("*-* All Finished *-*\n"); - $finish; - end +module top (); + event e; + initial begin + Cls c; + c = new; + c.trig_e(); + wait (e.triggered); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_event_control.out b/test_regress/t/t_event_control.out index 2debb40b8..a4f490048 100644 --- a/test_regress/t/t_event_control.out +++ b/test_regress/t/t_event_control.out @@ -1,12 +1,12 @@ -%Error-NOTIMING: t/t_event_control.v:14:7: Event control statement in this location requires --timing +%Error-NOTIMING: t/t_event_control.v:12:5: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 14 | @(clk); - | ^ + 12 | @(clk); + | ^ ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Error-NOTIMING: t/t_event_control.v:16:7: Event control statement in this location requires --timing +%Error-NOTIMING: t/t_event_control.v:14:5: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure - 16 | @(clk); - | ^ + 14 | @(clk); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_event_control.v b/test_regress/t/t_event_control.v index 806d00b62..6912e3185 100644 --- a/test_regress/t/t_event_control.v +++ b/test_regress/t/t_event_control.v @@ -4,19 +4,17 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - initial begin - @(clk); - $write("[%0t] Got\n", $time); - @(clk); - $write("[%0t] Got\n", $time); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + @(clk); + $write("[%0t] Got\n", $time); + @(clk); + $write("[%0t] Got\n", $time); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_event_control_assign.v b/test_regress/t/t_event_control_assign.v index 4d97ab5ba..40dad8d35 100644 --- a/test_regress/t/t_event_control_assign.v +++ b/test_regress/t/t_event_control_assign.v @@ -15,7 +15,9 @@ module t; task automatic send_evt(); fork - #10 begin ->evt1; end + #10 begin + ->evt1; + end begin event new_event; #20; @@ -30,10 +32,12 @@ module t; endtask task wait_for_event(); - fork begin - @evt1 $display("Received evt1"); - evt_recv_cnt++; - end join_none + fork + begin + @evt1 $display("Received evt1"); + evt_recv_cnt++; + end + join_none endtask endclass @@ -51,16 +55,12 @@ module t; foo1.send_evt(); #90; $display("- end of iteration -"); - if (evt_recv_cnt != i + 1) - $stop; - if (new_evt_recv_cnt != i) - $stop; + if (evt_recv_cnt != i + 1) $stop; + if (new_evt_recv_cnt != i) $stop; end - if (evt_recv_cnt != 4) - $stop; - if (new_evt_recv_cnt != 3) - $stop; + if (evt_recv_cnt != 4) $stop; + if (new_evt_recv_cnt != 3) $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_event_control_expr.v b/test_regress/t/t_event_control_expr.v index 76dc78392..59260a830 100644 --- a/test_regress/t/t_event_control_expr.v +++ b/test_regress/t/t_event_control_expr.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else @@ -18,24 +19,25 @@ // `define EXPR_TEST(name, test_edges, inputs, expr) \ module t_``name inputs; \ - logic[$bits(expr)-1:0] last = 0; \ - always @(expr) begin \ - if ($bits(expr) > 1) begin \ - `WRITE_VERBOSE(("[%0t] %s [changed] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ - end \ - if ($time > 0 && (expr) == last) $stop; \ - last <= expr; \ - end \ - generate if (test_edges) begin \ - always @(posedge expr) begin \ - `WRITE_VERBOSE(("[%0t] %s [posedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ - if ($time > 0 && ({1'b0, ~(expr)}[0] || last[0])) $stop; \ - end \ - always @(negedge expr) begin \ - `WRITE_VERBOSE(("[%0t] %s [negedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ - if ($time > 0 && ({1'b0, expr}[0] || ~last[0])) $stop; \ - end \ - end endgenerate \ + logic[$bits(expr)-1:0] last = 0; \ + always @(expr) begin \ + if ($bits(expr) > 1) begin \ + `WRITE_VERBOSE(("[%0t] %s [changed] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ + end \ + if ($time > 0 && (expr) == last) $stop; \ + last <= expr; \ + end \ + generate if (test_edges) begin \ + always @(posedge expr) begin \ + `WRITE_VERBOSE(("[%0t] %s [posedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ + if ($time > 0 && ({1'b0, ~(expr)}[0] || last[0])) $stop; \ + end \ + always @(negedge expr) begin \ + `WRITE_VERBOSE(("[%0t] %s [negedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ + if ($time > 0 && ({1'b0, expr}[0] || ~last[0])) $stop; \ + end \ + end \ + endgenerate \ endmodule `EXPR_TEST(xor, 1, (input a, b), b^a) @@ -60,18 +62,18 @@ function int id(int x); return x; endfunction `ifndef NO_CLASS `define CLASS_TEST(name, expr) \ module t_``name(input int k); \ - class Cls; \ - static int k; \ - function int get_k(); return k; endfunction \ - endclass \ - Cls obj = new; \ - assign obj.k = k; \ - int last = 0; \ - always @(expr) begin \ - `WRITE_VERBOSE(("[%0t] %s [changed] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ - if ($time > 0 && expr == last) $stop; \ - last <= expr; \ - end \ + class Cls; \ + static int k; \ + function int get_k(); return k; endfunction \ + endclass \ + Cls obj = new; \ + assign obj.k = k; \ + int last = 0; \ + always @(expr) begin \ + `WRITE_VERBOSE(("[%0t] %s [changed] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ + if ($time > 0 && expr == last) $stop; \ + last <= expr; \ + end \ endmodule `CLASS_TEST(class, obj.k) @@ -98,69 +100,67 @@ module t_cstmt; end endmodule -module t(/*AUTOARG*/ - // Inputs - clk +module t( + input clk ); - input clk; - logic a = 0, b = 0, c = 0; - t_xor u_xor(.*); - t_nand u_nand(.*); - t_concat1 u_concat1(.*); + logic a = 0, b = 0, c = 0; + t_xor u_xor(.*); + t_nand u_nand(.*); + t_concat1 u_concat1(.*); - logic[3:0] v = '0; - t_reduce u_reduce(.*); - t_concat2 u_concat2(.*); + logic[3:0] v = '0; + t_reduce u_reduce(.*); + t_concat2 u_concat2(.*); - int i = 0, j = 0; - t_add u_add(.*); - t_lt u_lt(.*); + int i = 0, j = 0; + t_add u_add(.*); + t_lt u_lt(.*); - int t[5] = {0, 1, 2, 3, 4}; - t_array u_array(.*); - t_array_complex u_array_complex(.*); + int t[5] = {0, 1, 2, 3, 4}; + t_array u_array(.*); + t_array_complex u_array_complex(.*); - int q[$]; - t_queue u_queue(.*); - t_queue_mul u_queue_mul(.*); + int q[$]; + t_queue u_queue(.*); + t_queue_mul u_queue_mul(.*); - t_func u_func(.*); + t_func u_func(.*); - int k; - assign k = i + j; - `ifndef NO_CLASS - t_class u_class(.*); - t_method u_method(.*); - `endif + int k; + assign k = i + j; + `ifndef NO_CLASS + t_class u_class(.*); + t_method u_method(.*); + `endif - t_cstmt u_cstmt(); + t_cstmt u_cstmt(); - int cyc = 0; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - // a, b, c - a <= ~a; - if (cyc % 2 == 0) b <= ~b; - else c <= ~c; - // v - if (cyc % 3 == 0) v[0] <= 1; - else v <= v << 1; - // i, j - i <= i + 2; - if (cyc % 2 == 0) j <= j + 4; - // t - t[cyc % 5] <= t[cyc % 5] + cyc; - // q - q.push_front(cyc); - `WRITE_VERBOSE(("[%0t] values: clk=%b, cyc=%0d, a=%b, b=%b, v=%b, i=%0x, j=%0x, t=[%0x, %0x, %0x, %0x, %0x], obj.k=%0x\n", - $time, clk, cyc, a, b, v, i, j, t[0], t[1], t[2], t[3], t[4], k)); - `WRITE_VERBOSE((" q=%p\n", q)); - if (cyc == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + // a, b, c + a <= ~a; + if (cyc % 2 == 0) b <= ~b; + else c <= ~c; + // v + if (cyc % 3 == 0) v[0] <= 1; + else v <= v << 1; + // i, j + i <= i + 2; + if (cyc % 2 == 0) j <= j + 4; + // t + t[cyc % 5] <= t[cyc % 5] + cyc; + // q + q.push_front(cyc); + `WRITE_VERBOSE(("[%0t] values: clk=%b, cyc=%0d, a=%b, b=%b, v=%b, i=%0x, j=%0x, t=[%0x, %0x, %0x, %0x, %0x], obj.k=%0x\n", + $time, clk, cyc, a, b, v, i, j, t[0], t[1], t[2], t[3], t[4], k)); + `WRITE_VERBOSE((" q=%p\n", q)); + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_event_control_prev_name_collision.v b/test_regress/t/t_event_control_prev_name_collision.v index 58c6fefd0..9f8d4cf98 100644 --- a/test_regress/t/t_event_control_prev_name_collision.v +++ b/test_regress/t/t_event_control_prev_name_collision.v @@ -3,10 +3,10 @@ // This file ONLY is placed under the Creative Commons Public Domain. // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module S( - input reset, - io_i, - output io_o +module S ( + input reset, + io_i, + output io_o ); reg s; always @(posedge reset) begin @@ -20,77 +20,75 @@ module S( assign io_o = s; endmodule -module Q( - input reset_e, - input reset_d, - output ready_e +module Q ( + input reset_e, + input reset_d, + output ready_e ); - wire reset_n; - wire io_v; - wire io_e; + wire reset_n; + wire io_v; + wire io_e; S e ( - .io_i (), - .reset (reset_e | ~reset_n), - .io_o (io_e) + .io_i(), + .reset(reset_e | ~reset_n), + .io_o(io_e) ); S v ( - .io_i (io_e), - .reset (reset_e), - .io_o (io_v) + .io_i(io_e), + .reset(reset_e), + .io_o(io_v) ); assign reset_n = ~reset_d; assign ready_e = io_v; endmodule -module Test( - input reset, - output valid +module Test ( + input reset, + output valid ); wire ready_e; Q q ( - .reset_e (reset), - .reset_d (reset), - .ready_e (ready_e) + .reset_e(reset), + .reset_d(reset), + .ready_e(ready_e) ); assign valid = ready_e; endmodule -module Test2( - input reset, - input valid +module Test2 ( + input reset, + input valid ); always begin if (~reset & valid) begin - $fatal; + $fatal; end end endmodule -module Dut( - input reset +module Dut ( + input reset ); - wire valid_g; + wire valid_g; Test t ( - .reset (reset), - .valid (valid_g) + .reset(reset), + .valid(valid_g) ); Test2 t2 ( - .reset (reset), - .valid (valid_g) + .reset(reset), + .valid(valid_g) ); endmodule -module t (/*AUTOARG*/ - ); - reg [$bits(dut.reset)-1:0] reset; +module t ( /*AUTOARG*/ +); + reg [$bits(dut.reset)-1:0] reset; - Dut dut ( - .reset(reset) - ); + Dut dut (.reset(reset)); initial begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_event_control_scope_var.v b/test_regress/t/t_event_control_scope_var.v index 66482fc3e..bedb77ef9 100644 --- a/test_regress/t/t_event_control_scope_var.v +++ b/test_regress/t/t_event_control_scope_var.v @@ -4,13 +4,19 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module test_mod(input reg clk, input reg reset, output integer result); +module test_mod ( + input reg clk, + input reg reset, + output integer result +); always @(reset) begin result <= 1; end endmodule -module Dut(input clk); +module Dut ( + input clk +); int num; integer result1; integer result2; @@ -38,24 +44,27 @@ module Dut(input clk); end test_mod t ( - .clk(clk), - .reset(reset1), - .result(result1) + .clk(clk), + .reset(reset1), + .result(result1) ); test_mod t2 ( - .clk(clk), - .reset(reset2), - .result(result2)); - endmodule - -module Dut_wrapper(input clk); - - Dut d(.clk(clk)); - Dut d2(.clk(clk)); + .clk(clk), + .reset(reset2), + .result(result2) + ); endmodule -module t (/*AUTOARG*/ - clk); - input clk; - Dut_wrapper d_w(.clk(clk)); +module Dut_wrapper ( + input clk +); + + Dut d (.clk(clk)); + Dut d2 (.clk(clk)); +endmodule + +module t ( + input clk +); + Dut_wrapper d_w (.clk(clk)); endmodule diff --git a/test_regress/t/t_event_control_star.out b/test_regress/t/t_event_control_star.out index d33d0e424..a04a01ff7 100644 --- a/test_regress/t/t_event_control_star.out +++ b/test_regress/t/t_event_control_star.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_event_control_star.v:19:6: Unsupported: no sense equation (@*) - 19 | @* a = c; - | ^ +%Error-UNSUPPORTED: t/t_event_control_star.v:19:5: Unsupported: no sense equation (@*) + 19 | @* a = c; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_event_control_star.v b/test_regress/t/t_event_control_star.v index c82ba653a..1c1a0a355 100644 --- a/test_regress/t/t_event_control_star.v +++ b/test_regress/t/t_event_control_star.v @@ -8,32 +8,32 @@ module t; - reg a; - reg b; - reg c; + reg a; + reg b; + reg c; - always @* begin // @(b or c) - a = b; - $display("[%0t] Triggered 1 @(b or c)", $time); + always @* begin // @(b or c) + a = b; + $display("[%0t] Triggered 1 @(b or c)", $time); - @* a = c; // @(c) - $display("[%0t] Triggered 2 @(c)", $time); - end + @* a = c; // @(c) + $display("[%0t] Triggered 2 @(c)", $time); + end - initial begin - #10; - b = 0; - #10; - b = 1; - #10; - c = 0; - #10; - c = 1; - #10; - c = 0; - #10; - $write("*-* All Finished *-*\n"); - $finish(0); - end + initial begin + #10; + b = 0; + #10; + b = 1; + #10; + c = 0; + #10; + c = 1; + #10; + c = 0; + #10; + $write("*-* All Finished *-*\n"); + $finish(0); + end endmodule diff --git a/test_regress/t/t_event_copy.out b/test_regress/t/t_event_copy.out index 81bba8753..5c17a0fb8 100644 --- a/test_regress/t/t_event_copy.out +++ b/test_regress/t/t_event_copy.out @@ -1,20 +1,20 @@ -%Error-UNSUPPORTED: t/t_event_copy.v:100:13: Assignment to and from event in statically scheduled context. - : ... note: In instance 't' - : Static event scheduling won't be able to handle this. - : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. - 100 | e4 = e3; - | ^ +%Error-UNSUPPORTED: t/t_event_copy.v:98:10: Assignment to and from event in statically scheduled context. + : ... note: In instance 't' + : Static event scheduling won't be able to handle this. + : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. + 98 | e4 = e3; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_event_copy.v:101:13: Assignment to and from event in statically scheduled context. +%Error-UNSUPPORTED: t/t_event_copy.v:99:10: Assignment to and from event in statically scheduled context. + : ... note: In instance 't' + : Static event scheduling won't be able to handle this. + : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. + 99 | e3 = e2; + | ^ +%Error-UNSUPPORTED: t/t_event_copy.v:126:10: Assignment to event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. - 101 | e3 = e2; - | ^ -%Error-UNSUPPORTED: t/t_event_copy.v:128:13: Assignment to event in statically scheduled context. - : ... note: In instance 't' - : Static event scheduling won't be able to handle this. - : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. - 128 | e3 = null; - | ^ + 126 | e3 = null; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_event_copy.v b/test_regress/t/t_event_copy.v index 208af79ff..04f94ae87 100644 --- a/test_regress/t/t_event_copy.v +++ b/test_regress/t/t_event_copy.v @@ -10,133 +10,131 @@ `define WRITE_VERBOSE(args) `endif -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk +); - event e1; - event e2; - event e3; - event e4; + event e1; + event e2; + event e3; + event e4; `ifndef IVERILOG - event ev [3:0]; + event ev [3:0]; `endif - int cyc; + int cyc; - int last_event; - always @(e1) begin - `WRITE_VERBOSE(("[%0t] e1\n", $time)); + int last_event; + always @(e1) begin + `WRITE_VERBOSE(("[%0t] e1\n", $time)); `ifndef IVERILOG - if (!e1.triggered) $stop; + if (!e1.triggered) $stop; `endif - last_event[1] = 1; - end + last_event[1] = 1; + end - always @(e2) begin - `WRITE_VERBOSE(("[%0t] e2\n", $time)); - last_event[2] = 1; - end + always @(e2) begin + `WRITE_VERBOSE(("[%0t] e2\n", $time)); + last_event[2] = 1; + end - always @(e3) begin - `WRITE_VERBOSE(("[%0t] e3\n", $time)); - last_event[3] = 1; - end + always @(e3) begin + `WRITE_VERBOSE(("[%0t] e3\n", $time)); + last_event[3] = 1; + end - always @(e4) begin - `WRITE_VERBOSE(("[%0t] e4\n", $time)); - last_event[4] = 1; - end + always @(e4) begin + `WRITE_VERBOSE(("[%0t] e4\n", $time)); + last_event[4] = 1; + end - always @(posedge clk) begin - `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); - cyc <= cyc + 1; - if (cyc == 1) begin - // Check no initial trigger - if (last_event != 0) $stop; - end - // - else if (cyc == 10) begin - last_event = 0; - -> e1; - end - else if (cyc == 12) begin - if (last_event != 32'b10) $stop; - last_event = 0; - end - else if (cyc == 13) begin - // Check not still triggering - if (last_event != 0) $stop; - last_event = 0; - end - // - else if (cyc == 20) begin - last_event = 0; + always @(posedge clk) begin + `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); + cyc <= cyc + 1; + if (cyc == 1) begin + // Check no initial trigger + if (last_event != 0) $stop; + end + // + else if (cyc == 10) begin + last_event = 0; + -> e1; + end + else if (cyc == 12) begin + if (last_event != 32'b10) $stop; + last_event = 0; + end + else if (cyc == 13) begin + // Check not still triggering + if (last_event != 0) $stop; + last_event = 0; + end + // + else if (cyc == 20) begin + last_event = 0; `ifdef IVERILOG - -> e2; + -> e2; `else - // Events are both references and events themselves. I.e. 'event e' - // declaration means 'event e = new'. Then e is a reference to that - // created event. - // - // Always having indirection is bad for performance, so Verilator - // should have 'event e' as an "EVENTVALUE" stored as a char, or - // ideally a one bit field reference (not vector as that can't be - // V3Ordered). - // - // Then events once copied become EVENTREFs, much like a ClassRef which - // points to an EVENTVALUE. Thus a Verilog "event" starts as an - // EVENTVALUE, and if an assignment is made it becomes an EVENTVALUE - // and an EVENTREF initing to that EVENTVALUE. - // - // All static scheduling for events would go out the window once an - // event can be pointed to by an EVENTREF, as basically any EVENTREF - // activation could be activating any event. A graph algorithm could - // determine what events/eventrefs are associated and only - // pessamistically schedule those events (users of EVENTVALUES) that - // are ever pointed to by an EVENTREF. - e4 = e3; // Old handle to e4 - e3 = e2; // Same event, also triggers e2 - // IEEE 1800-2023 15.5.5.1 says that this causes a merge, and the below - // should also activate the "old e3". However we could not find any - // simulator that actually does this. Instead the "old e3" becomes - // unreachable (via old handle), but is reachable by "e4" as assigned - // earlier. - ->> e3; // Delayed -`endif - end - else if (cyc == 22) begin - if (last_event != 32'b100) $stop; - last_event = 0; - -> e2; // IEEE says triggers e3, but does not - end - else if (cyc == 24) begin - if (last_event != 32'b100) $stop; - last_event = 0; - -> e4; // Triggers old e3 - end - else if (cyc == 26) begin - if (last_event != 32'b1000) $stop; - last_event = 0; - end + // Events are both references and events themselves. I.e. 'event e' + // declaration means 'event e = new'. Then e is a reference to that + // created event. // - else if (cyc == 30) begin - last_event = 0; -`ifndef IVERILOG - e3 = null; - -> e3; // Triggers nothing + // Always having indirection is bad for performance, so Verilator + // should have 'event e' as an "EVENTVALUE" stored as a char, or + // ideally a one bit field reference (not vector as that can't be + // V3Ordered). + // + // Then events once copied become EVENTREFs, much like a ClassRef which + // points to an EVENTVALUE. Thus a Verilog "event" starts as an + // EVENTVALUE, and if an assignment is made it becomes an EVENTVALUE + // and an EVENTREF initing to that EVENTVALUE. + // + // All static scheduling for events would go out the window once an + // event can be pointed to by an EVENTREF, as basically any EVENTREF + // activation could be activating any event. A graph algorithm could + // determine what events/eventrefs are associated and only + // pessamistically schedule those events (users of EVENTVALUES) that + // are ever pointed to by an EVENTREF. + e4 = e3; // Old handle to e4 + e3 = e2; // Same event, also triggers e2 + // IEEE 1800-2023 15.5.5.1 says that this causes a merge, and the below + // should also activate the "old e3". However we could not find any + // simulator that actually does this. Instead the "old e3" becomes + // unreachable (via old handle), but is reachable by "e4" as assigned + // earlier. + ->> e3; // Delayed `endif - end - else if (cyc == 32) begin - if (last_event != 0) $stop; - last_event = 0; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 22) begin + if (last_event != 32'b100) $stop; + last_event = 0; + -> e2; // IEEE says triggers e3, but does not + end + else if (cyc == 24) begin + if (last_event != 32'b100) $stop; + last_event = 0; + -> e4; // Triggers old e3 + end + else if (cyc == 26) begin + if (last_event != 32'b1000) $stop; + last_event = 0; + end + // + else if (cyc == 30) begin + last_event = 0; +`ifndef IVERILOG + e3 = null; + -> e3; // Triggers nothing +`endif + end + else if (cyc == 32) begin + if (last_event != 0) $stop; + last_event = 0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_event_method_bad.out b/test_regress/t/t_event_method_bad.out index d74966ad4..d658c769c 100644 --- a/test_regress/t/t_event_method_bad.out +++ b/test_regress/t/t_event_method_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_event_method_bad.v:12:10: Unknown built-in event method 'bad_method' - : ... note: In instance 't' - 12 | e1.bad_method(); - | ^~~~~~~~~~ +%Error: t/t_event_method_bad.v:12:8: Unknown built-in event method 'bad_method' + : ... note: In instance 't' + 12 | e1.bad_method(); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_event_method_bad.v b/test_regress/t/t_event_method_bad.v index 1cfbc7126..dbb992518 100644 --- a/test_regress/t/t_event_method_bad.v +++ b/test_regress/t/t_event_method_bad.v @@ -6,10 +6,10 @@ module t; - event e1; + event e1; - initial begin - e1.bad_method(); - end + initial begin + e1.bad_method(); + end endmodule diff --git a/test_regress/t/t_exit.v b/test_regress/t/t_exit.v index fb98d19a1..b4242265f 100644 --- a/test_regress/t/t_exit.v +++ b/test_regress/t/t_exit.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 program t; - initial begin - $write("*-* All Finished *-*\n"); - $exit; // Must be in program block - end + initial begin + $write("*-* All Finished *-*\n"); + $exit; // Must be in program block + end endprogram diff --git a/test_regress/t/t_expect.out b/test_regress/t/t_expect.out index 8a378f4bc..302732e34 100644 --- a/test_regress/t/t_expect.out +++ b/test_regress/t/t_expect.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_expect.v:19:7: Unsupported: expect - 19 | expect (@(posedge clk) a ##1 b) a = 110; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_expect.v:16:5: Unsupported: expect + 16 | expect (@(posedge clk) a ##1 b) a = 110; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_expect.v:21:7: Unsupported: expect - 21 | expect (@(posedge clk) a ##1 b) else a = 299; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_expect.v:23:7: Unsupported: expect - 23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_expect.v:18:5: Unsupported: expect + 18 | expect (@(posedge clk) a ##1 b) + | ^~~~~~ +%Error-UNSUPPORTED: t/t_expect.v:21:5: Unsupported: expect + 21 | expect (@(posedge clk) a ##1 b) a = 300; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_expect.v b/test_regress/t/t_expect.v index fd81ca4fe..e4739816f 100644 --- a/test_regress/t/t_expect.v +++ b/test_regress/t/t_expect.v @@ -4,25 +4,24 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg a; + reg b; - reg a; - reg b; + initial begin + #10; + expect (@(posedge clk) a ##1 b) a = 110; + #10; + expect (@(posedge clk) a ##1 b) + else a = 299; + #10; + expect (@(posedge clk) a ##1 b) a = 300; + else a = 399; + end - initial begin - #10; - expect (@(posedge clk) a ##1 b) a = 110; - #10; - expect (@(posedge clk) a ##1 b) else a = 299; - #10; - expect (@(posedge clk) a ##1 b) a = 300; else a = 399; - end - - // TODO set a/b appropriately - this is just a parsing test currently + // TODO set a/b appropriately - this is just a parsing test currently endmodule diff --git a/test_regress/t/t_expr_incr_unsup.out b/test_regress/t/t_expr_incr_unsup.out index 3f28464b5..3fc86120f 100644 --- a/test_regress/t/t_expr_incr_unsup.out +++ b/test_regress/t/t_expr_incr_unsup.out @@ -1,11 +1,11 @@ -%Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:34: Expression side effect may be mishandled +%Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:30: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression - 17 | $display("Value: %d", arr[postincrement_i()]++); - | ^ + 17 | $display("Value: %d", arr[postincrement_i()]++); + | ^ ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=latest ... Use "/* verilator lint_off SIDEEFFECT */" and lint_on around source to disable this message. -%Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:35: Expression side effect may be mishandled +%Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:31: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression - 17 | $display("Value: %d", arr[postincrement_i()]++); - | ^~~~~~~~~~~~~~~ + 17 | $display("Value: %d", arr[postincrement_i()]++); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_expr_incr_unsup.v b/test_regress/t/t_expr_incr_unsup.v index 0e48015f0..fb3619974 100644 --- a/test_regress/t/t_expr_incr_unsup.v +++ b/test_regress/t/t_expr_incr_unsup.v @@ -7,13 +7,13 @@ int i = 0; function int postincrement_i; - return i++; + return i++; endfunction module t; - initial begin - automatic int arr [1:0] = {0, 0}; - i = 0; - $display("Value: %d", arr[postincrement_i()]++); - end + initial begin + automatic int arr[1:0] = {0, 0}; + i = 0; + $display("Value: %d", arr[postincrement_i()]++); + end endmodule diff --git a/test_regress/t/t_exprstmt_on_lhs_of_nba.v b/test_regress/t/t_exprstmt_on_lhs_of_nba.v index 41b76412f..e9f5668b8 100644 --- a/test_regress/t/t_exprstmt_on_lhs_of_nba.v +++ b/test_regress/t/t_exprstmt_on_lhs_of_nba.v @@ -4,101 +4,99 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - data_o, - // Inputs - clk, rst_i, write_valid_i, write_front_i, read_valid_i, data_i - ); +module t ( /*AUTOARG*/ + // Outputs + data_o, + // Inputs + clk, rst_i, write_valid_i, write_front_i, read_valid_i, data_i +); - localparam NR_ELEMENTS = 16; - localparam DATAW = 32; + localparam NR_ELEMENTS = 16; + localparam DATAW = 32; - input clk; - input rst_i; - input write_valid_i; - input write_front_i; - input read_valid_i; - input [31:0] data_i; - output [31:0] data_o; + input clk; + input rst_i; + input write_valid_i; + input write_front_i; + input read_valid_i; + input [31:0] data_i; + output [31:0] data_o; - reg [31:0] FIFOContent [NR_ELEMENTS-1:0]; + reg [31:0] FIFOContent[NR_ELEMENTS-1:0]; - typedef logic [$clog2(NR_ELEMENTS)-1:0] FIFOPointer_t; + typedef logic [$clog2(NR_ELEMENTS)-1:0] FIFOPointer_t; - // verilator lint_off WIDTH - localparam FIFOPointer_t MAX_PTR_VAL = NR_ELEMENTS-1; - // verilator lint_on WIDTH - localparam FIFOPointer_t MIN_PTR_VAL = 0; - localparam FIFOPointer_t PTR_INC = 1; - FIFOPointer_t write_pointer; - FIFOPointer_t read_pointer; + // verilator lint_off WIDTH + localparam FIFOPointer_t MAX_PTR_VAL = NR_ELEMENTS - 1; + // verilator lint_on WIDTH + localparam FIFOPointer_t MIN_PTR_VAL = 0; + localparam FIFOPointer_t PTR_INC = 1; + FIFOPointer_t write_pointer; + FIFOPointer_t read_pointer; - function FIFOPointer_t nextPointer(input FIFOPointer_t val); - if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) - && val == MAX_PTR_VAL) - nextPointer = MIN_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 - else - nextPointer = val + PTR_INC; - endfunction + function FIFOPointer_t nextPointer(input FIFOPointer_t val); + if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS + 1) && val == MAX_PTR_VAL) + nextPointer = MIN_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 + else nextPointer = val + PTR_INC; + endfunction - function FIFOPointer_t prevPointer(input FIFOPointer_t val); - if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) - && val == MIN_PTR_VAL) - prevPointer = MAX_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 - else - prevPointer = val - PTR_INC; - endfunction + function FIFOPointer_t prevPointer(input FIFOPointer_t val); + if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS + 1) && val == MIN_PTR_VAL) + prevPointer = MAX_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 + else prevPointer = val - PTR_INC; + endfunction - reg [$clog2(NR_ELEMENTS)-1:0] level; - reg is_empty; + reg [$clog2(NR_ELEMENTS)-1:0] level; + reg is_empty; - always @(posedge clk) begin - if (write_valid_i) - FIFOContent[write_front_i ? (read_valid_i ? read_pointer : prevPointer(read_pointer)) : write_pointer] <= data_i; - end + always @(posedge clk) begin + if (write_valid_i) + FIFOContent[write_front_i?(read_valid_i?read_pointer : prevPointer( + read_pointer + )) : write_pointer] <= data_i; + end - assign data_o = FIFOContent[read_pointer]; + assign data_o = FIFOContent[read_pointer]; - always @(posedge clk) begin - if (rst_i) begin - is_empty <= 1; - end - else if (write_valid_i) begin - is_empty <= 0; - end - else if (read_valid_i && write_pointer == nextPointer(read_pointer)) begin - is_empty <= 1; - end - end + always @(posedge clk) begin + if (rst_i) begin + is_empty <= 1; + end + else if (write_valid_i) begin + is_empty <= 0; + end + else if (read_valid_i && write_pointer == nextPointer(read_pointer)) begin + is_empty <= 1; + end + end - always @(posedge clk) begin - if (rst_i) begin - level <= 0; - end - else begin - level <= level + (write_valid_i ? 1 : 0) - (read_valid_i ? 1 : 0); - end - end + always @(posedge clk) begin + if (rst_i) begin + level <= 0; + end + else begin + level <= level + (write_valid_i ? 1 : 0) - (read_valid_i ? 1 : 0); + end + end - always @(posedge clk) begin - if (rst_i) begin - write_pointer <= 0; - end - else if (write_valid_i && !write_front_i) begin - write_pointer <= nextPointer(write_pointer); - end - end + always @(posedge clk) begin + if (rst_i) begin + write_pointer <= 0; + end + else if (write_valid_i && !write_front_i) begin + write_pointer <= nextPointer(write_pointer); + end + end - always @(posedge clk) begin - if (rst_i) begin - read_pointer <= 0; - end - else if (read_valid_i) begin - if (!(write_valid_i && write_front_i))read_pointer <= nextPointer(read_pointer); - end - else if (write_valid_i && write_front_i) begin - read_pointer <= prevPointer(read_pointer); - end - end + always @(posedge clk) begin + if (rst_i) begin + read_pointer <= 0; + end + else if (read_valid_i) begin + if (!(write_valid_i && write_front_i)) read_pointer <= nextPointer(read_pointer); + end + else if (write_valid_i && write_front_i) begin + read_pointer <= prevPointer(read_pointer); + end + end endmodule diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index b0a9f7d75..46e3aceab 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -4,49 +4,47 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - /*verilator public_module*/ + /*verilator public_module*/ - input clk; - // No verilator_public needed, because it's outside the "" in the $c statement - reg [7:0] cyc; initial cyc = 0; - reg c_worked; - reg [8:0] c_wider; + // No verilator_public needed, because it's outside the "" in the $c statement + reg [7:0] cyc; initial cyc = 0; + reg c_worked; + reg [8:0] c_wider; - wire one = 1'b1; + wire one = 1'b1; - always @ (posedge clk) begin - cyc <= cyc + 8'd1; + always @ (posedge clk) begin + cyc <= cyc + 8'd1; - // coverage testing - if (one) begin end - if (!one) begin end - if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line + // coverage testing + if (one) begin end + if (!one) begin end + if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line - if (cyc == 8'd1) begin - c_worked <= 0; - end - if (cyc == 8'd2) begin + if (cyc == 8'd1) begin + c_worked <= 0; + end + if (cyc == 8'd2) begin `ifdef VERILATOR - $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); - $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");"); - c_worked <= $c("this->my_function()"); - c_wider <= $c9("0x10"); + $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); + $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");"); + c_worked <= $c("this->my_function()"); + c_wider <= $c9("0x10"); `else - c_worked <= 1'b1; - c_wider <= 9'h10; + c_worked <= 1'b1; + c_wider <= 9'h10; `endif - end - if (cyc == 8'd3) begin - if (c_worked !== 1'b1) $stop; - if (c_wider !== 9'h10) $stop; - $finish; - end - end + end + if (cyc == 8'd3) begin + if (c_worked !== 1'b1) $stop; + if (c_wider !== 9'h10) $stop; + $finish; + end + end `ifdef verilator `systemc_header @@ -55,11 +53,11 @@ module t (/*AUTOARG*/ #ifndef DID_INT_HEADER #error "`systemc_header didn't work" #endif - bool m_did_ctor; - uint32_t my_function() { - if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); - return 1; - } + bool m_did_ctor; + uint32_t my_function() { + if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); + return 1; + } `systemc_imp_header #define DID_IMP_HEADER 1 `systemc_implementation @@ -67,10 +65,10 @@ module t (/*AUTOARG*/ #error "`systemc_imp_header didn't work" #endif `systemc_ctor - m_did_ctor = 1; + m_did_ctor = 1; `systemc_dtor - printf("In systemc_dtor\n"); - printf("*-* All Finished *-*\n"); + printf("In systemc_dtor\n"); + printf("*-* All Finished *-*\n"); `verilog // Test verilator comment after a endif diff --git a/test_regress/t/t_extend_c_class.v b/test_regress/t/t_extend_c_class.v index 265f835a6..f07ed74e3 100644 --- a/test_regress/t/t_extend_c_class.v +++ b/test_regress/t/t_extend_c_class.v @@ -4,56 +4,54 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [7:0] cyc; initial cyc = 0; + reg [7:0] cyc; initial cyc = 0; - reg [31:0] in; - wire [31:0] out; - t_extend_c_class_v sub (.in(in), .out(out)); + reg [31:0] in; + wire [31:0] out; + t_extend_c_class_v sub (.in(in), .out(out)); - always @ (posedge clk) begin - cyc <= cyc + 8'd1; - if (cyc == 8'd1) begin - in <= 32'h10; - end - if (cyc == 8'd2) begin - if (out != 32'h11) $stop; - end - if (cyc == 8'd9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 8'd1; + if (cyc == 8'd1) begin + in <= 32'h10; + end + if (cyc == 8'd2) begin + if (out != 32'h11) $stop; + end + if (cyc == 8'd9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module t_extend_c_class_v (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); + // Outputs + out, + // Inputs + in + ); - input [31:0] in; - output logic [31:0] out; + input [31:0] in; + output logic [31:0] out; - always @* begin - // When "in" changes, call my method - out = $c("this->m_myobjp->my_math(", in, ")"); - end + always @* begin + // When "in" changes, call my method + out = $c("this->m_myobjp->my_math(", in, ")"); + end `systemc_header -#include "t_extend_c_class_c.h" // Header for contained object +#include "t_extend_c_class_c.h" // Header for contained object `systemc_interface - t_extend_c_class_c* m_myobjp; // Pointer to object we are embedding + t_extend_c_class_c* m_myobjp; // Pointer to object we are embedding `systemc_ctor - m_myobjp = new t_extend_c_class_c(); // Construct contained object + m_myobjp = new t_extend_c_class_c(); // Construct contained object `systemc_dtor - delete m_myobjp; // Destruct contained object + delete m_myobjp; // Destruct contained object `verilog endmodule diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index af9d48f7b..2a8555d88 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -45,16 +45,16 @@ endclass module t; - int i; + int i; - initial begin - Cls c; - c = new; - i = $c(c, "->my_function()"); - $c(c, "->my_imp_function();"); - $c(c, "->my_inline_function();"); - c = null; // Causes destruction and All Finished - $finish; - end + initial begin + Cls c; + c = new; + i = $c(c, "->my_function()"); + $c(c, "->my_imp_function();"); + $c(c, "->my_inline_function();"); + c = null; // Causes destruction and All Finished + $finish; + end endmodule diff --git a/test_regress/t/t_extract_static_const.v b/test_regress/t/t_extract_static_const.v index c14d6a529..4c825e1af 100644 --- a/test_regress/t/t_extract_static_const.v +++ b/test_regress/t/t_extract_static_const.v @@ -6,41 +6,49 @@ module t; - bit [255:0] C; - initial C = {32'h1111_1111, - 32'h2222_2222, - 32'h3333_3333, - 32'h4444_4444, - 32'h5555_5555, - 32'h6666_6666, - 32'h7777_7777, - 32'h8888_8888}; + bit [255:0] C; + initial + C = { + 32'h1111_1111, + 32'h2222_2222, + 32'h3333_3333, + 32'h4444_4444, + 32'h5555_5555, + 32'h6666_6666, + 32'h7777_7777, + 32'h8888_8888 + }; - // Same values as above, but with different type - logic [255:0] D; - initial D = {32'h1111_1111, - 32'h2222_2222, - 32'h3333_3333, - 32'h4444_4444, - 32'h5555_5555, - 32'h6666_6666, - 32'h7777_7777, - 32'h8888_8888}; + // Same values as above, but with different type + logic [255:0] D; + initial + D = { + 32'h1111_1111, + 32'h2222_2222, + 32'h3333_3333, + 32'h4444_4444, + 32'h5555_5555, + 32'h6666_6666, + 32'h7777_7777, + 32'h8888_8888 + }; - int i; + int i; - initial begin - // Note: Base index via $c to prevent optimization by Verilator - i = $c(0*32); $display("0x%8x", C[i+:32]); - i = $c(1*32); $display("0x%8x", D[i+:32]); - i = $c(2*32); $display("0x%8x", C[i+:32]); - i = $c(3*32); $display("0x%8x", D[i+:32]); - i = $c(4*32); $display("0x%8x", C[i+:32]); - i = $c(5*32); $display("0x%8x", D[i+:32]); - i = $c(6*32); $display("0x%8x", C[i+:32]); - i = $c(7*32); $display("0x%8x", D[i+:32]); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Note: Base index via $c to prevent optimization by Verilator + // verilog_format: off + i = $c(0*32); $display("0x%8x", C[i+:32]); + i = $c(1*32); $display("0x%8x", D[i+:32]); + i = $c(2*32); $display("0x%8x", C[i+:32]); + i = $c(3*32); $display("0x%8x", D[i+:32]); + i = $c(4*32); $display("0x%8x", C[i+:32]); + i = $c(5*32); $display("0x%8x", D[i+:32]); + i = $c(6*32); $display("0x%8x", C[i+:32]); + i = $c(7*32); $display("0x%8x", D[i+:32]); + // verilog_format: on + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_extract_static_const_multimodule.v b/test_regress/t/t_extract_static_const_multimodule.v index 74ffc6d76..afe617a85 100644 --- a/test_regress/t/t_extract_static_const_multimodule.v +++ b/test_regress/t/t_extract_static_const_multimodule.v @@ -8,99 +8,112 @@ // Constants should not be shared by different non-inlined modules // -module a( - input wire clk, - input wire trig_i, - output reg trig_o - ); - /* verilator no_inline_module */ +module a ( + input wire clk, + input wire trig_i, + output reg trig_o +); + /* verilator no_inline_module */ - // Same constant as in module b - wire [255:0] C = {32'h1111_1111, - 32'h2222_2222, - 32'h3333_3333, - 32'h4444_4444, - 32'h5555_5555, - 32'h6666_6666, - 32'h7777_7777, - 32'h8888_8888}; + // Same constant as in module b + wire [255:0] C = { + 32'h1111_1111, + 32'h2222_2222, + 32'h3333_3333, + 32'h4444_4444, + 32'h5555_5555, + 32'h6666_6666, + 32'h7777_7777, + 32'h8888_8888 + }; - int i; + int i; - always @(posedge clk) begin - trig_o <= 1'd0; - if (trig_i) begin - // Note: Base index via $c to prevent optimizatoin by Verilator - i = $c(0*32); $display("0x%8x", C[i+:32]); - i = $c(2*32); $display("0x%8x", C[i+:32]); - i = $c(4*32); $display("0x%8x", C[i+:32]); - i = $c(6*32); $display("0x%8x", C[i+:32]); - $display("0x%32x", C); - trig_o <= 1'd1; - end - end + always @(posedge clk) begin + trig_o <= 1'd0; + if (trig_i) begin + // Note: Base index via $c to prevent optimizatoin by Verilator + // verilog_format: off + i = $c(0*32); $display("0x%8x", C[i+:32]); + i = $c(2*32); $display("0x%8x", C[i+:32]); + i = $c(4*32); $display("0x%8x", C[i+:32]); + i = $c(6*32); $display("0x%8x", C[i+:32]); + // verilog_format: on + $display("0x%32x", C); + trig_o <= 1'd1; + end + end endmodule -module b( - input wire clk, - input wire trig_i, - output reg trig_o - ); - /* verilator no_inline_module */ +module b ( + input wire clk, + input wire trig_i, + output reg trig_o +); + /* verilator no_inline_module */ - // Same constant as in module a - wire [255:0] C = {32'h1111_1111, - 32'h2222_2222, - 32'h3333_3333, - 32'h4444_4444, - 32'h5555_5555, - 32'h6666_6666, - 32'h7777_7777, - 32'h8888_8888}; + // Same constant as in module a + wire [255:0] C = { + 32'h1111_1111, + 32'h2222_2222, + 32'h3333_3333, + 32'h4444_4444, + 32'h5555_5555, + 32'h6666_6666, + 32'h7777_7777, + 32'h8888_8888 + }; - int i; + int i; - always @(posedge clk) begin - trig_o <= 1'd0; - if (trig_i) begin - // Note: Base index via $c to prevent optimizatoin by Verilator - i = $c(1*32); $display("0x%8x", C[i+:32]); - i = $c(3*32); $display("0x%8x", C[i+:32]); - i = $c(5*32); $display("0x%8x", C[i+:32]); - i = $c(7*32); $display("0x%8x", C[i+:32]); - $display("0x%32x", C); - trig_o <= 1'd1; - end - end + always @(posedge clk) begin + trig_o <= 1'd0; + if (trig_i) begin + // Note: Base index via $c to prevent optimizatoin by Verilator + // verilog_format: off + i = $c(1*32); $display("0x%8x", C[i+:32]); + i = $c(3*32); $display("0x%8x", C[i+:32]); + i = $c(5*32); $display("0x%8x", C[i+:32]); + i = $c(7*32); $display("0x%8x", C[i+:32]); + // verilog_format: on + $display("0x%32x", C); + trig_o <= 1'd1; + end + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc = 0; - integer cyc = 0; + reg trig_i; + wire trig_ab; + wire trig_o; - reg trig_i; - wire trig_ab; - wire trig_o; + a a_inst ( + .clk(clk), + .trig_i(trig_i), + .trig_o(trig_ab) + ); + b b_inst ( + .clk(clk), + .trig_i(trig_ab), + .trig_o(trig_o) + ); - a a_inst(.clk(clk), .trig_i(trig_i), .trig_o(trig_ab)); - b b_inst(.clk(clk), .trig_i(trig_ab), .trig_o(trig_o)); + always @(posedge clk) begin + trig_i <= cyc == 1; - always @(posedge clk) begin - trig_i <= cyc == 1; + if (trig_o) begin + $write("*-* All Finished *-*\n"); + $finish; + end - if (trig_o) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - cyc++; - end + cyc++; + end endmodule diff --git a/test_regress/t/t_fallback_bad.out b/test_regress/t/t_fallback_bad.out index 6d2ba11ae..2bd8a18df 100644 --- a/test_regress/t/t_fallback_bad.out +++ b/test_regress/t/t_fallback_bad.out @@ -1,31 +1,31 @@ -%Error: t/t_fallback_bad.v:26:16: Can't find definition of task/function: 'tsk' - 26 | super.tsk; - | ^~~ +%Error: t/t_fallback_bad.v:28:13: Can't find definition of task/function: 'tsk' + 28 | super.tsk; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_fallback_bad.v:27:15: Can't find definition of task/function: 'tsk' - 27 | this.tsk; - | ^~~ -%Error: t/t_fallback_bad.v:28:16: Can't find definition of variable/method: 'f' - 28 | super.f = 8; - | ^ -%Error: t/t_fallback_bad.v:29:15: Can't find definition of variable/method: 'f' - 29 | this.f = 8; - | ^ -%Error: t/t_fallback_bad.v:30:20: Can't find definition of 'tsk' in dotted task/function: 'sub1.sub2.tsk' - 30 | sub1.sub2.tsk; - | ^~~ +%Error: t/t_fallback_bad.v:29:12: Can't find definition of task/function: 'tsk' + 29 | this.tsk; + | ^~~ +%Error: t/t_fallback_bad.v:30:13: Can't find definition of variable/method: 'f' + 30 | super.f = 8; + | ^ +%Error: t/t_fallback_bad.v:31:12: Can't find definition of variable/method: 'f' + 31 | this.f = 8; + | ^ +%Error: t/t_fallback_bad.v:32:17: Can't find definition of 'tsk' in dotted task/function: 'sub1.sub2.tsk' + 32 | sub1.sub2.tsk; + | ^~~ ... Known scopes under 'tsk': sub2 -%Error: t/t_fallback_bad.v:31:15: Can't find definition of scope/variable/func: 'f' - 31 | pkg::f = 8; - | ^ -%Error: t/t_fallback_bad.v:32:15: Can't find definition of task/function: 'tsk' - 32 | pkg::tsk(); - | ^~~ -%Error: t/t_fallback_bad.v:33:20: Can't find definition of 'f' in dotted variable/method: 'sub1.sub2.f' - 33 | sub1.sub2.f = 8; - | ^ -%Error: t/t_fallback_bad.v:34:20: Can't find definition of 'f' in dotted scope/variable: 'sub1.sub2.f' - 34 | sub1.sub2.f.f = 8; - | ^ +%Error: t/t_fallback_bad.v:33:12: Can't find definition of scope/variable/func: 'f' + 33 | pkg::f = 8; + | ^ +%Error: t/t_fallback_bad.v:34:12: Can't find definition of task/function: 'tsk' + 34 | pkg::tsk(); + | ^~~ +%Error: t/t_fallback_bad.v:35:17: Can't find definition of 'f' in dotted variable/method: 'sub1.sub2.f' + 35 | sub1.sub2.f = 8; + | ^ +%Error: t/t_fallback_bad.v:36:17: Can't find definition of 'f' in dotted scope/variable: 'sub1.sub2.f' + 36 | sub1.sub2.f.f = 8; + | ^ ... Known scopes under 'sub1.sub2': %Error: Exiting due to diff --git a/test_regress/t/t_fallback_bad.v b/test_regress/t/t_fallback_bad.v index f1215747e..2514bde49 100644 --- a/test_regress/t/t_fallback_bad.v +++ b/test_regress/t/t_fallback_bad.v @@ -5,7 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 int f = 5; -task tsk; endtask +task tsk; +endtask package pkg; endpackage @@ -14,30 +15,31 @@ module subm; endmodule module submo; - subm sub2(); + subm sub2 (); endmodule module t; - submo sub1(); + submo sub1 (); - class Base;endclass - class Cls extends Base; - task calltsk; - super.tsk; - this.tsk; - super.f = 8; - this.f = 8; - sub1.sub2.tsk; - pkg::f = 8; - pkg::tsk(); - sub1.sub2.f = 8; - sub1.sub2.f.f = 8; - endtask - endclass + class Base; + endclass + class Cls extends Base; + task calltsk; + super.tsk; + this.tsk; + super.f = 8; + this.f = 8; + sub1.sub2.tsk; + pkg::f = 8; + pkg::tsk(); + sub1.sub2.f = 8; + sub1.sub2.f.f = 8; + endtask + endclass - Cls obj = new; - initial begin - obj.calltsk; - if (f != 5) $stop; - end + Cls obj = new; + initial begin + obj.calltsk; + if (f != 5) $stop; + end endmodule diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v index 610061f1f..38c931bc4 100644 --- a/test_regress/t/t_final.v +++ b/test_regress/t/t_final.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module submodule (); - // This bug only appears when not inlining - // verilator no_inline_module - initial begin - $write("d"); - end - final begin - $write("d"); - end - final ; // Empty test + // This bug only appears when not inlining + // verilator no_inline_module + initial begin + $write("d"); + end + final begin + $write("d"); + end + final ; // Empty test endmodule module t; - generate - for (genvar i = 0; i < 100; i = i + 1) begin : module_set - submodule u_submodule(); - end - endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + generate + for (genvar i = 0; i < 100; i = i + 1) begin : module_set + submodule u_submodule(); + end + endgenerate + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_bboxsys.v b/test_regress/t/t_flag_bboxsys.v index 597eb4620..4f5b56cd0 100644 --- a/test_regress/t/t_flag_bboxsys.v +++ b/test_regress/t/t_flag_bboxsys.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg a; - initial begin - $unknown_sys_task_call_to_be_bbox("blah"); - $unkown_sys_task_call_noarg; - a = $unknown_sys_func_call(23); - a = $unknown_sys_func_call_noarg; - $write("*-* All Finished *-*\n"); - $finish; - end + reg a; + initial begin + $unknown_sys_task_call_to_be_bbox("blah"); + $unkown_sys_task_call_noarg; + a = $unknown_sys_func_call(23); + a = $unknown_sys_func_call_noarg; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_comp_limit_parens.v b/test_regress/t/t_flag_comp_limit_parens.v index 0f31e5f5d..8eeff374f 100644 --- a/test_regress/t/t_flag_comp_limit_parens.v +++ b/test_regress/t/t_flag_comp_limit_parens.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - r - ); - input real r; + // Inputs + r + ); + input real r; - initial begin - $display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1))))))))); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1))))))))); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_compiler.v b/test_regress/t/t_flag_compiler.v index 32ed50ef4..4803a0c80 100644 --- a/test_regress/t/t_flag_compiler.v +++ b/test_regress/t/t_flag_compiler.v @@ -4,72 +4,74 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [89:0] in; + reg [89:0] in; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [89:0] out; // From test of Test.v - wire [44:0] line0; - wire [44:0] line1; - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [89:0] out; // From test of Test.v + wire [44:0] line0; + wire [44:0] line1; + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[89:0]), - .line0 (line0[44:0]), - .line1 (line1[44:0]), - // Inputs - .clk (clk), - .in (in[89:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[89:0]), + .line0(line0[44:0]), + .line1(line1[44:0]), + // Inputs + .clk(clk), + .in(in[89:0]) + ); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out); + $write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out); `endif - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; + end + else if (cyc == 10) begin + if (in == out) begin + $write("*-* All Finished *-*\n"); + $finish; end - else if (cyc==10) begin - if (in==out) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("*-* Failed!! *-*\n"); - $finish; - end + else begin + $write("*-* Failed!! *-*\n"); + $finish; end - end + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - line0, line1, out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + line0, + line1, + out, + // Inputs + clk, + in +); - input clk; - input [89:0] in; + input clk; + input [89:0] in; - output reg [44:0] line0; - output reg [44:0] line1; - output reg [89:0] out; + output reg [44:0] line0; + output reg [44:0] line1; + output reg [89:0] out; - assign {line0,line1} = in; - always @(posedge clk) begin - out <= {line0,line1}; - end + assign {line0, line1} = in; + always @(posedge clk) begin + out <= {line0, line1}; + end endmodule diff --git a/test_regress/t/t_flag_context_bad.out b/test_regress/t/t_flag_context_bad.out index c1a8e4c02..6900db90b 100644 --- a/test_regress/t/t_flag_context_bad.out +++ b/test_regress/t/t_flag_context_bad.out @@ -1,8 +1,8 @@ -%Warning-WIDTHTRUNC: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. +%Warning-WIDTHTRUNC: t/t_flag_context_bad.v:9:18: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... note: In instance 't' ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-UNUSEDSIGNAL: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' +%Warning-UNUSEDSIGNAL: t/t_flag_context_bad.v:9:14: Signal is not used: 'foo' : ... note: In instance 't' ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_flag_context_bad.v b/test_regress/t/t_flag_context_bad.v index f9c43b66c..e07ea0eb5 100644 --- a/test_regress/t/t_flag_context_bad.v +++ b/test_regress/t/t_flag_context_bad.v @@ -6,6 +6,6 @@ module t; - wire [2:0] foo = 5'b11111; + wire [2:0] foo = 5'b11111; endmodule diff --git a/test_regress/t/t_flag_csplit.v b/test_regress/t/t_flag_csplit.v index 8c287d5e9..3ce4f32a9 100644 --- a/test_regress/t/t_flag_csplit.v +++ b/test_regress/t/t_flag_csplit.v @@ -4,59 +4,64 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - parameter CNT = 5; + parameter CNT = 5; - wire [31:0] w [CNT:0]; + wire [31:0] w[CNT:0]; - generate - for (genvar g=0; g>> 31 != -1) $stop; + // Check parameter assigned simple integer literal is signed + if ((int11 << 27) >>> 31 != -1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_parameter_hier.v b/test_regress/t/t_flag_parameter_hier.v index d92484dd7..78cfc5a77 100644 --- a/test_regress/t/t_flag_parameter_hier.v +++ b/test_regress/t/t_flag_parameter_hier.v @@ -5,80 +5,79 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); +`define check(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - u u (); - tx x (); + u u (); + tx x (); - parameter PARAM = 0; - parameter HIER = 0; - initial begin - $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); + parameter PARAM = 0; + parameter HIER = 0; + initial begin + $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG - `check(PARAM, 0); + `check(PARAM, 0); `elsif NC - `check(PARAM, 0); + `check(PARAM, 0); `elsif VCS - `check(PARAM, 10); + `check(PARAM, 10); `else - `check(PARAM, 10); + `check(PARAM, 10); `endif - `check(HIER, 0); - end - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + `check(HIER, 0); + end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module u; - ux x(); + ux x (); endmodule module ux; - parameter PARAM = 0; - parameter HIER = 0; - initial begin - $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); + parameter PARAM = 0; + parameter HIER = 0; + initial begin + $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG - `check(PARAM, 0); + `check(PARAM, 0); `elsif NC - `check(PARAM, 0); + `check(PARAM, 0); `elsif VCS - `check(PARAM, 10); + `check(PARAM, 10); `else - `check(PARAM, 0); + `check(PARAM, 0); `endif - `check(HIER, 0); - end + `check(HIER, 0); + end endmodule module tx; - parameter PARAM = 0; - parameter HIER = 0; - initial begin - $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); + parameter PARAM = 0; + parameter HIER = 0; + initial begin + $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG - `check(PARAM, 0); + `check(PARAM, 0); `elsif NC - `check(PARAM, 10); + `check(PARAM, 10); `elsif VCS - `check(PARAM, 10); + `check(PARAM, 10); `else - `check(PARAM, 0); + `check(PARAM, 0); `endif `ifdef NC - `check(HIER, 20); + `check(HIER, 20); `else - `check(HIER, 0); + `check(HIER, 0); `endif - end + end endmodule diff --git a/test_regress/t/t_flag_parameter_pkg.v b/test_regress/t/t_flag_parameter_pkg.v index 094ee408b..797f0d369 100644 --- a/test_regress/t/t_flag_parameter_pkg.v +++ b/test_regress/t/t_flag_parameter_pkg.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 package pack_a; - parameter PARAM_A = 0; + parameter PARAM_A = 0; endpackage : pack_a //module t; module t; - parameter PARAM_A = 0; + parameter PARAM_A = 0; - initial begin - $display(PARAM_A); - if (PARAM_A != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display(PARAM_A); + if (PARAM_A != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_prefix.v b/test_regress/t/t_flag_prefix.v index 39470ac9b..b19546a52 100644 --- a/test_regress/t/t_flag_prefix.v +++ b/test_regress/t/t_flag_prefix.v @@ -5,33 +5,33 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub sub(); + sub sub(); endmodule module sub; - // no_inline_module, so it goes into separate file - /* verilator no_inline_module */ + // no_inline_module, so it goes into separate file + /* verilator no_inline_module */ - // Goes into const pool which is separate file - wire logic [255:0] C = {32'h1111_1111, - 32'h2222_2222, - 32'h3333_3333, - 32'h4444_4444, - 32'h5555_5555, - 32'h6666_6666, - 32'h7777_7777, - 32'h8888_8888}; + // Goes into const pool which is separate file + wire logic [255:0] C = {32'h1111_1111, + 32'h2222_2222, + 32'h3333_3333, + 32'h4444_4444, + 32'h5555_5555, + 32'h6666_6666, + 32'h7777_7777, + 32'h8888_8888}; - int i; + int i; - initial begin - // Note: Base index via $c to prevent optimization - i = $c(0*32); $display("0x%32x", C[i+:32]); - i = $c(1*32); $display("0x%32x", C[i+:32]); - i = $c(2*32); $display("0x%32x", C[i+:32]); - i = $c(3*32); $display("0x%32x", C[i+:32]); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Note: Base index via $c to prevent optimization + i = $c(0*32); $display("0x%32x", C[i+:32]); + i = $c(1*32); $display("0x%32x", C[i+:32]); + i = $c(2*32); $display("0x%32x", C[i+:32]); + i = $c(3*32); $display("0x%32x", C[i+:32]); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_quiet_stats.v b/test_regress/t/t_flag_quiet_stats.v index 57d264ae8..f318a0ff3 100644 --- a/test_regress/t/t_flag_quiet_stats.v +++ b/test_regress/t/t_flag_quiet_stats.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_relinc.v b/test_regress/t/t_flag_relinc.v index 31f454451..719bb9a77 100644 --- a/test_regress/t/t_flag_relinc.v +++ b/test_regress/t/t_flag_relinc.v @@ -7,5 +7,5 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - t_flag_relinc_sub sub (); + t_flag_relinc_sub sub (); endmodule diff --git a/test_regress/t/t_flag_stats.v b/test_regress/t/t_flag_stats.v index 323b631fd..039a06a0a 100644 --- a/test_regress/t/t_flag_stats.v +++ b/test_regress/t/t_flag_stats.v @@ -4,13 +4,16 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (b, b2); - output reg [31:0] b; - output reg [31:0] b2; // Need 2 vars of same width to cover V3Stats - initial begin - b = 11; - b2 = 22; - $write("*-* All Finished *-*\n"); - $finish; - end +module t ( + b, + b2 +); + output reg [31:0] b; + output reg [31:0] b2; // Need 2 vars of same width to cover V3Stats + initial begin + b = 11; + b2 = 22; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_structs_packed.v b/test_regress/t/t_flag_structs_packed.v index 3d5a95760..b1c8293f5 100644 --- a/test_regress/t/t_flag_structs_packed.v +++ b/test_regress/t/t_flag_structs_packed.v @@ -6,20 +6,16 @@ module x; - typedef struct { - int a; - } notpacked_t; + typedef struct {int a;} notpacked_t; - typedef struct packed { - notpacked_t b; - } ispacked_t; + typedef struct packed {notpacked_t b;} ispacked_t; - ispacked_t p; + ispacked_t p; - initial begin - p.b = 1; - if (p.b != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + p.b = 1; + if (p.b != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_structs_packed_bad.out b/test_regress/t/t_flag_structs_packed_bad.out index c692c05e7..815b967fa 100644 --- a/test_regress/t/t_flag_structs_packed_bad.out +++ b/test_regress/t/t_flag_structs_packed_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_flag_structs_packed.v:14:19: Unpacked data type 'struct{}x.notpacked_t' in packed struct/union (IEEE 1800-2023 7.2.1) +%Error: t/t_flag_structs_packed.v:11:38: Unpacked data type 'struct{}x.notpacked_t' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 'x' - 14 | notpacked_t b; - | ^ + 11 | typedef struct packed {notpacked_t b;} ispacked_t; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_timescale.v b/test_regress/t/t_flag_timescale.v index 4f666928c..89727bb30 100644 --- a/test_regress/t/t_flag_timescale.v +++ b/test_regress/t/t_flag_timescale.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub sub(); - initial begin - $write("t: "); - $printtimescale; - sub.pts(); - $write("*-* All Finished *-*\n"); - $finish; - end + sub sub (); + initial begin + $write("t: "); + $printtimescale; + sub.pts(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -`timescale 1s/1s +`timescale 1s / 1s module sub; - task pts; - $write("sub: "); - $printtimescale; - endtask + task pts; + $write("sub: "); + $printtimescale; + endtask endmodule diff --git a/test_regress/t/t_flag_timescale_override.v b/test_regress/t/t_flag_timescale_override.v index 5de3ce48b..89124a600 100644 --- a/test_regress/t/t_flag_timescale_override.v +++ b/test_regress/t/t_flag_timescale_override.v @@ -4,20 +4,20 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 1s/1s +`timescale 1s / 1s module t; - sub sub (); - initial begin - $printtimescale; - sub.pts(); - $write("*-* All Finished *-*\n"); - $finish; - end + sub sub (); + initial begin + $printtimescale; + sub.pts(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub; - task pts; - $printtimescale; - endtask + task pts; + $printtimescale; + endtask endmodule diff --git a/test_regress/t/t_flag_werror.v b/test_regress/t/t_flag_werror.v index 445056058..c856c77bb 100644 --- a/test_regress/t/t_flag_werror.v +++ b/test_regress/t/t_flag_werror.v @@ -6,7 +6,7 @@ module t; - // Width error below - wire [3:0] foo = 6'h2e; + // Width error below + wire [3:0] foo = 6'h2e; endmodule diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 904df576d..b8c0c1db2 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -1,7 +1,7 @@ -%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. +%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:18: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' - 10 | wire [3:0] foo = 6'h2e; - | ^ + 10 | wire [3:0] foo = 6'h2e; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index 55ffa6d25..5fa153925 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -1,6 +1,6 @@ -%Error-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. +%Error-WIDTHTRUNC: t/t_flag_werror.v:10:18: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' - 10 | wire [3:0] foo = 6'h2e; - | ^ + 10 | wire [3:0] foo = 6'h2e; + | ^ ... For error description see https://verilator.org/warn/WIDTHTRUNC?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index 16a2669fd..4fad55e05 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -1,6 +1,6 @@ -%Warning-WIDTHTRUNC: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. +%Warning-WIDTHTRUNC: t/t_flag_wfatal.v:10:18: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' - 10 | wire [3:0] foo = 6'h2e; - | ^ + 10 | wire [3:0] foo = 6'h2e; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_flag_wfatal.v b/test_regress/t/t_flag_wfatal.v index 445056058..c856c77bb 100644 --- a/test_regress/t/t_flag_wfatal.v +++ b/test_regress/t/t_flag_wfatal.v @@ -6,7 +6,7 @@ module t; - // Width error below - wire [3:0] foo = 6'h2e; + // Width error below + wire [3:0] foo = 6'h2e; endmodule diff --git a/test_regress/t/t_flag_woff.v b/test_regress/t/t_flag_woff.v index ee714358e..e1a33c621 100644 --- a/test_regress/t/t_flag_woff.v +++ b/test_regress/t/t_flag_woff.v @@ -6,15 +6,15 @@ module t; - // width warnings off due to command line - wire A = 15'd1234; + // width warnings off due to command line + wire A = 15'd1234; - // width warnings off due to command line + manual switch - // verilator lint_off WIDTH - wire B = 15'd1234; + // width warnings off due to command line + manual switch + // verilator lint_off WIDTH + wire B = 15'd1234; - // this turnon does nothing as off on command line - // verilator lint_on WIDTH - wire C = 15'd1234; + // this turnon does nothing as off on command line + // verilator lint_on WIDTH + wire C = 15'd1234; endmodule diff --git a/test_regress/t/t_flag_wpedantic_bad.out b/test_regress/t/t_flag_wpedantic_bad.out index 0942660a4..e38e4f6b0 100644 --- a/test_regress/t/t_flag_wpedantic_bad.out +++ b/test_regress/t/t_flag_wpedantic_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_flag_wpedantic_bad.v:8:8: syntax error, unexpected global - 8 | reg global; - | ^~~~~~ +%Error: t/t_flag_wpedantic_bad.v:8:7: syntax error, unexpected global + 8 | reg global; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_wpedantic_bad.v b/test_regress/t/t_flag_wpedantic_bad.v index 9514dca08..2cf3f67dd 100644 --- a/test_regress/t/t_flag_wpedantic_bad.v +++ b/test_regress/t/t_flag_wpedantic_bad.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg global; + reg global; endmodule diff --git a/test_regress/t/t_flag_xinitial_0.v b/test_regress/t/t_flag_xinitial_0.v index 1e5b9ae0b..0825d1a57 100644 --- a/test_regress/t/t_flag_xinitial_0.v +++ b/test_regress/t/t_flag_xinitial_0.v @@ -4,21 +4,21 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - value - ); +module t ( /*AUTOARG*/ + // Outputs + value +); - output reg [63:0] value; + output reg [63:0] value; - initial begin + initial begin `ifdef VERILATOR - // Default is all ones, so we assume that here - if (value != '0) $stop; + // Default is all ones, so we assume that here + if (value != '0) $stop; `else - if (value != {64{1'bx}}) $stop; + if (value != {64{1'bx}}) $stop; `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_flag_xinitial_unique.v b/test_regress/t/t_flag_xinitial_unique.v index dd63dc905..68a857af8 100644 --- a/test_regress/t/t_flag_xinitial_unique.v +++ b/test_regress/t/t_flag_xinitial_unique.v @@ -4,18 +4,19 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - value, value2 - ); +module t ( /*AUTOARG*/ + // Outputs + value, + value2 +); - output reg [63:0] value; - output wire [64:0] value2; + output reg [63:0] value; + output wire [64:0] value2; - assign value2 = {8'bx, 57'h12}; + assign value2 = {8'bx, 57'h12}; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_for_assign.v b/test_regress/t/t_for_assign.v index 41fe53660..3b390c16d 100644 --- a/test_regress/t/t_for_assign.v +++ b/test_regress/t/t_for_assign.v @@ -4,40 +4,42 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: on `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: off module t; - int a, b; - int sum; - // Complicated assignment cases + int a, b; + int sum; + // Complicated assignment cases - initial begin - sum = 0; - for (integer a=0; a<3; ) begin - a = a + 1; - sum = sum + a; - end - `checkd(sum, 6); + initial begin + sum = 0; + for (integer a = 0; a < 3;) begin + a = a + 1; + sum = sum + a; + end + `checkd(sum, 6); - // foperator_assignment - sum = 0; - for (integer a=0; a<3; a=a+1, sum += a) ; - `checkd(sum, 6); + // foperator_assignment + sum = 0; + for (integer a = 0; a < 3; a = a + 1, sum += a); + `checkd(sum, 6); - // inc_or_dec_expression - sum = 0; - for (integer a=0; a<3; a++, ++sum) ; - `checkd(sum, 3); + // inc_or_dec_expression + sum = 0; + for (integer a = 0; a < 3; a++, ++sum); + `checkd(sum, 3); - // task_subroutine_call - sum = 0; - for (integer a=0; a<3; a++, sum += $clog2(a)) ; - `checkd(sum, 3); + // task_subroutine_call + sum = 0; + for (integer a = 0; a < 3; a++, sum += $clog2(a)); + `checkd(sum, 3); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v index 0bfd96e95..5b99fde19 100644 --- a/test_regress/t/t_for_break.v +++ b/test_regress/t/t_for_break.v @@ -4,141 +4,139 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] l_stop = crc[3:0]; - wire [3:0] l_break = crc[7:4]; - wire [3:0] l_continue = crc[11:8]; + // Take CRC data and apply to testblock inputs + wire [3:0] l_stop = crc[3:0]; + wire [3:0] l_break = crc[7:4]; + wire [3:0] l_continue = crc[11:8]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - wire [15:0] out0 = Test0(l_stop, l_break, l_continue); - wire [15:0] out1 = Test1(l_stop, l_break, l_continue); - wire [15:0] out2 = Test2(l_stop, l_break, l_continue); - wire [15:0] out3 = Test3(l_stop, l_break, l_continue); + wire [15:0] out0 = Test0(l_stop, l_break, l_continue); + wire [15:0] out1 = Test1(l_stop, l_break, l_continue); + wire [15:0] out2 = Test2(l_stop, l_break, l_continue); + wire [15:0] out3 = Test3(l_stop, l_break, l_continue); - // Aggregate outputs into a single result vector - wire [63:0] result = {out3,out2,out1,out0}; + // Aggregate outputs into a single result vector + wire [63:0] result = {out3, out2, out1, out0}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - if (out0!==out1) $stop; - if (out0!==out2) $stop; - if (out0!==out3) $stop; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h293e9f9798e97da0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + if (out0 !== out1) $stop; + if (out0 !== out2) $stop; + if (out0 !== out3) $stop; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h293e9f9798e97da0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - function [15:0] Test0; - input [3:0] loop_stop; - input [3:0] loop_break; - input [3:0] loop_continue; - integer i; - reg broken; + function [15:0] Test0; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; + reg broken; - Test0 = 0; - broken = 0; - begin - for (i=1; i<20; i=i+1) begin - if (!broken) begin - Test0 = Test0 + 1; - if (i[3:0] != loop_continue) begin // continue - if (i[3:0] == loop_break) begin - broken = 1'b1; - end - if (!broken) begin - Test0 = Test0 + i[15:0]; - end - end + Test0 = 0; + broken = 0; + begin + for (i = 1; i < 20; i = i + 1) begin + if (!broken) begin + Test0 = Test0 + 1; + if (i[3:0] != loop_continue) begin // continue + if (i[3:0] == loop_break) begin + broken = 1'b1; end - end + if (!broken) begin + Test0 = Test0 + i[15:0]; + end + end + end end - endfunction + end + endfunction - function [15:0] Test1; - input [3:0] loop_stop; - input [3:0] loop_break; - input [3:0] loop_continue; - integer i; + function [15:0] Test1; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; - Test1 = 0; - begin : outer_block - for (i=1; i<20; i=i+1) begin : inner_block - Test1 = Test1 + 1; - // continue, IE jump to end-of-inner_block. Must be inside inner_block. - if (i[3:0] == loop_continue) disable inner_block; - // break, IE jump to end-of-outer_block. Must be inside outer_block. - if (i[3:0] == loop_break) disable outer_block; - Test1 = Test1 + i[15:0]; - end : inner_block - end : outer_block - endfunction + Test1 = 0; + begin : outer_block + for (i = 1; i < 20; i = i + 1) begin : inner_block + Test1 = Test1 + 1; + // continue, IE jump to end-of-inner_block. Must be inside inner_block. + if (i[3:0] == loop_continue) disable inner_block; + // break, IE jump to end-of-outer_block. Must be inside outer_block. + if (i[3:0] == loop_break) disable outer_block; + Test1 = Test1 + i[15:0]; + end : inner_block + end : outer_block + endfunction - function [15:0] Test2; - input [3:0] loop_stop; - input [3:0] loop_break; - input [3:0] loop_continue; - integer i; + function [15:0] Test2; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; - Test2 = 0; - begin - for (i=1; i<20; i=i+1) begin - Test2 = Test2 + 1; - if (i[3:0] == loop_continue) continue; - if (i[3:0] == loop_break) break; - Test2 = Test2 + i[15:0]; - end + Test2 = 0; + begin + for (i = 1; i < 20; i = i + 1) begin + Test2 = Test2 + 1; + if (i[3:0] == loop_continue) continue; + if (i[3:0] == loop_break) break; + Test2 = Test2 + i[15:0]; end - endfunction + end + endfunction - function [15:0] Test3; - input [3:0] loop_stop; - input [3:0] loop_break; - input [3:0] loop_continue; - integer i; + function [15:0] Test3; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; - Test3 = 0; - begin - for (i=1; i<20; i=i+1) begin - Test3 = Test3 + 1; - if (i[3:0] == loop_continue) continue; - // return, IE jump to end-of-function optionally setting return value - if (i[3:0] == loop_break) return Test3; - Test3 = Test3 + i[15:0]; - end + Test3 = 0; + begin + for (i = 1; i < 20; i = i + 1) begin + Test3 = Test3 + 1; + if (i[3:0] == loop_continue) continue; + // return, IE jump to end-of-function optionally setting return value + if (i[3:0] == loop_break) return Test3; + Test3 = Test3 + i[15:0]; end - endfunction + end + endfunction endmodule diff --git a/test_regress/t/t_for_comma.v b/test_regress/t/t_for_comma.v index 30e172be9..71df8ec10 100644 --- a/test_regress/t/t_for_comma.v +++ b/test_regress/t/t_for_comma.v @@ -4,60 +4,61 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define checkc(expc) \ - do begin \ - if (c !== expc) begin \ - $write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \ - $stop; \ - end \ - a=0; b=0; c=0; \ - end while(0); + do begin \ + if (c !== expc) begin \ + $write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \ + $stop; \ + end \ + a=0; b=0; c=0; \ + end while(0); module t; - int a, b, c; + int a, b, c; - initial begin - for (; ; ) begin c = c + 1 + a + b; break; end - `checkc(1); - for (; ; a = a + 1) begin c = c + 1 + a + b; break; end - `checkc(1); - for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end - `checkc(1); - for (; a < 3; ) begin c = c + 1 + a + b; break; end - `checkc(1); - for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end - `checkc(1); - for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end - `checkc(1); - for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end - `checkc(2); - for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end - `checkc(5); - for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end - `checkc(6); - for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end - `checkc(2); - for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end - `checkc(5); - for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end - `checkc(6); - for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end - `checkc(2); - for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end - `checkc(5); - for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end - `checkc(6); - for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end - `checkc(3); - for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end - `checkc(7); - for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end - `checkc(8); - for (int a = 1, x = 1; a < 3; a = a + 1, x = x + 1) begin c = c + 1 + a + x; end - `checkc(8); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + for (; ; ) begin c = c + 1 + a + b; break; end + `checkc(1); + for (; ; a = a + 1) begin c = c + 1 + a + b; break; end + `checkc(1); + for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end + `checkc(1); + for (; a < 3; ) begin c = c + 1 + a + b; break; end + `checkc(1); + for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end + `checkc(1); + for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end + `checkc(1); + for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end + `checkc(2); + for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end + `checkc(5); + for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end + `checkc(6); + for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end + `checkc(2); + for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end + `checkc(5); + for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end + `checkc(6); + for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end + `checkc(2); + for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end + `checkc(5); + for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end + `checkc(6); + for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end + `checkc(3); + for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end + `checkc(7); + for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end + `checkc(8); + for (int a = 1, x = 1; a < 3; a = a + 1, x = x + 1) begin c = c + 1 + a + x; end + `checkc(8); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index ad30094d9..05cf5ba6d 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -4,97 +4,102 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - integer j; - reg [63:0] cam_lookup_hit_vector; + integer j; + reg [63:0] cam_lookup_hit_vector; - integer hit_count; - always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin - hit_count = 0; - for (j=0; j < 64; j=j+1) begin - hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; + integer hit_count; + always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin + hit_count = 0; + for (j = 0; j < 64; j = j + 1) begin + hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; + end + end + + integer hit_count2; + always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin + hit_count2 = 0; + for (j = 63; j >= 0; j = j - 1) begin + hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; + end + end + + integer hit_count3; + always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin + hit_count3 = 0; + for (j = 63; j > 0; j = j - 1) begin + if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; + end + end + + reg [127:0] wide_for_index; + reg [31:0] wide_for_count; + always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin + wide_for_count = 0; + for ( + wide_for_index = 128'hff_00000000_00000000; + wide_for_index < 128'hff_00000000_00000100; + wide_for_index = wide_for_index + 2 + ) begin + wide_for_count = wide_for_count + 32'h1; + end + end + + // While loop + int w; + initial begin + while (w < 10) w = w + 1; + if (w != 10) $stop; + while (w < 20) begin + w = w + 2; + end + while (w < 20) begin + w = w + 99999; + end // NEVER + if (w != 20) $stop; + end + + // Do-While loop + int dw; + initial begin + do dw = dw + 1; while (dw < 10); + if (dw != 10) $stop; + do dw = dw + 2; while (dw < 20); + if (dw != 20) $stop; + do dw = dw + 5; while (dw < 20); // Once + if (dw != 25) $stop; + end + + always @(posedge clk) begin + cam_lookup_hit_vector <= 0; + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + cam_lookup_hit_vector <= 64'h00010000_00010000; end - end - - integer hit_count2; - always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin - hit_count2 = 0; - for (j=63; j >= 0; j=j-1) begin - hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; + if (cyc == 2) begin + if (hit_count != 32'd2) $stop; + if (hit_count2 != 32'd2) $stop; + if (hit_count3 != 32'd2) $stop; + cam_lookup_hit_vector <= 64'h01010010_00010001; end - end - - integer hit_count3; - always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin - hit_count3 = 0; - for (j=63; j > 0; j=j-1) begin - if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; + if (cyc == 3) begin + if (hit_count != 32'd5) $stop; + if (hit_count2 != 32'd5) $stop; + if (hit_count3 != 32'd4) $stop; + if (wide_for_count != 32'h80) $stop; end - end - - reg [127:0] wide_for_index; - reg [31:0] wide_for_count; - always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin - wide_for_count = 0; - for (wide_for_index = 128'hff_00000000_00000000; - wide_for_index < 128'hff_00000000_00000100; - wide_for_index = wide_for_index + 2) begin - wide_for_count = wide_for_count+32'h1; + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end - end - - // While loop - int w; - initial begin - while (w<10) w=w+1; - if (w!=10) $stop; - while (w<20) begin w=w+2; end - while (w<20) begin w=w+99999; end // NEVER - if (w!=20) $stop; - end - - // Do-While loop - int dw; - initial begin - do dw=dw+1; while (dw<10); - if (dw!=10) $stop; - do dw=dw+2; while (dw<20); - if (dw!=20) $stop; - do dw=dw+5; while (dw<20); // Once - if (dw!=25) $stop; - end - - always @ (posedge clk) begin - cam_lookup_hit_vector <= 0; - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - cam_lookup_hit_vector <= 64'h00010000_00010000; - end - if (cyc==2) begin - if (hit_count != 32'd2) $stop; - if (hit_count2 != 32'd2) $stop; - if (hit_count3 != 32'd2) $stop; - cam_lookup_hit_vector <= 64'h01010010_00010001; - end - if (cyc==3) begin - if (hit_count != 32'd5) $stop; - if (hit_count2 != 32'd5) $stop; - if (hit_count3 != 32'd4) $stop; - if (wide_for_count != 32'h80) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end + end + end endmodule diff --git a/test_regress/t/t_for_disable_dot.v b/test_regress/t/t_for_disable_dot.v index fe51ef5a8..314176a13 100644 --- a/test_regress/t/t_for_disable_dot.v +++ b/test_regress/t/t_for_disable_dot.v @@ -6,17 +6,17 @@ module t; - int i; + int i; - initial begin - begin : named - for (i = 0; i < 10; ++i) begin : loop - if (i == 5) disable t.named; - end + initial begin + begin : named + for (i = 0; i < 10; ++i) begin : loop + if (i == 5) disable t.named; end - if (i != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (i != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v index 992aa4f60..4ab1c22d0 100644 --- a/test_regress/t/t_for_funcbound.v +++ b/test_regress/t/t_for_funcbound.v @@ -4,74 +4,74 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer j; + integer hit_count; + reg [63:0] cam_lookup_hit_vector; - integer j; - integer hit_count; - reg [63:0] cam_lookup_hit_vector; + strings strings (); - strings strings (); - - task show; - input [8*8-1:0] str; - reg [7:0] char; - integer loc; - begin - $write("[%0t] ", $time); - strings.stringStart(8*8-1); - for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin - $write("%c",char); - end - $write("\n"); + task show; + input [8*8-1:0] str; + reg [7:0] char; + integer loc; + begin + $write("[%0t] ", $time); + strings.stringStart(8 * 8 - 1); + for ( + char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str) + ) begin + $write("%c", char); end - endtask + $write("\n"); + end + endtask - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - show("hello\000xx"); - end - if (cyc==2) begin - show("world\000xx"); - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + show("hello\000xx"); end - end + if (cyc == 2) begin + show("world\000xx"); + end + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module strings; - // **NOT** reentrant, just a test! - integer index; - task stringStart; - input [31:0] bits; - begin - index = (bits-1)/8; - end - endtask + // **NOT** reentrant, just a test! + integer index; + task stringStart; + input [31:0] bits; + begin + index = (bits - 1) / 8; + end + endtask - function isNull; - input [7:0] chr; - isNull = (chr == 8'h0); - endfunction + function isNull; + input [7:0] chr; + isNull = (chr == 8'h0); + endfunction - function [7:0] stringByte; - input [8*8-1:0] str; - begin - if (index<=0) stringByte=8'h0; - else stringByte = str[index*8 +: 8]; - index = index - 1; - end - endfunction + function [7:0] stringByte; + input [8*8-1:0] str; + begin + if (index <= 0) stringByte = 8'h0; + else stringByte = str[index*8+:8]; + index = index - 1; + end + endfunction endmodule diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v index 27da2447f..f10d5abb0 100644 --- a/test_regress/t/t_for_init_bug.v +++ b/test_regress/t/t_for_init_bug.v @@ -4,32 +4,31 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - priority_mask, - // Inputs - muxed_requests - ); +module t ( /*AUTOARG*/ + // Outputs + priority_mask, + // Inputs + muxed_requests +); - parameter ARW = 7; + parameter ARW = 7; - // verilator lint_off UNOPTFLAT - integer i,j; + // verilator lint_off UNOPTFLAT + integer i, j; - output reg [ARW-1:0] priority_mask; + output reg [ARW-1:0] priority_mask; - input [ARW-1:0] muxed_requests; + input [ARW-1:0] muxed_requests; - always @* begin - for (i=ARW-1;i>0;i=i-1) begin - priority_mask[i]=1'b0; - // vvvv=== note j=j not j=i; was bug - for( j=j;j>=0;j=j-1) - priority_mask[i]=priority_mask[j] | muxed_requests[j]; - end - //Bit zero is always enabled - priority_mask[0]=1'b0; - end + always @* begin + for (i = ARW - 1; i > 0; i = i - 1) begin + priority_mask[i] = 1'b0; + // vvvv=== note j=j not j=i; was bug + for (j = j; j >= 0; j = j - 1) priority_mask[i] = priority_mask[j] | muxed_requests[j]; + end + //Bit zero is always enabled + priority_mask[0] = 1'b0; + end endmodule diff --git a/test_regress/t/t_for_local.v b/test_regress/t/t_for_local.v index 44013f363..f177ec3f9 100644 --- a/test_regress/t/t_for_local.v +++ b/test_regress/t/t_for_local.v @@ -4,51 +4,50 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [7:0] cyc; initial cyc = 0; + reg [7:0] cyc; + initial cyc = 0; - reg [31:0] loops; - reg [31:0] loops2; + reg [31:0] loops; + reg [31:0] loops2; - always @ (posedge clk) begin - cyc <= cyc+8'd1; - if (cyc == 8'd1) begin - $write("[%0t] t_loop: Running\n", $time); - // Unwind < - loops = 0; - loops2 = 0; - for (int i=0; i<16; i=i+1) begin - loops = loops + i; // surefire lint_off_line ASWEMB - loops2 = loops2 + i; // surefire lint_off_line ASWEMB - end - if (loops !== 120) $stop; - if (loops2 !== 120) $stop; - // Check we can declare the same signal twice - loops = 0; - for (int i=0; i<=16; i=i+1) begin - loops = loops + 1; - end - if (loops !== 17) $stop; - // Check type is correct - loops = 0; - for (byte unsigned i=5; i>4; i=i+1) begin - loops = loops + 1; - end - if (loops !== 251) $stop; - // Check large loops - loops = 0; - for (int i=0; i<100000; i=i+1) begin - loops = loops + 1; - end - if (loops !== 100000) $stop; - $write("*-* All Finished *-*\n"); - $finish; + always @(posedge clk) begin + cyc <= cyc + 8'd1; + if (cyc == 8'd1) begin + $write("[%0t] t_loop: Running\n", $time); + // Unwind < + loops = 0; + loops2 = 0; + for (int i = 0; i < 16; i = i + 1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB end - end + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Check we can declare the same signal twice + loops = 0; + for (int i = 0; i <= 16; i = i + 1) begin + loops = loops + 1; + end + if (loops !== 17) $stop; + // Check type is correct + loops = 0; + for (byte unsigned i = 5; i > 4; i = i + 1) begin + loops = loops + 1; + end + if (loops !== 251) $stop; + // Check large loops + loops = 0; + for (int i = 0; i < 100000; i = i + 1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v index 2f7c81088..f4b90ebfb 100644 --- a/test_regress/t/t_for_loop.v +++ b/test_regress/t/t_for_loop.v @@ -4,114 +4,119 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [7:0] cyc; initial cyc = 0; + reg [7:0] cyc; + initial cyc = 0; - reg [31:0] loops; - reg [31:0] loops2; - integer i; + reg [31:0] loops; + reg [31:0] loops2; + integer i; - always @ (posedge clk) begin - cyc <= cyc+8'd1; - if (cyc == 8'd1) begin - $write("[%0t] t_loop: Running\n", $time); - // Unwind < - loops = 0; - loops2 = 0; - for (i=0; i<16; i=i+1) begin - loops = loops + i; // surefire lint_off_line ASWEMB - loops2 = loops2 + i; // surefire lint_off_line ASWEMB - end - if (i !== 16) $stop; - if (loops !== 120) $stop; - if (loops2 !== 120) $stop; - // Unwind <= - loops = 0; - for (i=0; i<=16; i=i+1) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Don't unwind breaked loops - loops = 0; - for (i=0; i<16; i=i+1) begin - loops = loops + 1; - if (i==7) i=99; // break out of loop - end - if (loops !== 8) $stop; - // Don't unwind large loops! - loops = 0; - for (i=0; i<100000; i=i+1) begin - loops = loops + 1; - end - if (loops !== 100000) $stop; - // Test post-increment - loops = 0; - for (i=0; i<=16; i++) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Test pre-increment - loops = 0; - for (i=0; i<=16; ++i) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Test post-decrement - loops = 0; - for (i=16; i>=0; i--) begin - loops = loops + 1; - end - if (i !== -1) $stop; - if (loops !== 17) $stop; - // Test pre-decrement - loops = 0; - for (i=16; i>=0; --i) begin - loops = loops + 1; - end - if (i !== -1) $stop; - if (loops !== 17) $stop; - // - // 1800-2017 optionals init/expr/incr - loops = 0; - i = 0; - for (; i<10; ++i) ++loops; - if (loops !== 10) $stop; - // - loops = 0; - i = 0; - for (i=0; i<10; ) begin ++loops; ++i; end - if (loops !== 10) $stop; - // - loops = 0; - i = 0; - for (; ; ++i) begin ++loops; break; end - if (loops !== 1) $stop; - // - // bug1605 - i = 1; - for (i=20; 0; ) ; - if (i != 20) $stop; - for (i=30; i<10; i++) ; - if (i != 30) $stop; - // Comma - loops = 0; - for (i=0; i<20; ++i, ++loops); - if (loops !== 20) $stop; - loops = 0; - for (i=0; i<20; ++loops, ++i); - if (loops !== 20) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + always @(posedge clk) begin + cyc <= cyc + 8'd1; + if (cyc == 8'd1) begin + $write("[%0t] t_loop: Running\n", $time); + // Unwind < + loops = 0; + loops2 = 0; + for (i = 0; i < 16; i = i + 1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB end - end + if (i !== 16) $stop; + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Unwind <= + loops = 0; + for (i = 0; i <= 16; i = i + 1) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Don't unwind breaked loops + loops = 0; + for (i = 0; i < 16; i = i + 1) begin + loops = loops + 1; + if (i == 7) i = 99; // break out of loop + end + if (loops !== 8) $stop; + // Don't unwind large loops! + loops = 0; + for (i = 0; i < 100000; i = i + 1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + // Test post-increment + loops = 0; + for (i = 0; i <= 16; i++) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test pre-increment + loops = 0; + for (i = 0; i <= 16; ++i) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test post-decrement + loops = 0; + for (i = 16; i >= 0; i--) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // Test pre-decrement + loops = 0; + for (i = 16; i >= 0; --i) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // + // 1800-2017 optionals init/expr/incr + loops = 0; + i = 0; + for (; i < 10; ++i)++loops; + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (i = 0; i < 10;) begin + ++loops; + ++i; + end + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (;; ++i) begin + ++loops; + break; + end + if (loops !== 1) $stop; + // + // bug1605 + i = 1; + for (i = 20; 0;); + if (i != 20) $stop; + for (i = 30; i < 10; i++); + if (i != 30) $stop; + // Comma + loops = 0; + for (i = 0; i < 20; ++i, ++loops); + if (loops !== 20) $stop; + loops = 0; + for (i = 0; i < 20; ++loops, ++i); + if (loops !== 20) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_force.v b/test_regress/t/t_force.v index 0112a7c8a..858b42ebb 100644 --- a/test_regress/t/t_force.v +++ b/test_regress/t/t_force.v @@ -10,119 +10,117 @@ `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [3:0] in; - tri [3:0] bus = in; + reg [3:0] in; + tri [3:0] bus = in; - int never_driven; - int never_forced; + int never_driven; + int never_forced; - real r; + real r; - task force_bus; - force bus[1:0] = 2'b10; - endtask + task force_bus; + force bus[1:0] = 2'b10; + endtask - task release_bus; + task release_bus; + release bus; + endtask + + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + in <= 4'b0101; + end + else if (cyc == 1) begin + `checkh(in, 4'b0101); + end + // Check forces with no driver + if (cyc == 1) begin + force never_driven = 32'h888; + end + else if (cyc == 2) begin + `checkh(never_driven, 32'h888); + end + // + // Check release with no force + else if (cyc == 10) begin + never_forced <= 5432; + end + else if (cyc == 11) begin + `checkh(never_forced, 5432); + end + else if (cyc == 12) begin + release never_forced; // no-op + end + else if (cyc == 13) begin + `checkh(never_forced, 5432); + end + // + // bus + else if (cyc == 20) begin + `checkh(bus, 4'b0101); + force bus = 4'b0111; + end + else if (cyc == 21) begin + `checkh(bus, 4'b0111); + force bus = 4'b1111; + end + else if (cyc == 22) begin + `checkh(bus, 4'b1111); release bus; - endtask - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - in <= 4'b0101; - end - else if (cyc == 1) begin - `checkh(in, 4'b0101); - end - // Check forces with no driver - if (cyc == 1) begin - force never_driven = 32'h888; - end - else if (cyc == 2) begin - `checkh(never_driven, 32'h888); - end - // - // Check release with no force - else if (cyc == 10) begin - never_forced <= 5432; - end - else if (cyc == 11) begin - `checkh(never_forced, 5432); - end - else if (cyc == 12) begin - release never_forced; // no-op - end - else if (cyc == 13) begin - `checkh(never_forced, 5432); - end - // - // bus - else if (cyc == 20) begin - `checkh(bus, 4'b0101); - force bus = 4'b0111; - end - else if (cyc == 21) begin - `checkh(bus, 4'b0111); - force bus = 4'b1111; - end - else if (cyc == 22) begin - `checkh(bus, 4'b1111); - release bus; - end - else if (cyc == 23) begin - `checkh(bus, 4'b0101); - end - // - else if (cyc == 30) begin - force_bus(); - end - else if (cyc == 31) begin - `checkh(bus, 4'b0110); - end - else if (cyc == 32) begin - release bus[0]; - end - else if (cyc == 33) begin - `checkh(bus, 4'b0111); - release_bus(); - end - else if (cyc == 34) begin - `checkh(in, 4'b0101); - `checkh(bus, 4'b0101); - end - // - else if (cyc == 40) begin - r <= 1.25; - end - else if (cyc == 41) begin - `checkr(r, 1.25); - end - else if (cyc == 42) begin - force r = 2.5; - end - else if (cyc == 43) begin - `checkr(r, 2.5); - end - else if (cyc == 44) begin - release r; - end - else if (cyc == 45) begin - `checkr(r, 2.5); - end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + else if (cyc == 23) begin + `checkh(bus, 4'b0101); + end + // + else if (cyc == 30) begin + force_bus(); + end + else if (cyc == 31) begin + `checkh(bus, 4'b0110); + end + else if (cyc == 32) begin + release bus[0]; + end + else if (cyc == 33) begin + `checkh(bus, 4'b0111); + release_bus(); + end + else if (cyc == 34) begin + `checkh(in, 4'b0101); + `checkh(bus, 4'b0101); + end + // + else if (cyc == 40) begin + r <= 1.25; + end + else if (cyc == 41) begin + `checkr(r, 1.25); + end + else if (cyc == 42) begin + force r = 2.5; + end + else if (cyc == 43) begin + `checkr(r, 2.5); + end + else if (cyc == 44) begin + release r; + end + else if (cyc == 45) begin + `checkr(r, 2.5); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_force_bad_rw.out b/test_regress/t/t_force_bad_rw.out index 65c9076b4..b9656d8d5 100644 --- a/test_regress/t/t_force_bad_rw.out +++ b/test_regress/t/t_force_bad_rw.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced - 14 | foreach (ass[index]) begin - | ^~~~~ +%Error-UNSUPPORTED: t/t_force_bad_rw.v:14:18: Unsupported: Signals used via read-write reference cannot be forced + 14 | foreach (ass[index]) begin + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_force_bad_rw.v b/test_regress/t/t_force_bad_rw.v index b9259fb07..d80a819da 100644 --- a/test_regress/t/t_force_bad_rw.v +++ b/test_regress/t/t_force_bad_rw.v @@ -6,18 +6,18 @@ module t; - int ass[int]; + int ass[int]; - initial begin - ass[2] = 20; + initial begin + ass[2] = 20; - foreach (ass[index]) begin - force index = 0; - $display("ii %d\n", index); - end + foreach (ass[index]) begin + force index = 0; + $display("ii %d\n", index); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_force_chained.v b/test_regress/t/t_force_chained.v index c046aa8f4..e197ee355 100644 --- a/test_regress/t/t_force_chained.v +++ b/test_regress/t/t_force_chained.v @@ -9,7 +9,7 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on - module t; +module t; reg [1:0] a; wire [1:0] b = 1; bit [1:0] c; diff --git a/test_regress/t/t_force_func.v b/test_regress/t/t_force_func.v index e61404763..5586d8061 100644 --- a/test_regress/t/t_force_func.v +++ b/test_regress/t/t_force_func.v @@ -9,8 +9,8 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on - function bit [1:0] get_arg (bit [1:0] x); - return x; +function bit [1:0] get_arg(bit [1:0] x); + return x; endfunction module t; diff --git a/test_regress/t/t_force_initial.v b/test_regress/t/t_force_initial.v index bd25714ab..b381b3bc9 100644 --- a/test_regress/t/t_force_initial.v +++ b/test_regress/t/t_force_initial.v @@ -9,14 +9,14 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on - module t; +module t; reg [1:0] a = 0; reg [1:0] b = 2; initial begin - force b = a; - `checkh(a, 0); - `checkh(b, 0); + force b = a; + `checkh(a, 0); + `checkh(b, 0); end initial begin diff --git a/test_regress/t/t_force_input_assign_bad.out b/test_regress/t/t_force_input_assign_bad.out index 133179ba5..bcdcd234c 100644 --- a/test_regress/t/t_force_input_assign_bad.out +++ b/test_regress/t/t_force_input_assign_bad.out @@ -1,14 +1,14 @@ -%Error-ASSIGNIN: t/t_force_input_assign_bad.v:18:10: Assigning to input/const variable: 'i' - : ... note: In instance 't' - 18 | s1.i = 2; - | ^ +%Error-ASSIGNIN: t/t_force_input_assign_bad.v:20:8: Assigning to input/const variable: 'i' + : ... note: In instance 't' + 20 | s1.i = 2; + | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest -%Error-ASSIGNIN: t/t_force_input_assign_bad.v:21:10: Assigning to input/const variable: 'i' +%Error-ASSIGNIN: t/t_force_input_assign_bad.v:23:8: Assigning to input/const variable: 'i' + : ... note: In instance 't' + 23 | s2.i = 2; + | ^ +%Error-ASSIGNIN: t/t_force_input_assign_bad.v:27:15: Assigning to input/const variable: 'i' : ... note: In instance 't' - 21 | s2.i = 2; - | ^ -%Error-ASSIGNIN: t/t_force_input_assign_bad.v:25:17: Assigning to input/const variable: 'i' - : ... note: In instance 't' - 25 | assign s3.i = 2; - | ^ + 27 | assign s3.i = 2; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_force_input_assign_bad.v b/test_regress/t/t_force_input_assign_bad.v index 4635ca000..339ced0bb 100644 --- a/test_regress/t/t_force_input_assign_bad.v +++ b/test_regress/t/t_force_input_assign_bad.v @@ -4,29 +4,31 @@ // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -module sub(input [1:0] i); +module sub ( + input [1:0] i +); endmodule module t; - sub s1(1); - sub s2(1); - sub s3(1); - sub s4(1); - sub s5(1); + sub s1 (1); + sub s2 (1); + sub s3 (1); + sub s4 (1); + sub s5 (1); initial begin - // these should fail - s1.i = 2; - force s1.i = '1; + // these should fail + s1.i = 2; + force s1.i = '1; - s2.i = 2; - release s2.i; + s2.i = 2; + release s2.i; - force s3.i = '1; - assign s3.i = 2; + force s3.i = '1; + assign s3.i = 2; - // these should not - force s4.i = '1; + // these should not + force s4.i = '1; - release s5.i; + release s5.i; end endmodule diff --git a/test_regress/t/t_force_mid.v b/test_regress/t/t_force_mid.v index 24209fab3..e93ca1cd3 100644 --- a/test_regress/t/t_force_mid.v +++ b/test_regress/t/t_force_mid.v @@ -9,54 +9,55 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t(/*AUTOARG*/ - // Outputs - topout, - // Inputs - clk, topin - ); +module t ( /*AUTOARG*/ + // Outputs + topout, + // Inputs + clk, + topin +); - input clk; - input [3:0] topin; - output [3:0] topout; + input clk; + input [3:0] topin; + output [3:0] topout; - integer cyc = 0; + integer cyc = 0; - assign topout = 4'b0101; + assign topout = 4'b0101; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - if (topout != 4'b0101) $stop; - if (topin != 4'b1001) $stop; - end - else if (cyc == 1) begin - force topout = 4'b1010; - end - else if (cyc == 2) begin - if (topout != 4'b1010) $stop; - release topout; - end - else if (cyc == 3) begin - if (topout != 4'b0101) $stop; - end - else if (cyc == 4) begin - force topin = 4'b1100; - end - else if (cyc == 5) begin - if (topin != 4'b1100) $stop; - release topin; - end - else if (cyc == 6) begin - if (topin != 4'b1001) $stop; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + if (topout != 4'b0101) $stop; + if (topin != 4'b1001) $stop; + end + else if (cyc == 1) begin + force topout = 4'b1010; + end + else if (cyc == 2) begin + if (topout != 4'b1010) $stop; + release topout; + end + else if (cyc == 3) begin + if (topout != 4'b0101) $stop; + end + else if (cyc == 4) begin + force topin = 4'b1100; + end + else if (cyc == 5) begin + if (topin != 4'b1100) $stop; + release topin; + end + else if (cyc == 6) begin + if (topin != 4'b1001) $stop; + end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_force_multi.v b/test_regress/t/t_force_multi.v index 9445577bf..c856443e5 100644 --- a/test_regress/t/t_force_multi.v +++ b/test_regress/t/t_force_multi.v @@ -11,9 +11,8 @@ module t(/*AUTOARG*/ // Inputs - clk + input clk ); - input clk; integer cyc = 0; diff --git a/test_regress/t/t_force_release.v b/test_regress/t/t_force_release.v index 02908831d..6fcefb6af 100644 --- a/test_regress/t/t_force_release.v +++ b/test_regress/t/t_force_release.v @@ -11,7 +11,7 @@ // Example from IEEE 1800-2023 10.6.2 - module t; +module t; logic a, b, c, d; wire e; and and1 (e, a, b, c); diff --git a/test_regress/t/t_force_release_net.v b/test_regress/t/t_force_release_net.v index 4a7b71bce..bfe504971 100644 --- a/test_regress/t/t_force_release_net.v +++ b/test_regress/t/t_force_release_net.v @@ -9,126 +9,123 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - int cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + wire net_1; + wire [7:0] net_8, alias_net_8; + assign net_1 = ~cyc[0]; + assign net_8 = ~cyc[1+:8]; + alias net_8 = alias_net_8; - wire net_1; - wire [7:0] net_8, alias_net_8; - assign net_1 = ~cyc[0]; - assign net_8 = ~cyc[1 +: 8]; - alias net_8 = alias_net_8; + always @(posedge clk) begin + $display("%d pre : %x %x", cyc, net_8, net_1); - always @ (posedge clk) begin - $display("%d pre : %x %x", cyc, net_8, net_1); - - case (cyc) - 4: begin - `checkh (net_1, 0); - `checkh (net_8, ~cyc[1 +: 8]); - end - 5: begin - `checkh (net_1, 0); - `checkh (net_8, 8'h5f); - end - 6: begin - `checkh (net_1, 1); - `checkh (net_8, 8'h5f); - end - 7, 8: begin - `checkh (net_1, 1); - `checkh (net_8, 8'hf5); - end - 9: begin - `checkh (net_1, ~cyc[0]); - `checkh (net_8, 8'hf5); - end - 11, 12: begin - `checkh (net_1, 1); - `checkh (net_8, 8'h5a); - end - 13, 14: begin - `checkh (net_1, 0); - `checkh (net_8, 8'ha5); - end - default: begin - `checkh ({net_8, net_1}, ~cyc[0 +: 9]); - end - endcase + case (cyc) + 4: begin + `checkh(net_1, 0); + `checkh(net_8, ~cyc[1+:8]); + end + 5: begin + `checkh(net_1, 0); + `checkh(net_8, 8'h5f); + end + 6: begin + `checkh(net_1, 1); + `checkh(net_8, 8'h5f); + end + 7, 8: begin + `checkh(net_1, 1); + `checkh(net_8, 8'hf5); + end + 9: begin + `checkh(net_1, ~cyc[0]); + `checkh(net_8, 8'hf5); + end + 11, 12: begin + `checkh(net_1, 1); + `checkh(net_8, 8'h5a); + end + 13, 14: begin + `checkh(net_1, 0); + `checkh(net_8, 8'ha5); + end + default: begin + `checkh({net_8, net_1}, ~cyc[0+:9]); + end + endcase `ifndef REVERSE - if (cyc == 3) force net_1 = 0; - if (cyc == 5) force net_1 = 1; - if (cyc == 8) release net_1; + if (cyc == 3) force net_1 = 0; + if (cyc == 5) force net_1 = 1; + if (cyc == 8) release net_1; - if (cyc == 4) force net_8 = 8'h5f; - if (cyc == 6) force net_8 = 8'hf5; - if (cyc == 9) release net_8; + if (cyc == 4) force net_8 = 8'h5f; + if (cyc == 6) force net_8 = 8'hf5; + if (cyc == 9) release net_8; - if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; - if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; - if (cyc == 14) release {net_1, net_8}; + if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; + if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; + if (cyc == 14) release {net_1, net_8}; `else - if (cyc == 8) release net_1; - if (cyc == 5) force net_1 = 1; - if (cyc == 3) force net_1 = 0; + if (cyc == 8) release net_1; + if (cyc == 5) force net_1 = 1; + if (cyc == 3) force net_1 = 0; - if (cyc == 9) release net_8; - if (cyc == 6) force net_8 = 8'hf5; - if (cyc == 4) force net_8 = 8'h5f; + if (cyc == 9) release net_8; + if (cyc == 6) force net_8 = 8'hf5; + if (cyc == 4) force net_8 = 8'h5f; - if (cyc == 14) release {net_1, net_8}; - if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; - if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; + if (cyc == 14) release {net_1, net_8}; + if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; + if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; `endif - $display("%d post: %x %x", cyc, net_8, net_1); + $display("%d post: %x %x", cyc, net_8, net_1); - case (cyc) - 3: begin - `checkh (net_1, 0); - `checkh (net_8, ~cyc[1 +: 8]); - end - 4: begin - `checkh (net_1, 0); - `checkh (net_8, 8'h5f); - end - 5: begin - `checkh (net_1, 1); - `checkh (net_8, 8'h5f); - end - 6, 7: begin - `checkh (net_1, 1); - `checkh (net_8, 8'hf5); - end - 8: begin - `checkh (net_1, ~cyc[0]); - `checkh (net_8, 8'hf5); - end - 10, 11: begin - `checkh (net_1, 1); - `checkh (net_8, 8'h5a); - end - 12, 13: begin - `checkh (net_1, 0); - `checkh (net_8, 8'ha5); - end - default: begin - `checkh ({net_8, net_1}, ~cyc[0 +: 9]); - `checkh ({alias_net_8, net_1}, ~cyc[0 +: 9]); - end - endcase - - if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; + case (cyc) + 3: begin + `checkh(net_1, 0); + `checkh(net_8, ~cyc[1+:8]); end - end + 4: begin + `checkh(net_1, 0); + `checkh(net_8, 8'h5f); + end + 5: begin + `checkh(net_1, 1); + `checkh(net_8, 8'h5f); + end + 6, 7: begin + `checkh(net_1, 1); + `checkh(net_8, 8'hf5); + end + 8: begin + `checkh(net_1, ~cyc[0]); + `checkh(net_8, 8'hf5); + end + 10, 11: begin + `checkh(net_1, 1); + `checkh(net_8, 8'h5a); + end + 12, 13: begin + `checkh(net_1, 0); + `checkh(net_8, 8'ha5); + end + default: begin + `checkh({net_8, net_1}, ~cyc[0+:9]); + `checkh({alias_net_8, net_1}, ~cyc[0+:9]); + end + endcase + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_force_release_var.v b/test_regress/t/t_force_release_var.v index b98cc2608..98b906013 100644 --- a/test_regress/t/t_force_release_var.v +++ b/test_regress/t/t_force_release_var.v @@ -9,132 +9,129 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; - int cyc = 0; - always @(posedge clk) cyc <= cyc + 1; + reg var_1 = 0; + reg [7:0] var_8 = 0; + always @(posedge clk) begin + var_1 <= cyc[0]; + var_8 <= cyc[1+:8]; + end - reg var_1 = 0; - reg [7:0] var_8 = 0; - always @(posedge clk) begin - var_1 <= cyc[0]; - var_8 <= cyc[1 +: 8]; - end + always @(posedge clk) begin + $display("%d pre : %x %x", cyc, var_8, var_1); - always @ (posedge clk) begin - $display("%d pre : %x %x", cyc, var_8, var_1); - - case (cyc) - 0: begin - // Uninitialized - end - 14: begin - `checkh (var_1, 1); - `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); - end - 15: begin - `checkh (var_1, 1); - `checkh (var_8, 8'hf5); - end - 16: begin - `checkh (var_1, 0); - `checkh (var_8, 8'hf5); - end - 17, 18: begin - `checkh (var_1, 0); - `checkh (var_8, 8'h5f); - end - 19: begin - `checkh (var_1, ~cyc[0]); - `checkh (var_8, 8'h5f); - end - 21, 22: begin - `checkh (var_1, 1); - `checkh (var_8, 8'h5a); - end - 23, 24: begin - `checkh (var_1, 0); - `checkh (var_8, 8'ha5); - end - default: begin - `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); - end - endcase + case (cyc) + 0: begin + // Uninitialized + end + 14: begin + `checkh(var_1, 1); + `checkh({1'b0, var_8}, (cyc[0+:9] - 1) >> 1); + end + 15: begin + `checkh(var_1, 1); + `checkh(var_8, 8'hf5); + end + 16: begin + `checkh(var_1, 0); + `checkh(var_8, 8'hf5); + end + 17, 18: begin + `checkh(var_1, 0); + `checkh(var_8, 8'h5f); + end + 19: begin + `checkh(var_1, ~cyc[0]); + `checkh(var_8, 8'h5f); + end + 21, 22: begin + `checkh(var_1, 1); + `checkh(var_8, 8'h5a); + end + 23, 24: begin + `checkh(var_1, 0); + `checkh(var_8, 8'ha5); + end + default: begin + `checkh({var_8, var_1}, cyc[0+:9] - 1); + end + endcase `ifndef REVERSE - if (cyc == 13) force var_1 = 1; - if (cyc == 15) force var_1 = 0; - if (cyc == 18) release var_1; + if (cyc == 13) force var_1 = 1; + if (cyc == 15) force var_1 = 0; + if (cyc == 18) release var_1; - if (cyc == 14) force var_8 = 8'hf5; - if (cyc == 16) force var_8 = 8'h5f; - if (cyc == 19) release var_8; + if (cyc == 14) force var_8 = 8'hf5; + if (cyc == 16) force var_8 = 8'h5f; + if (cyc == 19) release var_8; - if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; - if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; - if (cyc == 24) release {var_1, var_8}; + if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; + if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; + if (cyc == 24) release {var_1, var_8}; `else - if (cyc == 18) release var_1; - if (cyc == 15) force var_1 = 0; - if (cyc == 13) force var_1 = 1; + if (cyc == 18) release var_1; + if (cyc == 15) force var_1 = 0; + if (cyc == 13) force var_1 = 1; - if (cyc == 19) release var_8; - if (cyc == 16) force var_8 = 8'h5f; - if (cyc == 14) force var_8 = 8'hf5; + if (cyc == 19) release var_8; + if (cyc == 16) force var_8 = 8'h5f; + if (cyc == 14) force var_8 = 8'hf5; - if (cyc == 24) release {var_1, var_8}; - if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; - if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; + if (cyc == 24) release {var_1, var_8}; + if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; + if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; `endif - $display("%d post: %x %x", cyc, var_8, var_1); + $display("%d post: %x %x", cyc, var_8, var_1); - case (cyc) - 0: begin - // Uninitialized - end - 13: begin - `checkh (var_1, 1); - `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); - end - 14: begin - `checkh (var_1, 1); - `checkh (var_8, 8'hf5); - end - 15: begin - `checkh (var_1, 0); - `checkh (var_8, 8'hf5); - end - 16, 17, 18: begin - `checkh (var_1, 0); - `checkh (var_8, 8'h5f); - end - 19: begin - `checkh (var_1, ~cyc[0]); - `checkh (var_8, 8'h5f); - end - 20, 21: begin - `checkh (var_1, 1); - `checkh (var_8, 8'h5a); - end - 22, 23, 24: begin - `checkh (var_1, 0); - `checkh (var_8, 8'ha5); - end - default: begin - `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); - end - endcase - - if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; + case (cyc) + 0: begin + // Uninitialized end - end + 13: begin + `checkh(var_1, 1); + `checkh({1'b0, var_8}, (cyc[0+:9] - 1) >> 1); + end + 14: begin + `checkh(var_1, 1); + `checkh(var_8, 8'hf5); + end + 15: begin + `checkh(var_1, 0); + `checkh(var_8, 8'hf5); + end + 16, 17, 18: begin + `checkh(var_1, 0); + `checkh(var_8, 8'h5f); + end + 19: begin + `checkh(var_1, ~cyc[0]); + `checkh(var_8, 8'h5f); + end + 20, 21: begin + `checkh(var_1, 1); + `checkh(var_8, 8'h5a); + end + 22, 23, 24: begin + `checkh(var_1, 0); + `checkh(var_8, 8'ha5); + end + default: begin + `checkh({var_8, var_1}, cyc[0+:9] - 1); + end + endcase + + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_force_struct_partial.v b/test_regress/t/t_force_struct_partial.v index a2e8f4762..7c6d8a610 100644 --- a/test_regress/t/t_force_struct_partial.v +++ b/test_regress/t/t_force_struct_partial.v @@ -10,24 +10,26 @@ // verilog_format: on typedef struct packed { - logic sig1; - logic sig2; - logic not_forced; + logic sig1; + logic sig2; + logic not_forced; } s1; -module t(clk); - input clk; - s1 s1inst; - logic a = 1'b0; - logic b; - initial force s1inst.sig1 = a; - always @(posedge clk) begin - force s1inst.sig2 = 1'b1; - force s1inst.sig1 = b; +module t ( + clk +); + input clk; + s1 s1inst; + logic a = 1'b0; + logic b; + initial force s1inst.sig1 = a; + always @(posedge clk) begin + force s1inst.sig2 = 1'b1; + force s1inst.sig1 = b; - `checkh(s1inst.sig1, b); - `checkh(s1inst.sig2, 1'b1); + `checkh(s1inst.sig1, b); + `checkh(s1inst.sig2, 1'b1); - $finish; - end + $finish; + end endmodule diff --git a/test_regress/t/t_force_subnet.v b/test_regress/t/t_force_subnet.v index 1b3be4fc7..903344779 100644 --- a/test_regress/t/t_force_subnet.v +++ b/test_regress/t/t_force_subnet.v @@ -9,48 +9,48 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - logic [7:0] subnet; - sub1 sub1(.*); + logic [7:0] subnet; + sub1 sub1 (.*); - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - `checkh(subnet, 8'h11); - force sub1.subnet = 8'h01; // sub1.subnet *not* the same as subnet - end - else if (cyc == 11) begin - `checkh(subnet, 8'h01); - force subnet = 8'h10; // sub1.subnet *not* the same as subnet - end - else if (cyc == 12) begin - `checkh(subnet, 8'h10); - release subnet; // sub1.subnet *not* same as subnet - end - else if (cyc == 13) begin - `checkh(subnet, 8'h01); - release sub1.subnet; - end - else if (cyc == 13) begin - `checkh(subnet, 8'h11); - end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + `checkh(subnet, 8'h11); + force sub1.subnet = 8'h01; // sub1.subnet *not* the same as subnet + end + else if (cyc == 11) begin + `checkh(subnet, 8'h01); + force subnet = 8'h10; // sub1.subnet *not* the same as subnet + end + else if (cyc == 12) begin + `checkh(subnet, 8'h10); + release subnet; // sub1.subnet *not* same as subnet + end + else if (cyc == 13) begin + `checkh(subnet, 8'h01); + release sub1.subnet; + end + else if (cyc == 13) begin + `checkh(subnet, 8'h11); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub1(output logic [7:0] subnet); - assign subnet = 8'h11; +module sub1 ( + output logic [7:0] subnet +); + assign subnet = 8'h11; endmodule diff --git a/test_regress/t/t_force_subvar.v b/test_regress/t/t_force_subvar.v index a53802be8..b3764ff34 100644 --- a/test_regress/t/t_force_subvar.v +++ b/test_regress/t/t_force_subvar.v @@ -9,51 +9,49 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - sub sub(); + sub sub (); - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - // procedural var sub.subvar - if (cyc == 50) begin - `checkh(sub.subvar, 32'h666); - force sub.subvar = 32'hffff; - end - else if (cyc == 51) begin - `checkh(sub.subvar, 32'hffff); - sub.subvar = 32'h543; // Ignored as still forced - end - else if (cyc == 52) begin - `checkh(sub.subvar, 32'hffff); - end - else if (cyc == 53) begin - release sub.subvar; - end - else if (cyc == 54) begin - `checkh(sub.subvar, 32'hffff); // Retains value until next procedural change - sub.subvar = 32'h544; - end - else if (cyc == 56) begin - `checkh(sub.subvar, 32'h544); - end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + // procedural var sub.subvar + if (cyc == 50) begin + `checkh(sub.subvar, 32'h666); + force sub.subvar = 32'hffff; + end + else if (cyc == 51) begin + `checkh(sub.subvar, 32'hffff); + sub.subvar = 32'h543; // Ignored as still forced + end + else if (cyc == 52) begin + `checkh(sub.subvar, 32'hffff); + end + else if (cyc == 53) begin + release sub.subvar; + end + else if (cyc == 54) begin + `checkh(sub.subvar, 32'hffff); // Retains value until next procedural change + sub.subvar = 32'h544; + end + else if (cyc == 56) begin + `checkh(sub.subvar, 32'h544); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module sub; - int subvar; - initial subvar = 32'h666; + int subvar; + initial subvar = 32'h666; endmodule diff --git a/test_regress/t/t_force_tri.out b/test_regress/t/t_force_tri.out index ec2e7742f..96360d50b 100644 --- a/test_regress/t/t_force_tri.out +++ b/test_regress/t/t_force_tri.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_force_tri.v:29:10: Unsupported tristate construct: ASSIGNFORCE - : ... note: In instance 't' - 29 | force bus = 4'bzz10; - | ^~~~~ +%Error-UNSUPPORTED: t/t_force_tri.v:27:7: Unsupported tristate construct: ASSIGNFORCE + : ... note: In instance 't' + 27 | force bus = 4'bzz10; + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_force_tri.v b/test_regress/t/t_force_tri.v index bf6c26dc8..3c304fc42 100644 --- a/test_regress/t/t_force_tri.v +++ b/test_regress/t/t_force_tri.v @@ -9,33 +9,31 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - logic [3:0] bus; + logic [3:0] bus; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - bus <= 4'b0101; - end - else if (cyc == 1) begin - force bus = 4'bzz10; - end - else if (cyc == 2) begin - `checkh(bus, 4'bzz10); - end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + bus <= 4'b0101; + end + else if (cyc == 1) begin + force bus = 4'bzz10; + end + else if (cyc == 2) begin + `checkh(bus, 4'bzz10); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_forceable_net.v b/test_regress/t/t_forceable_net.v index 910551852..58771947f 100644 --- a/test_regress/t/t_forceable_net.v +++ b/test_regress/t/t_forceable_net.v @@ -4,80 +4,83 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t ( - input wire clk, - input wire rst, - output reg [31:0] cyc - ); + input wire clk, + input wire rst, + output reg [31:0] cyc +); - always @(posedge clk) begin - if (rst) begin - cyc <= 0; - end else begin - cyc <= cyc +1; - end - end + always @(posedge clk) begin + if (rst) begin + cyc <= 0; + end + else begin + cyc <= cyc + 1; + end + end `ifdef CMT - wire net_1 /* verilator forceable */; - wire [7:0] net_8 /* verilator forceable */; + wire net_1 /* verilator forceable */; + wire [7:0] net_8 /* verilator forceable */; `else - wire net_1; - wire [7:0] net_8; + wire net_1; + wire [7:0] net_8; `endif - assign net_1 = ~cyc[0]; - assign net_8 = ~cyc[1 +: 8]; + assign net_1 = ~cyc[0]; + assign net_8 = ~cyc[1+:8]; - wire obs_1 = net_1; - wire [7:0] obs_8 = net_8; + wire obs_1 = net_1; + wire [7:0] obs_8 = net_8; - always @ (posedge clk) begin - $display("%d: %x %x", cyc, obs_8, obs_1); + always @(posedge clk) begin + $display("%d: %x %x", cyc, obs_8, obs_1); - if (!rst) begin - case (cyc) - 3: begin - `checkh (obs_1, 0); - `checkh (obs_8, ~cyc[1 +: 8]); - end - 4: begin - `checkh (obs_1, 0); - `checkh (obs_8, 8'h5f); - end - 5: begin - `checkh (obs_1, 1); - `checkh (obs_8, 8'h5f); - end - 6, 7: begin - `checkh (obs_1, 1); - `checkh (obs_8, 8'hf5); - end - 8: begin - `checkh (obs_1, ~cyc[0]); - `checkh (obs_8, 8'hf5); - end - 10, 11: begin - `checkh (obs_1, 1); - `checkh (obs_8, 8'h5a); - end - 12, 13: begin - `checkh (obs_1, 0); - `checkh (obs_8, 8'ha5); - end - default: begin - `checkh ({obs_8, obs_1}, ~cyc[0 +: 9]); - end - endcase - end + if (!rst) begin + case (cyc) + 3: begin + `checkh(obs_1, 0); + `checkh(obs_8, ~cyc[1+:8]); + end + 4: begin + `checkh(obs_1, 0); + `checkh(obs_8, 8'h5f); + end + 5: begin + `checkh(obs_1, 1); + `checkh(obs_8, 8'h5f); + end + 6, 7: begin + `checkh(obs_1, 1); + `checkh(obs_8, 8'hf5); + end + 8: begin + `checkh(obs_1, ~cyc[0]); + `checkh(obs_8, 8'hf5); + end + 10, 11: begin + `checkh(obs_1, 1); + `checkh(obs_8, 8'h5a); + end + 12, 13: begin + `checkh(obs_1, 0); + `checkh(obs_8, 8'ha5); + end + default: begin + `checkh({obs_8, obs_1}, ~cyc[0+:9]); + end + endcase + end - if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_forceable_var.v b/test_regress/t/t_forceable_var.v index 9423c942d..c6613ed0a 100644 --- a/test_regress/t/t_forceable_var.v +++ b/test_regress/t/t_forceable_var.v @@ -4,100 +4,104 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t ( - input wire clk, - input wire rst, - output reg [31:0] cyc - ); + input wire clk, + input wire rst, + output reg [31:0] cyc +); - always @(posedge clk) begin - if (rst) begin - cyc <= 0; - end else begin - cyc <= cyc +1; - end - end + always @(posedge clk) begin + if (rst) begin + cyc <= 0; + end + else begin + cyc <= cyc + 1; + end + end - reg tmp_1; - reg [7:0] tmp_8; + reg tmp_1; + reg [7:0] tmp_8; - always @(posedge clk) begin - if (rst) begin - tmp_1 <= 0; - tmp_8 <= 0; - end else begin - tmp_1 <= cyc[0]; - tmp_8 <= cyc[1 +: 8]; - end - end + always @(posedge clk) begin + if (rst) begin + tmp_1 <= 0; + tmp_8 <= 0; + end + else begin + tmp_1 <= cyc[0]; + tmp_8 <= cyc[1+:8]; + end + end `ifdef CMT - reg var_1 /* verilator forceable */; - reg [7:0] var_8 /* verilator forceable */; + reg var_1 /* verilator forceable */; + reg [7:0] var_8 /* verilator forceable */; `else - reg var_1; - reg [7:0] var_8; + reg var_1; + reg [7:0] var_8; `endif - always @* var_1 = tmp_1; - always @* var_8 = tmp_8; + always @* var_1 = tmp_1; + always @* var_8 = tmp_8; - reg obs_1; - reg [7:0] obs_8; + reg obs_1; + reg [7:0] obs_8; - always @* obs_1 = var_1; - always @* obs_8 = var_8; + always @* obs_1 = var_1; + always @* obs_8 = var_8; - always @ (posedge clk) begin - $display("%d: %x %x", cyc, obs_8, obs_1); + always @(posedge clk) begin + $display("%d: %x %x", cyc, obs_8, obs_1); - if (!rst) begin - case (cyc) - 0: begin // Reset values - `checkh (obs_1, 0); - `checkh (obs_8, 0); - end - 13: begin - `checkh (obs_1, 1); - `checkh ({1'b0, obs_8}, (cyc[0 +: 9] - 1) >> 1); - end - 14: begin - `checkh (obs_1, 1); - `checkh (obs_8, 8'hf5); - end - 15: begin - `checkh (obs_1, 0); - `checkh (obs_8, 8'hf5); - end - 16, 17: begin - `checkh (obs_1, 0); - `checkh (obs_8, 8'h5f); - end - 18: begin - `checkh (obs_1, ~cyc[0]); - `checkh (obs_8, 8'h5f); - end - 20, 21: begin - `checkh (obs_1, 1); - `checkh (obs_8, 8'h5a); - end - 22, 23: begin - `checkh (obs_1, 0); - `checkh (obs_8, 8'ha5); - end - default: begin - `checkh ({obs_8, obs_1}, cyc[0 +: 9] - 1); - end - endcase - end + if (!rst) begin + case (cyc) + 0: begin // Reset values + `checkh(obs_1, 0); + `checkh(obs_8, 0); + end + 13: begin + `checkh(obs_1, 1); + `checkh({1'b0, obs_8}, (cyc[0+:9] - 1) >> 1); + end + 14: begin + `checkh(obs_1, 1); + `checkh(obs_8, 8'hf5); + end + 15: begin + `checkh(obs_1, 0); + `checkh(obs_8, 8'hf5); + end + 16, 17: begin + `checkh(obs_1, 0); + `checkh(obs_8, 8'h5f); + end + 18: begin + `checkh(obs_1, ~cyc[0]); + `checkh(obs_8, 8'h5f); + end + 20, 21: begin + `checkh(obs_1, 1); + `checkh(obs_8, 8'h5a); + end + 22, 23: begin + `checkh(obs_1, 0); + `checkh(obs_8, 8'ha5); + end + default: begin + `checkh({obs_8, obs_1}, cyc[0+:9] - 1); + end + endcase + end - if (cyc == 30) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 30) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index 4020752bc..65b1fd176 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -4,170 +4,168 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - // verilator lint_off ASCRANGE - // verilator lint_off WIDTH + // verilator lint_off ASCRANGE + // verilator lint_off WIDTH - reg [63:0] sum; // Checked not in objects - reg [63:0] add; - reg [2:1] [4:3] array [5:6] [7:8]; - reg [1:2] [3:4] larray [6:5] [8:7]; - bit [31:0] depth1_array [0:0]; - int oned [3:1]; - int twod [3:1][9:8]; - string str1; - string str2; + reg [63:0] sum; // Checked not in objects + reg [63:0] add; + reg [2:1][4:3] array[5:6][7:8]; + reg [1:2][3:4] larray[6:5][8:7]; + bit [31:0] depth1_array[0:0]; + int oned[3:1]; + int twod[3:1][9:8]; + string str1; + string str2; - typedef struct packed { - reg [1:0] [63:0] subarray; - } str_t; - typedef struct packed { - str_t mid; - } mid_t; - mid_t strarray[3]; + typedef struct packed {reg [1:0][63:0] subarray;} str_t; + typedef struct packed {str_t mid;} mid_t; + mid_t strarray[3]; - function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); - crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; - endfunction + function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, + input [31:0] d); + crc = {sum[62:0], sum[63]} ^ {4'b0, a[7:0], 4'h0, b[7:0], 4'h0, c[7:0], 4'h0, d[7:0]}; + endfunction - initial begin - sum = 0; - // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.py to confirm that all loops - // have been unrolled and flattened away and no loop vars - // remain in the generated .cpp - foreach (depth1_array[index_a]) begin - sum = crc(sum, index_a, 0, 0, 0); + initial begin + sum = 0; + // We use 'index_' as the prefix for all loop vars, + // this allows t_foreach.py to confirm that all loops + // have been unrolled and flattened away and no loop vars + // remain in the generated .cpp + foreach (depth1_array[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); - // Ensure the index never goes out of bounds. - // We used to get this wrong for an array of depth 1. - assert (index_a != -1); - assert (index_a != 1); - end - `checkh(sum, 64'h0); + // Ensure the index never goes out of bounds. + // We used to get this wrong for an array of depth 1. + assert (index_a != -1); + assert (index_a != 1); + end + `checkh(sum, 64'h0); - sum = 0; - foreach (array[index_a]) begin - sum = crc(sum, index_a, 0, 0, 0); - end - `checkh(sum, 64'h000000c000000000); + sum = 0; + foreach (array[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); + end + `checkh(sum, 64'h000000c000000000); - sum = 0; - foreach (array[index_a,index_b]) begin - sum = crc(sum, index_a, index_b, 0, 0); - end - `checkh(sum, 64'h000003601e000000); + sum = 0; + foreach (array[index_a, index_b]) begin + sum = crc(sum, index_a, index_b, 0, 0); + end + `checkh(sum, 64'h000003601e000000); - sum = 0; - foreach (array[index_a,index_b,index_c]) begin - sum = crc(sum, index_a, index_b, index_c, 0); - end - `checkh(sum, 64'h00003123fc101000); + sum = 0; + foreach (array[index_a, index_b, index_c]) begin + sum = crc(sum, index_a, index_b, index_c, 0); + end + `checkh(sum, 64'h00003123fc101000); - sum = 0; - foreach (array[index_a,index_b,index_c,index_d]) begin - sum = crc(sum, index_a, index_b, index_c, index_d); - end - `checkh(sum, 64'h0030128ab2a8e557); + sum = 0; + foreach (array[index_a, index_b, index_c, index_d]) begin + sum = crc(sum, index_a, index_b, index_c, index_d); + end + `checkh(sum, 64'h0030128ab2a8e557); - // comma syntax - sum = 0; - foreach (array[,index_b]) begin - $display(index_b); - sum = crc(sum, 0, index_b, 0, 0); - end - `checkh(sum, 64'h0000000006000000); + // comma syntax + sum = 0; + foreach (array[, index_b]) begin + $display(index_b); + sum = crc(sum, 0, index_b, 0, 0); + end + `checkh(sum, 64'h0000000006000000); - // - sum = 0; - foreach (larray[index_a]) begin - sum = crc(sum, index_a, 0, 0, 0); - end - `checkh(sum, 64'h0000009000000000); + // + sum = 0; + foreach (larray[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); + end + `checkh(sum, 64'h0000009000000000); - sum = 0; - foreach (larray[index_a,index_b]) begin - sum = crc(sum, index_a, index_b, 0, 0); - sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; - end - `checkh(sum, 64'h000002704b057073); + sum = 0; + foreach (larray[index_a, index_b]) begin + sum = crc(sum, index_a, index_b, 0, 0); + sum = sum + {4'b0, index_a[7:0], 4'h0, index_b[7:0]}; + end + `checkh(sum, 64'h000002704b057073); - sum = 0; - foreach (larray[index_a,index_b,index_c]) begin - sum = crc(sum, index_a, index_b, index_c, 0); - end - `checkh(sum, 64'h00002136f9000000); + sum = 0; + foreach (larray[index_a, index_b, index_c]) begin + sum = crc(sum, index_a, index_b, index_c, 0); + end + `checkh(sum, 64'h00002136f9000000); - sum = 0; - foreach (larray[index_a,index_b,index_c,index_d]) begin - sum = crc(sum, index_a, index_b, index_c, index_d); - end - `checkh(sum, 64'h0020179aa7aa0aaa); + sum = 0; + foreach (larray[index_a, index_b, index_c, index_d]) begin + sum = crc(sum, index_a, index_b, index_c, index_d); + end + `checkh(sum, 64'h0020179aa7aa0aaa); - add = 0; - strarray[0].mid.subarray[0] = 1; - strarray[0].mid.subarray[1] = 2; - strarray[1].mid.subarray[0] = 4; - strarray[1].mid.subarray[1] = 5; - strarray[2].mid.subarray[0] = 6; - strarray[2].mid.subarray[1] = 7; - foreach (strarray[s]) - foreach (strarray[s].mid.subarray[ss]) - add += strarray[s].mid.subarray[ss]; - `checkh(add, 'h19); + add = 0; + strarray[0].mid.subarray[0] = 1; + strarray[0].mid.subarray[1] = 2; + strarray[1].mid.subarray[0] = 4; + strarray[1].mid.subarray[1] = 5; + strarray[2].mid.subarray[0] = 6; + strarray[2].mid.subarray[1] = 7; + foreach (strarray[s]) + foreach (strarray[s].mid.subarray[ss]) add += strarray[s].mid.subarray[ss]; + `checkh(add, 'h19); - add = 0; - foreach (oned[i]) begin - ++add; - break; - end - `checkh(add, 1); // 9 + add = 0; + foreach (oned[i]) begin + ++add; + break; + end + `checkh(add, 1); // 9 - add = 0; - foreach (oned[i]) begin - ++add; - continue; - add += 100; - end - `checkh(add, 3); // 9, 8, 7 + add = 0; + foreach (oned[i]) begin + ++add; + continue; + add += 100; + end + `checkh(add, 3); // 9, 8, 7 - add = 0; - foreach (twod[i, j]) begin - ++add; - break; - end - // See https://www.accellera.org/images/eda/sv-bc/10303.html - `checkh(add, 1); // 3,9 + add = 0; + foreach (twod[i, j]) begin + ++add; + break; + end + // See https://www.accellera.org/images/eda/sv-bc/10303.html + `checkh(add, 1); // 3,9 - add = 0; - foreach (twod[i, j]) begin - ++add; - continue; - add += 100; - end - `checkh(add, 6); + add = 0; + foreach (twod[i, j]) begin + ++add; + continue; + add += 100; + end + `checkh(add, 6); - foreach (twod[i, j]); // Null body check + foreach (twod[i, j]); // Null body check - str1 = "abcd"; - str2 = "1234"; - foreach (str1[i]) begin - str2[i] = str1[i]; - end - if (str1 != str2) $stop; + str1 = "abcd"; + str2 = "1234"; + foreach (str1[i]) begin + str2[i] = str1[i]; + end + if (str1 != str2) $stop; - str1 = ""; - add = 0; - foreach(str1[i]) begin - add++; - end - `checkh(add, 0); + str1 = ""; + add = 0; + foreach (str1[i]) begin + add++; + end + `checkh(add, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_foreach_array.v b/test_regress/t/t_foreach_array.v index 43e219448..0784d87c0 100644 --- a/test_regress/t/t_foreach_array.v +++ b/test_regress/t/t_foreach_array.v @@ -5,121 +5,121 @@ // SPDX-License-Identifier: CC0-1.0 module t_foreach_array; - // Define various structures to test foreach behavior - int dyn_arr[][]; - int queue[$][$]; - int unpacked_arr [3:1][9:8]; - int associative_array_3d[string][string][string]; + // Define various structures to test foreach behavior + int dyn_arr[][]; + int queue[$][$]; + int unpacked_arr[3:1][9:8]; + int associative_array_3d[string][string][string]; - int queue_unp[$][3]; // Outer dynamic queue with fixed-size inner arrays - int unp_queue[3][$]; // Fixed-size outer array with dynamic inner queues - int dyn_queue[][]; // Fully dynamic 2D array - int queue_dyn[$][]; // Outer dynamic queue with dynamic inner queues - int dyn_unp[][3]; // Dynamic outer array with fixed-size inner arrays - int unp_dyn[3][]; // Fixed-size outer array with dynamic inner arrays + int queue_unp[$][3]; // Outer dynamic queue with fixed-size inner arrays + int unp_queue[3][$]; // Fixed-size outer array with dynamic inner queues + int dyn_queue[][]; // Fully dynamic 2D array + int queue_dyn[$][]; // Outer dynamic queue with dynamic inner queues + int dyn_unp[][3]; // Dynamic outer array with fixed-size inner arrays + int unp_dyn[3][]; // Fixed-size outer array with dynamic inner arrays - // Define counter for various structures of array - int count_que, exp_count_que; - int count_dyn, exp_count_dyn; - int count_unp, exp_count_unp; - int count_assoc; - int count_queue_unp, exp_count_queue_unp; - int count_unp_queue, exp_count_unp_queue; - int count_dyn_queue, exp_count_dyn_queue; - int count_queue_dyn, exp_count_queue_dyn; - int count_dyn_unp, exp_count_dyn_unp; - int count_unp_dyn, exp_count_unp_dyn; + // Define counter for various structures of array + int count_que, exp_count_que; + int count_dyn, exp_count_dyn; + int count_unp, exp_count_unp; + int count_assoc; + int count_queue_unp, exp_count_queue_unp; + int count_unp_queue, exp_count_unp_queue; + int count_dyn_queue, exp_count_dyn_queue; + int count_queue_dyn, exp_count_queue_dyn; + int count_dyn_unp, exp_count_dyn_unp; + int count_unp_dyn, exp_count_unp_dyn; - string k1, k2, k3; + string k1, k2, k3; - initial begin - // Initialize - queue = '{'{1, 2, 3}, '{4, 5}, '{6}}; - dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}}; - associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; - associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; - associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; - associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; - associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; - associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; - associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; - associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; - associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9; + initial begin + // Initialize + queue = '{'{1, 2, 3}, '{4, 5}, '{6}}; + dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}}; + associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; + associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; + associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; + associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; + associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; + associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; + associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; + associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; + associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9; - queue_unp = '{'{1, 2, 3}, '{4, 5, 6}, '{7, 8, 9}}; - unp_queue[0] = '{10, 11}; - unp_queue[1] = '{12, 13, 14}; - unp_queue[2] = '{15}; - dyn_queue = '{'{16, 17}, '{18, 19, 20}}; - queue_dyn = '{'{21, 22}, '{23, 24, 25}}; - dyn_unp = '{'{26, 27, 28}, '{29, 30, 31}}; - unp_dyn[0] = '{32, 33}; - unp_dyn[1] = '{34, 35, 36}; - unp_dyn[2] = '{37}; + queue_unp = '{'{1, 2, 3}, '{4, 5, 6}, '{7, 8, 9}}; + unp_queue[0] = '{10, 11}; + unp_queue[1] = '{12, 13, 14}; + unp_queue[2] = '{15}; + dyn_queue = '{'{16, 17}, '{18, 19, 20}}; + queue_dyn = '{'{21, 22}, '{23, 24, 25}}; + dyn_unp = '{'{26, 27, 28}, '{29, 30, 31}}; + unp_dyn[0] = '{32, 33}; + unp_dyn[1] = '{34, 35, 36}; + unp_dyn[2] = '{37}; - // Perform foreach loop counting and expected value calculation - count_que = 0; - foreach(queue[i, j]) count_que++; - exp_count_que = 0; - foreach(queue[i]) foreach(queue[i][j]) exp_count_que++; + // Perform foreach loop counting and expected value calculation + count_que = 0; + foreach (queue[i, j]) count_que++; + exp_count_que = 0; + foreach (queue[i]) foreach (queue[i][j]) exp_count_que++; - count_dyn = 0; - foreach(dyn_arr[i, j]) count_dyn++; - exp_count_dyn = 0; - foreach(dyn_arr[i]) foreach(dyn_arr[i][j]) exp_count_dyn++; + count_dyn = 0; + foreach (dyn_arr[i, j]) count_dyn++; + exp_count_dyn = 0; + foreach (dyn_arr[i]) foreach (dyn_arr[i][j]) exp_count_dyn++; - count_unp = 0; - foreach(unpacked_arr[i, j]) count_unp++; - exp_count_unp = 0; - foreach(unpacked_arr[i]) foreach(unpacked_arr[i][j]) exp_count_unp++; + count_unp = 0; + foreach (unpacked_arr[i, j]) count_unp++; + exp_count_unp = 0; + foreach (unpacked_arr[i]) foreach (unpacked_arr[i][j]) exp_count_unp++; - count_assoc = 0; - foreach(associative_array_3d[k1, k2, k3]) count_assoc++; + count_assoc = 0; + foreach (associative_array_3d[k1, k2, k3]) count_assoc++; - count_queue_unp = 0; - foreach (queue_unp[i, j]) count_queue_unp++; - exp_count_queue_unp = 0; - foreach (queue_unp[i]) foreach (queue_unp[i][j]) exp_count_queue_unp++; + count_queue_unp = 0; + foreach (queue_unp[i, j]) count_queue_unp++; + exp_count_queue_unp = 0; + foreach (queue_unp[i]) foreach (queue_unp[i][j]) exp_count_queue_unp++; - count_unp_queue = 0; - foreach (unp_queue[i, j]) count_unp_queue++; - exp_count_unp_queue = 0; - foreach (unp_queue[i]) foreach (unp_queue[i][j]) exp_count_unp_queue++; + count_unp_queue = 0; + foreach (unp_queue[i, j]) count_unp_queue++; + exp_count_unp_queue = 0; + foreach (unp_queue[i]) foreach (unp_queue[i][j]) exp_count_unp_queue++; - count_dyn_queue = 0; - foreach (dyn_queue[i, j]) count_dyn_queue++; - exp_count_dyn_queue = 0; - foreach (dyn_queue[i]) foreach (dyn_queue[i][j]) exp_count_dyn_queue++; + count_dyn_queue = 0; + foreach (dyn_queue[i, j]) count_dyn_queue++; + exp_count_dyn_queue = 0; + foreach (dyn_queue[i]) foreach (dyn_queue[i][j]) exp_count_dyn_queue++; - count_queue_dyn = 0; - foreach (queue_dyn[i, j]) count_queue_dyn++; - exp_count_queue_dyn = 0; - foreach (queue_dyn[i]) foreach (queue_dyn[i][j]) exp_count_queue_dyn++; + count_queue_dyn = 0; + foreach (queue_dyn[i, j]) count_queue_dyn++; + exp_count_queue_dyn = 0; + foreach (queue_dyn[i]) foreach (queue_dyn[i][j]) exp_count_queue_dyn++; - count_dyn_unp = 0; - foreach (dyn_unp[i, j]) count_dyn_unp++; - exp_count_dyn_unp = 0; - foreach (dyn_unp[i]) foreach (dyn_unp[i][j]) exp_count_dyn_unp++; + count_dyn_unp = 0; + foreach (dyn_unp[i, j]) count_dyn_unp++; + exp_count_dyn_unp = 0; + foreach (dyn_unp[i]) foreach (dyn_unp[i][j]) exp_count_dyn_unp++; - count_unp_dyn = 0; - foreach (unp_dyn[i, j]) count_unp_dyn++; - exp_count_unp_dyn = 0; - foreach (unp_dyn[i]) foreach (unp_dyn[i][j]) exp_count_unp_dyn++; + count_unp_dyn = 0; + foreach (unp_dyn[i, j]) count_unp_dyn++; + exp_count_unp_dyn = 0; + foreach (unp_dyn[i]) foreach (unp_dyn[i][j]) exp_count_unp_dyn++; - // Verification checks - if (count_que != 6 || count_que != exp_count_que) $stop; - if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop; - if (count_unp != 6 || count_unp != exp_count_unp) $stop; - if (count_assoc != 9) $stop; - if (count_queue_unp != exp_count_queue_unp) $stop; - if (count_unp_queue != exp_count_unp_queue) $stop; - if (count_dyn_queue != exp_count_dyn_queue) $stop; - if (count_queue_dyn != exp_count_queue_dyn) $stop; - if (count_dyn_unp != exp_count_dyn_unp) $stop; - if (count_unp_dyn != exp_count_unp_dyn) $stop; + // Verification checks + if (count_que != 6 || count_que != exp_count_que) $stop; + if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop; + if (count_unp != 6 || count_unp != exp_count_unp) $stop; + if (count_assoc != 9) $stop; + if (count_queue_unp != exp_count_queue_unp) $stop; + if (count_unp_queue != exp_count_unp_queue) $stop; + if (count_dyn_queue != exp_count_dyn_queue) $stop; + if (count_queue_dyn != exp_count_queue_dyn) $stop; + if (count_dyn_unp != exp_count_dyn_unp) $stop; + if (count_unp_dyn != exp_count_unp_dyn) $stop; - $write("*-* All Finished *-*\\n"); - $finish; - end + $write("*-* All Finished *-*\\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_foreach_bad.out b/test_regress/t/t_foreach_bad.out index 9c519fec6..69bdb661c 100644 --- a/test_regress/t/t_foreach_bad.out +++ b/test_regress/t/t_foreach_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_foreach_bad.v:14:7: Foreach missing bracketed loop variable is no-operation (IEEE 1800-2023 12.7.3) - 14 | foreach (array); - | ^~~~~~~ +%Error: t/t_foreach_bad.v:14:5: Foreach missing bracketed loop variable is no-operation (IEEE 1800-2023 12.7.3) + 14 | foreach (array); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_foreach_bad.v:18:23: 'foreach' loop variable expects simple variable name - 18 | foreach (array[a.b]); - | ^ +%Error: t/t_foreach_bad.v:18:21: 'foreach' loop variable expects simple variable name + 18 | foreach (array[a.b]); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_foreach_bad.v b/test_regress/t/t_foreach_bad.v index b2cd9e93e..e1829785b 100644 --- a/test_regress/t/t_foreach_bad.v +++ b/test_regress/t/t_foreach_bad.v @@ -6,19 +6,19 @@ module t; - integer a, b; + integer a, b; - reg [2:0][2:0] array; + reg [2:0][2:0] array; - initial begin - foreach (array); // no index + initial begin + foreach (array); // no index - foreach (array.array[a]); // not supported + foreach (array.array[a]); // not supported - foreach (array[a.b]); // no index + foreach (array[a.b]); // no index - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_foreach_blkname.v b/test_regress/t/t_foreach_blkname.v index 659c41bec..8a0b48c16 100644 --- a/test_regress/t/t_foreach_blkname.v +++ b/test_regress/t/t_foreach_blkname.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - function void func(); - int a[2]; - begin - int t; - end - foreach (a[i]) begin - end - begin - int x; - end - endfunction + function void func(); + int a[2]; + begin + int t; + end + foreach (a[i]) begin + end + begin + int x; + end + endfunction endmodule diff --git a/test_regress/t/t_foreach_class.v b/test_regress/t/t_foreach_class.v index 13f3b61a1..116ef7920 100644 --- a/test_regress/t/t_foreach_class.v +++ b/test_regress/t/t_foreach_class.v @@ -4,44 +4,47 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; - int q[$]; - function new(); - q.push_back(1); - q.push_back(2); - q.push_back(3); - endfunction + int q[$]; + function new(); + q.push_back(1); + q.push_back(2); + q.push_back(3); + endfunction endclass module t; - int two[5:6]; + int two[5:6]; - if (1) begin : named - Cls c; - end + if (1) begin : named + Cls c; + end - function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); - crc = {sum[62:0],sum[63]} ^ {20'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; - endfunction + function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, + input [31:0] d); + crc = {sum[62:0], sum[63]} ^ {20'b0, a[7:0], 4'h0, b[7:0], 4'h0, c[7:0], 4'h0, d[7:0]}; + endfunction - bit [63:0] sum; + bit [63:0] sum; - initial begin - named.c = new; - sum = 0; - foreach (named.c.q[i]) begin - foreach (two[j]) begin - // $display(i, j); - sum = crc(sum, i, named.c.q[i], j, 0); - end + initial begin + named.c = new; + sum = 0; + foreach (named.c.q[i]) begin + foreach (two[j]) begin + // $display(i, j); + sum = crc(sum, i, named.c.q[i], j, 0); end - `checkh(sum, 64'h000000a02d0fc000); + end + `checkh(sum, 64'h000000a02d0fc000); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_foreach_const.v b/test_regress/t/t_foreach_const.v index cd8144c98..48c4030f8 100644 --- a/test_regress/t/t_foreach_const.v +++ b/test_regress/t/t_foreach_const.v @@ -4,209 +4,203 @@ // SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - // verilator lint_off ASCRANGE - // verilator lint_off WIDTH + // verilator lint_off ASCRANGE + // verilator lint_off WIDTH - reg [63:0] sum; // Checked not in objects - reg [63:0] add; - reg [2:1] [4:3] array [5:6] [7:8]; - reg [1:2] [3:4] larray [6:5] [8:7]; - bit [31:0] depth1_array [0:0]; - int oned [3:1]; - int twod [3:1][9:8]; + reg [63:0] sum; // Checked not in objects + reg [63:0] add; + reg [2:1][4:3] array[5:6][7:8]; + reg [1:2][3:4] larray[6:5][8:7]; + bit [31:0] depth1_array[0:0]; + int oned[3:1]; + int twod[3:1][9:8]; - typedef struct packed { - reg [1:0] [63:0] subarray; - } str_t; - typedef struct packed { - str_t mid; - } mid_t; + typedef struct packed {reg [1:0][63:0] subarray;} str_t; + typedef struct packed {str_t mid;} mid_t; - function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); - crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; - endfunction + function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, + input [31:0] d); + crc = {sum[62:0], sum[63]} ^ {4'b0, a[7:0], 4'h0, b[7:0], 4'h0, c[7:0], 4'h0, d[7:0]}; + endfunction - function [63:0] test1; - test1 = 0; - // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.py to confirm that all loops - // have been unrolled and flattened away and no loop vars - // remain in the generated .cpp - foreach (depth1_array[index_a]) begin - test1 = crc(test1, index_a, 0, 0, 0); + function [63:0] test1; + test1 = 0; + // We use 'index_' as the prefix for all loop vars, + // this allows t_foreach.py to confirm that all loops + // have been unrolled and flattened away and no loop vars + // remain in the generated .cpp + foreach (depth1_array[index_a]) begin + test1 = crc(test1, index_a, 0, 0, 0); - // Ensure the index never goes out of bounds. - // We used to get this wrong for an array of depth 1. - if (index_a == -1) return 7; - if (index_a == 1) return 7; - end - endfunction - localparam PAR1 = test1(); + // Ensure the index never goes out of bounds. + // We used to get this wrong for an array of depth 1. + if (index_a == -1) return 7; + if (index_a == 1) return 7; + end + endfunction + localparam PAR1 = test1(); - function [63:0] test2; - test2 = 0; - foreach (array[index_a]) begin - test2 = crc(test2, index_a, 0, 0, 0); - end - endfunction - localparam PAR2 = test2(); + function [63:0] test2; + test2 = 0; + foreach (array[index_a]) begin + test2 = crc(test2, index_a, 0, 0, 0); + end + endfunction + localparam PAR2 = test2(); - function [63:0] test3; - test3 = 0; - foreach (array[index_a,index_b]) begin - test3 = crc(test3, index_a, index_b, 0, 0); - end - endfunction - localparam PAR3 = test3(); + function [63:0] test3; + test3 = 0; + foreach (array[index_a, index_b]) begin + test3 = crc(test3, index_a, index_b, 0, 0); + end + endfunction + localparam PAR3 = test3(); - function [63:0] test4; - test4 = 0; - foreach (array[index_a,index_b,index_c]) begin - test4 = crc(test4, index_a, index_b, index_c, 0); - end - endfunction - localparam PAR4 = test4(); + function [63:0] test4; + test4 = 0; + foreach (array[index_a, index_b, index_c]) begin + test4 = crc(test4, index_a, index_b, index_c, 0); + end + endfunction + localparam PAR4 = test4(); - function [63:0] test5; - test5 = 0; - foreach (array[index_a,index_b,index_c,index_d]) begin - test5 = crc(test5, index_a, index_b, index_c, index_d); - end - endfunction - localparam PAR5 = test5(); + function [63:0] test5; + test5 = 0; + foreach (array[index_a, index_b, index_c, index_d]) begin + test5 = crc(test5, index_a, index_b, index_c, index_d); + end + endfunction + localparam PAR5 = test5(); - function [63:0] test6; - // comma syntax - test6 = 0; - foreach (array[,index_b]) begin - $display(index_b); - test6 = crc(test6, 0, index_b, 0, 0); - end - endfunction - localparam PAR6 = test6(); + function [63:0] test6; + // comma syntax + test6 = 0; + foreach (array[, index_b]) begin + $display(index_b); + test6 = crc(test6, 0, index_b, 0, 0); + end + endfunction + localparam PAR6 = test6(); - function [63:0] test7; - test7 = 0; - foreach (larray[index_a]) begin - test7 = crc(test7, index_a, 0, 0, 0); - end - endfunction - localparam PAR7 = test7(); + function [63:0] test7; + test7 = 0; + foreach (larray[index_a]) begin + test7 = crc(test7, index_a, 0, 0, 0); + end + endfunction + localparam PAR7 = test7(); - function [63:0] test8; - test8 = 0; - foreach (larray[index_a,index_b]) begin - test8 = crc(test8, index_a, index_b, 0, 0); - test8 = test8 + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; - end - endfunction - localparam PAR8 = test8(); + function [63:0] test8; + test8 = 0; + foreach (larray[index_a, index_b]) begin + test8 = crc(test8, index_a, index_b, 0, 0); + test8 = test8 + {4'b0, index_a[7:0], 4'h0, index_b[7:0]}; + end + endfunction + localparam PAR8 = test8(); - function [63:0] test9; - test9 = 0; - foreach (larray[index_a,index_b,index_c]) begin - test9 = crc(test9, index_a, index_b, index_c, 0); - end - endfunction - localparam PAR9 = test9(); + function [63:0] test9; + test9 = 0; + foreach (larray[index_a, index_b, index_c]) begin + test9 = crc(test9, index_a, index_b, index_c, 0); + end + endfunction + localparam PAR9 = test9(); - function [63:0] test10; - test10 = 0; - foreach (larray[index_a,index_b,index_c,index_d]) begin - test10 = crc(test10, index_a, index_b, index_c, index_d); - end - endfunction - localparam PAR10 = test10(); + function [63:0] test10; + test10 = 0; + foreach (larray[index_a, index_b, index_c, index_d]) begin + test10 = crc(test10, index_a, index_b, index_c, index_d); + end + endfunction + localparam PAR10 = test10(); - function [63:0] test11; - automatic mid_t strarray[3]; - strarray = '{ - '{ '{ '{2, 1} } }, - '{ '{ '{5, 4} } }, - '{ '{ '{7, 6} } } - }; - test11 = 0; - foreach (strarray[s]) - foreach (strarray[s].mid.subarray[ss]) - test11 += strarray[s].mid.subarray[ss]; - endfunction - localparam PAR11 = test11(); + function [63:0] test11; + automatic mid_t strarray[3]; + strarray = '{'{'{'{2, 1}}}, '{'{'{5, 4}}}, '{'{'{7, 6}}}}; + test11 = 0; + foreach (strarray[s]) + foreach (strarray[s].mid.subarray[ss]) test11 += strarray[s].mid.subarray[ss]; + endfunction + localparam PAR11 = test11(); - function [63:0] test12; - test12 = 0; - foreach (oned[i]) begin - ++test12; - break; - end - endfunction - localparam PAR12 = test12(); + function [63:0] test12; + test12 = 0; + foreach (oned[i]) begin + ++test12; + break; + end + endfunction + localparam PAR12 = test12(); - function [63:0] test13; - test13 = 0; - foreach (oned[i]) begin - ++test13; - continue; - test13 += 100; - end - endfunction - localparam PAR13 = test13(); + function [63:0] test13; + test13 = 0; + foreach (oned[i]) begin + ++test13; + continue; + test13 += 100; + end + endfunction + localparam PAR13 = test13(); - function [63:0] test14; - test14 = 0; - foreach (twod[i, j]) begin - ++test14; - break; - end - endfunction - localparam PAR14 = test14(); + function [63:0] test14; + test14 = 0; + foreach (twod[i, j]) begin + ++test14; + break; + end + endfunction + localparam PAR14 = test14(); - function [63:0] test15; - test15 = 0; - foreach (twod[i, j]) begin - ++test15; - continue; - test15 += 100; - end + function [63:0] test15; + test15 = 0; + foreach (twod[i, j]) begin + ++test15; + continue; + test15 += 100; + end - foreach (twod[i, j]); // Null body check - endfunction - localparam PAR15 = test15(); + foreach (twod[i, j]); // Null body check + endfunction + localparam PAR15 = test15(); - function automatic [63:0] test16; - string str1 = ""; - test16 = 0; - foreach(str1[i]) begin - test16++; - end - endfunction - localparam PAR16 = test16(); + function automatic [63:0] test16; + string str1 = ""; + test16 = 0; + foreach (str1[i]) begin + test16++; + end + endfunction + localparam PAR16 = test16(); - initial begin - `checkh(PAR1, 64'h0); - `checkh(PAR2, 64'h000000c000000000); - `checkh(PAR3, 64'h000003601e000000); - `checkh(PAR4, 64'h00003123fc101000); - `checkh(PAR5, 64'h0030128ab2a8e557); - `checkh(PAR6, 64'h0000000006000000); - `checkh(PAR7, 64'h0000009000000000); - `checkh(PAR8, 64'h000002704b057073); - `checkh(PAR9, 64'h00002136f9000000); - `checkh(PAR10, 64'h0020179aa7aa0aaa); - `checkh(PAR11, 'h19); + initial begin + `checkh(PAR1, 64'h0); + `checkh(PAR2, 64'h000000c000000000); + `checkh(PAR3, 64'h000003601e000000); + `checkh(PAR4, 64'h00003123fc101000); + `checkh(PAR5, 64'h0030128ab2a8e557); + `checkh(PAR6, 64'h0000000006000000); + `checkh(PAR7, 64'h0000009000000000); + `checkh(PAR8, 64'h000002704b057073); + `checkh(PAR9, 64'h00002136f9000000); + `checkh(PAR10, 64'h0020179aa7aa0aaa); + `checkh(PAR11, 'h19); - `checkh(PAR12, 1); // 9 - `checkh(PAR13, 3); // 9, 8, 7 - // See https://www.accellera.org/images/eda/sv-bc/10303.html - `checkh(PAR14, 1); // 3,9 - `checkh(PAR15, 6); - `checkh(PAR16, 0); + `checkh(PAR12, 1); // 9 + `checkh(PAR13, 3); // 9, 8, 7 + // See https://www.accellera.org/images/eda/sv-bc/10303.html + `checkh(PAR14, 1); // 3,9 + `checkh(PAR15, 6); + `checkh(PAR16, 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_foreach_iface.v b/test_regress/t/t_foreach_iface.v index 7f7146ef2..4a0f33983 100644 --- a/test_regress/t/t_foreach_iface.v +++ b/test_regress/t/t_foreach_iface.v @@ -4,25 +4,29 @@ // SPDX-FileCopyrightText: 2022 Pawel Jewstafjew // SPDX-License-Identifier: CC0-1.0 -interface Iface (input bit [31:0] regs [1]); - initial begin - automatic string instance_path = $sformatf("%m"); - $display("Iface path %s\n", instance_path); - $write("*-* All Finished *-*\n"); - $finish; - end +interface Iface ( + input bit [31:0] regs[1] +); + initial begin + automatic string instance_path = $sformatf("%m"); + $display("Iface path %s\n", instance_path); + $write("*-* All Finished *-*\n"); + $finish; + end - bit [0:0] ppp; - always_comb begin - // Ok: - //for (int index = 1 ; index < 2 ; ++index) begin - foreach (regs[index]) begin - ppp[index] = 1; - end - end + bit [0:0] ppp; + always_comb begin + // Ok: + //for (int index = 1 ; index < 2 ; ++index) begin + foreach (regs[index]) begin + ppp[index] = 1; + end + end endinterface -module top (input bit [31:0] regs [1]); - Iface t1(.regs(regs)); +module top ( + input bit [31:0] regs[1] +); + Iface t1 (.regs(regs)); endmodule diff --git a/test_regress/t/t_foreach_nindex_bad.out b/test_regress/t/t_foreach_nindex_bad.out index 41a402add..cf238b1f3 100644 --- a/test_regress/t/t_foreach_nindex_bad.out +++ b/test_regress/t/t_foreach_nindex_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_foreach_nindex_bad.v:12:34: foreach loop variables exceed number of indices of array +%Error: t/t_foreach_nindex_bad.v:12:32: foreach loop variables exceed number of indices of array : ... note: In instance 't' - 12 | foreach (array[i, j, badk, badl]); - | ^~~~ + 12 | foreach (array[i, j, badk, badl]); + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_foreach_nindex_bad.v b/test_regress/t/t_foreach_nindex_bad.v index ee1a67340..6d0deccb8 100644 --- a/test_regress/t/t_foreach_nindex_bad.v +++ b/test_regress/t/t_foreach_nindex_bad.v @@ -6,12 +6,12 @@ module t; - int array[2][2]; + int array[2][2]; - initial begin - foreach (array[i, j, badk, badl]); // bad + initial begin + foreach (array[i, j, badk, badl]); // bad - $stop; - end + $stop; + end endmodule diff --git a/test_regress/t/t_foreach_type_bad.out b/test_regress/t/t_foreach_type_bad.out index e39352d27..9cee0109c 100644 --- a/test_regress/t/t_foreach_type_bad.out +++ b/test_regress/t/t_foreach_type_bad.out @@ -1,18 +1,18 @@ -%Error: t/t_foreach_type_bad.v:19:18: Illegal 'foreach' loop on CLASSREFDTYPE 'Cls' data type +%Error: t/t_foreach_type_bad.v:19:16: Illegal 'foreach' loop on CLASSREFDTYPE 'Cls' data type : ... note: In instance 't' - 19 | foreach (c[i]); - | ^ + 19 | foreach (c[i]); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_foreach_type_bad.v:21:18: Illegal 'foreach' loop on BASICDTYPE 'real' data type +%Error: t/t_foreach_type_bad.v:21:16: Illegal 'foreach' loop on BASICDTYPE 'real' data type : ... note: In instance 't' - 21 | foreach (r[i]); - | ^ -%Error: t/t_foreach_type_bad.v:23:21: Illegal 'foreach' loop on BASICDTYPE 'bit' data type + 21 | foreach (r[i]); + | ^ +%Error: t/t_foreach_type_bad.v:23:19: Illegal 'foreach' loop on BASICDTYPE 'bit' data type : ... note: In instance 't' - 23 | foreach (b[i, j, k]); - | ^ -%Error: t/t_foreach_type_bad.v:25:18: Illegal 'foreach' loop on BASICDTYPE 'real' data type + 23 | foreach (b[i, j, k]); + | ^ +%Error: t/t_foreach_type_bad.v:25:16: Illegal 'foreach' loop on BASICDTYPE 'real' data type : ... note: In instance 't' - 25 | foreach (r[, i]); - | ^ + 25 | foreach (r[, i]); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_foreach_type_bad.v b/test_regress/t/t_foreach_type_bad.v index 5a5abef15..c1a5bd3f3 100644 --- a/test_regress/t/t_foreach_type_bad.v +++ b/test_regress/t/t_foreach_type_bad.v @@ -9,22 +9,22 @@ endclass module t; - real r; + real r; - bit b[2]; + bit b[2]; - Cls c; + Cls c; - initial begin - foreach (c[i]); // bad type + initial begin + foreach (c[i]); // bad type - foreach (r[i]); // no loop var + foreach (r[i]); // no loop var - foreach (b[i, j, k]); // extra loop var + foreach (b[i, j, k]); // extra loop var - foreach (r[, i]); // no loop var and extra + foreach (r[, i]); // no loop var and extra - $stop; - end + $stop; + end endmodule diff --git a/test_regress/t/t_fork.out b/test_regress/t/t_fork.out index a2e1e97f4..deab2aab9 100644 --- a/test_regress/t/t_fork.out +++ b/test_regress/t/t_fork.out @@ -1,6 +1,6 @@ -%Error-NOTIMING: t/t_fork.v:10:7: Fork statements require --timing +%Error-NOTIMING: t/t_fork.v:10:5: Fork statements require --timing : ... note: In instance 't' - 10 | fork : fblk - | ^~~~ + 10 | fork : fblk + | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_fork.v b/test_regress/t/t_fork.v index 9759c2940..3c18c09ed 100644 --- a/test_regress/t/t_fork.v +++ b/test_regress/t/t_fork.v @@ -6,16 +6,16 @@ module t; - initial begin - fork : fblk - begin - $write("Forked"); - end - begin - $write("*-* All Finished *-*\n"); - $finish; - end - join : fblk - end + initial begin + fork : fblk + begin + $write("Forked"); + end + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join : fblk + end endmodule diff --git a/test_regress/t/t_fork_bbox.v b/test_regress/t/t_fork_bbox.v index 1a9fc9a95..684a89d47 100644 --- a/test_regress/t/t_fork_bbox.v +++ b/test_regress/t/t_fork_bbox.v @@ -6,13 +6,13 @@ module t; - initial begin - fork : fblk - begin - $write("*-* All Finished *-*\n"); - $finish; - end - join : fblk - end + initial begin + fork : fblk + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join : fblk + end endmodule diff --git a/test_regress/t/t_fork_block_item_declaration.v b/test_regress/t/t_fork_block_item_declaration.v index c48501c1d..674d5e4d1 100644 --- a/test_regress/t/t_fork_block_item_declaration.v +++ b/test_regress/t/t_fork_block_item_declaration.v @@ -9,15 +9,15 @@ static int counts[10]; class Foo; static task do_something(); for (int i = 0; i < 10; i++) - frk : fork + frk : + fork int ii = i; #(10 + i) begin $display("i: %d, ii: %d", i, ii); - if (counts[ii]++ != 0) - $stop; + if (counts[ii]++ != 0) $stop; end join_none : frk - #1; + #1; endtask endclass @@ -29,8 +29,7 @@ module t; Foo::do_something(); #20; - if (counts != desired_counts) - $stop; + if (counts != desired_counts) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_fork_finish.v b/test_regress/t/t_fork_finish.v index a8d9172fc..6e769d7bf 100644 --- a/test_regress/t/t_fork_finish.v +++ b/test_regress/t/t_fork_finish.v @@ -9,7 +9,9 @@ module t; forever begin fork begin - assert ($c(1)) begin + assert ($c( + 1 + )) begin $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_fork_func_bad.out b/test_regress/t/t_fork_func_bad.out index 03066dfd1..f58e1fcac 100644 --- a/test_regress/t/t_fork_func_bad.out +++ b/test_regress/t/t_fork_func_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_fork_func_bad.v:11:10: Return isn't legal under fork (IEEE 1800-2023 9.2.3) - 11 | return 0; - | ^~~~~~ +%Error: t/t_fork_func_bad.v:11:7: Return isn't legal under fork (IEEE 1800-2023 9.2.3) + 11 | return 0; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_fork_func_bad.v b/test_regress/t/t_fork_func_bad.v index 9ec53517a..929aeca0f 100644 --- a/test_regress/t/t_fork_func_bad.v +++ b/test_regress/t/t_fork_func_bad.v @@ -6,16 +6,16 @@ module t; - function int f; - fork - return 0; // Illegal 9.3.2 - join_none - endfunction + function int f; + fork + return 0; // Illegal 9.3.2 + join_none + endfunction - int i; + int i; - initial begin - i = f(); - end + initial begin + i = f(); + end endmodule diff --git a/test_regress/t/t_fork_initial.v b/test_regress/t/t_fork_initial.v index e274d7fed..e8ea5b55d 100644 --- a/test_regress/t/t_fork_initial.v +++ b/test_regress/t/t_fork_initial.v @@ -5,14 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial fork - reg i; - i = 1'b1; - begin - #1; - if (i != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial + fork + reg i; + i = 1'b1; + begin + #1; + if (i != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end join endmodule diff --git a/test_regress/t/t_fork_jumpblock.v b/test_regress/t/t_fork_jumpblock.v index f4309f903..537f665b5 100644 --- a/test_regress/t/t_fork_jumpblock.v +++ b/test_regress/t/t_fork_jumpblock.v @@ -5,19 +5,21 @@ // SPDX-License-Identifier: CC0-1.0 class bar; - task foo(logic r); - int a, b; - if (r) return; - fork a = #1 b; join_none - endtask + task foo(logic r); + int a, b; + if (r) return; + fork + a = #1 b; + join_none + endtask endclass module t; - bar b = new; + bar b = new; - initial begin - b.foo(0); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + b.foo(0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_fork_label.v b/test_regress/t/t_fork_label.v index 316ed630d..3a1bdb586 100644 --- a/test_regress/t/t_fork_label.v +++ b/test_regress/t/t_fork_label.v @@ -6,29 +6,30 @@ module t; - initial begin - // Label checks - begin : b1 - end : b1 - // - b2 : begin - end : b2 - // With no statements this is a NOP - fork : f1 - join : f1 - // - f2: fork - join_any : f2 - // - fork - join_none - // With one statement this is supported and optimized to a begin/end - fork : fblk - begin - $write("*-* All Finished *-*\n"); - $finish; - end - join : fblk - end + initial begin + // Label checks + begin : b1 + end : b1 + // + b2 : begin + end : b2 + // With no statements this is a NOP + fork : f1 + join : f1 + // + f2 : + fork + join_any : f2 + // + fork + join_none + // With one statement this is supported and optimized to a begin/end + fork : fblk + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join : fblk + end endmodule diff --git a/test_regress/t/t_fork_none_var.v b/test_regress/t/t_fork_none_var.v index bbf2b5b6c..180fa8b31 100644 --- a/test_regress/t/t_fork_none_var.v +++ b/test_regress/t/t_fork_none_var.v @@ -6,42 +6,42 @@ module t; - logic [3:0] m_mask; + logic [3:0] m_mask; - initial begin - int i; - automatic int n = 4; - m_mask = 0; - fork - begin + initial begin + int i; + automatic int n = 4; + m_mask = 0; + fork + begin + fork + begin fork - begin + begin + for (i = 0; i < n; i++) begin fork - begin - for(i = 0; i < n; i++) begin - fork - automatic int k = i; - begin - // see issue #4493 - $display("[%0t] start %0d", $time, k); - // UVM's arb_sequence_q[is_relevant_entries[k]].wait_for_relevant(); - m_mask[k] = 1; - #1; - end - join_none - wait (m_mask[i]); - end - end - join_any - end + automatic int k = i; + begin + // see issue #4493 + $display("[%0t] start %0d", $time, k); + // UVM's arb_sequence_q[is_relevant_entries[k]].wait_for_relevant(); + m_mask[k] = 1; + #1; + end + join_none + wait (m_mask[i]); + end + end join_any - end - join + end + join_any + end + join - if (m_mask != {4{1'b1}}) $stop; + if (m_mask != {4{1'b1}}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_fork_output_arg.v b/test_regress/t/t_fork_output_arg.v index 892b049f6..fffa1b64d 100644 --- a/test_regress/t/t_fork_output_arg.v +++ b/test_regress/t/t_fork_output_arg.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int x = 100; - task get_x(output int arg); - arg = x; - endtask + int x = 100; + task get_x(output int arg); + arg = x; + endtask endclass task automatic test; - int o; - Cls c = new; - fork - c.get_x(o); - join_any - if (o != 100) $stop; + int o; + Cls c = new; + fork + c.get_x(o); + join_any + if (o != 100) $stop; endtask module t; - initial begin - test(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + test(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_fork_port.v b/test_regress/t/t_fork_port.v index 96d169dfa..edaa24b4b 100644 --- a/test_regress/t/t_fork_port.v +++ b/test_regress/t/t_fork_port.v @@ -5,15 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic x; - sub s(x); - initial #1 x = 1; + logic x; + sub s (x); + initial #1 x = 1; endmodule -module sub(input x); - initial fork begin +module sub ( + input x +); + initial + fork + begin @x; $write("*-* All Finished *-*\n"); $finish; - end join_any + end + join_any endmodule diff --git a/test_regress/t/t_fork_repeat.v b/test_regress/t/t_fork_repeat.v index 6f5fcc46c..fe517752e 100644 --- a/test_regress/t/t_fork_repeat.v +++ b/test_regress/t/t_fork_repeat.v @@ -5,30 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 module t; - bit clk; + bit clk; - // Gen Clock - always #10 - clk = ~clk; + // Gen Clock + always #10 clk = ~clk; - initial begin - fork - begin - forever - @(posedge clk); - end - begin - repeat(10) - @(posedge clk); - end - begin - for(int i=0; i < 6; ++i) - @(posedge clk); - end - join_any + initial begin + fork + begin + forever @(posedge clk); + end + begin + repeat (10) @(posedge clk); + end + begin + for (int i = 0; i < 6; ++i) @(posedge clk); + end + join_any - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_fork_repeat_reset.v b/test_regress/t/t_fork_repeat_reset.v index 28a95c071..f2792f2bf 100644 --- a/test_regress/t/t_fork_repeat_reset.v +++ b/test_regress/t/t_fork_repeat_reset.v @@ -6,55 +6,55 @@ module t; - logic clock; + logic clock; - initial begin - clock = '0; - forever begin - clock = #5ns ~clock; + initial begin + clock = '0; + forever begin + clock = #5ns ~clock; + end + end + + task static has_fork_task(input [31:0] address); + @(posedge clock); + fork + begin + repeat ($urandom_range(9)) @(posedge clock); end - end + join + endtask - task static has_fork_task(input [31:0] address); - @(posedge clock); - fork - begin - repeat($urandom_range(9)) @(posedge clock); - end - join - endtask + // Intentionally created a recursive task chain (that should be unreachable anyway): + // call_task() + // --> (unreachable) --> calls local_sub_task() + // --> calls call_task() + // --> ... + // --> (reachable) --> calls has_fork_task() done. - // Intentionally created a recursive task chain (that should be unreachable anyway): - // call_task() - // --> (unreachable) --> calls local_sub_task() - // --> calls call_task() - // --> ... - // --> (reachable) --> calls has_fork_task() done. + task static call_task(input [31:0] address); + if (1) begin + // Workaround1: Comment this out to pass the compile. + has_fork_task(address); + end + else begin + // Workaround2: Comment this out to pass the compile + // Should be unreachable anyway. + local_sub_task(.address(address)); + end + endtask - task static call_task(input [31:0] address); - if (1) begin - // Workaround1: Comment this out to pass the compile. - has_fork_task(address); - end - else begin - // Workaround2: Comment this out to pass the compile - // Should be unreachable anyway. - local_sub_task(.address(address)); - end - endtask + task static local_sub_task(input [31:0] address); + logic [63:0] req; + logic [39:0] resp; + req = '0; + call_task(.address(32'h0000_1234)); + resp = '0; + endtask - task static local_sub_task(input [31:0] address); - logic [63:0] req; - logic [39:0] resp; - req = '0; - call_task(.address(32'h0000_1234)); - resp = '0; - endtask - - initial begin : main - #100ns; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin : main + #100ns; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index 1421c5ef1..1e068aa03 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -5,167 +5,165 @@ // SPDX-License-Identifier: CC0-1.0 module t; - reg [2:0] value; - reg [31:0] rglobal; - reg [31:0] vec [1:0]; - reg [31:0] n; - int abcd; + reg [2:0] value; + reg [31:0] rglobal; + reg [31:0] vec[1:0]; + reg [31:0] n; + int abcd; - initial begin - rglobal = 1; - value = 2; - if (add(value) != 3'd3) $stop; - if (rglobal != 2) $stop; - if (add(add(3'd1)) != 3'd3) $stop; - if (rglobal != 4) $stop; - if (munge4(4'b0010) != 4'b1011) $stop; - if (toint(2) != 3) $stop; - if (rglobal != 5) $stop; - setit; - incr(rglobal,rglobal,32'h10); - if (rglobal != 32'h17) $stop; - nop(32'h11); - empty; - empty(); + initial begin + rglobal = 1; + value = 2; + if (add(value) != 3'd3) $stop; + if (rglobal != 2) $stop; + if (add(add(3'd1)) != 3'd3) $stop; + if (rglobal != 4) $stop; + if (munge4(4'b0010) != 4'b1011) $stop; + if (toint(2) != 3) $stop; + if (rglobal != 5) $stop; + setit; + incr(rglobal, rglobal, 32'h10); + if (rglobal != 32'h17) $stop; + nop(32'h11); + empty; + empty(); - rglobal = 32'h00000001; - flipupperbit(rglobal,4'd4); - flipupperbit(rglobal,4'd12); - if (rglobal !== 32'h10100001) $stop; + rglobal = 32'h00000001; + flipupperbit(rglobal, 4'd4); + flipupperbit(rglobal, 4'd12); + if (rglobal !== 32'h10100001) $stop; - if (nil_func(32'h12,32'h12) != 32'h24) $stop; - nil_task(32'h012,32'h112,rglobal); - if (rglobal !== 32'h124) $stop; + if (nil_func(32'h12, 32'h12) != 32'h24) $stop; + nil_task(32'h012, 32'h112, rglobal); + if (rglobal !== 32'h124) $stop; - vec[0] = 32'h333; - vec[1] = 32'habc; - incr(vec[1],vec[0],vec[1]); - if (vec[0] != 32'h333) $stop; - if (vec[1] != 32'hdef) $stop; + vec[0] = 32'h333; + vec[1] = 32'habc; + incr(vec[1], vec[0], vec[1]); + if (vec[0] != 32'h333) $stop; + if (vec[1] != 32'hdef) $stop; - // verilator lint_off SELRANGE - incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector! - // verilator lint_on SELRANGE + // verilator lint_off SELRANGE + incr(vec[2], vec[0], vec[2]); // Reading/Writing past end of vector! + // verilator lint_on SELRANGE - n=1; - nil(); - if (n !== 10) $stop; + n = 1; + nil(); + if (n !== 10) $stop; - // Functions called as tasks - // verilator lint_off IGNOREDRETURN - rglobal = 32'h4; - if (inc_and_return(32'h2) != 32'h6) $stop; - if (rglobal !== 32'h6) $stop; - rglobal = 32'h6; + // Functions called as tasks + // verilator lint_off IGNOREDRETURN + rglobal = 32'h4; + if (inc_and_return(32'h2) != 32'h6) $stop; + if (rglobal !== 32'h6) $stop; + rglobal = 32'h6; - inc_and_return(32'h3); - if (rglobal !== 32'h9) $stop; - // verilator lint_on IGNOREDRETURN + inc_and_return(32'h3); + if (rglobal !== 32'h9) $stop; + // verilator lint_on IGNOREDRETURN - abcd = 0; - set_1_to_abcd; - if (abcd != 1) $stop; - set_2_to_abcd; - if (abcd != 2) $stop; + abcd = 0; + set_1_to_abcd; + if (abcd != 1) $stop; + set_2_to_abcd; + if (abcd != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end - function [2:0] add; - input [2:0] fromv; - begin - add = fromv + 3'd1; - begin : named - reg [31:0] flocal; - flocal = 1; - rglobal = rglobal + flocal; - end : named // SystemVerilog end labels - end - endfunction - - function [3:0] munge4; - input [3:0] fromv; // Different fromv than the 'fromv' signal above - reg one; + function [2:0] add; + input [2:0] fromv; + begin + add = fromv + 3'd1; begin : named - reg [1:0] flocal; - // Function calling a function - one = 1'b1; - munge4 = {one, add(fromv[2:0])}; - end - endfunction + reg [31:0] flocal; + flocal = 1; + rglobal = rglobal + flocal; + end : named // SystemVerilog end labels + end + endfunction - task setit; - reg [31:0] temp; - begin - temp = rglobal + 32'h1; - rglobal = temp + 32'h1; - end - endtask + function [3:0] munge4; + input [3:0] fromv; // Different fromv than the 'fromv' signal above + reg one; + begin : named + reg [1:0] flocal; + // Function calling a function + one = 1'b1; + munge4 = {one, add(fromv[2:0])}; + end + endfunction - task incr ( - // Check a V2K style input/output list - output [31:0] z, - input [31:0] a, inc - ); - z = a + inc; - endtask + task setit; + reg [31:0] temp; + begin + temp = rglobal + 32'h1; + rglobal = temp + 32'h1; + end + endtask - task nop; - input [31:0] a; - begin - end - endtask + task incr( + // Check a V2K style input/output list + output [31:0] z, input [31:0] a, inc); + z = a + inc; + endtask - task empty; - endtask + task nop; + input [31:0] a; + begin + end + endtask - task flipupperbit; - inout [31:0] vector; - input [3:0] bitnum; - reg [4:0] bitnum2; - begin - bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation - vector[bitnum2] = vector[bitnum2] ^ 1'b1; - end - endtask + task empty; + endtask - task nil_task; - input [31:0] a; - input [31:0] b; - output [31:0] q; - // verilator no_inline_task - q = nil_func(a, b); - endtask + task flipupperbit; + inout [31:0] vector; + input [3:0] bitnum; + reg [4:0] bitnum2; + begin + bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation + vector[bitnum2] = vector[bitnum2] ^ 1'b1; + end + endtask - function void nil; - n = 10; - endfunction + task nil_task; + input [31:0] a; + input [31:0] b; + output [31:0] q; + // verilator no_inline_task + q = nil_func(a, b); + endtask - function [31:0] nil_func; - input [31:0] fa; - input [31:0] fb; - // verilator no_inline_task - nil_func = fa + fb; - endfunction + function void nil; + n = 10; + endfunction - function integer toint; - input integer fa; - toint = fa + 32'h1; - endfunction + function [31:0] nil_func; + input [31:0] fa; + input [31:0] fb; + // verilator no_inline_task + nil_func = fa + fb; + endfunction - function [31:0] inc_and_return; - input [31:0] inc; - rglobal = rglobal + inc; - return rglobal; - endfunction + function integer toint; + input integer fa; + toint = fa + 32'h1; + endfunction - function void set_1_to_abcd; - abcd = 1; - endfunction + function [31:0] inc_and_return; + input [31:0] inc; + rglobal = rglobal + inc; + return rglobal; + endfunction - task set_2_to_abcd; - abcd = 2; - endtask + function void set_1_to_abcd; + abcd = 1; + endfunction + + task set_2_to_abcd; + abcd = 2; + endtask endmodule diff --git a/test_regress/t/t_func_arg_complex.v b/test_regress/t/t_func_arg_complex.v index 7f44912ec..816166d96 100644 --- a/test_regress/t/t_func_arg_complex.v +++ b/test_regress/t/t_func_arg_complex.v @@ -5,103 +5,106 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; - enum { ONEK = 1000, TWOK = 2000 } sev_t; - int m_default_data; - function int trigger(int data=get_default_data()); - return data; - endfunction + enum { + ONEK = 1000, + TWOK = 2000 + } sev_t; + int m_default_data; + function int trigger(int data = get_default_data()); + return data; + endfunction - task triggert(output int o, input int data=get_default_data()); - o = data; - endtask + task triggert(output int o, input int data = get_default_data()); + o = data; + endtask - virtual function int get_default_data(); - return m_default_data; - endfunction + virtual function int get_default_data(); + return m_default_data; + endfunction - function int uvm_report(int severity, - int verbosity = (severity == 1) ? ONEK : TWOK); - return verbosity; - endfunction + function int uvm_report(int severity, int verbosity = (severity == 1) ? ONEK : TWOK); + return verbosity; + endfunction endclass module t; - function int mod_trigger(int data=mod_data()); - return data; - endfunction + function int mod_trigger(int data = mod_data()); + return data; + endfunction - task mod_triggert(output int o, input int data=mod_data()); - o = data; - endtask + task mod_triggert(output int o, input int data = mod_data()); + o = data; + endtask - int mod_default_data; - function int mod_data(); - return mod_default_data; - endfunction + int mod_default_data; + function int mod_data(); + return mod_default_data; + endfunction - int v; + int v; - initial begin - begin - mod_triggert(v, 1234); - `checkd(v, 1234); + initial begin + begin + mod_triggert(v, 1234); + `checkd(v, 1234); - mod_default_data = 42; - v = mod_trigger(); - `checkd(v, 42); - v = mod_trigger(11); - `checkd(v, 11); - mod_default_data = 43; - v = mod_trigger(); - `checkd(v, 43); - v = mod_trigger(); // Multiple to test look up of duplicates - `checkd(v, 43); + mod_default_data = 42; + v = mod_trigger(); + `checkd(v, 42); + v = mod_trigger(11); + `checkd(v, 11); + mod_default_data = 43; + v = mod_trigger(); + `checkd(v, 43); + v = mod_trigger(); // Multiple to test look up of duplicates + `checkd(v, 43); - mod_default_data = 52; - mod_triggert(v); - `checkd(v, 52); - mod_triggert(v); // Multiple to test look up of duplicates - `checkd(v, 52); - end - begin - Cls c = new; + mod_default_data = 52; + mod_triggert(v); + `checkd(v, 52); + mod_triggert(v); // Multiple to test look up of duplicates + `checkd(v, 52); + end + begin + Cls c = new; - c.m_default_data = 42; - v = c.trigger(); - `checkd(v, 42); - v = c.trigger(11); - `checkd(v, 11); - c.m_default_data = 43; - v = c.trigger(); - `checkd(v, 43); - v = c.trigger(); // Multiple to test look up of duplicates - `checkd(v, 43); - v = c.trigger(); // Multiple to test look up of duplicates - `checkd(v, 43); + c.m_default_data = 42; + v = c.trigger(); + `checkd(v, 42); + v = c.trigger(11); + `checkd(v, 11); + c.m_default_data = 43; + v = c.trigger(); + `checkd(v, 43); + v = c.trigger(); // Multiple to test look up of duplicates + `checkd(v, 43); + v = c.trigger(); // Multiple to test look up of duplicates + `checkd(v, 43); - c.m_default_data = 52; - c.triggert(v); - `checkd(v, 52); - c.triggert(v); // Multiple to test look up of duplicates - `checkd(v, 52); + c.m_default_data = 52; + c.triggert(v); + `checkd(v, 52); + c.triggert(v); // Multiple to test look up of duplicates + `checkd(v, 52); - v = c.uvm_report(1); - `checkd(v, 1000); - v = c.uvm_report(2); - `checkd(v, 2000); - v = c.uvm_report(1, 111); - `checkd(v, 111); - v = c.uvm_report(1, 222); - `checkd(v, 222); - end + v = c.uvm_report(1); + `checkd(v, 1000); + v = c.uvm_report(2); + `checkd(v, 2000); + v = c.uvm_report(1, 111); + `checkd(v, 111); + v = c.uvm_report(1, 222); + `checkd(v, 222); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_automatic_clear.v b/test_regress/t/t_func_automatic_clear.v index 1e1f41928..3614d9000 100644 --- a/test_regress/t/t_func_automatic_clear.v +++ b/test_regress/t/t_func_automatic_clear.v @@ -14,151 +14,149 @@ // allocated when entering the function. module t; - function automatic int ts_queue(); - static int qs[$]; - qs.push_back(0); - // $display(" qs: %p", qs); - return qs.size(); - endfunction + function automatic int ts_queue(); + static int qs[$]; + qs.push_back(0); + // $display(" qs: %p", qs); + return qs.size(); + endfunction - function automatic int t_queue(); - int q[$]; - q.push_back(0); - // $display(" q: %p", q); - return q.size(); - endfunction + function automatic int t_queue(); + int q[$]; + q.push_back(0); + // $display(" q: %p", q); + return q.size(); + endfunction - function automatic int t_scalar(); - int x; - ++x; - return x; - endfunction + function automatic int t_scalar(); + int x; + ++x; + return x; + endfunction - typedef struct { - int y; - } y_t; + typedef struct {int y;} y_t; - function automatic int t_struct(); - y_t y; - ++y.y; - return y.y; - endfunction + function automatic int t_struct(); + y_t y; + ++y.y; + return y.y; + endfunction - function automatic string t_string(); - string x; - x = {x, "s"}; - return x; - endfunction + function automatic string t_string(); + string x; + x = {x, "s"}; + return x; + endfunction -class ClsZ; - int z; -endclass + class ClsZ; + int z; + endclass - function automatic int t_class(); - ClsZ z = new(); - ++z.z; - return z.z; - endfunction + function automatic int t_class(); + ClsZ z = new(); + ++z.z; + return z.z; + endfunction - typedef string dyn_t[]; - function automatic dyn_t t_dyn(); - dyn_t x; - x = {x, "s"}; - return x; - endfunction + typedef string dyn_t[]; + function automatic dyn_t t_dyn(); + dyn_t x; + x = {x, "s"}; + return x; + endfunction - typedef string assoc_t[int]; - function automatic assoc_t t_assoc(); - static int ins = 0; - assoc_t x; - ins = ins + 1; - x[ins] = "s"; - return x; - endfunction + typedef string assoc_t[int]; + function automatic assoc_t t_assoc(); + static int ins = 0; + assoc_t x; + ins = ins + 1; + x[ins] = "s"; + return x; + endfunction - typedef string wild_t[*]; - function automatic wild_t t_wild(); - static int ins = 0; - wild_t x; - ins = ins + 1; - x[ins] = "s"; - return x; - endfunction + typedef string wild_t [*]; + function automatic wild_t t_wild(); + static int ins = 0; + wild_t x; + ins = ins + 1; + x[ins] = "s"; + return x; + endfunction - typedef int unpack_t[8]; - function automatic unpack_t t_unpack(); - static int ins = 0; - unpack_t x; - ins = ins + 1; - x[ins] = ins; - return x; - endfunction + typedef int unpack_t[8]; + function automatic unpack_t t_unpack(); + static int ins = 0; + unpack_t x; + ins = ins + 1; + x[ins] = ins; + return x; + endfunction - // ======================= + // ======================= - function automatic void main(); - for (int i = 0; i < 3; ++i) begin - int qn = ts_queue(); - int qo = ts_queue(); - `checkh(qn, i * 2 + 1); - `checkh(qo, i * 2 + 2); + function automatic void main(); + for (int i = 0; i < 3; ++i) begin + int qn = ts_queue(); + int qo = ts_queue(); + `checkh(qn, i * 2 + 1); + `checkh(qo, i * 2 + 2); + end + + for (int i = 0; i < 3; ++i) begin + int qn = t_queue(); + `checkh(qn, 1); + end + + for (int i = 0; i < 3; ++i) begin + int x = t_scalar(); + `checkh(x, 1); + end + + for (int i = 0; i < 3; ++i) begin + int y = t_struct(); + `checkh(y, 1); + end + + for (int i = 0; i < 3; ++i) begin + int z = t_class(); + `checkh(z, 1); + end + + for (int i = 0; i < 3; ++i) begin + string z = t_string(); + `checks(z, "s"); + end + + for (int i = 0; i < 3; ++i) begin + dyn_t z = t_dyn(); + `checkh(z.size(), 1); + end + + for (int i = 0; i < 3; ++i) begin + assoc_t z = t_assoc(); + `checkh(z.size(), 1); + end + + for (int i = 0; i < 3; ++i) begin + wild_t z = t_wild(); + `checkh(z.size(), 1); + end + + for (int i = 0; i < 3; ++i) begin + int cnt; + unpack_t z = t_unpack(); + cnt = 0; + for (int j = 0; j < $high(z); ++j) begin + if (z[j] != 0) cnt = cnt + 1; end + `checkh(cnt, 1); + end - for (int i = 0; i < 3; ++i) begin - int qn = t_queue(); - `checkh(qn, 1); - end + endfunction - for (int i = 0; i < 3; ++i) begin - int x = t_scalar(); - `checkh(x, 1); - end - - for (int i = 0; i < 3; ++i) begin - int y = t_struct(); - `checkh(y, 1); - end - - for (int i = 0; i < 3; ++i) begin - int z = t_class(); - `checkh(z, 1); - end - - for (int i = 0; i < 3; ++i) begin - string z = t_string(); - `checks(z, "s"); - end - - for (int i = 0; i < 3; ++i) begin - dyn_t z = t_dyn(); - `checkh(z.size(), 1); - end - - for (int i = 0; i < 3; ++i) begin - assoc_t z = t_assoc(); - `checkh(z.size(), 1); - end - - for (int i = 0; i < 3; ++i) begin - wild_t z = t_wild(); - `checkh(z.size(), 1); - end - - for (int i = 0; i < 3; ++i) begin - int cnt; - unpack_t z = t_unpack(); - cnt = 0; - for (int j = 0; j < $high(z); ++j) begin - if (z[j] != 0) cnt = cnt + 1; - end - `checkh(cnt, 1); - end - - endfunction - - initial begin - main(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + main(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_bad.out b/test_regress/t/t_func_bad.out index 2f8b13abc..61639d5ab 100644 --- a/test_regress/t/t_func_bad.out +++ b/test_regress/t/t_func_bad.out @@ -1,41 +1,41 @@ -%Error: t/t_func_bad.v:9:11: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' - : ... note: In instance 't' - 9 | if (add(3'd1) != 0) $stop; - | ^~~ +%Error: t/t_func_bad.v:9:9: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' + : ... note: In instance 't' + 9 | if (add(3'd1) != 0) $stop; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_func_bad.v:10:27: Too many arguments in call to function 'add' +%Error: t/t_func_bad.v:10:25: Too many arguments in call to function 'add' : ... note: In instance 't' - 10 | if (add(3'd1, 3'd2, 3'd3) != 0) $stop; - | ^~~ - : ... Location of function 'add' declaration: - 19 | function [2:0] add; - | ^~~ -%Error: t/t_func_bad.v:11:7: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' + 10 | if (add(3'd1, 3'd2, 3'd3) != 0) $stop; + | ^~~ + : ... Location of function 'add' declaration: + 19 | function [2:0] add; + | ^~~ +%Error: t/t_func_bad.v:11:5: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' : ... note: In instance 't' - 11 | x; - | ^ -%Warning-WIDTHTRUNC: t/t_func_bad.v:11:7: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. + 11 | x; + | ^ +%Warning-WIDTHTRUNC: t/t_func_bad.v:11:5: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. : ... note: In instance 't' - 11 | x; - | ^ + 11 | x; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_func_bad.v:14:17: No such argument 'no_such' in call to function 'f' +%Error: t/t_func_bad.v:14:15: No such argument 'no_such' in call to function 'f' : ... note: In instance 't' - 14 | f(.j(1), .no_such(2)); - | ^ + 14 | f(.j(1), .no_such(2)); + | ^ : ... Location of function 'f' declaration - 37 | function automatic int f( int j = 1, int dup = 0 ); - | ^ -%Error: t/t_func_bad.v:15:19: Duplicate argument 'dup' in function call to FUNC 'f' + 38 | function automatic int f(int j = 1, int dup = 0); + | ^ +%Error: t/t_func_bad.v:15:17: Duplicate argument 'dup' in function call to FUNC 'f' : ... note: In instance 't' - 15 | f(.dup(1), .dup(3)); - | ^~~ + 15 | f(.dup(1), .dup(3)); + | ^~~ %Error: t/t_func_bad.v:16:13: Too many arguments in call to function 'f' : ... note: In instance 't' - 16 | f(1,2,3); - | ^ + 16 | f(1, 2, 3); + | ^ : ... Location of function 'f' declaration: - 37 | function automatic int f( int j = 1, int dup = 0 ); - | ^ + 38 | function automatic int f(int j = 1, int dup = 0); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad.v b/test_regress/t/t_func_bad.v index 6e546f489..1eae117fc 100644 --- a/test_regress/t/t_func_bad.v +++ b/test_regress/t/t_func_bad.v @@ -5,37 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - if (add(3'd1) != 0) $stop; // Too few args - if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args - x; // Too few args - if (hasout(3'd1) != 0) $stop; // outputs - // - f(.j(1), .no_such(2)); // Name mismatch - f(.dup(1), .dup(3)); // Duplicate - f(1,2,3); // Too many - end + initial begin + if (add(3'd1) != 0) $stop; // Too few args + if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args + x; // Too few args + if (hasout(3'd1) != 0) $stop; // outputs + // + f(.j(1), .no_such(2)); // Name mismatch + f(.dup(1), .dup(3)); // Duplicate + f(1, 2, 3); // Too many + end - function [2:0] add; - input [2:0] from1; - input [2:0] from2; - begin - add = from1 + from2; - end - endfunction + function [2:0] add; + input [2:0] from1; + input [2:0] from2; + begin + add = from1 + from2; + end + endfunction - task x; - output y; - begin end - endtask + task x; + output y; + begin + end + endtask - function hasout; - output [2:0] illegal_output; - hasout = 0; - endfunction + function hasout; + output [2:0] illegal_output; + hasout = 0; + endfunction - function automatic int f( int j = 1, int dup = 0 ); - return (j<<16) | dup; - endfunction + function automatic int f(int j = 1, int dup = 0); + return (j << 16) | dup; + endfunction endmodule diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index a5d0a836d..1563d0ccc 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -1,13 +1,13 @@ -%Warning-WIDTHEXPAND: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. +%Warning-WIDTHEXPAND: t/t_func_bad_width.v:13:11: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. : ... note: In instance 't' - 13 | out = MUX (in); - | ^~~ + 13 | out = MUX(in); + | ^~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. - : ... note: In instance 't' - 13 | out = MUX (in); - | ^ +%Warning-WIDTHTRUNC: t/t_func_bad_width.v:13:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. + : ... note: In instance 't' + 13 | out = MUX(in); + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_bad_width.v b/test_regress/t/t_func_bad_width.v index 490b56341..3dfc0eb99 100644 --- a/test_regress/t/t_func_bad_width.v +++ b/test_regress/t/t_func_bad_width.v @@ -6,18 +6,18 @@ module t; - reg [3:0] out; - reg [38:0] in; - initial begin - in = 39'h0; - out = MUX (in); - $write("bad widths %x", out); - end + reg [3:0] out; + reg [38:0] in; + initial begin + in = 39'h0; + out = MUX(in); + $write("bad widths %x", out); + end - function [31:0] MUX; - input [39:0] XX ; - begin - MUX = XX[39:8]; - end - endfunction + function [31:0] MUX; + input [39:0] XX; + begin + MUX = XX[39:8]; + end + endfunction endmodule diff --git a/test_regress/t/t_func_begin2.v b/test_regress/t/t_func_begin2.v index 38d0a1283..b477559a8 100644 --- a/test_regress/t/t_func_begin2.v +++ b/test_regress/t/t_func_begin2.v @@ -4,26 +4,27 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module init; - task t1; - reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; - reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; - reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; - begin : READER - $display ("Time: %0t Instance: %m", $time); - end - endtask + task t1; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; + reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; + begin : READER + $display ("Time: %0t Instance: %m", $time); + end + endtask - task t2; - reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; - begin : READER - $display ("Time: %0t Instance: %m", $time); - end - endtask + task t2; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + begin : READER + $display ("Time: %0t Instance: %m", $time); + end + endtask endmodule module test(); - init u_ram1(); - init u_ram2(); + init u_ram1(); + init u_ram2(); endmodule diff --git a/test_regress/t/t_func_call_order.v b/test_regress/t/t_func_call_order.v index 8df21f945..c3e633a1e 100644 --- a/test_regress/t/t_func_call_order.v +++ b/test_regress/t/t_func_call_order.v @@ -4,40 +4,44 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int a; - function int assign5; - a = 5; - return 5; - endfunction - function int assign3; - a = 3; - return 3; - endfunction - function int incr; - a++; - return a; - endfunction - function int assign5_return_arg(int x); - a = 5; - return x; - endfunction - int i; + int a; + function int assign5; + a = 5; + return 5; + endfunction + function int assign3; + a = 3; + return 3; + endfunction + function int incr; + a++; + return a; + endfunction + function int assign5_return_arg(int x); + a = 5; + return x; + endfunction + int i; - initial begin - a = 1; - i = assign5() + assign3() + incr(); - `checkd(a, 4); `checkd(i, 12); + initial begin + a = 1; + i = assign5() + assign3() + incr(); + `checkd(a, 4); + `checkd(i, 12); - a = 1; - i = assign5_return_arg(assign3()+incr()); - `checkd(a, 5); `checkd(i, 7); + a = 1; + i = assign5_return_arg(assign3() + incr()); + `checkd(a, 5); + `checkd(i, 7); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v index e593e39e0..7fd918efd 100644 --- a/test_regress/t/t_func_check.v +++ b/test_regress/t/t_func_check.v @@ -7,73 +7,79 @@ // verilator lint_off VARHIDDEN module t ( - clk - ); - input clk; - integer cyc = 0; - reg [63:0] crc; initial crc = 64'h1; + clk +); + input clk; + integer cyc = 0; + reg [63:0] crc; + initial crc = 64'h1; - chk chk (.clk (clk), - .rst_l (1'b1), - .expr (|crc) - ); + chk chk ( + .clk(clk), + .rst_l(1'b1), + .expr(|crc) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module chk (input clk, input rst_l, input expr); +module chk ( + input clk, + input rst_l, + input expr +); - int errors; + int errors; - task printerr; - input [8*64:1] msg; - begin - errors = errors + 1; - $write("%%Error: %0s\n", msg); - $stop; + task printerr; + input [8*64:1] msg; + begin + errors = errors + 1; + $write("%%Error: %0s\n", msg); + $stop; + end + endtask + + always @(posedge clk) begin + if (rst_l) begin + if (expr == 1'b0) begin + printerr("expr not asserted"); end - endtask + end + end - always @(posedge clk) begin - if (rst_l) begin - if (expr == 1'b0) begin - printerr("expr not asserted"); - end - end - end + wire noxs = ((expr ^ expr) == 1'b0); - wire noxs = ((expr ^ expr) == 1'b0); + // TODO: this test is dodgy, noxs can be proven constant, so this block + // should never relly trigger... + reg hasx; + always @(noxs) begin + if (noxs) begin + hasx = 1'b0; + end + else begin + hasx = 1'b1; + end + end - // TODO: this test is dodgy, noxs can be proven constant, so this block - // should never relly trigger... - reg hasx; - always @ (noxs) begin - if (noxs) begin - hasx = 1'b0; + always @(posedge clk) begin + if (rst_l) begin + if (hasx) begin + printerr("expr has unknowns"); end - else begin - hasx = 1'b1; - end - end - - always @(posedge clk) begin - if (rst_l) begin - if (hasx) begin - printerr("expr has unknowns"); - end - end - end + end + end endmodule diff --git a/test_regress/t/t_func_complex.v b/test_regress/t/t_func_complex.v index 561717d29..39d7767f5 100644 --- a/test_regress/t/t_func_complex.v +++ b/test_regress/t/t_func_complex.v @@ -5,71 +5,71 @@ // SPDX-License-Identifier: CC0-1.0 module t; - typedef integer q_t[$]; + typedef integer q_t[$]; - function void queue_set(ref q_t q); + function void queue_set(ref q_t q); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - q.push_back(42); - if (q.size() != 1) $stop; - endfunction + q.push_back(42); + if (q.size() != 1) $stop; + endfunction - // verilator lint_off NORETURN - function int get_noreturn(); + // verilator lint_off NORETURN + function int get_noreturn(); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - endfunction - // verilator lint_on NORETURN + endfunction + // verilator lint_on NORETURN - function int get_uninit(); + function int get_uninit(); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - int uninit; - return get_uninit; - endfunction + int uninit; + return get_uninit; + endfunction - function void queue_check_nref(q_t q); + function void queue_check_nref(q_t q); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - q[0] = 11; - if (q[0] != 11) $stop; - endfunction + q[0] = 11; + if (q[0] != 11) $stop; + endfunction - function void queue_check_ref(const ref q_t q); + function void queue_check_ref(const ref q_t q); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - if (q[0] != 42) $stop; - endfunction + if (q[0] != 42) $stop; + endfunction - function q_t queue_ret(); + function q_t queue_ret(); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - queue_ret = '{101}; - endfunction + queue_ret = '{101}; + endfunction - initial begin - q_t iq; - queue_set(iq); - if (iq.size() != 1) $stop; - queue_check_ref(iq); + initial begin + q_t iq; + queue_set(iq); + if (iq.size() != 1) $stop; + queue_check_ref(iq); - iq[0] = 44; - queue_check_nref(iq); - if (iq[0] != 44) $stop; + iq[0] = 44; + queue_check_nref(iq); + if (iq[0] != 44) $stop; - iq = queue_ret(); - if (iq[0] != 101) $stop; + iq = queue_ret(); + if (iq[0] != 101) $stop; - if (get_noreturn() != 0) $stop; - if (get_uninit() != 0) $stop; + if (get_noreturn() != 0) $stop; + if (get_uninit() != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_const.v b/test_regress/t/t_func_const.v index 8ce636ef2..0156421be 100644 --- a/test_regress/t/t_func_const.v +++ b/test_regress/t/t_func_const.v @@ -5,135 +5,136 @@ // SPDX-License-Identifier: CC0-1.0 package testpackage; - localparam PARAM = 1024 >> 3; + localparam PARAM = 1024 >> 3; endpackage import testpackage::*; module t; - localparam P4 = f_add(P3,1); - localparam P8 = f_add2(P3,P3,f_add(1,1)); - localparam P5 = f_while(7); - localparam P16 = f_for(P4); - localparam P18 = f_case(P4); - localparam P6 = f_return(P4); - localparam P3 = 3; - localparam P128 = f_package(); - localparam [15:0] PSEL = f_concat_sel(16'h4321); + localparam P4 = f_add(P3, 1); + localparam P8 = f_add2(P3, P3, f_add(1, 1)); + localparam P5 = f_while(7); + localparam P16 = f_for(P4); + localparam P18 = f_case(P4); + localparam P6 = f_return(P4); + localparam P3 = 3; + localparam P128 = f_package(); + localparam [15:0] PSEL = f_concat_sel(16'h4321); - typedef struct packed { - logic [7:0] data; - } type_t; - typedef type_t [1:0] flist; - localparam flist PLIST = {8'd4,8'd8}; - localparam flist PARR = f_list_swap_2(PLIST); - typedef struct packed { - logic first; - logic second; - logic [31:0] data; - } bigstruct_t; - localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff); + typedef struct packed {logic [7:0] data;} type_t; + typedef type_t [1:0] flist; + localparam flist PLIST = {8'd4, 8'd8}; + localparam flist PARR = f_list_swap_2(PLIST); + typedef struct packed { + logic first; + logic second; + logic [31:0] data; + } bigstruct_t; + localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff); - initial begin + initial begin `ifdef TEST_VERBOSE - $display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18); + $display("P5=%0d P8=%0d P16=%0d P18=%0d", P5, P8, P16, P18); `endif - if (P3 !== 3) $stop; - if (P4 !== 4) $stop; - if (P5 !== 5) $stop; - if (P6 !== 6) $stop; - if (P8 !== 8) $stop; - if (P16 !== 16) $stop; - if (P18 !== 18) $stop; - if (PARR[0] != PLIST[1]) $stop; - if (PARR[1] != PLIST[0]) $stop; - if (bigparam.first != 1'b1) $stop; - if (bigparam.second != 1'b0) $stop; - if (bigparam.data != 32'hfff12fff) $stop; - if (P128 != 128) $stop; - if (PSEL != 16'h1234) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (P3 !== 3) $stop; + if (P4 !== 4) $stop; + if (P5 !== 5) $stop; + if (P6 !== 6) $stop; + if (P8 !== 8) $stop; + if (P16 !== 16) $stop; + if (P18 !== 18) $stop; + if (PARR[0] != PLIST[1]) $stop; + if (PARR[1] != PLIST[0]) $stop; + if (bigparam.first != 1'b1) $stop; + if (bigparam.second != 1'b0) $stop; + if (bigparam.data != 32'hfff12fff) $stop; + if (P128 != 128) $stop; + if (PSEL != 16'h1234) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - function integer f_package(); - return PARAM; - endfunction + function integer f_package(); + return PARAM; + endfunction - function integer f_add(input [31:0] a, input [31:0] b); - f_add = a+b; - endfunction + function integer f_add(input [31:0] a, input [31:0] b); + f_add = a + b; + endfunction - // Speced ok: function called from function - function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - f_add2 = f_add(a,b)+c; - endfunction + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + f_add2 = f_add(a, b) + c; + endfunction - // Speced ok: local variables - function integer f_for(input [31:0] a); - integer i; - integer times; - begin - times = 1; - for (i=0; i 1) break; + end + while (1) begin + out = out + 1; + if (a > 1) return 2 + out; + end + f_return = 0; + endfunction - function automatic integer f_return(input [31:0] a); - integer out = 2; - while (1) begin - out = out+1; - if (a>1) break; - end - while (1) begin - out = out+1; - if (a>1) return 2+out; - end - f_return = 0; - endfunction + function flist f_list_swap_2(input flist in_list); + f_list_swap_2[0].data = in_list[1].data; + f_list_swap_2[1].data = in_list[0].data; + endfunction - function flist f_list_swap_2(input flist in_list); - f_list_swap_2[0].data = in_list[1].data; - f_list_swap_2[1].data = in_list[0].data; - endfunction + function bigstruct_t f_return_struct(input first, input second, input [31:0] data); + bigstruct_t result; + result.data = data; + result.first = first; + result.second = second; + return result; + endfunction - function bigstruct_t f_return_struct(input first, input second, input [31:0] data); - bigstruct_t result; - result.data = data; - result.first = first; - result.second = second; - return result; - endfunction - - function [15:0] f_concat_sel(input [15:0] in); - reg [3:0] tmp1, tmp2, tmp3, tmp4; - {tmp4, tmp3, tmp2, tmp1} = in; - f_concat_sel = {tmp1, tmp2, tmp3, tmp4}; - endfunction + function [15:0] f_concat_sel(input [15:0] in); + reg [3:0] tmp1, tmp2, tmp3, tmp4; + {tmp4, tmp3, tmp2, tmp1} = in; + f_concat_sel = {tmp1, tmp2, tmp3, tmp4}; + endfunction endmodule diff --git a/test_regress/t/t_func_const2_bad.out b/test_regress/t/t_func_const2_bad.out index 1f2d4e74d..3575f9fd4 100644 --- a/test_regress/t/t_func_const2_bad.out +++ b/test_regress/t/t_func_const2_bad.out @@ -1,17 +1,17 @@ %Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' +%Error: t/t_func_const2_bad.v:22:22: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't.b8_a7.c9' - t/t_func_const2_bad.v:10:6: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const2_bad.v:15:13: ... Called from 'f_add()' with parameters: + t/t_func_const2_bad.v:9:20: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const2_bad.v:14:12: ... Called from 'f_add()' with parameters: a = 32'h7 b = 32'h8 - t/t_func_const2_bad.v:22:23: ... Called from 'f_add2()' with parameters: + t/t_func_const2_bad.v:22:22: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - 22 | localparam SOMEP = f_add2(A, B, 9); - | ^~~~~~ + 22 | localparam SOMEP = f_add2(A, B, 9); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_const2_bad.v b/test_regress/t/t_func_const2_bad.v index 5cabc03b5..669ddf715 100644 --- a/test_regress/t/t_func_const2_bad.v +++ b/test_regress/t/t_func_const2_bad.v @@ -5,47 +5,48 @@ // SPDX-License-Identifier: CC0-1.0 function integer f_add(input [31:0] a, input [31:0] b); - f_add = a+b; - if (f_add == 15) - $fatal(2, "f_add = 15"); + f_add = a + b; + if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - f_add2 = f_add(a,b)+c; + f_add2 = f_add(a, b) + c; endfunction -module c9 - #(parameter A = 1, - parameter B = 1); +module c9 #( + parameter A = 1, + parameter B = 1 +); - localparam SOMEP = f_add2(A, B, 9); + localparam SOMEP = f_add2(A, B, 9); endmodule -module b8 - #(parameter A = 1); +module b8 #( + parameter A = 1 +); - c9 - #(.A (A), - .B (8)) - c9(); + c9 #( + .A(A), + .B(8) + ) c9 (); endmodule module t; - localparam P6 = f_add(5, 1); - localparam P14 = f_add2(2, 3, f_add(4, 5)); - //localparam P24 = f_add2(7, 8, 9); + localparam P6 = f_add(5, 1); + localparam P14 = f_add2(2, 3, f_add(4, 5)); + //localparam P24 = f_add2(7, 8, 9); - b8 b8(); - b8 #(.A (6)) b8_a6(); - b8 #(.A (7)) b8_a7(); + b8 b8 (); + b8 #(.A(6)) b8_a6 (); + b8 #(.A(7)) b8_a7 (); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_const_packed_array_bad.out b/test_regress/t/t_func_const_packed_array_bad.out index 27f2585a3..6a3cb0b25 100644 --- a/test_regress/t/t_func_const_packed_array_bad.out +++ b/test_regress/t/t_func_const_packed_array_bad.out @@ -1,16 +1,16 @@ %Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' +%Error: t/t_func_const_packed_array_bad.v:12:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' - t/t_func_const_packed_array_bad.v:23:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_array_bad.v:31:16: ... Called from 'f_add()' with parameters: + t/t_func_const_packed_array_bad.v:22:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_array_bad.v:30:14: ... Called from 'f_add()' with parameters: params = [0 = 32'h7, 1 = 32'h8] - t/t_func_const_packed_array_bad.v:12:21: ... Called from 'f_add2()' with parameters: + t/t_func_const_packed_array_bad.v:12:20: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - 12 | localparam P24 = f_add2(7, 8, 9); - | ^~~~~~ + 12 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_array_bad.v b/test_regress/t/t_func_const_packed_array_bad.v index 07d7a7138..032684715 100644 --- a/test_regress/t/t_func_const_packed_array_bad.v +++ b/test_regress/t/t_func_const_packed_array_bad.v @@ -6,28 +6,27 @@ module t; - localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1}; - localparam P6 = f_add(P); - localparam P14 = f_add2(2, 3, f_add(P)); - localparam P24 = f_add2(7, 8, 9); + localparam [1 : 0][31 : 0] P = {32'd5, 32'd1}; + localparam P6 = f_add(P); + localparam P14 = f_add2(2, 3, f_add(P)); + localparam P24 = f_add2(7, 8, 9); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end - function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params); - f_add = params[0]+params[1]; - if (f_add == 15) - $fatal(2, "f_add = 15"); - endfunction + function integer f_add(input [1 : 0][31 : 0] params); + f_add = params[0] + params[1]; + if (f_add == 15) $fatal(2, "f_add = 15"); + endfunction - // Speced ok: function called from function - function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - logic [ 1 : 0 ] [ 31 : 0 ] params; - params[0] = a; - params[1] = b; - f_add2 = f_add(params)+c; - endfunction + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + logic [1 : 0][31 : 0] params; + params[0] = a; + params[1] = b; + f_add2 = f_add(params) + c; + endfunction endmodule diff --git a/test_regress/t/t_func_const_packed_struct_bad.out b/test_regress/t/t_func_const_packed_struct_bad.out index 6a160173a..80235c212 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.out +++ b/test_regress/t/t_func_const_packed_struct_bad.out @@ -1,16 +1,16 @@ %Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_struct_bad.v:14:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' +%Error: t/t_func_const_packed_struct_bad.v:14:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' - t/t_func_const_packed_struct_bad.v:25:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_struct_bad.v:33:16: ... Called from 'f_add()' with parameters: + t/t_func_const_packed_struct_bad.v:24:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_struct_bad.v:32:14: ... Called from 'f_add()' with parameters: params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}] - t/t_func_const_packed_struct_bad.v:14:21: ... Called from 'f_add2()' with parameters: + t/t_func_const_packed_struct_bad.v:14:20: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - 14 | localparam P24 = f_add2(7, 8, 9); - | ^~~~~~ + 14 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad.v b/test_regress/t/t_func_const_packed_struct_bad.v index 577e85cb6..93a6d68a2 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.v +++ b/test_regress/t/t_func_const_packed_struct_bad.v @@ -6,30 +6,29 @@ module t; - typedef struct packed { - logic [ 31 : 0 ] a; - logic [ 31 : 0 ] b; - } params_t; + typedef struct packed { + logic [31 : 0] a; + logic [31 : 0] b; + } params_t; - localparam P24 = f_add2(7, 8, 9); + localparam P24 = f_add2(7, 8, 9); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end - function integer f_add(input params_t [ 1 : 0 ] params); - f_add = params[0].a+params[1].b; - if (f_add == 15) - $fatal(2, "f_add = 15"); - endfunction + function integer f_add(input params_t [1 : 0] params); + f_add = params[0].a + params[1].b; + if (f_add == 15) $fatal(2, "f_add = 15"); + endfunction - // Speced ok: function called from function - function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - params_t [ 1 : 0 ] params; - params[0] = '{a:a, b:555}; - params[1] = '{a:12345, b:b}; - f_add2 = f_add(params)+c; - endfunction + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t [1 : 0] params; + params[0] = '{a: a, b: 555}; + params[1] = '{a: 12345, b: b}; + f_add2 = f_add(params) + c; + endfunction endmodule diff --git a/test_regress/t/t_func_const_packed_struct_bad2.out b/test_regress/t/t_func_const_packed_struct_bad2.out index d554dc1ca..8b79460df 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.out +++ b/test_regress/t/t_func_const_packed_struct_bad2.out @@ -1,16 +1,16 @@ %Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' +%Error: t/t_func_const_packed_struct_bad2.v:20:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' - t/t_func_const_packed_struct_bad2.v:31:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_struct_bad2.v:43:16: ... Called from 'f_add()' with parameters: + t/t_func_const_packed_struct_bad2.v:30:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_struct_bad2.v:42:14: ... Called from 'f_add()' with parameters: params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}] - t/t_func_const_packed_struct_bad2.v:20:21: ... Called from 'f_add2()' with parameters: + t/t_func_const_packed_struct_bad2.v:20:20: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - 20 | localparam P24 = f_add2(7, 8, 9); - | ^~~~~~ + 20 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad2.v b/test_regress/t/t_func_const_packed_struct_bad2.v index 746e321c3..0789c9b4c 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.v +++ b/test_regress/t/t_func_const_packed_struct_bad2.v @@ -6,40 +6,39 @@ module t; - typedef struct packed { - logic [ 31 : 0 ] b; - logic [ 7 : 0 ] bar; - } sub_params_t; + typedef struct packed { + logic [31 : 0] b; + logic [7 : 0] bar; + } sub_params_t; - typedef struct packed { - logic [ 31 : 0 ] a; - logic [ 5 : 0 ] foo; - sub_params_t sub_params; - } params_t; + typedef struct packed { + logic [31 : 0] a; + logic [5 : 0] foo; + sub_params_t sub_params; + } params_t; - localparam P24 = f_add2(7, 8, 9); + localparam P24 = f_add2(7, 8, 9); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end - function integer f_add(input params_t [ 1 : 0 ] params); - f_add = params[0].a+params[1].sub_params.b; - if (f_add == 15) - $fatal(2, "f_add = 15"); - endfunction + function integer f_add(input params_t [1 : 0] params); + f_add = params[0].a + params[1].sub_params.b; + if (f_add == 15) $fatal(2, "f_add = 15"); + endfunction - // Speced ok: function called from function - function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - params_t [ 1 : 0 ] params; - sub_params_t sp0; - sub_params_t sp1; - sp0 = '{b:55, bar:111}; - params[0] = '{a:a, foo:11, sub_params:sp0}; - sp1 = '{b:b, bar:112}; - params[1] = '{a:12345, foo:12, sub_params:sp1}; - f_add2 = f_add(params)+c; - endfunction + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t [1 : 0] params; + sub_params_t sp0; + sub_params_t sp1; + sp0 = '{b: 55, bar: 111}; + params[0] = '{a: a, foo: 11, sub_params: sp0}; + sp1 = '{b: b, bar: 112}; + params[1] = '{a: 12345, foo: 12, sub_params: sp1}; + f_add2 = f_add(params) + c; + endfunction endmodule diff --git a/test_regress/t/t_func_const_struct_bad.out b/test_regress/t/t_func_const_struct_bad.out index e813e4766..0b00d84c3 100644 --- a/test_regress/t/t_func_const_struct_bad.out +++ b/test_regress/t/t_func_const_struct_bad.out @@ -1,16 +1,16 @@ %Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' +%Error: t/t_func_const_struct_bad.v:17:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' - t/t_func_const_struct_bad.v:28:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_struct_bad.v:38:16: ... Called from 'f_add()' with parameters: + t/t_func_const_struct_bad.v:27:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_struct_bad.v:34:14: ... Called from 'f_add()' with parameters: params = '{a: 32'h7, b: 32'h8} - t/t_func_const_struct_bad.v:17:21: ... Called from 'f_add2()' with parameters: + t/t_func_const_struct_bad.v:17:20: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - 17 | localparam P24 = f_add2(7, 8, 9); - | ^~~~~~ + 17 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_struct_bad.v b/test_regress/t/t_func_const_struct_bad.v index 767761763..4a7b0a618 100644 --- a/test_regress/t/t_func_const_struct_bad.v +++ b/test_regress/t/t_func_const_struct_bad.v @@ -6,35 +6,31 @@ module t; - typedef struct packed { - logic [ 31 : 0 ] a; - logic [ 31 : 0 ] b; - } params_t; + typedef struct packed { + logic [31 : 0] a; + logic [31 : 0] b; + } params_t; - localparam params_t P = '{a:5, b:1}; - localparam P6 = f_add(P); - localparam P14 = f_add2(2, 3, f_add(P)); - localparam P24 = f_add2(7, 8, 9); + localparam params_t P = '{a: 5, b: 1}; + localparam P6 = f_add(P); + localparam P14 = f_add2(2, 3, f_add(P)); + localparam P24 = f_add2(7, 8, 9); - initial begin - // Should never get here - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end - function integer f_add(input params_t params); - f_add = params.a+params.b; - if (f_add == 15) - $fatal(2, "f_add = 15"); - endfunction + function integer f_add(input params_t params); + f_add = params.a + params.b; + if (f_add == 15) $fatal(2, "f_add = 15"); + endfunction - // Speced ok: function called from function - function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); - params_t params; - params = '{ - a: a, - b: b - }; - f_add2 = f_add(params)+c; - endfunction + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t params; + params = '{a: a, b: b}; + f_add2 = f_add(params) + c; + endfunction endmodule diff --git a/test_regress/t/t_func_crc.v b/test_regress/t/t_func_crc.v index f8ef4126a..b962a1256 100644 --- a/test_regress/t/t_func_crc.v +++ b/test_regress/t/t_func_crc.v @@ -3,144 +3,144 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg [63:0] d; + reg [31:0] c; - reg [63:0] d; - reg [31:0] c; + wire [31:0] q = crc(d, c); + reg [31:0] q_r; - wire [31:0] q = crc (d, c); - reg [31:0] q_r; - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - q_r <= q; - c <= q; - d <= {d[62:0], ^d[63:48]}; - //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); - if (cyc==1) begin - // Assign inputs randomly - q_r <= 32'h12345678; - c <= 32'h12345678; - d <= 64'hffffffff_ffffffff; - end - if (cyc==2) begin - d <= 64'hffffffff_ffffffff; - end - if (cyc==3) begin - d <= 64'hffffffff_ffffffff; - end - if (cyc==4) begin - d <= 64'h50183721_81a04b1a; - end - if (cyc==5) begin - end - if (cyc==9) begin - if (q !== 32'h38295e96) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + q_r <= q; + c <= q; + d <= {d[62:0], ^d[63:48]}; + //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); + if (cyc == 1) begin + // Assign inputs randomly + q_r <= 32'h12345678; + c <= 32'h12345678; + d <= 64'hffffffff_ffffffff; end - end - - function [31:0] crc; - input [63:0] di; - input [31:0] ci; - reg [63:0] drev; - begin - drev = reverse(di); - crc = newcrc(drev, ci); + if (cyc == 2) begin + d <= 64'hffffffff_ffffffff; end - endfunction - - function [63:0] reverse; - input [63:0] di; - integer i; - begin - reverse = 64'b0; - for (i=0; i<64; i=i+1) reverse[i] = di[63-i]; + if (cyc == 3) begin + d <= 64'hffffffff_ffffffff; end - endfunction - - function [31:0] newcrc; - input [63:0] D; - input [31:0] C; - reg [31:0] N; - reg [31:0] DT; - begin - N = 32'b0; - // Note this isn't a real CRC code; it's been munged for privacy - N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] - ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; - N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] - ^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0]; - N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11] - ^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7]; - N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0] - ^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1]; - N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0] - ^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2]; - N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1] - ^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1]; - N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1] - ^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0]; - N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0] - ^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4]; - N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2] - ^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6]; - N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7] - ^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1]; - N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1] - ^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2]; - N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1] - ^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1]; - N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2] - ^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6]; - N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11] - ^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9]; - N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0] - ^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1]; - N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2] - ^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5]; - N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1] - ^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6]; - N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0] - ^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0]; - N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7] - ^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0]; - N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2] - ^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0]; - N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1] - ^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4]; - N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1] - ^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2]; - N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3] - ^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5]; - N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3] - ^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1]; - N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0] - ^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0]; - N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2] - ^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6]; - N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0] - ^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1]; - N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2] - ^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3]; - N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0] - ^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0]; - N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0] - ^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0]; - N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0] - ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; - N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] - ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; - newcrc = N; + if (cyc == 4) begin + d <= 64'h50183721_81a04b1a; end - endfunction + if (cyc == 5) begin + end + if (cyc == 9) begin + if (q !== 32'h38295e96) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + function [31:0] crc; + input [63:0] di; + input [31:0] ci; + reg [63:0] drev; + begin + drev = reverse(di); + crc = newcrc(drev, ci); + end + endfunction + + function [63:0] reverse; + input [63:0] di; + integer i; + begin + reverse = 64'b0; + for (i = 0; i < 64; i = i + 1) reverse[i] = di[63-i]; + end + endfunction + + function [31:0] newcrc; + input [63:0] D; + input [31:0] C; + reg [31:0] N; + reg [31:0] DT; + begin + N = 32'b0; + // Note this isn't a real CRC code; it's been munged for privacy + // verilog_format: off + N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] + ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; + N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] + ^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0]; + N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11] + ^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7]; + N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0] + ^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1]; + N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0] + ^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2]; + N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1] + ^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1]; + N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1] + ^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0]; + N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0] + ^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4]; + N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2] + ^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6]; + N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7] + ^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1]; + N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1] + ^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2]; + N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1] + ^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1]; + N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2] + ^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6]; + N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11] + ^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9]; + N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0] + ^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1]; + N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2] + ^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5]; + N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1] + ^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6]; + N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0] + ^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0]; + N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7] + ^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0]; + N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2] + ^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0]; + N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1] + ^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4]; + N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1] + ^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2]; + N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3] + ^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5]; + N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3] + ^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1]; + N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0] + ^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0]; + N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2] + ^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6]; + N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0] + ^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1]; + N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2] + ^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3]; + N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0] + ^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0]; + N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0] + ^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0]; + N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0] + ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; + N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] + ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; + // verilog_format: on + newcrc = N; + end + endfunction endmodule diff --git a/test_regress/t/t_func_default_warn.v b/test_regress/t/t_func_default_warn.v index 5172cc469..dd582b857 100644 --- a/test_regress/t/t_func_default_warn.v +++ b/test_regress/t/t_func_default_warn.v @@ -7,22 +7,22 @@ function automatic logic foo ( - // Intentionally provide a non-width'ed default value - // This should warn, not error out - input logic x = 0 - ); - return x; + // Intentionally provide a non-width'ed default value + // This should warn, not error out + input logic x = 0 + ); + return x; endfunction module t; - logic foo_val; + logic foo_val; - initial begin - foo_val = foo(); - if (foo_val != 1'b0) $stop; + initial begin + foo_val = foo(); + if (foo_val != 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_defaults.v b/test_regress/t/t_func_defaults.v index 3c56a6b7e..a42ff3c30 100644 --- a/test_regress/t/t_func_defaults.v +++ b/test_regress/t/t_func_defaults.v @@ -8,42 +8,38 @@ parameter logic BAR = 1'b1; function automatic logic calc_y; - return 1'b1; + return 1'b1; endfunction -function automatic logic [1:0] foo - ( - input logic x = BAR, - input logic y = calc_y() - ); - return x + y; +function automatic logic [1:0] foo(input logic x = BAR, input logic y = calc_y()); + return x + y; endfunction class Foo; - static int x; - static function int get_x; - return x; - endfunction + static int x; + static function int get_x; + return x; + endfunction endclass function int mult2(int x = Foo::get_x()); - return 2 * x; + return 2 * x; endfunction module t; - logic [1:0] foo_val; + logic [1:0] foo_val; - initial begin - foo_val = foo(); - if (foo_val != 2'b10) $stop; + initial begin + foo_val = foo(); + if (foo_val != 2'b10) $stop; - if (mult2(1) != 2) $stop; - if (mult2() != 0) $stop; - Foo::x = 30; - if (mult2() != 60) $stop; + if (mult2(1) != 2) $stop; + if (mult2() != 0) $stop; + Foo::x = 30; + if (mult2() != 60) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index 172eef864..cf6c68153 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -5,51 +5,51 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - // verilator lint_off MULTIDRIVEN + // verilator lint_off MULTIDRIVEN - ma ma0 (); + ma ma0 (); - initial t.ma0.u_b[0].f(1); - initial t.ma0.u_b[0].f(clk); + initial t.ma0.u_b[0].f(1); + initial t.ma0.u_b[0].f(clk); - global_mod #(32'hf00d) global_cell (); - global_mod #(32'hf22d) global_cell2 (); + global_mod #(32'hf00d) global_cell (); + global_mod #(32'hf22d) global_cell2 (); - input clk; - integer cyc=1; + input clk; + integer cyc=1; - function [31:0] getName; input fake; getName = "t "; endfunction + function [31:0] getName; input fake; getName = "t "; endfunction - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==2) begin - if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; - if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; - end - if (cyc==3) begin - if (ma0. getName(1'b0) !== "ma ") $stop; - if (ma0.mb0. getName(1'b0) !== "mb ") $stop; - if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; - end - if (cyc==4) begin - if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; - if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; - if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; - end - if (cyc==5) begin - ma0. checkName(ma0. getName(1'b0)); - ma0.mb0. checkName(ma0.mb0. getName(1'b0)); - ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==2) begin + if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; + if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; + end + if (cyc==3) begin + if (ma0. getName(1'b0) !== "ma ") $stop; + if (ma0.mb0. getName(1'b0) !== "mb ") $stop; + if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; + end + if (cyc==4) begin + if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; + end + if (cyc==5) begin + ma0. checkName(ma0. getName(1'b0)); + ma0.mb0. checkName(ma0.mb0. getName(1'b0)); + ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule @@ -59,11 +59,11 @@ endmodule `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE - `define INLINE_MODULE /*verilator inline_module*/ - `define INLINE_MID_MODULE /*verilator inline_module*/ + `define INLINE_MODULE /*verilator inline_module*/ + `define INLINE_MID_MODULE /*verilator inline_module*/ `else - `define INLINE_MODULE /*verilator public_module*/ - `define INLINE_MID_MODULE /*verilator public_module*/ + `define INLINE_MODULE /*verilator public_module*/ + `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif `else @@ -72,87 +72,87 @@ endmodule `endif module global_mod; - `INLINE_MODULE - parameter INITVAL = 0; - integer globali; + `INLINE_MODULE + parameter INITVAL = 0; + integer globali; - initial globali = INITVAL; - function [31:0] getName; input fake; getName = "gmod"; endfunction - function [31:0] getGlob; input fake; getGlob = globali; endfunction + initial globali = INITVAL; + function [31:0] getName; input fake; getName = "gmod"; endfunction + function [31:0] getGlob; input fake; getGlob = globali; endfunction endmodule module ma (); - `INLINE_MODULE + `INLINE_MODULE - mb #(0) mb0 (); - reg [31:0] gName; initial gName = "ma "; - function [31:0] getName; input fake; getName = "ma "; endfunction - task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask + mb #(0) mb0 (); + reg [31:0] gName; initial gName = "ma "; + function [31:0] getName; input fake; getName = "ma "; endfunction + task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask - initial begin - if (ma.getName(1'b0) !== "ma ") $stop; - if (mb0.getName(1'b0) !== "mb ") $stop; - if (mb0.mc0.getName(1'b0) !== "mc ") $stop; - end + initial begin + if (ma.getName(1'b0) !== "ma ") $stop; + if (mb0.getName(1'b0) !== "mb ") $stop; + if (mb0.mc0.getName(1'b0) !== "mc ") $stop; + end endmodule module mb (); - `INLINE_MID_MODULE - parameter P2 = 0; + `INLINE_MID_MODULE + parameter P2 = 0; - mc #(P2,0) mc0 (); - mc #(P2,1) mc1 (); - global_mod #(32'hf33d) global_cell2 (); + mc #(P2,0) mc0 (); + mc #(P2,1) mc1 (); + global_mod #(32'hf33d) global_cell2 (); - reg [31:0] gName; initial gName = "mb "; - function [31:0] getName; input fake; getName = "mb "; endfunction - function [31:0] getP2 ; input fake; getP2 = P2; endfunction - task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask + reg [31:0] gName; initial gName = "mb "; + function [31:0] getName; input fake; getName = "mb "; endfunction + function [31:0] getP2 ; input fake; getP2 = P2; endfunction + task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask - initial begin + initial begin `ifndef verilator #1; `endif - if (ma. getName(1'b0) !== "ma ") $stop; - if ( getName(1'b0) !== "mb ") $stop; - if (mc1.getName(1'b0) !== "mc ") $stop; + if (ma. getName(1'b0) !== "ma ") $stop; + if ( getName(1'b0) !== "mb ") $stop; + if (mc1.getName(1'b0) !== "mc ") $stop; - ma. checkName (ma. gName); - /**/checkName ( gName); - mc1.checkName (mc1.gName); - ma. checkName (ma. getName(1'b0)); - /**/checkName ( getName(1'b0)); - mc1.checkName (mc1.getName(1'b0)); - end + ma. checkName (ma. gName); + /**/checkName ( gName); + mc1.checkName (mc1.gName); + ma. checkName (ma. getName(1'b0)); + /**/checkName ( getName(1'b0)); + mc1.checkName (mc1.getName(1'b0)); + end endmodule module mc (); - `INLINE_MODULE - parameter P2 = 0; - parameter P3 = 0; + `INLINE_MODULE + parameter P2 = 0; + parameter P3 = 0; - reg [31:0] gName; initial gName = "mc "; - function [31:0] getName; input fake; getName = "mc "; endfunction - function [31:0] getP3 ; input fake; getP3 = P3; endfunction - task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask + reg [31:0] gName; initial gName = "mc "; + function [31:0] getName; input fake; getName = "mc "; endfunction + function [31:0] getP3 ; input fake; getP3 = P3; endfunction + task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask - initial begin + initial begin `ifndef verilator #1; `endif - if (ma.getName(1'b0) !== "ma ") $stop; - if (mb.getName(1'b0) !== "mb ") $stop; - if (mc.getName(1'b0) !== "mc ") $stop; - ma.checkName (ma.gName); - mb.checkName (mb.gName); - mc.checkName (mc.gName); - ma.checkName (ma.getName(1'b0)); - mb.checkName (mb.getName(1'b0)); - mc.checkName (mc.getName(1'b0)); - end + if (ma.getName(1'b0) !== "ma ") $stop; + if (mb.getName(1'b0) !== "mb ") $stop; + if (mc.getName(1'b0) !== "mc ") $stop; + ma.checkName (ma.gName); + mb.checkName (mb.gName); + mc.checkName (mc.gName); + ma.checkName (ma.getName(1'b0)); + mb.checkName (mb.getName(1'b0)); + mc.checkName (mc.getName(1'b0)); + end endmodule module b; - function void f(bit v); - $display("%m"); - endfunction : f; + function void f(bit v); + $display("%m"); + endfunction : f; endmodule : b diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 09fe4c966..255b9d460 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -4,96 +4,90 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; - wire noswap = crc[32]; - wire nibble = crc[33]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire noswap = crc[32]; + wire nibble = crc[33]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .noswap (noswap), - .nibble (nibble), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .noswap (noswap), + .nibble (nibble), + .in (in[31:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h89522c3f5e5ca324) $stop; - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h89522c3f5e5ca324) $stop; + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, noswap, nibble, in - ); - input clk; +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, noswap, nibble, in + ); + input clk; - input noswap; - input nibble; + input noswap; + input nibble; - input [31:0] in; - output [31:0] out; + input [31:0] in; + output [31:0] out; - function [7:0] EndianSwap; - input Nibble; - input [7:0] Data; - begin - EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], + function [7:0] EndianSwap; + input Nibble; + input [7:0] Data; + begin + EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], Data[4], Data[5], Data[6], Data[7] } : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); - end - endfunction + end + endfunction - assign out[31:24] = (noswap ? in[31:24] - : EndianSwap(nibble, in[31:24])); - assign out[23:16] = (noswap ? in[23:16] - : EndianSwap(nibble, in[23:16])); - assign out[15:8] = (noswap ? in[15:8] - : EndianSwap(nibble, in[15:8])); - assign out[7:0] = (noswap ? in[7:0] - : EndianSwap(nibble, in[7:0])); + assign out[31:24] = (noswap ? in[31:24] : EndianSwap(nibble, in[31:24])); + assign out[23:16] = (noswap ? in[23:16] : EndianSwap(nibble, in[23:16])); + assign out[15:8] = (noswap ? in[15:8] : EndianSwap(nibble, in[15:8])); + assign out[7:0] = (noswap ? in[7:0] : EndianSwap(nibble, in[7:0])); endmodule diff --git a/test_regress/t/t_func_first.v b/test_regress/t/t_func_first.v index a0b80224c..4623de1d6 100644 --- a/test_regress/t/t_func_first.v +++ b/test_regress/t/t_func_first.v @@ -4,36 +4,35 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg [7:0] cyc; initial cyc = 0; - reg set_in_task; + reg [7:0] cyc; + initial cyc = 0; + reg set_in_task; - always @ (posedge clk) begin - if (cyc == 8'd0) begin - cyc <= 8'd1; - set_in_task <= 0; - end - if (cyc == 8'd1) begin - cyc <= 8'h2; - ttask; - end - if (cyc == 8'd2) begin - if (!set_in_task) $stop; - cyc <= 8'hf; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 8'd0) begin + cyc <= 8'd1; + set_in_task <= 0; + end + if (cyc == 8'd1) begin + cyc <= 8'h2; + ttask; + end + if (cyc == 8'd2) begin + if (!set_in_task) $stop; + cyc <= 8'hf; + $write("*-* All Finished *-*\n"); + $finish; + end + end - task ttask; - begin - set_in_task <= 1'b1; - end - endtask + task ttask; + begin + set_in_task <= 1'b1; + end + endtask endmodule diff --git a/test_regress/t/t_func_flip.v b/test_regress/t/t_func_flip.v index 911484111..1409d8494 100644 --- a/test_regress/t/t_func_flip.v +++ b/test_regress/t/t_func_flip.v @@ -4,51 +4,52 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`define INT_RANGE 31:0 -`define INT_RANGE 31:0 // Duplicate identical defs are OK +`define INT_RANGE 31:0 +`define INT_RANGE 31:0 // Duplicate identical defs are OK `define INT_RANGE_MAX 31 `define VECTOR_RANGE 511:0 -module t (clk); +module t ( + input clk +); - // verilator lint_off WIDTH + // verilator lint_off WIDTH - parameter WIDTH = 16; // Must be a power of 2 - parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) - parameter USE_BS = 1; // set to 1 for enable + parameter WIDTH = 16; // Must be a power of 2 + parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) + parameter USE_BS = 1; // set to 1 for enable - input clk; + function [`VECTOR_RANGE] func_tree_left; + input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector + reg [`VECTOR_RANGE] flip; + begin + flip = 'd0; + func_tree_left = flip; + end + endfunction - function [`VECTOR_RANGE] func_tree_left; - input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector - reg [`VECTOR_RANGE] flip; - begin - flip = 'd0; - func_tree_left = flip; + reg [WIDTH-1:0] a; // value to be shifted + reg [WIDTH-1:0] tree_left; + always @(a) begin : barrel_shift + tree_left = func_tree_left(a); + end // barrel_shift + + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a = 5; end - endfunction - - reg [WIDTH-1:0] a; // value to be shifted - reg [WIDTH-1:0] tree_left; - always @(a) begin : barrel_shift - tree_left = func_tree_left (a); - end // barrel_shift - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a = 5; - end - if (cyc==2) begin - $display ("%x\n",tree_left); - //if (tree_left != 'd15) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 2) begin + $display("%x\n", tree_left); + //if (tree_left != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_func_gen.v b/test_regress/t/t_func_gen.v index c87019760..fdf9e9627 100644 --- a/test_regress/t/t_func_gen.v +++ b/test_regress/t/t_func_gen.v @@ -6,29 +6,26 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - genvar g; - logic [1:0] mask = 0; - generate - for (g=0; g<2; g++) - begin : picker - logic block_passed = 0; // Just for visualizing V3LinkDot debug - function [3:0] pick; - input [3:0] randnum; - pick = randnum+g[3:0]; - endfunction - always @(posedge clk) begin - if (pick(3)!=3+g[3:0]) $stop; - else mask[g] = 1'b1; - if (mask == 2'b11) begin // All iterations must be finished - $write("*-* All Finished *-*\n"); - $finish; - end - end +module t ( + input clk +); + genvar g; + logic [1:0] mask = 0; + generate + for (g = 0; g < 2; g++) begin : picker + logic block_passed = 0; // Just for visualizing V3LinkDot debug + function [3:0] pick; + input [3:0] randnum; + pick = randnum + g[3:0]; + endfunction + always @(posedge clk) begin + if (pick(3) != 3 + g[3:0]) $stop; + else mask[g] = 1'b1; + if (mask == 2'b11) begin // All iterations must be finished + $write("*-* All Finished *-*\n"); + $finish; end - endgenerate + end + end + endgenerate endmodule diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v index 5550bf81e..e79894013 100644 --- a/test_regress/t/t_func_graphcirc.v +++ b/test_regress/t/t_func_graphcirc.v @@ -4,50 +4,52 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - ReadContDisps; - end - else if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ReadContDisps; + end + else if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end `ifndef verilator - DispContDisps; + DispContDisps; `endif - end + end - task ReadContDisps; - begin - $display("%m: Here: %d", cyc); - end - endtask + task ReadContDisps; + begin + $display("%m: Here: %d", cyc); + end + endtask - integer dindex; + integer dindex; - task DispContDisps; - /* verilator public */ - begin - if (cyc >= 2) begin - if ( cyc >= 4 ) begin - dindex = dindex + 2; //*** Error line - $display("%m: DIndex increment %d", cyc); + task DispContDisps; + /* verilator public */ + begin + if (cyc >= 2) begin + if (cyc >= 4) begin + dindex = dindex + 2; //*** Error line + $display("%m: DIndex increment %d", cyc); `ifdef VERILATOR - $c("VL_PRINTF(\"Hello1?\\n\");"); + $c("VL_PRINTF(\"Hello1?\\n\");"); `endif - end + end `ifdef VERILATOR - $c("VL_PRINTF(\"Hello2?\\n\");"); - $c("VL_PRINTF(\"Hello3?\\n\");"); + $c("VL_PRINTF(\"Hello2?\\n\");"); + $c("VL_PRINTF(\"Hello3?\\n\");"); `endif - end end - endtask + end + endtask endmodule diff --git a/test_regress/t/t_func_grey.v b/test_regress/t/t_func_grey.v index b4a458155..cf3201d55 100644 --- a/test_regress/t/t_func_grey.v +++ b/test_regress/t/t_func_grey.v @@ -4,37 +4,44 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - // surefire lint_off _NETNM - // surefire lint_off STMINI + // surefire lint_off _NETNM + // surefire lint_off STMINI - input clk; - integer _mode; initial _mode = 0; + integer _mode; + initial _mode = 0; - wire [2:0] b3; reg [2:0] g3; - wire [5:0] b6; reg [5:0] g6; + wire [2:0] b3; + reg [2:0] g3; + wire [5:0] b6; + reg [5:0] g6; - t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3)); - t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6)); + t_func_grey2bin #(3) g2b3 ( + .b(b3), + .g(g3) + ); + t_func_grey2bin #(6) g2b6 ( + .b(b6), + .g(g6) + ); - always @ (posedge clk) begin - if (_mode==0) begin - _mode <= 1; - g3 <= 3'b101; - g6 <= 6'b110101; - end - else if (_mode==1) begin - if (b3 !== 3'b110) $stop; - if (b6 !== 6'b100110) $stop; - _mode <= 2; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (_mode == 0) begin + _mode <= 1; + g3 <= 3'b101; + g6 <= 6'b110101; + end + else if (_mode == 1) begin + if (b3 !== 3'b110) $stop; + if (b6 !== 6'b100110) $stop; + _mode <= 2; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule @@ -46,27 +53,27 @@ endmodule // b[1] = ^g[3:1] // b[0] = ^g[3:[SZ-1:0] cur0] -module t_func_grey2bin (/*AUTOARG*/ - // Outputs - b, - // Inputs - g - ); +module t_func_grey2bin ( /*AUTOARG*/ + // Outputs + b, + // Inputs + g +); - // surefire lint_off STMFOR + // surefire lint_off STMFOR - parameter SZ = 5; - output [SZ-1:0] b; - input [SZ-1:0] g; + parameter SZ = 5; + output [SZ-1:0] b; + input [SZ-1:0] g; - /*AUTOREG*/ - // Beginning of automatic regs (for this module's undeclared outputs) - reg [SZ-1:0] b; - // End of automatics + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [SZ-1:0] b; + // End of automatics - integer i; - always @(/*AUTOSENSE*/g) - for (i=0; i> i); // surefire lint_off_line LATASS + integer i; + always @( /*AUTOSENSE*/ g) + for (i = 0; i < SZ; i = i + 1) + b[i] = ^(g >> i); // surefire lint_off_line LATASS endmodule diff --git a/test_regress/t/t_func_impure_bad.out b/test_regress/t/t_func_impure_bad.out index b3e1b1acc..29c596d46 100644 --- a/test_regress/t/t_func_impure_bad.out +++ b/test_regress/t/t_func_impure_bad.out @@ -1,14 +1,14 @@ -%Error-IMPURE: t/t_func_impure_bad.v:11:9: Unsupported: External variable referenced by non-inlined function/task: 't.foo' - 11 | task foo; - | ^~~ - t/t_func_impure_bad.v:13:7: ... Location of the external reference: 't.sig' - 13 | sig = '1; - | ^~~ +%Error-IMPURE: t/t_func_impure_bad.v:11:8: Unsupported: External variable referenced by non-inlined function/task: 't.foo' + 11 | task foo; + | ^~~ + t/t_func_impure_bad.v:13:5: ... Location of the external reference: 't.sig' + 13 | sig = '1; + | ^~~ ... For error description see https://verilator.org/warn/IMPURE?v=latest -%Error-IMPURE: t/t_func_impure_bad.v:20:9: Unsupported: External variable referenced by non-inlined function/task: 't.baz' - 20 | task baz; - | ^~~ - t/t_func_impure_bad.v:17:7: ... Location of the external reference: 't.sig' - 17 | sig = '1; - | ^~~ +%Error-IMPURE: t/t_func_impure_bad.v:20:8: Unsupported: External variable referenced by non-inlined function/task: 't.baz' + 20 | task baz; + | ^~~ + t/t_func_impure_bad.v:17:5: ... Location of the external reference: 't.sig' + 17 | sig = '1; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_impure_bad.v b/test_regress/t/t_func_impure_bad.v index d45511ad3..ce3499f00 100644 --- a/test_regress/t/t_func_impure_bad.v +++ b/test_regress/t/t_func_impure_bad.v @@ -6,25 +6,25 @@ module t; - int sig; + int sig; - task foo; - // verilator no_inline_task - sig = '1; - endtask + task foo; + // verilator no_inline_task + sig = '1; + endtask - task bar; - sig = '1; - endtask + task bar; + sig = '1; + endtask - task baz; - // verilator no_inline_task - bar(); - endtask + task baz; + // verilator no_inline_task + bar(); + endtask - initial begin - foo(); - baz(); - end + initial begin + foo(); + baz(); + end endmodule diff --git a/test_regress/t/t_func_inconly.v b/test_regress/t/t_func_inconly.v index 043f7e340..78c70b3fe 100644 --- a/test_regress/t/t_func_inconly.v +++ b/test_regress/t/t_func_inconly.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 module t; - task main; - integer varintask; - varintask = 0; - while (varintask < 4) begin - varintask = varintask + 1; - end - if (varintask != 4) $stop; - endtask - initial begin - main; - $write("*-* All Finished *-*\n"); - $finish; - end + task main; + integer varintask; + varintask = 0; + while (varintask < 4) begin + varintask = varintask + 1; + end + if (varintask != 4) $stop; + endtask + initial begin + main; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_inout_bit_sel.v b/test_regress/t/t_func_inout_bit_sel.v index d407267e1..dd0ef503d 100644 --- a/test_regress/t/t_func_inout_bit_sel.v +++ b/test_regress/t/t_func_inout_bit_sel.v @@ -4,28 +4,30 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; - function bit get_x_set_1(inout bit x); - bit a = x; - x = 1; - return a; - endfunction + function bit get_x_set_1(inout bit x); + bit a = x; + x = 1; + return a; + endfunction endclass module t; - int a; - bit b; - Cls cls; - initial begin - cls = new; - b = cls.get_x_set_1(a[1]); - `checkh(b, 0); - `checkh(a[1], 1); + int a; + bit b; + Cls cls; + initial begin + cls = new; + b = cls.get_x_set_1(a[1]); + `checkh(b, 0); + `checkh(a[1], 1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_io_order.v b/test_regress/t/t_func_io_order.v index 682f41ca7..350c3ccf9 100644 --- a/test_regress/t/t_func_io_order.v +++ b/test_regress/t/t_func_io_order.v @@ -4,72 +4,68 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + // Inputs + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire ain = crc[0]; + // Take CRC data and apply to testblock inputs + wire ain = crc[0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic bout; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic bout; // From test of Test.v + // End of automatics - Test test(/*AUTOINST*/ - // Outputs - .bout (bout), - // Inputs - .ain (ain)); + Test test ( /*AUTOINST*/ + // Outputs + .bout(bout), + // Inputs + .ain(ain) + ); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc < 10) begin - if (bout != ~ain) $stop; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + if (bout != ~ain) $stop; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(/*AUTOARG*/ - // Outputs - bout, - // Inputs - ain - ); +module Test ( /*AUTOARG*/ + // Outputs + bout, + // Inputs + ain +); - input logic ain; - output logic bout; + input logic ain; + output logic bout; - function automatic void inv - (input logic w_in, - output logic w_out); - w_out = ~w_in; - endfunction + function automatic void inv(input logic w_in, output logic w_out); + w_out = ~w_in; + endfunction - always_comb - inv(.w_out(bout), - .w_in(ain)); + always_comb inv(.w_out(bout), .w_in(ain)); endmodule diff --git a/test_regress/t/t_func_lib.v b/test_regress/t/t_func_lib.v index 6006e2aa5..ff7e45de5 100644 --- a/test_regress/t/t_func_lib.v +++ b/test_regress/t/t_func_lib.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index 13bca13cc..59041f4f1 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -6,96 +6,124 @@ `define zednkw 200 -module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr); -input zfghtn; -input [4:0] cjtmau; -input vipmpg; -input [7:0] knquim; -input [7:0] kqxkkr; +module BreadAddrDP ( + zfghtn, + cjtmau, + vipmpg, + knquim, + kqxkkr +); + input zfghtn; + input [4:0] cjtmau; + input vipmpg; + input [7:0] knquim; + input [7:0] kqxkkr; -reg covfok; + reg covfok; -reg [15:0] xwieqw; -reg [2:0] ofnjjt; + reg [15:0] xwieqw; + reg [2:0] ofnjjt; -reg [37:0] hdsejo[1:0]; + reg [37:0] hdsejo[1:0]; -reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; -reg vrqrih, ryyjxy; -reg fgzsox; + reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; + reg vrqrih, ryyjxy; + reg fgzsox; -wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr; -wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10]; -wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10]; -wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr; -wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr; + wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr; + wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10]; + wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10]; + wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr; + wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr; -wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); -wire smxixw = vrqrih | (ryyjxy & ktsveg); + wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); + wire smxixw = vrqrih | (ryyjxy & ktsveg); -wire [7:0] grvsrs, kyxrft, uxhkka; + wire [7:0] grvsrs, kyxrft, uxhkka; -wire [7:0] eianuv = 8'h01 << ofnjjt; -wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; -wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; -wire [7:0] nahzat = {8{iytyol}} & eianuv; + wire [7:0] eianuv = 8'h01 << ofnjjt; + wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; + wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; + wire [7:0] nahzat = {8{iytyol}} & eianuv; -genvar i; -generate - for (i=0;i<8;i=i+1) - begin : dnlpyw - DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i], - knquim[3:0], covfok, grvsrs[i]); - DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i], - knquim[7:4], covfok, kyxrft[i]); - DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i], - kqxkkr[3:0], covfok, uxhkka[i]); - end -endgenerate + genvar i; + generate + for (i = 0; i < 8; i = i + 1) begin : dnlpyw + DecCountReg4 bzpytc ( + zfghtn, + fgzsox, + zlnzlj[i], + knquim[3:0], + covfok, + grvsrs[i] + ); + DecCountReg4 oghukp ( + zfghtn, + fgzsox, + zlnzlj[i], + knquim[7:4], + covfok, + kyxrft[i] + ); + DecCountReg4 ttvjoo ( + zfghtn, + fgzsox, + nahzat[i], + kqxkkr[3:0], + covfok, + uxhkka[i] + ); + end + endgenerate endmodule -module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh); -input clk, fgzsox, fckiyr, covfok; -input [3:0] uezcjy; -output juvlsh; +module DecCountReg4 ( + clk, + fgzsox, + fckiyr, + uezcjy, + covfok, + juvlsh +); + input clk, fgzsox, fckiyr, covfok; + input [3:0] uezcjy; + output juvlsh; -task Xinit; -begin + task Xinit; + begin `ifdef TEST_HARNESS - khgawe = 1'b0; + khgawe = 1'b0; `endif -end -endtask -function X; -input vrdejo; -begin + end + endtask + function X; + input vrdejo; + begin `ifdef TEST_HARNESS - if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1; + if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1; `endif - X = vrdejo; -end -endfunction -task Xcheck; -input vzpwwy; -begin -end -endtask + X = vrdejo; + end + endfunction + task Xcheck; + input vzpwwy; + begin + end + endtask -reg [3:0] udbvtl; + reg [3:0] udbvtl; -assign juvlsh = |udbvtl; -wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1)); + assign juvlsh = |udbvtl; + wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1)); -wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox; + wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox; -always @(posedge clk) -begin - Xinit; - if (X(qqibou)) - udbvtl <= #`zednkw mppedc; + always @(posedge clk) begin + Xinit; + if (X(qqibou)) udbvtl <= #`zednkw mppedc; - Xcheck(fgzsox); -end + Xcheck(fgzsox); + end endmodule diff --git a/test_regress/t/t_func_link.v b/test_regress/t/t_func_link.v index 31950f388..8bff7bbdf 100644 --- a/test_regress/t/t_func_link.v +++ b/test_regress/t/t_func_link.v @@ -4,12 +4,13 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module Test(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); // Replace this module with the device under test. // @@ -21,11 +22,11 @@ module Test(/*AUTOARG*/ output reg [31:0] out; integer cyc = 0; - SubTest subtest(.out); + SubTest subtest (.out); always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc < 99) begin @@ -39,15 +40,15 @@ module Test(/*AUTOARG*/ end endmodule -module SubTest( - output logic[31:0] out +module SubTest ( + output logic [31:0] out ); if (1) begin : block - function void set(logic[31:0] in); - out <= in; - endfunction + function void set(logic [31:0] in); + out <= in; + endfunction end : block diff --git a/test_regress/t/t_func_many_return.v b/test_regress/t/t_func_many_return.v index 89c157369..7d25a5f2c 100644 --- a/test_regress/t/t_func_many_return.v +++ b/test_regress/t/t_func_many_return.v @@ -6,246 +6,246 @@ module t; - function automatic string get_csr_name(input logic [11:0] csr_addr); - // verilator no_inline_task - unique case (csr_addr) - 12'd0000: return "xx0000xxxxx"; - 12'd0001: return "xx0001xxxx"; - 12'd1952: return "xx1952xxxxx"; - 12'd1953: return "xx1953xxx1"; - 12'd1954: return "xx1954xxx2"; - 12'd1955: return "xx1955xxx3"; - 12'd1968: return "xx1968xx"; - 12'd1969: return "xx1969x"; - 12'd1970: return "xx1970xxxxxx"; - 12'd0256: return "xx0256xxxxx"; - 12'd0258: return "xx0258xxxxx"; - 12'd0259: return "xx0259xxxxx"; - 12'd0260: return "xx0260x"; - 12'd0261: return "xx0261xxx"; - 12'd0262: return "xx0262xxxxxxxx"; - 12'd2816: return "xx2816xxxx"; - 12'd2818: return "xx2818xxxxxx"; - 12'd2819: return "xx2819xxxxxxxxx3"; - 12'd2820: return "xx2820xxxxxxxxx4"; - 12'd2821: return "xx2821xxxxxxxxx5"; - 12'd2822: return "xx2822xxxxxxxxx6"; - 12'd2823: return "xx2823xxxxxxxxx7"; - 12'd2824: return "xx2824xxxxxxxxx8"; - 12'd2825: return "xx2825xxxxxxxxx9"; - 12'd2826: return "xx2826xxxxxxxxx10"; - 12'd2827: return "xx2827xxxxxxxxx11"; - 12'd2828: return "xx2828xxxxxxxxx12"; - 12'd2829: return "xx2829xxxxxxxxx13"; - 12'd2830: return "xx2830xxxxxxxxx14"; - 12'd2831: return "xx2831xxxxxxxxx15"; - 12'd2832: return "xx2832xxxxxxxxx16"; - 12'd2833: return "xx2833xxxxxxxxx17"; - 12'd2834: return "xx2834xxxxxxxxx18"; - 12'd2835: return "xx2835xxxxxxxxx19"; - 12'd2836: return "xx2836xxxxxxxxx20"; - 12'd2837: return "xx2837xxxxxxxxx21"; - 12'd2838: return "xx2838xxxxxxxxx22"; - 12'd2839: return "xx2839xxxxxxxxx23"; - 12'd2840: return "xx2840xxxxxxxxx24"; - 12'd2841: return "xx2841xxxxxxxxx25"; - 12'd2842: return "xx2842xxxxxxxxx26"; - 12'd2843: return "xx2843xxxxxxxxx27"; - 12'd2844: return "xx2844xxxxxxxxx28"; - 12'd2845: return "xx2845xxxxxxxxx29"; - 12'd2846: return "xx2846xxxxxxxxx30"; - 12'd2847: return "xx2847xxxxxxxxx31"; - 12'd2944: return "xx2944xxxxx"; - 12'd2946: return "xx2946xxxxxxx"; - 12'd2947: return "xx2947xxxxxxxxx3x"; - 12'd2948: return "xx2948xxxxxxxxx4x"; - 12'd2949: return "xx2949xxxxxxxxx5x"; - 12'd2950: return "xx2950xxxxxxxxx6x"; - 12'd2951: return "xx2951xxxxxxxxx7x"; - 12'd2952: return "xx2952xxxxxxxxx8x"; - 12'd2953: return "xx2953xxxxxxxxx9x"; - 12'd2954: return "xx2954xxxxxxxxx10x"; - 12'd2955: return "xx2955xxxxxxxxx11x"; - 12'd2956: return "xx2956xxxxxxxxx12x"; - 12'd2957: return "xx2957xxxxxxxxx13x"; - 12'd2958: return "xx2958xxxxxxxxx14x"; - 12'd2959: return "xx2959xxxxxxxxx15x"; - 12'd2960: return "xx2960xxxxxxxxx16x"; - 12'd2961: return "xx2961xxxxxxxxx17x"; - 12'd2962: return "xx2962xxxxxxxxx18x"; - 12'd2963: return "xx2963xxxxxxxxx19x"; - 12'd2964: return "xx2964xxxxxxxxx20x"; - 12'd2965: return "xx2965xxxxxxxxx21x"; - 12'd2966: return "xx2966xxxxxxxxx22x"; - 12'd2967: return "xx2967xxxxxxxxx23x"; - 12'd2968: return "xx2968xxxxxxxxx24x"; - 12'd2969: return "xx2969xxxxxxxxx25x"; - 12'd2970: return "xx2970xxxxxxxxx26x"; - 12'd2971: return "xx2971xxxxxxxxx27x"; - 12'd2972: return "xx2972xxxxxxxxx28x"; - 12'd2973: return "xx2973xxxxxxxxx29x"; - 12'd2974: return "xx2974xxxxxxxxx30x"; - 12'd2975: return "xx2975xxxxxxxxx31x"; - 12'd0002: return "xx0002x"; - 12'd3072: return "xx3072xxx"; - 12'd3073: return "xx3073xx"; - 12'd3074: return "xx3074xxxxx"; - 12'd3075: return "xx3075xxxxxxxx3"; - 12'd3076: return "xx3076xxxxxxxx4"; - 12'd3077: return "xx3077xxxxxxxx5"; - 12'd3078: return "xx3078xxxxxxxx6"; - 12'd3079: return "xx3079xxxxxxxx7"; - 12'd3080: return "xx3080xxxxxxxx8"; - 12'd3081: return "xx3081xxxxxxxx9"; - 12'd3082: return "xx3082xxxxxxxx10"; - 12'd3083: return "xx3083xxxxxxxx11"; - 12'd3084: return "xx3084xxxxxxxx12"; - 12'd3085: return "xx3085xxxxxxxx13"; - 12'd3086: return "xx3086xxxxxxxx14"; - 12'd3087: return "xx3087xxxxxxxx15"; - 12'd3088: return "xx3088xxxxxxxx16"; - 12'd3089: return "xx3089xxxxxxxx17"; - 12'd3090: return "xx3090xxxxxxxx18"; - 12'd3091: return "xx3091xxxxxxxx19"; - 12'd3092: return "xx3092xxxxxxxx20"; - 12'd3093: return "xx3093xxxxxxxx21"; - 12'd3094: return "xx3094xxxxxxxx22"; - 12'd3095: return "xx3095xxxxxxxx23"; - 12'd3096: return "xx3096xxxxxxxx24"; - 12'd3097: return "xx3097xxxxxxxx25"; - 12'd3098: return "xx3098xxxxxxxx26"; - 12'd3099: return "xx3099xxxxxxxx27"; - 12'd3100: return "xx3100xxxxxxxx28"; - 12'd3101: return "xx3101xxxxxxxx29"; - 12'd3102: return "xx3102xxxxxxxx30"; - 12'd3103: return "xx3103xxxxxxxx31"; - 12'd3200: return "xx3200xxxx"; - 12'd3201: return "xx3201xxx"; - 12'd3202: return "xx3202xxxxxx"; - 12'd3203: return "xx3203xxxxxxxx3x"; - 12'd3204: return "xx3204xxxxxxxx4x"; - 12'd3205: return "xx3205xxxxxxxx5x"; - 12'd3206: return "xx3206xxxxxxxx6x"; - 12'd3207: return "xx3207xxxxxxxx7x"; - 12'd3208: return "xx3208xxxxxxxx8x"; - 12'd3209: return "xx3209xxxxxxxx9x"; - 12'd0320: return "xx0320xxxxxx"; - 12'd3210: return "xx3210xxxxxxxx10x"; - 12'd3211: return "xx3211xxxxxxxx11x"; - 12'd3212: return "xx3212xxxxxxxx12x"; - 12'd3213: return "xx3213xxxxxxxx13x"; - 12'd3214: return "xx3214xxxxxxxx14x"; - 12'd3215: return "xx3215xxxxxxxx15x"; - 12'd3216: return "xx3216xxxxxxxx16x"; - 12'd3217: return "xx3217xxxxxxxx17x"; - 12'd3218: return "xx3218xxxxxxxx18x"; - 12'd3219: return "xx3219xxxxxxxx19x"; - 12'd3220: return "xx3220xxxxxxxx20x"; - 12'd3221: return "xx3221xxxxxxxx21x"; - 12'd3222: return "xx3222xxxxxxxx22x"; - 12'd3223: return "xx3223xxxxxxxx23x"; - 12'd3224: return "xx3224xxxxxxxx24x"; - 12'd3225: return "xx3225xxxxxxxx25x"; - 12'd3226: return "xx3226xxxxxxxx26x"; - 12'd3227: return "xx3227xxxxxxxx27x"; - 12'd3228: return "xx3228xxxxxxxx28x"; - 12'd3229: return "xx3229xxxxxxxx29x"; - 12'd3230: return "xx3230xxxxxxxx30x"; - 12'd3231: return "xx3231xxxxxxxx31x"; - 12'd3857: return "xx3857xxxxxxx"; - 12'd3858: return "xx3858xxxxx"; - 12'd3859: return "xx3859xxxx"; - 12'd3860: return "xx3860xxxxx"; - 12'd0512: return "xx0512xxxxx"; - 12'd0514: return "xx0514xxxxx"; - 12'd0515: return "xx0515xxxxx"; - 12'd0516: return "xx0516x"; - 12'd0517: return "xx0517xxx"; - 12'd0576: return "xx0576xxxxxx"; - 12'd0577: return "xx0577xx"; - 12'd0578: return "xx0578xxxx"; - 12'd0579: return "xx0579xxxxxx"; - 12'd0580: return "xx0580x"; - 12'd0768: return "xx0768xxxxx"; - 12'd0769: return "xx0769xx"; - 12'd0770: return "xx0770xxxxx"; - 12'd0771: return "xx0771xxxxx"; - 12'd0772: return "xx0772x"; - 12'd0773: return "xx0773xxx"; - 12'd0774: return "xx0774xxxxxxxx"; - 12'd0800: return "xx0800xxxxxxxxxxx"; - 12'd0803: return "xx0803xxxxxxx3"; - 12'd0804: return "xx0804xxxxxxx4"; - 12'd0805: return "xx0805xxxxxxx5"; - 12'd0806: return "xx0806xxxxxxx6"; - 12'd0807: return "xx0807xxxxxxx7"; - 12'd0808: return "xx0808xxxxxxx8"; - 12'd0809: return "xx0809xxxxxxx9"; - 12'd0810: return "xx0810xxxxxxx10"; - 12'd0811: return "xx0811xxxxxxx11"; - 12'd0812: return "xx0812xxxxxxx12"; - 12'd0813: return "xx0813xxxxxxx13"; - 12'd0814: return "xx0814xxxxxxx14"; - 12'd0815: return "xx0815xxxxxxx15"; - 12'd0816: return "xx0816xxxxxxx16"; - 12'd0817: return "xx0817xxxxxxx17"; - 12'd0818: return "xx0818xxxxxxx18"; - 12'd0819: return "xx0819xxxxxxx19"; - 12'd0820: return "xx0820xxxxxxx20"; - 12'd0821: return "xx0821xxxxxxx21"; - 12'd0822: return "xx0822xxxxxxx22"; - 12'd0823: return "xx0823xxxxxxx23"; - 12'd0824: return "xx0824xxxxxxx24"; - 12'd0825: return "xx0825xxxxxxx25"; - 12'd0826: return "xx0826xxxxxxx26"; - 12'd0827: return "xx0827xxxxxxx27"; - 12'd0828: return "xx0828xxxxxxx28"; - 12'd0829: return "xx0829xxxxxxx29"; - 12'd0830: return "xx0830xxxxxxx30"; - 12'd0831: return "xx0831xxxxxxx31"; - 12'd0832: return "xx0832xxxxxx"; - 12'd0833: return "xx0833xx"; - 12'd0834: return "xx0834xxxx"; - 12'd0835: return "xx0835xxx"; - 12'd0836: return "xx0836x"; - 12'd0896: return "xx0896xxx"; - 12'd0897: return "xx0897xxxx"; - 12'd0898: return "xx0898xxxx"; - 12'd0899: return "xx0899xxxxx"; - 12'd0900: return "xx0900xxxx"; - 12'd0901: return "xx0901xxxxx"; - 12'd0928: return "xx0928xxxx0"; - 12'd0929: return "xx0929xxxx1"; - 12'd0930: return "xx0930xxxx2"; - 12'd0931: return "xx0931xxxx3"; - 12'd0944: return "xx0944xxxxx0"; - 12'd0945: return "xx0945xxxxx1"; - 12'd0946: return "xx0946xxxxx2"; - 12'd0947: return "xx0947xxxxx3"; - 12'd0948: return "xx0948xxxxx4"; - 12'd0949: return "xx0949xxxxx5"; - 12'd0950: return "xx0950xxxxx6"; - 12'd0951: return "xx0951xxxxx7"; - 12'd0952: return "xx0952xxxxx8"; - 12'd0953: return "xx0953xxxxx9"; - 12'd0954: return "xx0954xxxxx10"; - 12'd0955: return "xx0955xxxxx11"; - 12'd0956: return "xx0956xxxxx12"; - 12'd0957: return "xx0957xxxxx13"; - 12'd0958: return "xx0958xxxxx14"; - 12'd0959: return "xx0959xxxxx15"; - default: return $sformatf("0x%x", csr_addr); - endcase - endfunction + function automatic string get_csr_name(input logic [11:0] csr_addr); + // verilator no_inline_task + unique case (csr_addr) + 12'd0000: return "xx0000xxxxx"; + 12'd0001: return "xx0001xxxx"; + 12'd1952: return "xx1952xxxxx"; + 12'd1953: return "xx1953xxx1"; + 12'd1954: return "xx1954xxx2"; + 12'd1955: return "xx1955xxx3"; + 12'd1968: return "xx1968xx"; + 12'd1969: return "xx1969x"; + 12'd1970: return "xx1970xxxxxx"; + 12'd0256: return "xx0256xxxxx"; + 12'd0258: return "xx0258xxxxx"; + 12'd0259: return "xx0259xxxxx"; + 12'd0260: return "xx0260x"; + 12'd0261: return "xx0261xxx"; + 12'd0262: return "xx0262xxxxxxxx"; + 12'd2816: return "xx2816xxxx"; + 12'd2818: return "xx2818xxxxxx"; + 12'd2819: return "xx2819xxxxxxxxx3"; + 12'd2820: return "xx2820xxxxxxxxx4"; + 12'd2821: return "xx2821xxxxxxxxx5"; + 12'd2822: return "xx2822xxxxxxxxx6"; + 12'd2823: return "xx2823xxxxxxxxx7"; + 12'd2824: return "xx2824xxxxxxxxx8"; + 12'd2825: return "xx2825xxxxxxxxx9"; + 12'd2826: return "xx2826xxxxxxxxx10"; + 12'd2827: return "xx2827xxxxxxxxx11"; + 12'd2828: return "xx2828xxxxxxxxx12"; + 12'd2829: return "xx2829xxxxxxxxx13"; + 12'd2830: return "xx2830xxxxxxxxx14"; + 12'd2831: return "xx2831xxxxxxxxx15"; + 12'd2832: return "xx2832xxxxxxxxx16"; + 12'd2833: return "xx2833xxxxxxxxx17"; + 12'd2834: return "xx2834xxxxxxxxx18"; + 12'd2835: return "xx2835xxxxxxxxx19"; + 12'd2836: return "xx2836xxxxxxxxx20"; + 12'd2837: return "xx2837xxxxxxxxx21"; + 12'd2838: return "xx2838xxxxxxxxx22"; + 12'd2839: return "xx2839xxxxxxxxx23"; + 12'd2840: return "xx2840xxxxxxxxx24"; + 12'd2841: return "xx2841xxxxxxxxx25"; + 12'd2842: return "xx2842xxxxxxxxx26"; + 12'd2843: return "xx2843xxxxxxxxx27"; + 12'd2844: return "xx2844xxxxxxxxx28"; + 12'd2845: return "xx2845xxxxxxxxx29"; + 12'd2846: return "xx2846xxxxxxxxx30"; + 12'd2847: return "xx2847xxxxxxxxx31"; + 12'd2944: return "xx2944xxxxx"; + 12'd2946: return "xx2946xxxxxxx"; + 12'd2947: return "xx2947xxxxxxxxx3x"; + 12'd2948: return "xx2948xxxxxxxxx4x"; + 12'd2949: return "xx2949xxxxxxxxx5x"; + 12'd2950: return "xx2950xxxxxxxxx6x"; + 12'd2951: return "xx2951xxxxxxxxx7x"; + 12'd2952: return "xx2952xxxxxxxxx8x"; + 12'd2953: return "xx2953xxxxxxxxx9x"; + 12'd2954: return "xx2954xxxxxxxxx10x"; + 12'd2955: return "xx2955xxxxxxxxx11x"; + 12'd2956: return "xx2956xxxxxxxxx12x"; + 12'd2957: return "xx2957xxxxxxxxx13x"; + 12'd2958: return "xx2958xxxxxxxxx14x"; + 12'd2959: return "xx2959xxxxxxxxx15x"; + 12'd2960: return "xx2960xxxxxxxxx16x"; + 12'd2961: return "xx2961xxxxxxxxx17x"; + 12'd2962: return "xx2962xxxxxxxxx18x"; + 12'd2963: return "xx2963xxxxxxxxx19x"; + 12'd2964: return "xx2964xxxxxxxxx20x"; + 12'd2965: return "xx2965xxxxxxxxx21x"; + 12'd2966: return "xx2966xxxxxxxxx22x"; + 12'd2967: return "xx2967xxxxxxxxx23x"; + 12'd2968: return "xx2968xxxxxxxxx24x"; + 12'd2969: return "xx2969xxxxxxxxx25x"; + 12'd2970: return "xx2970xxxxxxxxx26x"; + 12'd2971: return "xx2971xxxxxxxxx27x"; + 12'd2972: return "xx2972xxxxxxxxx28x"; + 12'd2973: return "xx2973xxxxxxxxx29x"; + 12'd2974: return "xx2974xxxxxxxxx30x"; + 12'd2975: return "xx2975xxxxxxxxx31x"; + 12'd0002: return "xx0002x"; + 12'd3072: return "xx3072xxx"; + 12'd3073: return "xx3073xx"; + 12'd3074: return "xx3074xxxxx"; + 12'd3075: return "xx3075xxxxxxxx3"; + 12'd3076: return "xx3076xxxxxxxx4"; + 12'd3077: return "xx3077xxxxxxxx5"; + 12'd3078: return "xx3078xxxxxxxx6"; + 12'd3079: return "xx3079xxxxxxxx7"; + 12'd3080: return "xx3080xxxxxxxx8"; + 12'd3081: return "xx3081xxxxxxxx9"; + 12'd3082: return "xx3082xxxxxxxx10"; + 12'd3083: return "xx3083xxxxxxxx11"; + 12'd3084: return "xx3084xxxxxxxx12"; + 12'd3085: return "xx3085xxxxxxxx13"; + 12'd3086: return "xx3086xxxxxxxx14"; + 12'd3087: return "xx3087xxxxxxxx15"; + 12'd3088: return "xx3088xxxxxxxx16"; + 12'd3089: return "xx3089xxxxxxxx17"; + 12'd3090: return "xx3090xxxxxxxx18"; + 12'd3091: return "xx3091xxxxxxxx19"; + 12'd3092: return "xx3092xxxxxxxx20"; + 12'd3093: return "xx3093xxxxxxxx21"; + 12'd3094: return "xx3094xxxxxxxx22"; + 12'd3095: return "xx3095xxxxxxxx23"; + 12'd3096: return "xx3096xxxxxxxx24"; + 12'd3097: return "xx3097xxxxxxxx25"; + 12'd3098: return "xx3098xxxxxxxx26"; + 12'd3099: return "xx3099xxxxxxxx27"; + 12'd3100: return "xx3100xxxxxxxx28"; + 12'd3101: return "xx3101xxxxxxxx29"; + 12'd3102: return "xx3102xxxxxxxx30"; + 12'd3103: return "xx3103xxxxxxxx31"; + 12'd3200: return "xx3200xxxx"; + 12'd3201: return "xx3201xxx"; + 12'd3202: return "xx3202xxxxxx"; + 12'd3203: return "xx3203xxxxxxxx3x"; + 12'd3204: return "xx3204xxxxxxxx4x"; + 12'd3205: return "xx3205xxxxxxxx5x"; + 12'd3206: return "xx3206xxxxxxxx6x"; + 12'd3207: return "xx3207xxxxxxxx7x"; + 12'd3208: return "xx3208xxxxxxxx8x"; + 12'd3209: return "xx3209xxxxxxxx9x"; + 12'd0320: return "xx0320xxxxxx"; + 12'd3210: return "xx3210xxxxxxxx10x"; + 12'd3211: return "xx3211xxxxxxxx11x"; + 12'd3212: return "xx3212xxxxxxxx12x"; + 12'd3213: return "xx3213xxxxxxxx13x"; + 12'd3214: return "xx3214xxxxxxxx14x"; + 12'd3215: return "xx3215xxxxxxxx15x"; + 12'd3216: return "xx3216xxxxxxxx16x"; + 12'd3217: return "xx3217xxxxxxxx17x"; + 12'd3218: return "xx3218xxxxxxxx18x"; + 12'd3219: return "xx3219xxxxxxxx19x"; + 12'd3220: return "xx3220xxxxxxxx20x"; + 12'd3221: return "xx3221xxxxxxxx21x"; + 12'd3222: return "xx3222xxxxxxxx22x"; + 12'd3223: return "xx3223xxxxxxxx23x"; + 12'd3224: return "xx3224xxxxxxxx24x"; + 12'd3225: return "xx3225xxxxxxxx25x"; + 12'd3226: return "xx3226xxxxxxxx26x"; + 12'd3227: return "xx3227xxxxxxxx27x"; + 12'd3228: return "xx3228xxxxxxxx28x"; + 12'd3229: return "xx3229xxxxxxxx29x"; + 12'd3230: return "xx3230xxxxxxxx30x"; + 12'd3231: return "xx3231xxxxxxxx31x"; + 12'd3857: return "xx3857xxxxxxx"; + 12'd3858: return "xx3858xxxxx"; + 12'd3859: return "xx3859xxxx"; + 12'd3860: return "xx3860xxxxx"; + 12'd0512: return "xx0512xxxxx"; + 12'd0514: return "xx0514xxxxx"; + 12'd0515: return "xx0515xxxxx"; + 12'd0516: return "xx0516x"; + 12'd0517: return "xx0517xxx"; + 12'd0576: return "xx0576xxxxxx"; + 12'd0577: return "xx0577xx"; + 12'd0578: return "xx0578xxxx"; + 12'd0579: return "xx0579xxxxxx"; + 12'd0580: return "xx0580x"; + 12'd0768: return "xx0768xxxxx"; + 12'd0769: return "xx0769xx"; + 12'd0770: return "xx0770xxxxx"; + 12'd0771: return "xx0771xxxxx"; + 12'd0772: return "xx0772x"; + 12'd0773: return "xx0773xxx"; + 12'd0774: return "xx0774xxxxxxxx"; + 12'd0800: return "xx0800xxxxxxxxxxx"; + 12'd0803: return "xx0803xxxxxxx3"; + 12'd0804: return "xx0804xxxxxxx4"; + 12'd0805: return "xx0805xxxxxxx5"; + 12'd0806: return "xx0806xxxxxxx6"; + 12'd0807: return "xx0807xxxxxxx7"; + 12'd0808: return "xx0808xxxxxxx8"; + 12'd0809: return "xx0809xxxxxxx9"; + 12'd0810: return "xx0810xxxxxxx10"; + 12'd0811: return "xx0811xxxxxxx11"; + 12'd0812: return "xx0812xxxxxxx12"; + 12'd0813: return "xx0813xxxxxxx13"; + 12'd0814: return "xx0814xxxxxxx14"; + 12'd0815: return "xx0815xxxxxxx15"; + 12'd0816: return "xx0816xxxxxxx16"; + 12'd0817: return "xx0817xxxxxxx17"; + 12'd0818: return "xx0818xxxxxxx18"; + 12'd0819: return "xx0819xxxxxxx19"; + 12'd0820: return "xx0820xxxxxxx20"; + 12'd0821: return "xx0821xxxxxxx21"; + 12'd0822: return "xx0822xxxxxxx22"; + 12'd0823: return "xx0823xxxxxxx23"; + 12'd0824: return "xx0824xxxxxxx24"; + 12'd0825: return "xx0825xxxxxxx25"; + 12'd0826: return "xx0826xxxxxxx26"; + 12'd0827: return "xx0827xxxxxxx27"; + 12'd0828: return "xx0828xxxxxxx28"; + 12'd0829: return "xx0829xxxxxxx29"; + 12'd0830: return "xx0830xxxxxxx30"; + 12'd0831: return "xx0831xxxxxxx31"; + 12'd0832: return "xx0832xxxxxx"; + 12'd0833: return "xx0833xx"; + 12'd0834: return "xx0834xxxx"; + 12'd0835: return "xx0835xxx"; + 12'd0836: return "xx0836x"; + 12'd0896: return "xx0896xxx"; + 12'd0897: return "xx0897xxxx"; + 12'd0898: return "xx0898xxxx"; + 12'd0899: return "xx0899xxxxx"; + 12'd0900: return "xx0900xxxx"; + 12'd0901: return "xx0901xxxxx"; + 12'd0928: return "xx0928xxxx0"; + 12'd0929: return "xx0929xxxx1"; + 12'd0930: return "xx0930xxxx2"; + 12'd0931: return "xx0931xxxx3"; + 12'd0944: return "xx0944xxxxx0"; + 12'd0945: return "xx0945xxxxx1"; + 12'd0946: return "xx0946xxxxx2"; + 12'd0947: return "xx0947xxxxx3"; + 12'd0948: return "xx0948xxxxx4"; + 12'd0949: return "xx0949xxxxx5"; + 12'd0950: return "xx0950xxxxx6"; + 12'd0951: return "xx0951xxxxx7"; + 12'd0952: return "xx0952xxxxx8"; + 12'd0953: return "xx0953xxxxx9"; + 12'd0954: return "xx0954xxxxx10"; + 12'd0955: return "xx0955xxxxx11"; + 12'd0956: return "xx0956xxxxx12"; + 12'd0957: return "xx0957xxxxx13"; + 12'd0958: return "xx0958xxxxx14"; + 12'd0959: return "xx0959xxxxx15"; + default: return $sformatf("0x%x", csr_addr); + endcase + endfunction - int i; + int i; - initial begin - if (get_csr_name(12'd0957) != "xx0957xxxxx13") $stop; - if (get_csr_name(12'd2830) != "xx2830xxxxxxxxx14") $stop; + initial begin + if (get_csr_name(12'd0957) != "xx0957xxxxx13") $stop; + if (get_csr_name(12'd2830) != "xx2830xxxxxxxxx14") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_mlog2.v b/test_regress/t/t_func_mlog2.v index 3ee90fc89..d938864b0 100644 --- a/test_regress/t/t_func_mlog2.v +++ b/test_regress/t/t_func_mlog2.v @@ -4,53 +4,56 @@ // SPDX-FileCopyrightText: 2003-2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + clk +); + input clk; - integer cyc; initial cyc=1; - integer sum; - integer cpre; - always @ (posedge clk) begin - if (cyc!=0) begin - cpre = cyc; - cyc <= cyc + 1; - if (cyc==1) begin - if (mlog2(32'd0) != 32'd0) $stop; - if (mlog2(32'd1) != 32'd0) $stop; - if (mlog2(32'd3) != 32'd2) $stop; - sum <= 32'd0; - end - else if (cyc<90) begin - // (cyc) so if we trash the variable things will get upset. - sum <= mlog2(cyc) + sum * 32'd42; - if (cpre != cyc) $stop; - end - else if (cyc==90) begin - if (sum !== 32'h0f12bb51) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + integer sum; + integer cpre; + always @(posedge clk) begin + if (cyc != 0) begin + cpre = cyc; + cyc <= cyc + 1; + if (cyc == 1) begin + if (mlog2(32'd0) != 32'd0) $stop; + if (mlog2(32'd1) != 32'd0) $stop; + if (mlog2(32'd3) != 32'd2) $stop; + sum <= 32'd0; end - end + else if (cyc < 90) begin + // (cyc) so if we trash the variable things will get upset. + sum <= mlog2(cyc) + sum * 32'd42; + if (cpre != cyc) $stop; + end + else if (cyc == 90) begin + if (sum !== 32'h0f12bb51) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - function integer mlog2; - input [31:0] value; - integer i; - begin - if(value < 32'd1) begin - mlog2 = 0; - end - else begin - value = value - 32'd1; - mlog2 = 0; - for(i=0;i<32;i=i+1) begin - if(value > 32'd0) begin - mlog2 = mlog2 + 1; - end - value = value >> 1; - end - end + function integer mlog2; + input [31:0] value; + integer i; + begin + if (value < 32'd1) begin + mlog2 = 0; end - endfunction + else begin + value = value - 32'd1; + mlog2 = 0; + for (i = 0; i < 32; i = i + 1) begin + if (value > 32'd0) begin + mlog2 = mlog2 + 1; + end + value = value >> 1; + end + end + end + endfunction endmodule diff --git a/test_regress/t/t_func_modify_input.v b/test_regress/t/t_func_modify_input.v index 5a7bbadd6..7739c749d 100644 --- a/test_regress/t/t_func_modify_input.v +++ b/test_regress/t/t_func_modify_input.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 class foo; - function void g(input integer x); - f(x); - endfunction - function void f(inout integer x); - endfunction + function void g(input integer x); + f(x); + endfunction + function void f(inout integer x); + endfunction endclass diff --git a/test_regress/t/t_func_named.v b/test_regress/t/t_func_named.v index 11c41bb7f..46a72bc6c 100644 --- a/test_regress/t/t_func_named.v +++ b/test_regress/t/t_func_named.v @@ -4,27 +4,31 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - function automatic int f( int j = 1, int s = 0 ); - return (j<<16) | s; - endfunction + function automatic int f( int j = 1, int s = 0 ); + return (j<<16) | s; + endfunction - initial begin - `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); - `checkh( f(.s(1)) , 32'h1_0001 ); - `checkh( f(, 1) , 32'h1_0001 ); - `checkh( f(.j(2)) , 32'h2_0000 ); - `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); - `checkh( f(.s(), .j()) , 32'h1_0000 ); - `checkh( f(2) , 32'h2_0000 ); - `checkh( f() , 32'h1_0000 ); + initial begin + // verilog_format: off + `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); + `checkh( f(.s(1)) , 32'h1_0001 ); + `checkh( f(, 1) , 32'h1_0001 ); + `checkh( f(.j(2)) , 32'h2_0000 ); + `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); + `checkh( f(.s(), .j()) , 32'h1_0000 ); + `checkh( f(2) , 32'h2_0000 ); + `checkh( f() , 32'h1_0000 ); + // verilog_format: on - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_no_lifetime_bad.out b/test_regress/t/t_func_no_lifetime_bad.out index 5bf7797db..42b35c641 100644 --- a/test_regress/t/t_func_no_lifetime_bad.out +++ b/test_regress/t/t_func_no_lifetime_bad.out @@ -1,29 +1,29 @@ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:16: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) : ... Suggest use 'function automatic' or 'function static' - 26 | function int f_implicit_static(); - | ^~~~~~~~~~~~~~~~~ - t/t_func_no_lifetime_bad.v:27:11: ... Location of implicit static variable - : ... The initializer value will only be set once - 27 | int cnt = 0; - | ^~~ + 26 | function int f_implicit_static(); + | ^~~~~~~~~~~~~~~~~ + t/t_func_no_lifetime_bad.v:27:9: ... Location of implicit static variable + : ... The initializer value will only be set once + 27 | int cnt = 0; + | ^~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:8: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) : ... Suggest use 'task automatic' or 'task static' - 31 | task t_implicit_static(); - | ^~~~~~~~~~~~~~~~~ - t/t_func_no_lifetime_bad.v:32:11: ... Location of implicit static variable - : ... The initializer value will only be set once - 32 | int cnt = 0; - | ^~~ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) + 31 | task t_implicit_static(); + | ^~~~~~~~~~~~~~~~~ + t/t_func_no_lifetime_bad.v:32:9: ... Location of implicit static variable + : ... The initializer value will only be set once + 32 | int cnt = 0; + | ^~~ +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:7: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' - 9 | int cnt = 0; - | ^~~ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:8: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) + 9 | int cnt = 0; + | ^~~ +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:7: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' - 15 | int cnt = 0; - | ^~~ + 15 | int cnt = 0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_no_lifetime_bad.v b/test_regress/t/t_func_no_lifetime_bad.v index bd1f74be1..3e533371d 100644 --- a/test_regress/t/t_func_no_lifetime_bad.v +++ b/test_regress/t/t_func_no_lifetime_bad.v @@ -6,49 +6,49 @@ // Not legal to put "static" here, so no warning function int f_dunit_static(); - int cnt = 0; // Ok to require "static" here somehday - return ++cnt; + int cnt = 0; // Ok to require "static" here somehday + return ++cnt; endfunction // Not legal to put "static" here, so no warning task t_dunit_static(); - int cnt = 0; // Ok to require "static" here somehday - $display("%d", ++cnt); + int cnt = 0; // Ok to require "static" here somehday + $display("%d", ++cnt); endtask task t_dunit_static_ok(input int in_ok = 1); - static int cnt_ok = 0; // No warning here - $display("%d", ++cnt_ok); + static int cnt_ok = 0; // No warning here + $display("%d", ++cnt_ok); endtask module t; - function int f_implicit_static(); - int cnt = 0; - return ++cnt; - endfunction + function int f_implicit_static(); + int cnt = 0; + return ++cnt; + endfunction - task t_implicit_static(); - int cnt = 0; - $display("%d", ++cnt); - endtask + task t_implicit_static(); + int cnt = 0; + $display("%d", ++cnt); + endtask - // verilator lint_off IMPLICITSTATIC - function int f_implicit_but_lint_off(); - int cnt = 0; - return ++cnt; - endfunction + // verilator lint_off IMPLICITSTATIC + function int f_implicit_but_lint_off(); + int cnt = 0; + return ++cnt; + endfunction - int a, b; - initial begin - a = f_dunit_static(); - t_dunit_static(); - t_dunit_static_ok(); + int a, b; + initial begin + a = f_dunit_static(); + t_dunit_static(); + t_dunit_static_ok(); - a = f_implicit_static(); - t_implicit_static(); - b = f_implicit_but_lint_off(); - $stop; - end + a = f_implicit_static(); + t_implicit_static(); + b = f_implicit_but_lint_off(); + $stop; + end endmodule diff --git a/test_regress/t/t_func_no_parentheses_bad.out b/test_regress/t/t_func_no_parentheses_bad.out index 96df8cc0c..a8328b2de 100644 --- a/test_regress/t/t_func_no_parentheses_bad.out +++ b/test_regress/t/t_func_no_parentheses_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_func_no_parentheses_bad.v:16:11: Found definition of 'func' as a FUNC but expected a variable - 16 | a = func; - | ^~~~ +%Error: t/t_func_no_parentheses_bad.v:16:9: Found definition of 'func' as a FUNC but expected a variable + 16 | a = func; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_no_parentheses_bad.v b/test_regress/t/t_func_no_parentheses_bad.v index 80c20f2a8..68e9dbde8 100644 --- a/test_regress/t/t_func_no_parentheses_bad.v +++ b/test_regress/t/t_func_no_parentheses_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 function static int func(); - int cnt = 0; - return ++cnt; + int cnt = 0; + return ++cnt; endfunction module t; - int a; - initial begin - a = func; - $stop; - end + int a; + initial begin + a = func; + $stop; + end endmodule diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v index 62d2ff7fb..5d1f1ee53 100644 --- a/test_regress/t/t_func_noinl.v +++ b/test_regress/t/t_func_noinl.v @@ -4,113 +4,114 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [31:0] inp = crc[31:0]; - wire reset = (cyc < 5); + wire [31:0] inp = crc[31:0]; + wire reset = (cyc < 5); - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] outp; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] outp; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .outp (outp[31:0]), - // Inputs - .reset (reset), - .clk (clk), - .inp (inp[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .outp(outp[31:0]), + // Inputs + .reset(reset), + .clk(clk), + .inp(inp[31:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, outp}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, outp}; - // What checksum will we end up with -`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb + // What checksum will we end up with + `define EXPECTED_SUM 64'ha7f0a34f9cf56ccb - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - outp, - // Inputs - reset, clk, inp - ); +module Test ( /*AUTOARG*/ + // Outputs + outp, + // Inputs + reset, + clk, + inp +); - input reset; - input clk; - input [31:0] inp; - output [31:0] outp; + input reset; + input clk; + input [31:0] inp; + output [31:0] outp; - function automatic [31:0] no_inline_function; - input [31:0] var1; - input [31:0] var2; - /*verilator no_inline_task*/ - reg [31*2:0] product1 ; - reg [31*2:0] product2 ; - integer i; - reg [31:0] tmp; + function automatic [31:0] no_inline_function; + input [31:0] var1; + input [31:0] var2; + /*verilator no_inline_task*/ + reg [31*2:0] product1; + reg [31*2:0] product2; + integer i; + reg [31:0] tmp; - begin - product2 = {(31*2+1){1'b0}}; + begin + product2 = {(31 * 2 + 1) {1'b0}}; - for (i = 0; i < 32; i = i + 1) - if (var2[i]) begin - product1 = { {31*2+1-32{1'b0}}, var1} << i; - product2 = product2 ^ product1; - end - no_inline_function = 0; - - for (i= 0; i < 31; i = i + 1 ) - no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; + for (i = 0; i < 32; i = i + 1) + if (var2[i]) begin + product1 = {{31 * 2 + 1 - 32{1'b0}}, var1} << i; + product2 = product2 ^ product1; end - endfunction + no_inline_function = 0; - reg [31:0] outp; - reg [31:0] inp_d; + for (i = 0; i < 31; i = i + 1) + no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; + end + endfunction - always @( posedge clk ) begin - if( reset ) begin - outp <= 0; - end - else begin - inp_d <= inp; - outp <= no_inline_function(inp, inp_d); - end - end + reg [31:0] outp; + reg [31:0] inp_d; + + always @(posedge clk) begin + if (reset) begin + outp <= 0; + end + else begin + inp_d <= inp; + outp <= no_inline_function(inp, inp_d); + end + end endmodule diff --git a/test_regress/t/t_func_numones.v b/test_regress/t/t_func_numones.v index 4de7ae579..2b5ed4871 100644 --- a/test_regress/t/t_func_numones.v +++ b/test_regress/t/t_func_numones.v @@ -4,47 +4,48 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); + reg [31:0] r32; + wire [3:0] w4; + wire [4:0] w5; - reg [31:0] r32; - wire [3:0] w4; - wire [4:0] w5; + assign w4 = NUMONES_8(r32[7:0]); + assign w5 = NUMONES_16(r32[15:0]); - assign w4 = NUMONES_8 ( r32[7:0] ); - assign w5 = NUMONES_16( r32[15:0] ); + function [3:0] NUMONES_8; + input [7:0] i8; + reg [7:0] i8; + begin + NUMONES_8 = 4'b1; + end + endfunction // NUMONES_8 - function [3:0] NUMONES_8; - input [7:0] i8; - reg [7:0] i8; - begin - NUMONES_8 = 4'b1; + function [4:0] NUMONES_16; + input [15:0] i16; + reg [15:0] i16; + begin + NUMONES_16 = (NUMONES_8(i16[7:0]) + NUMONES_8(i16[15:8])); + end + endfunction + + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + r32 <= 32'h12345678; end - endfunction // NUMONES_8 - - function [4:0] NUMONES_16; - input [15:0] i16; - reg [15:0] i16; - begin - NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] )); + if (cyc == 2) begin + if (w4 !== 1) $stop; + if (w5 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - endfunction - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - r32 <= 32'h12345678; - end - if (cyc==2) begin - if (w4 !== 1) $stop; - if (w5 !== 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - end + end + end endmodule diff --git a/test_regress/t/t_func_outfirst.v b/test_regress/t/t_func_outfirst.v index 366217711..610decc8b 100644 --- a/test_regress/t/t_func_outfirst.v +++ b/test_regress/t/t_func_outfirst.v @@ -10,107 +10,107 @@ `define MAX_AOA `AOA_BITS'd255 `define BURP_DIVIDER 9'd16 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; - wire reset = (cyc<7); + // Take CRC data and apply to testblock inputs + wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; + wire reset = (cyc < 7); - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .AOA_B (AOA_B[`AOA_BITS-1:0]), - // Inputs - .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), - .reset (reset), - .clk (clk)); + Test test ( /*AUTOINST*/ + // Outputs + .AOA_B(AOA_B[`AOA_BITS-1:0]), + // Inputs + .DDIFF_B(DDIFF_B[`DDIFF_BITS-1:0]), + .reset(reset), + .clk(clk) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {56'h0, AOA_B}; + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, AOA_B}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h3a74e9d34771ad93 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h3a74e9d34771ad93 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - AOA_B, - // Inputs - DDIFF_B, reset, clk - ); +module Test ( /*AUTOARG*/ + // Outputs + AOA_B, + // Inputs + DDIFF_B, + reset, + clk +); - input [`DDIFF_BITS-1:0] DDIFF_B; - input reset; - input clk; - output reg [`AOA_BITS-1:0] AOA_B; + input [`DDIFF_BITS-1:0] DDIFF_B; + input reset; + input clk; + output reg [`AOA_BITS-1:0] AOA_B; - reg [`AOA_BITS-1:0] AOA_NEXT_B; - reg [`AOA_BITS-1:0] tmp; + reg [`AOA_BITS-1:0] AOA_NEXT_B; + reg [`AOA_BITS-1:0] tmp; - always @(posedge clk) begin - if (reset) begin - AOA_B <= 8'h80; - end - else begin - AOA_B <= AOA_NEXT_B; - end - end + always @(posedge clk) begin + if (reset) begin + AOA_B <= 8'h80; + end + else begin + AOA_B <= AOA_NEXT_B; + end + end - always @* begin - // verilator lint_off WIDTH - tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); - t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); - // verilator lint_on WIDTH - end + always @* begin + // verilator lint_off WIDTH + tmp = ((`HALF_DDIFF - DDIFF_B) / `BURP_DIVIDER); + t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF - DDIFF_B) / `BURP_DIVIDER)); + // verilator lint_on WIDTH + end - task t_aoa_update; - output [`AOA_BITS-1:0] aoa_reg_next; - input [`AOA_BITS-1:0] aoa_reg; - input [`AOA_BITS-1:0] aoa_delta_update; - begin - if ((`MAX_AOA-aoa_reg)0; log2=log2+1) - arg = (arg >> 1); - end - endfunction + function integer log2(input integer arg); + begin + for (log2 = 0; arg > 0; log2 = log2 + 1) arg = (arg >> 1); + end + endfunction - always @ (posedge clk or negedge rst_n) - if (!rst_n) begin - pos1 <= 0; - pos2 <= 0; - end - else begin - pos1 <= pos1 + 1; - pos2 <= pos2 + 1; - end + always @(posedge clk or negedge rst_n) + if (!rst_n) begin + pos1 <= 0; + pos2 <= 0; + end + else begin + pos1 <= pos1 + 1; + pos2 <= pos2 + 1; + end endmodule diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index ad2aa7882..059126c6f 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -4,233 +4,244 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - tpub p1 (.clk(clk), .i(32'd1)); - tpub p2 (.clk(clk), .i(32'd2)); + tpub p1 ( + .clk(clk), + .i(32'd1) + ); + tpub p2 ( + .clk(clk), + .i(32'd2) + ); - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin `ifdef verilator - $c("this->publicTop();"); + $c("this->publicTop();"); `endif - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - task publicTop; - // verilator public - // We have different optimizations if only one of something, so try it out. - $write("Hello in publicTop\n"); - endtask + task publicTop; + // verilator public + // We have different optimizations if only one of something, so try it out. + $write("Hello in publicTop\n"); + endtask - task test_task(input [19:0] in [2], output [19:0] out [2]); - // Issue 3316 - // verilator public - out[0] = in[1]; - out[1] = in[0]; - endtask + task test_task(input [19:0] in[2], output [19:0] out[2]); + // Issue 3316 + // verilator public + out[0] = in[1]; + out[1] = in[0]; + endtask endmodule module tpub ( - input clk, - input [31:0] i); + input clk, + input [31:0] i +); - reg [23:0] var_long; - reg [59:0] var_quad; - reg [71:0] var_wide; - reg var_bool; + reg [23:0] var_long; + reg [59:0] var_quad; + reg [71:0] var_wide; + reg var_bool; - // verilator lint_off BLKANDNBLK - reg [11:0] var_flop; - // verilator lint_on BLKANDNBLK + // verilator lint_off BLKANDNBLK + reg [11:0] var_flop; + // verilator lint_on BLKANDNBLK - reg [23:0] got_long /*verilator public*/; - reg [59:0] got_quad /*verilator public*/; - reg [71:0] got_wide /*verilator public*/; - reg got_bool /*verilator public*/; + reg [23:0] got_long /*verilator public*/; + reg [59:0] got_quad /*verilator public*/; + reg [71:0] got_wide /*verilator public*/; + reg got_bool /*verilator public*/; - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - // cyc==1 is in top level - if (cyc==2) begin - publicNoArgs; - publicSetBool(1'b1); - publicSetLong(24'habca); - publicSetQuad(60'h4444_3333_2222); - publicSetWide(72'h12_5678_9123_1245_2352); - var_flop <= 12'habe; - end - if (cyc==3) begin - if (1'b1 != publicGetSetBool(1'b0)) $stop; - if (24'habca != publicGetSetLong(24'h1234)) $stop; - if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; - if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; - end - if (cyc==4) begin - publicGetBool(got_bool); - if (1'b0 != got_bool) $stop; - publicGetLong(got_long); - if (24'h1234 != got_long) $stop; - publicGetQuad(got_quad); - if (60'h123_4567_89ab != got_quad) $stop; - publicGetWide(got_wide); - if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; - end - // + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + // cyc==1 is in top level + if (cyc == 2) begin + publicNoArgs; + publicSetBool(1'b1); + publicSetLong(24'habca); + publicSetQuad(60'h4444_3333_2222); + publicSetWide(72'h12_5678_9123_1245_2352); + var_flop <= 12'habe; + end + if (cyc == 3) begin + if (1'b1 != publicGetSetBool(1'b0)) $stop; + if (24'habca != publicGetSetLong(24'h1234)) $stop; + if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; + if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; + end + if (cyc == 4) begin + publicGetBool(got_bool); + if (1'b0 != got_bool) $stop; + publicGetLong(got_long); + if (24'h1234 != got_long) $stop; + publicGetQuad(got_quad); + if (60'h123_4567_89ab != got_quad) $stop; + publicGetWide(got_wide); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + end + // `ifdef VERILATOR_PUBLIC_TASKS - if (cyc==11) begin - $c("this->publicNoArgs();"); - $c("this->publicSetBool(true);"); - $c("this->publicSetLong(0x11bca);"); - $c("this->publicSetQuad(0x66655554444ULL);"); - $c("this->publicSetFlop(0x321);"); - //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); - end - if (cyc==12) begin - $c("this->got_bool = this->publicGetSetBool(true);"); - $c("this->got_long = this->publicGetSetLong(0x11bca);"); - $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); - end - if (cyc==13) begin - $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); - if (1'b1 != got_bool) $stop; - $c("this->publicGetLong(this->got_long);"); - if (24'h11bca != got_long) $stop; - $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); - if (60'haaaa_bbbb_cccc != got_quad) $stop; - $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); - if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; - //Below doesn't work, because we're calling it inside the loop that sets var_flop - // if (12'h321 != var_flop) $stop; - end - if (cyc==14) begin - if ($c32("this->publicInstNum()") != i) $stop; - end + if (cyc == 11) begin + $c("this->publicNoArgs();"); + $c("this->publicSetBool(true);"); + $c("this->publicSetLong(0x11bca);"); + $c("this->publicSetQuad(0x66655554444ULL);"); + $c("this->publicSetFlop(0x321);"); + //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); + end + if (cyc == 12) begin + $c("this->got_bool = this->publicGetSetBool(true);"); + $c("this->got_long = this->publicGetSetLong(0x11bca);"); + $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); + end + if (cyc == 13) begin + $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); + if (1'b1 != got_bool) $stop; + $c("this->publicGetLong(this->got_long);"); + if (24'h11bca != got_long) $stop; + $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); + if (60'haaaa_bbbb_cccc != got_quad) $stop; + $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + //Below doesn't work, because we're calling it inside the loop that sets var_flop + // if (12'h321 != var_flop) $stop; + end + if (cyc == 14) begin + if ($c32("this->publicInstNum()") != i) $stop; + end `endif - end - end + end + end - task publicEmpty; - // verilator public - begin end - endtask + task publicEmpty; + // verilator public + begin + end + endtask - task publicNoArgs; - // verilator public - $write("Hello in publicNoArgs\n"); - endtask + task publicNoArgs; + // verilator public + $write("Hello in publicNoArgs\n"); + endtask - task publicSetBool; - // verilator public - input in_bool; + task publicSetBool; + // verilator public + input in_bool; + var_bool = in_bool; + endtask + + task publicSetLong; + // verilator public + input [23:0] in_long; + reg [23:0] not_long; + begin + not_long = ~in_long; // Test that we can have local variables + var_long = ~not_long; + end + endtask + + task publicSetQuad; + // verilator public + input [59:0] in_quad; + var_quad = in_quad; + endtask + + task publicSetFlop; + // verilator public + input [11:0] in_flop; + var_flop = in_flop; + endtask + + task publicSetWide; + // verilator public + input [71:0] in_wide; + var_wide = in_wide; + endtask + + task publicGetBool; + // verilator public + output out_bool; + out_bool = var_bool; + endtask + + task publicGetLong; + // verilator public + output [23:0] out_long; + out_long = var_long; + endtask + + task publicGetQuad; + // verilator public + output [59:0] out_quad; + out_quad = var_quad; + endtask + + task publicGetWide; + // verilator public + output [71:0] out_wide; + out_wide = var_wide; + endtask + + function publicGetSetBool; + // verilator public + input in_bool; + begin + publicGetSetBool = var_bool; var_bool = in_bool; - endtask + end + endfunction - task publicSetLong; - // verilator public - input [23:0] in_long; - reg [23:0] not_long; - begin - not_long = ~in_long; // Test that we can have local variables - var_long = ~not_long; - end - endtask + function [23:0] publicGetSetLong; + // verilator public + input [23:0] in_long; + begin + publicGetSetLong = var_long; + var_long = in_long; + end + endfunction - task publicSetQuad; - // verilator public - input [59:0] in_quad; + function [59:0] publicGetSetQuad; + // verilator public + input [59:0] in_quad; + begin + publicGetSetQuad = var_quad; var_quad = in_quad; - endtask + end + endfunction - task publicSetFlop; - // verilator public - input [11:0] in_flop; - var_flop = in_flop; - endtask - - task publicSetWide; - // verilator public - input [71:0] in_wide; + function [71:0] publicGetSetWide; + // Can't be public, as no wide return types in C++ + input [71:0] in_wide; + begin + publicGetSetWide = var_wide; var_wide = in_wide; - endtask - - task publicGetBool; - // verilator public - output out_bool; - out_bool = var_bool; - endtask - - task publicGetLong; - // verilator public - output [23:0] out_long; - out_long = var_long; - endtask - - task publicGetQuad; - // verilator public - output [59:0] out_quad; - out_quad = var_quad; - endtask - - task publicGetWide; - // verilator public - output [71:0] out_wide; - out_wide = var_wide; - endtask - - function publicGetSetBool; - // verilator public - input in_bool; - begin - publicGetSetBool = var_bool; - var_bool = in_bool; - end - endfunction - - function [23:0] publicGetSetLong; - // verilator public - input [23:0] in_long; - begin - publicGetSetLong = var_long; - var_long = in_long; - end - endfunction - - function [59:0] publicGetSetQuad; - // verilator public - input [59:0] in_quad; - begin - publicGetSetQuad = var_quad; - var_quad = in_quad; - end - endfunction - - function [71:0] publicGetSetWide; - // Can't be public, as no wide return types in C++ - input [71:0] in_wide; - begin - publicGetSetWide = var_wide; - var_wide = in_wide; - end - endfunction + end + endfunction `ifdef VERILATOR_PUBLIC_TASKS - function [31:0] publicInstNum; - // verilator public - publicInstNum = i; - endfunction + function [31:0] publicInstNum; + // verilator public + publicInstNum = i; + endfunction `endif endmodule diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v index bb3c7d5eb..a58525f3c 100644 --- a/test_regress/t/t_func_rand.v +++ b/test_regress/t/t_func_rand.v @@ -5,29 +5,29 @@ // SPDX-License-Identifier: CC0-1.0 module t (clk, Rand); - input clk; - output reg [31:0] Rand; + input clk; + output reg [31:0] Rand; `ifdef verilator - `systemc_interface - unsigned int QxRandTbl (unsigned int tbl, unsigned int idx) { return 0xfeed0fad; } - `verilog + `systemc_interface + unsigned int QxRandTbl (unsigned int tbl, unsigned int idx) { return 0xfeed0fad; } + `verilog `endif - function [31:0] QxRand32; - /* verilator public */ - input [7:0] tbl; - input [7:0] idx; - begin + function [31:0] QxRand32; + /* verilator public */ + input [7:0] tbl; + input [7:0] idx; + begin `ifdef verilator - QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")"); + QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")"); `else - QxRand32 = 32'hfeed0fad; + QxRand32 = 32'hfeed0fad; `endif - end - endfunction + end + endfunction - always @(posedge clk) begin - Rand <= #1 QxRand32 (8'h0, 8'h7); - end + always @(posedge clk) begin + Rand <= #1 QxRand32 (8'h0, 8'h7); + end endmodule diff --git a/test_regress/t/t_func_range.v b/test_regress/t/t_func_range.v index e618c09a8..4cffcffe5 100644 --- a/test_regress/t/t_func_range.v +++ b/test_regress/t/t_func_range.v @@ -4,61 +4,63 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - // verilator lint_off WIDTH + // verilator lint_off WIDTH -`define INT_RANGE 31:0 -`define INT_RANGE_MAX 31 -`define VECTOR_RANGE 63:0 + `define INT_RANGE 31:0 + `define INT_RANGE_MAX 31 + `define VECTOR_RANGE 63:0 - reg [`INT_RANGE] stashb, stasha, stashn, stashm; + reg [`INT_RANGE] stashb, stasha, stashn, stashm; - function [`VECTOR_RANGE] copy_range; - input [`VECTOR_RANGE] y; - input [`INT_RANGE] b; - input [`INT_RANGE] a; + function [`VECTOR_RANGE] copy_range; + input [`VECTOR_RANGE] y; + input [`INT_RANGE] b; + input [`INT_RANGE] a; - input [`VECTOR_RANGE] x; - input [`INT_RANGE] n; - input [`INT_RANGE] m; + input [`VECTOR_RANGE] x; + input [`INT_RANGE] n; + input [`INT_RANGE] m; - begin - copy_range = y; - stashb = b; - stasha = a; - stashn = n; - stashm = m; + begin + copy_range = y; + stashb = b; + stasha = a; + stashn = n; + stashm = m; + end + endfunction + + parameter DATA_SIZE = 16; + parameter NUM_OF_REGS = 32; + + reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; + reg [DATA_SIZE-1:0] memread_rf_reg; + always @(memread_rf) begin : memread_convert + memread_rf_reg = copy_range('d0, DATA_SIZE - 'd1, DATA_SIZE - 'd1, memread_rf, DATA_SIZE - 'd1, + DATA_SIZE - 'd1); + end + + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + memread_rf = 512'haa; end - endfunction - - parameter DATA_SIZE = 16; - parameter NUM_OF_REGS = 32; - - reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; - reg [DATA_SIZE-1:0] memread_rf_reg; - always @(memread_rf) begin : memread_convert - memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, - DATA_SIZE-'d1, DATA_SIZE-'d1); - end - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - memread_rf = 512'haa; - end - if (cyc==3) begin - if (stashb != 'd15) $stop; - if (stasha != 'd15) $stop; - if (stashn != 'd15) $stop; - if (stashm != 'd15) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 3) begin + if (stashb != 'd15) $stop; + if (stasha != 'd15) $stop; + if (stashn != 'd15) $stop; + if (stashm != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_func_real_abs.v b/test_regress/t/t_func_real_abs.v index bc13a7451..0e41e240e 100644 --- a/test_regress/t/t_func_real_abs.v +++ b/test_regress/t/t_func_real_abs.v @@ -8,43 +8,42 @@ module t; - function real ABS (real num); - ABS = (num < 0) ? -num : num; - endfunction + function real ABS(real num); + ABS = (num < 0) ? -num : num; + endfunction - function logic range_chk; - input real last; - input real period; - input real cmp; - range_chk = 0; - if ( last >= 0 ) begin - if ( ABS(last - period) > cmp ) begin - range_chk = 1; - end + function logic range_chk; + input real last; + input real period; + input real cmp; + range_chk = 0; + if (last >= 0) begin + if (ABS(last - period) > cmp) begin + range_chk = 1; end - endfunction + end + endfunction - function integer ceil; - input num; - real num; - if (num > $rtoi(num)) - ceil = $rtoi(num) + 1; - else - // verilator lint_off REALCVT - ceil = num; - // verilator lint_on REALCVT - endfunction + function integer ceil; + input num; + real num; + if (num > $rtoi(num)) ceil = $rtoi(num) + 1; + else + // verilator lint_off REALCVT + ceil = num; + // verilator lint_on REALCVT + endfunction - initial begin - if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop; - if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop; - if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop; - if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop; - if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop; - if (ceil(-2.1) != -2) $stop; - if (ceil(2.1) != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop; + if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop; + if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop; + if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop; + if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop; + if (ceil(-2.1) != -2) $stop; + if (ceil(2.1) != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_real_exprstmt.v b/test_regress/t/t_func_real_exprstmt.v index a8a0d93a1..9c8fb7594 100644 --- a/test_regress/t/t_func_real_exprstmt.v +++ b/test_regress/t/t_func_real_exprstmt.v @@ -6,18 +6,18 @@ module t; - function automatic real logWrapper(real x); - return $ln(x); - endfunction + function automatic real logWrapper(real x); + return $ln(x); + endfunction - initial begin - // See bug4543 - $display("bad x=%f, y=%f", logWrapper(10.0), 1.0 * logWrapper(10.0)); - $display("noc x=%f, y=%f", $ln(10.0), 1.0 * $ln(10.0)); - if (logWrapper(10.0) != $ln(10.0)) $stop; - if (logWrapper(10.0) != 1.0 * logWrapper(10.0)) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // See bug4543 + $display("bad x=%f, y=%f", logWrapper(10.0), 1.0 * logWrapper(10.0)); + $display("noc x=%f, y=%f", $ln(10.0), 1.0 * $ln(10.0)); + if (logWrapper(10.0) != $ln(10.0)) $stop; + if (logWrapper(10.0) != 1.0 * logWrapper(10.0)) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index 60dcd09c6..8ea0fb2c9 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -8,21 +8,21 @@ module t; - function real get_real_one; - input ignored; - get_real_one = 1.1; - endfunction + function real get_real_one; + input ignored; + get_real_one = 1.1; + endfunction - localparam R_PARAM = get_real_one(1'b0); - localparam R_PARAM_2 = (R_PARAM > 0); + localparam R_PARAM = get_real_one(1'b0); + localparam R_PARAM_2 = (R_PARAM > 0); - generate - initial begin - if (R_PARAM != 1.1) $stop; - if (R_PARAM_2 != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - endgenerate + generate + initial begin + if (R_PARAM != 1.1) $stop; + if (R_PARAM_2 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + endgenerate endmodule diff --git a/test_regress/t/t_func_recurse.v b/test_regress/t/t_func_recurse.v index 9aca61ca2..4e09beaa1 100644 --- a/test_regress/t/t_func_recurse.v +++ b/test_regress/t/t_func_recurse.v @@ -6,17 +6,17 @@ module t; - function automatic int recurse_self; - input int i; - if (i == 0) recurse_self = 0; - else recurse_self = i + recurse_self(i - 1) * 2; - endfunction + function automatic int recurse_self; + input int i; + if (i == 0) recurse_self = 0; + else recurse_self = i + recurse_self(i - 1) * 2; + endfunction - initial begin - if (recurse_self(0) != 0) $stop; - if (recurse_self(3) != (3 + 2*(2 + 2*(1)))) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (recurse_self(0) != 0) $stop; + if (recurse_self(3) != (3 + 2 * (2 + 2 * (1)))) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_recurse2.v b/test_regress/t/t_func_recurse2.v index bf003b5a2..728b2ed2c 100644 --- a/test_regress/t/t_func_recurse2.v +++ b/test_regress/t/t_func_recurse2.v @@ -6,22 +6,22 @@ module t; - function automatic int recurse_1; - input int i; - if (i == 0) recurse_1 = 0; - else recurse_1 = i + recurse_2(i); - endfunction + function automatic int recurse_1; + input int i; + if (i == 0) recurse_1 = 0; + else recurse_1 = i + recurse_2(i); + endfunction - function automatic int recurse_2; - input int i; - return recurse_1(i - 1) * 2; - endfunction + function automatic int recurse_2; + input int i; + return recurse_1(i - 1) * 2; + endfunction - initial begin - if (recurse_1(0) != 0) $stop; - if (recurse_1(3) != (3 + 2*(2 + 2*(1)))) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (recurse_1(0) != 0) $stop; + if (recurse_1(3) != (3 + 2 * (2 + 2 * (1)))) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_redef.v b/test_regress/t/t_func_redef.v index b26be4e64..d80248cc2 100644 --- a/test_regress/t/t_func_redef.v +++ b/test_regress/t/t_func_redef.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 function automatic integer min(input integer a, input integer b); - return (a < b) ? a : b; + return (a < b) ? a : b; endfunction -module t - #(parameter A=16, parameter B=8) - (/*AUTOARG*/ - // Outputs - c, - // Inputs - a, b - ); +module t #( + parameter A = 16, + parameter B = 8 +) ( /*AUTOARG*/ + // Outputs + c, + // Inputs + a, + b +); - input [A-1:0] a; - input [B-1:0] b; - output logic [min(A,B)-1:0] c; + input [A-1:0] a; + input [B-1:0] b; + output logic [min(A,B)-1:0] c; - always_comb - for (int i = 0; i < min(A,B); i++) - assign c[i] = a[i] | b[i]; + always_comb for (int i = 0; i < min(A, B); i++) assign c[i] = a[i] | b[i]; endmodule diff --git a/test_regress/t/t_func_ref.v b/test_regress/t/t_func_ref.v index d142afe12..a0ae3bbb9 100644 --- a/test_regress/t/t_func_ref.v +++ b/test_regress/t/t_func_ref.v @@ -4,57 +4,59 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class MyInt; - int x; - function new(int a); - x = a; - endfunction + int x; + function new(int a); + x = a; + endfunction endclass function int get_val_set_5(ref int x); - automatic int y = x; - x = 5; - return y; + automatic int y = x; + x = 5; + return y; endfunction module t; - int b; - int arr[1]; - MyInt mi; + int b; + int arr[1]; + MyInt mi; - task update_inout(inout int flag, input bit upflag); - flag = upflag ? 1 + flag : flag; - endtask - task update_ref(ref int flag, input bit upflag); - flag = upflag ? 1 + flag : flag; - endtask + task update_inout(inout int flag, input bit upflag); + flag = upflag ? 1 + flag : flag; + endtask + task update_ref(ref int flag, input bit upflag); + flag = upflag ? 1 + flag : flag; + endtask - int my_flag; + int my_flag; - initial begin - mi = new(1); - b = get_val_set_5(mi.x); - `checkh(mi.x, 5); - `checkh(b, 1); + initial begin + mi = new(1); + b = get_val_set_5(mi.x); + `checkh(mi.x, 5); + `checkh(b, 1); - arr[0] = 10; - b = get_val_set_5(arr[0]); - `checkh(arr[0], 5); - `checkh(b, 10); + arr[0] = 10; + b = get_val_set_5(arr[0]); + `checkh(arr[0], 5); + `checkh(b, 10); - update_ref(my_flag, 1); - if (my_flag !== 1) $stop; - update_ref(my_flag, 0); - if (my_flag !== 1) $stop; - update_inout(my_flag, 1); - if (my_flag !== 2) $stop; - update_inout(my_flag, 0); - if (my_flag !== 2) $stop; + update_ref(my_flag, 1); + if (my_flag !== 1) $stop; + update_ref(my_flag, 0); + if (my_flag !== 1) $stop; + update_inout(my_flag, 1); + if (my_flag !== 2) $stop; + update_inout(my_flag, 0); + if (my_flag !== 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_ref_arg.v b/test_regress/t/t_func_ref_arg.v index 29abf15fb..a3c68d4ea 100644 --- a/test_regress/t/t_func_ref_arg.v +++ b/test_regress/t/t_func_ref_arg.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class MyInt; int x; diff --git a/test_regress/t/t_func_ref_bad.out b/test_regress/t/t_func_ref_bad.out index c5ec9fe9d..1378c4e38 100644 --- a/test_regress/t/t_func_ref_bad.out +++ b/test_regress/t/t_func_ref_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_func_ref_bad.v:19:22: Function/task ref argument is not of allowed type - 19 | b = cls.get_x(a[1]); - | ^ +%Error: t/t_func_ref_bad.v:19:20: Function/task ref argument is not of allowed type + 19 | b = cls.get_x(a[1]); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_ref_bad.v b/test_regress/t/t_func_ref_bad.v index 5abadd8c5..83884f6a4 100644 --- a/test_regress/t/t_func_ref_bad.v +++ b/test_regress/t/t_func_ref_bad.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - function logic get_x(ref logic x); - return x; - endfunction + function logic get_x(ref logic x); + return x; + endfunction endclass module t; - logic [10:0] a; - logic b; - Cls cls; - initial begin - cls = new; - b = cls.get_x(a[1]); - $stop; - end + logic [10:0] a; + logic b; + Cls cls; + initial begin + cls = new; + b = cls.get_x(a[1]); + $stop; + end endmodule diff --git a/test_regress/t/t_func_refio_bad.out b/test_regress/t/t_func_refio_bad.out index fe6b535da..5b9677680 100644 --- a/test_regress/t/t_func_refio_bad.out +++ b/test_regress/t/t_func_refio_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_func_refio_bad.v:16:17: Ref argument requires matching types; port 'q' requires 'integer$[$]' but connection is 'logic[31:0]'. +%Error: t/t_func_refio_bad.v:16:15: Ref argument requires matching types; port 'q' requires 'integer$[$]' but connection is 'logic[31:0]'. : ... note: In instance 't' - 16 | queue_set(42); - | ^~ + 16 | queue_set(42); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_refio_bad.v b/test_regress/t/t_func_refio_bad.v index b81984b26..6a1a7d674 100644 --- a/test_regress/t/t_func_refio_bad.v +++ b/test_regress/t/t_func_refio_bad.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - typedef integer q_t[$]; + typedef integer q_t[$]; - function void queue_set(ref q_t q); - q.push_back(42); - endfunction + function void queue_set(ref q_t q); + q.push_back(42); + endfunction - initial begin - q_t iq; - queue_set(42); // 42 is bad, meant iq - end + initial begin + q_t iq; + queue_set(42); // 42 is bad, meant iq + end endmodule diff --git a/test_regress/t/t_func_regfirst.v b/test_regress/t/t_func_regfirst.v index 24c24a561..631a369fd 100644 --- a/test_regress/t/t_func_regfirst.v +++ b/test_regress/t/t_func_regfirst.v @@ -4,75 +4,84 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + clk +); + input clk; - reg [2:0] a; - reg [2:0] b; - reg q; + reg [2:0] a; + reg [2:0] b; + reg q; - f6 f6 (/*AUTOINST*/ - // Outputs - .q (q), - // Inputs - .a (a[2:0]), - .b (b[2:0]), - .clk (clk)); + f6 f6 ( /*AUTOINST*/ + // Outputs + .q(q), + // Inputs + .a(a[2:0]), + .b(b[2:0]), + .clk(clk) + ); - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 3'b000; - b <= 3'b100; - end - if (cyc==2) begin - a <= 3'b011; - b <= 3'b001; - if (q != 1'b0) $stop; - end - if (cyc==3) begin - a <= 3'b011; - b <= 3'b011; - if (q != 1'b0) $stop; - end - if (cyc==9) begin - if (q != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a <= 3'b000; + b <= 3'b100; end - end + if (cyc == 2) begin + a <= 3'b011; + b <= 3'b001; + if (q != 1'b0) $stop; + end + if (cyc == 3) begin + a <= 3'b011; + b <= 3'b011; + if (q != 1'b0) $stop; + end + if (cyc == 9) begin + if (q != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module f6 (a, b, clk, q); - input [2:0] a; - input [2:0] b; - input clk; - output q; - reg out; +module f6 ( + a, + b, + clk, + q +); + input [2:0] a; + input [2:0] b; + input clk; + output q; + reg out; - function func6; - reg result; - input [5:0] src; - begin - if (src[5:0] == 6'b011011) begin - result = 1'b1; - end - else begin - result = 1'b0; - end - func6 = result; + function func6; + reg result; + input [5:0] src; + begin + if (src[5:0] == 6'b011011) begin + result = 1'b1; end - endfunction + else begin + result = 1'b0; + end + func6 = result; + end + endfunction - wire [5:0] w6 = {a, b}; - always @(posedge clk) begin - out <= func6(w6); - end + wire [5:0] w6 = {a, b}; + always @(posedge clk) begin + out <= func6(w6); + end - assign q = out; + assign q = out; endmodule diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v index 4b09e6de9..44871ae8e 100644 --- a/test_regress/t/t_func_return.v +++ b/test_regress/t/t_func_return.v @@ -8,60 +8,56 @@ typedef logic [7-1:0] wb_ind_t; typedef logic [7-1:0] id_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - wire [6:0] out = line_wb_ind( in[6:0] ); + wire [6:0] out = line_wb_ind(in[6:0]); - // Aggregate outputs into a single result vector - wire [63:0] result = {57'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hc918fa0aa882a206 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hc918fa0aa882a206 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - function wb_ind_t line_wb_ind( id_t id ); - if( id[$bits(id_t)-1] == 0 ) - return {2'b00, id[$bits(wb_ind_t)-3:0]}; - else - return {2'b01, id[$bits(wb_ind_t)-3:0]}; - endfunction // line_wb_ind + function wb_ind_t line_wb_ind(id_t id); + if (id[$bits(id_t)-1] == 0) return {2'b00, id[$bits(wb_ind_t)-3:0]}; + else return {2'b01, id[$bits(wb_ind_t)-3:0]}; + endfunction // line_wb_ind endmodule diff --git a/test_regress/t/t_func_return_bad.out b/test_regress/t/t_func_return_bad.out index a715ca985..ca4146501 100644 --- a/test_regress/t/t_func_return_bad.out +++ b/test_regress/t/t_func_return_bad.out @@ -1,21 +1,21 @@ -%Error: t/t_func_return_bad.v:10:7: Return underneath a task shouldn't have return value - 10 | return 1; - | ^~~~~~ +%Error: t/t_func_return_bad.v:10:5: Return underneath a task shouldn't have return value + 10 | return 1; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_func_return_bad.v:13:7: Return underneath a function should have return value - 13 | return; - | ^~~~~~ -%Error: t/t_func_return_bad.v:17:7: Return isn't underneath a task or function - 17 | return; - | ^~~~~~ -%Error: t/t_func_return_bad.v:18:7: continue isn't underneath a loop - 18 | continue; - | ^~~~~~~~ -%Error: t/t_func_return_bad.v:19:7: break isn't underneath a loop - 19 | break; - | ^~~~~ -%Error-UNSUPPORTED: t/t_func_return_bad.v:22:7: disable isn't underneath a begin with name: 'foo' - 22 | disable foo; - | ^~~~~~~ +%Error: t/t_func_return_bad.v:13:5: Return underneath a function should have return value + 13 | return; + | ^~~~~~ +%Error: t/t_func_return_bad.v:17:5: Return isn't underneath a task or function + 17 | return; + | ^~~~~~ +%Error: t/t_func_return_bad.v:18:5: continue isn't underneath a loop + 18 | continue; + | ^~~~~~~~ +%Error: t/t_func_return_bad.v:19:5: break isn't underneath a loop + 19 | break; + | ^~~~~ +%Error-UNSUPPORTED: t/t_func_return_bad.v:22:5: disable isn't underneath a begin with name: 'foo' + 22 | disable foo; + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_func_return_bad.v b/test_regress/t/t_func_return_bad.v index 331382f93..871bee78d 100644 --- a/test_regress/t/t_func_return_bad.v +++ b/test_regress/t/t_func_return_bad.v @@ -6,19 +6,19 @@ module t; - task t1; - return 1; // Shouldn't return value - endtask - function int f1; - return; // Should return value - endfunction + task t1; + return 1; // Shouldn't return value + endtask + function int f1; + return; // Should return value + endfunction - initial begin - return; // Not under function - continue; // Not under loop - break; // Not under loop - begin : foo - end - disable foo; // Disabling outside block - end + initial begin + return; // Not under function + continue; // Not under loop + break; // Not under loop + begin : foo + end + disable foo; // Disabling outside block + end endmodule diff --git a/test_regress/t/t_func_sel.v b/test_regress/t/t_func_sel.v index 1b5e3fba6..b0ba66712 100644 --- a/test_regress/t/t_func_sel.v +++ b/test_regress/t/t_func_sel.v @@ -7,57 +7,52 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; - parameter W = 104; +module t ( + input clk +); + parameter W = 104; - integer cyc = 0; - reg [63:0] crc; - reg [127:0] sum; - wire [127:0] result; + integer cyc = 0; + reg [63:0] crc; + reg [127:0] sum; + wire [127:0] result; - wire [103:0] in; - reg [103:0] out; + wire [103:0] in; + reg [103:0] out; - assign in = {crc[39:0], crc[63:0]}; + assign in = {crc[39:0], crc[63:0]}; - always @(posedge clk) begin - out <= reverse(in); - end + always @(posedge clk) begin + out <= reverse(in); + end - assign result = {24'h0, out }; + assign result = {24'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n", - $time, cyc, crc, result, in, out); + $write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n", $time, cyc, crc, result, in, out); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {sum[127:1], 1'b0} + result; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {sum[127:1], 1'b0} + result; - if (cyc < 10) begin - crc <= 1; - sum <= '0; - end - else if (cyc >= 90) begin - $display("SUM = %x_%x_%x_%x", sum[127:96], - sum[95:64], sum[63:32], sum[31:0]); -`define EXPECTED_SUM 128'h00002d36_42d1a346_8d1a5936_42d1a319 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc < 10) begin + crc <= 1; + sum <= '0; + end + else if (cyc >= 90) begin + $display("SUM = %x_%x_%x_%x", sum[127:96], sum[95:64], sum[63:32], sum[31:0]); + `define EXPECTED_SUM 128'h00002d36_42d1a346_8d1a5936_42d1a319 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end - function [W-1:0] reverse(input [W-1:0] val); - integer i; - // Bug workaround: reverse = '0; - for (i = 0; i < W; i = i + 1) - reverse[W-1-i] = val[i]; - endfunction + function [W-1:0] reverse(input [W-1:0] val); + integer i; + // Bug workaround: reverse = '0; + for (i = 0; i < W; i = i + 1) reverse[W-1-i] = val[i]; + endfunction endmodule diff --git a/test_regress/t/t_func_sum.v b/test_regress/t/t_func_sum.v index 32000941f..b2f31a47e 100644 --- a/test_regress/t/t_func_sum.v +++ b/test_regress/t/t_func_sum.v @@ -4,90 +4,88 @@ // SPDX-FileCopyrightText: 2008-2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [9:0] I1 = crc[9:0]; - wire [9:0] I2 = crc[19:10]; + wire [9:0] I1 = crc[9:0]; + wire [9:0] I2 = crc[19:10]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [9:0] S; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [9:0] S; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .S (S[9:0]), - // Inputs - .I1 (I1[9:0]), - .I2 (I2[9:0])); + Test test ( /*AUTOINST*/ + // Outputs + .S(S[9:0]), + // Inputs + .I1(I1[9:0]), + .I2(I2[9:0]) + ); - wire [63:0] result = {32'h0, 22'h0, S}; + wire [63:0] result = {32'h0, 22'h0, S}; -`define EXPECTED_SUM 64'h24c38b77b0fcc2e7 + `define EXPECTED_SUM 64'h24c38b77b0fcc2e7 - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - S, - // Inputs - I1, I2 - ); +module Test ( /*AUTOARG*/ + // Outputs + S, + // Inputs + I1, + I2 +); - input [9:0] I1/*verilator public*/; - input [9:0] I2/*verilator public*/; - output reg [9:0] S/*verilator public*/; + input [9:0] I1 /*verilator public*/; + input [9:0] I2 /*verilator public*/; + output reg [9:0] S /*verilator public*/; - always @(I1 or I2) - t2(I1,I2,S); + always @(I1 or I2) t2(I1, I2, S); - task t1; - input In1,In2; - output Sum; - Sum = In1 ^ In2; - endtask + task t1; + input In1, In2; + output Sum; + Sum = In1 ^ In2; + endtask - task t2; - input[9:0] In1,In2; - output [9:0] Sum; - integer I; - begin - for (I=0;I<10;I=I+1) - t1(In1[I],In2[I],Sum[I]); - end - endtask + task t2; + input [9:0] In1, In2; + output [9:0] Sum; + integer I; + begin + for (I = 0; I < 10; I = I + 1) t1(In1[I], In2[I], Sum[I]); + end + endtask endmodule diff --git a/test_regress/t/t_func_tie_bad.out b/test_regress/t/t_func_tie_bad.out index 65b000d3c..4b44d858b 100644 --- a/test_regress/t/t_func_tie_bad.out +++ b/test_regress/t/t_func_tie_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_func_tie_bad.v:11:15: Function/task output connected to constant instead of variable: 'b' - 11 | func(0, 1'b1); - | ^~~~ +%Error: t/t_func_tie_bad.v:11:13: Function/task output connected to constant instead of variable: 'b' + 11 | func(0, 1'b1); + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_tie_bad.v b/test_regress/t/t_func_tie_bad.v index 2e0e0df37..4640502d3 100644 --- a/test_regress/t/t_func_tie_bad.v +++ b/test_regress/t/t_func_tie_bad.v @@ -6,16 +6,13 @@ module t; - initial begin - // verilator lint_off IGNOREDRETURN - func(0, 1'b1); - end + initial begin + // verilator lint_off IGNOREDRETURN + func(0, 1'b1); + end - function automatic int func - ( - input int a, - output bit b ); - return 0; - endfunction + function automatic int func(input int a, output bit b); + return 0; + endfunction endmodule diff --git a/test_regress/t/t_func_twocall.v b/test_regress/t/t_func_twocall.v index 850d9690c..4d861fd09 100644 --- a/test_regress/t/t_func_twocall.v +++ b/test_regress/t/t_func_twocall.v @@ -4,58 +4,58 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - reg [7:0] crc; + reg [7:0] crc; - wire [61:59] ah = crc[5:3]; - wire [61:59] bh = ~crc[4:2]; - wire [41:2] al = {crc,crc,crc,crc,crc}; - wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; - reg sel; + wire [61:59] ah = crc[5:3]; + wire [61:59] bh = ~crc[4:2]; + wire [41:2] al = {crc, crc, crc, crc, crc}; + wire [41:2] bl = ~{crc[6:0], crc[6:0], crc[6:0], crc[6:0], crc[6:0], crc[6:2]}; + reg sel; - wire [61:28] q = ( sel - ? func(ah, al) - : func(bh, bl)); + wire [61:28] q = (sel ? func(ah, al) : func(bh, bl)); - function [61:28] func; - input [61:59] inh; - input [41:2] inl; - reg [42:28] func_mid; - reg carry; - begin - carry = &inl[27:2]; - func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; - func[61:59] = inh + {2'b0, func_mid[42]}; - func[58:42] = {17{func_mid[41]}}; - func[41:28] = func_mid[41:28]; + function [61:28] func; + input [61:59] inh; + input [41:2] inl; + reg [42:28] func_mid; + reg carry; + begin + carry = &inl[27:2]; + func_mid = {1'b0, inl[41:28]} + {14'b0, carry}; + func[61:59] = inh + {2'b0, func_mid[42]}; + func[58:42] = {17{func_mid[41]}}; + func[41:28] = func_mid[41:28]; + end + endfunction + + integer cyc; + initial cyc = 1; + always @(posedge clk) begin + //$write("%d %x\n", cyc, q); + if (cyc != 0) begin + cyc <= cyc + 1; + sel <= ~sel; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + if (cyc == 1) begin + sel <= 1'b1; + crc <= 8'h12; end - endfunction - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - //$write("%d %x\n", cyc, q); - if (cyc!=0) begin - cyc <= cyc + 1; - sel <= ~sel; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==1) begin - sel <= 1'b1; - crc <= 8'h12; - end - if (cyc==2) if (q!=34'h100000484) $stop; - if (cyc==3) if (q!=34'h37fffeddb) $stop; - if (cyc==4) if (q!=34'h080001212) $stop; - if (cyc==5) if (q!=34'h1fffff7ef) $stop; - if (cyc==6) if (q!=34'h200000848) $stop; - if (cyc==7) if (q!=34'h380001ebd) $stop; - if (cyc==8) if (q!=34'h07fffe161) $stop; - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 2) if (q != 34'h100000484) $stop; + if (cyc == 3) if (q != 34'h37fffeddb) $stop; + if (cyc == 4) if (q != 34'h080001212) $stop; + if (cyc == 5) if (q != 34'h1fffff7ef) $stop; + if (cyc == 6) if (q != 34'h200000848) $stop; + if (cyc == 7) if (q != 34'h380001ebd) $stop; + if (cyc == 8) if (q != 34'h07fffe161) $stop; + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_func_types.v b/test_regress/t/t_func_types.v index 6c0fefc86..2a6ac3f4d 100644 --- a/test_regress/t/t_func_types.v +++ b/test_regress/t/t_func_types.v @@ -6,47 +6,49 @@ module t; - function int int123(); int123 = 32'h123; endfunction + // verilog_format: off + function int int123(); int123 = 32'h123; endfunction - function bit f_bit ; input bit i; f_bit = ~i; endfunction - function int f_int ; input int i; f_int = ~i; endfunction - function byte f_byte ; input byte i; f_byte = ~i; endfunction - function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction - function longint f_longint ; input longint i; f_longint = ~i; endfunction - function chandle f_chandle ; input chandle i; f_chandle = i; endfunction + function bit f_bit ; input bit i; f_bit = ~i; endfunction + function int f_int ; input int i; f_int = ~i; endfunction + function byte f_byte ; input byte i; f_byte = ~i; endfunction + function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction + function longint f_longint ; input longint i; f_longint = ~i; endfunction + function chandle f_chandle ; input chandle i; f_chandle = i; endfunction - // Note there's no "input" here vvvv, it's the default - function bit g_bit (bit i); g_bit = ~i; endfunction - function int g_int (int i); g_int = ~i; endfunction - function byte g_byte (byte i); g_byte = ~i; endfunction - function shortint g_shortint(shortint i); g_shortint = ~i; endfunction - function longint g_longint (longint i); g_longint = ~i; endfunction - function chandle g_chandle (chandle i); g_chandle = i; endfunction + // Note there's no "input" here vvvv, it's the default + function bit g_bit (bit i); g_bit = ~i; endfunction + function int g_int (int i); g_int = ~i; endfunction + function byte g_byte (byte i); g_byte = ~i; endfunction + function shortint g_shortint(shortint i); g_shortint = ~i; endfunction + function longint g_longint (longint i); g_longint = ~i; endfunction + function chandle g_chandle (chandle i); g_chandle = i; endfunction + // verilog_format: on - chandle c; + chandle c; - initial begin + initial begin - if (int123() !== 32'h123) $stop; + if (int123() !== 32'h123) $stop; - if (f_bit(1'h1) !== 1'h0) $stop; - if (f_bit(1'h0) !== 1'h1) $stop; - if (f_int(32'h1) !== 32'hfffffffe) $stop; - if (f_byte(8'h1) !== 8'hfe) $stop; - if (f_shortint(16'h1) !== 16'hfffe) $stop; - if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; - if (f_chandle(c) !== c) $stop; + if (f_bit(1'h1) !== 1'h0) $stop; + if (f_bit(1'h0) !== 1'h1) $stop; + if (f_int(32'h1) !== 32'hfffffffe) $stop; + if (f_byte(8'h1) !== 8'hfe) $stop; + if (f_shortint(16'h1) !== 16'hfffe) $stop; + if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; + if (f_chandle(c) !== c) $stop; - if (g_bit(1'h1) !== 1'h0) $stop; - if (g_bit(1'h0) !== 1'h1) $stop; - if (g_int(32'h1) !== 32'hfffffffe) $stop; - if (g_byte(8'h1) !== 8'hfe) $stop; - if (g_shortint(16'h1) !== 16'hfffe) $stop; - if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; - if (g_chandle(c) !== c) $stop; + if (g_bit(1'h1) !== 1'h0) $stop; + if (g_bit(1'h0) !== 1'h1) $stop; + if (g_int(32'h1) !== 32'hfffffffe) $stop; + if (g_byte(8'h1) !== 8'hfe) $stop; + if (g_shortint(16'h1) !== 16'hfffe) $stop; + if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; + if (g_chandle(c) !== c) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_under.v b/test_regress/t/t_func_under.v index 80cad6e78..0c3835983 100644 --- a/test_regress/t/t_func_under.v +++ b/test_regress/t/t_func_under.v @@ -4,24 +4,22 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [3:0] counter = 0; - integer l2; - function automatic log2 (input [3:0] x); - integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; - endfunction - always @(posedge clk) begin - counter <= counter + 1; - l2 <= log2(counter); - // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): - $display("log2(%d) == %d", counter, log2(counter)); - // - $write("*-* All Finished *-*\n"); - $finish; - end + reg [3:0] counter = 0; + integer l2; + function automatic log2(input [3:0] x); + integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; + endfunction + always @(posedge clk) begin + counter <= counter + 1; + l2 <= log2(counter); + // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): + $display("log2(%d) == %d", counter, log2(counter)); + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_under2.v b/test_regress/t/t_func_under2.v index db9eb731c..044f21a88 100644 --- a/test_regress/t/t_func_under2.v +++ b/test_regress/t/t_func_under2.v @@ -7,39 +7,39 @@ // bug598 module t (/*AUTOARG*/ - // Outputs - val, - // Inputs - clk - ); + // Outputs + val, + // Inputs + clk + ); - input clk; - output integer val; - integer dbg_addr = 0; + input clk; + output integer val; + integer dbg_addr = 0; - function func1; - input en; - input [31:0] a; - func1 = en && (a == 1); - endfunction + function func1; + input en; + input [31:0] a; + func1 = en && (a == 1); + endfunction - function func2; - input en; - input [31:0] a; - func2 = en && (a == 2); - endfunction + function func2; + input en; + input [31:0] a; + func2 = en && (a == 2); + endfunction - always @(posedge clk) begin - case( 1'b1 ) - // This line is OK: - func1(1'b1, dbg_addr) : val = 1; - // This fails: - // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement - func2(1'b1, dbg_addr) : val = 2; - default : val = 0; - endcase - // - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + case( 1'b1 ) + // This line is OK: + func1(1'b1, dbg_addr) : val = 1; + // This fails: + // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement + func2(1'b1, dbg_addr) : val = 2; + default : val = 0; + endcase + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_uninit.v b/test_regress/t/t_func_uninit.v index a9152f83a..25bd9285c 100644 --- a/test_regress/t/t_func_uninit.v +++ b/test_regress/t/t_func_uninit.v @@ -9,26 +9,26 @@ function int zeroed; endfunction function automatic integer what_bit; - input [31:0] a; - // what_bit = 0; - for (int i = 31; i >= 0; i = i - 1) begin - if (a[i] == 1'b1) begin - what_bit = i; - end - end + input [31:0] a; + // what_bit = 0; + for (int i = 31; i >= 0; i = i - 1) begin + if (a[i] == 1'b1) begin + what_bit = i; + end + end endfunction module t; - parameter ZERO = zeroed(); + parameter ZERO = zeroed(); - parameter PP = what_bit(0); + parameter PP = what_bit(0); - initial begin - if (ZERO != 0) $stop; - if (PP != 'x) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (ZERO != 0) $stop; + if (PP != 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_unit.v b/test_regress/t/t_func_unit.v index 85692325b..4140afbc1 100644 --- a/test_regress/t/t_func_unit.v +++ b/test_regress/t/t_func_unit.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 task tsk(output tfo); - tfo = 1'b0; + tfo = 1'b0; endtask module t (/*AUTOARG*/ - // Outputs - to - ); - output reg to[2:0]; + // Outputs + to + ); + output reg to[2:0]; - integer i = 0; + integer i = 0; - initial begin - tsk(to[i]); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + tsk(to[i]); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_v.v b/test_regress/t/t_func_v.v index 3b8f45236..aa83d5227 100644 --- a/test_regress/t/t_func_v.v +++ b/test_regress/t/t_func_v.v @@ -8,28 +8,28 @@ module t; `ifdef T_FUNC_V_NOINL - // verilator no_inline_module + // verilator no_inline_module `endif - level1 ul1(); - initial ul1.doit(4'b0); + level1 ul1 (); + initial ul1.doit(4'b0); endmodule -module level1(); +module level1 (); `ifdef T_FUNC_V_NOINL - // verilator no_inline_module + // verilator no_inline_module `endif - level2 ul2(); + level2 ul2 (); - task doit(input logic [3:0] v); - ul2.mem = v; - $write("*-* All Finished *-*\n"); - $finish; - endtask + task doit(input logic [3:0] v); + ul2.mem = v; + $write("*-* All Finished *-*\n"); + $finish; + endtask endmodule -module level2(); +module level2 (); `ifdef T_FUNC_V_NOINL - // verilator no_inline_module + // verilator no_inline_module `endif - logic [3:0] mem; + logic [3:0] mem; endmodule diff --git a/test_regress/t/t_func_void.v b/test_regress/t/t_func_void.v index 22c3f0bb5..0407d1bc0 100644 --- a/test_regress/t/t_func_void.v +++ b/test_regress/t/t_func_void.v @@ -4,42 +4,43 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + input clk +); - int side_effect; + int side_effect; - function int f1; - input int in; - f1 = in + 1; - side_effect += in + 1; - endfunction + function int f1; + input int in; + f1 = in + 1; + side_effect += in + 1; + endfunction - class Cls; - static function int initialize(); - return 6; - endfunction - endclass + class Cls; + static function int initialize(); + return 6; + endfunction + endclass - initial begin - int got; - side_effect = 1; - // - got = f1(10); - if (got != 11) $stop; - if (side_effect != 12) $stop; - // verilator lint_off IGNOREDRETURN - f1(20); - // verilator lint_on IGNOREDRETURN - if (side_effect != 33) $stop; - // - void'(f1(30)); - if (side_effect != 64) $stop; - // - void'(Cls::initialize()); - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + int got; + side_effect = 1; + // + got = f1(10); + if (got != 11) $stop; + if (side_effect != 12) $stop; + // verilator lint_off IGNOREDRETURN + f1(20); + // verilator lint_on IGNOREDRETURN + if (side_effect != 33) $stop; + // + void'(f1(30)); + if (side_effect != 64) $stop; + // + void'(Cls::initialize()); + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index 37b0f4cb6..f664d3b3e 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,12 +1,12 @@ -%Warning-IGNOREDRETURN: t/t_func_void_bad.v:24:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) - 24 | f1(); - | ^~ +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:24:5: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 24 | f1(); + | ^~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. -%Warning-IGNOREDRETURN: t/t_func_void_bad.v:27:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) - 27 | c.fi(); - | ^~ -%Warning-IGNOREDRETURN: t/t_func_void_bad.v:28:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) - 28 | c.sfi(); - | ^~~ +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:27:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 27 | c.fi(); + | ^~ +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:28:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) + 28 | c.sfi(); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_void_bad.v b/test_regress/t/t_func_void_bad.v index 4bf00d330..3e49d8f6a 100644 --- a/test_regress/t/t_func_void_bad.v +++ b/test_regress/t/t_func_void_bad.v @@ -5,30 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - function int fi(); - return 10; - endfunction - static function int sfi(); - return 10; - endfunction + function int fi(); + return 10; + endfunction + static function int sfi(); + return 10; + endfunction endclass module t; - function int f1; - return 20; - endfunction + function int f1; + return 20; + endfunction - initial begin - Cls c; - // - f1(); // Bad - ignored result - // - c = new; - c.fi(); // Bad - ignored result - c.sfi(); // Bad - ignored result - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + // + f1(); // Bad - ignored result + // + c = new; + c.fi(); // Bad - ignored result + c.sfi(); // Bad - ignored result + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_while.v b/test_regress/t/t_func_while.v index bab93123a..e0aa694de 100644 --- a/test_regress/t/t_func_while.v +++ b/test_regress/t/t_func_while.v @@ -4,30 +4,29 @@ // SPDX-FileCopyrightText: 2018 Julien Margetts // SPDX-License-Identifier: CC0-1.0 -module t #(parameter SZ = 4096) - ( - input wire clk, +module t #( + parameter SZ = 4096 +) ( + input wire clk, output reg [tdw(SZ)-1:0] data - ); +); - // bug1330 - function integer clog2(input integer value); - integer tmp; - tmp = value-1; - clog2 = 0; - for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1) - tmp = tmp>>1; - endfunction + // bug1330 + function integer clog2(input integer value); + integer tmp; + tmp = value - 1; + clog2 = 0; + for (clog2 = 0; (tmp > 0) && (clog2 < 32); clog2 = clog2 + 1) tmp = tmp >> 1; + endfunction - function integer tdw(input integer SZ); - tdw = clog2(SZ); - endfunction + function integer tdw(input integer SZ); + tdw = clog2(SZ); + endfunction - integer b; + integer b; - always @(posedge clk) - for (b=0; b nt0) = (0, 0); - endspecify + specify + specparam CDS_LIBNAME = "foobar"; + (nt0 *> nt0) = (0, 0); + endspecify - specify - // delay parameters - specparam - a$A1$Y = 1.0, - b$A0$Z = 1.0; + specify + // delay parameters + specparam + a$A1$Y = 1.0, + b$A0$Z = 1.0; - // path delays - (A1 *> Q) = (a$A1$Y, a$A1$Y); - (A0 *> Q) = (b$A0$Y, a$A0$Z); + // path delays + (A1 *> Q) = (a$A1$Y, a$A1$Y); + (A0 *> Q) = (b$A0$Y, a$A0$Z); - if (C1) (IN => OUT) = (1,1); - ifnone (IN => OUT) = (2,2); + if (C1) (IN => OUT) = (1,1); + ifnone (IN => OUT) = (2,2); - showcancelled Q; - noshowcancelled Q; - pulsestyle_ondetect Q; - pulsestyle_onevent Q; + showcancelled Q; + noshowcancelled Q; + pulsestyle_ondetect Q; + pulsestyle_onevent Q; - // other unimplemented stuff - $fullskew(); - $hold(); - $nochange(); - $period(); - $recovery(); - $recrem(); - $removal(); - $setup(); - $skew(); - $timeskew(); - $width(); + // other unimplemented stuff + $fullskew(); + $hold(); + $nochange(); + $period(); + $recovery(); + $recrem(); + $removal(); + $setup(); + $skew(); + $timeskew(); + $width(); endspecify `endif - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 32'h18f6b034; - b <= 32'h834bf892; - end - if (cyc==2) begin - a <= 32'h529ab56f; - b <= 32'h7835a237; - if (bf !== 3'b100) $stop; - if (bfm != 3'b000) $stop; - if (ntm != 3'b111) $stop; - if (nt0 !== 1'b1) $stop; - if (an0 !== 1'b0) $stop; - if (nd0 !== 1'b1) $stop; - if (or0 !== 1'b0) $stop; - if (nr0 !== 1'b1) $stop; - if (xo0 !== 1'b0) $stop; - if (xn0 !== 1'b1) $stop; - if (ba != 32'h18f6b034) $stop; - end - if (cyc==3) begin - if (bf !== 3'b111) $stop; - if (bfm != 3'b111) $stop; - if (ntm != 3'b000) $stop; - if (nt0 !== 1'b0) $stop; - if (an0 !== 1'b1) $stop; - if (nd0 !== 1'b0) $stop; - if (or0 !== 1'b1) $stop; - if (nr0 !== 1'b0) $stop; - if (xo0 !== 1'b0) $stop; - if (xn0 !== 1'b0) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 32'h18f6b034; + b <= 32'h834bf892; end - end + if (cyc==2) begin + a <= 32'h529ab56f; + b <= 32'h7835a237; + if (bf !== 3'b100) $stop; + if (bfm != 3'b000) $stop; + if (ntm != 3'b111) $stop; + if (nt0 !== 1'b1) $stop; + if (an0 !== 1'b0) $stop; + if (nd0 !== 1'b1) $stop; + if (or0 !== 1'b0) $stop; + if (nr0 !== 1'b1) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b1) $stop; + if (ba != 32'h18f6b034) $stop; + end + if (cyc==3) begin + if (bf !== 3'b111) $stop; + if (bfm != 3'b111) $stop; + if (ntm != 3'b000) $stop; + if (nt0 !== 1'b0) $stop; + if (an0 !== 1'b1) $stop; + if (nd0 !== 1'b0) $stop; + if (or0 !== 1'b1) $stop; + if (nr0 !== 1'b0) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b0) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_gate_basic_specify_bad.out b/test_regress/t/t_gate_basic_specify_bad.out index c0e5a82ee..3b16e0887 100644 --- a/test_regress/t/t_gate_basic_specify_bad.out +++ b/test_regress/t/t_gate_basic_specify_bad.out @@ -1,14 +1,14 @@ -%Warning-RISEFALLDLY: t/t_gate_basic.v:26:12: Unsupported: rising/falling/turn-off delays. Using the first delay - 26 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); - | ^ +%Warning-RISEFALLDLY: t/t_gate_basic.v:25:11: Unsupported: rising/falling/turn-off delays. Using the first delay + 25 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); + | ^ ... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest ... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message. -%Warning-SPECIFYIGN: t/t_gate_basic.v:50:27: Ignoring unsupported: specify block construct - 50 | (nt0 *> nt0) = (0, 0); - | ^ +%Warning-SPECIFYIGN: t/t_gate_basic.v:49:25: Ignoring unsupported: specify block construct + 49 | (nt0 *> nt0) = (0, 0); + | ^ ... For warning description see https://verilator.org/warn/SPECIFYIGN?v=latest ... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message. -%Warning-SPECIFYIGN: t/t_gate_basic.v:60:32: Ignoring unsupported: specify block construct - 60 | (A1 *> Q) = (a$A1$Y, a$A1$Y); - | ^ +%Warning-SPECIFYIGN: t/t_gate_basic.v:59:31: Ignoring unsupported: specify block construct + 59 | (A1 *> Q) = (a$A1$Y, a$A1$Y); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_gate_delay_unsup.out b/test_regress/t/t_gate_delay_unsup.out index 24b698bab..b28579928 100644 --- a/test_regress/t/t_gate_delay_unsup.out +++ b/test_regress/t/t_gate_delay_unsup.out @@ -1,6 +1,6 @@ -%Warning-RISEFALLDLY: t/t_gate_basic.v:26:12: Unsupported: rising/falling/turn-off delays. Using the first delay - 26 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); - | ^ +%Warning-RISEFALLDLY: t/t_gate_basic.v:25:11: Unsupported: rising/falling/turn-off delays. Using the first delay + 25 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); + | ^ ... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest ... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_gate_delref.v b/test_regress/t/t_gate_delref.v index db32a89dd..3ac9e3c12 100644 --- a/test_regress/t/t_gate_delref.v +++ b/test_regress/t/t_gate_delref.v @@ -5,45 +5,49 @@ // SPDX-License-Identifier: CC0-1.0 // bug1475 -module t (/*AUTOARG*/ - // Outputs - ID_45, IDa_f4c, - // Inputs - clk, ID_d9f, IDa_657, ID_477 - ); - input clk; - output reg ID_45; - input ID_d9f; - input IDa_657; - output reg IDa_f4c; +module t ( /*AUTOARG*/ + // Outputs + ID_45, + IDa_f4c, + // Inputs + clk, + ID_d9f, + IDa_657, + ID_477 +); + input clk; + output reg ID_45; + input ID_d9f; + input IDa_657; + output reg IDa_f4c; - reg ID_13; - input ID_477; - reg ID_489; - reg ID_8d1; - reg IDa_183; - reg IDa_91c; - reg IDa_a96; - reg IDa_d6b; - reg IDa_eb9; - wire ID_fc8 = ID_d9f & ID_13; //<< - wire ID_254 = ID_d9f & ID_13; - wire ID_f40 = ID_fc8 ? ID_8d1 : 0; - wire ID_f4c = ID_fc8 ? 0 : ID_477; - wire ID_442 = IDa_91c; - wire ID_825 = ID_489; - always @(posedge clk) begin - ID_13 <= ID_f40; - ID_8d1 <= IDa_eb9; - ID_489 <= ID_442; - ID_45 <= ID_825; - IDa_d6b <= IDa_a96; - IDa_f4c <= ID_f4c; - if (ID_254) begin - IDa_91c <= IDa_d6b; - IDa_183 <= IDa_657; - IDa_a96 <= IDa_657; - IDa_eb9 <= IDa_183; - end - end + reg ID_13; + input ID_477; + reg ID_489; + reg ID_8d1; + reg IDa_183; + reg IDa_91c; + reg IDa_a96; + reg IDa_d6b; + reg IDa_eb9; + wire ID_fc8 = ID_d9f & ID_13; //<< + wire ID_254 = ID_d9f & ID_13; + wire ID_f40 = ID_fc8 ? ID_8d1 : 0; + wire ID_f4c = ID_fc8 ? 0 : ID_477; + wire ID_442 = IDa_91c; + wire ID_825 = ID_489; + always @(posedge clk) begin + ID_13 <= ID_f40; + ID_8d1 <= IDa_eb9; + ID_489 <= ID_442; + ID_45 <= ID_825; + IDa_d6b <= IDa_a96; + IDa_f4c <= ID_f4c; + if (ID_254) begin + IDa_91c <= IDa_d6b; + IDa_183 <= IDa_657; + IDa_a96 <= IDa_657; + IDa_eb9 <= IDa_183; + end + end endmodule diff --git a/test_regress/t/t_gate_elim.v b/test_regress/t/t_gate_elim.v index 6d0bfb65f..cbab6f35d 100644 --- a/test_regress/t/t_gate_elim.v +++ b/test_regress/t/t_gate_elim.v @@ -4,119 +4,144 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg b; + reg b; - wire vconst1 = 1'b0; - wire vconst2 = !(vconst1); - wire vconst3 = !vconst2; - wire vconst = vconst3; + wire vconst1 = 1'b0; + wire vconst2 = !(vconst1); + wire vconst3 = !vconst2; + wire vconst = vconst3; - wire qa; - wire qb; - wire qc; - wire qd; - wire qe; - ta ta (.b(b), .vconst(vconst), .q(qa)); - tb tb (.clk(clk), .vconst(vconst), .q(qb)); - tc tc (.b(b), .vconst(vconst), .q(qc)); - td td (.b(b), .vconst(vconst), .q(qd)); - te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); + wire qa; + wire qb; + wire qc; + wire qd; + wire qe; + ta ta ( + .b(b), + .vconst(vconst), + .q(qa) + ); + tb tb ( + .clk(clk), + .vconst(vconst), + .q(qb) + ); + tc tc ( + .b(b), + .vconst(vconst), + .q(qc) + ); + td td ( + .b(b), + .vconst(vconst), + .q(qd) + ); + te te ( + .clk(clk), + .b(b), + .vconst(vconst), + .q(qe) + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $display("%b",{qa,qb,qc,qd,qe}); + $display("%b", {qa, qb, qc, qd, qe}); `endif - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - b <= 1'b1; - end - if (cyc==2) begin - if (qa!=1'b1) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - b <= 1'b0; - end - if (cyc==3) begin - if (qa!=1'b0) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - if (qe!=1'b0) $stop; - b <= 1'b1; - end - if (cyc==4) begin - if (qa!=1'b1) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - if (qe!=1'b1) $stop; - b <= 1'b0; - end - if (cyc==5) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + b <= 1'b1; end - end + if (cyc == 2) begin + if (qa != 1'b1) $stop; + if (qb != 1'b0) $stop; + if (qd != 1'b0) $stop; + b <= 1'b0; + end + if (cyc == 3) begin + if (qa != 1'b0) $stop; + if (qb != 1'b0) $stop; + if (qd != 1'b0) $stop; + if (qe != 1'b0) $stop; + b <= 1'b1; + end + if (cyc == 4) begin + if (qa != 1'b1) $stop; + if (qb != 1'b0) $stop; + if (qd != 1'b0) $stop; + if (qe != 1'b1) $stop; + b <= 1'b0; + end + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module ta ( - input vconst, - input b, - output reg q); + input vconst, + input b, + output reg q +); - always @ (/*AS*/b or vconst) begin - q = vconst | b; - end + always @( /*AS*/ b or vconst) begin + q = vconst | b; + end endmodule module tb ( - input vconst, - input clk, - output reg q); + input vconst, + input clk, + output reg q +); - always @ (posedge clk) begin - q <= vconst; - end + always @(posedge clk) begin + q <= vconst; + end endmodule module tc ( - input vconst, - input b, - output reg q); - always @ (posedge vconst) begin - q <= b; - $stop; - end + input vconst, + input b, + output reg q +); + always @(posedge vconst) begin + q <= b; + $stop; + end endmodule module td ( - input vconst, - input b, - output reg q); + input vconst, + input b, + output reg q +); - always @ (/*AS*/vconst) begin - q = vconst; - end + always @( /*AS*/ vconst) begin + q = vconst; + end endmodule module te ( - input clk, - input vconst, - input b, - output reg q); - reg qmid; - always @ (posedge vconst or posedge clk) begin - qmid <= b; - end - always @ (posedge clk or posedge vconst) begin - q <= qmid; - end + input clk, + input vconst, + input b, + output reg q +); + reg qmid; + always @(posedge vconst or posedge clk) begin + qmid <= b; + end + always @(posedge clk or posedge vconst) begin + q <= qmid; + end endmodule diff --git a/test_regress/t/t_gate_fdup.v b/test_regress/t/t_gate_fdup.v index cc5dfb8ff..27a6d49ea 100644 --- a/test_regress/t/t_gate_fdup.v +++ b/test_regress/t/t_gate_fdup.v @@ -5,29 +5,29 @@ // SPDX-License-Identifier: CC0-1.0 module fnor2(f, a, b); - parameter W = 1; + parameter W = 1; - output [W-1:0]f; - input [W-1:0] a, b; + output [W-1:0]f; + input [W-1:0] a, b; - supply0 gnd; - supply1 vcc; + supply0 gnd; + supply1 vcc; - generate - genvar i; - for (i = 0; i < W; i = i + 1) begin - wire w; - pmos(f[i], w, a[i]); - pmos(w, vcc, b[i]); - nmos(f[i], gnd, a[i]); - nmos(f[i], gnd, b[i]); - end - endgenerate + generate + genvar i; + for (i = 0; i < W; i = i + 1) begin + wire w; + pmos(f[i], w, a[i]); + pmos(w, vcc, b[i]); + nmos(f[i], gnd, a[i]); + nmos(f[i], gnd, b[i]); + end + endgenerate endmodule module t(f, a, b); - output [1:0] f; - input [1:0] a, b; + output [1:0] f; + input [1:0] a, b; - fnor2 #(2) n(f, a, b); + fnor2 #(2) n(f, a, b); endmodule diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v index 953d2af6f..113b9ec32 100644 --- a/test_regress/t/t_gate_implicit.v +++ b/test_regress/t/t_gate_implicit.v @@ -4,77 +4,88 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire RBL2; // From t of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire RBL2; // From t of Test.v + // End of automatics - wire RWL1 = crc[2]; - wire RWL2 = crc[3]; + wire RWL1 = crc[2]; + wire RWL2 = crc[3]; - Test t (/*AUTOINST*/ - // Outputs - .RBL2 (RBL2), - // Inputs - .RWL1 (RWL1), - .RWL2 (RWL2)); + Test t ( /*AUTOINST*/ + // Outputs + .RBL2(RBL2), + // Inputs + .RWL1(RWL1), + .RWL2(RWL2) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'h0, RBL2}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, RBL2}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hb6d6b86aa20a882a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hb6d6b86aa20a882a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - output RBL2, - input RWL1, RWL2); + output RBL2, + input RWL1, + RWL2 +); - // verilator lint_off IMPLICIT - not I1 (RWL2_n, RWL2); - bufif1 I2 (RBL2, n3, 1'b1); - Mxor I3 (n3, RWL1, RWL2_n); - // verilator lint_on IMPLICIT + // verilator lint_off IMPLICIT + not I1 (RWL2_n, RWL2); + bufif1 I2 (RBL2, n3, 1'b1); + Mxor I3 ( + n3, + RWL1, + RWL2_n + ); + // verilator lint_on IMPLICIT endmodule -module Mxor (output out, input a, b); - assign out = (a ^ b); +module Mxor ( + output out, + input a, + b +); + assign out = (a ^ b); endmodule diff --git a/test_regress/t/t_gate_inline_wide_exclude_multiple.v b/test_regress/t/t_gate_inline_wide_exclude_multiple.v index e416e73ec..45051405b 100644 --- a/test_regress/t/t_gate_inline_wide_exclude_multiple.v +++ b/test_regress/t/t_gate_inline_wide_exclude_multiple.v @@ -4,23 +4,23 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -localparam N = 256; // Wider than expand limit. +localparam N = 256; // Wider than expand limit. -module t( - input wire [N-1:0] i, - output logic [N-1:0] o_multiple1, - output logic [N-1:0] o_multiple2, - output wire [N-1:0] o - ); +module t ( + input wire [N-1:0] i, + output logic [N-1:0] o_multiple1, + output logic [N-1:0] o_multiple2, + output wire [N-1:0] o +); - // Exclude from inline wide expressions referenced multiple times. - wire [N-1:0] wide_multiple_assigns = N >> i; - wire [N-1:0] wide = N << i; + // Exclude from inline wide expressions referenced multiple times. + wire [N-1:0] wide_multiple_assigns = N >> i; + wire [N-1:0] wide = N << i; - for (genvar n = 0; n < N - 1; ++n) begin - assign o[n] = i[N-1-n] | wide[N-1-n]; - end + for (genvar n = 0; n < N - 1; ++n) begin + assign o[n] = i[N-1-n] | wide[N-1-n]; + end - assign o_multiple1 = wide_multiple_assigns | i + 1; - assign o_multiple2 = wide_multiple_assigns | i + 2; + assign o_multiple1 = wide_multiple_assigns | i + 1; + assign o_multiple2 = wide_multiple_assigns | i + 2; endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v index 19e20c90a..947276b8d 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic [255:0] arrd [0:0] = '{ 1 }; - logic [255:0] y0; + logic [255:0] arrd[0:0] = '{1}; + logic [255:0] y0; - // Do not exclude from inlining wide arraysels. - always_comb y0 = arrd[0]; + // Do not exclude from inlining wide arraysels. + always_comb y0 = arrd[0]; - always_comb begin - if (y0 != 1 && y0 != 0) begin - $stop; - end - end + always_comb begin + if (y0 != 1 && y0 != 0) begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_const.v b/test_regress/t/t_gate_inline_wide_noexclude_const.v index 0fe85071e..c35ed5319 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_const.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_const.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 module t; - logic [255:0] arrd = 256'b0; - logic [255:0] y0; + logic [255:0] arrd = 256'b0; + logic [255:0] y0; - // Do not exclude from inlining wide variables with const assignments. - always_comb y0 = 256'(arrd[0]); + // Do not exclude from inlining wide variables with const assignments. + always_comb y0 = 256'(arrd[0]); - always_comb begin - if (y0 != 1 && y0 != 0) begin - $stop; - end - end + always_comb begin + if (y0 != 1 && y0 != 0) begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v index c49112c4d..c70022d24 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v @@ -4,23 +4,31 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -localparam N = 256; // Wider than expand limit. +localparam N = 256; // Wider than expand limit. -module t( - input wire [N-1:0] i, - output wire [N-1:0] o - ); +module t ( + input wire [N-1:0] i, + output wire [N-1:0] o +); - // Do not exclude from inlining wides referenced in different scope. - wire [N-1:0] wide = N ~^ i; + // Do not exclude from inlining wides referenced in different scope. + wire [N-1:0] wide = N ~^ i; - sub sub(i, wide, o); + sub sub ( + i, + wide, + o + ); endmodule -module sub(input wire [N-1:0] i, input wire [N-1:0] wide, output logic [N-1:0] o); - initial begin - for (integer n = 0; n < N ; ++n) begin - o[n] = i[N-1-n] | wide[N-1-n]; - end - end +module sub ( + input wire [N-1:0] i, + input wire [N-1:0] wide, + output logic [N-1:0] o +); + initial begin + for (integer n = 0; n < N; ++n) begin + o[n] = i[N-1-n] | wide[N-1-n]; + end + end endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_sel.v b/test_regress/t/t_gate_inline_wide_noexclude_sel.v index d4061c2d3..c17107a04 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_sel.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_sel.v @@ -5,40 +5,46 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - output reg [1020:0] res1, - output reg [1020:0] res2, - output reg [1022:0] res3, - output reg [1022:0] res4 - ); - always_inline always_inline(res1, res2); - dont_inline dont_inline(res3, res4); + output reg [1020:0] res1, + output reg [1020:0] res2, + output reg [1022:0] res3, + output reg [1022:0] res4 +); + always_inline always_inline ( + res1, + res2 + ); + dont_inline dont_inline ( + res3, + res4 + ); endmodule -module always_inline( - output reg [1020:0] res1, - output reg [1020:0] res2 - ); +module always_inline ( + output reg [1020:0] res1, + output reg [1020:0] res2 +); - wire [1023:0] a; - wire [478:0] b; + wire [1023:0] a; + wire [478:0] b; - assign b = a[510:32]; - assign res1 = {542'b0, b}; - assign res2 = {542'b1, b}; + assign b = a[510:32]; + assign res1 = {542'b0, b}; + assign res2 = {542'b1, b}; endmodule // SEL does not have proper offset so we do not have guarantee that it will be // emitted as '[' operator, thus we do not exclude it from inlining. -module dont_inline( - output reg [1022:0] res1, - output reg [1022:0] res2 - ); +module dont_inline ( + output reg [1022:0] res1, + output reg [1022:0] res2 +); - wire [1023:0] a; - wire [480:0] b; + wire [1023:0] a; + wire [480:0] b; - // LSB % 32 != 0 - assign b = a[510:30]; - assign res1 = {542'b0, b}; - assign res2 = {542'b1, b}; + // LSB % 32 != 0 + assign b = a[510:30]; + assign res1 = {542'b0, b}; + assign res2 = {542'b1, b}; endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v index 072fe1eae..1b1231c4e 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v @@ -4,18 +4,18 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -localparam N = 65; // Wide but narrower than expand limit +localparam N = 65; // Wide but narrower than expand limit -module t( - input wire [N-1:0] i, - output wire [N-1:0] o - ); +module t ( + input wire [N-1:0] i, + output wire [N-1:0] o +); - // Do not exclude from inlining wides small enough to be handled by - // V3Expand. - wire [65:0] wide_small = N << i * i / N; + // Do not exclude from inlining wides small enough to be handled by + // V3Expand. + wire [65:0] wide_small = N << i * i / N; - for (genvar n = 0; n < N; ++n) begin - assign o[n] = i[n] ^ wide_small[n]; - end + for (genvar n = 0; n < N; ++n) begin + assign o[n] = i[n] ^ wide_small[n]; + end endmodule diff --git a/test_regress/t/t_gate_inline_wide_noexclude_varref.v b/test_regress/t/t_gate_inline_wide_noexclude_varref.v index 392bf4b07..d9ad78f7b 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_varref.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_varref.v @@ -4,14 +4,20 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t(input [255:0] clk); - // Do not exclude from inlining wide reference assignments. - mod1 mod1(clk); - mod2 mod2(clk); +module t ( + input [255:0] clk +); + // Do not exclude from inlining wide reference assignments. + mod1 mod1 (clk); + mod2 mod2 (clk); endmodule -module mod1(input [255:0] clk); +module mod1 ( + input [255:0] clk +); endmodule -module mod2(input [255:0] clk); +module mod2 ( + input [255:0] clk +); endmodule diff --git a/test_regress/t/t_gate_lvalue_const.v b/test_regress/t/t_gate_lvalue_const.v index 22fe2958c..c8a8c00bd 100644 --- a/test_regress/t/t_gate_lvalue_const.v +++ b/test_regress/t/t_gate_lvalue_const.v @@ -4,65 +4,63 @@ // SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, rst - ); +module t ( + input clk, + input rst +); - input clk; - input rst; + logic [2:0] ctrl_inc_single; + logic [2:0] ctrl_inc_double; - logic [2:0] ctrl_inc_single; - logic [2:0] ctrl_inc_double; + logic [2:0] cnt_single; + always_ff @(posedge clk) begin + if (rst) begin + cnt_single <= '0; + end + else if (ctrl_inc_single != '0 && cnt_single != '1) begin + cnt_single <= cnt_single + 1'd1; + end + end - logic [2:0] cnt_single; - always_ff @(posedge clk) begin - if (rst) begin - cnt_single <= '0; - end - else if (ctrl_inc_single != '0 && cnt_single != '1) begin - cnt_single <= cnt_single + 1'd1; - end - end + logic [2:0] cnt_double; + always_ff @(posedge clk) begin + if (rst) begin + cnt_double <= '0; + end + else if (ctrl_inc_double != '0 && cnt_double != '1) begin + cnt_double <= cnt_double + 1'd1; + end + end - logic [2:0] cnt_double; - always_ff @(posedge clk) begin - if (rst) begin - cnt_double <= '0; - end - else if (ctrl_inc_double != '0 && cnt_double != '1) begin - cnt_double <= cnt_double + 1'd1; - end - end + always_comb ctrl_inc_single = '0; + always_comb ctrl_inc_double = '0; - always_comb ctrl_inc_single = '0; - always_comb ctrl_inc_double = '0; + testMod test_i (.data_i(cnt_single)); + testMod test_j (.data_i(cnt_double)); - testMod test_i (.data_i(cnt_single)); - testMod test_j (.data_i(cnt_double)); - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module testMod - (input wire [2:0] data_i); +module testMod ( + input wire [2:0] data_i +); - typedef logic [63:0] time_t; - // verilator lint_off MULTIDRIVEN - time_t [2:0] last_transition; - // verilator lint_on MULTIDRIVEN - genvar b; + typedef logic [63:0] time_t; + // verilator lint_off MULTIDRIVEN + time_t [2:0] last_transition; + // verilator lint_on MULTIDRIVEN + genvar b; - generate - for (b = 0; b <= 2; b++) begin : gen_trans - always_ff @(posedge data_i[b] or negedge data_i[b]) begin - last_transition[b] <= $time; - end + generate + for (b = 0; b <= 2; b++) begin : gen_trans + always_ff @(posedge data_i[b] or negedge data_i[b]) begin + last_transition[b] <= $time; end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_gate_opt.v b/test_regress/t/t_gate_opt.v index bdc237edc..92d96516d 100644 --- a/test_regress/t/t_gate_opt.v +++ b/test_regress/t/t_gate_opt.v @@ -7,31 +7,41 @@ // bug5101 module t; - logic [1:0] in0, in1, out; - logic sel; - assign in0 = 1; - assign in1 = 2; - assign sel = 1'b1; + logic [1:0] in0, in1, out; + logic sel; + assign in0 = 1; + assign in1 = 2; + assign sel = 1'b1; - initial begin - $display("out:%d", out); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("out:%d", out); + $write("*-* All Finished *-*\n"); + $finish; + end - bug5101 u_bug5101(.in0, .in1, .sel, .out); + bug5101 u_bug5101 ( + .in0, + .in1, + .sel, + .out + ); endmodule -module bug5101(input wire [1:0] in0, input wire [1:0] in1, input wire sel, output logic [1:0] out); - // verilator no_inline_module - function logic [1:0] incr(input [1:0] in); - logic [1:0] tmp; - tmp = in + 1; - return tmp; +module bug5101 ( + input wire [1:0] in0, + input wire [1:0] in1, + input wire sel, + output logic [1:0] out +); + // verilator no_inline_module + function logic [1:0] incr(input [1:0] in); + logic [1:0] tmp; + tmp = in + 1; + return tmp; endfunction always_comb - if (sel) out = in0; - else out = incr(in1); + if (sel) out = in0; + else out = incr(in1); endmodule diff --git a/test_regress/t/t_gate_ormux.v b/test_regress/t/t_gate_ormux.v index b061450a1..2f4047af3 100644 --- a/test_regress/t/t_gate_ormux.v +++ b/test_regress/t/t_gate_ormux.v @@ -5,263 +5,261 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - logic [31:0] rdata; - logic [31:0] rdata2; - wire [31:0] wdata = crc[31:0]; - wire [15:0] sel = {11'h0, crc[36:32]}; - wire we = crc[48]; + logic [31:0] rdata; + logic [31:0] rdata2; + wire [31:0] wdata = crc[31:0]; + wire [15:0] sel = {11'h0, crc[36:32]}; + wire we = crc[48]; - Test test (/*AUTOINST*/ - // Outputs - .rdata (rdata[31:0]), - .rdata2 (rdata2[31:0]), - // Inputs - .clk (clk), - .we (we), - .sel (sel[15:0]), - .wdata (wdata[31:0])); + Test test (/*AUTOINST*/ + // Outputs + .rdata (rdata[31:0]), + .rdata2 (rdata2[31:0]), + // Inputs + .clk (clk), + .we (we), + .sel (sel[15:0]), + .wdata (wdata[31:0])); - // 5.07 4.42 -> 13% - wire [63:0] result = {rdata2, rdata}; + // 5.07 4.42 -> 13% + wire [63:0] result = {rdata2, rdata}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (rdata2 != rdata) $stop; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (rdata2 != rdata) $stop; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h8977713eb467bc86 - if (sum !== `EXPECTED_SUM) $stop; - end - else if (cyc == `SIM_CYCLES) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + end + else if (cyc == `SIM_CYCLES) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test(/*AUTOARG*/ - // Outputs - rdata, rdata2, - // Inputs - clk, we, sel, wdata - ); - input clk; - input we; - input [15:0] sel; - input [31:0] wdata; - output logic [31:0] rdata; - output logic [31:0] rdata2; + // Outputs + rdata, rdata2, + // Inputs + clk, we, sel, wdata + ); + input clk; + input we; + input [15:0] sel; + input [31:0] wdata; + output logic [31:0] rdata; + output logic [31:0] rdata2; - logic we_d1r; - logic [15:0] sel_d1r; - logic [31:0] wdata_d1r; - always_ff @ (posedge clk) begin - we_d1r <= we; - sel_d1r <= sel; - wdata_d1r <= wdata; - end + logic we_d1r; + logic [15:0] sel_d1r; + logic [31:0] wdata_d1r; + always_ff @ (posedge clk) begin + we_d1r <= we; + sel_d1r <= sel; + wdata_d1r <= wdata; + end - reg [31:0] csr0000; - reg [31:0] csr0001; - reg [31:0] csr0002; - reg [31:0] csr0003; - reg [31:0] csr0004; - reg [31:0] csr0005; - reg [31:0] csr0006; - reg [31:0] csr0007; - reg [31:0] csr0008; - reg [31:0] csr0009; - reg [31:0] csr000a; - reg [31:0] csr000b; - reg [31:0] csr000c; - reg [31:0] csr000d; - reg [31:0] csr000e; - reg [31:0] csr000f; - wire [31:0] csr0010 = 32'h33675230; - wire [31:0] csr0011 = 32'h00fa2144; - wire [31:0] csr0012 = 32'h6a5e8e10; - wire [31:0] csr0013 = 32'h000a5b5e; - wire [31:0] csr0014 = 32'h002fe51b; - wire [31:0] csr0015 = 32'h00027e00; - wire [31:0] csr0016 = 32'h0000e3c0; - wire [31:0] csr0017 = 32'h00efcf16; - wire [31:0] csr0018 = 32'h007a2600; - wire [31:0] csr0019 = 32'h0a4a9f10; - wire [31:0] csr001a = 32'h7d789de3; - wire [31:0] csr001b = 32'h40f655f9; - wire [31:0] csr001c = 32'hadad01f4; - wire [31:0] csr001d = 32'h02e7b33c; - wire [31:0] csr001e = 32'h12101533; - wire [31:0] csr001f = 32'h2cc1cce5; - initial begin - csr0000 = 32'he172d365; - csr0001 = 32'h35cc25e2; - csr0002 = 32'haf48436e; - csr0003 = 32'h135e55e4; - csr0004 = 32'h5fd6e48a; - csr0005 = 32'hb07d34ad; - csr0006 = 32'h2aa05deb; - csr0007 = 32'hfe97b680; - csr0008 = 32'h960f20bb; - csr0009 = 32'h251129f0; - csr000a = 32'hef3d2f93; - csr000b = 32'hef4bc127; - csr000c = 32'h3dfecb10; - csr000d = 32'h1b4690f5; - csr000e = 32'ha07822ab; - csr000f = 32'hf817cbf6; - end + reg [31:0] csr0000; + reg [31:0] csr0001; + reg [31:0] csr0002; + reg [31:0] csr0003; + reg [31:0] csr0004; + reg [31:0] csr0005; + reg [31:0] csr0006; + reg [31:0] csr0007; + reg [31:0] csr0008; + reg [31:0] csr0009; + reg [31:0] csr000a; + reg [31:0] csr000b; + reg [31:0] csr000c; + reg [31:0] csr000d; + reg [31:0] csr000e; + reg [31:0] csr000f; + wire [31:0] csr0010 = 32'h33675230; + wire [31:0] csr0011 = 32'h00fa2144; + wire [31:0] csr0012 = 32'h6a5e8e10; + wire [31:0] csr0013 = 32'h000a5b5e; + wire [31:0] csr0014 = 32'h002fe51b; + wire [31:0] csr0015 = 32'h00027e00; + wire [31:0] csr0016 = 32'h0000e3c0; + wire [31:0] csr0017 = 32'h00efcf16; + wire [31:0] csr0018 = 32'h007a2600; + wire [31:0] csr0019 = 32'h0a4a9f10; + wire [31:0] csr001a = 32'h7d789de3; + wire [31:0] csr001b = 32'h40f655f9; + wire [31:0] csr001c = 32'hadad01f4; + wire [31:0] csr001d = 32'h02e7b33c; + wire [31:0] csr001e = 32'h12101533; + wire [31:0] csr001f = 32'h2cc1cce5; + initial begin + csr0000 = 32'he172d365; + csr0001 = 32'h35cc25e2; + csr0002 = 32'haf48436e; + csr0003 = 32'h135e55e4; + csr0004 = 32'h5fd6e48a; + csr0005 = 32'hb07d34ad; + csr0006 = 32'h2aa05deb; + csr0007 = 32'hfe97b680; + csr0008 = 32'h960f20bb; + csr0009 = 32'h251129f0; + csr000a = 32'hef3d2f93; + csr000b = 32'hef4bc127; + csr000c = 32'h3dfecb10; + csr000d = 32'h1b4690f5; + csr000e = 32'ha07822ab; + csr000f = 32'hf817cbf6; + end - always_ff @ (posedge clk) begin - if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; - end + always_ff @ (posedge clk) begin + if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; + end - wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - assign rdata = (32'h0 - | {32{dec0000}} & csr0000 - | {32{dec0001}} & csr0001 - | {32{dec0002}} & csr0002 - | {32{dec0003}} & csr0003 - | {32{dec0004}} & csr0004 - | {32{dec0005}} & csr0005 - | {32{dec0006}} & csr0006 - | {32{dec0007}} & csr0007 - | {32{dec0008}} & csr0008 - | {32{dec0009}} & csr0009 - | {32{dec000a}} & csr000a - | {32{dec000b}} & csr000b - | {32{dec000c}} & csr000c - | {32{dec000d}} & csr000d - | {32{dec000e}} & csr000e - | {32{dec000f}} & csr000f - | {32{dec0010}} & csr0010 - | {32{dec0011}} & csr0011 - | {32{dec0012}} & csr0012 - | {32{dec0013}} & csr0013 - | {32{dec0014}} & csr0014 - | {32{dec0015}} & csr0015 - | {32{dec0016}} & csr0016 - | {32{dec0017}} & csr0017 - | {32{dec0018}} & csr0018 - | {32{dec0019}} & csr0019 - | {32{dec001a}} & csr001a - | {32{dec001b}} & csr001b - | {32{dec001c}} & csr001c - | {32{dec001d}} & csr001d - | {32{dec001e}} & csr001e - | {32{dec001f}} & csr001f - ); + assign rdata = (32'h0 + | {32{dec0000}} & csr0000 + | {32{dec0001}} & csr0001 + | {32{dec0002}} & csr0002 + | {32{dec0003}} & csr0003 + | {32{dec0004}} & csr0004 + | {32{dec0005}} & csr0005 + | {32{dec0006}} & csr0006 + | {32{dec0007}} & csr0007 + | {32{dec0008}} & csr0008 + | {32{dec0009}} & csr0009 + | {32{dec000a}} & csr000a + | {32{dec000b}} & csr000b + | {32{dec000c}} & csr000c + | {32{dec000d}} & csr000d + | {32{dec000e}} & csr000e + | {32{dec000f}} & csr000f + | {32{dec0010}} & csr0010 + | {32{dec0011}} & csr0011 + | {32{dec0012}} & csr0012 + | {32{dec0013}} & csr0013 + | {32{dec0014}} & csr0014 + | {32{dec0015}} & csr0015 + | {32{dec0016}} & csr0016 + | {32{dec0017}} & csr0017 + | {32{dec0018}} & csr0018 + | {32{dec0019}} & csr0019 + | {32{dec001a}} & csr001a + | {32{dec001b}} & csr001b + | {32{dec001c}} & csr001c + | {32{dec001d}} & csr001d + | {32{dec001e}} & csr001e + | {32{dec001f}} & csr001f + ); - always_comb begin - case (sel_d1r) - 16'h0000: rdata2 = csr0000; - 16'h0001: rdata2 = csr0001; - 16'h0002: rdata2 = csr0002; - 16'h0003: rdata2 = csr0003; - 16'h0004: rdata2 = csr0004; - 16'h0005: rdata2 = csr0005; - 16'h0006: rdata2 = csr0006; - 16'h0007: rdata2 = csr0007; - 16'h0008: rdata2 = csr0008; - 16'h0009: rdata2 = csr0009; - 16'h000a: rdata2 = csr000a; - 16'h000b: rdata2 = csr000b; - 16'h000c: rdata2 = csr000c; - 16'h000d: rdata2 = csr000d; - 16'h000e: rdata2 = csr000e; - 16'h000f: rdata2 = csr000f; - 16'h0010: rdata2 = csr0010; - 16'h0011: rdata2 = csr0011; - 16'h0012: rdata2 = csr0012; - 16'h0013: rdata2 = csr0013; - 16'h0014: rdata2 = csr0014; - 16'h0015: rdata2 = csr0015; - 16'h0016: rdata2 = csr0016; - 16'h0017: rdata2 = csr0017; - 16'h0018: rdata2 = csr0018; - 16'h0019: rdata2 = csr0019; - 16'h001a: rdata2 = csr001a; - 16'h001b: rdata2 = csr001b; - 16'h001c: rdata2 = csr001c; - 16'h001d: rdata2 = csr001d; - 16'h001e: rdata2 = csr001e; - 16'h001f: rdata2 = csr001f; - default: rdata2 = 0; - endcase - end + always_comb begin + case (sel_d1r) + 16'h0000: rdata2 = csr0000; + 16'h0001: rdata2 = csr0001; + 16'h0002: rdata2 = csr0002; + 16'h0003: rdata2 = csr0003; + 16'h0004: rdata2 = csr0004; + 16'h0005: rdata2 = csr0005; + 16'h0006: rdata2 = csr0006; + 16'h0007: rdata2 = csr0007; + 16'h0008: rdata2 = csr0008; + 16'h0009: rdata2 = csr0009; + 16'h000a: rdata2 = csr000a; + 16'h000b: rdata2 = csr000b; + 16'h000c: rdata2 = csr000c; + 16'h000d: rdata2 = csr000d; + 16'h000e: rdata2 = csr000e; + 16'h000f: rdata2 = csr000f; + 16'h0010: rdata2 = csr0010; + 16'h0011: rdata2 = csr0011; + 16'h0012: rdata2 = csr0012; + 16'h0013: rdata2 = csr0013; + 16'h0014: rdata2 = csr0014; + 16'h0015: rdata2 = csr0015; + 16'h0016: rdata2 = csr0016; + 16'h0017: rdata2 = csr0017; + 16'h0018: rdata2 = csr0018; + 16'h0019: rdata2 = csr0019; + 16'h001a: rdata2 = csr001a; + 16'h001b: rdata2 = csr001b; + 16'h001c: rdata2 = csr001c; + 16'h001d: rdata2 = csr001d; + 16'h001e: rdata2 = csr001e; + 16'h001f: rdata2 = csr001f; + default: rdata2 = 0; + endcase + end endmodule diff --git a/test_regress/t/t_gate_primitives_implicit_net.out b/test_regress/t/t_gate_primitives_implicit_net.out index 61abfe8bc..a32e7f254 100644 --- a/test_regress/t/t_gate_primitives_implicit_net.out +++ b/test_regress/t/t_gate_primitives_implicit_net.out @@ -1,214 +1,214 @@ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:20: Signal definition not found, creating implicitly: 'i_and1' - 18 | and g_and(o_and, i_and1, i_and2, i_and3), +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:20: Signal definition not found, creating implicitly: 'i_and1' + 19 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:28: Signal definition not found, creating implicitly: 'i_and2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:28: Signal definition not found, creating implicitly: 'i_and2' : ... Suggested alternative: 'i_and1' - 18 | and g_and(o_and, i_and1, i_and2, i_and3), + 19 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:36: Signal definition not found, creating implicitly: 'i_and3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:36: Signal definition not found, creating implicitly: 'i_and3' : ... Suggested alternative: 'i_and1' - 18 | and g_and(o_and, i_and1, i_and2, i_and3), + 19 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:13: Signal definition not found, creating implicitly: 'o_and' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:13: Signal definition not found, creating implicitly: 'o_and' : ... Suggested alternative: 'i_and1' - 18 | and g_and(o_and, i_and1, i_and2, i_and3), + 19 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:11: Signal definition not found, creating implicitly: 'o2_and' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:11: Signal definition not found, creating implicitly: 'o2_and' : ... Suggested alternative: 'o_and' - 19 | g2_and(o2_and, i_and1, i_and2, i_and3); + 20 | g2_and(o2_and, i_and1, i_and2, i_and3); | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_not1' - 20 | not g_not(o_not1, o_not2, i_not1), +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:29: Signal definition not found, creating implicitly: 'i_not1' + 21 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:13: Signal definition not found, creating implicitly: 'o_not1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:13: Signal definition not found, creating implicitly: 'o_not1' : ... Suggested alternative: 'i_not1' - 20 | not g_not(o_not1, o_not2, i_not1), + 21 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'o_not2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:21: Signal definition not found, creating implicitly: 'o_not2' : ... Suggested alternative: 'o_not1' - 20 | not g_not(o_not1, o_not2, i_not1), + 21 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:11: Signal definition not found, creating implicitly: 'o2_not1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:11: Signal definition not found, creating implicitly: 'o2_not1' : ... Suggested alternative: 'o_not1' - 21 | g2_not(o2_not1, o_not2, i_not1); + 22 | g2_not(o2_not1, o_not2, i_not1); | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:20: Signal definition not found, creating implicitly: 'i_nor1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:20: Signal definition not found, creating implicitly: 'i_nor1' : ... Suggested alternative: 'i_not1' - 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + 23 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:28: Signal definition not found, creating implicitly: 'i_nor2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:28: Signal definition not found, creating implicitly: 'i_nor2' : ... Suggested alternative: 'i_nor1' - 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + 23 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:36: Signal definition not found, creating implicitly: 'i_nor3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:36: Signal definition not found, creating implicitly: 'i_nor3' : ... Suggested alternative: 'i_nor1' - 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + 23 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:13: Signal definition not found, creating implicitly: 'o_nor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:13: Signal definition not found, creating implicitly: 'o_nor' : ... Suggested alternative: 'i_nor1' - 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + 23 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:11: Signal definition not found, creating implicitly: 'o2_nor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o2_nor' : ... Suggested alternative: 'o_nor' - 23 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); + 24 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:17: Signal definition not found, creating implicitly: 'i_or1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:17: Signal definition not found, creating implicitly: 'i_or1' : ... Suggested alternative: 'i_nor1' - 24 | or g_or(o_or, i_or1, i_or2, i_or3), + 25 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:24: Signal definition not found, creating implicitly: 'i_or2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:24: Signal definition not found, creating implicitly: 'i_or2' : ... Suggested alternative: 'i_nor2' - 24 | or g_or(o_or, i_or1, i_or2, i_or3), + 25 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:31: Signal definition not found, creating implicitly: 'i_or3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:31: Signal definition not found, creating implicitly: 'i_or3' : ... Suggested alternative: 'i_nor3' - 24 | or g_or(o_or, i_or1, i_or2, i_or3), + 25 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o_or' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:11: Signal definition not found, creating implicitly: 'o_or' : ... Suggested alternative: 'o_nor' - 24 | or g_or(o_or, i_or1, i_or2, i_or3), + 25 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:10: Signal definition not found, creating implicitly: 'o2_or' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:10: Signal definition not found, creating implicitly: 'o2_or' : ... Suggested alternative: 'o2_nor' - 25 | g2_or(o2_or, i_or1, i_or2, i_or3); + 26 | g2_or(o2_or, i_or1, i_or2, i_or3); | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:23: Signal definition not found, creating implicitly: 'i_nand1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:23: Signal definition not found, creating implicitly: 'i_nand1' : ... Suggested alternative: 'i_and1' - 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + 27 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:32: Signal definition not found, creating implicitly: 'i_nand2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:32: Signal definition not found, creating implicitly: 'i_nand2' : ... Suggested alternative: 'i_and2' - 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + 27 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_nand3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:41: Signal definition not found, creating implicitly: 'i_nand3' : ... Suggested alternative: 'i_and3' - 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + 27 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:15: Signal definition not found, creating implicitly: 'o_nand' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:15: Signal definition not found, creating implicitly: 'o_nand' : ... Suggested alternative: 'o_and' - 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + 27 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:12: Signal definition not found, creating implicitly: 'o2_nand' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:12: Signal definition not found, creating implicitly: 'o2_nand' : ... Suggested alternative: 'o2_and' - 27 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); + 28 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:20: Signal definition not found, creating implicitly: 'i_xor1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:20: Signal definition not found, creating implicitly: 'i_xor1' : ... Suggested alternative: 'i_nor1' - 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + 29 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:28: Signal definition not found, creating implicitly: 'i_xor2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:28: Signal definition not found, creating implicitly: 'i_xor2' : ... Suggested alternative: 'i_nor2' - 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + 29 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:36: Signal definition not found, creating implicitly: 'i_xor3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:36: Signal definition not found, creating implicitly: 'i_xor3' : ... Suggested alternative: 'i_nor3' - 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + 29 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:13: Signal definition not found, creating implicitly: 'o_xor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:13: Signal definition not found, creating implicitly: 'o_xor' : ... Suggested alternative: 'o_nor' - 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + 29 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:11: Signal definition not found, creating implicitly: 'o2_xor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:11: Signal definition not found, creating implicitly: 'o2_xor' : ... Suggested alternative: 'o2_nor' - 29 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); + 30 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:22: Signal definition not found, creating implicitly: 'i_xnor1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:22: Signal definition not found, creating implicitly: 'i_xnor1' : ... Suggested alternative: 'i_nor1' - 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + 31 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:31: Signal definition not found, creating implicitly: 'i_xnor2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:31: Signal definition not found, creating implicitly: 'i_xnor2' : ... Suggested alternative: 'i_nor2' - 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + 31 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:40: Signal definition not found, creating implicitly: 'i_xnor3' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:40: Signal definition not found, creating implicitly: 'i_xnor3' : ... Suggested alternative: 'i_nor3' - 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + 31 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:14: Signal definition not found, creating implicitly: 'o_xnor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:14: Signal definition not found, creating implicitly: 'o_xnor' : ... Suggested alternative: 'o_nor' - 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + 31 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:11: Signal definition not found, creating implicitly: 'o2_xnor' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:11: Signal definition not found, creating implicitly: 'o2_xnor' : ... Suggested alternative: 'o2_nor' - 31 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); + 32 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:29: Signal definition not found, creating implicitly: 'i_buf1' - 32 | buf g_buf(o_buf1, o_buf2, i_buf1), +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:29: Signal definition not found, creating implicitly: 'i_buf1' + 33 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:13: Signal definition not found, creating implicitly: 'o_buf1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:13: Signal definition not found, creating implicitly: 'o_buf1' : ... Suggested alternative: 'i_buf1' - 32 | buf g_buf(o_buf1, o_buf2, i_buf1), + 33 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:21: Signal definition not found, creating implicitly: 'o_buf2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:21: Signal definition not found, creating implicitly: 'o_buf2' : ... Suggested alternative: 'o_buf1' - 32 | buf g_buf(o_buf1, o_buf2, i_buf1), + 33 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:11: Signal definition not found, creating implicitly: 'o2_buf1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:11: Signal definition not found, creating implicitly: 'o2_buf1' : ... Suggested alternative: 'o_buf1' - 33 | g2_buf(o2_buf1, o_buf2, i_buf1); + 34 | g2_buf(o2_buf1, o_buf2, i_buf1); | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:40: Signal definition not found, creating implicitly: 'i_bufif02' - 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:40: Signal definition not found, creating implicitly: 'i_bufif02' + 35 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:29: Signal definition not found, creating implicitly: 'i_bufif01' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:29: Signal definition not found, creating implicitly: 'i_bufif01' : ... Suggested alternative: 'i_bufif02' - 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + 35 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:19: Signal definition not found, creating implicitly: 'o_bufif0' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:19: Signal definition not found, creating implicitly: 'o_bufif0' : ... Suggested alternative: 'i_bufif01' - 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + 35 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:14: Signal definition not found, creating implicitly: 'o2_bufif0' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:14: Signal definition not found, creating implicitly: 'o2_bufif0' : ... Suggested alternative: 'o_bufif0' - 35 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); + 36 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:40: Signal definition not found, creating implicitly: 'i_bufif12' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:40: Signal definition not found, creating implicitly: 'i_bufif12' : ... Suggested alternative: 'i_bufif02' - 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + 37 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:29: Signal definition not found, creating implicitly: 'i_bufif11' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:29: Signal definition not found, creating implicitly: 'i_bufif11' : ... Suggested alternative: 'i_bufif01' - 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + 37 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:19: Signal definition not found, creating implicitly: 'o_bufif1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:19: Signal definition not found, creating implicitly: 'o_bufif1' : ... Suggested alternative: 'o_bufif0' - 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + 37 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:14: Signal definition not found, creating implicitly: 'o2_bufif1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:14: Signal definition not found, creating implicitly: 'o2_bufif1' : ... Suggested alternative: 'o2_bufif0' - 37 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); + 38 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:40: Signal definition not found, creating implicitly: 'i_notif02' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:40: Signal definition not found, creating implicitly: 'i_notif02' : ... Suggested alternative: 'i_bufif02' - 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + 39 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:29: Signal definition not found, creating implicitly: 'i_notif01' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:29: Signal definition not found, creating implicitly: 'i_notif01' : ... Suggested alternative: 'i_notif02' - 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + 39 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:19: Signal definition not found, creating implicitly: 'o_notif0' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:19: Signal definition not found, creating implicitly: 'o_notif0' : ... Suggested alternative: 'i_notif01' - 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + 39 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:14: Signal definition not found, creating implicitly: 'o2_notif0' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:14: Signal definition not found, creating implicitly: 'o2_notif0' : ... Suggested alternative: 'o_notif0' - 39 | g2_notif0(o2_notif0, i_notif01, i_notif02); + 40 | g2_notif0(o2_notif0, i_notif01, i_notif02); | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:40: Signal definition not found, creating implicitly: 'i_notif12' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:40: Signal definition not found, creating implicitly: 'i_notif12' : ... Suggested alternative: 'i_notif02' - 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + 41 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:29: Signal definition not found, creating implicitly: 'i_notif11' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:29: Signal definition not found, creating implicitly: 'i_notif11' : ... Suggested alternative: 'i_notif01' - 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + 41 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:19: Signal definition not found, creating implicitly: 'o_notif1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:19: Signal definition not found, creating implicitly: 'o_notif1' : ... Suggested alternative: 'o_notif0' - 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + 41 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:14: Signal definition not found, creating implicitly: 'o2_notif1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:42:14: Signal definition not found, creating implicitly: 'o2_notif1' : ... Suggested alternative: 'o2_notif0' - 41 | g2_notif1(o2_notif1, i_notif11, i_notif12); + 42 | g2_notif1(o2_notif1, i_notif11, i_notif12); | ^~~~~~~~~ diff --git a/test_regress/t/t_gate_primitives_implicit_net.v b/test_regress/t/t_gate_primitives_implicit_net.v index f3bf1f44e..13af6e38f 100644 --- a/test_regress/t/t_gate_primitives_implicit_net.v +++ b/test_regress/t/t_gate_primitives_implicit_net.v @@ -9,6 +9,7 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on +// verilog_format: off module t( input clk ); diff --git a/test_regress/t/t_gate_strength.v b/test_regress/t/t_gate_strength.v index d9b1805dc..0333f098d 100644 --- a/test_regress/t/t_gate_strength.v +++ b/test_regress/t/t_gate_strength.v @@ -4,72 +4,70 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; - integer cyc; initial cyc=1; + integer cyc; initial cyc=1; - logic [31:0] a; + logic [31:0] a; - // verilator lint_off IMPLICIT - assign (highz0, supply1) nt00 = a[0]; - assign (supply0, highz1) nt01 = a[0]; - assign (supply0, supply1) nt02 = a[0]; - assign (strong0, strong1) nt03 = a[0]; - assign (pull0, pull1) nt04 = a[0]; - assign (weak0, weak1) nt05 = a[0]; + // verilator lint_off IMPLICIT + assign (highz0, supply1) nt00 = a[0]; + assign (supply0, highz1) nt01 = a[0]; + assign (supply0, supply1) nt02 = a[0]; + assign (strong0, strong1) nt03 = a[0]; + assign (pull0, pull1) nt04 = a[0]; + assign (weak0, weak1) nt05 = a[0]; - assign (highz0, supply1) nt10 = a[0]; - assign (supply0, highz1) nt11 = a[0]; - assign (supply0, supply1) nt12 = a[0]; - assign (strong0, strong1) nt13 = a[0]; - assign (pull0, pull1) nt14 = a[0]; - assign (weak0, weak1) nt15 = a[0]; - // verilator lint_on IMPLICIT + assign (highz0, supply1) nt10 = a[0]; + assign (supply0, highz1) nt11 = a[0]; + assign (supply0, supply1) nt12 = a[0]; + assign (strong0, strong1) nt13 = a[0]; + assign (pull0, pull1) nt14 = a[0]; + assign (weak0, weak1) nt15 = a[0]; + // verilator lint_on IMPLICIT - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 32'h18f6b030; - end - if (cyc==2) begin - a <= 32'h18f6b03f; - if (nt00 !== 1'b0) $stop; - if (nt01 !== 1'b0) $stop; - if (nt02 !== 1'b0) $stop; - if (nt03 !== 1'b0) $stop; - if (nt04 !== 1'b0) $stop; - if (nt05 !== 1'b0) $stop; - if (nt10 !== 1'b0) $stop; - if (nt11 !== 1'b0) $stop; - if (nt12 !== 1'b0) $stop; - if (nt13 !== 1'b0) $stop; - if (nt14 !== 1'b0) $stop; - if (nt15 !== 1'b0) $stop; - end - if (cyc==3) begin - if (nt00 !== 1'b1) $stop; - if (nt01 !== 1'b1) $stop; - if (nt02 !== 1'b1) $stop; - if (nt03 !== 1'b1) $stop; - if (nt04 !== 1'b1) $stop; - if (nt05 !== 1'b1) $stop; - if (nt10 !== 1'b1) $stop; - if (nt11 !== 1'b1) $stop; - if (nt12 !== 1'b1) $stop; - if (nt13 !== 1'b1) $stop; - if (nt14 !== 1'b1) $stop; - if (nt15 !== 1'b1) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 32'h18f6b030; end - end + if (cyc==2) begin + a <= 32'h18f6b03f; + if (nt00 !== 1'b0) $stop; + if (nt01 !== 1'b0) $stop; + if (nt02 !== 1'b0) $stop; + if (nt03 !== 1'b0) $stop; + if (nt04 !== 1'b0) $stop; + if (nt05 !== 1'b0) $stop; + if (nt10 !== 1'b0) $stop; + if (nt11 !== 1'b0) $stop; + if (nt12 !== 1'b0) $stop; + if (nt13 !== 1'b0) $stop; + if (nt14 !== 1'b0) $stop; + if (nt15 !== 1'b0) $stop; + end + if (cyc==3) begin + if (nt00 !== 1'b1) $stop; + if (nt01 !== 1'b1) $stop; + if (nt02 !== 1'b1) $stop; + if (nt03 !== 1'b1) $stop; + if (nt04 !== 1'b1) $stop; + if (nt05 !== 1'b1) $stop; + if (nt10 !== 1'b1) $stop; + if (nt11 !== 1'b1) $stop; + if (nt12 !== 1'b1) $stop; + if (nt13 !== 1'b1) $stop; + if (nt14 !== 1'b1) $stop; + if (nt15 !== 1'b1) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_gate_unsup.v b/test_regress/t/t_gate_unsup.v index 357e72b33..2cf8c0723 100644 --- a/test_regress/t/t_gate_unsup.v +++ b/test_regress/t/t_gate_unsup.v @@ -6,29 +6,29 @@ module t; - wire d, en, nc, pc; + wire d, en, nc, pc; - // verilator lint_off IMPLICIT - cmos (cm0, d, nc, pc); - rcmos (rc0, d, nc, pc); + // verilator lint_off IMPLICIT + cmos (cm0, d, nc, pc); + rcmos (rc0, d, nc, pc); - nmos (nm0, d, en); - pmos (pm0, d, en); - rnmos (rn0, d, en); - rpmos (rp0, d, en); + nmos (nm0, d, en); + pmos (pm0, d, en); + rnmos (rn0, d, en); + rpmos (rp0, d, en); - rtran (rt0, d); - tran (tr0, d); + rtran (rt0, d); + tran (tr0, d); - rtranif0 (r00, d, en); - rtranif1 (r10, d, en); - tranif0 (t00, d, en); - tranif1 (t10, d, en); - // verilator lint_on IMPLICIT + rtranif0 (r00, d, en); + rtranif1 (r10, d, en); + tranif0 (t00, d, en); + tranif1 (t10, d, en); + // verilator lint_on IMPLICIT - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_gen_alw.v b/test_regress/t/t_gen_alw.v index 517e8f9d7..32e125678 100644 --- a/test_regress/t/t_gen_alw.v +++ b/test_regress/t/t_gen_alw.v @@ -3,94 +3,92 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk + ); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [9:0] in = crc[9:0]; + // Take CRC data and apply to testblock inputs + wire [9:0] in = crc[9:0]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - Test test (// Outputs - .a(), - .b(), - /*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[9:0])); + Test test (// Outputs + .a(), + .b(), + /*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[9:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {64'h0}; + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test (/*AUTOARG*/ - // Outputs - a, b, - // Inputs - clk, in - ); - /*verilator hier_block*/ - input clk; - input [9:0] in; + // Outputs + a, b, + // Inputs + clk, in + ); + /*verilator hier_block*/ + input clk; + input [9:0] in; - output reg a [9:0]; - integer ai; - always @* begin - for (ai=0;ai<10;ai=ai+1) begin - a[ai]=in[ai]; + output reg a [9:0]; + integer ai; + always @* begin + for (ai=0;ai<10;ai=ai+1) begin + a[ai]=in[ai]; + end + end + + output reg [1:0] b [9:0]; + integer j; + + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + for (j=0; j<10; j=j+1) begin + if (a[j]) + b[i][j] <= 1'b0; + else + b[i][j] <= 1'b1; + end end - end - - output reg [1:0] b [9:0]; - integer j; - - generate - genvar i; - for (i=0; i<2; i=i+1) begin - always @(posedge clk) begin - for (j=0; j<10; j=j+1) begin - if (a[j]) - b[i][j] <= 1'b0; - else - b[i][j] <= 1'b1; - end - end - end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v index 33ce5aa84..70803aab8 100644 --- a/test_regress/t/t_gen_assign.v +++ b/test_regress/t/t_gen_assign.v @@ -5,57 +5,59 @@ `timescale 1ns / 1ps -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; + reg [63:0] crc; + reg [31:0] sum; - integer cyc; initial cyc = 0; - reg [63:0] crc; - reg [31:0] sum; + wire [8:0] Output; + wire [8:0] Input = crc[8:0]; - wire [8:0] Output; - wire [8:0] Input = crc[8:0]; + assigns assigns ( /*AUTOINST*/ + // Outputs + .Output(Output[8:0]), + // Inputs + .Input(Input[8:0]) + ); - assigns assigns (/*AUTOINST*/ - // Outputs - .Output (Output[8:0]), - // Inputs - .Input (Input[8:0])); - - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); + $write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 32'h0; - end - else if (cyc>10 && cyc<90) begin - sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; - end - else if (cyc==99) begin - if (sum !== 32'he8bbd130) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; + end + else if (cyc > 10 && cyc < 90) begin + sum <= {sum[30:0], sum[31]} ^ {23'h0, crc[8:0]}; + end + else if (cyc == 99) begin + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module assigns(Input, Output); - input [8:0] Input; - output [8:0] Output; +module assigns ( + Input, + Output +); + input [8:0] Input; + output [8:0] Output; - genvar i; - generate - for (i = 0; i < 8; i = i + 1) begin : ap - assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; - end - endgenerate + genvar i; + generate + for (i = 0; i < 8; i = i + 1) begin : ap + assign Output[(i>0)?i-1 : 8] = Input[(i>0)?i-1 : 8]; + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_class.v b/test_regress/t/t_gen_class.v index 02bb776f2..b192bee2a 100644 --- a/test_regress/t/t_gen_class.v +++ b/test_regress/t/t_gen_class.v @@ -11,59 +11,59 @@ // verilog_format: on module Child; - int ch_value; + int ch_value; endmodule module Parent; - for (genvar i = 0; i < 10; i++) begin : gen_child - Child child(); - end + for (genvar i = 0; i < 10; i++) begin : gen_child + Child child (); + end endmodule module t; - Parent parent(); + Parent parent (); - virtual class ChildAgentBase; - pure virtual task preload(int value); - pure virtual function string name(); - endclass + virtual class ChildAgentBase; + pure virtual task preload(int value); + pure virtual function string name(); + endclass - ChildAgentBase child_agents[10]; + ChildAgentBase child_agents[10]; - for (genvar i = 0; i < 10; i++) begin : gfor - class ChildAgent extends ChildAgentBase; - task automatic preload(int value); - parent.gen_child[i].child.ch_value = value; - endtask - function string name(); - return $sformatf("%m"); - endfunction - endclass + for (genvar i = 0; i < 10; i++) begin : gfor + class ChildAgent extends ChildAgentBase; + task automatic preload(int value); + parent.gen_child[i].child.ch_value = value; + endtask + function string name(); + return $sformatf("%m"); + endfunction + endclass - ChildAgent agent = new(); + ChildAgent agent = new(); - initial child_agents[i] = agent; - end + initial child_agents[i] = agent; + end - task automatic preload_children; - for (int i = 0; i < 10; i++) begin - child_agents[i].preload(i); - end - endtask + task automatic preload_children; + for (int i = 0; i < 10; i++) begin + child_agents[i].preload(i); + end + endtask - string s; + string s; - initial begin - #1; // Ensure all class instances are initialized - preload_children(); - `checkh(parent.gen_child[3].child.ch_value, 3); - `checkh(parent.gen_child[8].child.ch_value, 8); + initial begin + #1; // Ensure all class instances are initialized + preload_children(); + `checkh(parent.gen_child[3].child.ch_value, 3); + `checkh(parent.gen_child[8].child.ch_value, 8); `ifdef VERILATOR - // Some legal examples "t.gfor[4].\ChildAgent::name", "t.gfor[4].ChildAgent.name" - `checks(child_agents[4].name(), "t.gfor[4].ChildAgent.name"); + // Some legal examples "t.gfor[4].\ChildAgent::name", "t.gfor[4].ChildAgent.name" + `checks(child_agents[4].name(), "t.gfor[4].ChildAgent.name"); `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_gen_cond_bitrange.v b/test_regress/t/t_gen_cond_bitrange.v index 1e90d2603..73f3fd0a0 100644 --- a/test_regress/t/t_gen_cond_bitrange.v +++ b/test_regress/t/t_gen_cond_bitrange.v @@ -8,132 +8,126 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -`define MAX_SIZE 4 +`define MAX_SIZE 4 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // Set the parameters, so that we use a size less than MAX_SIZE - test_gen - #(.SIZE (2), - .MASK (2'b11)) - i_test_gen (.clk (clk)); + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen #( + .SIZE(2), + .MASK(2'b11) + ) i_test_gen ( + .clk(clk) + ); - // This is only a compilation test, but for good measure we do one clock - // cycle. - integer count; + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; - initial begin - count = 0; - end + initial begin + count = 0; + end - always @(posedge clk) begin - if (count == 1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - count = count + 1; - end - end + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end -endmodule // t +endmodule // t -module test_gen +module test_gen #( + parameter SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0 +) ( + input clk +); - #( parameter - SIZE = `MAX_SIZE, - MASK = `MAX_SIZE'b0) + // Generate blocks that rely on short-circuiting of the logic to avoid errors. + generate + genvar g; - (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - // Generate blocks that rely on short-circuiting of the logic to avoid errors. - generate - genvar g; - - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ((g < SIZE) && MASK[g]) begin - always @(posedge clk) begin + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end end - endgenerate + end + endgenerate - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if (!((g >= SIZE) || ~MASK[g])) begin - always @(posedge clk) begin + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) || ~MASK[g])) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end end - endgenerate + end + endgenerate - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if (!((g < SIZE) -> ~MASK[g])) begin - always @(posedge clk) begin + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g < SIZE) -> ~MASK[g])) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end end - endgenerate + end + endgenerate - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ( g < SIZE ? MASK[g] : 1'b0) begin - always @(posedge clk) begin + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (g < SIZE ? MASK[g] : 1'b0) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end end - endgenerate + end + endgenerate - // The other way round - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ( g >= SIZE ? 1'b0 : MASK[g]) begin - always @(posedge clk) begin + // The other way round + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (g >= SIZE ? 1'b0 : MASK[g]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_cond_bitrange_bad.out b/test_regress/t/t_gen_cond_bitrange_bad.out index 47a9d3a71..c01885190 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.out +++ b/test_regress/t/t_gen_cond_bitrange_bad.out @@ -1,19 +1,19 @@ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58:38: Selection index out of range: 2:2 outside 1:0 +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:52:35: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' - 58 | if ((g < (SIZE + 1)) && MASK[g]) begin - | ^ + 52 | if ((g < (SIZE + 1)) && MASK[g]) begin + | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:64:29: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' - 70 | if ((g < SIZE) && MASK[g + 1]) begin + 64 | if ((g < SIZE) && MASK[g+1]) begin + | ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:77:30: Selection index out of range: 2:2 outside 1:0 + : ... note: In instance 't.i_test_gen' + 77 | if ((g < (SIZE)) & MASK[g]) begin + | ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:90:32: Selection index out of range: 2:2 outside 1:0 + : ... note: In instance 't.i_test_gen' + 90 | if (!((g >= SIZE) | ~MASK[g])) begin | ^ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83:33: Selection index out of range: 2:2 outside 1:0 - : ... note: In instance 't.i_test_gen' - 83 | if ((g < (SIZE)) & MASK[g]) begin - | ^ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96:35: Selection index out of range: 2:2 outside 1:0 - : ... note: In instance 't.i_test_gen' - 96 | if (!((g >= SIZE) | ~MASK[g])) begin - | ^ %Error: Exiting due to diff --git a/test_regress/t/t_gen_cond_bitrange_bad.v b/test_regress/t/t_gen_cond_bitrange_bad.v index 617cdf8c0..b1e140e2c 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.v +++ b/test_regress/t/t_gen_cond_bitrange_bad.v @@ -10,97 +10,91 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -`define MAX_SIZE 3 +`define MAX_SIZE 3 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // Set the parameters, so that we use a size less than MAX_SIZE - test_gen - #(.SIZE (2), - .MASK (2'b11)) - i_test_gen (.clk (clk)); + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen #( + .SIZE(2), + .MASK(2'b11) + ) i_test_gen ( + .clk(clk) + ); - // This is only a compilation test, so we can immediately finish - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // This is only a compilation test, so we can immediately finish + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end -endmodule // t +endmodule // t -module test_gen +module test_gen #( + parameter SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0 +) ( + input clk +); - #( parameter - SIZE = `MAX_SIZE, - MASK = `MAX_SIZE'b0) + // Generate blocks that all have errors in applying short-circuting to + // generate "if" conditionals. - (/*AUTOARG*/ - // Inputs - clk - ); + // Attempt to access invalid bits of MASK in different ways + generate + genvar g; - input clk; - - // Generate blocks that all have errors in applying short-circuting to - // generate "if" conditionals. - - // Attempt to access invalid bits of MASK in different ways - generate - genvar g; - - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ((g < (SIZE + 1)) && MASK[g]) begin - always @(posedge clk) begin + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE + 1)) && MASK[g]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - end - end + end end - endgenerate + end + endgenerate - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ((g < SIZE) && MASK[g + 1]) begin - always @(posedge clk) begin + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g+1]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - end - end + end end - endgenerate + end + endgenerate - // Attempt to short-circuit bitwise AND - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if ((g < (SIZE)) & MASK[g]) begin - always @(posedge clk) begin + // Attempt to short-circuit bitwise AND + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE)) & MASK[g]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - end - end + end end - endgenerate + end + endgenerate - // Attempt to short-circuit bitwise OR - generate - for (g = 0; g < `MAX_SIZE; g = g + 1) begin - if (!((g >= SIZE) | ~MASK[g])) begin - always @(posedge clk) begin + // Attempt to short-circuit bitwise OR + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) | ~MASK[g])) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]); + $write("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - end - end + end end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_cond_const.v b/test_regress/t/t_gen_cond_const.v index 3abd26625..ad66df7d0 100644 --- a/test_regress/t/t_gen_cond_const.v +++ b/test_regress/t/t_gen_cond_const.v @@ -8,65 +8,59 @@ // SPDX-License-Identifier: CC0-1.0 -`define MAX_SIZE 4 +`define MAX_SIZE 4 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // Set the parameters, so that we use a size less than MAX_SIZE - test_gen - #(.SIZE (2), - .MASK (4'b1111)) - i_test_gen (.clk (clk)); + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen #( + .SIZE(2), + .MASK(4'b1111) + ) i_test_gen ( + .clk(clk) + ); - // This is only a compilation test, but for good measure we do one clock - // cycle. - integer count; + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; - initial begin - count = 0; - end + initial begin + count = 0; + end - always @(posedge clk) begin - if (count == 1) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - count = count + 1; - end - end + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end -endmodule // t +endmodule // t -module test_gen +module test_gen #( + parameter SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0 +) ( + input clk +); - #( parameter - SIZE = `MAX_SIZE, - MASK = `MAX_SIZE'b0) - - (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - // Generate blocks that rely on short-circuiting of the logic to avoid - // errors. - generate - if ((SIZE < 8'h04) && MASK[0]) begin - always @(posedge clk) begin + // Generate blocks that rely on short-circuiting of the logic to avoid + // errors. + generate + if ((SIZE < 8'h04) && MASK[0]) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Generate IF MASK[0] = %d\n", MASK[0]); + $write("Generate IF MASK[0] = %d\n", MASK[0]); `endif - end end - endgenerate + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_defparam.v b/test_regress/t/t_gen_defparam.v index b2395a467..76aa4e6f6 100644 --- a/test_regress/t/t_gen_defparam.v +++ b/test_regress/t/t_gen_defparam.v @@ -4,41 +4,44 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - parameter PAR = 3; +module t ( + input clk +); - wire [31:0] o1a,o1b; + parameter PAR = 3; - m1 #(0) m1a(.o(o1a)); - m1 #(1) m1b(.o(o1b)); + wire [31:0] o1a, o1b; - always @ (posedge clk) begin - if (o1a != 8) $stop; - if (o1b != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + m1 #(0) m1a (.o(o1a)); + m1 #(1) m1b (.o(o1b)); + + always @(posedge clk) begin + if (o1a != 8) $stop; + if (o1b != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module m1 (output wire [31:0] o); - parameter W = 0; - generate - if (W == 0) begin - m2 m2 (.o(o)); - defparam m2.PAR2 = 8; - end - else begin - m2 m2 (.o(o)); - defparam m2.PAR2 = 4; - end - endgenerate +module m1 ( + output wire [31:0] o +); + parameter W = 0; + generate + if (W == 0) begin + m2 m2 (.o(o)); + defparam m2.PAR2 = 8; + end + else begin + m2 m2 (.o(o)); + defparam m2.PAR2 = 4; + end + endgenerate endmodule -module m2 (output wire [31:0] o); - parameter PAR2 = 10; - assign o = PAR2; +module m2 ( + output wire [31:0] o +); + parameter PAR2 = 10; + assign o = PAR2; endmodule diff --git a/test_regress/t/t_gen_defparam_bad.out b/test_regress/t/t_gen_defparam_bad.out index 2cf6e7073..9e73dcabe 100644 --- a/test_regress/t/t_gen_defparam_bad.out +++ b/test_regress/t/t_gen_defparam_bad.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:9:12: Unsupported: defparam with no dot - 9 | id_15 = id_14; - | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:9:11: Unsupported: defparam with no dot + 9 | id_15 = id_14; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:18: Unsupported: defparam with no dot - 11 | defparam id_8 = 1, id_9 = 1; - | ^ -%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:28: Unsupported: defparam with no dot - 11 | defparam id_8 = 1, id_9 = 1; - | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:17: Unsupported: defparam with no dot + 11 | defparam id_8 = 1, id_9 = 1; + | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:27: Unsupported: defparam with no dot + 11 | defparam id_8 = 1, id_9 = 1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_gen_defparam_bad.v b/test_regress/t/t_gen_defparam_bad.v index a1b265dc3..df4f080da 100644 --- a/test_regress/t/t_gen_defparam_bad.v +++ b/test_regress/t/t_gen_defparam_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - defparam id_13.id_14 = -id_13, - id_15 = id_14; + defparam id_13.id_14 = -id_13, + id_15 = id_14; - defparam id_8 = 1, id_9 = 1; + defparam id_8 = 1, id_9 = 1; endmodule diff --git a/test_regress/t/t_gen_defparam_nfound_bad.out b/test_regress/t/t_gen_defparam_nfound_bad.out index c00886c1b..765ef8bd1 100644 --- a/test_regress/t/t_gen_defparam_nfound_bad.out +++ b/test_regress/t/t_gen_defparam_nfound_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_gen_defparam_nfound_bad.v:9:17: In defparam, instance z never declared - 9 | defparam z.W = 3; - | ^ +%Error: t/t_gen_defparam_nfound_bad.v:9:16: In defparam, instance z never declared + 9 | defparam z.W = 3; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_gen_defparam_nfound_bad.v b/test_regress/t/t_gen_defparam_nfound_bad.v index b00bc1460..f5329d428 100644 --- a/test_regress/t/t_gen_defparam_nfound_bad.v +++ b/test_regress/t/t_gen_defparam_nfound_bad.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t; - a a (); - defparam z.W = 3; // Bad + a a (); + defparam z.W = 3; // Bad endmodule module a; - parameter W = 0; + parameter W = 0; endmodule diff --git a/test_regress/t/t_gen_div0.v b/test_regress/t/t_gen_div0.v index 050f2da30..fe21437f2 100644 --- a/test_regress/t/t_gen_div0.v +++ b/test_regress/t/t_gen_div0.v @@ -4,36 +4,34 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOINST*/); +module t; - Test #( - .BIT_WIDTH (72), - .BYTE_WIDTH (9) - ) + Test #( + .BIT_WIDTH(72), + .BYTE_WIDTH(9) + ) u_test_inst (); - u_test_inst(); - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module Test (); - parameter BIT_WIDTH = ""; - parameter BYTE_WIDTH = ""; + parameter BIT_WIDTH = ""; + parameter BYTE_WIDTH = ""; - localparam BYTES = BIT_WIDTH / BYTE_WIDTH; + localparam BYTES = BIT_WIDTH / BYTE_WIDTH; - wire [BYTES - 1:0] i; - wire [BYTES - 1:0] o; + wire [BYTES - 1:0] i; + wire [BYTES - 1:0] o; - genvar g; - generate - for (g = 0; g < BYTES; g = g + 1) begin: gen - assign o[g] = (i[g] !== 1'b0); - end - endgenerate + genvar g; + generate + for (g = 0; g < BYTES; g = g + 1) begin : gen + assign o[g] = (i[g] !== 1'b0); + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_duplicated_blocks_bad.out b/test_regress/t/t_gen_duplicated_blocks_bad.out index f4c6fd043..d27c4b462 100644 --- a/test_regress/t/t_gen_duplicated_blocks_bad.out +++ b/test_regress/t/t_gen_duplicated_blocks_bad.out @@ -1,16 +1,16 @@ -%Error: t/t_gen_duplicated_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block' +%Error: t/t_gen_duplicated_blocks_bad.v:11:11: Duplicate declaration of generate block: 'block' : ... note: In instance 't' - 11 | begin : block - | ^~~~~ - t/t_gen_duplicated_blocks_bad.v:9:12: ... Location of original declaration - 9 | begin : block - | ^~~~~ + 11 | begin : block + | ^~~~~ + t/t_gen_duplicated_blocks_bad.v:9:11: ... Location of original declaration + 9 | begin : block + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_gen_duplicated_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1' +%Error: t/t_gen_duplicated_blocks_bad.v:15:22: Duplicate declaration of generate block: 'block1' : ... note: In instance 't' - 15 | if (X > 1) begin : block1 - | ^~~~~~ - t/t_gen_duplicated_blocks_bad.v:13:23: ... Location of original declaration - 13 | if (X > 0) begin : block1 - | ^~~~~~ + 15 | if (X > 1) begin : block1 + | ^~~~~~ + t/t_gen_duplicated_blocks_bad.v:13:22: ... Location of original declaration + 13 | if (X > 0) begin : block1 + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_gen_duplicated_blocks_bad.v b/test_regress/t/t_gen_duplicated_blocks_bad.v index 67a430da2..78c44cf1a 100644 --- a/test_regress/t/t_gen_duplicated_blocks_bad.v +++ b/test_regress/t/t_gen_duplicated_blocks_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - parameter X = 2; - begin : block - end - begin : block - end - if (X > 0) begin : block1 - end - if (X > 1) begin : block1 - end + parameter X = 2; + begin : block + end + begin : block + end + if (X > 0) begin : block1 + end + if (X > 1) begin : block1 + end endmodule diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index 2deda7334..47d7ba1a7 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -4,170 +4,196 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - reg [7:0] crc; - genvar g; + integer cyc = 0; - wire [7:0] out_p1; - wire [15:0] out_p2; - wire [7:0] out_p3; - wire [7:0] out_p4; + reg [7:0] crc; + genvar g; - paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); - paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); - paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); - gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); + wire [7:0] out_p1; + wire [15:0] out_p2; + wire [7:0] out_p3; + wire [7:0] out_p4; - wire [7:0] out_ef; - enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); + // verilog_format: off + paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); + paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); + paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); + gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); - cyc <= cyc + 1; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==0) begin - // Setup - crc <= 8'hed; - end - else if (cyc==1) begin - end - else if (cyc==3) begin - if (out_p1 !== 8'h2d) $stop; - if (out_p2 !== 16'h2d2d) $stop; - if (out_p3 !== 8'h78) $stop; - if (out_p4 !== 8'h44) $stop; - if (out_ef !== 8'hda) $stop; - end - else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + wire [7:0] out_ef; + enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); + // verilog_format: on + + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + if (cyc == 0) begin + // Setup + crc <= 8'hed; + end + else if (cyc == 1) begin + end + else if (cyc == 3) begin + if (out_p1 !== 8'h2d) $stop; + if (out_p2 !== 16'h2d2d) $stop; + if (out_p3 !== 8'h78) $stop; + if (out_p4 !== 8'h44) $stop; + if (out_ef !== 8'hda) $stop; + end + else if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module gencase (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); - parameter MODE = 0; - input [7:0] in; - output [7:0] out; - generate // : genblk1 - begin - case (MODE) - 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); - default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); - endcase - end - endgenerate +module gencase ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); + parameter MODE = 0; + input [7:0] in; + output [7:0] out; + generate // : genblk1 + begin + case (MODE) + 2: + mbuf mc[7:0] ( + .q(out[7:0]), + .a({in[5:0], in[7:6]}) + ); + default: + mbuf mc[7:0] ( + .q(out[7:0]), + .a({in[3:0], in[3:0]}) + ); + endcase + end + endgenerate endmodule -module paramed (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); - parameter WIDTH = 1; - parameter MODE = 0; - input [WIDTH-1:0] in; - output [WIDTH-1:0] out; +module paramed ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); + parameter WIDTH = 1; + parameter MODE = 0; + input [WIDTH-1:0] in; + output [WIDTH-1:0] out; - generate - if (MODE==0) initial $write("Mode=0\n"); - // No else - endgenerate + generate + if (MODE == 0) initial $write("Mode=0\n"); + // No else + endgenerate `ifndef NC // for(genvar) unsupported - `ifndef ATSIM // for(genvar) unsupported - generate - // Empty loop body, local genvar - for (genvar j=0; j<3; j=j+1) begin end - // Ditto to make sure j has new scope - for (genvar j=0; j<5; j=j+1) begin end - endgenerate - `endif +`ifndef ATSIM // for(genvar) unsupported + generate + // Empty loop body, local genvar + for (genvar j = 0; j < 3; j = j + 1) begin + end + // Ditto to make sure j has new scope + for (genvar j = 0; j < 5; j = j + 1) begin + end + endgenerate +`endif `endif - generate - endgenerate + generate + endgenerate - genvar i; - generate - if (MODE==0) begin - // Flip bitorder, direct assign method - for (i=0; i= 0; i = i-1) begin: fnxtclk1 - fnxtclk fnxtclk1 - (.u(c[i]), - .reset(reset), - .clk(clk), - .w(d[i]) ); - end - endgenerate + genvar i; + generate + for (i = 0; i >= 0; i = i - 1) begin : fnxtclk1 + fnxtclk fnxtclk1 ( + .u(c[i]), + .reset(reset), + .clk(clk), + .w(d[i]) + ); + end + endgenerate - assign b = d[0]; - assign c[0] = my_sig; - assign my_sig = 1'b1; + assign b = d[0]; + assign c[0] = my_sig; + assign my_sig = 1'b1; endmodule -module fnxtclk (u, reset, clk, w ); - input u; - input reset; - input clk; - output reg w; +module fnxtclk ( + u, + reset, + clk, + w +); + input u; + input reset; + input clk; + output reg w; - always @ (posedge clk or posedge reset) begin - if (reset == 1'b1) begin - w <= 1'b0; - end - else begin - w <= u; - end - end + always @(posedge clk or posedge reset) begin + if (reset == 1'b1) begin + w <= 1'b0; + end + else begin + w <= u; + end + end endmodule diff --git a/test_regress/t/t_gen_for_interface.v b/test_regress/t/t_gen_for_interface.v index 14663e3fc..0ee15ae3f 100644 --- a/test_regress/t/t_gen_for_interface.v +++ b/test_regress/t/t_gen_for_interface.v @@ -7,26 +7,26 @@ parameter N = 5; interface intf; - logic [N-1:0] data; + logic [N-1:0] data; endinterface module t ( - input logic clk - ); - intf localinterface [N-1:0](); + input logic clk +); + intf localinterface[N-1:0] (); - generate - genvar i,j; - for(i = 0; i < N; i++) begin - logic [N-1:0] dummy; - for(j = 0; j < N; j++) begin - assign dummy[j] = localinterface[j].data[i]; - end + generate + genvar i, j; + for (i = 0; i < N; i++) begin + logic [N-1:0] dummy; + for (j = 0; j < N; j++) begin + assign dummy[j] = localinterface[j].data[i]; end - endgenerate + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_gen_for_overlap.v b/test_regress/t/t_gen_for_overlap.v index 20addc698..dc83e0df2 100644 --- a/test_regress/t/t_gen_for_overlap.v +++ b/test_regress/t/t_gen_for_overlap.v @@ -6,45 +6,43 @@ // bug749 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - genvar g; - for (g=1; g<3; ++g) begin : gblk - sub2 #(.IN(g)) u (); - //sub #(.IN(g)) u2 (); - end + genvar g; + for (g = 1; g < 3; ++g) begin : gblk + sub2 #(.IN(g)) u (); + //sub #(.IN(g)) u2 (); + end - sub1 #(.IN(0)) u (); + sub1 #(.IN(0)) u (); - always @ (posedge clk) begin - if (t.u.IN != 0) $stop; - if (t.u.FLAVOR != 1) $stop; - //if (t.u2.IN != 0) $stop; // This should be not found - if (t.gblk[1].u.IN != 1) $stop; - if (t.gblk[2].u.IN != 2) $stop; - if (t.gblk[1].u.FLAVOR != 2) $stop; - if (t.gblk[2].u.FLAVOR != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (t.u.IN != 0) $stop; + if (t.u.FLAVOR != 1) $stop; + //if (t.u2.IN != 0) $stop; // This should be not found + if (t.gblk[1].u.IN != 1) $stop; + if (t.gblk[2].u.IN != 2) $stop; + if (t.gblk[1].u.FLAVOR != 2) $stop; + if (t.gblk[2].u.FLAVOR != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub1; - parameter [31:0] IN = 99; - parameter FLAVOR = 1; + parameter [31:0] IN = 99; + parameter FLAVOR = 1; `ifdef TEST_VERBOSE - initial $display("%m"); + initial $display("%m"); `endif endmodule module sub2; - parameter [31:0] IN = 99; - parameter FLAVOR = 2; + parameter [31:0] IN = 99; + parameter FLAVOR = 2; `ifdef TEST_VERBOSE - initial $display("%m"); + initial $display("%m"); `endif endmodule diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v index 4d59a72dc..a68c22cb2 100644 --- a/test_regress/t/t_gen_for_shuffle.v +++ b/test_regress/t/t_gen_for_shuffle.v @@ -3,78 +3,77 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[31:0]), + // Inputs + .in(in[31:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h3e3a62edb61f8c7f - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h3e3a62edb61f8c7f + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + in +); - input [31:0] in; - output [31:0] out; + input [31:0] in; + output [31:0] out; - genvar i; - generate - for (i=0; i<16; i=i+1) begin : gblk - assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; - end - endgenerate + genvar i; + generate + for (i = 0; i < 16; i = i + 1) begin : gblk + assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 44319dbc6..27c9d3c66 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -4,108 +4,137 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [3:0] Value = crc[3:0]; + wire [3:0] Value = crc[3:0]; - wire [3:0] Result; - wire [3:0] Result2; + wire [3:0] Result; + wire [3:0] Result2; - Testit testit (/*AUTOINST*/ - // Outputs - .Result (Result[3:0]), - .Result2 (Result2[3:0]), - // Inputs - .clk (clk), - .Value (Value[3:0])); + Testit testit ( /*AUTOINST*/ + // Outputs + .Result(Result[3:0]), + .Result2(Result2[3:0]), + // Inputs + .clk(clk), + .Value(Value[3:0]) + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x %x %x\n", $time, cyc, crc, Result, Result2); + $write("[%0t] cyc==%0d crc=%x %x %x\n", $time, cyc, crc, Result, Result2); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= {56'h0, Result, Result2} - ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= {56'h0, Result, Result2} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h4af37965592f64f9) $stop; + $finish; + end + end + +endmodule + +module Test ( + clk, + Value, + Result +); + input clk; + input Value; + output Result; + + reg Internal; + + assign Result = Internal; + + always @(posedge clk) Internal <= Value; +endmodule + +module Test_wrap1 ( + clk, + Value, + Result +); + input clk; + input Value; + output Result; + + Test t ( + clk, + Value, + Result + ); +endmodule + +module Test_wrap2 ( + clk, + Value, + Result +); + input clk; + input Value; + output Result; + + Test t ( + clk, + Value, + Result + ); +endmodule + +module Testit ( + clk, + Value, + Result, + Result2 +); + input clk; + input [3:0] Value; + output [3:0] Result; + output [3:0] Result2; + + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin : a + if ((i == 0) || (i == 2)) begin : gblk + Test_wrap1 test ( + clk, + Value[i], + Result[i] + ); end - else if (cyc<10) begin - sum <= 64'h0; + else begin : gblk + Test_wrap2 test ( + clk, + Value[i], + Result[i] + ); end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h4af37965592f64f9) $stop; - $finish; - end - end - -endmodule - -module Test (clk, Value, Result); - input clk; - input Value; - output Result; - - reg Internal; - - assign Result = Internal; - - always @(posedge clk) - Internal <= Value; -endmodule - -module Test_wrap1 (clk, Value, Result); - input clk; - input Value; - output Result; - - Test t (clk, Value, Result); -endmodule - -module Test_wrap2 (clk, Value, Result); - input clk; - input Value; - output Result; - - Test t (clk, Value, Result); -endmodule - -module Testit (clk, Value, Result, Result2); - input clk; - input [3:0] Value; - output [3:0] Result; - output [3:0] Result2; - - genvar i; - generate - for (i = 0; i < 4; i = i + 1) - begin : a - if ((i == 0) || (i == 2)) begin : gblk - Test_wrap1 test (clk, Value[i] , Result[i]); - end - else begin : gblk - Test_wrap2 test (clk, Value[i], Result[i]); - end - end - endgenerate - - assign Result2[0] = a[0].gblk.test.t.Internal; - assign Result2[1] = a[1].gblk.test.t.Internal; - assign Result2[2] = a[2].gblk.test.t.Internal; - assign Result2[3] = a[3].gblk.test.t.Internal; + end + endgenerate + + assign Result2[0] = a[0].gblk.test.t.Internal; + assign Result2[1] = a[1].gblk.test.t.Internal; + assign Result2[2] = a[2].gblk.test.t.Internal; + assign Result2[3] = a[3].gblk.test.t.Internal; endmodule diff --git a/test_regress/t/t_gen_genblk.out b/test_regress/t/t_gen_genblk.out index 9a6cb52a4..aafe37522 100644 --- a/test_regress/t/t_gen_genblk.out +++ b/test_regress/t/t_gen_genblk.out @@ -1,50 +1,50 @@ -021: got=top.t.direct_ignored.show1 -023: got=top.t.direct_ignored.genblk1.show2 exp=1 gennum=1 +022: got=top.t.direct_ignored.show1 +025: got=top.t.direct_ignored.genblk1.show2 exp=1 gennum=1 -030: got=top.t.empty_DISAGREE.genblk1.show2 exp=0 gennum=1 +035: got=top.t.empty_DISAGREE.genblk1.show2 exp=0 gennum=1 -037: got=top.t.empty_named_DISAGREE.genblk1.show2 exp=0 gennum=1 +045: got=top.t.empty_named_DISAGREE.genblk1.show2 exp=0 gennum=1 -043: got=top.t.unnamed_counts.show1 -046: got=top.t.unnamed_counts.genblk1.show2 exp=0 gennum=1 +052: got=top.t.unnamed_counts.show1 +056: got=top.t.unnamed_counts.genblk1.show2 exp=0 gennum=1 -052: got=top.t.named_counts.named.show1 -055: got=top.t.named_counts.genblk1.show2 exp=0 gennum=1 +063: got=top.t.named_counts.named.show1 +067: got=top.t.named_counts.genblk1.show2 exp=0 gennum=1 -061: got=top.t.if_direct_counts.genblk1.show1 -063: got=top.t.if_direct_counts.genblk2.show2 exp=2 gennum=2 +075: got=top.t.if_direct_counts.genblk1.show1 +078: got=top.t.if_direct_counts.genblk2.show2 exp=2 gennum=2 -069: got=top.t.if_begin_counts.genblk1.show1 -071: got=top.t.if_begin_counts.genblk2.show2 exp=2 gennum=2 +089: got=top.t.if_begin_counts.genblk1.show1 +093: got=top.t.if_begin_counts.genblk2.show2 exp=2 gennum=2 -076: got=top.t.if_named_counts.named.show1 -078: got=top.t.if_named_counts.named.subnamed.show1s -082: got=top.t.if_named_counts.genblk2.show2 exp=2 gennum=2 +099: got=top.t.if_named_counts.named.show1 +101: got=top.t.if_named_counts.named.subnamed.show1s +106: got=top.t.if_named_counts.genblk2.show2 exp=2 gennum=2 -089: got=top.t.begin_if_counts.genblk1.show1 -092: got=top.t.begin_if_counts.genblk2.show2 exp=2 gennum=2 +118: got=top.t.begin_if_counts.genblk1.show1 +123: got=top.t.begin_if_counts.genblk2.show2 exp=2 gennum=2 -099: got=top.t.for_empty_counts.genblk2.show2 exp=0 gennum=2 +132: got=top.t.for_empty_counts.genblk2.show2 exp=0 gennum=2 -104: got=top.t.for_direct_counts.genblk1[0].show1 -106: got=top.t.for_direct_counts.genblk2.show2 exp=2 gennum=2 +137: got=top.t.for_direct_counts.genblk1[0].show1 +140: got=top.t.for_direct_counts.genblk2.show2 exp=2 gennum=2 -111: got=top.t.for_named_counts.fornamed[0].show1 -114: got=top.t.for_named_counts.genblk2.show2 exp=2 gennum=2 +146: got=top.t.for_named_counts.fornamed[0].show1 +150: got=top.t.for_named_counts.genblk2.show2 exp=2 gennum=2 -119: got=top.t.for_begin_counts.genblk1[0].show1 -122: got=top.t.for_begin_counts.genblk2.show2 exp=2 gennum=2 +156: got=top.t.for_begin_counts.genblk1[0].show1 +160: got=top.t.for_begin_counts.genblk2.show2 exp=2 gennum=2 -132: got=top.t.if_if.genblk1.genblk1.show1 -136: got=top.t.if_if.genblk2.show2 exp=2 gennum=2 +172: got=top.t.if_if.genblk1.genblk1.show1 +177: got=top.t.if_if.genblk2.show2 exp=2 gennum=2 -142: got=top.t.case_direct.genblk1.show1 -146: got=top.t.case_direct.genblk2.show2 exp=2 gennum=2 +184: got=top.t.case_direct.genblk1.show1 +189: got=top.t.case_direct.genblk2.show2 exp=2 gennum=2 -152: got=top.t.case_begin_counts.genblk1.show1 -156: got=top.t.case_begin_counts.genblk2.show2 exp=2 gennum=2 +199: got=top.t.case_begin_counts.genblk1.show1 +207: got=top.t.case_begin_counts.genblk2.show2 exp=2 gennum=2 -162: got=top.t.case_named_counts.subnamed.show1 -166: got=top.t.case_named_counts.genblk2.show2 exp=2 gennum=2 +217: got=top.t.case_named_counts.subnamed.show1 +225: got=top.t.case_named_counts.genblk2.show2 exp=2 gennum=2 *-* All Finished *-* diff --git a/test_regress/t/t_gen_genblk.v b/test_regress/t/t_gen_genblk.v index 0d90ff9a4..2e272afae 100644 --- a/test_regress/t/t_gen_genblk.v +++ b/test_regress/t/t_gen_genblk.v @@ -3,223 +3,288 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`define CONCAT(a,b) a``b +`define CONCAT(a, b) a``b `define SHOW_LINED `CONCAT(show, `__LINE__) bit fails; -module t (/*AUTOARG*/ - // Inputs - clk, reset_l - ); +module t ( /*AUTOARG*/ + // Inputs + clk, + reset_l +); - input clk; - input reset_l; + input clk; + input reset_l; - generate - begin : direct_ignored - show #(`__LINE__) show1(); + generate + begin : direct_ignored + show #(`__LINE__) show1 (); - if (1) begin check #(`__LINE__, 1) show2(); end + if (1) begin + check #(`__LINE__, 1) show2 (); + end + end + + begin : empty_DISAGREE + // DISAGREEMENT: if empty unnamed begin/end counts + begin end - begin : empty_DISAGREE - // DISAGREEMENT: if empty unnamed begin/end counts - begin end + if (1) begin + check #(`__LINE__, 0) show2 (); + end + end - if (1) begin check #(`__LINE__, 0) show2(); end + begin : empty_named_DISAGREE + // DISAGREEMENT: if empty named begin/end counts + begin : empty_inside_named end - begin : empty_named_DISAGREE - // DISAGREEMENT: if empty named begin/end counts - begin : empty_inside_named end + if (1) begin + check #(`__LINE__, 0) show2 (); + end + end - if (1) begin check #(`__LINE__, 0) show2(); end + begin : unnamed_counts + // DISAGREEMENT: if unnamed begin/end counts + begin + show #(`__LINE__) show1 (); end - begin : unnamed_counts - // DISAGREEMENT: if unnamed begin/end counts - begin - show #(`__LINE__) show1(); - end + if (1) begin + check #(`__LINE__, 0) show2 (); + end + end - if (1) begin check #(`__LINE__, 0) show2(); end + begin : named_counts + // DISAGREEMENT: if named begin/end counts + begin : named + show #(`__LINE__) show1 (); end - begin : named_counts - // DISAGREEMENT: if named begin/end counts - begin : named - show #(`__LINE__) show1(); - end + if (1) begin + check #(`__LINE__, 0) show2 (); + end + end - if (1) begin check #(`__LINE__, 0) show2(); end + begin : if_direct_counts + if (0); + else + if (0); + else if (1) show #(`__LINE__) show1 (); + + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end + + begin : if_begin_counts + if (0) begin + end + else if (0) begin + show #(`__LINE__) show1_NOT (); + end + else if (1) begin + show #(`__LINE__) show1 (); end - begin : if_direct_counts - if (0) ; - else if (0) ; - else if (1) show #(`__LINE__) show1(); + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end - if (1) begin check #(`__LINE__, 2) show2(); end + begin : if_named_counts + if (1) begin : named + show #(`__LINE__) show1 (); + if (1) begin : subnamed + show #(`__LINE__) show1s (); + end end - begin : if_begin_counts - if (0) begin end - else if (0) begin show #(`__LINE__) show1_NOT(); end - else if (1) begin show #(`__LINE__) show1(); end + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end - if (1) begin check #(`__LINE__, 2) show2(); end + begin : begin_if_counts + begin + if (0) begin + end + else if (0) begin + show #(`__LINE__) show1_NOT (); + end + else if (1) begin + show #(`__LINE__) show1 (); + end + end + // DISAGREEMENT: this could be genblk01 + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end + + begin : for_empty_counts + // DISAGREEMENT: if empty genfor counts + for (genvar g = 0; g < 1; ++g); + + if (1) begin + check #(`__LINE__, 0) show2 (); + end + end + + begin : for_direct_counts + for (genvar g = 0; g < 1; ++g) show #(`__LINE__) show1 (); + + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end + + begin : for_named_counts + for (genvar g = 0; g < 1; ++g) begin : fornamed + show #(`__LINE__) show1 (); end - begin : if_named_counts - if (1) begin : named - show #(`__LINE__) show1(); - if (1) begin : subnamed - show #(`__LINE__) show1s(); - end - end + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end - if (1) begin check #(`__LINE__, 2) show2(); end + begin : for_begin_counts + for (genvar g = 0; g < 1; ++g) begin + show #(`__LINE__) show1 (); end - begin : begin_if_counts - begin - if (0) begin end - else if (0) begin show #(`__LINE__) show1_NOT(); end - else if (1) begin show #(`__LINE__) show1(); end - end - // DISAGREEMENT: this could be genblk01 - if (1) begin check #(`__LINE__, 2) show2(); end + if (1) begin + check #(`__LINE__, 2) show2 (); + end + end + + begin : if_if + if (0); + else if (0) begin : namedb + end + else begin + if (0) begin + end + else if (1) begin + show #(`__LINE__) show1 (); + end end - begin : for_empty_counts - // DISAGREEMENT: if empty genfor counts - for (genvar g = 0; g < 1; ++g) ; - - if (1) begin check #(`__LINE__, 0) show2(); end + if (1) begin + check #(`__LINE__, 2) show2 (); end + end - begin : for_direct_counts - for (genvar g = 0; g < 1; ++g) - show #(`__LINE__) show1(); + begin : case_direct + case (1) + 0: show #(`__LINE__) show1a_NOT (); + 1: show #(`__LINE__) show1 (); + 2: show #(`__LINE__) show1c_NOT (); + endcase - if (1) begin check #(`__LINE__, 2) show2(); end + if (1) begin + check #(`__LINE__, 2) show2 (); end + end - begin : for_named_counts - for (genvar g = 0; g < 1; ++g) begin : fornamed - show #(`__LINE__) show1(); - end + begin : case_begin_counts + case (1) + 0: begin + show #(`__LINE__) show1a_NOT (); + end + 1: begin + show #(`__LINE__) show1 (); + end + 2: begin + show #(`__LINE__) show1c_NOT (); + end + endcase - if (1) begin check #(`__LINE__, 2) show2(); end + if (1) begin + check #(`__LINE__, 2) show2 (); end + end - begin : for_begin_counts - for (genvar g = 0; g < 1; ++g) begin - show #(`__LINE__) show1(); - end + begin : case_named_counts + case (1) + 0: begin : subnamed + show #(`__LINE__) show1a_NOT (); + end + 1: begin : subnamed + show #(`__LINE__) show1 (); + end + 2: begin : subnamed + show #(`__LINE__) show1c_NOT (); + end + endcase - if (1) begin check #(`__LINE__, 2) show2(); end + if (1) begin + check #(`__LINE__, 2) show2 (); end + end - begin : if_if - if (0) ; - else if (0) begin : namedb - end - else begin - if (0) begin end - else if (1) begin - show #(`__LINE__) show1(); - end - end + endgenerate - if (1) begin check #(`__LINE__, 2) show2(); end - end + int cyc; - begin : case_direct - case (1) - 0 : show #(`__LINE__) show1a_NOT(); - 1 : show #(`__LINE__) show1(); - 2 : show #(`__LINE__) show1c_NOT(); - endcase + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 999) begin + if (fails) $stop; + else $write("*-* All Finished *-*\n"); + $finish; + end - if (1) begin check #(`__LINE__, 2) show2(); end - end - - begin : case_begin_counts - case (1) - 0 : begin show #(`__LINE__) show1a_NOT(); end - 1 : begin show #(`__LINE__) show1(); end - 2 : begin show #(`__LINE__) show1c_NOT(); end - endcase - - if (1) begin check #(`__LINE__, 2) show2(); end - end - - begin : case_named_counts - case (1) - 0 : begin : subnamed show #(`__LINE__) show1a_NOT(); end - 1 : begin : subnamed show #(`__LINE__) show1(); end - 2 : begin : subnamed show #(`__LINE__) show1c_NOT(); end - endcase - - if (1) begin check #(`__LINE__, 2) show2(); end - end - - endgenerate - - int cyc; - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 999) begin - if (fails) $stop; - else $write("*-* All Finished *-*\n"); - $finish; - end - - end + end endmodule -module show #(parameter LINE=0) (); - // Each instance compares on unique cycle based on line number - // so we get deterministic ordering (versus using an initial) - always @ (posedge t.clk) begin - if (t.cyc == LINE) begin - $display("%03d: got=%m", LINE); - end - end +module show #( + parameter LINE = 0 +) (); + // Each instance compares on unique cycle based on line number + // so we get deterministic ordering (versus using an initial) + always @(posedge t.clk) begin + if (t.cyc == LINE) begin + $display("%03d: got=%m", LINE); + end + end endmodule -module check #(parameter LINE=0, parameter EXP=0) (); - string mod; - int gennum; - int pos; +module check #( + parameter LINE = 0, + parameter EXP = 0 +) (); + string mod; + int gennum; + int pos; - always @ (posedge t.clk) begin - if (t.cyc == LINE) begin - mod = $sformatf("%m"); + always @(posedge t.clk) begin + if (t.cyc == LINE) begin + mod = $sformatf("%m"); - gennum = 0; - for (int pos = 0; pos < mod.len(); ++pos) begin - if (mod.substr(pos, pos+5) == "genblk") begin - pos += 6; - // verilator lint_off WIDTH - gennum = mod[pos] - "0"; - // verilator lint_on WIDTH - break; - end - end - - $write("%03d: got=%s exp=%0d gennum=%0d ", LINE, mod, EXP, gennum); - if (EXP == 0) $display(" "); - else if (gennum != EXP) begin - $display (" %%Error"); - fails = 1; - end - else $display; - - $display; + gennum = 0; + for (int pos = 0; pos < mod.len(); ++pos) begin + if (mod.substr(pos, pos + 5) == "genblk") begin + pos += 6; + // verilator lint_off WIDTH + gennum = mod[pos] - "0"; + // verilator lint_on WIDTH + break; + end end - end + + $write("%03d: got=%s exp=%0d gennum=%0d ", LINE, mod, EXP, gennum); + if (EXP == 0) $display(" "); + else if (gennum != EXP) begin + $display(" %%Error"); + fails = 1; + end + else $display; + + $display; + end + end endmodule diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v index 08aba68e2..d6c4c7a14 100644 --- a/test_regress/t/t_gen_if.v +++ b/test_regress/t/t_gen_if.v @@ -8,33 +8,37 @@ `timescale 1ns / 1ps -module t(data_i, data_o, single); - parameter OP_BITS = 32; - input [OP_BITS -1:0] data_i; - output [31:0] data_o; - input single; +module t ( + data_i, + data_o, + single +); + parameter OP_BITS = 32; + input [OP_BITS -1:0] data_i; + output [31:0] data_o; + input single; - // Bare begin/end extension of IEEE allowed by most all tools - begin - end - begin : named - end : named + // Bare begin/end extension of IEEE allowed by most all tools + begin + end + begin : named + end : named - //simplistic example, should choose 1st conditional generate and assign straight through - //the tool also compiles the special case and determines an error (replication value is 0 - generate - if (OP_BITS == 32) begin : general_case - assign data_o = data_i; - // Test implicit signals - /* verilator lint_off IMPLICIT */ - assign imp = single; - /* verilator lint_on IMPLICIT */ - end - else begin : special_case - assign data_o = {{(32 -OP_BITS){1'b0}},data_i}; - /* verilator lint_off IMPLICIT */ - assign imp = single; - /* verilator lint_on IMPLICIT */ - end - endgenerate + //simplistic example, should choose 1st conditional generate and assign straight through + //the tool also compiles the special case and determines an error (replication value is 0 + generate + if (OP_BITS == 32) begin : general_case + assign data_o = data_i; + // Test implicit signals + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ + end + else begin : special_case + assign data_o = {{(32 - OP_BITS) {1'b0}}, data_i}; + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ + end + endgenerate endmodule diff --git a/test_regress/t/t_gen_ifelse.v b/test_regress/t/t_gen_ifelse.v index cdcab94b1..5196f84c5 100644 --- a/test_regress/t/t_gen_ifelse.v +++ b/test_regress/t/t_gen_ifelse.v @@ -5,31 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module s; - parameter A = 0; - generate - if (A == 1) - int i; - else if (A == 2) - int i; - else - int i; - endgenerate - generate - if (A == 1) - int i; - else if (A == 2) - int i; - else - int i; - endgenerate + parameter A = 0; + generate + if (A == 1) int i; + else if (A == 2) int i; + else int i; + endgenerate + generate + if (A == 1) int i; + else if (A == 2) int i; + else int i; + endgenerate endmodule module t; - s #(0) s0(); - s #(1) s1(); - s #(2) s2(); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + s #(0) s0 (); + s #(1) s1 (); + s #(2) s2 (); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v index 8048bf163..d42a0c384 100644 --- a/test_regress/t/t_gen_inc.v +++ b/test_regress/t/t_gen_inc.v @@ -4,106 +4,106 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - genvar g; - integer i; + integer cyc = 0; - reg [31:0] v; + genvar g; + integer i; - reg [31:0] gen_pre_PLUSPLUS = 32'h0; - reg [31:0] gen_pre_MINUSMINUS = 32'h0; - reg [31:0] gen_post_PLUSPLUS = 32'h0; - reg [31:0] gen_post_MINUSMINUS = 32'h0; - reg [31:0] gen_PLUSEQ = 32'h0; - reg [31:0] gen_MINUSEQ = 32'h0; - reg [31:0] gen_TIMESEQ = 32'h0; - reg [31:0] gen_DIVEQ = 32'h0; - reg [31:0] gen_MODEQ = 32'h0; - reg [31:0] gen_ANDEQ = 32'h0; - reg [31:0] gen_OREQ = 32'h0; - reg [31:0] gen_XOREQ = 32'h0; - reg [31:0] gen_SLEFTEQ = 32'h0; - reg [31:0] gen_SRIGHTEQ = 32'h0; - reg [31:0] gen_SSRIGHTEQ = 32'h0; + reg [31:0] v; - generate - for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; - for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; - for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; - for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; - for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; - for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; - for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; - for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; - for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; - for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; - for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; - for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; - for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; - for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; - for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; - endgenerate + reg [31:0] gen_pre_PLUSPLUS = 32'h0; + reg [31:0] gen_pre_MINUSMINUS = 32'h0; + reg [31:0] gen_post_PLUSPLUS = 32'h0; + reg [31:0] gen_post_MINUSMINUS = 32'h0; + reg [31:0] gen_PLUSEQ = 32'h0; + reg [31:0] gen_MINUSEQ = 32'h0; + reg [31:0] gen_TIMESEQ = 32'h0; + reg [31:0] gen_DIVEQ = 32'h0; + reg [31:0] gen_MODEQ = 32'h0; + reg [31:0] gen_ANDEQ = 32'h0; + reg [31:0] gen_OREQ = 32'h0; + reg [31:0] gen_XOREQ = 32'h0; + reg [31:0] gen_SLEFTEQ = 32'h0; + reg [31:0] gen_SRIGHTEQ = 32'h0; + reg [31:0] gen_SSRIGHTEQ = 32'h0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 3) begin + // verilog_format: off + generate + for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; + for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; + for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; + for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; + for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; + for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; + for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; + for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; + for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; + for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; + for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; + endgenerate + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin `ifdef TEST_VERBOSE - $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); - $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); - $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); - $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); - $write("gen_PLUSEQ %b\n", gen_PLUSEQ); - $write("gen_MINUSEQ %b\n", gen_MINUSEQ); - $write("gen_TIMESEQ %b\n", gen_TIMESEQ); - $write("gen_DIVEQ %b\n", gen_DIVEQ); - $write("gen_MODEQ %b\n", gen_MODEQ); - $write("gen_ANDEQ %b\n", gen_ANDEQ); - $write("gen_OREQ %b\n", gen_OREQ); - $write("gen_XOREQ %b\n", gen_XOREQ); - $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); - $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); - $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); + $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); + $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); + $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); + $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); + $write("gen_PLUSEQ %b\n", gen_PLUSEQ); + $write("gen_MINUSEQ %b\n", gen_MINUSEQ); + $write("gen_TIMESEQ %b\n", gen_TIMESEQ); + $write("gen_DIVEQ %b\n", gen_DIVEQ); + $write("gen_MODEQ %b\n", gen_MODEQ); + $write("gen_ANDEQ %b\n", gen_ANDEQ); + $write("gen_OREQ %b\n", gen_OREQ); + $write("gen_XOREQ %b\n", gen_XOREQ); + $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); + $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); + $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); `endif - if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; - if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; - if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; - if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; - if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; - if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; - if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; - if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; - if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; - if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; - if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; - if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; + if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; + if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; + if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; + if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; - v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; - v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; - v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; - v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; - v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; - v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; - v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; - v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; - v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; - v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; - v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; + v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; + v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; + v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_gen_index.v b/test_regress/t/t_gen_index.v index 51321d684..a156df87c 100644 --- a/test_regress/t/t_gen_index.v +++ b/test_regress/t/t_gen_index.v @@ -13,60 +13,66 @@ // SPDX-License-Identifier: CC0-1.0 `define START 8 -`define SIZE 4 -`define END (`START + `SIZE) +`define SIZE 4 +`define END (`START + `SIZE) -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [`END-1:0] y; - wire [`END-1:0] x; + reg [`END-1:0] y; + wire [`END-1:0] x; - foo foo_i (.y (y), - .x (x), - .clk (clk)); + foo foo_i ( + .y(y), + .x(x), + .clk(clk) + ); - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end -endmodule // t +endmodule // t -module foo(output wire [`END-1:0] y, - input wire [`END-1:0] x, - input wire clk); +module foo ( + output wire [`END-1:0] y, + input wire [`END-1:0] x, + input wire clk +); - function peek_bar; - peek_bar = bar_inst[`START].i_bar.r; // this is ok - peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not. - endfunction + function peek_bar; + peek_bar = bar_inst[`START].i_bar.r; // this is ok + peek_bar = bar_inst[`START+1].i_bar.r; // this fails, should not. + endfunction - genvar g; - generate - for (g = `START; g < `END; g = g + 1) begin: bar_inst - bar i_bar(.x (x[g]), - .y (y[g]), - .clk (clk)); - end - endgenerate + genvar g; + generate + for (g = `START; g < `END; g = g + 1) begin : bar_inst + bar i_bar ( + .x(x[g]), + .y(y[g]), + .clk(clk) + ); + end + endgenerate endmodule : foo -module bar(output wire y, - input wire x, - input wire clk); +module bar ( + output wire y, + input wire x, + input wire clk +); - reg r = 0; - assign y = r; + reg r = 0; + assign y = r; - always @(posedge clk) begin - r = x ? ~x : y; - end + always @(posedge clk) begin + r = x ? ~x : y; + end endmodule : bar diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index 070baff8a..d00c7028a 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -6,83 +6,82 @@ `define STRINGIFY(x) `"x`" -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - wire out; - reg in; + integer cyc = 0; - Genit g (.clk(clk), .value(in), .result(out)); + wire out; + reg in; - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out); - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - in <= 1'b1; - end - else if (cyc==1) begin - in <= 1'b0; - end - else if (cyc==2) begin - if (out != 1'b1) $stop; - end - else if (cyc==3) begin - if (out != 1'b0) $stop; - end - else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + Genit g (.clk(clk), .value(in), .result(out)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + in <= 1'b1; + end + else if (cyc==1) begin + in <= 1'b0; + end + else if (cyc==2) begin + if (out != 1'b1) $stop; + end + else if (cyc==3) begin + if (out != 1'b0) $stop; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Generate (clk, value, result); - input clk; - input value; - output result; + input clk; + input value; + output result; - reg Internal; + reg Internal; - assign result = Internal; + assign result = Internal; - always @(posedge clk) - Internal <= value; + always @(posedge clk) + Internal <= value; endmodule module Checker (clk, value); input clk, value; - always @(posedge clk) begin - $write ("[%0t] value=%h\n", $time, value); - end + always @(posedge clk) begin + $write ("[%0t] value=%h\n", $time, value); + end endmodule module Test (clk, value, result); - input clk; - input value; - output result; + input clk; + input value; + output result; - Generate gen (clk, value, result); - Checker chk (clk, gen.Internal); + Generate gen (clk, value, result); + Checker chk (clk, gen.Internal); endmodule module Genit (clk, value, result); - input clk; - input value; - output result; + input clk; + input value; + output result; `ifndef ATSIM // else unsupported `ifndef NC // else unsupported `ifndef IVERILOG // else unsupported - `define WITH_FOR_GENVAR + `define WITH_FOR_GENVAR `endif `endif `endif @@ -90,25 +89,25 @@ module Genit (clk, value, result); `define WITH_GENERATE `ifdef WITH_GENERATE `ifndef WITH_FOR_GENVAR - genvar i; + genvar i; `endif - generate - for ( + generate + for ( `ifdef WITH_FOR_GENVAR - genvar + genvar `endif - i = 0; i < 1; i = i + 1) - begin : foo - Test tt (clk, value, result); - end - endgenerate + i = 0; i < 1; i = i + 1) + begin : foo + Test tt (clk, value, result); + end + endgenerate `else - Test tt (clk, value, result); + Test tt (clk, value, result); `endif - wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! - always @ (posedge clk) begin - $write("[%0t] Result2 = %x\n", $time, Result2); - end + wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! + always @ (posedge clk) begin + $write("[%0t] Result2 = %x\n", $time, Result2); + end endmodule diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v index 42e2d11e8..f6eaa02c4 100644 --- a/test_regress/t/t_gen_intdot2.v +++ b/test_regress/t/t_gen_intdot2.v @@ -6,156 +6,155 @@ `define STRINGIFY(x) `"x`" -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - reg check; - initial check = 1'b0; - Genit g (.clk(clk), .check(check)); + integer cyc = 0; - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out); - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - check <= 1'b0; - end - else if (cyc==1) begin - check <= 1'b1; - end - else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + reg check; + initial check = 1'b0; + Genit g (.clk(clk), .check(check)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + check <= 1'b0; + end + else if (cyc==1) begin + check <= 1'b1; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end //`define WAVES `ifdef WAVES - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(12, t); - end + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(12, t); + end `endif endmodule module One; - wire one = 1'b1; + wire one = 1'b1; endmodule module Genit ( - input clk, - input check); + input clk, + input check); - // ARRAY - One cellarray1[1:0] (); //cellarray[0..1][0..1] - always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; - always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; + // ARRAY + One cellarray1[1:0] (); //cellarray[0..1][0..1] + always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; + always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; - // IF - generate - // genblk1 refers to the if's name, not the "generate" itself. - if (1'b1) // IMPLIED begin: genblk1 - One ifcell1(); // genblk1.ifcell1 - else - One ifcell1(); // genblk1.ifcell1 - endgenerate - // DISAGREEMENT on this naming - always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; + // IF + generate + // genblk1 refers to the if's name, not the "generate" itself. + if (1'b1) // IMPLIED begin: genblk1 + One ifcell1(); // genblk1.ifcell1 + else + One ifcell1(); // genblk1.ifcell1 + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; - generate - begin : namedif2 - if (1'b1) - One ifcell2(); // namedif2.genblk1.ifcell2 - end - endgenerate - // DISAGREEMENT on this naming - always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; - - generate + generate + begin : namedif2 if (1'b1) - begin : namedif3 - One ifcell3(); // namedif3.ifcell3 - end - endgenerate - always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; + One ifcell2(); // namedif2.genblk1.ifcell2 + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; - // CASE - generate - begin : casecheck - case (1'b1) - 1'b1 : - One casecell10(); // genblk4.casecell10 - endcase + generate + if (1'b1) + begin : namedif3 + One ifcell3(); // namedif3.ifcell3 end - endgenerate - // DISAGREEMENT on this naming - always @ (posedge clk) if (casecheck.genblk1.casecell10.one !== 1'b1) $stop; + endgenerate + always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; - generate + // CASE + generate + begin : casecheck case (1'b1) - 1'b1 : begin : namedcase11 - One casecell11(); - end + 1'b1 : + One casecell10(); // genblk4.casecell10 endcase - endgenerate - always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (casecheck.genblk1.casecell10.one !== 1'b1) $stop; - genvar i; - genvar j; - - generate - begin : genfor - for (i = 0; i < 2; i = i + 1) - One cellfor20 (); // genfor.genblk1[0..1].cellfor20 + generate + case (1'b1) + 1'b1 : begin : namedcase11 + One casecell11(); end - endgenerate - // DISAGREEMENT on this naming - always @ (posedge clk) if (genfor.genblk1[0].cellfor20.one !== 1'b1) $stop; - always @ (posedge clk) if (genfor.genblk1[1].cellfor20.one !== 1'b1) $stop; + endcase + endgenerate + always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; - // COMBO - generate - for (i = 0; i < 2; i = i + 1) - begin : namedfor21 - One cellfor21 (); // namedfor21[0..1].cellfor21 - end - endgenerate - always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; - always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; + genvar i; + genvar j; - generate + generate + begin : genfor for (i = 0; i < 2; i = i + 1) - begin : namedfor30 - for (j = 0; j < 2; j = j + 1) - begin : forb30 - if (j == 0) - begin : forif30 - One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a - end - else + One cellfor20 (); // genfor.genblk1[0..1].cellfor20 + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (genfor.genblk1[0].cellfor20.one !== 1'b1) $stop; + always @ (posedge clk) if (genfor.genblk1[1].cellfor20.one !== 1'b1) $stop; + + // COMBO + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor21 + One cellfor21 (); // namedfor21[0..1].cellfor21 + end + endgenerate + always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; + + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor30 + for (j = 0; j < 2; j = j + 1) + begin : forb30 + if (j == 0) + begin : forif30 + One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a + end + else `ifdef verilator - begin : forif30b + begin : forif30b `else - begin : forif30 // forif30 seems to work on some simulators, not verilator yet + begin : forif30 // forif30 seems to work on some simulators, not verilator yet `endif - One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b - end - end - end - endgenerate - always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; - always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; + One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b + end + end + end + endgenerate + always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; `ifdef verilator - always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; - always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; `else - always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; - always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; `endif endmodule diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v index 4f7b7420c..f9b68a448 100644 --- a/test_regress/t/t_gen_local.v +++ b/test_regress/t/t_gen_local.v @@ -4,33 +4,32 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - localparam N = 31; + integer cyc = 0; - wire [31:0] vec; + localparam N = 31; - generate - genvar g; // bug461 - begin : topgen - for (g=0; g. ... Looked in: diff --git a/test_regress/t/t_gen_nonconst_bad.v b/test_regress/t/t_gen_nonconst_bad.v index ade175eb7..cff423c85 100644 --- a/test_regress/t/t_gen_nonconst_bad.v +++ b/test_regress/t/t_gen_nonconst_bad.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 module t; - nfound nfound(); + nfound nfound (); endmodule diff --git a/test_regress/t/t_gen_self_return.v b/test_regress/t/t_gen_self_return.v index 0ba7a9743..e76fa0bb8 100644 --- a/test_regress/t/t_gen_self_return.v +++ b/test_regress/t/t_gen_self_return.v @@ -4,52 +4,50 @@ // SPDX-FileCopyrightText: 2019 Roman Popov // SPDX-License-Identifier: CC0-1.0 -module dut - #( +module dut #( parameter DEPTH = 16, parameter WIDTH = 32, parameter RAM_SPLIT_WIDTH = 16 - ) - ( +) ( output logic [WIDTH-1:0] ram_dataout - ); +); - localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4 - localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2 - typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96 + localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4 + localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2 + typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96 - function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS); - index_calc[0] = '0; - for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH%NUM_RAM_BLOCKS))}; - for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i]; - // bug1467 was this return - return index_calc; - endfunction + function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS); + index_calc[0] = '0; + for (int i = 0; i < NUM_RAM_BLOCKS; i++) + index_calc[i+1] = WIDTH / NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH % NUM_RAM_BLOCKS))}; + for (int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i]; + // bug1467 was this return + return index_calc; + endfunction - localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS); + localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS); - generate - begin : ram_dataout_gen - for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin - always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0; - end + generate + begin : ram_dataout_gen + for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin + always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0; end - endgenerate + end + endgenerate - initial begin - if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module t - ( - input clk, - output logic [31:0] ram_dataout - ); +module t ( + input clk, + output logic [31:0] ram_dataout +); - dut dut0(.*); + dut dut0 (.*); endmodule diff --git a/test_regress/t/t_gen_upscope.v b/test_regress/t/t_gen_upscope.v index f7fecf2ce..94b81890a 100644 --- a/test_regress/t/t_gen_upscope.v +++ b/test_regress/t/t_gen_upscope.v @@ -31,55 +31,54 @@ mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.tag */ -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc = 0; +module t ( + input clk +); - tag tag (); - b b (); + integer cyc = 0; - always @ (t.cyc) begin - if (t.cyc == 2) $display("mod a has scope = %m"); - if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); - end + tag tag (); + b b (); - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(t.cyc) begin + if (t.cyc == 2) $display("mod a has scope = %m"); + if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module b (); - genvar g; - generate - for (g=0; g<2; g++) begin : gen - tag tag (); - c c (); - end - endgenerate - always @ (t.cyc) begin - if (t.cyc == 3) $display("mod b has scope = %m"); - if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); - end + genvar g; + generate + for (g = 0; g < 2; g++) begin : gen + tag tag (); + c c (); + end + endgenerate + always @(t.cyc) begin + if (t.cyc == 3) $display("mod b has scope = %m"); + if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); + end endmodule module c (); - always @ (t.cyc) begin - if (t.cyc == 4) $display("mod c has scope = %m"); - if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); - end + always @(t.cyc) begin + if (t.cyc == 4) $display("mod c has scope = %m"); + if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); + end endmodule module tag (); - bit [100*8-1:0] scope; - initial begin - $sformat(scope,"%m"); - $display("created tag with scope = %0s",scope); - end + bit [100*8-1:0] scope; + initial begin + $sformat(scope, "%m"); + $display("created tag with scope = %0s", scope); + end endmodule diff --git a/test_regress/t/t_gen_var_bad.out b/test_regress/t/t_gen_var_bad.out index b6e9b81de..33bee20a4 100644 --- a/test_regress/t/t_gen_var_bad.out +++ b/test_regress/t/t_gen_var_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_gen_var_bad.v:10:7: Non-genvar used in generate for: 'i' +%Error: t/t_gen_var_bad.v:10:5: Non-genvar used in generate for: 'i' : ... note: In instance 't' - 10 | for (i=0; i<3; i=i+1) begin - | ^~~ + 10 | for (i = 0; i < 3; i = i + 1) begin + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_gen_var_bad.v b/test_regress/t/t_gen_var_bad.v index 5a38223e0..ab2036976 100644 --- a/test_regress/t/t_gen_var_bad.v +++ b/test_regress/t/t_gen_var_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer i; - generate - for (i=0; i<3; i=i+1) begin // Bad: i is not a genvar - end - endgenerate + integer i; + generate + for (i = 0; i < 3; i = i + 1) begin // Bad: i is not a genvar + end + endgenerate endmodule diff --git a/test_regress/t/t_generate_fatal_bad.out b/test_regress/t/t_generate_fatal_bad.out index aa62b75d5..78a3f88b1 100644 --- a/test_regress/t/t_generate_fatal_bad.out +++ b/test_regress/t/t_generate_fatal_bad.out @@ -1,12 +1,12 @@ %Warning-USERFATAL: "boom" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' +%Error: t/t_generate_fatal_bad.v:15:28: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... note: In instance 't.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst' - t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:13:29: ... Called from 'get_baz()' with parameters: + t/t_generate_fatal_bad.v:9:3: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:15:28: ... Called from 'get_baz()' with parameters: bar = ?32?h0 - 13 | localparam integer BAZ = get_baz(BAR); - | ^~~~~~~ + 15 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_generate_fatal_bad.v b/test_regress/t/t_generate_fatal_bad.v index 02b03c8a4..9069ad525 100644 --- a/test_regress/t/t_generate_fatal_bad.v +++ b/test_regress/t/t_generate_fatal_bad.v @@ -5,42 +5,46 @@ // SPDX-License-Identifier: CC0-1.0 function integer get_baz(input integer bar); - get_baz = bar; - $fatal(2, "boom"); + get_baz = bar; + $fatal(2, "boom"); endfunction -module foo #(parameter BAR = 0); - localparam integer BAZ = get_baz(BAR); +module foo #( + parameter BAR = 0 +); + localparam integer BAZ = get_baz(BAR); endmodule -module foo2 #(parameter QUX = 0); - genvar x; - generate - for (x = 0; x < 2; x++) begin: foo2_loop - foo #(.BAR (QUX + x)) foo_in_foo2_inst(); - end - endgenerate +module foo2 #( + parameter QUX = 0 +); + genvar x; + generate + for (x = 0; x < 2; x++) begin : foo2_loop + foo #(.BAR(QUX + x)) foo_in_foo2_inst (); + end + endgenerate endmodule module t; - genvar i, j; - generate - for (i = 0; i < 2; i++) begin: genloop - foo #(.BAR (i)) foo_inst(); + genvar i, j; + generate + for (i = 0; i < 2; i++) begin : genloop + foo #(.BAR(i)) foo_inst (); + end + for (i = 2; i < 4; i++) begin : gen_l1 + for (j = 0; j < 2; j++) begin : gen_l2 + foo #(.BAR(i + j * 2)) foo_inst2 (); end - for (i = 2; i < 4; i++) begin: gen_l1 - for (j = 0; j < 2; j++) begin: gen_l2 - foo #(.BAR (i + j*2)) foo_inst2(); - end - end - if (1 == 1) begin: cond_true - foo #(.BAR (6)) foo_inst3(); - end - if (1 == 1) begin // unnamed - foo #(.BAR (7)) foo_inst4(); - end - for (i = 8; i < 12; i = i + 2) begin: nested_loop - foo2 #(.QUX (i)) foo2_inst(); - end - endgenerate + end + if (1 == 1) begin : cond_true + foo #(.BAR(6)) foo_inst3 (); + end + if (1 == 1) begin // unnamed + foo #(.BAR(7)) foo_inst4 (); + end + for (i = 8; i < 12; i = i + 2) begin : nested_loop + foo2 #(.QUX(i)) foo2_inst (); + end + endgenerate endmodule diff --git a/test_regress/t/t_genfor_hier.v b/test_regress/t/t_genfor_hier.v index db73bbb02..b06a6b485 100644 --- a/test_regress/t/t_genfor_hier.v +++ b/test_regress/t/t_genfor_hier.v @@ -5,20 +5,20 @@ // SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module m1(); - logic v1; +module m1 (); + logic v1; endmodule module t; - for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b - m1 m1_inst(); - end - for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin - always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0; - end + for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b + m1 m1_inst (); + end + for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin + always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0; + end - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_genfor_init_o0.v b/test_regress/t/t_genfor_init_o0.v index 70fec250c..4fe72b2c9 100644 --- a/test_regress/t/t_genfor_init_o0.v +++ b/test_regress/t/t_genfor_init_o0.v @@ -5,6 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - genvar i; - for (i = 0; i < 0; i = i + 1) begin end + genvar i; + for (i = 0; i < 0; i = i + 1) begin + end endmodule diff --git a/test_regress/t/t_genfor_signed.v b/test_regress/t/t_genfor_signed.v index 8ee774a5f..86b2d5692 100644 --- a/test_regress/t/t_genfor_signed.v +++ b/test_regress/t/t_genfor_signed.v @@ -4,49 +4,40 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t # - ( - parameter PIPE = 4 - )(/*AUTOARG*/ - // Inputs - clk - ); +module t #( + parameter PIPE = 4 +) ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - // These are ok - sub #( - .P_STOP (1) - ) u_sub1 (); - sub #( - .P_STOP (0) - ) u_sub0 (); + // These are ok + sub #(.P_STOP(1)) u_sub1 (); + sub #(.P_STOP(0)) u_sub0 (); - genvar i; - for (i = -1; i < 1; i++) begin: SUB_PIPE - sub #( - .P_STOP (i) - ) u_sub (); - end + genvar i; + for (i = -1; i < 1; i++) begin : SUB_PIPE + sub #(.P_STOP(i)) u_sub (); + end - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module sub # - ( - parameter P_START = 1, - parameter P_STOP = 0 - )( - ); +module sub #( + parameter P_START = 1, + parameter P_STOP = 0 +) (); - initial begin - for (int i = P_START; i >= P_STOP; --i) begin - $display("%m %0d..%0d i=%0d", P_START, P_STOP, i); - end - end + initial begin + for (int i = P_START; i >= P_STOP; --i) begin + $display("%m %0d..%0d i=%0d", P_START, P_STOP, i); + end + end endmodule diff --git a/test_regress/t/t_hier_block0_bad.out b/test_regress/t/t_hier_block0_bad.out index 5d125ae97..027c2f0fe 100644 --- a/test_regress/t/t_hier_block0_bad.out +++ b/test_regress/t/t_hier_block0_bad.out @@ -1,17 +1,17 @@ -%Error: t/t_hier_block0_bad.v:21:11: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string and type param parameters +%Error: t/t_hier_block0_bad.v:21:10: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string and type param parameters : ... note: In instance 't' - 21 | sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0)); - | ^~~~~~~~ + 21 | sub0 #(UNPACKED) i_sub0 ( + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_hier_block0_bad.v:62:41: Cannot access non-port symbols inside hierarchical block +%Error: t/t_hier_block0_bad.v:77:39: Cannot access non-port symbols inside hierarchical block : ... note: In instance 't.i_sub0' - 62 | $display("%m: i_sub.x: %d", i_sub.x); - | ^ -%Error: t/t_hier_block0_bad.v:26:50: Cannot access non-port symbols inside hierarchical block + 77 | $display("%m: i_sub.x: %d", i_sub.x); + | ^ +%Error: t/t_hier_block0_bad.v:35:48: Cannot access non-port symbols inside hierarchical block : ... note: In instance 't' - 26 | $display("%d i_sub0.ff: %d", count, i_sub0.ff); - | ^~ -%Error: t/t_hier_block0_bad.v:27:63: Cannot access scope inside hierarchical block - 27 | $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); - | ^~~ + 35 | $display("%d i_sub0.ff: %d", count, i_sub0.ff); + | ^~ +%Error: t/t_hier_block0_bad.v:36:61: Cannot access scope inside hierarchical block + 36 | $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_hier_block0_bad.v b/test_regress/t/t_hier_block0_bad.v index 73cb1cab8..7a0101ae4 100644 --- a/test_regress/t/t_hier_block0_bad.v +++ b/test_regress/t/t_hier_block0_bad.v @@ -6,77 +6,98 @@ `define HIER_BLOCK /*verilator hier_block*/ -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - wire [7:0] out0; - wire [7:0] out1; - int count = 0; + wire [7:0] out0; + wire [7:0] out1; + int count = 0; - // unpacked array cannot be passed to hierarchical block - localparam logic UNPACKED[0:1] = '{1'b1, 1'b0}; - sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0)); - sub1 #(.T(logic[7:0])) i_sub1(.in(out0), .out(out1)); + // unpacked array cannot be passed to hierarchical block + localparam logic UNPACKED[0:1] = '{1'b1, 1'b0}; + sub0 #(UNPACKED) i_sub0 ( + .clk(clk), + .in(8'(count)), + .out(out0) + ); + sub1 #( + .T(logic [7:0]) + ) i_sub1 ( + .in(out0), + .out(out1) + ); - always_ff @(posedge clk) begin - // dotted access under hierarchical block is not allowed ... - $display("%d i_sub0.ff: %d", count, i_sub0.ff); - $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); - // ... Except for ports on a dierct hierarchical child - $display("%d i_sub0.out: %d", count, i_sub0.out); - $display("%d out1: %d", count, out1); - if (count == 16) begin - if (out1 == 15) begin - $write("*-* All Finished *-*\n"); - $finish; - end else begin - $write("Missmatch\n"); - $stop; - end + always_ff @(posedge clk) begin + // dotted access under hierarchical block is not allowed ... + $display("%d i_sub0.ff: %d", count, i_sub0.ff); + $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); + // ... Except for ports on a dierct hierarchical child + $display("%d i_sub0.out: %d", count, i_sub0.out); + $display("%d out1: %d", count, out1); + if (count == 16) begin + if (out1 == 15) begin + $write("*-* All Finished *-*\n"); + $finish; end - count <= count + 1; - end + else begin + $write("Missmatch\n"); + $stop; + end + end + count <= count + 1; + end endmodule module sub0 #( - parameter logic UNPACKED[0:1] = '{1'b0, 1'b1} - ) ( - input wire clk, - input wire [7:0] in, - output wire [7:0] out); `HIER_BLOCK + parameter logic UNPACKED[0:1] = '{1'b0, 1'b1} +) ( + input wire clk, + input wire [7:0] in, + output wire [7:0] out +); + `HIER_BLOCK - logic [7:0] ff; + logic [7:0] ff; - always_ff @(posedge clk) ff <= in; - assign out = ff; + always_ff @(posedge clk) ff <= in; + assign out = ff; - logic [7:0] gg; - sub0_sub0 i_sub(.in(ff), .out(gg)); + logic [7:0] gg; + sub0_sub0 i_sub ( + .in(ff), + .out(gg) + ); - always_ff @(posedge clk) begin - // dotted access under hierarchical block is not allowed ... - $display("%m: i_sub.x: %d", i_sub.x); - // ... Except for ports on a direct hierarchical child - $display("%m: i_sub.out: %d", i_sub.out); - end + always_ff @(posedge clk) begin + // dotted access under hierarchical block is not allowed ... + $display("%m: i_sub.x: %d", i_sub.x); + // ... Except for ports on a direct hierarchical child + $display("%m: i_sub.out: %d", i_sub.out); + end endmodule module sub1 #( - parameter type T = logic - ) ( - input wire T in, output wire T out); `HIER_BLOCK - assign out = in; + parameter type T = logic +) ( + input wire T in, + output wire T out +); + `HIER_BLOCK + assign out = in; - sub1_sub #(T) sub(in, out); + sub1_sub #(T) sub ( + in, + out + ); endmodule module sub0_sub0 ( - input wire [7:0] in, - output wire [7:0] out + input wire [7:0] in, + output wire [7:0] out ); `HIER_BLOCK wire [7:0] x = in + 1; diff --git a/test_regress/t/t_hier_block1_bad.out b/test_regress/t/t_hier_block1_bad.out index df2b64a25..c265f1cc9 100644 --- a/test_regress/t/t_hier_block1_bad.out +++ b/test_regress/t/t_hier_block1_bad.out @@ -1,17 +1,17 @@ -%Warning-HIERBLOCK: t/t_hier_block1_bad.v:16:8: Top module marked as hierarchical block, ignoring +%Warning-HIERBLOCK: t/t_hier_block1_bad.v:19:8: Top module marked as hierarchical block, ignoring : ... note: In instance 't' : ... Suggest remove verilator hier_block on this module - 16 | module t ( + 19 | module t ( | ^ ... For warning description see https://verilator.org/warn/HIERBLOCK?v=latest ... Use "/* verilator lint_off HIERBLOCK */" and lint_on around source to disable this message. -%Error: t/t_hier_block1_bad.v:45:32: Modport cannot be used at the hierarchical block boundary +%Error: t/t_hier_block1_bad.v:59:23: Modport cannot be used at the hierarchical block boundary : ... note: In instance 't.i_sub1' - 45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/ - | ^~ + 59 | byte_ifs.receiver in, + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_hier_block1_bad.v:45:52: Modport cannot be used at the hierarchical block boundary +%Error: t/t_hier_block1_bad.v:60:21: Modport cannot be used at the hierarchical block boundary : ... note: In instance 't.i_sub1' - 45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/ - | ^~~ + 60 | byte_ifs.sender out + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_hier_block1_bad.v b/test_regress/t/t_hier_block1_bad.v index aa6e9c58d..6889f0770 100644 --- a/test_regress/t/t_hier_block1_bad.v +++ b/test_regress/t/t_hier_block1_bad.v @@ -6,42 +6,59 @@ `define HIER_BLOCK /*verilator hier_block*/ -interface byte_ifs(input clk); - logic [7:0] data; - modport sender(input clk, output data); - modport receiver(input clk, input data); -endinterface; +interface byte_ifs ( + input clk +); + logic [7:0] data; + modport sender(input clk, output data); + modport receiver(input clk, input data); +endinterface +; -module t (/*AUTOARG*/ - // Inputs - clk - ); `HIER_BLOCK // Top module can not be a hierarchy block - input wire clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + `HIER_BLOCK // Top module can not be a hierarchy block + input wire clk; - wire [7:0] out0; - int count = 0; + wire [7:0] out0; + int count = 0; - byte_ifs in_ifs(.clk(clk)); - byte_ifs out_ifs(.clk(clk)); - assign in_ifs.data = out0; + byte_ifs in_ifs (.clk(clk)); + byte_ifs out_ifs (.clk(clk)); + assign in_ifs.data = out0; - sub0 i_sub0(.clk(clk), .in(count), .out(out0)); - sub1 i_sub1(.in(in_ifs), .out(out_ifs)); + sub0 i_sub0 ( + .clk(clk), + .in(count), + .out(out0) + ); + sub1 i_sub1 ( + .in(in_ifs), + .out(out_ifs) + ); endmodule module sub0 ( - input wire clk, - input wire [7:0] in, - output wire [7:0] out); `HIER_BLOCK + input wire clk, + input wire [7:0] in, + output wire [7:0] out +); + `HIER_BLOCK - logic [7:0] ff; + logic [7:0] ff; - always_ff @(posedge clk) ff <= in; - assign out = ff; + always_ff @(posedge clk) ff <= in; + assign out = ff; endmodule -module sub1 (byte_ifs.receiver in, byte_ifs.sender out); `HIER_BLOCK - assign out.data = in.data; +module sub1 ( + byte_ifs.receiver in, + byte_ifs.sender out +); + `HIER_BLOCK + assign out.data = in.data; endmodule diff --git a/test_regress/t/t_hier_block_import.v b/test_regress/t/t_hier_block_import.v index d728e50ae..6a6fd82ff 100644 --- a/test_regress/t/t_hier_block_import.v +++ b/test_regress/t/t_hier_block_import.v @@ -6,25 +6,24 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(/*AUTOARG*/ - // inputs - clk +module t ( + input clk ); - input clk; - bit [31:0] outA; - bit [31:0] outB; - subA subA(.out(outA)); - subB subB(.out(outB)); + bit [31:0] outA; + bit [31:0] outB; - always @(posedge clk) begin - if (outA == `VALUE_A && outB == `VALUE_B) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Mismatch\n"); - $stop; - end - end + subA subA (.out(outA)); + subB subB (.out(outB)); + + always @(posedge clk) begin + if (outA == `VALUE_A && outB == `VALUE_B) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Mismatch\n"); + $stop; + end + end endmodule diff --git a/test_regress/t/t_hier_block_int.v b/test_regress/t/t_hier_block_int.v index 6738b53f9..d1d4eaf70 100644 --- a/test_regress/t/t_hier_block_int.v +++ b/test_regress/t/t_hier_block_int.v @@ -6,45 +6,50 @@ // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(/*AUTOARG*/ - // inputs - clk +module t ( + input clk ); - input clk; - byte out1; - shortint out2; - int out3; - longint out4; - integer out5; - time out6; + byte out1; + shortint out2; + int out3; + longint out4; + integer out5; + time out6; - sub sub(out1, out2, out3, out4, out5, out6); + sub sub ( + out1, + out2, + out3, + out4, + out5, + out6 + ); - always_ff @(posedge clk) begin - if (out1 == 1 && out2 == 2 && out3 == 3 && out4 == 4 && out5 == 5 && out6 == 6) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Mismatch\n"); - $stop; - end - end + always_ff @(posedge clk) begin + if (out1 == 1 && out2 == 2 && out3 == 3 && out4 == 4 && out5 == 5 && out6 == 6) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Mismatch\n"); + $stop; + end + end endmodule -module sub( - output byte out1, - output shortint out2, - output int out3, - output longint out4, - output integer out5, - output time out6 -); /*verilator hier_block*/ - assign out1 = 1; - assign out2 = 2; - assign out3 = 3; - assign out4 = 4; - assign out5 = 5; - assign out6 = 6; +module sub ( + output byte out1, + output shortint out2, + output int out3, + output longint out4, + output integer out5, + output time out6 +); /*verilator hier_block*/ + assign out1 = 1; + assign out2 = 2; + assign out3 = 3; + assign out4 = 4; + assign out5 = 5; + assign out6 = 6; endmodule diff --git a/test_regress/t/t_hier_block_libmod.v b/test_regress/t/t_hier_block_libmod.v index a32bb5e7f..d0bbb9993 100644 --- a/test_regress/t/t_hier_block_libmod.v +++ b/test_regress/t/t_hier_block_libmod.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Unlicense module t; - t_flag_relinc_sub i_t_flag_relinc_sub(); + t_flag_relinc_sub i_t_flag_relinc_sub(); endmodule `ifdef VERILATOR diff --git a/test_regress/t/t_hier_block_perf.v b/test_regress/t/t_hier_block_perf.v index ab1ac4b80..0a632c451 100644 --- a/test_regress/t/t_hier_block_perf.v +++ b/test_regress/t/t_hier_block_perf.v @@ -7,218 +7,233 @@ // based on t_gate_ormux `ifndef CORES - `define CORES 4 +`define CORES 4 `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - generate - for (genvar i = 0; i < `CORES; ++i) Core core(clk); - for (genvar i = 0; i < `CORES; ++i) CoreHier hierCore(clk); - endgenerate + generate + for (genvar i = 0; i < `CORES; ++i) Core core (clk); + for (genvar i = 0; i < `CORES; ++i) CoreHier hierCore (clk); + endgenerate endmodule -module Core(input clk); - reg [63:0] crc; - logic [31:0] rdata; - logic [31:0] rdata2; - wire [31:0] wdata = crc[31:0]; - wire [15:0] sel = {11'h0, crc[36:32]}; - wire we = crc[48]; +module Core ( + input clk +); + reg [63:0] crc; + logic [31:0] rdata; + logic [31:0] rdata2; + wire [31:0] wdata = crc[31:0]; + wire [15:0] sel = {11'h0, crc[36:32]}; + wire we = crc[48]; - Test test ( - // Outputs - .rdata (rdata[31:0]), - .rdata2 (rdata2[31:0]), - // Inputs - .clk (clk), - .we (we), - .sel (sel[15:0]), - .wdata (wdata[31:0])); - wire [63:0] result = {rdata2, rdata}; + Test test ( + // Outputs + .rdata(rdata[31:0]), + .rdata2(rdata2[31:0]), + // Inputs + .clk(clk), + .we(we), + .sel(sel[15:0]), + .wdata(wdata[31:0]) + ); + wire [63:0] result = {rdata2, rdata}; - Check check(.clk(clk), .crc(crc), .result(result), .rdata(rdata), .rdata2(rdata2)); + Check check ( + .clk(clk), + .crc(crc), + .result(result), + .rdata(rdata), + .rdata2(rdata2) + ); endmodule -module CoreHier(input clk); - // Dummy logic to have two different hier blocks at the same level. - integer cyc = 0; - always @(posedge clk) begin - cyc += 1; - if (cyc == 1) $display("%d", clk); - end +module CoreHier ( + input clk +); + // Dummy logic to have two different hier blocks at the same level. + integer cyc = 0; + always @(posedge clk) begin + cyc += 1; + if (cyc == 1) $display("%d", clk); + end endmodule -module Check( - input clk, - output reg [63:0] crc, - input wire [63:0] result, - input logic [31:0] rdata, - input logic [31:0] rdata2 - ); /*verilator hier_block*/ - integer cyc = 0; - reg [63:0] sum; +module Check ( + input clk, + output reg [63:0] crc, + input wire [63:0] result, + input logic [31:0] rdata, + input logic [31:0] rdata2 +); /*verilator hier_block*/ + integer cyc = 0; + reg [63:0] sum; - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (rdata2 != rdata) $stop; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h8977713eb467bc86 - if (sum !== `EXPECTED_SUM) $stop; - end - else if (cyc == `SIM_CYCLES) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (rdata2 != rdata) $stop; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + `define EXPECTED_SUM 64'h8977713eb467bc86 + if (sum !== `EXPECTED_SUM) $stop; + end + else if (cyc == `SIM_CYCLES) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test(/*AUTOARG*/ - // Outputs - rdata, rdata2, - // Inputs - clk, we, sel, wdata - ); /*verilator hier_block*/ - input clk; - input we; - input [15:0] sel; - input [31:0] wdata; - output logic [31:0] rdata; - output logic [31:0] rdata2; +module Test ( /*AUTOARG*/ + // Outputs + rdata, + rdata2, + // Inputs + clk, + we, + sel, + wdata +); /*verilator hier_block*/ + input clk; + input we; + input [15:0] sel; + input [31:0] wdata; + output logic [31:0] rdata; + output logic [31:0] rdata2; - logic we_d1r; - logic [15:0] sel_d1r; - logic [31:0] wdata_d1r; - always_ff @ (posedge clk) begin - we_d1r <= we; - sel_d1r <= sel; - wdata_d1r <= wdata; - end + logic we_d1r; + logic [15:0] sel_d1r; + logic [31:0] wdata_d1r; + always_ff @(posedge clk) begin + we_d1r <= we; + sel_d1r <= sel; + wdata_d1r <= wdata; + end - reg [31:0] csr0000; - reg [31:0] csr0001; - reg [31:0] csr0002; - reg [31:0] csr0003; - reg [31:0] csr0004; - reg [31:0] csr0005; - reg [31:0] csr0006; - reg [31:0] csr0007; - reg [31:0] csr0008; - reg [31:0] csr0009; - reg [31:0] csr000a; - reg [31:0] csr000b; - reg [31:0] csr000c; - reg [31:0] csr000d; - reg [31:0] csr000e; - reg [31:0] csr000f; - wire [31:0] csr0010 = 32'h33675230; - wire [31:0] csr0011 = 32'h00fa2144; - wire [31:0] csr0012 = 32'h6a5e8e10; - wire [31:0] csr0013 = 32'h000a5b5e; - wire [31:0] csr0014 = 32'h002fe51b; - wire [31:0] csr0015 = 32'h00027e00; - wire [31:0] csr0016 = 32'h0000e3c0; - wire [31:0] csr0017 = 32'h00efcf16; - wire [31:0] csr0018 = 32'h007a2600; - wire [31:0] csr0019 = 32'h0a4a9f10; - wire [31:0] csr001a = 32'h7d789de3; - wire [31:0] csr001b = 32'h40f655f9; - wire [31:0] csr001c = 32'hadad01f4; - wire [31:0] csr001d = 32'h02e7b33c; - wire [31:0] csr001e = 32'h12101533; - wire [31:0] csr001f = 32'h2cc1cce5; - initial begin - csr0000 = 32'he172d365; - csr0001 = 32'h35cc25e2; - csr0002 = 32'haf48436e; - csr0003 = 32'h135e55e4; - csr0004 = 32'h5fd6e48a; - csr0005 = 32'hb07d34ad; - csr0006 = 32'h2aa05deb; - csr0007 = 32'hfe97b680; - csr0008 = 32'h960f20bb; - csr0009 = 32'h251129f0; - csr000a = 32'hef3d2f93; - csr000b = 32'hef4bc127; - csr000c = 32'h3dfecb10; - csr000d = 32'h1b4690f5; - csr000e = 32'ha07822ab; - csr000f = 32'hf817cbf6; - end + reg [31:0] csr0000; + reg [31:0] csr0001; + reg [31:0] csr0002; + reg [31:0] csr0003; + reg [31:0] csr0004; + reg [31:0] csr0005; + reg [31:0] csr0006; + reg [31:0] csr0007; + reg [31:0] csr0008; + reg [31:0] csr0009; + reg [31:0] csr000a; + reg [31:0] csr000b; + reg [31:0] csr000c; + reg [31:0] csr000d; + reg [31:0] csr000e; + reg [31:0] csr000f; + wire [31:0] csr0010 = 32'h33675230; + wire [31:0] csr0011 = 32'h00fa2144; + wire [31:0] csr0012 = 32'h6a5e8e10; + wire [31:0] csr0013 = 32'h000a5b5e; + wire [31:0] csr0014 = 32'h002fe51b; + wire [31:0] csr0015 = 32'h00027e00; + wire [31:0] csr0016 = 32'h0000e3c0; + wire [31:0] csr0017 = 32'h00efcf16; + wire [31:0] csr0018 = 32'h007a2600; + wire [31:0] csr0019 = 32'h0a4a9f10; + wire [31:0] csr001a = 32'h7d789de3; + wire [31:0] csr001b = 32'h40f655f9; + wire [31:0] csr001c = 32'hadad01f4; + wire [31:0] csr001d = 32'h02e7b33c; + wire [31:0] csr001e = 32'h12101533; + wire [31:0] csr001f = 32'h2cc1cce5; + initial begin + csr0000 = 32'he172d365; + csr0001 = 32'h35cc25e2; + csr0002 = 32'haf48436e; + csr0003 = 32'h135e55e4; + csr0004 = 32'h5fd6e48a; + csr0005 = 32'hb07d34ad; + csr0006 = 32'h2aa05deb; + csr0007 = 32'hfe97b680; + csr0008 = 32'h960f20bb; + csr0009 = 32'h251129f0; + csr000a = 32'hef3d2f93; + csr000b = 32'hef4bc127; + csr000c = 32'h3dfecb10; + csr000d = 32'h1b4690f5; + csr000e = 32'ha07822ab; + csr000f = 32'hf817cbf6; + end - always_ff @ (posedge clk) begin - if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; - if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; - end + always_ff @(posedge clk) begin + if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; + end - wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; - wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; - wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; - wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; - assign rdata = (32'h0 + assign rdata = (32'h0 | {32{dec0000}} & csr0000 | {32{dec0001}} & csr0001 | {32{dec0002}} & csr0002 @@ -253,42 +268,42 @@ module Test(/*AUTOARG*/ | {32{dec001f}} & csr001f ); - always_comb begin - case (sel_d1r) - 16'h0000: rdata2 = csr0000; - 16'h0001: rdata2 = csr0001; - 16'h0002: rdata2 = csr0002; - 16'h0003: rdata2 = csr0003; - 16'h0004: rdata2 = csr0004; - 16'h0005: rdata2 = csr0005; - 16'h0006: rdata2 = csr0006; - 16'h0007: rdata2 = csr0007; - 16'h0008: rdata2 = csr0008; - 16'h0009: rdata2 = csr0009; - 16'h000a: rdata2 = csr000a; - 16'h000b: rdata2 = csr000b; - 16'h000c: rdata2 = csr000c; - 16'h000d: rdata2 = csr000d; - 16'h000e: rdata2 = csr000e; - 16'h000f: rdata2 = csr000f; - 16'h0010: rdata2 = csr0010; - 16'h0011: rdata2 = csr0011; - 16'h0012: rdata2 = csr0012; - 16'h0013: rdata2 = csr0013; - 16'h0014: rdata2 = csr0014; - 16'h0015: rdata2 = csr0015; - 16'h0016: rdata2 = csr0016; - 16'h0017: rdata2 = csr0017; - 16'h0018: rdata2 = csr0018; - 16'h0019: rdata2 = csr0019; - 16'h001a: rdata2 = csr001a; - 16'h001b: rdata2 = csr001b; - 16'h001c: rdata2 = csr001c; - 16'h001d: rdata2 = csr001d; - 16'h001e: rdata2 = csr001e; - 16'h001f: rdata2 = csr001f; - default: rdata2 = 0; - endcase - end + always_comb begin + case (sel_d1r) + 16'h0000: rdata2 = csr0000; + 16'h0001: rdata2 = csr0001; + 16'h0002: rdata2 = csr0002; + 16'h0003: rdata2 = csr0003; + 16'h0004: rdata2 = csr0004; + 16'h0005: rdata2 = csr0005; + 16'h0006: rdata2 = csr0006; + 16'h0007: rdata2 = csr0007; + 16'h0008: rdata2 = csr0008; + 16'h0009: rdata2 = csr0009; + 16'h000a: rdata2 = csr000a; + 16'h000b: rdata2 = csr000b; + 16'h000c: rdata2 = csr000c; + 16'h000d: rdata2 = csr000d; + 16'h000e: rdata2 = csr000e; + 16'h000f: rdata2 = csr000f; + 16'h0010: rdata2 = csr0010; + 16'h0011: rdata2 = csr0011; + 16'h0012: rdata2 = csr0012; + 16'h0013: rdata2 = csr0013; + 16'h0014: rdata2 = csr0014; + 16'h0015: rdata2 = csr0015; + 16'h0016: rdata2 = csr0016; + 16'h0017: rdata2 = csr0017; + 16'h0018: rdata2 = csr0018; + 16'h0019: rdata2 = csr0019; + 16'h001a: rdata2 = csr001a; + 16'h001b: rdata2 = csr001b; + 16'h001c: rdata2 = csr001c; + 16'h001d: rdata2 = csr001d; + 16'h001e: rdata2 = csr001e; + 16'h001f: rdata2 = csr001f; + default: rdata2 = 0; + endcase + end endmodule diff --git a/test_regress/t/t_hier_block_signed_logic.v b/test_regress/t/t_hier_block_signed_logic.v index b2dcd97c8..09ae111bd 100644 --- a/test_regress/t/t_hier_block_signed_logic.v +++ b/test_regress/t/t_hier_block_signed_logic.v @@ -6,46 +6,54 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(/*AUTOARG*/ - // inputs - clk +module t ( + input clk ); - input clk; - logic signed [31:0] in1 = 3; - logic signed [31:0] in2 = 4; - logic signed in_small1 = 1; - logic signed in_small2 = -1; + logic signed [31:0] in1 = 3; + logic signed [31:0] in2 = 4; + logic signed in_small1 = 1; + logic signed in_small2 = -1; - logic signed [31:0] out1; - logic signed [31:0] out2; - logic signed out_small1; - logic signed out_small2; + logic signed [31:0] out1; + logic signed [31:0] out2; + logic signed out_small1; + logic signed out_small2; - sub sub1(.in(in1), .in_small(in_small1), .out(out1), .out_small(out_small1)); - sub sub2(.in(in2), .in_small(in_small2), .out(out2), .out_small(out_small2)); + sub sub1 ( + .in(in1), + .in_small(in_small1), + .out(out1), + .out_small(out_small1) + ); + sub sub2 ( + .in(in2), + .in_small(in_small2), + .out(out2), + .out_small(out_small2) + ); - always_ff @(posedge clk) begin - if (out1 == signed'(-3) + always_ff @(posedge clk) begin + if (out1 == signed'(-3) && out2 == signed'(-4) && out_small1 == signed'(1'b1) && out_small2 == signed'(1'b1)) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("Mismatch\n"); - $stop; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("Mismatch\n"); + $stop; + end + end endmodule -module sub( - input logic signed [31:0] in, - input logic signed in_small, - output logic signed [31:0] out, - output logic signed out_small -); /*verilator hier_block*/ - assign out = -in; - assign out_small = -in_small; +module sub ( + input logic signed [31:0] in, + input logic signed in_small, + output logic signed [31:0] out, + output logic signed out_small +); /*verilator hier_block*/ + assign out = -in; + assign out_small = -in_small; endmodule diff --git a/test_regress/t/t_hier_block_struct.v b/test_regress/t/t_hier_block_struct.v index 168392b72..4fa39e12a 100644 --- a/test_regress/t/t_hier_block_struct.v +++ b/test_regress/t/t_hier_block_struct.v @@ -4,95 +4,91 @@ // SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 -typedef struct packed { - logic x; -} nested_named_t; +typedef struct packed {logic x;} nested_named_t; typedef struct packed { - struct packed { - logic x; - } nested_anonymous; - nested_named_t nested_named; - logic [1:0] x; + struct packed {logic x;} nested_anonymous; + nested_named_t nested_named; + logic [1:0] x; } nibble_t; -module t( - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - logic [63:0] crc; - logic [63:0] sum; + integer cyc = 0; + logic [63:0] crc; + logic [63:0] sum; - // Take CRC data and apply to testblock inputs - nibble_t[7:0] in; - assign in = crc[31:0]; + // Take CRC data and apply to testblock inputs + nibble_t [7:0] in; + assign in = crc[31:0]; - nibble_t[7:0] out; + nibble_t [7:0] out; - Test test( - .out0 ({out[1], out[0]}), - .out1 ({{out[5], out[4]}, {out[3], out[2]}}), - .out2 (out[6]), - .out3 (out[7]), - .clk (clk), - .in0 (in[0]), - .in1 (in[1]), - .in2 ({in[5], in[4], in[3], in[2]}), - .in3 ({in[7], in[6]})); + Test test ( + .out0({out[1], out[0]}), + .out1({{out[5], out[4]}, {out[3], out[2]}}), + .out2(out[6]), + .out3(out[7]), + .clk(clk), + .in0(in[0]), + .in1(in[1]), + .in2({in[5], in[4], in[3], in[2]}), + .in3({in[7], in[6]}) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test( - // Outputs - output nibble_t [1:0] out0, - output nibble_t [1:0] out1[2], - output nibble_t out2, - output nibble_t out3, - // Inputs - input clk, - input nibble_t in0, - input nibble_t in1, - input nibble_t [3:0] in2, - input nibble_t in3[2] - ); /*verilator hier_block*/ +module Test ( + // Outputs + output nibble_t [1:0] out0, + output nibble_t [1:0] out1[2], + output nibble_t out2, + output nibble_t out3, + // Inputs + input clk, + input nibble_t in0, + input nibble_t in1, + input nibble_t [3:0] in2, + input nibble_t in3[2] +); /*verilator hier_block*/ - always @(posedge clk) begin - {out3, out2, out1[0], out1[1], out0} <= {in3[0], in3[1], in2, in1, in0}; - end + always @(posedge clk) begin + {out3, out2, out1[0], out1[1], out0} <= {in3[0], in3[1], in2, in1, in0}; + end endmodule diff --git a/test_regress/t/t_hier_block_threads_bad.out b/test_regress/t/t_hier_block_threads_bad.out index 7d31c58b0..a02f41630 100644 --- a/test_regress/t/t_hier_block_threads_bad.out +++ b/test_regress/t/t_hier_block_threads_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_hier_block_threads_bad.v:23:8: Hierarchical blocks cannot be scheduled on more threads than in thread pool, threads = 4 hierarchical block threads = 8 +%Error: t/t_hier_block_threads_bad.v:21:8: Hierarchical blocks cannot be scheduled on more threads than in thread pool, threads = 4 hierarchical block threads = 8 : ... note: In instance 't.genblk1[1].hierCore' - 23 | module Core(input clk); /*verilator hier_block*/ + 21 | module Core ( | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_hier_block_threads_bad.vlt:9:1: Specifying workers for nested hierarchical blocks diff --git a/test_regress/t/t_hier_block_threads_bad.v b/test_regress/t/t_hier_block_threads_bad.v index b2dc314a0..2f3bb5d17 100644 --- a/test_regress/t/t_hier_block_threads_bad.v +++ b/test_regress/t/t_hier_block_threads_bad.v @@ -4,29 +4,31 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - generate - for (genvar i = 0; i < 2; ++i) Core hierCore(clk); - endgenerate + generate + for (genvar i = 0; i < 2; ++i) Core hierCore (clk); + endgenerate - always @(negedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(negedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Core(input clk); /* verilator hier_block */ - generate - for (genvar i = 0; i < 2; ++i) SubCore sub(clk); - endgenerate - always @(posedge clk) $display("%m"); +module Core ( + input clk +); /* verilator hier_block */ + generate + for (genvar i = 0; i < 2; ++i) SubCore sub (clk); + endgenerate + always @(posedge clk) $display("%m"); endmodule -module SubCore(input clk); /* verilator hier_block */ - always @(posedge clk) $display("%m"); +module SubCore ( + input clk +); /* verilator hier_block */ + always @(posedge clk) $display("%m"); endmodule diff --git a/test_regress/t/t_hier_block_type_param.v b/test_regress/t/t_hier_block_type_param.v index 4ccebbd46..9a6b07641 100644 --- a/test_regress/t/t_hier_block_type_param.v +++ b/test_regress/t/t_hier_block_type_param.v @@ -4,32 +4,36 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t( - clk - ); - input clk; - logic [31:0] in1; - logic [31:0] out1; +module t ( + input clk +); + logic [31:0] in1; + logic [31:0] out1; - assign in1 = 0; + assign in1 = 0; - Test #(.TYPE_t(logic[31:0])) test(.out (out1), .in (in1)); + Test #( + .TYPE_t(logic [31:0]) + ) test ( + .out(out1), + .in(in1) + ); - always @ (posedge clk) begin - if (out1 !== ~in1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (out1 !== ~in1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test - #(parameter type TYPE_t = logic [4:0]) - ( - output TYPE_t out, - input TYPE_t in - ); - /*verilator hier_block*/ +module Test #( + parameter type TYPE_t = logic [4:0] +) ( + output TYPE_t out, + input TYPE_t in +); + /*verilator hier_block*/ - assign out = ~ in; + assign out = ~in; endmodule diff --git a/test_regress/t/t_hier_block_type_param_multiple.v b/test_regress/t/t_hier_block_type_param_multiple.v index 70dd8ce43..fa9f48e0d 100644 --- a/test_regress/t/t_hier_block_type_param_multiple.v +++ b/test_regress/t/t_hier_block_type_param_multiple.v @@ -4,32 +4,38 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t( - clk - ); - input clk; - logic [31:0] in1; - logic [31:0] out1; +module t ( + input clk +); + logic [31:0] in1; + logic [31:0] out1; - assign in1 = 0; + assign in1 = 0; - Test #(.TYPE_IN(logic[31:0]), .TYPE_OUT(logic[31:0])) test(.out (out1), .in (in1)); + Test #( + .TYPE_IN(logic [31:0]), + .TYPE_OUT(logic [31:0]) + ) test ( + .out(out1), + .in(in1) + ); - always @ (posedge clk) begin - if (out1 !== ~in1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (out1 !== ~in1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test - #(parameter type TYPE_IN = logic [4:0], parameter type TYPE_OUT = logic [7:0]) - ( - output TYPE_IN out, - input TYPE_OUT in - ); - /*verilator hier_block*/ +module Test #( + parameter type TYPE_IN = logic [4:0], + parameter type TYPE_OUT = logic [7:0] +) ( + output TYPE_IN out, + input TYPE_OUT in +); + /*verilator hier_block*/ - assign out = ~ in; + assign out = ~in; endmodule diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.v b/test_regress/t/t_hier_block_type_param_multiple_instances.v index 0339769fb..864f6013f 100644 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.v +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.v @@ -4,39 +4,49 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t( - clk - ); - input clk; - logic [21:0] in1; - logic [21:0] out1; +module t ( + input clk +); - assign in1 = 0; + logic [21:0] in1; + logic [21:0] out1; - Test #(.TYPE_t(logic[21:0])) test(.out (out1), .in (in1)); + assign in1 = 0; - logic [63:0] in2; - logic [63:0] out2; + Test #( + .TYPE_t(logic [21:0]) + ) test ( + .out(out1), + .in(in1) + ); - assign in2 = 0; - Test #(.TYPE_t(logic[63:0])) test2(.out (out2), .in (in2)); + logic [63:0] in2; + logic [63:0] out2; - always @ (posedge clk) begin - if (out1 !== ~in1) $stop; - if (out2 !== ~in2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + assign in2 = 0; + Test #( + .TYPE_t(logic [63:0]) + ) test2 ( + .out(out2), + .in(in2) + ); + + always @(posedge clk) begin + if (out1 !== ~in1) $stop; + if (out2 !== ~in2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test - #(parameter type TYPE_t = logic [4:0]) - ( - output TYPE_t out, - input TYPE_t in - ); - /*verilator hier_block*/ +module Test #( + parameter type TYPE_t = logic [4:0] +) ( + output TYPE_t out, + input TYPE_t in +); + /*verilator hier_block*/ - assign out = ~ in; + assign out = ~in; endmodule diff --git a/test_regress/t/t_hier_block_type_param_nested.v b/test_regress/t/t_hier_block_type_param_nested.v index 5d9bbe23c..ae7adf57a 100644 --- a/test_regress/t/t_hier_block_type_param_nested.v +++ b/test_regress/t/t_hier_block_type_param_nested.v @@ -4,50 +4,65 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t( - clk - ); - input clk; - logic [2:0] in1; - logic [2:0] out1; +module t ( + input clk +); - assign in1 = 0; + logic [2:0] in1; + logic [2:0] out1; - Test #(.TYPE_t(logic[2:0])) test(.out (out1), .in (in1)); + assign in1 = 0; - logic [3:0] in2; - logic [3:0] out2; + Test #( + .TYPE_t(logic [2:0]) + ) test ( + .out(out1), + .in(in1) + ); - assign in2 = 0; - Test #(.TYPE_t(logic[3:0])) test2(.out (out2), .in (in2)); + logic [3:0] in2; + logic [3:0] out2; - always @ (posedge clk) begin - if (out1 !== ~in1) $stop; - if (out2 !== ~in2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + assign in2 = 0; + Test #( + .TYPE_t(logic [3:0]) + ) test2 ( + .out(out2), + .in(in2) + ); + + always @(posedge clk) begin + if (out1 !== ~in1) $stop; + if (out2 !== ~in2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test - #(parameter type TYPE_t = logic [5:0]) - ( - output TYPE_t out, - input TYPE_t in - ); - /*verilator hier_block*/ +module Test #( + parameter type TYPE_t = logic [5:0] +) ( + output TYPE_t out, + input TYPE_t in +); + /*verilator hier_block*/ - SubTest #(.TYPE_t(TYPE_t)) subTest(.out(out), .in(in)); + SubTest #( + .TYPE_t(TYPE_t) + ) subTest ( + .out(out), + .in(in) + ); endmodule -module SubTest - #(parameter type TYPE_t = logic [8:0]) - ( - output TYPE_t out, - input TYPE_t in - ); - /*verilator hier_block*/ +module SubTest #( + parameter type TYPE_t = logic [8:0] +) ( + output TYPE_t out, + input TYPE_t in +); + /*verilator hier_block*/ - assign out = ~ in; + assign out = ~in; endmodule diff --git a/test_regress/t/t_hier_block_type_param_typedef.v b/test_regress/t/t_hier_block_type_param_typedef.v index bd43276d2..5e5a2055c 100644 --- a/test_regress/t/t_hier_block_type_param_typedef.v +++ b/test_regress/t/t_hier_block_type_param_typedef.v @@ -4,40 +4,50 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t( - clk - ); - input clk; - logic [21:0] in1; - logic [21:0] out1; +module t ( + input clk +); - assign in1 = 0; - typedef logic[21:0] PARAM_T; - Test #(.TYPE_t(PARAM_T)) test(.out (out1), .in (in1)); + logic [21:0] in1; + logic [21:0] out1; - logic [63:0] in2; - logic [63:0] out2; + assign in1 = 0; + typedef logic [21:0] PARAM_T; + Test #( + .TYPE_t(PARAM_T) + ) test ( + .out(out1), + .in(in1) + ); - assign in2 = 0; - typedef logic[63:0] PARAM2_T; - Test #(.TYPE_t(PARAM2_T)) test2(.out (out2), .in (in2)); + logic [63:0] in2; + logic [63:0] out2; - always @ (posedge clk) begin - if (out1 !== ~in1) $stop; - if (out2 !== ~in2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + assign in2 = 0; + typedef logic [63:0] PARAM2_T; + Test #( + .TYPE_t(PARAM2_T) + ) test2 ( + .out(out2), + .in(in2) + ); + + always @(posedge clk) begin + if (out1 !== ~in1) $stop; + if (out2 !== ~in2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module Test - #(parameter type TYPE_t = logic [4:0]) - ( - output TYPE_t out, - input TYPE_t in - ); - /*verilator hier_block*/ +module Test #( + parameter type TYPE_t = logic [4:0] +) ( + output TYPE_t out, + input TYPE_t in +); + /*verilator hier_block*/ - assign out = ~ in; + assign out = ~in; endmodule diff --git a/test_regress/t/t_hier_bynum.v b/test_regress/t/t_hier_bynum.v index aae47ed40..c5baebf58 100644 --- a/test_regress/t/t_hier_bynum.v +++ b/test_regress/t/t_hier_bynum.v @@ -4,27 +4,35 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: Unlicense -module flop (q, d, clk); - // No AUTOARG; order of below is different from port order above - input wire clk; - output reg q; - input wire d; +module flop ( + q, + d, + clk +); + // No AUTOARG; order of below is different from port order above + input wire clk; + output reg q; + input wire d; - // verilator hier_block + // verilator hier_block - always_ff @(posedge clk) begin - q <= d; - end + always_ff @(posedge clk) begin + q <= d; + end endmodule module t ( - output wire q, - input wire d, - input wire clk - ); + output wire q, + input wire d, + input wire clk +); - // This intentionally uses pin number ordering - flop u_flop(q, d, clk); + // This intentionally uses pin number ordering + flop u_flop ( + q, + d, + clk + ); endmodule diff --git a/test_regress/t/t_hier_task.v b/test_regress/t/t_hier_task.v index d8a34281d..5b6ed0d75 100644 --- a/test_regress/t/t_hier_task.v +++ b/test_regress/t/t_hier_task.v @@ -5,44 +5,44 @@ // SPDX-License-Identifier: CC0-1.0 module mod_a; - mod_inner u_inner(); - mod_a_mon u_a_mon(); + mod_inner u_inner (); + mod_a_mon u_a_mon (); - initial begin - bit x; + initial begin + bit x; - u_inner.x = 1; - u_a_mon.y = 0; - u_a_mon.accessor; + u_inner.x = 1; + u_a_mon.y = 0; + u_a_mon.accessor; - if (u_a_mon.y != 1) begin - $write("%%Error: Incorrect value placed in submodule\n"); - $stop; - end + if (u_a_mon.y != 1) begin + $write("%%Error: Incorrect value placed in submodule\n"); + $stop; + end - u_inner.x = 0; - u_a_mon.accessor; + u_inner.x = 0; + u_a_mon.accessor; - if (u_a_mon.y != 0) begin - $write("%%Error: Incorrect value placed in submodule\n"); - $stop; - end + if (u_a_mon.y != 0) begin + $write("%%Error: Incorrect value placed in submodule\n"); + $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule : mod_a module mod_inner; - logic x; + logic x; endmodule : mod_inner module mod_a_mon; - bit y; - function automatic void accessor; - begin : accessor_block - bit read_x = mod_a.u_inner.x; - y = read_x; - end - endfunction + bit y; + function automatic void accessor; + begin : accessor_block + bit read_x = mod_a.u_inner.x; + y = read_x; + end + endfunction endmodule diff --git a/test_regress/t/t_hier_trace.v b/test_regress/t/t_hier_trace.v index 0c67b41a3..66b43284a 100644 --- a/test_regress/t/t_hier_trace.v +++ b/test_regress/t/t_hier_trace.v @@ -4,21 +4,22 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t( +module t ( input clk, - input reset_l); + input reset_l +); - sub_top u0_sub_top( - .clk(clk), - .reset_l(reset_l) - ); - sub_top u1_sub_top( - .clk(clk), - .reset_l(reset_l) - ); + sub_top u0_sub_top ( + .clk(clk), + .reset_l(reset_l) + ); + sub_top u1_sub_top ( + .clk(clk), + .reset_l(reset_l) + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_hierarchy_identifier.v b/test_regress/t/t_hierarchy_identifier.v index 6c65f48a0..66f86b121 100644 --- a/test_regress/t/t_hierarchy_identifier.v +++ b/test_regress/t/t_hierarchy_identifier.v @@ -4,51 +4,45 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + parameter SIZE = 8; - parameter SIZE = 8; + integer cnt = 0; - integer cnt = 0; + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; - logic [SIZE-1:0] vld_for; - logic vld_if = 1'b0; - logic vld_else = 1'b0; + genvar i; - genvar i; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if (cnt==SIZE) begin : \0escaped___name + // finish report + always @(posedge clk) + if (cnt == SIZE) begin : \0escaped___name $write("*-* All Finished *-*\n"); $finish; - end : \0escaped___name + end : \0escaped___name - generate - for (i=0; i0) begin : generate_if_if - always @ (posedge clk) - vld_if <= 1'b1; - end : generate_if_if - else begin : generate_if_else - always @ (posedge clk) - vld_else <= 1'b1; - end : generate_if_else - endgenerate + generate + if (SIZE > 0) begin : generate_if_if + always @(posedge clk) vld_if <= 1'b1; + end : generate_if_if + else begin : generate_if_else + always @(posedge clk) vld_else <= 1'b1; + end : generate_if_else + endgenerate endmodule : t diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out index fb853a322..ab4fb91d3 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.out +++ b/test_regress/t/t_hierarchy_identifier_bad.out @@ -1,17 +1,17 @@ -%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' - 34 | end : if_cnt_finish_bad - | ^~~~~~~~~~~~~~~~~ +%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:31:11: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' + 31 | end : if_cnt_finish_bad + | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/ENDLABEL?v=latest -%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' - 40 | end : generate_for_bad - | ^~~~~~~~~~~~~~~~ -%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' - 47 | end : generate_if_if_bad - | ^~~~~~~~~~~~~~~~~~ -%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' - 51 | end : generate_if_else_bad - | ^~~~~~~~~~~~~~~~~~~~ -%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't' - 54 | endmodule : t_bad +%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:36:11: End label 'generate_for_bad' does not match begin label 'generate_for' + 36 | end : generate_for_bad + | ^~~~~~~~~~~~~~~~ +%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:42:11: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' + 42 | end : generate_if_if_bad + | ^~~~~~~~~~~~~~~~~~ +%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:45:11: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' + 45 | end : generate_if_else_bad + | ^~~~~~~~~~~~~~~~~~~~ +%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:48:13: End label 't_bad' does not match begin label 't' + 48 | endmodule : t_bad | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_hierarchy_identifier_bad.v b/test_regress/t/t_hierarchy_identifier_bad.v index a92a70a28..ddb79d7e6 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.v +++ b/test_regress/t/t_hierarchy_identifier_bad.v @@ -4,51 +4,45 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + parameter SIZE = 8; - parameter SIZE = 8; + integer cnt = 0; - integer cnt = 0; + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; - logic [SIZE-1:0] vld_for; - logic vld_if = 1'b0; - logic vld_else = 1'b0; + genvar i; - genvar i; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if (cnt==SIZE) begin : if_cnt_finish + // finish report + always @(posedge clk) + if (cnt == SIZE) begin : if_cnt_finish $write("*-* All Finished *-*\n"); $finish; - end : if_cnt_finish_bad + end : if_cnt_finish_bad - generate - for (i=0; i0) begin : generate_if_if - always @ (posedge clk) - vld_if <= 1'b1; - end : generate_if_if_bad - else begin : generate_if_else - always @ (posedge clk) - vld_else <= 1'b1; - end : generate_if_else_bad - endgenerate + generate + if (SIZE > 0) begin : generate_if_if + always @(posedge clk) vld_if <= 1'b1; + end : generate_if_if_bad + else begin : generate_if_else + always @(posedge clk) vld_else <= 1'b1; + end : generate_if_else_bad + endgenerate endmodule : t_bad diff --git a/test_regress/t/t_hierarchy_unnamed.v b/test_regress/t/t_hierarchy_unnamed.v index e4540759f..b5625026f 100644 --- a/test_regress/t/t_hierarchy_unnamed.v +++ b/test_regress/t/t_hierarchy_unnamed.v @@ -4,22 +4,26 @@ // SPDX-FileCopyrightText: 2012 Chandan Egbert // SPDX-License-Identifier: CC0-1.0 -module sub(); +module sub (); endmodule -module t(input logic a, input logic b, - output logic x, output logic y); +module t ( + input logic a, + input logic b, + output logic x, + output logic y +); - always_comb begin - integer i; - x = a; - end + always_comb begin + integer i; + x = a; + end - sub u0(); + sub u0 (); - always_comb begin - integer j; - y = b; - end + always_comb begin + integer j; + y = b; + end endmodule diff --git a/test_regress/t/t_if_deep.v b/test_regress/t/t_if_deep.v index 9276b73d0..c4c5bd89d 100644 --- a/test_regress/t/t_if_deep.v +++ b/test_regress/t/t_if_deep.v @@ -4,55 +4,54 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out[31:0]), + // Inputs + .clk(clk), + .in(in[31:0]) + ); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // What checksum will we end up with -`define EXPECTED_SUM 64'h966e272fd829e672 + `define EXPECTED_SUM 64'h966e272fd829e672 // Test loop - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin + if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end - else if (cyc<10) begin + else if (cyc < 10) begin sum <= 64'h0; end - else if (cyc<90) begin + else if (cyc < 90) begin end - else if (cyc==99) begin + else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; @@ -63,26 +62,27 @@ module t (/*AUTOARG*/ endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); input clk; - input [31:0] in; + input [31:0] in; output [31:0] out; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [31:0] out; + reg [31:0] out; // End of automatics `ifdef verilator - `define dontOptimize $c1("1") + `define dontOptimize $c1("1") `else - `define dontOptimize 1'b1 + `define dontOptimize 1'b1 `endif always @(posedge clk) begin diff --git a/test_regress/t/t_if_same_bad.v b/test_regress/t/t_if_same_bad.v index 0f04bbf3f..87d04ea0f 100644 --- a/test_regress/t/t_if_same_bad.v +++ b/test_regress/t/t_if_same_bad.v @@ -6,53 +6,51 @@ // bug3806 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - reg [3:0] in; - tri [3:0] bus = in; + reg [3:0] in; + tri [3:0] bus = in; - int never_driven; - int never_forced; + int never_driven; + int never_forced; - task force_bus; - force bus[1:0] = 2'b10; - endtask + task force_bus; + force bus[1:0] = 2'b10; + endtask - task release_bus; - release bus; - endtask + task release_bus; + release bus; + endtask - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - in <= 4'b0101; - end - else if (cyc == 10) begin - $display("10"); - end - else if (cyc == 11) begin - $display("11"); - end - // - // bus - else if (cyc == 10) begin // Should warn - $display("10b"); - end - else if (cyc == 11) begin // Should warn - $display("11b"); - end - // - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + in <= 4'b0101; + end + else if (cyc == 10) begin + $display("10"); + end + else if (cyc == 11) begin + $display("11"); + end + // + // bus + else if (cyc == 10) begin // Should warn + $display("10b"); + end + else if (cyc == 11) begin // Should warn + $display("11b"); + end + // + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_if_swap.v b/test_regress/t/t_if_swap.v index a70708911..83df039a4 100644 --- a/test_regress/t/t_if_swap.v +++ b/test_regress/t/t_if_swap.v @@ -4,27 +4,24 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer f; + integer f; - always @(posedge clk) begin - if (!$feof(f)) begin - $display("Doing stuff with file."); - end - // Commenting out these two lines fixes the fault - else begin - end - if (!$feof(f)) begin - end - else begin - $display("Not doing stuff with file."); - end - end + always @(posedge clk) begin + if (!$feof(f)) begin + $display("Doing stuff with file."); + end + // Commenting out these two lines fixes the fault + else begin + end + if (!$feof(f)) begin + end + else begin + $display("Not doing stuff with file."); + end + end endmodule diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v index 4beb3f525..af415e16b 100644 --- a/test_regress/t/t_iff.v +++ b/test_regress/t/t_iff.v @@ -4,90 +4,86 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] result; // From test of Test.v - // End of automatics - Test test (.*); + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] result; // From test of Test.v + // End of automatics + Test test (.*); - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hd55eb7da9ba3354a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hd55eb7da9ba3354a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test - ( - input clk, - input [63:0] crc, - input [31:0] cyc, - output wire [63:0] result); +module Test ( + input clk, + input [63:0] crc, + input [31:0] cyc, + output wire [63:0] result +); - wire enable = crc[32]; - wire [7:0] d = crc[7:0]; + wire enable = crc[32]; + wire [7:0] d = crc[7:0]; - logic [7:0] d0_r; - always @(d iff enable) begin - d0_r <= d; - end + logic [7:0] d0_r; + always @(d iff enable) begin + d0_r <= d; + end - logic [7:0] d1_r; - always @(posedge d iff enable) begin - d1_r <= d; - end + logic [7:0] d1_r; + always @(posedge d iff enable) begin + d1_r <= d; + end - logic [7:0] d2_r; - always @(negedge d iff enable) begin - d2_r <= d; - end + logic [7:0] d2_r; + always @(negedge d iff enable) begin + d2_r <= d; + end - logic [7:0] d3_r; - always @(edge d iff enable) begin - d3_r <= d; - end + logic [7:0] d3_r; + always @(edge d iff enable) begin + d3_r <= d; + end - wire reset = (cyc < 10); - assert property (@(posedge clk iff enable) - disable iff (reset) - (crc != '0)); + wire reset = (cyc < 10); + assert property (@(posedge clk iff enable) disable iff (reset) (crc != '0)); - // Aggregate outputs into a single result vector - assign result = {32'h0, d3_r, d2_r, d1_r, d0_r}; + // Aggregate outputs into a single result vector + assign result = {32'h0, d3_r, d2_r, d1_r, d0_r}; endmodule diff --git a/test_regress/t/t_implements.v b/test_regress/t/t_implements.v index 1aef26518..00acdc6a7 100644 --- a/test_regress/t/t_implements.v +++ b/test_regress/t/t_implements.v @@ -8,63 +8,63 @@ interface class Icempty; endclass : Icempty interface class Icls1; - localparam LP1 = 1; - pure virtual function int icf1; - pure virtual function int icfboth; - pure virtual function int icfpartial; + localparam LP1 = 1; + pure virtual function int icf1; + pure virtual function int icfboth; + pure virtual function int icfpartial; endclass interface class Iext1 extends Icls1; - pure virtual function int icf101; + pure virtual function int icf101; endclass interface class Icls2; - pure virtual function int icf2(int in); - pure virtual function int icfboth; + pure virtual function int icf2(int in); + pure virtual function int icfboth; endclass virtual class Base implements Iext1, Icls2; - virtual function int icf1; - return 1; - endfunction - virtual function int icf101; - return 101; - endfunction - virtual function int icf2(int in); - return in + 2; - endfunction - virtual function int icfboth; - return 3; - endfunction - pure virtual function int icfpartial; + virtual function int icf1; + return 1; + endfunction + virtual function int icf101; + return 101; + endfunction + virtual function int icf2(int in); + return in + 2; + endfunction + virtual function int icfboth; + return 3; + endfunction + pure virtual function int icfpartial; endclass class Cls extends Base; - virtual function int icfpartial; - return 62; - endfunction + virtual function int icfpartial; + return 62; + endfunction endclass module t; - Cls c; - Iext1 i1; + Cls c; + Iext1 i1; - initial begin - if (Icls1::LP1 != 1) $stop; + initial begin + if (Icls1::LP1 != 1) $stop; - c = new; - if (c.icf1() != 1) $stop; - if (c.icf101() != 101) $stop; - if (c.icf2(1000) != 1002) $stop; - if (c.icfpartial() != 62) $stop; + c = new; + if (c.icf1() != 1) $stop; + if (c.icf101() != 101) $stop; + if (c.icf2(1000) != 1002) $stop; + if (c.icfpartial() != 62) $stop; - i1 = c; - if (i1.icf1() != 1) $stop; - if (i1.icf101() != 101) $stop; + i1 = c; + if (i1.icf1() != 1) $stop; + if (i1.icf101() != 101) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_implements_collision.v b/test_regress/t/t_implements_collision.v index df5ca2c92..bf692d893 100644 --- a/test_regress/t/t_implements_collision.v +++ b/test_regress/t/t_implements_collision.v @@ -5,33 +5,33 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls1; - pure virtual function int icfboth; + pure virtual function int icfboth; endclass interface class Icls2; - pure virtual function int icfboth; + pure virtual function int icfboth; endclass interface class IclsBoth extends Icls1, Icls2; - pure virtual function int icfboth; + pure virtual function int icfboth; endclass class Cls implements IclsBoth; - virtual function int icfboth; - return 3; - endfunction + virtual function int icfboth; + return 3; + endfunction endclass module t; - Cls c; + Cls c; - initial begin - c = new; - if (c.icfboth() != 3) $stop; + initial begin + c = new; + if (c.icfboth() != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_implements_collision_bad.out b/test_regress/t/t_implements_collision_bad.out index 1fba4459b..c641e56ae 100644 --- a/test_regress/t/t_implements_collision_bad.out +++ b/test_regress/t/t_implements_collision_bad.out @@ -1,14 +1,14 @@ %Error: t/t_implements_collision_bad.v:15:11: Class 'IclsBoth' implements 'Icls2' but missing inheritance conflict resolution for 'icfboth' (IEEE 1800-2023 8.26.6.2) 15 | interface class IclsBoth extends Icls1, Icls2; | ^~~~~ - t/t_implements_collision_bad.v:12:30: ... Location of interface class's function - 12 | pure virtual function int icfboth; - | ^~~~~~~ + t/t_implements_collision_bad.v:12:29: ... Location of interface class's function + 12 | pure virtual function int icfboth; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_implements_collision_bad.v:19:1: Class 'Cls' implements 'IclsBoth' but is missing implementation for 'icfboth' (IEEE 1800-2023 8.26) 19 | class Cls implements IclsBoth; | ^~~~~ - t/t_implements_collision_bad.v:8:30: ... Location of interface class's function - 8 | pure virtual function int icfboth; - | ^~~~~~~ + t/t_implements_collision_bad.v:8:29: ... Location of interface class's function + 8 | pure virtual function int icfboth; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_implements_collision_bad.v b/test_regress/t/t_implements_collision_bad.v index 488095e10..618629fc6 100644 --- a/test_regress/t/t_implements_collision_bad.v +++ b/test_regress/t/t_implements_collision_bad.v @@ -5,15 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls1; - pure virtual function int icfboth; + pure virtual function int icfboth; endclass interface class Icls2; - pure virtual function int icfboth; + pure virtual function int icfboth; endclass interface class IclsBoth extends Icls1, Icls2; - // Bad collision on icfboth + // Bad collision on icfboth endclass class Cls implements IclsBoth; @@ -22,15 +22,15 @@ endclass // This is not a collision - diamond interface class Ibase; - pure virtual function int fn(); + pure virtual function int fn(); endclass interface class Ic1 extends Ibase; - pure virtual function int fn1(); + pure virtual function int fn1(); endclass interface class Ic2 extends Ibase; - pure virtual function int fn2(); + pure virtual function int fn2(); endclass interface class Ic3 extends Ic1, Ic2; @@ -38,5 +38,5 @@ endclass module t; - Cls c; + Cls c; endmodule diff --git a/test_regress/t/t_implements_contents_bad.out b/test_regress/t/t_implements_contents_bad.out index 6a12a375c..26f65f32b 100644 --- a/test_regress/t/t_implements_contents_bad.out +++ b/test_regress/t/t_implements_contents_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_implements_contents_bad.v:8:8: Interface class cannot contain non-parameter members (IEEE 1800-2023 8.26): 'badi' - 8 | int badi; - | ^~~~ +%Error: t/t_implements_contents_bad.v:8:7: Interface class cannot contain non-parameter members (IEEE 1800-2023 8.26): 'badi' + 8 | int badi; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_implements_contents_bad.v:9:9: Interface class functions must be pure virtual (IEEE 1800-2023 8.26): 'badtask' - 9 | task badtask; - | ^~~~~~~ +%Error: t/t_implements_contents_bad.v:9:8: Interface class functions must be pure virtual (IEEE 1800-2023 8.26): 'badtask' + 9 | task badtask; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_implements_contents_bad.v b/test_regress/t/t_implements_contents_bad.v index 5f8531096..ffce2308d 100644 --- a/test_regress/t/t_implements_contents_bad.v +++ b/test_regress/t/t_implements_contents_bad.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls; - int badi; - task badtask; - endtask + int badi; + task badtask; + endtask endclass module t; diff --git a/test_regress/t/t_implements_missing_bad.out b/test_regress/t/t_implements_missing_bad.out index 9d33b1465..029ea9e2c 100644 --- a/test_regress/t/t_implements_missing_bad.out +++ b/test_regress/t/t_implements_missing_bad.out @@ -1,8 +1,8 @@ %Error: t/t_implements_missing_bad.v:12:1: Class 'Cls' implements 'Icls1' but is missing implementation for 'icf2' (IEEE 1800-2023 8.26) 12 | class Cls implements Icls1; | ^~~~~ - t/t_implements_missing_bad.v:9:30: ... Location of interface class's function - 9 | pure virtual function int icf2; - | ^~~~ + t/t_implements_missing_bad.v:9:29: ... Location of interface class's function + 9 | pure virtual function int icf2; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_implements_missing_bad.v b/test_regress/t/t_implements_missing_bad.v index 0ee7e3e18..3db5d5daf 100644 --- a/test_regress/t/t_implements_missing_bad.v +++ b/test_regress/t/t_implements_missing_bad.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls1; - pure virtual function int icf1; - pure virtual function int icf2; + pure virtual function int icf1; + pure virtual function int icf2; endclass class Cls implements Icls1; - virtual function int icf1; - return 1; - endfunction - // Bad missing icf2 + virtual function int icf1; + return 1; + endfunction + // Bad missing icf2 endclass module t; - Cls c; + Cls c; endmodule diff --git a/test_regress/t/t_implements_nested.v b/test_regress/t/t_implements_nested.v index 21934507c..f9398645d 100644 --- a/test_regress/t/t_implements_nested.v +++ b/test_regress/t/t_implements_nested.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - // IEEE 2023 only disallows nested interface inside another interface, not - // class - interface class good_can_nest; - endclass + // IEEE 2023 only disallows nested interface inside another interface, not + // class + interface class good_can_nest; + endclass endclass module t; - Cls c; + Cls c; endmodule diff --git a/test_regress/t/t_implements_nested_bad.out b/test_regress/t/t_implements_nested_bad.out index 204eb1006..3ec375c95 100644 --- a/test_regress/t/t_implements_nested_bad.out +++ b/test_regress/t/t_implements_nested_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_implements_nested_bad.v:9:17: Interface class shall not be nested within another interface class. (IEEE 1800-2023 8.26) - 9 | interface class bad_cannot_nest; - | ^~~~~ +%Error: t/t_implements_nested_bad.v:9:15: Interface class shall not be nested within another interface class. (IEEE 1800-2023 8.26) + 9 | interface class bad_cannot_nest; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_implements_nested_bad.v b/test_regress/t/t_implements_nested_bad.v index d82713e4e..8a785b8a8 100644 --- a/test_regress/t/t_implements_nested_bad.v +++ b/test_regress/t/t_implements_nested_bad.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - interface class inte; - interface class bad_cannot_nest; - endclass - endclass + interface class inte; + interface class bad_cannot_nest; + endclass + endclass endclass module t; - Cls c; + Cls c; endmodule diff --git a/test_regress/t/t_implements_new_bad.out b/test_regress/t/t_implements_new_bad.out index e04372ca9..2d1a3859a 100644 --- a/test_regress/t/t_implements_new_bad.out +++ b/test_regress/t/t_implements_new_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_implements_new_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'Icls' (IEEE 1800-2023 8.21) - : ... note: In instance 't' - 13 | c = new; - | ^~~ +%Error: t/t_implements_new_bad.v:13:9: Illegal to call 'new' using an abstract virtual class 'Icls' (IEEE 1800-2023 8.21) + : ... note: In instance 't' + 13 | c = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_implements_new_bad.v b/test_regress/t/t_implements_new_bad.v index e98806a88..c7363d0c7 100644 --- a/test_regress/t/t_implements_new_bad.v +++ b/test_regress/t/t_implements_new_bad.v @@ -8,10 +8,10 @@ interface class Icls; endclass module t; - Icls c; - initial begin - c = new; // Bad - $write("*-* All Finished *-*\n"); - $finish; - end + Icls c; + initial begin + c = new; // Bad + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_implements_noinherit_bad.out b/test_regress/t/t_implements_noinherit_bad.out index 6c609ec96..2fb90808a 100644 --- a/test_regress/t/t_implements_noinherit_bad.out +++ b/test_regress/t/t_implements_noinherit_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_implements_noinherit_bad.v:14:16: Can't find definition of variable: 'IP' - 14 | $display(IP); - | ^~ +%Error: t/t_implements_noinherit_bad.v:14:14: Can't find definition of variable: 'IP' + 14 | $display(IP); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_implements_noinherit_bad.v b/test_regress/t/t_implements_noinherit_bad.v index 8142b021c..69d27a6a3 100644 --- a/test_regress/t/t_implements_noinherit_bad.v +++ b/test_regress/t/t_implements_noinherit_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls; - localparam IP = 1; - typedef int i_t; + localparam IP = 1; + typedef int i_t; endclass class Cls implements Icls; - function void f; - $display(IP); // Bad - endfunction + function void f; + $display(IP); // Bad + endfunction endclass module t; - Cls c; + Cls c; endmodule diff --git a/test_regress/t/t_implements_noninterface_bad.v b/test_regress/t/t_implements_noninterface_bad.v index ca4753d6b..6c17c3b8f 100644 --- a/test_regress/t/t_implements_noninterface_bad.v +++ b/test_regress/t/t_implements_noninterface_bad.v @@ -17,5 +17,5 @@ class ClsBad2 extends Icls; endclass module t; - ClsBad2 c; + ClsBad2 c; endmodule diff --git a/test_regress/t/t_implements_notfound_bad.v b/test_regress/t/t_implements_notfound_bad.v index 668934c31..fd03e2661 100644 --- a/test_regress/t/t_implements_notfound_bad.v +++ b/test_regress/t/t_implements_notfound_bad.v @@ -8,5 +8,5 @@ class ClsI implements Inotfound; endclass module t; - ClsI ci; + ClsI ci; endmodule diff --git a/test_regress/t/t_implements_typed.v b/test_regress/t/t_implements_typed.v index 70bff2b88..a76e5674b 100644 --- a/test_regress/t/t_implements_typed.v +++ b/test_regress/t/t_implements_typed.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 interface class Icls; - typedef int int_t; - pure virtual function int ifunc(int_t val); + typedef int int_t; + pure virtual function int ifunc(int_t val); endclass interface class IclsExt extends Icls; - // Typedefs seen by extended, but not implements (need ::) - pure virtual function int ifuncExt(int_t v1, int_t v2); + // Typedefs seen by extended, but not implements (need ::) + pure virtual function int ifuncExt(int_t v1, int_t v2); endclass class IclsImp implements Icls; - function int ifunc(Icls::int_t val); - return val + 1; - endfunction + function int ifunc(Icls::int_t val); + return val + 1; + endfunction endclass // Bad, already have error for @@ -28,14 +28,14 @@ endclass module t; - IclsImp i1; + IclsImp i1; - initial begin - i1 = new; - if (i1.ifunc(2) != 3) $stop; + initial begin + i1 = new; + if (i1.ifunc(2) != 3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_impure_cond_empty_if.v b/test_regress/t/t_impure_cond_empty_if.v index 2569422ba..6106098ef 100644 --- a/test_regress/t/t_impure_cond_empty_if.v +++ b/test_regress/t/t_impure_cond_empty_if.v @@ -5,24 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 class uvm_component; - int x; - function void set_x(); - x = 1; - endfunction - function new(); - if(call_set_return_false()); - endfunction - function bit call_set_return_false; - set_x(); - return 0; - endfunction + int x; + function void set_x(); + x = 1; + endfunction + function new(); + if (call_set_return_false()); + endfunction + function bit call_set_return_false; + set_x(); + return 0; + endfunction endclass module t; - initial begin - automatic uvm_component a = new; - if (a.x != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic uvm_component a = new; + if (a.x != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inc_relink.v b/test_regress/t/t_inc_relink.v index 8089b1049..6776e9538 100644 --- a/test_regress/t/t_inc_relink.v +++ b/test_regress/t/t_inc_relink.v @@ -7,31 +7,31 @@ // Test if temporary vars are relinked if not used directly under FTASK. package A; // Create JUMPBLOCK; use n++ in it - task t; - automatic int n; - if ($random) return; - n = n++; - endtask + task t; + automatic int n; + if ($random) return; + n = n++; + endtask endpackage package B; // Create IF; use n++ in it - int n; - task t; - if ($random) n = n++; - endtask + int n; + task t; + if ($random) n = n++; + endtask endpackage module C; // Like above but in a module - int n = 0; + int n = 0; - initial if ($random) n = n++; + initial if ($random) n = n++; endmodule module t; // Actually use those to test relinking - C c(); + C c (); - initial begin - A::t(); - B::t(); - end + initial begin + A::t(); + B::t(); + end endmodule diff --git a/test_regress/t/t_incorrect_multi_driven.v b/test_regress/t/t_incorrect_multi_driven.v index 4efd5b0ab..c4acea012 100644 --- a/test_regress/t/t_incorrect_multi_driven.v +++ b/test_regress/t/t_incorrect_multi_driven.v @@ -4,53 +4,43 @@ // SPDX-FileCopyrightText: 2023 Adrien Le Masle // SPDX-License-Identifier: CC0-1.0 -interface test_if #(parameter int AA = 2, BB=5); +interface test_if #( + parameter int AA = 2, + BB = 5 +); - logic [AA-1 : 0] a; - logic [BB-1 : 0] b; - logic c; - logic d; + logic [AA-1 : 0] a; + logic [BB-1 : 0] b; + logic c; + logic d; - modport slave (input a, - input b, - input c, - input d); + modport slave(input a, input b, input c, input d); - modport master (output a, - output b, - output c, - output d); + modport master(output a, output b, output c, output d); endinterface : test_if -module test - (input logic [28:0] a, - output logic [28:0] b); +module test ( + input logic [28:0] a, + output logic [28:0] b +); - always_comb begin - b = a; - end + always_comb begin + b = a; + end endmodule -module multi_driven - ( - input logic [20-1 : 0] data_in, - output logic [20-1 : 0] data_out, - test_if.slave test_if_in, - test_if.master test_if_out - ); +module multi_driven ( + input logic [20-1 : 0] data_in, + output logic [20-1 : 0] data_out, + test_if.slave test_if_in, + test_if.master test_if_out +); - test test_inst - ( - .a({data_in, - test_if_in.a, - test_if_in.b, - test_if_in.c, - test_if_in.d}), - .b({data_out, - test_if_out.a, - test_if_out.b, - test_if_out.c, - test_if_out.d})); + test test_inst ( + .a({data_in, test_if_in.a, test_if_in.b, test_if_in.c, test_if_in.d}), + .b({data_out, test_if_out.a, test_if_out.b, test_if_out.c, test_if_out.d}) + ); -endmodule; +endmodule +; diff --git a/test_regress/t/t_incr_void.v b/test_regress/t/t_incr_void.v index bc58fdd41..9d66b0134 100644 --- a/test_regress/t/t_incr_void.v +++ b/test_regress/t/t_incr_void.v @@ -4,17 +4,13 @@ // SPDX-FileCopyrightText: 2023 Drew Ranck // SPDX-License-Identifier: CC0-1.0 -module t - (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc = 0; - int cyc = 0; - - always @ (posedge clk) begin : main + always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc > 100) begin @@ -32,16 +28,15 @@ module t logic [3:0] want_count_q = '0; always_ff @(posedge clk) begin : flops - count_q <= count_d; - want_count_q <= want_count_d; + count_q <= count_d; + want_count_q <= want_count_d; end always @(posedge clk) begin : simple_check if (cyc > 0) begin if (count_q !== want_count_q) begin - $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", - cyc, count_q, want_count_q); - $stop; // don't finish to fail the test. + $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", cyc, count_q, want_count_q); + $stop; // don't finish to fail the test. end end end diff --git a/test_regress/t/t_increment_bad.out b/test_regress/t/t_increment_bad.out index 08749d938..4a3194a36 100644 --- a/test_regress/t/t_increment_bad.out +++ b/test_regress/t/t_increment_bad.out @@ -1,23 +1,23 @@ -%Error-UNSUPPORTED: t/t_increment_bad.v:21:31: Unsupported: Incrementation in this context. - 21 | if (0 && test_string[pos++] != "e"); - | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_increment_bad.v:22:19: Unsupported: Incrementation in this context. - 22 | if (1 || pos-- != 1); - | ^~ -%Error-UNSUPPORTED: t/t_increment_bad.v:24:17: Unsupported: Incrementation in this context. - 24 | if (a <-> --b); - | ^~ -%Error-UNSUPPORTED: t/t_increment_bad.v:25:16: Unsupported: Incrementation in this context. - 25 | if (0 -> ++b); - | ^~ -%Error-UNSUPPORTED: t/t_increment_bad.v:27:24: Unsupported: Incrementation in this context. - 27 | pos = (a > 0) ? a++ : --b; - | ^~ -%Error-UNSUPPORTED: t/t_increment_bad.v:27:29: Unsupported: Incrementation in this context. - 27 | pos = (a > 0) ? a++ : --b; +%Error-UNSUPPORTED: t/t_increment_bad.v:19:29: Unsupported: Incrementation in this context. + 19 | if (0 && test_string[pos++] != "e"); | ^~ -%Error-UNSUPPORTED: t/t_increment_bad.v:32:37: Unsupported: Incrementation in this context. - 32 | assert property (@(posedge clk) a++ >= 0); - | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_increment_bad.v:20:17: Unsupported: Incrementation in this context. + 20 | if (1 || pos-- != 1); + | ^~ +%Error-UNSUPPORTED: t/t_increment_bad.v:22:15: Unsupported: Incrementation in this context. + 22 | if (a <-> --b); + | ^~ +%Error-UNSUPPORTED: t/t_increment_bad.v:23:14: Unsupported: Incrementation in this context. + 23 | if (0 -> ++b); + | ^~ +%Error-UNSUPPORTED: t/t_increment_bad.v:25:22: Unsupported: Incrementation in this context. + 25 | pos = (a > 0) ? a++ : --b; + | ^~ +%Error-UNSUPPORTED: t/t_increment_bad.v:25:27: Unsupported: Incrementation in this context. + 25 | pos = (a > 0) ? a++ : --b; + | ^~ +%Error-UNSUPPORTED: t/t_increment_bad.v:30:36: Unsupported: Incrementation in this context. + 30 | assert property (@(posedge clk) a++ >= 0); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_increment_bad.v b/test_regress/t/t_increment_bad.v index d0006a4a1..2087b5b18 100644 --- a/test_regress/t/t_increment_bad.v +++ b/test_regress/t/t_increment_bad.v @@ -4,30 +4,28 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int pos; - int a; - int b; - int array[2][2] = '{ '{0, 1}, '{2, 3}}; + int pos; + int a; + int b; + int array[2][2] = '{'{0, 1}, '{2, 3}}; - string test_string = "abcd"; + string test_string = "abcd"; - initial begin - if (0 && test_string[pos++] != "e"); - if (1 || pos-- != 1); + initial begin + if (0 && test_string[pos++] != "e"); + if (1 || pos-- != 1); - if (a <-> --b); - if (0 -> ++b); + if (a <-> --b); + if (0 -> ++b); - pos = (a > 0) ? a++ : --b; + pos = (a > 0) ? a++ : --b; - pos = array[0][0]++; - end + pos = array[0][0]++; + end - assert property (@(posedge clk) a++ >= 0); + assert property (@(posedge clk) a++ >= 0); endmodule diff --git a/test_regress/t/t_infinite_recursion.v b/test_regress/t/t_infinite_recursion.v index 377b5e1d9..9d8efb2c7 100644 --- a/test_regress/t/t_infinite_recursion.v +++ b/test_regress/t/t_infinite_recursion.v @@ -5,14 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class cls; - task t; t; endtask - task pre_randomize; - t; - endtask + task t; + t; + endtask + task pre_randomize; + t; + endtask endclass module t; - cls obj; - task static t; - int _ = obj.randomize() with {1 == 1;}; - endtask + cls obj; + task static t; + int _ = obj.randomize() with {1 == 1;}; + endtask endmodule diff --git a/test_regress/t/t_init_concat.v b/test_regress/t/t_init_concat.v index 9672a1c3b..31c2c35ae 100644 --- a/test_regress/t/t_init_concat.v +++ b/test_regress/t/t_init_concat.v @@ -4,84 +4,80 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [31:0] wr_data; - reg wr_en; - wire [31:0] rd_data; - wire [1:0] rd_guards; - wire [1:0] rd_guardsok; + reg [31:0] wr_data; + reg wr_en; + wire [31:0] rd_data; + wire [1:0] rd_guards; + wire [1:0] rd_guardsok; - regfile regfile (/*AUTOINST*/ - // Outputs - .rd_data (rd_data[31:0]), - .rd_guards (rd_guards[1:0]), - .rd_guardsok (rd_guardsok[1:0]), - // Inputs - .wr_data (wr_data[31:0]), - .wr_en (wr_en), - .clk (clk)); + regfile regfile ( /*AUTOINST*/ + // Outputs + .rd_data(rd_data[31:0]), + .rd_guards(rd_guards[1:0]), + .rd_guardsok(rd_guardsok[1:0]), + // Inputs + .wr_data(wr_data[31:0]), + .wr_en(wr_en), + .clk(clk) + ); - initial wr_en = 0; + initial wr_en = 0; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - if (!rd_guards[0]) $stop; - if (!rd_guardsok[0]) $stop; - wr_en <= 1'b1; - wr_data <= 32'hfeedf; - end - if (cyc==2) begin - wr_en <= 0; - end - if (cyc==3) begin - wr_en <= 0; - if (rd_data != 32'hfeedf) $stop; - if (rd_guards != 2'b11) $stop; - if (rd_guardsok != 2'b11) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + if (!rd_guards[0]) $stop; + if (!rd_guardsok[0]) $stop; + wr_en <= 1'b1; + wr_data <= 32'hfeedf; end - end + if (cyc == 2) begin + wr_en <= 0; + end + if (cyc == 3) begin + wr_en <= 0; + if (rd_data != 32'hfeedf) $stop; + if (rd_guards != 2'b11) $stop; + if (rd_guardsok != 2'b11) $stop; + end + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module regfile ( - input [31:0] wr_data, - input wr_en, - output reg [31:0] rd_data, - output [1:0] rd_guards /*verilator public*/, - output [1:0] rd_guardsok /*verilator public*/, - input clk - ); + input [31:0] wr_data, + input wr_en, + output reg [31:0] rd_data, + output [1:0] rd_guards /*verilator public*/, + output [1:0] rd_guardsok /*verilator public*/, + input clk +); - always @(posedge clk) begin - if (wr_en) - begin - rd_data <= wr_data; - end - end + always @(posedge clk) begin + if (wr_en) begin + rd_data <= wr_data; + end + end - // this initial statement will induce correct initialize behavior - // initial rd_guards= { 2'b11 }; + // this initial statement will induce correct initialize behavior + // initial rd_guards= { 2'b11 }; - assign rd_guards= { - rd_data[0], - 1'b1 - }; + assign rd_guards = {rd_data[0], 1'b1}; - assign rd_guardsok[0] = 1'b1; - assign rd_guardsok[1] = rd_data[0]; + assign rd_guardsok[0] = 1'b1; + assign rd_guardsok[1] = rd_data[0]; -endmodule // regfile +endmodule // regfile diff --git a/test_regress/t/t_initarray_nonarray.v b/test_regress/t/t_initarray_nonarray.v index 799a881c0..29ac3364c 100644 --- a/test_regress/t/t_initarray_nonarray.v +++ b/test_regress/t/t_initarray_nonarray.v @@ -7,7 +7,7 @@ // SPDX-FileCopyrightText: 2017 Jie Xu // SPDX-License-Identifier: CC0-1.0 -typedef logic [7:0] mask_t [7:0]; +typedef logic [7:0] mask_t[7:0]; // parameter logic [7:0] IMP_MASK[7:0] = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; @@ -15,9 +15,9 @@ parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8 module t; - mask_t a; - //logic [7:0] a[7:0]; + mask_t a; + //logic [7:0] a[7:0]; - assign a = IMP_MASK; + assign a = IMP_MASK; endmodule diff --git a/test_regress/t/t_initial.v b/test_regress/t/t_initial.v index a5cdf46ab..196129ea1 100644 --- a/test_regress/t/t_initial.v +++ b/test_regress/t/t_initial.v @@ -4,43 +4,42 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - reg _ranit; +module t ( + input clk +); - `include "t_initial_inc.vh" + reg _ranit; - // surefire lint_off STMINI - initial assign user_loaded_value = 1; + `include "t_initial_inc.vh" - initial _ranit = 0; + // surefire lint_off STMINI + initial assign user_loaded_value = 1; - always @ (posedge clk) begin - if (!_ranit) begin - _ranit <= 1; + initial _ranit = 0; - // Test $time - // surefire lint_off CWECBB - if ($time<20) $write("time<20\n"); - // surefire lint_on CWECBB + always @(posedge clk) begin + if (!_ranit) begin + _ranit <= 1; - // Test $write - $write ("[%0t] %m: User loaded ", $time); - $display ("%b", user_loaded_value); - if (user_loaded_value!=1) $stop; + // Test $time + // surefire lint_off CWECBB + if ($time < 20) $write("time<20\n"); + // surefire lint_on CWECBB - // Test $c + // Test $write + $write("[%0t] %m: User loaded ", $time); + $display("%b", user_loaded_value); + if (user_loaded_value != 1) $stop; + + // Test $c `ifdef VERILATOR - $c ("VL_PRINTF(\"Hi From C++\\n\");"); + $c("VL_PRINTF(\"Hi From C++\\n\");"); `endif - user_loaded_value <= 2; + user_loaded_value <= 2; - $write("*-* All Finished *-*\n"); - $finish; - end - end + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_initial_assign_sformatf.v b/test_regress/t/t_initial_assign_sformatf.v index 2a66dfc71..65a8eef67 100644 --- a/test_regress/t/t_initial_assign_sformatf.v +++ b/test_regress/t/t_initial_assign_sformatf.v @@ -4,29 +4,26 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -interface intf(); +interface intf; - function automatic string get_scope; - string the_scope = $sformatf("%m"); - return the_scope; - endfunction + function automatic string get_scope; + string the_scope = $sformatf("%m"); + return the_scope; + endfunction - initial $display(get_scope()); + initial $display(get_scope()); endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - intf the_intf(); + intf the_intf (); endmodule diff --git a/test_regress/t/t_initial_dlyass.v b/test_regress/t/t_initial_dlyass.v index d5cd6d36d..c733a3933 100644 --- a/test_regress/t/t_initial_dlyass.v +++ b/test_regress/t/t_initial_dlyass.v @@ -4,29 +4,28 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc; initial cyc = 0; - integer a; - integer b; + integer cyc; + initial cyc = 0; + integer a; + integer b; - initial begin - a <= 22; - b <= 33; - end + initial begin + a <= 22; + b <= 33; + end - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==99) begin - if (a != 22) $stop; - if (b != 33) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + if (a != 22) $stop; + if (b != 33) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index dfebc49eb..54d3da81c 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -1,11 +1,11 @@ -%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Non-blocking assignment '<=' in initial/final block +%Warning-INITIALDLY: t/t_initial_dlyass.v:17:7: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! - 18 | a <= 22; - | ^~ + 17 | a <= 22; + | ^~ ... For warning description see https://verilator.org/warn/INITIALDLY?v=latest ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. -%Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Non-blocking assignment '<=' in initial/final block +%Warning-INITIALDLY: t/t_initial_dlyass.v:18:7: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! - 19 | b <= 33; - | ^~ + 18 | b <= 33; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_initial_edge.v b/test_regress/t/t_initial_edge.v index 4c755755a..5dd694661 100644 --- a/test_regress/t/t_initial_edge.v +++ b/test_regress/t/t_initial_edge.v @@ -23,80 +23,86 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ns +`timescale 1ns / 1ns -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire res; - wire res_n; - reg rst; - reg rst_n; + wire res; + wire res_n; + reg rst; + reg rst_n; - integer count = 0; + integer count = 0; - initial_edge i_edge (.res (res), - .rst (rst)); + initial_edge i_edge ( + .res(res), + .rst(rst) + ); - initial_edge_n i_edge_n (.res_n (res_n), - .rst_n (rst_n)); + initial_edge_n i_edge_n ( + .res_n(res_n), + .rst_n(rst_n) + ); - // run for 3 cycles, with one cycle of reset. - always @(posedge clk) begin + // run for 3 cycles, with one cycle of reset. + always @(posedge clk) begin - rst <= (count == 0) ? 1 : 0; - rst_n <= (count == 0) ? 0 : 1; + rst <= (count == 0) ? 1 : 0; + rst_n <= (count == 0) ? 0 : 1; - if (count == 3) begin - if ((res == 1) && (res_n == 1)) begin - $write ("*-* All Finished *-*\n"); - $finish; - end - else begin -`ifdef TEST_VERBOSE - $write ("FAILED: res = %b, res_n = %b\n", res, res_n); -`endif - $stop; - end + if (count == 3) begin + if ((res == 1) && (res_n == 1)) begin + $write("*-* All Finished *-*\n"); + $finish; end + else begin +`ifdef TEST_VERBOSE + $write("FAILED: res = %b, res_n = %b\n", res, res_n); +`endif + $stop; + end + end - count = count + 1; + count = count + 1; - end + end endmodule -module initial_edge_n (res_n, - rst_n); - output res_n; - input rst_n; +module initial_edge_n ( + res_n, + rst_n +); + output res_n; + input rst_n; - reg res_n = 1'b0; + reg res_n = 1'b0; - always @(negedge rst_n) begin - if (rst_n == 1'b0) begin - res_n <= 1'b1; - end - end + always @(negedge rst_n) begin + if (rst_n == 1'b0) begin + res_n <= 1'b1; + end + end -endmodule // initial_edge_n +endmodule // initial_edge_n -module initial_edge (res, - rst); - output res; - input rst; +module initial_edge ( + res, + rst +); + output res; + input rst; - reg res = 1'b0; + reg res = 1'b0; - always @(posedge rst) begin - if (rst == 1'b1) begin - res <= 1'b1; - end - end + always @(posedge rst) begin + if (rst == 1'b1) begin + res <= 1'b1; + end + end -endmodule // initial_edge +endmodule // initial_edge diff --git a/test_regress/t/t_inside.v b/test_regress/t/t_inside.v index 669e8b4d2..96d55d6b8 100644 --- a/test_regress/t/t_inside.v +++ b/test_regress/t/t_inside.v @@ -4,85 +4,85 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef enum logic [1:0] - { ZERO = 2'd0, - ONE = 2'd1, - TWO = 2'd2, - THREE = 2'd3, - XXX = 2'dx - } num_t; + typedef enum logic [1:0] { + ZERO = 2'd0, + ONE = 2'd1, + TWO = 2'd2, + THREE = 2'd3, + XXX = 2'dx + } num_t; - function automatic logic is_odd; - input en; - input num_t number; - case (en) - 1'b1: begin - unique if (number inside {ONE, THREE}) - is_odd = 1'b1; - else if (number inside {ZERO, TWO}) - is_odd = 1'b0; - else - is_odd = 1'bx; - end - 1'b0: is_odd = 1'bx; - default: is_odd = 1'bx; - endcase - endfunction + function automatic logic is_odd; + input en; + input num_t number; + case (en) + 1'b1: begin + unique if (number inside {ONE, THREE}) is_odd = 1'b1; + else if (number inside {ZERO, TWO}) is_odd = 1'b0; + else is_odd = 1'bx; + end + 1'b0: is_odd = 1'bx; + default: is_odd = 1'bx; + endcase + endfunction - function automatic bit is_00_to_04 (input byte value); - return value inside { [ 8'h0 : 8'h04 ] }; - endfunction - function automatic bit is_fe_to_ff (input byte value); - return value inside { [ 8'hfe : 8'hff ] }; - endfunction + function automatic bit is_00_to_04(input byte value); + return value inside {[8'h0 : 8'h04]}; + endfunction + function automatic bit is_fe_to_ff(input byte value); + return value inside {[8'hfe : 8'hff]}; + endfunction - initial begin - `checkh ((4'd4 inside {4'd1,4'd5}), 1'b0); - `checkh ((4'd4 inside {4'd1,4'd4}), 1'b1); - // - `checkh ((4'b1011 inside {4'b1001}), 1'b0); - `checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==? - `checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==? - `checkh ((4'b1001 inside {4'b1??1}), 1'b1); + initial begin + `checkh((4'd4 inside {4'd1, 4'd5}), 1'b0); + `checkh((4'd4 inside {4'd1, 4'd4}), 1'b1); + // + `checkh((4'b1011 inside {4'b1001}), 1'b0); + `checkh((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==? + `checkh((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==? + `checkh((4'b1001 inside {4'b1??1}), 1'b1); `ifndef VERILATOR - `checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx); + `checkh((4'b1z11 inside {4'b11?1, 4'b1011}), 1'bx); `endif - // Range - `checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches - `checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); - `checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); - `checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); - `checkh ((4.0 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); - // - // Unsupported $ bound - // - // Unsupported if unpacked array, elements tranversed - //int unpackedarray [$] = '{8,9}; - //( expr inside {2, 3, unpackedarray}) // { 2,3,8,9} - // - `checkh (is_odd(1'b1, ZERO), 1'd0); - `checkh (is_odd(1'b1, ONE), 1'd1); - `checkh (is_odd(1'b1, TWO), 1'd0); - `checkh (is_odd(1'b1, THREE),1'd1); + // Range + `checkh((4'd4 inside {[4'd5 : 4'd3], [4'd10 : 4'd8]}), + 1'b0); // If left of colon < never matches + `checkh((4'd3 inside {[4'd1 : 4'd2], [4'd3 : 4'd5]}), 1'b1); + `checkh((4'd4 inside {[4'd1 : 4'd2], [4'd3 : 4'd5]}), 1'b1); + `checkh((4'd5 inside {[4'd1 : 4'd2], [4'd3 : 4'd5]}), 1'b1); + `checkh((4.0 inside {[4'd1 : 4'd2], [4'd3 : 4'd5]}), 1'b1); + // + // Unsupported $ bound + // + // Unsupported if unpacked array, elements tranversed + //int unpackedarray [$] = '{8,9}; + //( expr inside {2, 3, unpackedarray}) // { 2,3,8,9} + // + `checkh(is_odd(1'b1, ZERO), 1'd0); + `checkh(is_odd(1'b1, ONE), 1'd1); + `checkh(is_odd(1'b1, TWO), 1'd0); + `checkh(is_odd(1'b1, THREE), 1'd1); `ifndef VERILATOR - `checkh (is_odd(1'b1, XXX), 1'dx); + `checkh(is_odd(1'b1, XXX), 1'dx); `endif - // - // Should not give UNSIGNED/CMPCONST warnings - // (Verilator converts to 8'h00 >= 8'h00 which is always true) - `checkh(is_00_to_04(8'h00), 1'b1); - `checkh(is_00_to_04(8'h04), 1'b1); - `checkh(is_00_to_04(8'h05), 1'b0); - `checkh(is_fe_to_ff(8'hfd), 1'b0); - `checkh(is_fe_to_ff(8'hfe), 1'b1); - `checkh(is_fe_to_ff(8'hff), 1'b1); - // - $write("*-* All Finished *-*\n"); - $finish; - end + // + // Should not give UNSIGNED/CMPCONST warnings + // (Verilator converts to 8'h00 >= 8'h00 which is always true) + `checkh(is_00_to_04(8'h00), 1'b1); + `checkh(is_00_to_04(8'h04), 1'b1); + `checkh(is_00_to_04(8'h05), 1'b0); + `checkh(is_fe_to_ff(8'hfd), 1'b0); + `checkh(is_fe_to_ff(8'hfe), 1'b1); + `checkh(is_fe_to_ff(8'hff), 1'b1); + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inside2.v b/test_regress/t/t_inside2.v index 0dfb5935e..157e77b16 100644 --- a/test_regress/t/t_inside2.v +++ b/test_regress/t/t_inside2.v @@ -4,34 +4,29 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + typedef struct packed {logic signed [63:0] b;} a_t; - typedef struct packed { - logic signed [63:0] b; - } a_t; + a_t a_r; + a_t a_n; + logic signed [63:0] b; + logic res; - a_t a_r; - a_t a_n; - logic signed [63:0] b; - logic res; + assign b = a_r.b; - assign b = a_r.b; + always_comb begin + a_n = a_r; + res = '0; + if (b inside {1, 2}) begin + res = 1'b1; + end + end - always_comb begin - a_n = a_r; - res = '0; - if (b inside {1, 2}) begin - res = 1'b1; - end - end - - always_ff @(posedge clk) begin - a_r <= a_n; - end + always_ff @(posedge clk) begin + a_r <= a_n; + end endmodule diff --git a/test_regress/t/t_inside_assoc_unsup.out b/test_regress/t/t_inside_assoc_unsup.out index 4f0e9a0c0..c14829034 100644 --- a/test_regress/t/t_inside_assoc_unsup.out +++ b/test_regress/t/t_inside_assoc_unsup.out @@ -1,6 +1,6 @@ -%Error: t/t_inside_assoc_unsup.v:12:15: Inside operator not specified on associative arrays (IEEE 1800-2023 11.4.13) +%Error: t/t_inside_assoc_unsup.v:12:13: Inside operator not specified on associative arrays (IEEE 1800-2023 11.4.13) : ... note: In instance 't' - 12 | m = (10 inside {assoc}); - | ^~~~~~ + 12 | m = (10 inside {assoc}); + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_inside_assoc_unsup.v b/test_regress/t/t_inside_assoc_unsup.v index 3df80d6ee..378062c02 100644 --- a/test_regress/t/t_inside_assoc_unsup.v +++ b/test_regress/t/t_inside_assoc_unsup.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int assoc[int]; - bit m; + int assoc[int]; + bit m; - initial begin - m = (10 inside {assoc}); - end + initial begin + m = (10 inside {assoc}); + end endmodule diff --git a/test_regress/t/t_inside_dyn.v b/test_regress/t/t_inside_dyn.v index 7d64598ca..5171a618b 100644 --- a/test_regress/t/t_inside_dyn.v +++ b/test_regress/t/t_inside_dyn.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int q[$] = '{1, 2, 3}; - bit dyn[] = '{0, 0}; - string sq[] = '{"C", "D"}; + int q[$] = '{1, 2, 3}; + bit dyn[] = '{0, 0}; + string sq[] = '{"C", "D"}; - initial begin - if (!(1 inside {q})) $stop; - if (4 inside {q}) $stop; - if (!(4 inside {q, 4})) $stop; + initial begin + if (!(1 inside {q})) $stop; + if (4 inside {q}) $stop; + if (!(4 inside {q, 4})) $stop; - if (!(0 inside {dyn})) $stop; - if (1 inside {dyn}) $stop; - if (!("C" inside {sq})) $stop; + if (!(0 inside {dyn})) $stop; + if (1 inside {dyn}) $stop; + if (!("C" inside {sq})) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inside_queue_elem.v b/test_regress/t/t_inside_queue_elem.v index c0fcad54b..9eabc717d 100644 --- a/test_regress/t/t_inside_queue_elem.v +++ b/test_regress/t/t_inside_queue_elem.v @@ -6,14 +6,14 @@ module t; - initial begin - automatic int q[$] = {1, 2}; + initial begin + automatic int q[$] = {1, 2}; - if (!(1 inside {q[0], q[1]})) $stop; - if (3 inside {q[0], q[1]}) $stop; + if (!(1 inside {q[0], q[1]})) $stop; + if (3 inside {q[0], q[1]}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inside_unpacked.v b/test_regress/t/t_inside_unpacked.v index 9b44fa588..bde3e1c5f 100644 --- a/test_regress/t/t_inside_unpacked.v +++ b/test_regress/t/t_inside_unpacked.v @@ -4,39 +4,37 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - int array [10]; - logic l; + int array[10]; + logic l; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Setup - array[0] = 10; - array[1] = 20; - array[9] = 90; - end - else if (cyc < 99) begin - l = (10 inside {array}); - if (l != 1) $stop; - l = (20 inside {array}); - if (l != 1) $stop; - l = (90 inside {array}); - if (l != 1) $stop; - l = (99 inside {array}); - if (l != 0) $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + array[0] = 10; + array[1] = 20; + array[9] = 90; + end + else if (cyc < 99) begin + l = (10 inside {array}); + if (l != 1) $stop; + l = (20 inside {array}); + if (l != 1) $stop; + l = (90 inside {array}); + if (l != 1) $stop; + l = (99 inside {array}); + if (l != 0) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_inside_unpacked_param.out b/test_regress/t/t_inside_unpacked_param.out index f497fe7f7..3d5f4c474 100644 --- a/test_regress/t/t_inside_unpacked_param.out +++ b/test_regress/t/t_inside_unpacked_param.out @@ -1,10 +1,10 @@ -%Error: t/t_inside_unpacked_param.v:13:35: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. +%Error: t/t_inside_unpacked_param.v:13:34: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. : ... note: In instance 't' - 13 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; - | ^~~~~~ + 13 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inside_unpacked_param.v:14:37: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. +%Error: t/t_inside_unpacked_param.v:14:36: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. : ... note: In instance 't' - 14 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; - | ^~~~~~ + 14 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inside_unpacked_param.v b/test_regress/t/t_inside_unpacked_param.v index 2c159825c..134f3dcb7 100644 --- a/test_regress/t/t_inside_unpacked_param.v +++ b/test_regress/t/t_inside_unpacked_param.v @@ -6,17 +6,17 @@ module t; - localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; + localparam int CHECKLIST_P[2:0] = '{0, 1, 2}; - localparam HIT_LP = 1; - localparam MISS_LP = 4; - localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; - localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; + localparam HIT_LP = 1; + localparam MISS_LP = 4; + localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; + localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; - initial begin - if (HIT_INSIDE != 1) $stop; - if (MISS_INSIDE != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (HIT_INSIDE != 1) $stop; + if (MISS_INSIDE != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inside_wild.v b/test_regress/t/t_inside_wild.v index 49ebd4cc3..5b6b15895 100644 --- a/test_regress/t/t_inside_wild.v +++ b/test_regress/t/t_inside_wild.v @@ -4,81 +4,81 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [4:0] in = crc[4:0]; + wire [4:0] in = crc[4:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out), - // Inputs - .clk (clk), - .in (in[4:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out(out), + // Inputs + .clk(clk), + .in(in[4:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {63'h0, out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in +); - //bug718 + //bug718 - input clk; + input clk; - input logic [4:0] in; + input logic [4:0] in; - output logic out; + output logic out; - always @(posedge clk) begin - out <= in inside {5'b1_1?1?}; - end + always @(posedge clk) begin + out <= in inside {5'b1_1?1?}; + end endmodule diff --git a/test_regress/t/t_inst_2star_bad.out b/test_regress/t/t_inst_2star_bad.out index 906c976ee..f3b570af8 100644 --- a/test_regress/t/t_inst_2star_bad.out +++ b/test_regress/t/t_inst_2star_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_inst_2star_bad.v:12:17: Duplicate .* in an instance (IEEE 1800-2023 23.3.2) - 12 | sub sub (.*, .*); - | ^~ +%Error: t/t_inst_2star_bad.v:12:16: Duplicate .* in an instance (IEEE 1800-2023 23.3.2) + 12 | sub sub (.*, .*); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_2star_bad.v:14:13: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) - 14 | sub sub (foo, .*); - | ^~~ -%Error: t/t_inst_2star_bad.v:16:13: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) - 16 | sub sub (foo, .bar); - | ^~~ +%Error: t/t_inst_2star_bad.v:14:12: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) + 14 | sub sub (foo, .*); + | ^~~ +%Error: t/t_inst_2star_bad.v:16:12: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) + 16 | sub sub (foo, .bar); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_2star_bad.v b/test_regress/t/t_inst_2star_bad.v index 60ab2694c..59b8a0311 100644 --- a/test_regress/t/t_inst_2star_bad.v +++ b/test_regress/t/t_inst_2star_bad.v @@ -6,14 +6,14 @@ module t; - wire foo; - wire bar; + wire foo; + wire bar; - sub sub (.*, .*); + sub sub (.*, .*); - sub sub (foo, .*); + sub sub (foo, .*); - sub sub (foo, .bar); + sub sub (foo, .bar); endmodule diff --git a/test_regress/t/t_inst_array.v b/test_regress/t/t_inst_array.v index f4f363b25..cd14f9bc8 100644 --- a/test_regress/t/t_inst_array.v +++ b/test_regress/t/t_inst_array.v @@ -4,57 +4,64 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; - parameter ONE = 1; + integer cyc; + initial cyc = 1; + parameter ONE = 1; - wire [17:10] bitout; - reg [7:0] allbits; - reg [15:0] onebit; + wire [17:10] bitout; + reg [7:0] allbits; + reg [15:0] onebit; - sub sub [7:0] (allbits, onebit, bitout); + sub sub[7:0] ( + allbits, + onebit, + bitout + ); - integer x; + integer x; - always @ (posedge clk) begin - //$write("%x\n", bitout); - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - allbits <= 8'hac; - onebit <= 16'hc01a; - end - if (cyc==2) begin - if (bitout !== 8'h07) $stop; - allbits <= 8'hca; - onebit <= 16'h1f01; - end - if (cyc==3) begin - if (bitout !== 8'h41) $stop; - if (sub[0].bitout !== 1'b1) $stop; - if (sub[1].bitout !== 1'b0) $stop; -`ifndef verilator // Hacky array subscripting - if (sub[ONE].bitout !== 1'b0) $stop; -`endif - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + //$write("%x\n", bitout); + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + allbits <= 8'hac; + onebit <= 16'hc01a; end - end + if (cyc == 2) begin + if (bitout !== 8'h07) $stop; + allbits <= 8'hca; + onebit <= 16'h1f01; + end + if (cyc == 3) begin + if (bitout !== 8'h41) $stop; + if (sub[0].bitout !== 1'b1) $stop; + if (sub[1].bitout !== 1'b0) $stop; +`ifndef verilator // Hacky array subscripting + if (sub[ONE].bitout !== 1'b0) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule `ifdef USE_INLINE - `define INLINE_MODULE /*verilator inline_module*/ +`define INLINE_MODULE /*verilator inline_module*/ `else - `define INLINE_MODULE /*verilator public_module*/ +`define INLINE_MODULE /*verilator public_module*/ `endif -module sub (input [7:0] allbits, input [1:0] onebit, output bitout); - `INLINE_MODULE - assign bitout = (^ onebit) ^ (^ allbits); +module sub ( + input [7:0] allbits, + input [1:0] onebit, + output bitout +); + `INLINE_MODULE + assign bitout = (^onebit) ^ (^allbits); endmodule diff --git a/test_regress/t/t_inst_array_bad.out b/test_regress/t/t_inst_array_bad.out index 7a6718338..88a34bc0f 100644 --- a/test_regress/t/t_inst_array_bad.out +++ b/test_regress/t/t_inst_array_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_inst_array_bad.v:14:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3) +%Error: t/t_inst_array_bad.v:14:27: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3) : ... note: In instance 't' - 14 | sub sub [7:0] (allbits, onebitbad, bitout); - | ^~~~~~~~~ + 14 | sub sub [7:0] (allbits, onebitbad, bitout); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v index 86d3b223d..b581aecf9 100644 --- a/test_regress/t/t_inst_array_bad.v +++ b/test_regress/t/t_inst_array_bad.v @@ -6,20 +6,20 @@ module t; - wire [7:0] bitout; - reg [7:0] allbits; - reg [7:0] onebit; - reg [8:0] onebitbad; // Wrongly sized + wire [7:0] bitout; + reg [7:0] allbits; + reg [7:0] onebit; + reg [8:0] onebitbad; // Wrongly sized - sub sub [7:0] (allbits, onebitbad, bitout); + sub sub [7:0] (allbits, onebitbad, bitout); - // This is ok. - wire [9:8] b; - wire [1:0] c; - sub sub2 [9:8] (allbits,b,c); + // This is ok. + wire [9:8] b; + wire [1:0] c; + sub sub2 [9:8] (allbits,b,c); endmodule module sub (input [7:0] allbits, input onebit, output bitout); - assign bitout = onebit ^ (^ allbits); + assign bitout = onebit ^ (^ allbits); endmodule diff --git a/test_regress/t/t_inst_array_connect.v b/test_regress/t/t_inst_array_connect.v index 644eca973..ce962be48 100644 --- a/test_regress/t/t_inst_array_connect.v +++ b/test_regress/t/t_inst_array_connect.v @@ -4,83 +4,76 @@ // SPDX-FileCopyrightText: 2019 Julien Margetts // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); - input clk; +module t ( + input clk +); - localparam N = 4; + localparam N = 4; - wire [7:0] cval1[0:N-1]; - wire [7:0] cval2[N-1:0]; - wire [7:0] cval3[0:N-1]; - wire [7:0] cval4[N-1:0]; + wire [7:0] cval1[0:N-1]; + wire [7:0] cval2[N-1:0]; + wire [7:0] cval3[0:N-1]; + wire [7:0] cval4[N-1:0]; - wire [3:0] inc; + wire [3:0] inc; - assign inc = 4'b0001; + assign inc = 4'b0001; - // verilator lint_off ASCRANGE + // verilator lint_off ASCRANGE - COUNTER UCOUNTER1[N-1:0] - ( - .clk (clk), - .inc (inc), - .o (cval1) // Twisted - ); + COUNTER UCOUNTER1[N-1:0] ( + .clk(clk), + .inc(inc), + .o(cval1) // Twisted + ); - COUNTER UCOUNTER2[N-1:0] - ( - .clk (clk), - .inc (inc), - .o (cval2) // Matches - ); + COUNTER UCOUNTER2[N-1:0] ( + .clk(clk), + .inc(inc), + .o(cval2) // Matches + ); - COUNTER UCOUNTER3[0:N-1] - ( - .clk (clk), - .inc (inc), - .o (cval3) // Matches - ); + COUNTER UCOUNTER3[0:N-1] ( + .clk(clk), + .inc(inc), + .o(cval3) // Matches + ); - COUNTER UCOUNTER4[0:N-1] - ( - .clk (clk), - .inc (inc), - .o (cval4) // Twisted - ); + COUNTER UCOUNTER4[0:N-1] ( + .clk(clk), + .inc(inc), + .o(cval4) // Twisted + ); - always @(posedge clk) begin - if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0])) - $stop; + always @(posedge clk) begin + if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0])) $stop; - if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] + + if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] + cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0) - $stop; + $stop; `ifdef TEST_VERBOSE - $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]); - $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]); - $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]); - $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]); + $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]); + $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]); + $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]); + $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]); `endif - if (cval1[0] + cval1[3] > 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cval1[0] + cval1[3] > 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module COUNTER - ( - input clk, - input inc, - output reg [7:0] o - ); +module COUNTER ( + input clk, + input inc, + output reg [7:0] o +); - initial o = 8'd0; // No reset input + initial o = 8'd0; // No reset input - always @(posedge clk) if (inc) o <= o + 1; + always @(posedge clk) if (inc) o <= o + 1; endmodule diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v index e8b3d8a3b..3de78717a 100644 --- a/test_regress/t/t_inst_array_partial.v +++ b/test_regress/t/t_inst_array_partial.v @@ -4,93 +4,100 @@ // SPDX-FileCopyrightText: 2011 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - // verilator lint_off MULTIDRIVEN - wire [19:10] bitout; - // verilator lint_on MULTIDRIVEN - wire [29:24] short_bitout; - wire [7:0] allbits; - wire [15:0] twobits; + // verilator lint_off MULTIDRIVEN + wire [19:10] bitout; + // verilator lint_on MULTIDRIVEN + wire [29:24] short_bitout; + wire [7:0] allbits; + wire [15:0] twobits; - sub - i_sub1 [7:4] (.allbits (allbits), - .twobits (twobits[15:8]), - .bitout (bitout[17:14])), - i_sub2 [3:0] (.allbits (allbits), - .twobits (twobits[7:0]), - .bitout (bitout[13:10])); + sub + i_sub1[7:4] ( + .allbits(allbits), + .twobits(twobits[15:8]), + .bitout(bitout[17:14]) + ), + i_sub2[3:0] ( + .allbits(allbits), + .twobits(twobits[7:0]), + .bitout(bitout[13:10]) + ); - sub - i_sub3 [7:4] (.allbits (allbits), - .twobits (twobits[15:8]), - .bitout (bitout[17:14])); + sub i_sub3[7:4] ( + .allbits(allbits), + .twobits(twobits[15:8]), + .bitout(bitout[17:14]) + ); - sub - i_sub4 [7:4] (.allbits (allbits), - .twobits (twobits[15:8]), - .bitout (short_bitout[27:24])); + sub i_sub4[7:4] ( + .allbits(allbits), + .twobits(twobits[15:8]), + .bitout(short_bitout[27:24]) + ); - sub - i_sub5 [7:0] (.allbits (allbits), - .twobits (twobits), - .bitout (bitout[17:10])); + sub i_sub5[7:0] ( + .allbits(allbits), + .twobits(twobits), + .bitout(bitout[17:10]) + ); - sub - i_sub6 [7:4] (.allbits (allbits), - .twobits (twobits[15:8]), - .bitout ({bitout[18+:2],short_bitout[28+:2]})); + sub i_sub6[7:4] ( + .allbits(allbits), + .twobits(twobits[15:8]), + .bitout({bitout[18+:2], short_bitout[28+:2]}) + ); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Signals under test - assign allbits = crc[7:0]; - assign twobits = crc[15:0]; - wire [63:0] result = {48'h0, short_bitout, bitout}; + // Signals under test + assign allbits = crc[7:0]; + assign twobits = crc[15:0]; + wire [63:0] result = {48'h0, short_bitout, bitout}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'ha1da9ff8082a4ff6 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'ha1da9ff8082a4ff6 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end -endmodule // t +endmodule // t -module sub - ( input wire [7:0] allbits, - input wire [1:0] twobits, - output wire bitout); +module sub ( + input wire [7:0] allbits, + input wire [1:0] twobits, + output wire bitout +); - assign bitout = (^ twobits) ^ (^ allbits); + assign bitout = (^twobits) ^ (^allbits); -endmodule // sub +endmodule // sub diff --git a/test_regress/t/t_inst_array_struct.v b/test_regress/t/t_inst_array_struct.v index ca3713a9d..11333eaaf 100644 --- a/test_regress/t/t_inst_array_struct.v +++ b/test_regress/t/t_inst_array_struct.v @@ -4,45 +4,50 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - typedef struct packed { - bit one; - bit two; - } ps_t; + typedef struct packed { + bit one; + bit two; + } ps_t; - ps_t in0 [2]; - ps_t out0 [2]; + ps_t in0[2]; + ps_t out0[2]; - bit [1:0] in1 [2] = {{1'b1, 1'b0}, {1'b0, 1'b1}}; - bit [1:0] out1 [2]; + bit [1:0] in1[2] = {{1'b1, 1'b0}, {1'b0, 1'b1}}; + bit [1:0] out1[2]; - Sub sub0 [2] (in0, out0); - Sub sub1 [2] (in1, out1); + Sub sub0[2] ( + in0, + out0 + ); + Sub sub1[2] ( + in1, + out1 + ); - int cyc; + int cyc; - always @ (posedge clk) begin - cyc <= cyc + 1; - in0 = {{1'b1, 1'b0}, {1'b0, 1'b1}}; - if (cyc == 9) begin - $display("%p %p", in0, out0); - $display("%p %p", in1, out1); - if (out0[0] != 2'h2 || out0[1] != 2'h1) $stop; - if (out1[0] != 2'h2 || out1[1] != 2'h1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + in0 = {{1'b1, 1'b0}, {1'b0, 1'b1}}; + if (cyc == 9) begin + $display("%p %p", in0, out0); + $display("%p %p", in1, out1); + if (out0[0] != 2'h2 || out0[1] != 2'h1) $stop; + if (out1[0] != 2'h2 || out1[1] != 2'h1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Sub - (input bit [1:0] in, - output bit [1:0] out); - assign out = in; +module Sub ( + input bit [1:0] in, + output bit [1:0] out +); + assign out = in; endmodule diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v index 7fa14463f..7d8747254 100644 --- a/test_regress/t/t_inst_ccall.v +++ b/test_regress/t/t_inst_ccall.v @@ -4,51 +4,56 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [31:0] long; - reg [63:0] quad; - wire [31:0] longout; - wire [63:0] quadout; - wire [7:0] narrow = long[7:0]; - sub sub (/*AUTOINST*/ - // Outputs - .longout (longout[31:0]), - .quadout (quadout[63:0]), - // Inputs - .narrow (narrow[7:0]), - .quad (quad[63:0])); + reg [31:0] long; + reg [63:0] quad; + wire [31:0] longout; + wire [63:0] quadout; + wire [7:0] narrow = long[7:0]; + sub sub ( /*AUTOINST*/ + // Outputs + .longout(longout[31:0]), + .quadout(quadout[63:0]), + // Inputs + .narrow(narrow[7:0]), + .quad(quad[63:0]) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - long <= 32'h12345678; - quad <= 64'h12345678_abcdef12; - end - if (cyc==2) begin - if (longout !== 32'h79) $stop; - if (quadout !== 64'h12345678_abcdef13) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + long <= 32'h12345678; + quad <= 64'h12345678_abcdef12; end - end + if (cyc == 2) begin + if (longout !== 32'h79) $stop; + if (quadout !== 64'h12345678_abcdef13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout); - // verilator public_module +module sub ( + input [7:0] narrow, + input [63:0] quad, + output [31:0] longout, + output [63:0] quadout +); + // verilator public_module `ifdef verilator - assign longout = $c32("(", narrow, "+1)"); - assign quadout = $c64("(", quad, "+1)"); + assign longout = $c32("(", narrow, "+1)"); + assign quadout = $c64("(", quad, "+1)"); `else - assign longout = narrow + 8'd1; - assign quadout = quad + 64'd1; + assign longout = narrow + 8'd1; + assign quadout = quad + 64'd1; `endif endmodule diff --git a/test_regress/t/t_inst_comma.v b/test_regress/t/t_inst_comma.v index 62d9bede4..6dafa1c76 100644 --- a/test_regress/t/t_inst_comma.v +++ b/test_regress/t/t_inst_comma.v @@ -4,64 +4,69 @@ // SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; - parameter ONE = 1; + integer cyc; + initial cyc = 1; + parameter ONE = 1; - wire [17:10] bitout; - reg [7:0] allbits; - reg [15:0] onebit; + wire [17:10] bitout; + reg [7:0] allbits; + reg [15:0] onebit; - sub #(1) - sub0 (allbits, onebit[1:0], bitout[10]), - sub1 (allbits, onebit[3:2], bitout[11]), - sub2 (allbits, onebit[5:4], bitout[12]), - sub3 (allbits, onebit[7:6], bitout[13]), - sub4 (allbits, onebit[9:8], bitout[14]), - sub5 (allbits, onebit[11:10], bitout[15]), - sub6 (allbits, onebit[13:12], bitout[16]), - sub7 (allbits, onebit[15:14], bitout[17]); + // verilog_format: off + sub #(1) + sub0 (allbits, onebit[1:0], bitout[10]), + sub1 (allbits, onebit[3:2], bitout[11]), + sub2 (allbits, onebit[5:4], bitout[12]), + sub3 (allbits, onebit[7:6], bitout[13]), + sub4 (allbits, onebit[9:8], bitout[14]), + sub5 (allbits, onebit[11:10], bitout[15]), + sub6 (allbits, onebit[13:12], bitout[16]), + sub7 (allbits, onebit[15:14], bitout[17]); + // verilog_format: on - integer x; + integer x; - always @ (posedge clk) begin - //$write("%x\n", bitout); - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - allbits <= 8'hac; - onebit <= 16'hc01a; - end - if (cyc==2) begin - if (bitout !== 8'h07) $stop; - allbits <= 8'hca; - onebit <= 16'h1f01; - end - if (cyc==3) begin - if (bitout !== 8'h41) $stop; - if (sub0.bitout !== 1'b1) $stop; - if (sub1.bitout !== 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + //$write("%x\n", bitout); + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + allbits <= 8'hac; + onebit <= 16'hc01a; end - end + if (cyc == 2) begin + if (bitout !== 8'h07) $stop; + allbits <= 8'hca; + onebit <= 16'h1f01; + end + if (cyc == 3) begin + if (bitout !== 8'h41) $stop; + if (sub0.bitout !== 1'b1) $stop; + if (sub1.bitout !== 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule `ifdef USE_INLINE - `define INLINE_MODULE /*verilator inline_module*/ +`define INLINE_MODULE /*verilator inline_module*/ `else - `define INLINE_MODULE /*verilator public_module*/ +`define INLINE_MODULE /*verilator public_module*/ `endif -module sub (input [7:0] allbits, input [1:0] onebit, output bitout); - `INLINE_MODULE - parameter integer P = 0; - initial if (P != 1) $stop; - assign bitout = (^ onebit) ^ (^ allbits); +module sub ( + input [7:0] allbits, + input [1:0] onebit, + output bitout +); + `INLINE_MODULE + parameter integer P = 0; + initial if (P != 1) $stop; + assign bitout = (^onebit) ^ (^allbits); endmodule diff --git a/test_regress/t/t_inst_darray.v b/test_regress/t/t_inst_darray.v index a9ff0dc52..08053b370 100644 --- a/test_regress/t/t_inst_darray.v +++ b/test_regress/t/t_inst_darray.v @@ -7,80 +7,77 @@ typedef logic [63:0] uid_t; typedef logic [31:0] value_t; -interface the_intf #(parameter M = 5); - logic valid; - uid_t uid; - value_t [M-1:0] values; +interface the_intf #( + parameter M = 5 +); + logic valid; + uid_t uid; + value_t [M-1:0] values; - modport i( - output valid, - output uid, - output values - ); - modport t( - input valid, - input uid, - input values - ); + modport i(output valid, output uid, output values); + modport t(input valid, input uid, input values); endinterface module Contemplator #( - parameter IMPL = 0, - parameter M = 5, - parameter N = 1 ) - ( + parameter IMPL = 0, + parameter M = 5, + parameter N = 1 +) ( input logic clk, - the_intf.i out [N-1:0] - ); + the_intf.i out[N-1:0] +); - the_intf #(.M(M)) inp[N-1:0] (); + the_intf #(.M(M)) inp[N-1:0] (); - DeepThought #( - .N ( N )) - ultimateAnswerer( - .src ( inp ), - .dst ( out )); + DeepThought #( + .N(N) + ) ultimateAnswerer ( + .src(inp), + .dst(out) + ); endmodule module DeepThought #( - parameter N = 1 ) - ( + parameter N = 1 +) ( the_intf.t src[N-1:0], the_intf.i dst[N-1:0] - ); +); endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - localparam M = 5; - localparam N = 1; + localparam M = 5; + localparam N = 1; - the_intf #(.M(M)) out0 [N-1:0] (); - the_intf #(.M(M)) out1 [N-1:0] (); + the_intf #(.M(M)) out0[N-1:0] (); + the_intf #(.M(M)) out1[N-1:0] (); - Contemplator #( - .IMPL ( 0 ), - .M ( M ), - .N ( N )) - contemplatorOfTheZerothKind( - .clk ( clk ), - .out ( out0 )); + Contemplator #( + .IMPL(0), + .M(M), + .N(N) + ) contemplatorOfTheZerothKind ( + .clk(clk), + .out(out0) + ); - Contemplator #( - .IMPL ( 1 ), - .M ( M ), - .N ( N )) - contemplatorOfTheFirstKind( - .clk ( clk ), - .out ( out1 )); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + Contemplator #( + .IMPL(1), + .M(M), + .N(N) + ) contemplatorOfTheFirstKind ( + .clk(clk), + .out(out1) + ); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inst_dearray_slice.v b/test_regress/t/t_inst_dearray_slice.v index eea55deb1..06e62fc7d 100644 --- a/test_regress/t/t_inst_dearray_slice.v +++ b/test_regress/t/t_inst_dearray_slice.v @@ -4,87 +4,78 @@ // SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - wire [31:0] in = 0; - wire [31:0] out; + wire [31:0] in = 0; + wire [31:0] out; - Test test( - .out(out[31:0]), - .clk(clk), - .in (in[31:0]) - ); + Test test ( + .out(out[31:0]), + .clk(clk), + .in(in[31:0]) + ); - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule interface Intf (); endinterface -module Select - #( +module Select #( parameter int NUM_MASTER = 1 - ) - ( +) ( Intf Upstream, Intf Downstream[NUM_MASTER] - ); +); endmodule -module Crossbar - #( - parameter int NUM_MASTER = 1, - parameter int NUM_SLAVE = 1 - ) - ( - Intf Masters[NUM_MASTER] +module Crossbar #( + parameter int NUM_MASTER = 1, + parameter int NUM_SLAVE = 1 +) ( + Intf Masters[NUM_MASTER] +); + + Intf selectOut[(NUM_MASTER * (NUM_SLAVE+1))-1 : 0] (); + + + genvar i; + + for (i = 0; i < NUM_MASTER; i = i + 1) begin + Select #( + .NUM_MASTER(NUM_SLAVE + 1) + ) select_inst ( + .Upstream(Masters[i]), + // Following line triggered the dearrayAll segfault + .Downstream(selectOut[(i+1)*(NUM_SLAVE+1)-1 : i*(NUM_SLAVE+1)]) + ); + end + +endmodule + +module Test ( + input clk, + input [31:0] in, + output reg [31:0] out +); + + always @(posedge clk) begin + out <= in; + end + + Intf MST[2] (); //MST must have >1 array size to trigger dearrayAll segfault + + Crossbar #( + .NUM_MASTER(2), + .NUM_SLAVE(1) + ) xbar_inst ( + .Masters(MST) ); - Intf selectOut[(NUM_MASTER * (NUM_SLAVE+1))-1 : 0](); - - - genvar i; - - for (i = 0; i < NUM_MASTER; i = i + 1) begin - Select #( - .NUM_MASTER(NUM_SLAVE+1) - ) - select_inst ( - .Upstream(Masters[i]), - // Following line triggered the dearrayAll segfault - .Downstream(selectOut[(i+1)*(NUM_SLAVE+1) - 1 : i*(NUM_SLAVE+1)]) - ); - end - -endmodule - -module Test - ( - input clk, - input [31:0] in, - output reg [31:0] out - ); - - always @(posedge clk) begin - out <= in; - end - - Intf MST[2](); //MST must have >1 array size to trigger dearrayAll segfault - - Crossbar #( - .NUM_MASTER(2), - .NUM_SLAVE(1) - ) - xbar_inst ( - .Masters(MST) - ); - endmodule diff --git a/test_regress/t/t_inst_dff.v b/test_regress/t/t_inst_dff.v index 31b11af42..87cabf8ee 100644 --- a/test_regress/t/t_inst_dff.v +++ b/test_regress/t/t_inst_dff.v @@ -4,129 +4,145 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - localparam WIDTH = 31; + localparam WIDTH = 31; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [WIDTH-1:0] b; // From test of Test.v - wire [WIDTH-1:0] c; // From test of Test.v - // End of automatics - reg rst_l; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [WIDTH-1:0] b; // From test of Test.v + wire [WIDTH-1:0] c; // From test of Test.v + // End of automatics + reg rst_l; - Test #(.WIDTH(WIDTH)) - test (/*AUTOINST*/ - // Outputs - .b (b[WIDTH-1:0]), - .c (c[WIDTH-1:0]), - // Inputs - .clk (clk), - .rst_l (rst_l), - .in (in[WIDTH-1:0])); + Test #( + .WIDTH(WIDTH) + ) test ( /*AUTOINST*/ + // Outputs + .b(b[WIDTH-1:0]), + .c(c[WIDTH-1:0]), + // Inputs + .clk(clk), + .rst_l(rst_l), + .in(in[WIDTH-1:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {1'h0, c, 1'b0, b}; + // Aggregate outputs into a single result vector + wire [63:0] result = {1'h0, c, 1'b0, b}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - rst_l <= ~1'b1; - end - else if (cyc<10) begin - sum <= 64'h0; - rst_l <= ~1'b1; - // Hold reset while summing - end - else if (cyc<20) begin - rst_l <= ~1'b0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hbcfcebdb75ec9d32 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst_l <= ~1'b1; + end + else if (cyc < 10) begin + sum <= 64'h0; + rst_l <= ~1'b1; + // Hold reset while summing + end + else if (cyc < 20) begin + rst_l <= ~1'b0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hbcfcebdb75ec9d32 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - b, c, - // Inputs - clk, rst_l, in - ); +module Test ( /*AUTOARG*/ + // Outputs + b, + c, + // Inputs + clk, + rst_l, + in +); - parameter WIDTH = 5; + parameter WIDTH = 5; - input clk; - input rst_l; + input clk; + input rst_l; - input [WIDTH-1:0] in; - output wire [WIDTH-1:0] b; - output wire [WIDTH-1:0] c; + input [WIDTH-1:0] in; + output wire [WIDTH-1:0] b; + output wire [WIDTH-1:0] c; - dff # ( .WIDTH (WIDTH), - .RESET ('0), // Although this is a single bit, the parameter must be the specified type - .RESET_WIDTH (1) ) - sub1 - ( .clk(clk), .rst_l(rst_l), .q(b), .d(in) ); + dff #( + .WIDTH(WIDTH), + .RESET('0), // Although this is a single bit, the parameter must be the specified type + .RESET_WIDTH(1) + ) sub1 ( + .clk(clk), + .rst_l(rst_l), + .q(b), + .d(in) + ); - dff # ( .WIDTH (WIDTH), - .RESET ({ 1'b1, {(WIDTH-1){1'b0}} }), - .RESET_WIDTH (WIDTH)) - sub2 - ( .clk(clk), .rst_l(rst_l), .q(c), .d(in) ); + dff #( + .WIDTH(WIDTH), + .RESET({1'b1, {(WIDTH - 1) {1'b0}}}), + .RESET_WIDTH(WIDTH) + ) sub2 ( + .clk(clk), + .rst_l(rst_l), + .q(c), + .d(in) + ); endmodule -module dff (/*AUTOARG*/ - // Outputs - q, - // Inputs - clk, rst_l, d - ); +module dff ( /*AUTOARG*/ + // Outputs + q, + // Inputs + clk, + rst_l, + d +); - parameter WIDTH = 1; - parameter RESET = {WIDTH{1'b0}}; - parameter RESET_WIDTH = WIDTH; + parameter WIDTH = 1; + parameter RESET = {WIDTH{1'b0}}; + parameter RESET_WIDTH = WIDTH; - input clk; - input rst_l; - input [WIDTH-1:0] d; - output reg [WIDTH-1:0] q; + input clk; + input rst_l; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; - always_ff @(posedge clk or negedge rst_l) begin - if ($bits(RESET) != RESET_WIDTH) $stop; - // verilator lint_off WIDTH - if (~rst_l) q <= RESET; - // verilator lint_on WIDTH - else q <= d; - end + always_ff @(posedge clk or negedge rst_l) begin + if ($bits(RESET) != RESET_WIDTH) $stop; + // verilator lint_off WIDTH + if (~rst_l) q <= RESET; + // verilator lint_on WIDTH + else + q <= d; + end endmodule diff --git a/test_regress/t/t_inst_dtree.v b/test_regress/t/t_inst_dtree.v index 09b6eec73..721383a8d 100644 --- a/test_regress/t/t_inst_dtree.v +++ b/test_regress/t/t_inst_dtree.v @@ -4,69 +4,83 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); -`ifdef INLINE_A //verilator inline_module +`ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif - bmod bsub3 (.clk, .n(3)); - bmod bsub2 (.clk, .n(2)); - bmod bsub1 (.clk, .n(1)); - bmod bsub0 (.clk, .n(0)); + // verilog_format: off + bmod bsub3 (.clk, .n(3)); + bmod bsub2 (.clk, .n(2)); + bmod bsub1 (.clk, .n(1)); + bmod bsub0 (.clk, .n(0)); + // verilog_format: on endmodule -module bmod - (input clk, - input [31:0] n); +module bmod ( + input clk, + input [31:0] n +); -`ifdef INLINE_B //verilator inline_module +`ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif - cmod csub (.clk, .n); + cmod csub ( + .clk, + .n + ); endmodule -module cmod - (input clk, input [31:0] n); +module cmod ( + input clk, + input [31:0] n +); -`ifdef INLINE_C //verilator inline_module +`ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif - reg [31:0] clocal; - always @ (posedge clk) clocal <= n; + reg [31:0] clocal; + always @(posedge clk) clocal <= n; - dmod dsub (.clk, .n); + dmod dsub ( + .clk, + .n + ); endmodule -module dmod (input clk, input [31:0] n); +module dmod ( + input clk, + input [31:0] n +); -`ifdef INLINE_D //verilator inline_module +`ifdef INLINE_D //verilator inline_module `else //verilator no_inline_module `endif - reg [31:0] dlocal; - always @ (posedge clk) dlocal <= n; + reg [31:0] dlocal; + always @(posedge clk) dlocal <= n; - int cyc; - always @(posedge clk) begin - cyc <= cyc+1; - end - always @(posedge clk) begin - if (cyc>10) begin -`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif - if (csub.clocal !== n) $stop; - if (dlocal !== n) $stop; - end - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cyc; + always @(posedge clk) begin + cyc <= cyc + 1; + end + always @(posedge clk) begin + if (cyc > 10) begin +`ifdef TEST_VERBOSE + $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); +`endif + if (csub.clocal !== n) $stop; + if (dlocal !== n) $stop; + end + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_inst_first.v b/test_regress/t/t_inst_first.v index 668e52ab7..e21078fdd 100644 --- a/test_regress/t/t_inst_first.v +++ b/test_regress/t/t_inst_first.v @@ -4,126 +4,130 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, fastclk - ); +module t ( + input clk, + input fastclk +); - input clk; - input fastclk; + genvar unused; - genvar unused; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire o_com; // From b of t_inst_first_b.v + wire o_seq_d1r; // From b of t_inst_first_b.v + // End of automatics - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire o_com; // From b of t_inst_first_b.v - wire o_seq_d1r; // From b of t_inst_first_b.v - // End of automatics + integer _mode; // initial _mode=0 + reg na, nb, nc, nd, ne; + wire ma, mb, mc, md, me; + wire da, db, dc, dd, de; + reg [7:0] wa, wb, wc, wd, we; + wire [7:0] qa, qb, qc, qd, qe; - integer _mode; // initial _mode=0 - reg na,nb,nc,nd,ne; - wire ma,mb,mc,md,me; - wire da,db,dc,dd,de; - reg [7:0] wa,wb,wc,wd,we; - wire [7:0] qa,qb,qc,qd,qe; + wire [5:0] ra; + wire [4:0] rb; + wire [29:0] rc; + wire [63:0] rd; + reg [5:0] sa; + reg [4:0] sb; + reg [29:0] sc; + reg [63:0] sd; - wire [5:0] ra; - wire [4:0] rb; - wire [29:0] rc; - wire [63:0] rd; - reg [5:0] sa; - reg [4:0] sb; - reg [29:0] sc; - reg [63:0] sd; + reg _guard1; + initial _guard1 = 0; + wire [104:0] r_wide = {ra, rb, rc, rd}; + reg _guard2; + initial _guard2 = 0; + wire [98:0] r_wide0 = {rb, rc, rd}; + reg _guard3; + initial _guard3 = 0; + wire [93:0] r_wide1 = {rc, rd}; + reg _guard4; + initial _guard4 = 0; + wire [63:0] r_wide2 = {rd}; + reg _guard5; + initial _guard5 = 0; + wire [168:0] r_wide3 = {ra, rb, rc, rd, rd}; + reg [127:0] _guard6; + initial _guard6 = 0; - reg _guard1; initial _guard1=0; - wire [104:0] r_wide = {ra,rb,rc,rd}; - reg _guard2; initial _guard2=0; - wire [98:0] r_wide0 = {rb,rc,rd}; - reg _guard3; initial _guard3=0; - wire [93:0] r_wide1 = {rc,rd}; - reg _guard4; initial _guard4=0; - wire [63:0] r_wide2 = {rd}; - reg _guard5; initial _guard5=0; - wire [168:0] r_wide3 = {ra,rb,rc,rd,rd}; - reg [127:0] _guard6; initial _guard6=0; + t_inst_first_a a ( + .clk(clk), + // Outputs + .o_w5({ma, mb, mc, md, me}), + .o_w5_d1r({da, db, dc, dd, de}), + .o_w40({qa, qb, qc, qd, qe}), + .o_w104({ra, rb, rc, rd}), + // Inputs + .i_w5({na, nb, nc, nd, ne}), + .i_w40({wa, wb, wc, wd, we}), + .i_w104({sa, sb, sc, sd}) + ); - t_inst_first_a a ( - .clk (clk), - // Outputs - .o_w5 ({ma,mb,mc,md,me}), - .o_w5_d1r ({da,db,dc,dd,de}), - .o_w40 ({qa,qb,qc,qd,qe}), - .o_w104 ({ra,rb,rc,rd}), - // Inputs - .i_w5 ({na,nb,nc,nd,ne}), - .i_w40 ({wa,wb,wc,wd,we}), - .i_w104 ({sa,sb,sc,sd}) - ); + reg i_seq; + reg i_com; + wire [15:14] o2_comhigh; - reg i_seq; - reg i_com; - wire [15:14] o2_comhigh; + t_inst_first_b b ( + .o2_com(o2_comhigh), + .i2_com({i_com, ~i_com}), + .wide_for_trace(128'h1234_5678_aaaa_bbbb_cccc_dddd), + .wide_for_trace_2(_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), + /*AUTOINST*/ + // Outputs + .o_seq_d1r(o_seq_d1r), + .o_com(o_com), + // Inputs + .clk(clk), + .i_seq(i_seq), + .i_com(i_com) + ); - t_inst_first_b b ( - .o2_com (o2_comhigh), - .i2_com ({i_com,~i_com}), - .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), - .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), - /*AUTOINST*/ - // Outputs - .o_seq_d1r (o_seq_d1r), - .o_com (o_com), - // Inputs - .clk (clk), - .i_seq (i_seq), - .i_com (i_com)); + // surefire lint_off STMINI + initial _mode = 0; - // surefire lint_off STMINI - initial _mode = 0; + always @(posedge fastclk) begin + if (_mode == 1) begin + if (o_com !== ~i_com) $stop; + if (o2_comhigh !== {~i_com, i_com}) $stop; + end + end - always @ (posedge fastclk) begin - if (_mode==1) begin - if (o_com !== ~i_com) $stop; - if (o2_comhigh !== {~i_com,i_com}) $stop; - end - end + always @(posedge clk) begin + //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, + // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); + $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); + if (_mode == 0) begin + $write("[%0t] t_inst: Running\n", $time); + _mode <= 1; + {na, nb, nc, nd, ne} <= 5'b10110; + {wa, wb, wc, wd, we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; + {sa, sb, sc, sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; + // + i_seq <= 1'b1; + i_com <= 1'b1; + end + else if (_mode == 1) begin + _mode <= 2; + if ({ma, mb, mc, md, me} !== 5'b10110) $stop; + if ({qa, qb, qc, qd, qe} !== {8'ha, 8'hb, 8'hc, 8'hd, 8'he}) $stop; + if ({sa, sb, sc, sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; + end + else if (_mode == 2) begin + _mode <= 3; + if ({da, db, dc, dd, de} !== 5'b10110) $stop; + if (o_seq_d1r !== ~i_seq) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + if (|{_guard1, _guard2, _guard3, _guard4, _guard5, _guard6}) begin + $write("Guard error %x %x %x %x %x\n", _guard1, _guard2, _guard3, _guard4, _guard5); + $stop; + end + end - always @ (posedge clk) begin - //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, - // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); - $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); - if (_mode==0) begin - $write("[%0t] t_inst: Running\n", $time); - _mode<=1; - {na,nb,nc,nd,ne} <= 5'b10110; - {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; - {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; - // - i_seq <= 1'b1; - i_com <= 1'b1; - end - else if (_mode==1) begin - _mode<=2; - if ({ma,mb,mc,md,me} !== 5'b10110) $stop; - if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; - if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; - end - else if (_mode==2) begin - _mode<=3; - if ({da,db,dc,dd,de} !== 5'b10110) $stop; - if (o_seq_d1r !== ~i_seq) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; - end - if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin - $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); - $stop; - end - end - - // surefire lint_off UDDSDN - wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide}; + // surefire lint_off UDDSDN + wire _unused_ok = |{1'b1, r_wide0, r_wide1, r_wide2, r_wide3, r_wide}; endmodule diff --git a/test_regress/t/t_inst_first_a.v b/test_regress/t/t_inst_first_a.v index 61ccda166..8d90bfe70 100644 --- a/test_regress/t/t_inst_first_a.v +++ b/test_regress/t/t_inst_first_a.v @@ -4,34 +4,34 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_inst_first_a (/*AUTOARG*/ - // Outputs - o_w5, o_w5_d1r, o_w40, o_w104, - // Inputs - clk, i_w5, i_w40, i_w104 - ); +module t_inst_first_a ( /*AUTOARG*/ + // Outputs + o_w5, o_w5_d1r, o_w40, o_w104, + // Inputs + clk, i_w5, i_w40, i_w104 + ); - input clk; + input clk; - input [4:0] i_w5; - output [4:0] o_w5; - output [4:0] o_w5_d1r; - input [39:0] i_w40; - output [39:0] o_w40; - input [104:0] i_w104; - output [104:0] o_w104; + input [4:0] i_w5; + output [4:0] o_w5; + output [4:0] o_w5_d1r; + input [39:0] i_w40; + output [39:0] o_w40; + input [104:0] i_w104; + output [104:0] o_w104; - wire [4:0] o_w5 = i_w5; - wire [39:0] o_w40 = i_w40; - wire [104:0] o_w104 = i_w104; + wire [4:0] o_w5 = i_w5; + wire [39:0] o_w40 = i_w40; + wire [104:0] o_w104 = i_w104; - /*AUTOREG*/ - // Beginning of automatic regs (for this module's undeclared outputs) - reg [4:0] o_w5_d1r; - // End of automatics + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [4:0] o_w5_d1r; + // End of automatics - always @ (posedge clk) begin - o_w5_d1r <= i_w5; - end + always @(posedge clk) begin + o_w5_d1r <= i_w5; + end endmodule diff --git a/test_regress/t/t_inst_first_b.v b/test_regress/t/t_inst_first_b.v index eaf5be6f1..2f873e365 100644 --- a/test_regress/t/t_inst_first_b.v +++ b/test_regress/t/t_inst_first_b.v @@ -4,35 +4,33 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t_inst_first_b (/*AUTOARG*/ - // Outputs - o_seq_d1r, o_com, o2_com, - // Inputs - clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2 - ); - // verilator inline_module +module t_inst_first_b ( /*AUTOARG*/ + // Outputs + o_seq_d1r, o_com, o2_com, + // Inputs + clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2 + ); + // verilator inline_module - input clk; + input clk; - input i_seq; - output o_seq_d1r; - input i_com; - output o_com; - input [1:0] i2_com; - output [1:0] o2_com; - input [127:0] wide_for_trace; - input [127:0] wide_for_trace_2; + input i_seq; + output o_seq_d1r; + input i_com; + output o_com; + input [1:0] i2_com; + output [1:0] o2_com; + input [127:0] wide_for_trace; + input [127:0] wide_for_trace_2; - /*AUTOREG*/ - // Beginning of automatic regs (for this module's undeclared outputs) - // End of automatics + /*AUTOREG*/ - reg o_seq_d1r; - always @ (posedge clk) begin - o_seq_d1r <= ~i_seq; - end + reg o_seq_d1r; + always @(posedge clk) begin + o_seq_d1r <= ~i_seq; + end - wire [1:0] o2_com = ~i2_com; - wire o_com = ~i_com; + wire [1:0] o2_com = ~i2_com; + wire o_com = ~i_com; endmodule diff --git a/test_regress/t/t_inst_implicit.v b/test_regress/t/t_inst_implicit.v index 9357b9953..0e81f2b4b 100644 --- a/test_regress/t/t_inst_implicit.v +++ b/test_regress/t/t_inst_implicit.v @@ -4,48 +4,55 @@ // SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire [31:0] o; - wire [31:0] oe; + wire [31:0] o; + wire [31:0] oe; - Test test (/*AUTOINST*/ - // Outputs - .o (o[31:0]), - .oe (oe[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .o(o[31:0]), + .oe(oe[31:0]) + ); - // Test loop - always @ (posedge clk) begin - if (o !== 32'h00000001) $stop; - if (oe !== 32'h00000001) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + if (o !== 32'h00000001) $stop; + if (oe !== 32'h00000001) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module subimp(o,oe); - output [31:0] o; - assign o = 32'h12345679; - output [31:0] oe; - assign oe = 32'hab345679; +module subimp ( + o, + oe +); + output [31:0] o; + assign o = 32'h12345679; + output [31:0] oe; + assign oe = 32'hab345679; endmodule -module Test(o,oe); - output [31:0] o; - output [31:0] oe; - wire [31:0] xe; - assign xe[31:1] = 0; - // verilator lint_off IMPLICIT - // verilator lint_off WIDTH - subimp subimp(x, // x is implicit and one bit - xe[0]); // xe explicit one bit - assign o = x; - assign oe = xe; - // verilator lint_on WIDTH - // verilator lint_on IMPLICIT +module Test ( + o, + oe +); + output [31:0] o; + output [31:0] oe; + wire [31:0] xe; + assign xe[31:1] = 0; + // verilator lint_off IMPLICIT + // verilator lint_off WIDTH + subimp subimp ( + x, // x is implicit and one bit + xe[0] + ); // xe explicit one bit + assign o = x; + assign oe = xe; + // verilator lint_on WIDTH + // verilator lint_on IMPLICIT endmodule diff --git a/test_regress/t/t_inst_misarray2_bad.out b/test_regress/t/t_inst_misarray2_bad.out index ebcf3c57b..986d655db 100644 --- a/test_regress/t/t_inst_misarray2_bad.out +++ b/test_regress/t/t_inst_misarray2_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6) - : ... note: In instance 't' - 10 | .i_data(fft_oQ[6:0]) +%Error: t/t_inst_misarray2_bad.v:9:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6) + : ... note: In instance 't' + 9 | round round (.i_data(fft_oQ[6:0])); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_inst_misarray2_bad.v b/test_regress/t/t_inst_misarray2_bad.v index a7c608085..078330693 100644 --- a/test_regress/t/t_inst_misarray2_bad.v +++ b/test_regress/t/t_inst_misarray2_bad.v @@ -5,13 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire signed [16:0] fft_oQ [6:0]; - round round( - .i_data(fft_oQ[6:0]) - ); + wire signed [16:0] fft_oQ[6:0]; + round round (.i_data(fft_oQ[6:0])); endmodule -module round( - input wire signed [16:0] i_data // Misdeclared, not a vector - ); - wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}}; +module round ( + input wire signed [16:0] i_data // Misdeclared, not a vector +); + wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}}; endmodule diff --git a/test_regress/t/t_inst_misarray_bad.out b/test_regress/t/t_inst_misarray_bad.out index a4278e7d5..f3c2b76e4 100644 --- a/test_regress/t/t_inst_misarray_bad.out +++ b/test_regress/t/t_inst_misarray_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2023 7.6) - : ... note: In instance 't' - 17 | .foo(foo)); - | ^~~ +%Error: t/t_inst_misarray_bad.v:19:8: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2023 7.6) + : ... note: In instance 't' + 19 | .foo(foo) + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_inst_misarray_bad.v b/test_regress/t/t_inst_misarray_bad.v index 83a5f3696..f8de9eef5 100644 --- a/test_regress/t/t_inst_misarray_bad.v +++ b/test_regress/t/t_inst_misarray_bad.v @@ -4,38 +4,46 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic foo; initial foo = 0; + logic foo; + initial foo = 0; -// dut #(.W(4)) udut(.*); - dut #(.W(4)) udut(.clk(clk), - .foo(foo)); // Assigning logic to logic array + // dut #(.W(4)) udut(.*); + dut #( + .W(4) + ) udut ( + .clk(clk), + .foo(foo) + ); // Assigning logic to logic array endmodule -module dut - #(parameter W = 1) - (input logic clk, - input logic foo[W-1:0]); +module dut #( + parameter W = 1 +) ( + input logic clk, + input logic foo[W-1:0] +); - genvar i; - generate - for (i = 0; i < W; i++) begin - suba ua(.clk(clk), .foo(foo[i])); - end - endgenerate + genvar i; + generate + for (i = 0; i < W; i++) begin + suba ua ( + .clk(clk), + .foo(foo[i]) + ); + end + endgenerate endmodule -module suba - (input logic clk, - input logic foo); +module suba ( + input logic clk, + input logic foo +); - always @(posedge clk) - $display("foo=%b", foo); + always @(posedge clk) $display("foo=%b", foo); endmodule diff --git a/test_regress/t/t_inst_mism.v b/test_regress/t/t_inst_mism.v index b6dadb322..4b99ab606 100644 --- a/test_regress/t/t_inst_mism.v +++ b/test_regress/t/t_inst_mism.v @@ -6,37 +6,46 @@ //bug595 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic [6-1:0] foo; initial foo = 20; + logic [6-1:0] foo; + initial foo = 20; - dut #(.W(6)) udut(.clk(clk), - .foo(foo-16)); + dut #( + .W(6) + ) udut ( + .clk(clk), + .foo(foo - 16) + ); endmodule -module dut - #(parameter W = 1) - (input logic clk, - input logic [W-1:0] foo); +module dut #( + parameter W = 1 +) ( + input logic clk, + input logic [W-1:0] foo +); - genvar i; - generate - for (i = 0; i < W; i++) begin - suba ua(.clk(clk), .foo(foo[i])); - end - endgenerate + genvar i; + generate + for (i = 0; i < W; i++) begin + suba ua ( + .clk(clk), + .foo(foo[i]) + ); + end + endgenerate endmodule -module suba - (input logic clk, - input logic foo); +module suba ( + input logic clk, + input logic foo +); - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inst_missing.v b/test_regress/t/t_inst_missing.v index 690094f73..a18b6ea38 100644 --- a/test_regress/t/t_inst_missing.v +++ b/test_regress/t/t_inst_missing.v @@ -5,18 +5,28 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire ok = 1'b0; - // verilator lint_off UNDRIVEN - wire nc; - // verilator lint_on UNDRIVEN + wire ok = 1'b0; + // verilator lint_off UNDRIVEN + wire nc; + // verilator lint_on UNDRIVEN - // verilator lint_off PINNOCONNECT - // verilator lint_off PINCONNECTEMPTY - sub sub (ok, , nc); - // verilator lint_on PINCONNECTEMPTY - // verilator lint_on PINNOCONNECT + // verilator lint_off PINNOCONNECT + // verilator lint_off PINCONNECTEMPTY + sub sub ( + ok + ,, + nc + ); + // verilator lint_on PINCONNECTEMPTY + // verilator lint_on PINNOCONNECT endmodule -module sub (input ok, input none, input nc); - initial if (ok && none && nc) begin end // No unused warning +module sub ( + input ok, + input none, + input nc +); + initial + if (ok && none && nc) begin + end // No unused warning endmodule diff --git a/test_regress/t/t_inst_missing_bad.out b/test_regress/t/t_inst_missing_bad.out index 8407aaff4..c4db98814 100644 --- a/test_regress/t/t_inst_missing_bad.out +++ b/test_regress/t/t_inst_missing_bad.out @@ -1,14 +1,14 @@ -%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:13:17: Instance pin is not connected: '__pinNumber2' - 13 | sub sub (ok, , nc); - | ^ +%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:15:8: Instance pin is not connected: '__pinNumber2' + 15 | ,, + | ^ ... For warning description see https://verilator.org/warn/PINNOCONNECT?v=latest ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. -%Warning-PINMISSING: t/t_inst_missing_bad.v:13:8: Instance has missing pin: 'missing' - 13 | sub sub (ok, , nc); - | ^~~ - t/t_inst_missing_bad.v:16:51: ... Location of port declaration - 16 | module sub (input ok, input none, input nc, input missing); - | ^~~~~~~ +%Warning-PINMISSING: t/t_inst_missing_bad.v:13:7: Instance has missing pin: 'missing' + 13 | sub sub ( + | ^~~ + t/t_inst_missing_bad.v:24:11: ... Location of port declaration + 24 | input missing + | ^~~~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_inst_missing_bad.v b/test_regress/t/t_inst_missing_bad.v index c41d7acc7..26e8254fd 100644 --- a/test_regress/t/t_inst_missing_bad.v +++ b/test_regress/t/t_inst_missing_bad.v @@ -5,14 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - wire ok = 1'b0; - // verilator lint_off UNDRIVEN - wire nc; - // verilator lint_on UNDRIVEN + wire ok = 1'b0; + // verilator lint_off UNDRIVEN + wire nc; + // verilator lint_on UNDRIVEN - sub sub (ok, , nc); + sub sub ( + ok + ,, + nc + ); endmodule -module sub (input ok, input none, input nc, input missing); - initial if (ok && none && nc && missing) begin end // No unused warning +module sub ( + input ok, + input none, + input nc, + input missing +); + initial + if (ok && none && nc && missing) begin + end // No unused warning endmodule diff --git a/test_regress/t/t_inst_missing_dot_bad.out b/test_regress/t/t_inst_missing_dot_bad.out index f71c190a1..3a18145f8 100644 --- a/test_regress/t/t_inst_missing_dot_bad.out +++ b/test_regress/t/t_inst_missing_dot_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_inst_missing_dot_bad.v:9:22: Dotted reference to instance that refers to missing module/interface: 'missing' - 9 | $display("a=", missing.a); - | ^~~~~~~ +%Error: t/t_inst_missing_dot_bad.v:9:20: Dotted reference to instance that refers to missing module/interface: 'missing' + 9 | $display("a=", missing.a); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_missing_dot_bad.v:9:30: Can't find definition of 'a' in dotted variable/method: 'missing.a' - 9 | $display("a=", missing.a); - | ^ +%Error: t/t_inst_missing_dot_bad.v:9:28: Can't find definition of 'a' in dotted variable/method: 'missing.a' + 9 | $display("a=", missing.a); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_inst_missing_dot_bad.v b/test_regress/t/t_inst_missing_dot_bad.v index e6c026735..b08dba583 100644 --- a/test_regress/t/t_inst_missing_dot_bad.v +++ b/test_regress/t/t_inst_missing_dot_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - $display("a=", missing.a); - end - missing missing(); // Intentionally missing + initial begin + $display("a=", missing.a); + end + missing missing (); // Intentionally missing endmodule diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v index 290bbc7ff..d50380d55 100644 --- a/test_regress/t/t_inst_mnpipe.v +++ b/test_regress/t/t_inst_mnpipe.v @@ -4,69 +4,84 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - reg [7:0] crc; - reg [2:0] sum; - wire [2:0] in = crc[2:0]; - wire [2:0] out; + reg [7:0] crc; + reg [2:0] sum; + wire [2:0] in = crc[2:0]; + wire [2:0] out; - MxN_pipeline pipe (in, out, clk); + MxN_pipeline pipe ( + in, + out, + clk + ); - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum); - cyc <= cyc + 1; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==0) begin - // Setup - crc <= 8'hed; - sum <= 3'h0; - end - else if (cyc>10 && cyc<90) begin - sum <= {sum[1:0],sum[2]} ^ out; - end - else if (cyc==99) begin - if (crc !== 8'b01110000) $stop; - if (sum !== 3'h3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}}; + if (cyc == 0) begin + // Setup + crc <= 8'hed; + sum <= 3'h0; + end + else if (cyc > 10 && cyc < 90) begin + sum <= {sum[1:0], sum[2]} ^ out; + end + else if (cyc == 99) begin + if (crc !== 8'b01110000) $stop; + if (sum !== 3'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module dffn (q,d,clk); - parameter BITS = 1; +module dffn ( + q, + d, + clk +); + parameter BITS = 1; - input [BITS-1:0] d; - output reg [BITS-1:0] q; - input clk; + input [BITS-1:0] d; + output reg [BITS-1:0] q; + input clk; - always @ (posedge clk) begin - q <= d; - end + always @(posedge clk) begin + q <= d; + end endmodule -module MxN_pipeline (in, out, clk); - parameter M=3, N=4; +module MxN_pipeline ( + in, + out, + clk +); + parameter M = 3, N = 4; - input [M-1:0] in; - output [M-1:0] out; - input clk; + input [M-1:0] in; + output [M-1:0] out; + input clk; - // Unsupported: Per-bit array instantiations with output connections to non-wires. - //wire [M*(N-1):1] t; - //dffn #(M) p[N:1] ({out,t},{t,in},clk); + // Unsupported: Per-bit array instantiations with output connections to non-wires. + //wire [M*(N-1):1] t; + //dffn #(M) p[N:1] ({out,t},{t,in},clk); - wire [M*(N-1):1] w; - wire [M*N:1] q; - dffn #(M) p[N:1] (q,{w,in},clk); - assign {out,w} = q; + wire [M*(N-1):1] w; + wire [M*N:1] q; + dffn #(M) p[N:1] ( + q, + {w, in}, + clk + ); + assign {out, w} = q; endmodule diff --git a/test_regress/t/t_inst_name_long.v b/test_regress/t/t_inst_name_long.v index 5d1595cc5..50e5a47ba 100644 --- a/test_regress/t/t_inst_name_long.v +++ b/test_regress/t/t_inst_name_long.v @@ -7,40 +7,41 @@ // verilator lint_off PINMISSING // verilator lint_off WIDTHEXPAND +// verilog_format: off module t; - // Original issue - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - // Change sizes - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/Xxxxxxxxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); - sub #(.PARAM("FALSE")) - \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( - ); + // Original issue + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + // Change sizes + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/Xxxxxxxxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); + sub #(.PARAM("FALSE")) + \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( + ); endmodule module sub #(parameter PARAM = "TRUE") - (input [5:0] ACC_FIR); - always @(ACC_FIR) $display("WARNING: instance %m input is %d", PARAM); + (input [5:0] ACC_FIR); + always @(ACC_FIR) $display("WARNING: instance %m input is %d", PARAM); endmodule diff --git a/test_regress/t/t_inst_noname_bad.out b/test_regress/t/t_inst_noname_bad.out index 42e19be54..c200ae72e 100644 --- a/test_regress/t/t_inst_noname_bad.out +++ b/test_regress/t/t_inst_noname_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_inst_noname_bad.v:8:5: Instance of module must be named - 8 | m (); - | ^ +%Error: t/t_inst_noname_bad.v:8:3: Instance of module must be named + 8 | m(); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_noname_bad.v:9:5: Instance of module must be named - 9 | m (); - | ^ +%Error: t/t_inst_noname_bad.v:9:3: Instance of module must be named + 9 | m(); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_inst_noname_bad.v b/test_regress/t/t_inst_noname_bad.v index 58a88b137..608e3e9c2 100644 --- a/test_regress/t/t_inst_noname_bad.v +++ b/test_regress/t/t_inst_noname_bad.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t; - m (); - m (); + m(); + m(); endmodule module m; diff --git a/test_regress/t/t_inst_notunsized.v b/test_regress/t/t_inst_notunsized.v index 781f63914..f5c198940 100644 --- a/test_regress/t/t_inst_notunsized.v +++ b/test_regress/t/t_inst_notunsized.v @@ -4,108 +4,111 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [71:0] muxed; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [71:0] muxed; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .muxed (muxed[71:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test ( /*AUTOINST*/ + // Outputs + .muxed(muxed[71:0]), + // Inputs + .clk(clk), + .in(in[31:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {muxed[63:0]}; + // Aggregate outputs into a single result vector + wire [63:0] result = {muxed[63:0]}; - wire [5:0] width_check = cyc[5:0] + 1; + wire [5:0] width_check = cyc[5:0] + 1; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h20050a66e7b253d1 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h20050a66e7b253d1 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - muxed, - // Inputs - clk, in - ); - input clk; - input [31:0] in; - output [71:0] muxed; +module Test ( /*AUTOARG*/ + // Outputs + muxed, + // Inputs + clk, + in +); + input clk; + input [31:0] in; + output [71:0] muxed; - wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; - wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; + wire [71:0] a = {in[7:0], ~in[31:0], in[31:0]}; + wire [71:0] b = {~in[7:0], in[31:0], ~in[31:0]}; - /*AUTOWIRE*/ - Muxer muxer ( - .sa (0), - .sb (in[0]), - /*AUTOINST*/ - // Outputs - .muxed (muxed[71:0]), - // Inputs - .a (a[71:0]), - .b (b[71:0])); + /*AUTOWIRE*/ + Muxer muxer ( + .sa(0), + .sb(in[0]), + /*AUTOINST*/ + // Outputs + .muxed(muxed[71:0]), + // Inputs + .a(a[71:0]), + .b(b[71:0]) + ); endmodule -module Muxer (/*AUTOARG*/ - // Outputs - muxed, - // Inputs - sa, sb, a, b - ); - input sa; - input sb; +module Muxer ( /*AUTOARG*/ + // Outputs + muxed, + // Inputs + sa, + sb, + a, + b +); + input sa; + input sb; - output wire [71:0] muxed; - input [71:0] a; - input [71:0] b; + output wire [71:0] muxed; + input [71:0] a; + input [71:0] b; - // Constification wasn't sizing with inlining and gave - // unsized error on below - // v - assign muxed = (({72{sa}} & a) - | ({72{sb}} & b)); + // Constification wasn't sizing with inlining and gave + // unsized error on below + // v + assign muxed = (({72{sa}} & a) | ({72{sb}} & b)); endmodule diff --git a/test_regress/t/t_inst_overwide.v b/test_regress/t/t_inst_overwide.v index accae8d68..176a34966 100644 --- a/test_regress/t/t_inst_overwide.v +++ b/test_regress/t/t_inst_overwide.v @@ -4,48 +4,48 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - outc_w30, outd_w73, - // Inputs - clk, ina_w1, inb_w61 - ); +module t ( /*AUTOARG*/ + // Outputs + outc_w30, outd_w73, + // Inputs + clk, ina_w1, inb_w61 + ); - input clk; + input clk; - input ina_w1; - input [60:0] inb_w61; - output [29:0] outc_w30; - output [72:0] outd_w73; + input ina_w1; + input [60:0] inb_w61; + output [29:0] outc_w30; + output [72:0] outd_w73; - sub sub ( - // Outputs - .outy_w92 (outc_w30), // .large => (small) - .outz_w22 (outd_w73), // .small => (large) - // Inputs - .clk (clk), - .inw_w31 (ina_w1), // .large <= (small) - .inx_w11 (inb_w61) // .small <= (large) - ); + sub sub ( + // Outputs + .outy_w92(outc_w30), // .large => (small) + .outz_w22(outd_w73), // .small => (large) + // Inputs + .clk(clk), + .inw_w31(ina_w1), // .large <= (small) + .inx_w11(inb_w61) // .small <= (large) + ); endmodule -module sub (/*AUTOARG*/ - // Outputs - outy_w92, outz_w22, - // Inputs - clk, inw_w31, inx_w11 - ); +module sub ( /*AUTOARG*/ + // Outputs + outy_w92, outz_w22, + // Inputs + clk, inw_w31, inx_w11 + ); - input clk; - input [30:0] inw_w31; - input [10:0] inx_w11; - output reg [91:0] outy_w92 /*verilator public*/; - output reg [21:0] outz_w22 /*verilator public*/; + input clk; + input [30:0] inw_w31; + input [10:0] inx_w11; + output reg [91:0] outy_w92 /*verilator public*/; + output reg [21:0] outz_w22 /*verilator public*/; - always @(posedge clk) begin - outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; - outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; - end + always @(posedge clk) begin + outy_w92 <= {inw_w31[29:0], inw_w31[29:0], inw_w31[29:0], 2'b00}; + outz_w22 <= {inx_w11[10:0], inx_w11[10:0]}; + end -endmodule // regfile +endmodule // regfile diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index 29b06fd15..d55ca4fa6 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -1,21 +1,21 @@ -%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. - : ... note: In instance 't' - 23 | .outy_w92 (outc_w30), - | ^~~~~~~~ +%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:8: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. + : ... note: In instance 't' + 23 | .outy_w92(outc_w30), + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. - : ... note: In instance 't' - 24 | .outz_w22 (outd_w73), - | ^~~~~~~~ +%Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:8: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. + : ... note: In instance 't' + 24 | .outz_w22(outd_w73), + | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. - : ... note: In instance 't' - 27 | .inw_w31 (ina_w1), - | ^~~~~~~ -%Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. +%Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:8: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. : ... note: In instance 't' - 28 | .inx_w11 (inb_w61) - | ^~~~~~~ + 27 | .inw_w31(ina_w1), + | ^~~~~~~ +%Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:8: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. + : ... note: In instance 't' + 28 | .inx_w11(inb_w61) + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_param_comma_bad.out b/test_regress/t/t_inst_param_comma_bad.out index d34092240..190b66138 100644 --- a/test_regress/t/t_inst_param_comma_bad.out +++ b/test_regress/t/t_inst_param_comma_bad.out @@ -1,20 +1,20 @@ -%Error: t/t_inst_param_comma_bad.v:35:15: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 35 | M #(.P(13),) m1( - | ^ +%Error: t/t_inst_param_comma_bad.v:35:14: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 35 | M #(.P(13),) m1( + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_param_comma_bad.v:40:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 40 | M #(14,) m2 ( - | ^ -%Error: t/t_inst_param_comma_bad.v:45:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 45 | M #(14,) m3 ( - | ^ -%Error: t/t_inst_param_comma_bad.v:50:15: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 50 | N #(.P(13),) n1( - | ^ -%Error: t/t_inst_param_comma_bad.v:55:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 55 | N #(14,) n2 ( - | ^ -%Error: t/t_inst_param_comma_bad.v:60:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type - 60 | N #(14,) n3 ( - | ^ +%Error: t/t_inst_param_comma_bad.v:40:10: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 40 | M #(14,) m2 ( + | ^ +%Error: t/t_inst_param_comma_bad.v:45:10: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 45 | M #(14,) m3 ( + | ^ +%Error: t/t_inst_param_comma_bad.v:50:14: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 50 | N #(.P(13),) n1( + | ^ +%Error: t/t_inst_param_comma_bad.v:55:10: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 55 | N #(14,) n2 ( + | ^ +%Error: t/t_inst_param_comma_bad.v:60:10: syntax error, unexpected ')', expecting IDENTIFIER-for-type + 60 | N #(14,) n3 ( + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_inst_param_comma_bad.v b/test_regress/t/t_inst_param_comma_bad.v index 3adb791d7..5207fc628 100644 --- a/test_regress/t/t_inst_param_comma_bad.v +++ b/test_regress/t/t_inst_param_comma_bad.v @@ -5,61 +5,61 @@ // SPDX-License-Identifier: CC0-1.0 module M #( - parameter int P = 12, - parameter int Q = 13 - ) ( - input wire i, - output wire o - ); - assign o = i; + parameter int P = 12, + parameter int Q = 13 + ) ( + input wire i, + output wire o + ); + assign o = i; endmodule module N #( - parameter int P = 12 - ) ( - input wire i, - output wire o - ); - assign o = i; + parameter int P = 12 + ) ( + input wire i, + output wire o + ); + assign o = i; endmodule module t; wire i1, o1, i2, o2, i3, o3, i4, o4, i5, o5, i6, o6; - // All of these have superfluous commas after the first parameter. - // All of the N instances produced a PINNOTFOUND error, however as reported in issue #4979, - // none of the M instances do when they should. The copmma after the first parameter is not - // allowed in verilog. + // All of these have superfluous commas after the first parameter. + // All of the N instances produced a PINNOTFOUND error, however as reported in issue #4979, + // none of the M instances do when they should. The copmma after the first parameter is not + // allowed in verilog. - M #(.P(13),) m1( - .i(i1), - .o(o1) + M #(.P(13),) m1( + .i(i1), + .o(o1) + ); + + M #(14,) m2 ( + .i(i2), + .o(o2) ); - M #(14,) m2 ( - .i(i2), - .o(o2) - ); - - M #(14,) m3 ( - .i(i3), - .o(o3) - ); - - N #(.P(13),) n1( - .i(i4), - .o(o4) + M #(14,) m3 ( + .i(i3), + .o(o3) ); - N #(14,) n2 ( - .i(i5), - .o(o5) - ); + N #(.P(13),) n1( + .i(i4), + .o(o4) + ); - N #(14,) n3 ( - .i(i6), - .o(o6) - ); + N #(14,) n2 ( + .i(i5), + .o(o5) + ); + + N #(14,) n3 ( + .i(i6), + .o(o6) + ); endmodule diff --git a/test_regress/t/t_inst_param_override_bad.out b/test_regress/t/t_inst_param_override_bad.out index e5516191a..0ff6e0608 100644 --- a/test_regress/t/t_inst_param_override_bad.out +++ b/test_regress/t/t_inst_param_override_bad.out @@ -1,20 +1,20 @@ -%Error: t/t_inst_param_override_bad.v:33:23: Instance attempts to override 'PACKED_DATA_WIDTH' as a parameter, but it is a local parameter - 33 | axi_stream_if # (.PACKED_DATA_WIDTH(10)) axis1(clk); - | ^~~~~~~~~~~~~~~~~ +%Error: t/t_inst_param_override_bad.v:33:20: Instance attempts to override 'PACKED_DATA_WIDTH' as a parameter, but it is a local parameter + 33 | axi_stream_if #(.PACKED_DATA_WIDTH(10)) axis1 (clk); + | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_param_override_bad.v:35:23: Instance attempts to override 'mytask' as a parameter, but it is a task - 35 | axi_stream_if # (.mytask(10)) axis2(clk); - | ^~~~~~ -%Error: t/t_inst_param_override_bad.v:37:23: Instance attempts to override 'my_genvar' as a parameter, but it is a variable - 37 | axi_stream_if # (.my_genvar(10)) axis3(clk); - | ^~~~~~~~~ -%Error: t/t_inst_param_override_bad.v:39:23: Instance attempts to override 'clk' as a parameter, but it is a port - 39 | axi_stream_if # (.clk(10)) axis4(clk); - | ^~~ -%Error: t/t_inst_param_override_bad.v:41:23: Instance attempts to override 'tvalid' as a parameter, but it is a variable - 41 | axi_stream_if # (.tvalid(10)) axis5(clk); - | ^~~~~~ -%Error: t/t_inst_param_override_bad.v:43:23: Instance attempts to override 'i_sub' as a parameter, but it is an instance - 43 | axi_stream_if # (.i_sub(10)) axis6(clk); - | ^~~~~ +%Error: t/t_inst_param_override_bad.v:35:20: Instance attempts to override 'mytask' as a parameter, but it is a task + 35 | axi_stream_if #(.mytask(10)) axis2 (clk); + | ^~~~~~ +%Error: t/t_inst_param_override_bad.v:37:20: Instance attempts to override 'my_genvar' as a parameter, but it is a variable + 37 | axi_stream_if #(.my_genvar(10)) axis3 (clk); + | ^~~~~~~~~ +%Error: t/t_inst_param_override_bad.v:39:20: Instance attempts to override 'clk' as a parameter, but it is a port + 39 | axi_stream_if #(.clk(10)) axis4 (clk); + | ^~~ +%Error: t/t_inst_param_override_bad.v:41:20: Instance attempts to override 'tvalid' as a parameter, but it is a variable + 41 | axi_stream_if #(.tvalid(10)) axis5 (clk); + | ^~~~~~ +%Error: t/t_inst_param_override_bad.v:43:20: Instance attempts to override 'i_sub' as a parameter, but it is an instance + 43 | axi_stream_if #(.i_sub(10)) axis6 (clk); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_param_override_bad.v b/test_regress/t/t_inst_param_override_bad.v index 1ecc33c89..b882576b7 100644 --- a/test_regress/t/t_inst_param_override_bad.v +++ b/test_regress/t/t_inst_param_override_bad.v @@ -4,42 +4,42 @@ // SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 -module sub(); +module sub (); endmodule interface axi_stream_if #( - parameter int DATA_WIDTH = 64, + parameter int DATA_WIDTH = 64, parameter type TUSER_TYPE = logic ) ( input clk ); - task mytask(); - endtask : mytask + task mytask(); + endtask : mytask - genvar my_genvar; + genvar my_genvar; - logic tvalid; + logic tvalid; - sub i_sub(); + sub i_sub (); - localparam PACKED_DATA_WIDTH = DATA_WIDTH + DATA_WIDTH / 8 + 1 + $bits(TUSER_TYPE); + localparam PACKED_DATA_WIDTH = DATA_WIDTH + DATA_WIDTH / 8 + 1 + $bits(TUSER_TYPE); endinterface module t; - logic clk; + logic clk; - // overriding a localparam - axi_stream_if # (.PACKED_DATA_WIDTH(10)) axis1(clk); - // overriding a non-var - axi_stream_if # (.mytask(10)) axis2(clk); - // overriding a non-port/interface/param var - axi_stream_if # (.my_genvar(10)) axis3(clk); - // overriding a port - axi_stream_if # (.clk(10)) axis4(clk); - // overriding a signal - axi_stream_if # (.tvalid(10)) axis5(clk); - // overriding an instance - axi_stream_if # (.i_sub(10)) axis6(clk); + // overriding a localparam + axi_stream_if #(.PACKED_DATA_WIDTH(10)) axis1 (clk); + // overriding a non-var + axi_stream_if #(.mytask(10)) axis2 (clk); + // overriding a non-port/interface/param var + axi_stream_if #(.my_genvar(10)) axis3 (clk); + // overriding a port + axi_stream_if #(.clk(10)) axis4 (clk); + // overriding a signal + axi_stream_if #(.tvalid(10)) axis5 (clk); + // overriding an instance + axi_stream_if #(.i_sub(10)) axis6 (clk); endmodule diff --git a/test_regress/t/t_inst_paren_bad.out b/test_regress/t/t_inst_paren_bad.out index fe6d0d327..b3ffdd723 100644 --- a/test_regress/t/t_inst_paren_bad.out +++ b/test_regress/t/t_inst_paren_bad.out @@ -8,8 +8,8 @@ : ... Top module 't' 10 | module t; | ^ -%Error: t/t_inst_paren_bad.v:11:4: Can't find typedef/interface: 'sub' - 11 | sub sub_inst; - | ^~~ +%Error: t/t_inst_paren_bad.v:11:3: Can't find typedef/interface: 'sub' + 11 | sub sub_inst; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_inst_paren_bad.v b/test_regress/t/t_inst_paren_bad.v index f3974d5e3..4592e1eb5 100644 --- a/test_regress/t/t_inst_paren_bad.v +++ b/test_regress/t/t_inst_paren_bad.v @@ -8,5 +8,5 @@ module sub; endmodule module t; - sub sub_inst; // No () + sub sub_inst; // No () endmodule diff --git a/test_regress/t/t_inst_pin_place_bad.out b/test_regress/t/t_inst_pin_place_bad.out index 0a305f913..8184ae5f8 100644 --- a/test_regress/t/t_inst_pin_place_bad.out +++ b/test_regress/t/t_inst_pin_place_bad.out @@ -1,16 +1,16 @@ -%Warning-PINMISSING: t/t_inst_pin_place_bad.v:21:7: Instance has missing pin: 'pin_1' - 21 | ) i_sub ( - | ^~~~~ +%Warning-PINMISSING: t/t_inst_pin_place_bad.v:21:5: Instance has missing pin: 'pin_1' + 21 | ) i_sub ( + | ^~~~~ t/t_inst_pin_place_bad.v:11:11: ... Location of port declaration 11 | input pin_1 | ^~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. -%Error: t/t_inst_pin_place_bad.v:22:10: Instance attempts to connect to 'PARAM_A', but it is a parameter - 22 | .PARAM_A(1) - | ^~~~~~~ +%Error: t/t_inst_pin_place_bad.v:22:8: Instance attempts to connect to 'PARAM_A', but it is a parameter + 22 | .PARAM_A(1) + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_inst_pin_place_bad.v:20:10: Instance attempts to override 'pin_1' as a parameter, but it is a port - 20 | .pin_1(1) - | ^~~~~ +%Error: t/t_inst_pin_place_bad.v:20:8: Instance attempts to override 'pin_1' as a parameter, but it is a port + 20 | .pin_1(1) + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_pin_place_bad.v b/test_regress/t/t_inst_pin_place_bad.v index a93d2202b..0a22ab8e0 100644 --- a/test_regress/t/t_inst_pin_place_bad.v +++ b/test_regress/t/t_inst_pin_place_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 -module sub # ( +module sub #( parameter PARAM_A = 1, parameter type PARAM_B = logic ) ( @@ -13,12 +13,12 @@ module sub # ( endmodule module t; - parameter type PARAM_B = string; + parameter type PARAM_B = string; - sub #( - .PARAM_B(PARAM_B), - .pin_1(1) - ) i_sub ( - .PARAM_A(1) - ); + sub #( + .PARAM_B(PARAM_B), + .pin_1(1) + ) i_sub ( + .PARAM_A(1) + ); endmodule diff --git a/test_regress/t/t_inst_pin_realnreal.out b/test_regress/t/t_inst_pin_realnreal.out index 486d7613c..a96669476 100644 --- a/test_regress/t/t_inst_pin_realnreal.out +++ b/test_regress/t/t_inst_pin_realnreal.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_inst_pin_realnreal.v:51:32: Unsupported: Output port connection 'out' connects real to non-real +%Error-UNSUPPORTED: t/t_inst_pin_realnreal.v:49:31: Unsupported: Output port connection 'out' connects real to non-real : ... note: In instance 't.netlist' - 51 | pga_model pga0(.in, .gain, .out(pga_out)); - | ^~~ + 49 | pga_model pga0(.in, .gain, .out(pga_out)); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_inst_pin_realnreal.v b/test_regress/t/t_inst_pin_realnreal.v index 84a9df30f..6b551989b 100644 --- a/test_regress/t/t_inst_pin_realnreal.v +++ b/test_regress/t/t_inst_pin_realnreal.v @@ -4,73 +4,71 @@ // SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; - integer cyc; initial cyc=1; + integer cyc; initial cyc=1; - wire gain = 1'b0; - real in; - always_comb in = (cyc-4) * 1.0; - wire cmp; + wire gain = 1'b0; + real in; + always_comb in = (cyc-4) * 1.0; + wire cmp; - adc_netlist netlist(.clk, .in, .gain, .cmp); + adc_netlist netlist(.clk, .in, .gain, .cmp); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - $display("cyc=%0d cmp=%d", cyc, cmp); - if (cyc == 3) begin - if (cmp != 0) $stop; - end - else if (cyc == 4) begin - if (cmp != 1) $stop; - end - else if (cyc == 5) begin - if (cmp != 0) $stop; - end - else if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + $display("cyc=%0d cmp=%d", cyc, cmp); + if (cyc == 3) begin + if (cmp != 0) $stop; end - end + else if (cyc == 4) begin + if (cmp != 1) $stop; + end + else if (cyc == 5) begin + if (cmp != 0) $stop; + end + else if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module adc_netlist(clk, in, gain, cmp); - input clk; - input real in; - input gain; - output cmp; + input clk; + input real in; + input gain; + output cmp; - wire pga_out; //TODO: convert to real or support real - pga_model pga0(.in, .gain, .out(pga_out)); - comparator_model cmp0(.clk, .in(pga_out), .cmp); + wire pga_out; //TODO: convert to real or support real + pga_model pga0(.in, .gain, .out(pga_out)); + comparator_model cmp0(.clk, .in(pga_out), .cmp); endmodule module pga_model(in, gain, out); - input real in; - input gain; - output real out; + input real in; + input gain; + output real out; - always_comb begin - out = in * 3.0; - end + always_comb begin + out = in * 3.0; + end endmodule module comparator_model(clk, in, cmp); - input clk; - input real in; - output logic cmp; + input clk; + input real in; + output logic cmp; - always_ff @(posedge clk) begin - cmp <= in > 0.0; - end + always_ff @(posedge clk) begin + cmp <= in > 0.0; + end endmodule diff --git a/test_regress/t/t_inst_port_array.v b/test_regress/t/t_inst_port_array.v index a4d2b7f7e..1b8839482 100644 --- a/test_regress/t/t_inst_port_array.v +++ b/test_regress/t/t_inst_port_array.v @@ -4,46 +4,54 @@ // SPDX-FileCopyrightText: 2013 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic [6-1:0] foo[4-1:0]; + logic [6-1:0] foo[4-1:0]; - //initial $display("%m: %p\n", foo); - //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice - //logic [6-1:0] foo2[4-1:0][5:6]; - //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal + //initial $display("%m: %p\n", foo); + //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice + //logic [6-1:0] foo2[4-1:0][5:6]; + //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal - dut #(.W(6), - .D(4)) udut(.clk(clk), - .foo(foo[4-1:0])); + dut #( + .W(6), + .D(4) + ) udut ( + .clk(clk), + .foo(foo[4-1:0]) + ); endmodule -module dut - #(parameter W = 1, - parameter D = 1) - (input logic clk, - input logic [W-1:0] foo[D-1:0]); +module dut #( + parameter W = 1, + parameter D = 1 +) ( + input logic clk, + input logic [W-1:0] foo[D-1:0] +); - genvar i, j; - generate - for (j = 0; j < D; j++) begin - for (i = 0; i < W; i++) begin - suba ua(.clk(clk), .foo(foo[j][i])); - end - end - endgenerate + genvar i, j; + generate + for (j = 0; j < D; j++) begin + for (i = 0; i < W; i++) begin + suba ua ( + .clk(clk), + .foo(foo[j][i]) + ); + end + end + endgenerate endmodule -module suba - (input logic clk, - input logic foo); +module suba ( + input logic clk, + input logic foo +); - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inst_prepost.v b/test_regress/t/t_inst_prepost.v index 4eb33ec17..f7e86d805 100644 --- a/test_regress/t/t_inst_prepost.v +++ b/test_regress/t/t_inst_prepost.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 module t; - sub #(10,11,12,13) sub (); + sub #(10, 11, 12, 13) sub (); endmodule -module sub (); - parameter A = 0; - parameter B = 1; +module sub (); + parameter A = 0; + parameter B = 1; - ip ip(); + ip ip (); - parameter C = 2; - parameter D = 3; + parameter C = 2; + parameter D = 3; - initial begin - if (A!=10) $stop; - if (B!=11) $stop; - if (C!=12) $stop; - if (D!=13) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (A != 10) $stop; + if (B != 11) $stop; + if (C != 12) $stop; + if (D != 13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inst_public.v b/test_regress/t/t_inst_public.v index f426e170b..942984a4f 100644 --- a/test_regress/t/t_inst_public.v +++ b/test_regress/t/t_inst_public.v @@ -6,26 +6,26 @@ module t; - Pub pub(); + Pub pub (); - localparam ZERO = 0; - if (ZERO) Dead dead(); + localparam ZERO = 0; + if (ZERO) Dead dead (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module Pub; - // verilator public_module + // verilator public_module - // no signals here + // no signals here endmodule module Dead; - // verilator public_module + // verilator public_module endmodule diff --git a/test_regress/t/t_inst_recurse2_bad.v b/test_regress/t/t_inst_recurse2_bad.v index 5e1725f7d..a7a120050 100644 --- a/test_regress/t/t_inst_recurse2_bad.v +++ b/test_regress/t/t_inst_recurse2_bad.v @@ -6,10 +6,10 @@ module t; - looped looped (); + looped looped (); endmodule module looped; - looped looped (); + looped looped (); endmodule diff --git a/test_regress/t/t_inst_recurse_bad.v b/test_regress/t/t_inst_recurse_bad.v index d963cfb3b..cb568ae50 100644 --- a/test_regress/t/t_inst_recurse_bad.v +++ b/test_regress/t/t_inst_recurse_bad.v @@ -6,14 +6,14 @@ module t; - looped looped (); + looped looped (); endmodule module looped; - looped2 looped2 (); + looped2 looped2 (); endmodule module looped2; - looped looped (); + looped looped (); endmodule diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v index b79b1542f..bd46592dd 100644 --- a/test_regress/t/t_inst_signed.v +++ b/test_regress/t/t_inst_signed.v @@ -4,63 +4,67 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 0; - integer cyc; initial cyc = 0; + wire signed [7:0] sgn_wide; + wire [7:0] unsgn_wide; - wire signed [7:0] sgn_wide; - wire [7:0] unsgn_wide; + // The instantiation will Z extend, not sign extend + // verilator lint_off WIDTH + sub sub ( + .clk, + .sgn(sgn_wide), + .unsgn(unsgn_wide), + .iss(3'sh7), + .isu(3'h7), + .ius(3'sh7), + .iuu(3'h7) + ); + // verilator lint_on WIDTH - // The instantiation will Z extend, not sign extend - // verilator lint_off WIDTH - sub sub (.clk, - .sgn(sgn_wide), .unsgn(unsgn_wide), - .iss(3'sh7), .isu(3'h7), - .ius(3'sh7), .iuu(3'h7)); - // verilator lint_on WIDTH - - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); + $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); `endif - if (sgn_wide[2:0] != 3'sh7) $stop; - if (unsgn_wide[2:0] != 3'h7) $stop; - // Simulators differ here. - if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC - && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS - if (unsgn_wide !== 8'sbzzzzz111 - && unsgn_wide!== 8'sb00000111) $stop; - cyc <= cyc + 1; - if (cyc==3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (sgn_wide[2:0] != 3'sh7) $stop; + if (unsgn_wide[2:0] != 3'h7) $stop; + // Simulators differ here. + if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC + && sgn_wide !== 8'sb11111111) + $stop; // sign extension - VCS + if (unsgn_wide !== 8'sbzzzzz111 && unsgn_wide !== 8'sb00000111) $stop; + cyc <= cyc + 1; + if (cyc == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module sub ( - input clk, - output wire signed [2:0] sgn, - output wire [2:0] unsgn, - input signed [7:0] iss, - input signed [7:0] isu, - input [7:0] ius, - input [7:0] iuu); - assign sgn = 3'sh7; - assign unsgn = 3'h7; - always @ (posedge clk) begin + input clk, + output wire signed [2:0] sgn, + output wire [2:0] unsgn, + input signed [7:0] iss, + input signed [7:0] isu, + input [7:0] ius, + input [7:0] iuu +); + assign sgn = 3'sh7; + assign unsgn = 3'h7; + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("in: %x %x %x %x\n", iss, isu, ius, iuu); - if (iss != 8'hff) $stop; - if (isu != 8'h07) $stop; - if (ius != 8'hff) $stop; - if (iuu != 8'h07) $stop; + $write("in: %x %x %x %x\n", iss, isu, ius, iuu); + if (iss != 8'hff) $stop; + if (isu != 8'h07) $stop; + if (ius != 8'hff) $stop; + if (iuu != 8'h07) $stop; `endif - end + end endmodule diff --git a/test_regress/t/t_inst_signed1.v b/test_regress/t/t_inst_signed1.v index 27a9b5393..74e9f6f3f 100644 --- a/test_regress/t/t_inst_signed1.v +++ b/test_regress/t/t_inst_signed1.v @@ -4,49 +4,58 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg signed i; - wire signed o1; - wire signed o2; + reg signed i; + wire signed o1; + wire signed o2; - integer cyc; initial cyc = 0; + integer cyc; + initial cyc = 0; - sub1 sub1 (.i(i), .o(o1)); - sub2 sub2 (.i(o1), .o(o2)); + sub1 sub1 ( + .i(i), + .o(o1) + ); + sub2 sub2 ( + .i(o1), + .o(o2) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - i <= 1'b0; - end - else if (cyc==1) begin - if (o2 != 1'b0) $stop; - i <= 1'b1; - end - else if (cyc==2) begin - if (o2 != 1'b1) $stop; - end - if (cyc==3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + i <= 1'b0; + end + else if (cyc == 1) begin + if (o2 != 1'b0) $stop; + i <= 1'b1; + end + else if (cyc == 2) begin + if (o2 != 1'b1) $stop; + end + if (cyc == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule //msg2540 module sub1 ( - input signed i, - output wire signed o); - assign o = ~i; + input signed i, + output wire signed o +); + assign o = ~i; endmodule -module sub2 (i,o); - input signed i; - output signed o; - wire signed o = ~i; +module sub2 ( + i, + o +); + input signed i; + output signed o; + wire signed o = ~i; endmodule diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v index 3391b870d..791e8b639 100644 --- a/test_regress/t/t_inst_slice.v +++ b/test_regress/t/t_inst_slice.v @@ -5,81 +5,82 @@ // SPDX-License-Identifier: CC0-1.0 // bug1015 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [1:0] i = crc[1:0]; - logic [1:0] o [13:10] ; + // Take CRC data and apply to testblock inputs + wire [1:0] i = crc[1:0]; + logic [1:0] o[13:10]; - Test test (/*AUTOINST*/ - // Outputs - .o (o/*[1:0].[3:0]*/), - // Inputs - .i (i[1:0])); + Test test ( /*AUTOINST*/ + // Outputs + .o(o /*[1:0].[3:0]*/), + // Inputs + .i(i[1:0]) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, 6'h0, o[13], 6'h0, o[12], 6'h0, o[11], 6'h0, o[10]}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); + $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hb42b2f48a0a9375a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hb42b2f48a0a9375a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test - ( - output logic [1:0] o [3:0], - //but this works - //logic [N-1:0] o - input [1:0] i); +module Test ( + output logic [1:0] o[3:0], + //but this works + //logic [N-1:0] o + input [1:0] i +); - parameter N = 4; + parameter N = 4; - logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; + logic [1:0] a[3:0]; + initial a = '{2'h0, 2'h1, 2'h2, 2'h3}; - sub sub [N-1:0] (.o (o), // many-to-many - .a (a), // many-to-many - .i (i)); // many-to-one + sub sub[N-1:0] ( + .o(o), // many-to-many + .a(a), // many-to-many + .i(i) + ); // many-to-one endmodule -module sub - ( - input logic [1:0] i, - input logic [1:0] a, - output logic [1:0] o - ); - assign o = i + a; +module sub ( + input logic [1:0] i, + input logic [1:0] a, + output logic [1:0] o +); + assign o = i + a; endmodule diff --git a/test_regress/t/t_inst_slice_part_select.v b/test_regress/t/t_inst_slice_part_select.v index 827561026..2d553c4aa 100644 --- a/test_regress/t/t_inst_slice_part_select.v +++ b/test_regress/t/t_inst_slice_part_select.v @@ -4,90 +4,81 @@ // SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - wire [31:0] in = 0; - wire [31:0] out; + wire [31:0] in = 0; + wire [31:0] out; - Test test( - .out(out[31:0]), - .clk(clk), - .in (in[31:0]) - ); + Test test ( + .out(out[31:0]), + .clk(clk), + .in(in[31:0]) + ); - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule interface Intf (); endinterface -module Select - #( +module Select #( parameter int NUM_MASTER = 1 - ) - ( +) ( Intf Upstream, Intf Downstream[NUM_MASTER] - ); +); endmodule -module Crossbar - #( - parameter int NUM_MASTER = 1, - parameter int NUM_SLAVE = 1 - ) - ( - Intf Masters[NUM_MASTER] +module Crossbar #( + parameter int NUM_MASTER = 1, + parameter int NUM_SLAVE = 1 +) ( + Intf Masters[NUM_MASTER] +); + + Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0] (); + + + genvar i; + + for (i = 0; i < NUM_MASTER; i = i + 1) begin + Select #( + .NUM_MASTER(NUM_SLAVE) + ) select_inst ( + .Upstream(Masters[i]), + // Following line seems to trigger a bad calculation for dimension where port + // is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE + .Downstream(selectOut[(i)*(NUM_SLAVE)+:(NUM_SLAVE)]) + // The following line works as intended and should be functionally identical to the above line + // .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)]) + ); + end + +endmodule + +module Test ( + input clk, + input [31:0] in, + output reg [31:0] out +); + + always @(posedge clk) begin + out <= in; + end + + Intf MST[10] (); + + Crossbar #( + .NUM_MASTER(10), + .NUM_SLAVE(1) + ) xbar_inst ( + .Masters(MST) ); - Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0](); - - - genvar i; - - for (i = 0; i < NUM_MASTER; i = i + 1) begin - Select #( - .NUM_MASTER(NUM_SLAVE) - ) - select_inst ( - .Upstream(Masters[i]), - // Following line seems to trigger a bad calculation for dimension where port - // is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE - .Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)]) - // The following line works as intended and should be functionally identical to the above line -// .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)]) - ); - end - -endmodule - -module Test - ( - input clk, - input [31:0] in, - output reg [31:0] out - ); - - always @(posedge clk) begin - out <= in; - end - - Intf MST[10](); - - Crossbar #( - .NUM_MASTER(10), - .NUM_SLAVE(1) - ) - xbar_inst ( - .Masters(MST) - ); - endmodule diff --git a/test_regress/t/t_inst_sv.v b/test_regress/t/t_inst_sv.v index e2cfeb46d..16441d4ed 100644 --- a/test_regress/t/t_inst_sv.v +++ b/test_regress/t/t_inst_sv.v @@ -4,72 +4,69 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - supply0 [1:0] low; - supply1 [1:0] high; + supply0 [1:0] low; + supply1 [1:0] high; - reg [7:0] isizedwire; - reg ionewire; + reg [7:0] isizedwire; + reg ionewire; - wire oonewire; - wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v + wire oonewire; + wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v - t_inst sub - ( + t_inst sub ( .osizedreg, .oonewire, // Inputs - .isizedwire (isizedwire[7:0]), + .isizedwire(isizedwire[7:0]), .* //.ionewire (ionewire) - ); + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - ionewire <= 1'b1; - isizedwire <= 8'd8; - end - if (cyc==2) begin - if (low != 2'b00) $stop; - if (high != 2'b11) $stop; - if (oonewire !== 1'b1) $stop; - if (isizedwire !== 8'd8) $stop; - end - if (cyc==3) begin - ionewire <= 1'b0; - isizedwire <= 8'd7; - end - if (cyc==4) begin - if (oonewire !== 1'b0) $stop; - if (isizedwire !== 8'd7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; end - end + if (cyc == 2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + end + if (cyc == 3) begin + ionewire <= 1'b0; + isizedwire <= 8'd7; + end + if (cyc == 4) begin + if (oonewire !== 1'b0) $stop; + if (isizedwire !== 8'd7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module t_inst - ( - output reg [7:0] osizedreg, - output wire oonewire /*verilator public*/, - input [7:0] isizedwire, - input wire ionewire - ); +module t_inst ( + output reg [7:0] osizedreg, + output wire oonewire /*verilator public*/, + input [7:0] isizedwire, + input wire ionewire +); - assign oonewire = ionewire; + assign oonewire = ionewire; - always @* begin - osizedreg = isizedwire; - end + always @* begin + osizedreg = isizedwire; + end endmodule diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v index 6a0a211f6..cc3def710 100644 --- a/test_regress/t/t_inst_tree.v +++ b/test_regress/t/t_inst_tree.v @@ -5,83 +5,83 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); - input clk; - integer cyc; initial cyc=1; + input clk; + integer cyc; initial cyc=1; - reg printclk; + reg printclk; - ps ps (printclk); + ps ps (printclk); - reg [7:0] a; - wire [7:0] z; + reg [7:0] a; + wire [7:0] z; - l1 u (~a,z); + l1 u (~a,z); - always @ (posedge clk) begin - printclk <= 0; - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - printclk <= 1'b1; - end - if (cyc==2) begin - a <= 8'b1; - end - if (cyc==3) begin - if (z !== 8'hf8) $stop; - //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; - //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; - //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; - //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; - //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; - //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + printclk <= 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + printclk <= 1'b1; end - end + if (cyc==2) begin + a <= 8'b1; + end + if (cyc==3) begin + if (z !== 8'hf8) $stop; + //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; + //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; + //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; + //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; + //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; + //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module ps (input printclk); - // Check that %m stays correct across inlines - always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); + // Check that %m stays correct across inlines + always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); endmodule module l1 (input [7:0] a, output [7:0] z); - wire [7:0] z0; wire [7:0] z1; - assign z = z0+z1; - l2 u0 (a, z0); l2 u1 (a, z1); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + l2 u0 (a, z0); l2 u1 (a, z1); endmodule module l2 (input [7:0] a, output [7:0] z); - wire [7:0] z0; wire [7:0] z1; - assign z = z0+z1; - wire [7:0] a1 = a+8'd1; - l3 u0 (a, z0); l3 u1 (a1, z1); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l3 u0 (a, z0); l3 u1 (a1, z1); endmodule module l3 (input [7:0] a, output [7:0] z); - wire [7:0] z0; wire [7:0] z1; - assign z = z0+z1; - wire [7:0] a1 = a+8'd1; - l4 u0 (a, z0); l4 u1 (a1, z1); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l4 u0 (a, z0); l4 u1 (a1, z1); endmodule module l4 (input [7:0] a, output [7:0] z); - wire [7:0] z0; wire [7:0] z1; - assign z = z0+z1; - wire [7:0] a1 = a+8'd1; - l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); endmodule module l5 (input [7:0] a, output [7:0] z); - parameter PARAM = 5; - wire [7:0] z0; wire [7:0] z1; - assign z = a; + parameter PARAM = 5; + wire [7:0] z0; wire [7:0] z1; + assign z = a; endmodule diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index d8a3af367..41ecffceb 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -4,67 +4,68 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - supply0 [1:0] low; - supply1 [1:0] high; + supply0 [1:0] low; + supply1 [1:0] high; - reg [7:0] isizedwire; - reg ionewire; + reg [7:0] isizedwire; + reg ionewire; `ifdef never_just_for_verilog_mode - wire oonewire; // From sub of t_inst_v2k__sub.v + wire oonewire; // From sub of t_inst_v2k__sub.v `endif - wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v - wire [1:0] tied; - wire [3:0] tied_also; + wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v + wire [1:0] tied; + wire [3:0] tied_also; - hello hsub (.tied_also); + hello hsub (.tied_also); - // Double underscore tests bug631 - t_inst_v2k__sub sub - ( + // Double underscore tests bug631 + t_inst_v2k__sub sub ( // Outputs - .osizedreg (osizedreg[7:0]), + .osizedreg(osizedreg[7:0]), // verilator lint_off IMPLICIT - .oonewire (oonewire), + .oonewire(oonewire), // verilator lint_on IMPLICIT - .tied (tied[1:0]), + .tied(tied[1:0]), // Inputs - .isizedwire (isizedwire[7:0]), - .ionewire (ionewire)); + .isizedwire(isizedwire[7:0]), + .ionewire(ionewire) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - ionewire <= 1'b1; - isizedwire <= 8'd8; - end - if (cyc==2) begin - if (low != 2'b00) $stop; - if (high != 2'b11) $stop; - if (oonewire !== 1'b1) $stop; - if (isizedwire !== 8'd8) $stop; - if (tied != 2'b10) $stop; - if (tied_also != 4'b1010) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; end - end + if (cyc == 2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + if (tied != 2'b10) $stop; + if (tied_also != 4'b1010) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule -module hello(tied_also); - initial $write ("Hello\n"); - output reg [3:0] tied_also = 4'b1010; +module hello ( + tied_also +); + initial $write("Hello\n"); + output reg [3:0] tied_also = 4'b1010; endmodule diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v index 39c86f763..c2717f0f7 100644 --- a/test_regress/t/t_inst_wideconst.v +++ b/test_regress/t/t_inst_wideconst.v @@ -4,66 +4,65 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [41:0] aaa; - wire [41:0] bbb; + reg [41:0] aaa; + wire [41:0] bbb; - // verilator public_module - wire [41:0] z_0; - wire [41:0] z_1; + // verilator public_module + wire [41:0] z_0; + wire [41:0] z_1; - wide w_0( - .xxx( { {40{1'b0}},2'b11 } ), - .yyy( aaa[1:0] ), - .zzz( z_0 ) - ); + wide w_0 ( + .xxx({{40{1'b0}}, 2'b11}), + .yyy(aaa[1:0]), + .zzz(z_0) + ); - wide w_1( - .xxx( aaa ), - .yyy( 2'b10 ), - .zzz( z_1 ) - ); + wide w_1 ( + .xxx(aaa), + .yyy(2'b10), + .zzz(z_1) + ); - assign bbb= z_0 + z_1; + assign bbb = z_0 + z_1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - aaa <= 42'b01; - end - if (cyc==2) begin - aaa <= 42'b10; - if (z_0 != 42'h4) $stop; - if (z_1 != 42'h3) $stop; - end - if (cyc==3) begin - if (z_0 != 42'h5) $stop; - if (z_1 != 42'h4) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + aaa <= 42'b01; end - end + if (cyc == 2) begin + aaa <= 42'b10; + if (z_0 != 42'h4) $stop; + if (z_1 != 42'h3) $stop; + end + if (cyc == 3) begin + if (z_0 != 42'h5) $stop; + if (z_1 != 42'h4) $stop; + end + if (cyc == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module wide ( - input [41:0] xxx, - input [1:0] yyy, - output [41:0] zzz - ); - // verilator public_module + input [41:0] xxx, + input [1:0] yyy, + output [41:0] zzz +); + // verilator public_module - assign zzz = xxx+ { {40{1'b0}},yyy }; + assign zzz = xxx + {{40{1'b0}}, yyy}; endmodule diff --git a/test_regress/t/t_interconnect.out b/test_regress/t/t_interconnect.out index 7cc18791b..e91910e20 100644 --- a/test_regress/t/t_interconnect.out +++ b/test_regress/t/t_interconnect.out @@ -1,14 +1,14 @@ -%Error-UNSUPPORTED: t/t_interconnect.v:12:4: Unsupported: interconnect - 12 | interconnect a; - | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_interconnect.v:12:3: Unsupported: interconnect + 12 | interconnect a; + | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_interconnect.v:13:4: Unsupported: interconnect - 13 | interconnect b; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_interconnect.v:22:11: Unsupported: interconnect - 22 | output interconnect a, - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_interconnect.v:23:11: Unsupported: interconnect - 23 | output interconnect b); - | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_interconnect.v:13:3: Unsupported: interconnect + 13 | interconnect b; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_interconnect.v:21:12: Unsupported: interconnect + 21 | output interconnect a, + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_interconnect.v:22:12: Unsupported: interconnect + 22 | output interconnect b); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interconnect.v b/test_regress/t/t_interconnect.v index a4d327863..c4c724d0b 100644 --- a/test_regress/t/t_interconnect.v +++ b/test_regress/t/t_interconnect.v @@ -9,41 +9,39 @@ module t; - interconnect a; - interconnect b; + interconnect a; + interconnect b; - moda suba (.a, .b); - modb #(.TA_t(real)) subb (.a(a), .b(b)); + moda suba (.a, .b); + modb #(.TA_t(real)) subb (.a(a), .b(b)); endmodule -module moda - ( - output interconnect a, - output interconnect b); - modaa subaa (.a, .b); +module moda ( + output interconnect a, + output interconnect b); + modaa subaa (.a, .b); endmodule -module modaa - ( - output real a, - output int b); - initial begin - a = 1.234; - b = 1234; - end +module modaa ( + output real a, + output int b); + initial begin + a = 1.234; + b = 1234; + end endmodule module modb #(parameter type TA_t = int) ( - input TA_t a, - input int b); - initial begin - #10; - if (a != 1.234) $stop; - if (b != 1234) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + input TA_t a, + input int b); + initial begin + #10; + if (a != 1.234) $stop; + if (b != 1234) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interconnect_bad.out b/test_regress/t/t_interconnect_bad.out index 061e7f1e2..f351208e1 100644 --- a/test_regress/t/t_interconnect_bad.out +++ b/test_regress/t/t_interconnect_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_interconnect_bad.v:9:4: Unsupported: interconnect - 9 | interconnect a; - | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_interconnect_bad.v:9:3: Unsupported: interconnect + 9 | interconnect a; + | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_interconnect_bad.v b/test_regress/t/t_interconnect_bad.v index 961792fe5..af7503c11 100644 --- a/test_regress/t/t_interconnect_bad.v +++ b/test_regress/t/t_interconnect_bad.v @@ -6,12 +6,12 @@ module t; - interconnect a; + interconnect a; - assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment + assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment - initial begin - a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment - end + initial begin + a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment + end endmodule diff --git a/test_regress/t/t_interface.v b/test_regress/t/t_interface.v index 9f09df9f2..071e007e4 100644 --- a/test_regress/t/t_interface.v +++ b/test_regress/t/t_interface.v @@ -4,167 +4,164 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic rst = 1'b1; // reset + integer rst_cnt = 0; - logic rst = 1'b1; // reset - integer rst_cnt = 0; + // reset is removed after a delay + always @ (posedge clk) + begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; + end - // reset is removed after a delay - always @ (posedge clk) - begin - rst_cnt <= rst_cnt + 1; - rst <= rst_cnt <= 3; - end + // counters + int cnt; + int cnt_src; + int cnt_drn; - // counters - int cnt; - int cnt_src; - int cnt_drn; + // add all counters + assign cnt = cnt_src + cnt_drn + inf.cnt; - // add all counters - assign cnt = cnt_src + cnt_drn + inf.cnt; + // finish report + always @ (posedge clk) + if (cnt == 3*16) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) - if (cnt == 3*16) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // interface instance + handshake inf ( + .clk (clk), + .rst (rst) + ); - // interface instance - handshake inf ( - .clk (clk), - .rst (rst) - ); + // source instance + source #( + .RW (8), + .RP (8'b11100001) + ) source ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_src) + ); - // source instance - source #( - .RW (8), - .RP (8'b11100001) - ) source ( - .clk (clk), - .rst (rst), - .inf (inf), - .cnt (cnt_src) - ); - - // drain instance - drain #( - .RW (8), - .RP (8'b11010100) - ) drain ( - .clk (clk), - .rst (rst), - .inf (inf), - .cnt (cnt_drn) - ); + // drain instance + drain #( + .RW (8), + .RP (8'b11010100) + ) drain ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_drn) + ); endmodule : t // interface definition interface handshake #( - parameter int unsigned WC = 32 + parameter int unsigned WC = 32 )( - input logic clk, - input logic rst + input logic clk, + input logic rst ); - // modport signals - logic req; // request - logic grt; // grant - logic inc; // increment + // modport signals + logic req; // request + logic grt; // grant + logic inc; // increment - // local signals - integer cnt; // counter + // local signals + integer cnt; // counter - // source - modport src ( - output req, - input grt - ); + // source + modport src ( + output req, + input grt + ); - // drain - modport drn ( - input req, - output grt - ); + // drain + modport drn ( + input req, + output grt + ); - // incremet condition - assign inc = req & grt; + // incremet condition + assign inc = req & grt; - // local logic (counter) - always @ (posedge clk, posedge rst) - if (rst) cnt <= '0; - else cnt <= cnt + {31'h0, inc}; + // local logic (counter) + always @ (posedge clk, posedge rst) + if (rst) cnt <= '0; + else cnt <= cnt + {31'h0, inc}; endinterface : handshake // source module module source #( - // random generator parameters - parameter int unsigned RW=1, // LFSR width - parameter bit [RW-1:0] RP='0, // LFSR polinom - parameter bit [RW-1:0] RR='1 // LFSR reset state + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state )( - input logic clk, - input logic rst, - handshake.src inf, - output integer cnt + input logic clk, + input logic rst, + handshake.src inf, + output integer cnt ); - // LFSR - logic [RW-1:0] rnd; + // LFSR + logic [RW-1:0] rnd; - // LFSR in Galois form - always @ (posedge clk, posedge rst) - if (rst) rnd <= RR; - else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); - // counter - always @ (posedge clk, posedge rst) - if (rst) cnt <= 32'd0; - else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; - // request signal - assign inf.req = rnd[0]; + // request signal + assign inf.req = rnd[0]; endmodule : source // drain module module drain #( - // random generator parameters - parameter int unsigned RW=1, // LFSR width - parameter bit [RW-1:0] RP='0, // LFSR polinom - parameter bit [RW-1:0] RR='1 // LFSR reset state + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state )( - input logic clk, - input logic rst, - handshake.drn inf, - output integer cnt + input logic clk, + input logic rst, + handshake.drn inf, + output integer cnt ); - // LFSR - logic [RW-1:0] rnd; + // LFSR + logic [RW-1:0] rnd; - // LFSR in Galois form - always @ (posedge clk, posedge rst) - if (rst) rnd <= RR; - else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); - // counter - always @ (posedge clk, posedge rst) - if (rst) cnt <= 32'd0; - else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; - // grant signal - assign inf.grt = rnd[0]; + // grant signal + assign inf.grt = rnd[0]; endmodule : drain diff --git a/test_regress/t/t_interface1.v b/test_regress/t/t_interface1.v index be074184e..3092ac15b 100644 --- a/test_regress/t/t_interface1.v +++ b/test_regress/t/t_interface1.v @@ -7,40 +7,39 @@ // Very simple test for interface pathclearing interface ifc; - logic [3:0] value; + logic [3:0] value; endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc itop(); + ifc itop (); - sub c1 (.isub(itop), - .i_value(4'h4)); + sub c1 ( + .isub(itop), + .i_value(4'h4) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison - if (itop.value != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison + if (itop.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub - ( - ifc isub, - input logic [3:0] i_value - ); +module sub ( + ifc isub, + input logic [3:0] i_value +); - always @* begin - isub.value = i_value; - end + always @* begin + isub.value = i_value; + end endmodule : sub diff --git a/test_regress/t/t_interface1_modport.v b/test_regress/t/t_interface1_modport.v index ab64c2854..3d8968c64 100644 --- a/test_regress/t/t_interface1_modport.v +++ b/test_regress/t/t_interface1_modport.v @@ -7,51 +7,49 @@ // Very simple test for interface pathclearing interface ifc; - integer hidden_from_isub; - integer value; - modport out_modport (output value); + integer hidden_from_isub; + integer value; + modport out_modport (output value); endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc=1; - ifc itop(); + ifc itop(); - sub c1 (.isub(itop), - .i_value(4)); + sub c1 (.isub(itop), + .i_value(4)); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (itop.value != 4) $stop; - itop.hidden_from_isub = 20; - if (itop.hidden_from_isub != 20) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop.value != 4) $stop; + itop.hidden_from_isub = 20; + if (itop.hidden_from_isub != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module sub `ifdef NANSI // bug868 ( - isub, i_value - ); - ifc.out_modport isub; // Note parenthesis are not legal here - input integer i_value; + isub, i_value + ); + ifc.out_modport isub; // Note parenthesis are not legal here + input integer i_value; `else ( - ifc.out_modport isub, - input integer i_value - ); + ifc.out_modport isub, + input integer i_value + ); `endif - always @* begin - isub.value = i_value; - end + always @* begin + isub.value = i_value; + end endmodule diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v index 872550823..e11f71b1f 100644 --- a/test_regress/t/t_interface2.v +++ b/test_regress/t/t_interface2.v @@ -4,103 +4,101 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc=1; - counter_io c1_data(); - counter_io c2_data(); - //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells - counter_io c3_data(); + counter_io c1_data(); + counter_io c2_data(); + //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells + counter_io c3_data(); - counter_ansi c1 (.clkm(clk), - .c_data(c1_data), - .i_value(4'h1)); - counter_ansi c2 (.clkm(clk), - .c_data(c2_data), - .i_value(4'h2)); + counter_ansi c1 (.clkm(clk), + .c_data(c1_data), + .i_value(4'h1)); + counter_ansi c2 (.clkm(clk), + .c_data(c2_data), + .i_value(4'h2)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif - /**/ c3 (.clkm(clk), - .c_data(c3_data), - .i_value(4'h3)); + /**/ c3 (.clkm(clk), + .c_data(c3_data), + .i_value(4'h3)); - initial begin - c1_data.value = 4'h4; - c2_data.value = 4'h5; - c3_data.value = 4'h6; - end + initial begin + c1_data.value = 4'h4; + c2_data.value = 4'h5; + c3_data.value = 4'h6; + end - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc<2) begin - c1_data.reset <= 1; - c2_data.reset <= 1; - c3_data.reset <= 1; - end - if (cyc==2) begin - c1_data.reset <= 0; - c2_data.reset <= 0; - c3_data.reset <= 0; - end - if (cyc==3) begin - if (c1_data.get_lcl() != 12345) $stop; - end - if (cyc==20) begin - $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, - c1_data.value, c1_data.reset, - c2_data.value, c2_data.reset, - c3_data.value, c3_data.reset); - if (c1_data.value != 2) $stop; - if (c2_data.value != 3) $stop; - if (c3_data.value != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc<2) begin + c1_data.reset <= 1; + c2_data.reset <= 1; + c3_data.reset <= 1; + end + if (cyc==2) begin + c1_data.reset <= 0; + c2_data.reset <= 0; + c3_data.reset <= 0; + end + if (cyc==3) begin + if (c1_data.get_lcl() != 12345) $stop; + end + if (cyc==20) begin + $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, + c1_data.value, c1_data.reset, + c2_data.value, c2_data.reset, + c3_data.value, c3_data.reset); + if (c1_data.value != 2) $stop; + if (c2_data.value != 3) $stop; + if (c3_data.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule interface counter_io; - logic [3:0] value; - logic reset; - integer lcl; - task set_lcl (input integer a); lcl=a; endtask - function integer get_lcl (); return lcl; endfunction + logic [3:0] value; + logic reset; + integer lcl; + task set_lcl (input integer a); lcl=a; endtask + function integer get_lcl (); return lcl; endfunction endinterface interface ifunused; - logic unused; + logic unused; endinterface module counter_ansi ( - input clkm, - counter_io c_data, - input logic [3:0] i_value - ); + input clkm, + counter_io c_data, + input logic [3:0] i_value + ); - initial begin - c_data.set_lcl(12345); - end + initial begin + c_data.set_lcl(12345); + end - always @ (posedge clkm) begin - c_data.value <= c_data.reset ? i_value : c_data.value + 1; - end + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end endmodule : counter_ansi `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi(clkm, c_data, i_value); - input clkm; - counter_io c_data; - input logic [3:0] i_value; + input clkm; + counter_io c_data; + input logic [3:0] i_value; - always @ (posedge clkm) begin - c_data.value <= c_data.reset ? i_value : c_data.value + 1; - end + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end endmodule : counter_nansi `endif @@ -108,6 +106,6 @@ endmodule : counter_nansi // Other simulators will see it, and is illegal to have unconnected interface `ifdef VERILATOR module modunused (ifunused ifinunused); - ifunused ifunused(); + ifunused ifunused(); endmodule `endif diff --git a/test_regress/t/t_interface_and_struct_pattern.v b/test_regress/t/t_interface_and_struct_pattern.v index 39109a3b9..d3ed947db 100644 --- a/test_regress/t/t_interface_and_struct_pattern.v +++ b/test_regress/t/t_interface_and_struct_pattern.v @@ -5,55 +5,55 @@ // SPDX-License-Identifier: CC0-1.0 package Package_pkg; - typedef struct packed { - int bar; - int baz; - } pkg_struct_t; + typedef struct packed { + int bar; + int baz; + } pkg_struct_t; endpackage -interface intf - #(parameter type data_type = bit) - (input wire clk, - input wire rst); - data_type data; - modport source ( - input clk, rst, - output data - ); +interface intf #( + parameter type data_type = bit +) ( + input wire clk, + input wire rst +); + data_type data; + modport source(input clk, rst, output data); endinterface module sub ( intf.source bar, input clk, - input rst); + input rst +); - typedef struct packed { - int foo; - int baz; - } struct_t; + typedef struct packed { + int foo; + int baz; + } struct_t; - intf #(.data_type(struct_t)) the_intf (.*); + intf #(.data_type(struct_t)) the_intf (.*); - Package_pkg::pkg_struct_t output_bar = Package_pkg::pkg_struct_t'{ - bar: the_intf.data.foo, - baz: the_intf.data.baz - }; + Package_pkg::pkg_struct_t output_bar = Package_pkg::pkg_struct_t +'{bar: the_intf.data.foo, baz: the_intf.data.baz}; endmodule -module t(clk); - input clk; - logic rst; +module t ( + clk +); + input clk; + logic rst; - intf bar (.*); - sub the_sub ( - .bar(bar), - .clk, - .rst - ); + intf bar (.*); + sub the_sub ( + .bar(bar), + .clk, + .rst + ); - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_ar2a.v b/test_regress/t/t_interface_ar2a.v index 8e2142d3f..ea6ce08af 100644 --- a/test_regress/t/t_interface_ar2a.v +++ b/test_regress/t/t_interface_ar2a.v @@ -6,25 +6,23 @@ module t; - ahb_slave_intf AHB_S[1](); + ahb_slave_intf AHB_S[1] (); - AHB_MEM uMEM(.S(AHB_S[0].source)); -// AHB_MEM V_MEM(.S(AHB_S[0])); + AHB_MEM uMEM (.S(AHB_S[0].source)); + // AHB_MEM V_MEM(.S(AHB_S[0])); endmodule -module AHB_MEM - ( - ahb_slave_intf.source S - ); +module AHB_MEM ( + ahb_slave_intf.source S +); endmodule -interface ahb_slave_intf - (); +interface ahb_slave_intf (); - logic [31:0] HADDR; + logic [31:0] HADDR; - modport source (input HADDR); + modport source(input HADDR); endinterface diff --git a/test_regress/t/t_interface_ar2b.v b/test_regress/t/t_interface_ar2b.v index f715e7a47..d0a5f2618 100644 --- a/test_regress/t/t_interface_ar2b.v +++ b/test_regress/t/t_interface_ar2b.v @@ -6,30 +6,28 @@ module t; - sub sub [1] (); + sub sub[1] (); - ahb_slave_intf AHB_S[1](); + ahb_slave_intf AHB_S[1] (); - AHB_MEM uMEM(.S(AHB_S[0])); -// AHB_MEM uMEM(.S(AHB_S[0].source)); + AHB_MEM uMEM (.S(AHB_S[0])); + // AHB_MEM uMEM(.S(AHB_S[0].source)); endmodule module sub; endmodule -module AHB_MEM - ( - ahb_slave_intf.source S - ); +module AHB_MEM ( + ahb_slave_intf.source S +); endmodule -interface ahb_slave_intf - (); +interface ahb_slave_intf (); - logic [31:0] HADDR; + logic [31:0] HADDR; - modport source (input HADDR); + modport source(input HADDR); endinterface diff --git a/test_regress/t/t_interface_ar3.out b/test_regress/t/t_interface_ar3.out index bebabf4bb..7d55bb39e 100644 --- a/test_regress/t/t_interface_ar3.out +++ b/test_regress/t/t_interface_ar3.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_interface_ar3.v:16:36: Unsupported: interface slices +%Error-UNSUPPORTED: t/t_interface_ar3.v:18:18: Unsupported: interface slices : ... note: In instance 't' - 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); - | ^ + 18 | .infc(iinst[0:1]) + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Internal Error: t/t_interface_ar3.v:16:36: ../V3Inst.cpp:#: No interface varref under array +%Error: Internal Error: t/t_interface_ar3.v:18:18: ../V3Inst.cpp:#: No interface varref under array : ... note: In instance 't' - 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); - | ^ + 18 | .infc(iinst[0:1]) + | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_interface_ar3.v b/test_regress/t/t_interface_ar3.v index 8ea3beb1d..84e7b5047 100644 --- a/test_regress/t/t_interface_ar3.v +++ b/test_regress/t/t_interface_ar3.v @@ -5,62 +5,66 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input logic clk, - output logic HRESETn - ); + input logic clk, + output logic HRESETn +); - int primsig[3]; + int primsig[3]; - ahb_slave_intf iinst[3] (primsig[2:0]); + ahb_slave_intf iinst[3] (primsig[2:0]); - sub sub01 [2] (.clk, .infc(iinst[0:1])); - sub sub2 (.clk, .infc(iinst[2])); + sub sub01[2] ( + .clk, + .infc(iinst[0:1]) + ); + sub sub2 ( + .clk, + .infc(iinst[2]) + ); - initial begin - primsig[0] = 30; - primsig[1] = 31; - primsig[2] = 32; - iinst[0].data = 10; - iinst[1].data = 11; - iinst[2].data = 12; - end + initial begin + primsig[0] = 30; + primsig[1] = 31; + primsig[2] = 32; + iinst[0].data = 10; + iinst[1].data = 11; + iinst[2].data = 12; + end - int cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - if (iinst[0].primsig != 30) $stop; - if (iinst[1].primsig != 31) $stop; - if (iinst[2].primsig != 32) $stop; - if (iinst[0].data != 10) $stop; - if (iinst[1].data != 11) $stop; - if (iinst[2].data != 12) $stop; - if (sub01[0].internal != 10) $stop; - if (sub01[1].internal != 11) $stop; - if (sub2.internal != 12) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + if (iinst[0].primsig != 30) $stop; + if (iinst[1].primsig != 31) $stop; + if (iinst[2].primsig != 32) $stop; + if (iinst[0].data != 10) $stop; + if (iinst[1].data != 11) $stop; + if (iinst[2].data != 12) $stop; + if (sub01[0].internal != 10) $stop; + if (sub01[1].internal != 11) $stop; + if (sub2.internal != 12) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub -( - input logic clk, - ahb_slave_intf infc - ); +module sub ( + input logic clk, + ahb_slave_intf infc +); - int internal; + int internal; - always_comb internal = infc.data; + always_comb internal = infc.data; endmodule -interface ahb_slave_intf - ( +interface ahb_slave_intf ( input int primsig - ); +); - int data; + int data; endinterface diff --git a/test_regress/t/t_interface_array.v b/test_regress/t/t_interface_array.v index 1609aad05..4c15ab02e 100644 --- a/test_regress/t/t_interface_array.v +++ b/test_regress/t/t_interface_array.v @@ -5,76 +5,69 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - bit a; + bit a; - modport source ( - output a - ); + modport source(output a); - modport sink ( - input a - ); + modport sink(input a); endinterface -function integer identity (input integer val); - return val; +function integer identity(input integer val); + return val; endfunction -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + localparam N = 5; - localparam N = 5; + bit [N-1:0] a_in; + bit [N-1:0] a_out; + bit [N-1:0] ack_out; - bit [N-1:0] a_in; - bit [N-1:0] a_out; - bit [N-1:0] ack_out; + foo_intf foos[N-1:0] (); - foo_intf foos [N-1:0] (); + // Deferred link dotting with genvars + generate + genvar i; + for (i = 0; i < N - 4; i++) begin : someLoop + assign ack_out[i] = a_in[i]; + assign foos[i].a = a_in[i]; + assign a_out[i] = foos[i].a; + end + endgenerate - // Deferred link dotting with genvars - generate - genvar i; - for (i = 0; i < N-4; i++) begin : someLoop - assign ack_out[i] = a_in[i]; - assign foos[i].a = a_in[i]; - assign a_out[i] = foos[i].a; - end - endgenerate + // Defferred link dotting with localparam + localparam THE_LP = N - 3; + assign ack_out[THE_LP] = a_in[THE_LP]; + assign foos[THE_LP].a = a_in[THE_LP]; + assign a_out[THE_LP] = foos[THE_LP].a; - // Defferred link dotting with localparam - localparam THE_LP = N-3; - assign ack_out[THE_LP] = a_in[THE_LP]; - assign foos[THE_LP].a = a_in[THE_LP]; - assign a_out[THE_LP] = foos[THE_LP].a; + // Defferred link dotting with arithmetic expression + assign ack_out[N-2] = a_in[N-2]; + assign foos[N-2].a = a_in[N-2]; + assign a_out[N-2] = foos[N-2].a; - // Defferred link dotting with arithmetic expression - assign ack_out[N-2] = a_in[N-2]; - assign foos[N-2].a = a_in[N-2]; - assign a_out[N-2] = foos[N-2].a; + // Defferred link dotting with funcrefs + assign ack_out[identity(N-1)] = a_in[identity(N-1)]; + assign foos[identity(N-1)].a = a_in[identity(N-1)]; + assign a_out[identity(N-1)] = foos[identity(N-1)].a; - // Defferred link dotting with funcrefs - assign ack_out[identity(N-1)] = a_in[identity(N-1)]; - assign foos[identity(N-1)].a = a_in[identity(N-1)]; - assign a_out[identity(N-1)] = foos[identity(N-1)].a; + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + {{N - 1{1'b0}}, 1'b1}; - initial a_in = '0; - always @(posedge clk) begin - a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", ack_out, + a_out); + $stop; + end - if (ack_out != a_out) begin - $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", - ack_out, a_out); - $stop; - end - - if (& a_in) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (&a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_interface_array2.v b/test_regress/t/t_interface_array2.v index f2b7190e8..aa9afee7e 100644 --- a/test_regress/t/t_interface_array2.v +++ b/test_regress/t/t_interface_array2.v @@ -5,65 +5,66 @@ // SPDX-License-Identifier: CC0-1.0 interface intf; - logic logic_in_intf; - modport source(output logic_in_intf); - modport sink(input logic_in_intf); + logic logic_in_intf; + modport source(output logic_in_intf); + modport sink(input logic_in_intf); endinterface -module modify_interface -( -input logic value, -intf.source intf_inst +module modify_interface ( + input logic value, + intf.source intf_inst ); -assign intf_inst.logic_in_intf = value; + assign intf_inst.logic_in_intf = value; endmodule function integer return_3(); - return 3; + return 3; endfunction -module t -#( +module t #( parameter N = 6 -)(); - intf ifs[N-1:0] (); - logic [N-1:0] data; - assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}; +) (); + intf ifs[N-1:0] (); + logic [N-1:0] data; + assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}; - generate - genvar i; - for (i = 0;i < 3; i++) begin - assign ifs[i].logic_in_intf = data[i]; - end - endgenerate - // verilator lint_off SIDEEFFECT - modify_interface m3 ( - .value(data[return_3()]), - .intf_inst(ifs[return_3()])); - // verilator lint_on SIDEEFFECT - - modify_interface m4 ( - .value(data[4]), - .intf_inst(ifs[4])); - - modify_interface m5 ( - .value(~ifs[4].logic_in_intf), - .intf_inst(ifs[5])); - - generate - genvar j; - for (j = 0;j < N-1; j++) begin - initial begin - #1; - if (ifs[j].logic_in_intf != data[j]) $stop; - end - end - endgenerate - - initial begin - #1; - if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop; - $write("*-* All Finished *-*\n"); - $finish; + generate + genvar i; + for (i = 0; i < 3; i++) begin + assign ifs[i].logic_in_intf = data[i]; end + endgenerate + // verilator lint_off SIDEEFFECT + modify_interface m3 ( + .value(data[return_3()]), + .intf_inst(ifs[return_3()]) + ); + // verilator lint_on SIDEEFFECT + + modify_interface m4 ( + .value(data[4]), + .intf_inst(ifs[4]) + ); + + modify_interface m5 ( + .value(~ifs[4].logic_in_intf), + .intf_inst(ifs[5]) + ); + + generate + genvar j; + for (j = 0; j < N - 1; j++) begin + initial begin + #1; + if (ifs[j].logic_in_intf != data[j]) $stop; + end + end + endgenerate + + initial begin + #1; + if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_array3.v b/test_regress/t/t_interface_array3.v index e98b1e18a..fd552f3d2 100644 --- a/test_regress/t/t_interface_array3.v +++ b/test_regress/t/t_interface_array3.v @@ -5,50 +5,53 @@ // SPDX-License-Identifier: CC0-1.0 interface my_ifc (); - logic sig; - modport master ( output sig ); - modport slave ( input sig ); + logic sig; + modport master(output sig); + modport slave(input sig); endinterface package my_pkg; - typedef virtual my_ifc my_vif; - function void my_func; - input my_vif in_vif; - begin - in_vif.sig = 1'b1; - end - endfunction + typedef virtual my_ifc my_vif; + function void my_func; + input my_vif in_vif; + begin + in_vif.sig = 1'b1; + end + endfunction endpackage -module dut (input logic clk, my_ifc.slave sif[2]); - generate - genvar i; - for (i=0; i<2; i++) begin - always_ff @( posedge clk ) begin - if (sif[i].sig == 1'b1) $display("Hello World %0d", i); - end +module dut ( + input logic clk, + my_ifc.slave sif[2] +); + generate + genvar i; + for (i = 0; i < 2; i++) begin + always_ff @(posedge clk) begin + if (sif[i].sig == 1'b1) $display("Hello World %0d", i); end - endgenerate + end + endgenerate endmodule module t; - import my_pkg::*; + import my_pkg::*; - logic clk; - my_ifc sif[2] (); + logic clk; + my_ifc sif[2] (); - dut DUT (.*); + dut DUT (.*); - initial begin - clk = 0; - forever #(5) clk = ~clk; - end + initial begin + clk = 0; + forever #(5) clk = ~clk; + end - initial begin - repeat (4) @(posedge clk); - my_func(sif[0]); - my_func(sif[1]); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + repeat (4) @(posedge clk); + my_func(sif[0]); + my_func(sif[1]); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_array_bad.out b/test_regress/t/t_interface_array_bad.out index 657cf8efd..70d632635 100644 --- a/test_regress/t/t_interface_array_bad.out +++ b/test_regress/t/t_interface_array_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_interface_array_bad.v:23:16: Expecting expression to be constant, but variable isn't const: 'bar' +%Error: t/t_interface_array_bad.v:23:15: Expecting expression to be constant, but variable isn't const: 'bar' : ... note: In instance 't' - 23 | assign foos[bar].a = 1'b1; - | ^~~ + 23 | assign foos[bar].a = 1'b1; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_array_bad.v:23:15: Could not expand constant selection inside dotted reference: 'bar' +%Error: t/t_interface_array_bad.v:23:14: Could not expand constant selection inside dotted reference: 'bar' : ... note: In instance 't' - 23 | assign foos[bar].a = 1'b1; - | ^ + 23 | assign foos[bar].a = 1'b1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_bad.v b/test_regress/t/t_interface_array_bad.v index 9806c54f7..4064f297d 100644 --- a/test_regress/t/t_interface_array_bad.v +++ b/test_regress/t/t_interface_array_bad.v @@ -5,50 +5,50 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - logic a; + logic a; endinterface -function integer the_other_func (input integer val); - return val; +function integer the_other_func(input integer val); + return val; endfunction module t; - localparam N = 4; + localparam N = 4; - foo_intf foos [N-1:0] (); - logic [ 7 : 0 ] bar; + foo_intf foos[N-1:0] (); + logic [7 : 0] bar; - // Non-constant dotted select is not allowed - assign foos[bar].a = 1'b1; + // Non-constant dotted select is not allowed + assign foos[bar].a = 1'b1; - baz baz_inst (); + baz baz_inst (); - // Unsure how to produce V3Param AstCellRef visitor errors - //assign baz_inst.x = 1'b1; - //assign baz_inst.N = 1'b1; - //assign baz_inst.7 = 1'b1; - //assign baz_inst.qux_t = 1'b1; - //assign baz_inst.the_func = 1'b1; - //assign baz_inst.THE_LP = 1'b1; + // Unsure how to produce V3Param AstCellRef visitor errors + //assign baz_inst.x = 1'b1; + //assign baz_inst.N = 1'b1; + //assign baz_inst.7 = 1'b1; + //assign baz_inst.qux_t = 1'b1; + //assign baz_inst.the_func = 1'b1; + //assign baz_inst.THE_LP = 1'b1; - //assign bar.x = 1'b1; - //assign fake_inst.x = 1'b1; - //assign the_other_func.x = 1'b1; + //assign bar.x = 1'b1; + //assign fake_inst.x = 1'b1; + //assign the_other_func.x = 1'b1; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module baz; - typedef integer qux_t; + typedef integer qux_t; - function integer the_func (input integer val); - return val; - endfunction + function integer the_func(input integer val); + return val; + endfunction - localparam THE_LP = 5; + localparam THE_LP = 5; endmodule diff --git a/test_regress/t/t_interface_array_modport.v b/test_regress/t/t_interface_array_modport.v index 883bec0f4..2525ce2d8 100644 --- a/test_regress/t/t_interface_array_modport.v +++ b/test_regress/t/t_interface_array_modport.v @@ -5,37 +5,34 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - logic a; + logic a; - modport m(input a); + modport m(input a); endinterface -module foo_mod - ( - foo_intf foo, - foo_intf.m bars[4] - ); +module foo_mod ( + foo_intf foo, + foo_intf.m bars[4] +); endmodule module t; - localparam N = 4; + localparam N = 4; - foo_intf foos [N-1:0] (); - foo_intf bars [N] (); - //foo_intf foos (); + foo_intf foos[N-1:0] (); + foo_intf bars[N] (); + //foo_intf foos (); - foo_mod - foo_mod - ( - .foo (foos[2]), - .bars (bars) - //.foo (foos) - ); + foo_mod foo_mod ( + .foo(foos[2]), + .bars(bars) + //.foo (foos) + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index cce609d06..a5af54af4 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -4,67 +4,65 @@ // SPDX-FileCopyrightText: 2017 Mike Popoloski // SPDX-License-Identifier: CC0-1.0 -interface foo_intf - ( - input x - ); +interface foo_intf ( + input x +); endinterface -module foo_subm - ( - input x - ); +module foo_subm ( + input x +); endmodule module t; - localparam N = 3; + localparam N = 3; - wire [2:0] X = 3'b110; + wire [2:0] X = 3'b110; - // Should not cause ASCRANGE warning, as no harm in array selections. - // verilator lint_on ASCRANGE - foo_intf foo1 [N] (.x(1'b1)); - foo_subm sub1 [N] (.x(1'b1)); + // Should not cause ASCRANGE warning, as no harm in array selections. + // verilator lint_on ASCRANGE + foo_intf foo1[N] (.x(1'b1)); + foo_subm sub1[N] (.x(1'b1)); - // Will cause ASCRANGE warning? - // verilator lint_off ASCRANGE - foo_intf foos [N] (.x(X)); - foo_intf fool [1:3] (.x(X)); - foo_intf foom [3:1] (.x(X)); + // Will cause ASCRANGE warning? + // verilator lint_off ASCRANGE + foo_intf foos[N] (.x(X)); + foo_intf fool[1:3] (.x(X)); + foo_intf foom[3:1] (.x(X)); - foo_subm subs [N] (.x(X)); - foo_subm subl [1:3] (.x(X)); - foo_subm subm [3:1] (.x(X)); + foo_subm subs[N] (.x(X)); + foo_subm subl[1:3] (.x(X)); + foo_subm subm[3:1] (.x(X)); - initial begin - // Check numbering with 0 first - // NC has a bug here - if (foos[0].x !== 1'b1) $stop; - if (foos[1].x !== 1'b1) $stop; - if (foos[2].x !== 1'b0) $stop; - // - if (fool[1].x !== 1'b1) $stop; - if (fool[2].x !== 1'b1) $stop; - if (fool[3].x !== 1'b0) $stop; - // - if (foom[1].x !== 1'b0) $stop; - if (foom[2].x !== 1'b1) $stop; - if (foom[3].x !== 1'b1) $stop; - // - if (subs[0].x !== 1'b1) $stop; - if (subs[1].x !== 1'b1) $stop; - if (subs[2].x !== 1'b0) $stop; - // - if (subl[1].x !== 1'b1) $stop; - if (subl[2].x !== 1'b1) $stop; - if (subl[3].x !== 1'b0) $stop; - // - if (subm[1].x !== 1'b0) $stop; - if (subm[2].x !== 1'b1) $stop; - if (subm[3].x !== 1'b1) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Check numbering with 0 first + // NC has a bug here + if (foos[0].x !== 1'b1) $stop; + if (foos[1].x !== 1'b1) $stop; + if (foos[2].x !== 1'b0) $stop; + // + if (fool[1].x !== 1'b1) $stop; + if (fool[2].x !== 1'b1) $stop; + if (fool[3].x !== 1'b0) $stop; + // + if (foom[1].x !== 1'b0) $stop; + if (foom[2].x !== 1'b1) $stop; + if (foom[3].x !== 1'b1) $stop; + // + if (subs[0].x !== 1'b1) $stop; + if (subs[1].x !== 1'b1) $stop; + if (subs[2].x !== 1'b0) $stop; + // + if (subl[1].x !== 1'b1) $stop; + if (subl[2].x !== 1'b1) $stop; + if (subl[3].x !== 1'b0) $stop; + // + if (subm[1].x !== 1'b0) $stop; + if (subm[2].x !== 1'b1) $stop; + if (subm[3].x !== 1'b1) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index efeba5432..6157cc4be 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -1,19 +1,19 @@ -%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:26:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:24:24: Ascending instance range connecting to vector: left < right of instance range: [0:2] : ... note: In instance 't' - 26 | foo_intf foos [N] (.x(X)); - | ^ + 24 | foo_intf foos[N] (.x(X)); + | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. -%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:27:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:25:26: Ascending instance range connecting to vector: left < right of instance range: [1:3] : ... note: In instance 't' - 27 | foo_intf fool [1:3] (.x(X)); - | ^ -%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:30:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] - : ... note: In instance 't' - 30 | foo_subm subs [N] (.x(X)); + 25 | foo_intf fool[1:3] (.x(X)); | ^ -%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:31:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:28:24: Ascending instance range connecting to vector: left < right of instance range: [0:2] : ... note: In instance 't' - 31 | foo_subm subl [1:3] (.x(X)); - | ^ + 28 | foo_subm subs[N] (.x(X)); + | ^ +%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:29:26: Ascending instance range connecting to vector: left < right of instance range: [1:3] + : ... note: In instance 't' + 29 | foo_subm subl[1:3] (.x(X)); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index b88110bfe..1cecb8ea3 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -4,30 +4,28 @@ // SPDX-FileCopyrightText: 2017 Mike Popoloski // SPDX-License-Identifier: CC0-1.0 -interface foo_intf - ( - input x - ); +interface foo_intf ( + input x +); endinterface -module foo_subm - ( - input x - ); +module foo_subm ( + input x +); endmodule module t; - localparam N = 3; + localparam N = 3; - wire [2:0] X = 3'b110; + wire [2:0] X = 3'b110; - // Will cause ASCRANGE warning? - foo_intf foos [N] (.x(X)); // bad - foo_intf fool [1:3] (.x(X)); // bad - foo_intf foom [3:1] (.x(X)); // ok + // Will cause ASCRANGE warning? + foo_intf foos[N] (.x(X)); // bad + foo_intf fool[1:3] (.x(X)); // bad + foo_intf foom[3:1] (.x(X)); // ok - foo_subm subs [N] (.x(X)); // bad - foo_subm subl [1:3] (.x(X)); // bad - foo_subm subm [3:1] (.x(X)); // ok + foo_subm subs[N] (.x(X)); // bad + foo_subm subl[1:3] (.x(X)); // bad + foo_subm subm[3:1] (.x(X)); // ok endmodule diff --git a/test_regress/t/t_interface_array_parameter_access.v b/test_regress/t/t_interface_array_parameter_access.v index 489efbf8b..06ce45529 100644 --- a/test_regress/t/t_interface_array_parameter_access.v +++ b/test_regress/t/t_interface_array_parameter_access.v @@ -4,40 +4,44 @@ // SPDX-FileCopyrightText: 2024 Todd Strader // SPDX-License-Identifier: CC0-1.0 -interface intf - #(parameter int FOO = 4) - (input wire clk, - input wire rst); - modport modp (input clk, rst); +interface intf #( + parameter int FOO = 4 +) ( + input wire clk, + input wire rst +); + modport modp(input clk, rst); endinterface -module sub (intf.modp the_intf_port [4], intf.modp single_intf_port); - localparam intf_foo = the_intf_port[0].FOO; - localparam single_foo = single_intf_port.FOO; +module sub ( + intf.modp the_intf_port[4], + intf.modp single_intf_port +); + localparam intf_foo = the_intf_port[0].FOO; + localparam single_foo = single_intf_port.FOO; - initial begin - if (intf_foo != 4) $stop; - if (single_foo != 4) $stop; - end + initial begin + if (intf_foo != 4) $stop; + if (single_foo != 4) $stop; + end endmodule module t ( clk ); - logic rst; - input clk; + logic rst; + input clk; - intf the_intf [4] (.*); - intf single_intf (.*); + intf the_intf[4] (.*); + intf single_intf (.*); - sub - the_sub ( - .the_intf_port (the_intf), - .single_intf_port(single_intf) - ); + sub the_sub ( + .the_intf_port(the_intf), + .single_intf_port(single_intf) + ); - always @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_arraymux.v b/test_regress/t/t_interface_arraymux.v index 06e970d71..5b6ece68a 100644 --- a/test_regress/t/t_interface_arraymux.v +++ b/test_regress/t/t_interface_arraymux.v @@ -5,141 +5,137 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef logic [31:0] unique_id_t; - typedef struct packed { - unique_id_t foo; - } inner_thing_t; - typedef struct packed { - inner_thing_t bar; - inner_thing_t baz; - } outer_thing_t; + typedef logic [31:0] unique_id_t; + typedef struct packed {unique_id_t foo;} inner_thing_t; + typedef struct packed { + inner_thing_t bar; + inner_thing_t baz; + } outer_thing_t; endpackage import pkg::*; -interface the_intf - #(parameter M=5); - outer_thing_t [M-1:0] things; - logic valid; - modport i ( - output things, - output valid); - modport t ( - input things, - input valid); +interface the_intf #( + parameter M = 5 +); + outer_thing_t [M-1:0] things; + logic valid; + modport i(output things, output valid); + modport t(input things, input valid); endinterface -module ThingMuxOH - #( +module ThingMuxOH #( parameter NTHINGS = 1, - parameter M = 5 ) - ( + parameter M = 5 +) ( input logic [NTHINGS-1:0] select_oh, - the_intf.t things_in [NTHINGS-1:0], + the_intf.t things_in[NTHINGS-1:0], the_intf.i thing_out - ); - assign thing_out.valid = things_in[0].valid; +); + assign thing_out.valid = things_in[0].valid; endmodule -module ThingMuxShort - #( +module ThingMuxShort #( parameter NTHINGS = 1, - parameter M = 5 ) - ( + parameter M = 5 +) ( input logic [NTHINGS-1:0] select_oh, - the_intf.t things_in [NTHINGS], + the_intf.t things_in[NTHINGS], the_intf.i thing_out - ); - assign thing_out.valid = things_in[0].valid; +); + assign thing_out.valid = things_in[0].valid; endmodule -module Thinker - #( +module Thinker #( parameter M = 5, - parameter N = 2) - ( + parameter N = 2 +) ( input logic clk, input logic reset, - input unique_id_t uids[0:N-1], + input unique_id_t uids[0:N-1], the_intf.t thing_inp, the_intf.i thing_out - ); +); - the_intf #(.M(M)) curr_things [N-1:0] (); - the_intf #(.M(M)) prev_things [N-1:0] (); - the_intf #(.M(M)) s_things [N] (); - the_intf #(.M(M)) curr_thing (); - the_intf #(.M(M)) prev_thing (); - the_intf #(.M(M)) s_thing (); + the_intf #(.M(M)) curr_things[N-1:0] (); + the_intf #(.M(M)) prev_things[N-1:0] (); + the_intf #(.M(M)) s_things[N] (); + the_intf #(.M(M)) curr_thing (); + the_intf #(.M(M)) prev_thing (); + the_intf #(.M(M)) s_thing (); - logic [N-1:0] select_oh; + logic [N-1:0] select_oh; - // 1st mux: - ThingMuxOH #( - .NTHINGS ( N ), - .M ( M )) - curr_thing_mux( - .select_oh( select_oh ), - .things_in( curr_things ), - .thing_out( curr_thing )); + // 1st mux: + ThingMuxOH #( + .NTHINGS(N), + .M(M) + ) curr_thing_mux ( + .select_oh(select_oh), + .things_in(curr_things), + .thing_out(curr_thing) + ); - // 2nd mux, comment this out and no problem: - ThingMuxOH #( - .NTHINGS ( N ), - .M ( M )) - prev_thing_mux( - .select_oh( select_oh ), - .things_in( prev_things ), - .thing_out( prev_thing )); + // 2nd mux, comment this out and no problem: + ThingMuxOH #( + .NTHINGS(N), + .M(M) + ) prev_thing_mux ( + .select_oh(select_oh), + .things_in(prev_things), + .thing_out(prev_thing) + ); - // 3rd mux, using short array nomenclature: - ThingMuxShort #( - .NTHINGS ( N ), - .M ( M )) - s_thing_mux( - .select_oh( select_oh ), - .things_in( s_things ), - .thing_out( s_thing )); + // 3rd mux, using short array nomenclature: + ThingMuxShort #( + .NTHINGS(N), + .M(M) + ) s_thing_mux ( + .select_oh(select_oh), + .things_in(s_things), + .thing_out(s_thing) + ); endmodule -module t - ( - input logic clk, - input logic reset - ); +module t ( + input logic clk, + input logic reset +); - localparam M = 5; - localparam N = 2; + localparam M = 5; + localparam N = 2; - unique_id_t uids[0:N-1]; + unique_id_t uids[0:N-1]; - the_intf #(.M(M)) thing_inp(); - the_intf #(.M(M)) thing_out(); + the_intf #(.M(M)) thing_inp (); + the_intf #(.M(M)) thing_out (); - Thinker #( - .M ( M ), - .N ( N )) - thinker( - .clk ( clk ), - .reset ( reset ), - .uids ( uids ), - .thing_inp( thing_inp ), - .thing_out( thing_out )); + Thinker #( + .M(M), + .N(N) + ) thinker ( + .clk(clk), + .reset(reset), + .uids(uids), + .thing_inp(thing_inp), + .thing_out(thing_out) + ); - // Previously there was a problem in V3Inst if non-default parameters was used - localparam K = 2; - the_intf #(.M(K)) thing_inp2(); - the_intf #(.M(K)) thing_out2(); + // Previously there was a problem in V3Inst if non-default parameters was used + localparam K = 2; + the_intf #(.M(K)) thing_inp2 (); + the_intf #(.M(K)) thing_out2 (); - Thinker #( - .M ( K ), - .N ( N )) - thinker2( - .clk ( clk ), - .reset ( reset ), - .uids ( uids ), - .thing_inp( thing_inp2 ), - .thing_out( thing_out2 )); + Thinker #( + .M(K), + .N(N) + ) thinker2 ( + .clk(clk), + .reset(reset), + .uids(uids), + .thing_inp(thing_inp2), + .thing_out(thing_out2) + ); endmodule diff --git a/test_regress/t/t_interface_asvar_bad.out b/test_regress/t/t_interface_asvar_bad.out index e5f12840a..4b60044a0 100644 --- a/test_regress/t/t_interface_asvar_bad.out +++ b/test_regress/t/t_interface_asvar_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_interface_asvar_bad.v:29:16: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. +%Error: t/t_interface_asvar_bad.v:26:14: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. : ... note: In instance 't.source' - 29 | getter = itf; - | ^~~ + 26 | getter = itf; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_asvar_bad.v:30:23: Operator ADD expected non-interface on RHS but 'itf' is an interface. +%Error: t/t_interface_asvar_bad.v:27:21: Operator ADD expected non-interface on RHS but 'itf' is an interface. : ... note: In instance 't.source' - 30 | getter = 4'd3 + itf; - | ^~~ + 27 | getter = 4'd3 + itf; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_asvar_bad.v b/test_regress/t/t_interface_asvar_bad.v index 868905f34..198e9cf35 100644 --- a/test_regress/t/t_interface_asvar_bad.v +++ b/test_regress/t/t_interface_asvar_bad.v @@ -6,28 +6,25 @@ module t; - counter_if iface(); + counter_if iface (); - source source ( - .itf (iface) - ); + source source (.itf(iface)); endmodule interface counter_if; - logic [3:0] value; + logic [3:0] value; endinterface -module source - ( - counter_if itf - ); +module source ( + counter_if itf +); - logic [3:0] getter; + logic [3:0] getter; - initial begin - getter = itf; // Intended to write itf.value - getter = 4'd3 + itf; // Intended to write itf.value - end + initial begin + getter = itf; // Intended to write itf.value + getter = 4'd3 + itf; // Intended to write itf.value + end endmodule diff --git a/test_regress/t/t_interface_bind_public.v b/test_regress/t/t_interface_bind_public.v index 1312a477d..5f00a21ed 100644 --- a/test_regress/t/t_interface_bind_public.v +++ b/test_regress/t/t_interface_bind_public.v @@ -4,118 +4,112 @@ // SPDX-FileCopyrightText: 2018 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 -interface hex2ram_if - ( - input bit trigger - ); +interface hex2ram_if ( + input bit trigger +); - string instance_path = $sformatf("%m"); - string testfile = ""; - bit has_testfile = |($value$plusargs("testfile=%s", testfile)); - bit armed = 1'b1; - bit armed_trigger; + string instance_path = $sformatf("%m"); + string testfile = ""; + bit has_testfile = |($value$plusargs("testfile=%s", testfile)); + bit armed = 1'b1; + bit armed_trigger; - initial begin - $display("successfully bound hex2ram_if to %s", instance_path); - armed = has_testfile && 1'b1; - end + initial begin + $display("successfully bound hex2ram_if to %s", instance_path); + armed = has_testfile && 1'b1; + end - assign armed_trigger = armed && trigger; + assign armed_trigger = armed && trigger; - always @(posedge armed_trigger) begin - $display("%m(%0t): saw deassertion of reset", $time); - end + always @(posedge armed_trigger) begin + $display("%m(%0t): saw deassertion of reset", $time); + end endinterface : hex2ram_if -module t - ( - clk - ); +module t ( + input clk +); - input clk; - bit reset; + bit reset; - wire success; - SimpleTestHarness testHarness - ( + wire success; + SimpleTestHarness testHarness ( .clk(clk), .reset(reset), .io_success(success) - ); + ); - integer cyc = 0; + integer cyc = 0; - always @ (posedge clk) begin - cyc = cyc + 1; - if (cyc<10) begin - reset <= '0; - end - else if (cyc<20) begin - reset <= '1; - end - else if (cyc<30) begin - reset <= '0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc = cyc + 1; + if (cyc < 10) begin + reset <= '0; + end + else if (cyc < 20) begin + reset <= '1; + end + else if (cyc < 30) begin + reset <= '0; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset)); +bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset)); -module testharness_ext - ( - input W0_clk, - input [24:0] W0_addr, - input W0_en, - input [127:0] W0_data, - input [0:0] W0_mask, - input R0_clk, - input [24:0] R0_addr, - input R0_en, - output [127:0] R0_data - ); +module testharness_ext ( + input W0_clk, + input [24:0] W0_addr, + input W0_en, + input [127:0] W0_data, + input [0:0] W0_mask, + input R0_clk, + input [24:0] R0_addr, + input R0_en, + output [127:0] R0_data +); - reg [24:0] reg_R0_addr; - wire [127:0] R0_rdata_mask; - reg [127:0] ram [33554431:0]; - wire [127:0] W0_wdata_mask; + reg [24:0] reg_R0_addr; + wire [127:0] R0_rdata_mask; + reg [127:0] ram[33554431:0]; + wire [127:0] W0_wdata_mask; - always @(posedge R0_clk) - if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge R0_clk) if (R0_en) reg_R0_addr <= R0_addr; - always @(posedge W0_clk) - if (W0_en) begin - if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask; - end - assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;; - assign R0_rdata_mask = 0; - assign W0_wdata_mask = 0; + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask; + end + assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask; + ; + assign R0_rdata_mask = 0; + assign W0_wdata_mask = 0; endmodule -module SimpleTestHarness - ( - input clk, - input reset, - output io_success); +module SimpleTestHarness ( + input clk, + input reset, + output io_success +); - wire [24:0] testharness_ext_R0_addr; - wire testharness_ext_R0_en; - wire testharness_ext_R0_clk; - wire [127:0] testharness_ext_R0_data; - wire [24:0] testharness_ext_W0_addr; - wire testharness_ext_W0_en; - wire testharness_ext_W0_clk; - wire [127:0] testharness_ext_W0_data; - wire [0:0] testharness_ext_W0_mask; + wire [24:0] testharness_ext_R0_addr; + wire testharness_ext_R0_en; + wire testharness_ext_R0_clk; + wire [127:0] testharness_ext_R0_data; + wire [24:0] testharness_ext_W0_addr; + wire testharness_ext_W0_en; + wire testharness_ext_W0_clk; + wire [127:0] testharness_ext_W0_data; + wire [0:0] testharness_ext_W0_mask; - testharness_ext testharness_ext - ( + testharness_ext testharness_ext ( .R0_addr(testharness_ext_R0_addr), .R0_en(testharness_ext_R0_en), .R0_clk(testharness_ext_R0_clk), @@ -125,6 +119,6 @@ module SimpleTestHarness .W0_clk(testharness_ext_W0_clk), .W0_data(testharness_ext_W0_data), .W0_mask(testharness_ext_W0_mask) - ); + ); endmodule diff --git a/test_regress/t/t_interface_colon_bad.out b/test_regress/t/t_interface_colon_bad.out index 8479b85bf..5024e24e9 100644 --- a/test_regress/t/t_interface_colon_bad.out +++ b/test_regress/t/t_interface_colon_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_colon_bad.v:14:7: Package/class for ':: reference' not found: 'iface' - 14 | iface::func(); - | ^~~~~ +%Error: t/t_interface_colon_bad.v:14:5: Package/class for ':: reference' not found: 'iface' + 14 | iface::func(); + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_colon_bad.v b/test_regress/t/t_interface_colon_bad.v index a202e8574..283d58dc9 100644 --- a/test_regress/t/t_interface_colon_bad.v +++ b/test_regress/t/t_interface_colon_bad.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 interface iface; - function static func; - endfunction + function static func; + endfunction endinterface module t; - initial begin - iface::func(); // BAD - $stop; - end + initial begin + iface::func(); // BAD + $stop; + end endmodule diff --git a/test_regress/t/t_interface_dearray.v b/test_regress/t/t_interface_dearray.v index 88f355664..1cfee02b3 100644 --- a/test_regress/t/t_interface_dearray.v +++ b/test_regress/t/t_interface_dearray.v @@ -16,44 +16,44 @@ class B; endclass class C; - a_array_t vif; + a_array_t vif; - function void set(int index, a_t iface); - vif[index] = iface; - endfunction + function void set(int index, a_t iface); + vif[index] = iface; + endfunction endclass -module tb_top(); - A a[6](); - C c, d, e; - a_array_t g; +module tb_top (); + A a[6] (); + C c, d, e; + a_array_t g; - initial begin - static a_t aa = a[0]; + initial begin + static a_t aa = a[0]; - automatic B b = new(a[0]); + automatic B b = new(a[0]); - c = new(); - c.vif = a; + c = new(); + c.vif = a; - d = new(); - d.set(0, a[0]); - d.vif[1] = a[1]; + d = new(); + d.set(0, a[0]); + d.vif[1] = a[1]; - g[0] = a[0]; - g = a; + g[0] = a[0]; + g = a; - d.vif[0] = g[0]; - d.vif = g; + d.vif[0] = g[0]; + d.vif = g; - e = new(); + e = new(); - for (int i = 0; i < 6; ++i) begin - e.vif[i] = g[i]; - end + for (int i = 0; i < 6; ++i) begin + e.vif[i] = g[i]; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_dearray_bad.out b/test_regress/t/t_interface_dearray_bad.out index 143493309..7624661c7 100644 --- a/test_regress/t/t_interface_dearray_bad.out +++ b/test_regress/t/t_interface_dearray_bad.out @@ -1,27 +1,27 @@ -%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:23:9: Unexpected target of interface assignment ['IFACEREFDTYPE$[0:5]'] +%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:23:7: Unexpected target of interface assignment ['IFACEREFDTYPE$[0:5]'] : ... note: In instance 'tb_top' - 23 | a = f; - | ^ + 23 | a = f; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:26:13: Array size mismatch in interface assignment +%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:26:11: Array size mismatch in interface assignment : ... note: In instance 'tb_top' - 26 | c.vif = b; - | ^ -%Error: t/t_interface_dearray_bad.v:31:23: Expecting expression to be constant, but variable isn't const: 'i' - : ... note: In instance 'tb_top' - 31 | d.vif[i] = a[i]; - | ^ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:31:23: Non-constant index in RHS interface array selection - : ... note: In instance 'tb_top' - 31 | d.vif[i] = a[i]; - | ^ -%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:35:16: Interface slices unsupported - : ... note: In instance 'tb_top' - 35 | e.vif = b[0:5]; - | ^ -%Error: Internal Error: t/t_interface_dearray_bad.v:23:11: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:# - : ... note: In instance 'tb_top' - 23 | a = f; + 26 | c.vif = b; | ^ +%Error: t/t_interface_dearray_bad.v:31:20: Expecting expression to be constant, but variable isn't const: 'i' + : ... note: In instance 'tb_top' + 31 | d.vif[i] = a[i]; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:31:20: Non-constant index in RHS interface array selection + : ... note: In instance 'tb_top' + 31 | d.vif[i] = a[i]; + | ^ +%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:35:14: Interface slices unsupported + : ... note: In instance 'tb_top' + 35 | e.vif = b[0:5]; + | ^ +%Error: Internal Error: t/t_interface_dearray_bad.v:23:9: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:# + : ... note: In instance 'tb_top' + 23 | a = f; + | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_interface_dearray_bad.v b/test_regress/t/t_interface_dearray_bad.v index 93e2f20fc..1cf7692f8 100644 --- a/test_regress/t/t_interface_dearray_bad.v +++ b/test_regress/t/t_interface_dearray_bad.v @@ -11,31 +11,31 @@ typedef virtual A a_t; typedef a_t a_array_t[6]; class C; - a_array_t vif; + a_array_t vif; endclass -module tb_top(); - A a[6](), b[7](), f[6](); - C c, d, e; - a_array_t g; +module tb_top (); + A a[6] (), b[7] (), f[6] (); + C c, d, e; + a_array_t g; - initial begin - a = f; + initial begin + a = f; - c = new(); - c.vif = b; + c = new(); + c.vif = b; - d = new(); + d = new(); - for (int i = 0; i < 6; ++i) begin - d.vif[i] = a[i]; - end + for (int i = 0; i < 6; ++i) begin + d.vif[i] = a[i]; + end - e = new(); - e.vif = b[0:5]; + e = new(); + e.vif = b[0:5]; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_derived_type.v b/test_regress/t/t_interface_derived_type.v index 7732ab714..da1f17d87 100644 --- a/test_regress/t/t_interface_derived_type.v +++ b/test_regress/t/t_interface_derived_type.v @@ -8,35 +8,41 @@ interface intf #( parameter type data_t = bit, parameter int arr[2][4] ) (); - data_t data; - // TODO -- some kind of issue with multi-dimensional array constness: - // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' - // : ... note: In instance 't.sub16' - // 19 | logic [arr[0][0]-1:0] other_data; - // | ^~~ - // `define SHOW_2D_BUG - `ifdef SHOW_2D_BUG - logic [arr[0][0]-1:0] other_data; - `else - logic [$bits(data)-1:0] other_data; - `endif + data_t data; + // TODO -- some kind of issue with multi-dimensional array constness: + // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' + // : ... note: In instance 't.sub16' + // 19 | logic [arr[0][0]-1:0] other_data; + // | ^~~ + // `define SHOW_2D_BUG +`ifdef SHOW_2D_BUG + logic [arr[0][0]-1:0] other_data; +`else + logic [$bits(data)-1:0] other_data; +`endif endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; + input clk; - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); - sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); + sub #( + .width(16), + .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub16 (); endmodule @@ -44,19 +50,17 @@ module sub #( parameter int width, parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; - intf #( - .data_t(user_type_t), - .arr(arr) - ) the_intf (); + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); - logic [width-1:0] signal; + logic [width-1:0] signal; - always_comb begin - the_intf.data.field = signal; - the_intf.other_data = signal; - end + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end endmodule diff --git a/test_regress/t/t_interface_down.v b/test_regress/t/t_interface_down.v index da941c14b..4397a538a 100644 --- a/test_regress/t/t_interface_down.v +++ b/test_regress/t/t_interface_down.v @@ -5,69 +5,76 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - integer value; + integer value; endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); -`ifdef INLINE_A //verilator inline_module +module t ( + input clk +); +`ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif - input clk; - integer cyc=1; - ifc itop1a(); - ifc itop1b(); - ifc itop2a(); - ifc itop2b(); + integer cyc = 1; - wrapper c1 (.isuba(itop1a), - .isubb(itop1b), - .i_valuea(14), - .i_valueb(15)); - wrapper c2 (.isuba(itop2a), - .isubb(itop2b), - .i_valuea(24), - .i_valueb(25)); + ifc itop1a (); + ifc itop1b (); + ifc itop2a (); + ifc itop2b (); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (itop1a.value != 14) $stop; - if (itop1b.value != 15) $stop; - if (itop2a.value != 24) $stop; - if (itop2b.value != 25) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + wrapper c1 ( + .isuba(itop1a), + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15) + ); + wrapper c2 ( + .isuba(itop2a), + .isubb(itop2b), + .i_valuea(24), + .i_valueb(25) + ); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + if (itop2a.value != 24) $stop; + if (itop2b.value != 25) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module wrapper - ( - ifc isuba, - ifc isubb, - input integer i_valuea, - input integer i_valueb - ); -`ifdef INLINE_B //verilator inline_module +module wrapper ( + ifc isuba, + ifc isubb, + input integer i_valuea, + input integer i_valueb +); +`ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif - lower subsuba (.isub(isuba), .i_value(i_valuea)); - lower subsubb (.isub(isubb), .i_value(i_valueb)); + lower subsuba ( + .isub(isuba), + .i_value(i_valuea) + ); + lower subsubb ( + .isub(isubb), + .i_value(i_valueb) + ); endmodule -module lower - ( - ifc isub, - input integer i_value - ); -`ifdef INLINE_C //verilator inline_module +module lower ( + ifc isub, + input integer i_value +); +`ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif - always @* begin - isub.value = i_value; - end + always @* begin + isub.value = i_value; + end endmodule diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v index dfa2897f8..14f74ce0d 100644 --- a/test_regress/t/t_interface_dups.v +++ b/test_regress/t/t_interface_dups.v @@ -4,165 +4,168 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [4:0] din_data = crc[4:0]; - wire [0:0] din_valid = crc[6]; - wire [0:0] dout0_ready = crc[16]; - wire [0:0] dout1_ready = crc[17]; - wire [0:0] dout2_ready = crc[18]; + // Take CRC data and apply to testblock inputs + wire [4:0] din_data = crc[4:0]; + wire [0:0] din_valid = crc[6]; + wire [0:0] dout0_ready = crc[16]; + wire [0:0] dout1_ready = crc[17]; + wire [0:0] dout2_ready = crc[18]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic din_ready; // From test of Test.v - logic [0:0] dout0_data; // From test of Test.v - logic dout0_valid; // From test of Test.v - logic [1:0] dout1_data; // From test of Test.v - logic dout1_valid; // From test of Test.v - logic [2:0] dout2_data; // From test of Test.v - logic dout2_valid; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic din_ready; // From test of Test.v + logic [0:0] dout0_data; // From test of Test.v + logic dout0_valid; // From test of Test.v + logic [1:0] dout1_data; // From test of Test.v + logic dout1_valid; // From test of Test.v + logic [2:0] dout2_data; // From test of Test.v + logic dout2_valid; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .din_ready (din_ready), - .dout0_valid (dout0_valid), - .dout0_data (dout0_data[0:0]), - .dout1_valid (dout1_valid), - .dout1_data (dout1_data[1:0]), - .dout2_valid (dout2_valid), - .dout2_data (dout2_data[2:0]), - // Inputs - .din_valid (din_valid), - .din_data (din_data[4:0]), - .dout0_ready (dout0_ready), - .dout1_ready (dout1_ready), - .dout2_ready (dout2_ready)); + Test test ( /*AUTOINST*/ + // Outputs + .din_ready(din_ready), + .dout0_valid(dout0_valid), + .dout0_data(dout0_data[0:0]), + .dout1_valid(dout1_valid), + .dout1_data(dout1_data[1:0]), + .dout2_valid(dout2_valid), + .dout2_data(dout2_data[2:0]), + // Inputs + .din_valid(din_valid), + .din_data(din_data[4:0]), + .dout0_ready(dout0_ready), + .dout1_ready(dout1_ready), + .dout2_ready(dout2_ready) + ); - // Aggregate outputs into a single result vector - wire [63:0] result = {48'h0, din_ready, - 2'd0, dout2_valid, dout2_data, - 2'd0, dout1_valid, dout1_data, - 2'd0, dout0_valid, dout0_data}; + // Aggregate outputs into a single result vector + wire [63:0] result = { + 48'h0, + din_ready, + 2'd0, + dout2_valid, + dout2_data, + 2'd0, + dout1_valid, + dout1_data, + 2'd0, + dout0_valid, + dout0_data + }; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h6fd1bead9df31b07 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h6fd1bead9df31b07 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -interface dti - #(W_DATA = 64 - )(); +interface dti #( + W_DATA = 64 +) (); - logic [W_DATA-1:0] data; - logic valid; - logic ready; + logic [W_DATA-1:0] data; + logic valid; + logic ready; - modport producer (output data, - output valid, - input ready); - modport consumer (input data, - input valid, - output ready); + modport producer(output data, output valid, input ready); + modport consumer(input data, input valid, output ready); endinterface : dti -module Test - ( - output logic din_ready, - input logic din_valid, - input logic [4:0] din_data, - input logic dout0_ready, - output logic dout0_valid, - output logic [0:0] dout0_data, - input logic dout1_ready, - output logic dout1_valid, - output logic [1:0] dout1_data, - input logic dout2_ready, - output logic dout2_valid, - output logic [2:0] dout2_data - ); +module Test ( + output logic din_ready, + input logic din_valid, + input logic [4:0] din_data, + input logic dout0_ready, + output logic dout0_valid, + output logic [0:0] dout0_data, + input logic dout1_ready, + output logic dout1_valid, + output logic [1:0] dout1_data, + input logic dout2_ready, + output logic dout2_valid, + output logic [2:0] dout2_data +); - // Interface declarations - dti #(.W_DATA(5)) din(); - dti #(.W_DATA(1)) dout0(); - dti #(.W_DATA(2)) dout1(); - dti #(.W_DATA(3)) dout2(); + // Interface declarations + dti #(.W_DATA(5)) din (); + dti #(.W_DATA(1)) dout0 (); + dti #(.W_DATA(2)) dout1 (); + dti #(.W_DATA(3)) dout2 (); - // Interface wiring to top level ports - assign din.valid = din_valid; - assign din.data = din_data; - assign din_ready = din.ready; + // Interface wiring to top level ports + assign din.valid = din_valid; + assign din.data = din_data; + assign din_ready = din.ready; - assign dout0_valid = dout0.valid; - assign dout0_data = dout0.data; - assign dout0.ready = dout0_ready; + assign dout0_valid = dout0.valid; + assign dout0_data = dout0.data; + assign dout0.ready = dout0_ready; - assign dout1_valid = dout1.valid; - assign dout1_data = dout1.data; - assign dout1.ready = dout1_ready; + assign dout1_valid = dout1.valid; + assign dout1_data = dout1.data; + assign dout1.ready = dout1_ready; - assign dout2_valid = dout2.valid; - assign dout2_data = dout2.data; - assign dout2.ready = dout2_ready; + assign dout2_valid = dout2.valid; + assign dout2_data = dout2.data; + assign dout2.ready = dout2_ready; - assign din.ready = 0; - assign dout0.data = 0; - assign dout1.data = 0; - assign dout2.data = 0; + assign din.ready = 0; + assign dout0.data = 0; + assign dout1.data = 0; + assign dout2.data = 0; - typedef struct packed { - logic [1:0] ctrl; - logic [2:0] data; - } din_t; + typedef struct packed { + logic [1:0] ctrl; + logic [2:0] data; + } din_t; - din_t din_s; - assign din_s = din.data; + din_t din_s; + assign din_s = din.data; - always_comb begin - dout0.valid = 0; - dout1.valid = 0; - dout2.valid = 0; + always_comb begin + dout0.valid = 0; + dout1.valid = 0; + dout2.valid = 0; - case (din_s.ctrl) - 0 : dout0.valid = din.valid; - 1 : dout1.valid = din.valid; - 2 : dout2.valid = din.valid; - default: ; - endcase - end + case (din_s.ctrl) + 0: dout0.valid = din.valid; + 1: dout1.valid = din.valid; + 2: dout2.valid = din.valid; + default: ; + endcase + end endmodule diff --git a/test_regress/t/t_interface_find.v b/test_regress/t/t_interface_find.v index 284b31e4f..34ddf7c29 100644 --- a/test_regress/t/t_interface_find.v +++ b/test_regress/t/t_interface_find.v @@ -7,37 +7,36 @@ // Auto-resolved by t_interface_find_ifc.v // interface t_interface_find_ifc; -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - t_interface_find_ifc itop(); + t_interface_find_ifc itop (); - sub c1 (.isub(itop), - .i_value(4'h4)); + sub c1 ( + .isub(itop), + .i_value(4'h4) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison - if (itop.value != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison + if (itop.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub - ( - t_interface_find_ifc isub, - input logic [3:0] i_value - ); +module sub ( + t_interface_find_ifc isub, + input logic [3:0] i_value +); - always @* begin - isub.value = i_value; - end + always @* begin + isub.value = i_value; + end endmodule : sub diff --git a/test_regress/t/t_interface_find_ifc.v b/test_regress/t/t_interface_find_ifc.v index ddf1ec395..efca31286 100644 --- a/test_regress/t/t_interface_find_ifc.v +++ b/test_regress/t/t_interface_find_ifc.v @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 interface t_interface_find_ifc; - logic [3:0] value; + logic [3:0] value; endinterface diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index 2c3d61772..2a90dd100 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -6,60 +6,64 @@ // Very simple test for interface pathclearing -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc #(1) itopa(); - ifc #(2) itopb(); + ifc #(1) itopa (); + ifc #(2) itopb (); - sub #(1) ca (.isub(itopa), - .i_value(4)); - sub #(2) cb (.isub(itopb), - .i_value(5)); + sub #(1) ca ( + .isub(itopa), + .i_value(4) + ); + sub #(2) cb ( + .isub(itopb), + .i_value(5) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - if (itopa.MODE != 1) $stop; - if (itopb.MODE != 2) $stop; - end - if (cyc==20) begin - if (itopa.get_value() != 4) $stop; - if (itopb.get_value() != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc == 20) begin + if (itopa.get_value() != 4) $stop; + if (itopb.get_value() != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub - #(parameter MODE = 0) - ( - ifc.out_modport isub, - input integer i_value - ); +module sub #( + parameter MODE = 0 +) ( + ifc.out_modport isub, + input integer i_value +); - always @* isub.value = i_value; + always @* isub.value = i_value; endmodule interface ifc; - parameter MODE = 0; - // Modports under generates not supported by all commercial simulators + parameter MODE = 0; + // Modports under generates not supported by all commercial simulators - integer value; - modport out_modport (output value); - function integer get_value(); return value; endfunction + integer value; + modport out_modport(output value); + function integer get_value(); + return value; + endfunction - // IEEE 1800-2017 deprecated alowing modports inside generates - // generate if (MODE == 0) begin - // integer valuea; - // modport out_modport (output valuea); - // function integer get_valuea(); return valuea; endfunction - // end + // IEEE 1800-2017 deprecated alowing modports inside generates + // generate if (MODE == 0) begin + // integer valuea; + // modport out_modport (output valuea); + // function integer get_valuea(); return valuea; endfunction + // end endinterface diff --git a/test_regress/t/t_interface_gen10.v b/test_regress/t/t_interface_gen10.v index d3f31b60b..0e5235c16 100644 --- a/test_regress/t/t_interface_gen10.v +++ b/test_regress/t/t_interface_gen10.v @@ -6,29 +6,33 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); - logic val; - function integer func (); return 5; endfunction +interface intf #( + parameter PARAM = 0 +) (); + logic val; + function integer func(); + return 5; + endfunction endinterface -module t1(intf mod_intf); - initial begin - $display("%m %d", mod_intf.val); - end +module t1 ( + intf mod_intf +); + initial begin + $display("%m %d", mod_intf.val); + end endmodule module t; - generate - begin : TestIf - intf #(.PARAM(1)) my_intf [0:0] (); - t1 t (.mod_intf(my_intf[0])); - end - endgenerate + generate + begin : TestIf + intf #(.PARAM(1)) my_intf[0:0] (); + t1 t (.mod_intf(my_intf[0])); + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen11.v b/test_regress/t/t_interface_gen11.v index 0fc617cde..5ff1e84db 100644 --- a/test_regress/t/t_interface_gen11.v +++ b/test_regress/t/t_interface_gen11.v @@ -6,35 +6,41 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); - logic val; - function integer func (); return 5; endfunction +interface intf #( + parameter PARAM = 0 +) (); + logic val; + function integer func(); + return 5; + endfunction endinterface -module t1(intf mod_intf); - initial begin - $display("%m %d", mod_intf.val); - end +module t1 ( + intf mod_intf +); + initial begin + $display("%m %d", mod_intf.val); + end endmodule -module t2(intf mod_intfs [1:0]); - generate +module t2 ( + intf mod_intfs[1:0] +); + generate begin - t1 t(.mod_intf(mod_intfs[0])); + t1 t (.mod_intf(mod_intfs[0])); end - endgenerate + endgenerate endmodule module t; - intf #(.PARAM(1)) my_intf [1:0] (); + intf #(.PARAM(1)) my_intf[1:0] (); - t2 t2 (.mod_intfs(my_intf)); + t2 t2 (.mod_intfs(my_intf)); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen12.v b/test_regress/t/t_interface_gen12.v index 636645f21..19c3787f4 100644 --- a/test_regress/t/t_interface_gen12.v +++ b/test_regress/t/t_interface_gen12.v @@ -7,24 +7,24 @@ // bug1005 module foo_module; - generate - for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block - logic baz; - end - endgenerate + generate + for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block + logic baz; + end + endgenerate endmodule module bar_module; - foo_module foo(); + foo_module foo (); endmodule module t; - bar_module bar(); - initial begin - bar.foo.my_gen_block[0].baz = 1; - if (bar.foo.my_gen_block[0].baz) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + bar_module bar (); + initial begin + bar.foo.my_gen_block[0].baz = 1; + if (bar.foo.my_gen_block[0].baz) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_interface_gen13.v b/test_regress/t/t_interface_gen13.v index 9eabdde8c..abfaa2bd8 100644 --- a/test_regress/t/t_interface_gen13.v +++ b/test_regress/t/t_interface_gen13.v @@ -6,54 +6,55 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); +interface intf #( + parameter PARAM = 0 +) (); - int p1; - generate - initial p1 = 1; - endgenerate + int p1; + generate + initial p1 = 1; + endgenerate - int p2; - generate begin + int p2; + generate + begin initial p2 = 1; - end - endgenerate + end + endgenerate - int p3; - int p3_no; - if (PARAM == 1) initial p3 = 1; else initial p3_no = 1; + int p3; + int p3_no; + if (PARAM == 1) initial p3 = 1; + else initial p3_no = 1; - int p4; - int p4_no; - case (PARAM) - 1: initial p4 = 1; - default: initial p4_no = 1; - endcase + int p4; + int p4_no; + case (PARAM) + 1: initial p4 = 1; + default: + initial p4_no = 1; + endcase - int p5; - for (genvar g=0; g<=PARAM; ++g) initial p5 = 1; + int p5; + for (genvar g = 0; g <= PARAM; ++g) initial p5 = 1; endinterface -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - intf #(.PARAM(1)) my_intf (); + intf #(.PARAM(1)) my_intf (); - always @ (posedge clk) begin - if (my_intf.p1 != 1) $stop; - if (my_intf.p2 != 1) $stop; - if (my_intf.p3 != 1) $stop; - if (my_intf.p3_no != 0) $stop; - if (my_intf.p4 != 1) $stop; - if (my_intf.p4_no != 0) $stop; - if (my_intf.p5 != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (my_intf.p1 != 1) $stop; + if (my_intf.p2 != 1) $stop; + if (my_intf.p3 != 1) $stop; + if (my_intf.p3_no != 0) $stop; + if (my_intf.p4 != 1) $stop; + if (my_intf.p4_no != 0) $stop; + if (my_intf.p5 != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen2.v b/test_regress/t/t_interface_gen2.v index ab6c5b401..2049c6ea5 100644 --- a/test_regress/t/t_interface_gen2.v +++ b/test_regress/t/t_interface_gen2.v @@ -6,66 +6,68 @@ // Very simple test for interface pathclearing -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc #(2) itopa(); - ifc #(4) itopb(); + ifc #(2) itopa (); + ifc #(4) itopb (); - sub ca (.isub(itopa), - .clk); - sub cb (.isub(itopb), - .clk); + sub ca ( + .isub(itopa), + .clk + ); + sub cb ( + .isub(itopb), + .clk + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); + $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); `endif - cyc <= cyc + 1; - itopa.valuei <= cyc[1:0]; - itopb.valuei <= cyc[3:0]; - if (cyc==1) begin - if (itopa.WIDTH != 2) $stop; - if (itopb.WIDTH != 4) $stop; - if ($bits(itopa.valueo) != 2) $stop; - if ($bits(itopb.valueo) != 4) $stop; - if ($bits(itopa.out_modport.valueo) != 2) $stop; - if ($bits(itopb.out_modport.valueo) != 4) $stop; - end - if (cyc==4) begin - if (itopa.valueo != 2'b11) $stop; - if (itopb.valueo != 4'b0011) $stop; - end - if (cyc==5) begin - if (itopa.valueo != 2'b00) $stop; - if (itopb.valueo != 4'b0100) $stop; - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + itopa.valuei <= cyc[1:0]; + itopb.valuei <= cyc[3:0]; + if (cyc == 1) begin + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; + end + if (cyc == 4) begin + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; + end + if (cyc == 5) begin + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; + end + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -interface ifc - #(parameter WIDTH = 1); - // verilator lint_off MULTIDRIVEN - logic [WIDTH-1:0] valuei; - logic [WIDTH-1:0] valueo; - // verilator lint_on MULTIDRIVEN - modport out_modport (input valuei, output valueo); +interface ifc #( + parameter WIDTH = 1 +); + // verilator lint_off MULTIDRIVEN + logic [WIDTH-1:0] valuei; + logic [WIDTH-1:0] valueo; + // verilator lint_on MULTIDRIVEN + modport out_modport(input valuei, output valueo); endinterface // Note not parameterized -module sub - ( - ifc.out_modport isub, - input clk - ); - always @(posedge clk) isub.valueo <= isub.valuei + 1; +module sub ( + ifc.out_modport isub, + input clk +); + always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule diff --git a/test_regress/t/t_interface_gen3.v b/test_regress/t/t_interface_gen3.v index 1e8f6756b..d793e705b 100644 --- a/test_regress/t/t_interface_gen3.v +++ b/test_regress/t/t_interface_gen3.v @@ -6,66 +6,68 @@ // Very simple test for interface pathclearing -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc #(2) itopa(); - ifc #(4) itopb(); + ifc #(2) itopa (); + ifc #(4) itopb (); - sub ca (.isub(itopa.out_modport), - .clk); - sub cb (.isub(itopb.out_modport), - .clk); + sub ca ( + .isub(itopa.out_modport), + .clk + ); + sub cb ( + .isub(itopb.out_modport), + .clk + ); - always @ (posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); + $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); `endif - cyc <= cyc + 1; - itopa.valuei <= cyc[1:0]; - itopb.valuei <= cyc[3:0]; - if (cyc==1) begin - if (itopa.WIDTH != 2) $stop; - if (itopb.WIDTH != 4) $stop; - if ($bits(itopa.valueo) != 2) $stop; - if ($bits(itopb.valueo) != 4) $stop; - if ($bits(itopa.out_modport.valueo) != 2) $stop; - if ($bits(itopb.out_modport.valueo) != 4) $stop; - end - if (cyc==4) begin - if (itopa.valueo != 2'b11) $stop; - if (itopb.valueo != 4'b0011) $stop; - end - if (cyc==5) begin - if (itopa.valueo != 2'b00) $stop; - if (itopb.valueo != 4'b0100) $stop; - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + itopa.valuei <= cyc[1:0]; + itopb.valuei <= cyc[3:0]; + if (cyc == 1) begin + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; + end + if (cyc == 4) begin + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; + end + if (cyc == 5) begin + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; + end + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -interface ifc - #(parameter WIDTH = 1); - // verilator lint_off MULTIDRIVEN - logic [WIDTH-1:0] valuei; - logic [WIDTH-1:0] valueo; - // verilator lint_on MULTIDRIVEN - modport out_modport (input valuei, output valueo); +interface ifc #( + parameter WIDTH = 1 +); + // verilator lint_off MULTIDRIVEN + logic [WIDTH-1:0] valuei; + logic [WIDTH-1:0] valueo; + // verilator lint_on MULTIDRIVEN + modport out_modport(input valuei, output valueo); endinterface // Note not parameterized -module sub - ( - ifc.out_modport isub, - input clk - ); - always @(posedge clk) isub.valueo <= isub.valuei + 1; +module sub ( + ifc.out_modport isub, + input clk +); + always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule diff --git a/test_regress/t/t_interface_gen4.v b/test_regress/t/t_interface_gen4.v index 10b574206..9b1a539ff 100644 --- a/test_regress/t/t_interface_gen4.v +++ b/test_regress/t/t_interface_gen4.v @@ -6,54 +6,56 @@ // bug789 generates -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc #(1) itopa(); - ifc #(2) itopb(); + ifc #(1) itopa (); + ifc #(2) itopb (); - sub #(1) ca (.isub(itopa), - .i_value(4)); - sub #(2) cb (.isub(itopb), - .i_value(5)); + sub #(1) ca ( + .isub(itopa), + .i_value(4) + ); + sub #(2) cb ( + .isub(itopb), + .i_value(5) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==1) begin - if (itopa.MODE != 1) $stop; - if (itopb.MODE != 2) $stop; - end - if (cyc==20) begin - if (itopa.i != 4) $stop; - if (itopb.i != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc == 20) begin + if (itopa.i != 4) $stop; + if (itopb.i != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub - #(parameter MODE = 0) - ( +module sub #( + parameter MODE = 0 +) ( ifc isub, input integer i_value - ); +); - // Commercial unsupported Xmrs into scopes within interfaces - generate - always_comb isub.i = i_value; - endgenerate + // Commercial unsupported Xmrs into scopes within interfaces + generate + always_comb isub.i = i_value; + endgenerate endmodule interface ifc; - parameter MODE = 0; - // Commercial unsupported Xmrs into scopes within interfaces - generate - integer i; - endgenerate + parameter MODE = 0; + // Commercial unsupported Xmrs into scopes within interfaces + generate + integer i; + endgenerate endinterface diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v index ca54aaf56..35b692056 100644 --- a/test_regress/t/t_interface_gen5.v +++ b/test_regress/t/t_interface_gen5.v @@ -6,56 +6,63 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); - logic val; - function integer func (); return 5; endfunction +interface intf #( + parameter PARAM = 0 +) (); + logic val; + function integer func(); + return 5; + endfunction endinterface -module t1(intf mod_intf); - initial begin - $display("%m %d", mod_intf.val); - end +module t1 ( + intf mod_intf +); + initial begin + $display("%m %d", mod_intf.val); + end endmodule module t; - generate - begin : TestIf - intf #(.PARAM(1)) my_intf (); - assign my_intf.val = '0; - t1 t (.mod_intf(my_intf)); -// initial $display("%0d", my_intf.func()); - end - endgenerate + generate + begin : TestIf + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '0; + t1 t (.mod_intf(my_intf)); + // initial $display("%0d", my_intf.func()); + end + endgenerate - generate - begin - intf #(.PARAM(1)) my_intf (); - assign my_intf.val = '1; - t1 t (.mod_intf(my_intf)); -// initial $display("%0d", my_intf.func()); - end - endgenerate + generate + begin + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '1; + t1 t (.mod_intf(my_intf)); + // initial $display("%0d", my_intf.func()); + end + endgenerate - localparam LP = 1; - logic val; + localparam LP = 1; + logic val; - generate begin + generate + begin if (LP) begin - intf #(.PARAM(2)) my_intf (); - assign my_intf.val = '1; - assign val = my_intf.val; - end else begin - intf #(.PARAM(3)) my_intf (); - assign my_intf.val = '1; - assign val = my_intf.val; + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; end - end endgenerate + else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; + end + end + endgenerate - initial begin - $display("%0d", val); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $display("%0d", val); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index 18858412d..5ab130dba 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -6,52 +6,55 @@ // bug1001 -interface intf - #(parameter PARAM = 0) - (); - logic val; +interface intf #( + parameter PARAM = 0 +) (); + logic val; endinterface module t; - generate + generate + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end + else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + endgenerate + + generate + begin if (1) begin - intf #(.PARAM(2)) my_intf (); - assign my_intf.val = '1; - end else begin - intf #(.PARAM(3)) my_intf (); - assign my_intf.val = '0; + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; end - endgenerate + else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + end + endgenerate - generate + generate + begin begin - if (1) begin - intf #(.PARAM(2)) my_intf (); - assign my_intf.val = '1; - end else begin - intf #(.PARAM(3)) my_intf (); - assign my_intf.val = '0; - end + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end + else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end end - endgenerate + end + endgenerate - generate - begin - begin - if (1) begin - intf #(.PARAM(2)) my_intf (); - assign my_intf.val = '1; - end else begin - intf #(.PARAM(3)) my_intf (); - assign my_intf.val = '0; - end - end - end - endgenerate - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index a9dfb6e8a..4c2b7f37b 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -6,65 +6,69 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); - /* verilator lint_off MULTIDRIVEN */ - logic val; - /* verilator lint_on MULTIDRIVEN */ - function integer func (); return 5; endfunction +interface intf #( + parameter PARAM = 0 +) (); + /* verilator lint_off MULTIDRIVEN */ + logic val; + /* verilator lint_on MULTIDRIVEN */ + function integer func(); + return 5; + endfunction endinterface -module t1(intf mod_intf); - initial begin - $display("%m %d", mod_intf.val); - end +module t1 ( + intf mod_intf +); + initial begin + $display("%m %d", mod_intf.val); + end endmodule module t; - intf #(.PARAM(1)) my_intf [1:0] (); + intf #(.PARAM(1)) my_intf[1:0] (); - generate - genvar the_genvar; - begin : ia - for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf - begin - assign my_intf[the_genvar].val = '1; - t1 t (.mod_intf(my_intf[the_genvar])); - end - end + generate + genvar the_genvar; + begin : ia + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + begin + assign my_intf[the_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_genvar])); + end end - endgenerate + end + endgenerate - generate - genvar the_second_genvar; - begin : ib - intf #(.PARAM(1)) my_intf [1:0] (); - for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf - begin - assign my_intf[the_second_genvar].val = '1; - t1 t (.mod_intf(my_intf[the_second_genvar])); - end - end + generate + genvar the_second_genvar; + begin : ib + intf #(.PARAM(1)) my_intf[1:0] (); + for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf + begin + assign my_intf[the_second_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_second_genvar])); + end end - endgenerate + end + endgenerate - generate - genvar the_third_genvar; - begin : ic - for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf - begin - intf #(.PARAM(1)) my_intf [1:0] (); - assign my_intf[the_third_genvar].val = '1; - t1 t (.mod_intf(my_intf[the_third_genvar])); - end - end + generate + genvar the_third_genvar; + begin : ic + for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf + begin + intf #(.PARAM(1)) my_intf[1:0] (); + assign my_intf[the_third_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_third_genvar])); + end end - endgenerate + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen8.v b/test_regress/t/t_interface_gen8.v index 1de7133b9..401e2c3c1 100644 --- a/test_regress/t/t_interface_gen8.v +++ b/test_regress/t/t_interface_gen8.v @@ -6,51 +6,55 @@ // bug998 -interface intf - #(parameter PARAM = 0) - (); - logic val; - function integer func (); return 5; endfunction +interface intf #( + parameter PARAM = 0 +) (); + logic val; + function integer func(); + return 5; + endfunction endinterface -module t1(intf mod_intf); - initial begin - $display("%m %d", mod_intf.val); - end +module t1 ( + intf mod_intf +); + initial begin + $display("%m %d", mod_intf.val); + end endmodule module t; - //intf #(.PARAM(1)) my_intf [1:0] (); - intf #(.PARAM(1)) my_intf (); + //intf #(.PARAM(1)) my_intf [1:0] (); + intf #(.PARAM(1)) my_intf (); - generate - genvar the_genvar; - for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf - //assign my_intf[the_genvar].val = '1; - //t1 t (.mod_intf(my_intf[the_genvar])); - t1 t (.mod_intf(my_intf)); - end - endgenerate + generate + genvar the_genvar; + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + //assign my_intf[the_genvar].val = '1; + //t1 t (.mod_intf(my_intf[the_genvar])); + t1 t (.mod_intf(my_intf)); + end + endgenerate -// t1 t (.mod_intf(my_intf[1])); + // t1 t (.mod_intf(my_intf[1])); -// generate -// begin : TestIf -// assign my_intf[1].val = '1; -// t1 t (.mod_intf(my_intf[1])); -// end -// endgenerate + // generate + // begin : TestIf + // assign my_intf[1].val = '1; + // t1 t (.mod_intf(my_intf[1])); + // end + // endgenerate -// generate -// begin -// assign my_intf[0].val = '1; -// t1 t (.mod_intf(my_intf[0])); -// end -// endgenerate + // generate + // begin + // assign my_intf[0].val = '1; + // t1 t (.mod_intf(my_intf[0])); + // end + // endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_gen9.v b/test_regress/t/t_interface_gen9.v index a329dba5f..652356c7c 100644 --- a/test_regress/t/t_interface_gen9.v +++ b/test_regress/t/t_interface_gen9.v @@ -6,28 +6,30 @@ // bug998 -module t1(input logic foo); - initial begin - $display("%m %d", foo); - end +module t1 ( + input logic foo +); + initial begin + $display("%m %d", foo); + end endmodule module t; - logic [1:0] my_foo; + logic [1:0] my_foo; - generate - genvar the_genvar; - for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf - //logic tmp_foo; - //assign tmp_foo = my_foo[the_genvar]; - t1 t (.foo(my_foo[the_genvar])); - //t1 t (.foo(tmp_foo)); - end - endgenerate + generate + genvar the_genvar; + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + //logic tmp_foo; + //assign tmp_foo = my_foo[the_genvar]; + t1 t (.foo(my_foo[the_genvar])); + //t1 t (.foo(tmp_foo)); + end + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_hidden.v b/test_regress/t/t_interface_hidden.v index bda43b19a..8c43558f5 100644 --- a/test_regress/t/t_interface_hidden.v +++ b/test_regress/t/t_interface_hidden.v @@ -4,73 +4,72 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - ifc ifc(); // Cell name hides interface's name - assign ifc.ifi = 55; + ifc ifc (); // Cell name hides interface's name + assign ifc.ifi = 55; - sub sub (.isub(ifc)); // Cell name hides module's name + sub sub (.isub(ifc)); // Cell name hides module's name - int om; + int om; - mod_or_type mot (.*); + mod_or_type mot (.*); - hides_with_type hides_type(); - hides_with_decl hides_decl(); + hides_with_type hides_type (); + hides_with_decl hides_decl (); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 20) begin - if (om != 22) $stop; - if (mot.LOCAL != 22) $stop; - if (ifc.ifo != 55) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (om != 22) $stop; + if (mot.LOCAL != 22) $stop; + if (ifc.ifo != 55) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub - ( - ifc isub - ); - always @* begin - isub.ifo = isub.ifi; - end +module sub ( + ifc isub +); + always @* begin + isub.ifo = isub.ifi; + end endmodule -module mod_or_type(output int om); - localparam LOCAL = 22; - initial om = 22; +module mod_or_type ( + output int om +); + localparam LOCAL = 22; + initial om = 22; endmodule -module hides_with_type(); - typedef int ifc; // Hides interface - typedef int mod_or_type; // Hides module +module hides_with_type (); + typedef int ifc; // Hides interface + typedef int mod_or_type; // Hides module - ifc /*=int*/ hides_ifc; - mod_or_type /*=int*/ hides_mod; + ifc /*=int*/ hides_ifc; + mod_or_type /*=int*/ hides_mod; - initial hides_ifc = 33; - initial hides_mod = 44; + initial hides_ifc = 33; + initial hides_mod = 44; endmodule -module hides_with_decl(); - int ifc; // Hides interface - int mod_or_type; // Hides module +module hides_with_decl (); + int ifc; // Hides interface + int mod_or_type; // Hides module - initial ifc = 66; - initial mod_or_type = 77; + initial ifc = 66; + initial mod_or_type = 77; endmodule interface ifc; - localparam LOCAL = 12; - int ifi; - int ifo; + localparam LOCAL = 12; + int ifi; + int ifo; endinterface diff --git a/test_regress/t/t_interface_import_param.v b/test_regress/t/t_interface_import_param.v index aec218dde..565114e9b 100644 --- a/test_regress/t/t_interface_import_param.v +++ b/test_regress/t/t_interface_import_param.v @@ -12,36 +12,38 @@ package bus_pkg; endpackage interface simple_bus - import bus_pkg::*; // Import preceding parameters. - #(p_width = WIDTH) - (input logic clk); + import bus_pkg::*; // Import preceding parameters. +#( + p_width = WIDTH +) ( + input logic clk +); - logic req, gnt; - logic [p_width-1:0] addr; - logic [p_width-1:0] data; + logic req, gnt; + logic [p_width-1:0] addr; + logic [p_width-1:0] data; - modport slave(input req, addr, clk, - output gnt, - input data); + modport slave(input req, addr, clk, output gnt, input data); - modport master(input gnt, clk, - output req, addr, - output data); + modport master(input gnt, clk, output req, addr, output data); endinterface -module mem(simple_bus a); - logic avail; - always @(posedge a.clk) - a.gnt <= a.req & avail; - initial begin - if ($bits(a.data) != 8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end +module mem ( + simple_bus a +); + logic avail; + always @(posedge a.clk) a.gnt <= a.req & avail; + initial begin + if ($bits(a.data) != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module t (input clk); - simple_bus sb(clk); - mem mem(sb.slave); +module t ( + input clk +); + simple_bus sb (clk); + mem mem (sb.slave); endmodule diff --git a/test_regress/t/t_interface_localparam.v b/test_regress/t/t_interface_localparam.v index a753aa752..358c8d9a4 100644 --- a/test_regress/t/t_interface_localparam.v +++ b/test_regress/t/t_interface_localparam.v @@ -4,57 +4,53 @@ // SPDX-FileCopyrightText: 2023 Justin Thiel // SPDX-License-Identifier: CC0-1.0 -interface SimpleIntf -#( - parameter int VAL = 28 -) -(); +interface SimpleIntf #( + parameter int VAL = 28 +) (); - // This value is calculated incorrectly for other instances of - // this interface when it is accessed via the HDL for any other - // instance of this interface - localparam int valDiv2 = VAL/2; - localparam int valDiv4 = valDiv2/2; + // This value is calculated incorrectly for other instances of + // this interface when it is accessed via the HDL for any other + // instance of this interface + localparam int valDiv2 = VAL / 2; + localparam int valDiv4 = valDiv2 / 2; - localparam bit mismatch2 = (VAL != (2*valDiv2) ); - localparam bit mismatch4 = (VAL != (4*valDiv4) ); + localparam bit mismatch2 = (VAL != (2 * valDiv2)); + localparam bit mismatch4 = (VAL != (4 * valDiv4)); - initial begin - $write("%m: VAL %0d, valDiv2 %0d, mismatch2 %0d\n", - VAL, valDiv2, mismatch2); - $write("%m: VAL %0d, valDiv4 %0d, mismatch4 %0d\n", - VAL, valDiv4, mismatch2); - if (mismatch2) $stop; - if (mismatch4) $stop; - end + initial begin + $write("%m: VAL %0d, valDiv2 %0d, mismatch2 %0d\n", VAL, valDiv2, mismatch2); + $write("%m: VAL %0d, valDiv4 %0d, mismatch4 %0d\n", VAL, valDiv4, mismatch2); + if (mismatch2) $stop; + if (mismatch4) $stop; + end endinterface -module Core( - SimpleIntf intf +module Core ( + SimpleIntf intf ); - // this will constify and valDiv2 will have the default value - localparam valDiv4Upper = intf.valDiv2; + // this will constify and valDiv2 will have the default value + localparam valDiv4Upper = intf.valDiv2; - SimpleIntf #(.VAL(68)) core_intf (); + SimpleIntf #(.VAL(68)) core_intf (); - initial begin - if (intf.valDiv2 != valDiv4Upper) begin - $display("%%Error: param = %0d", intf.valDiv2); - end - end + initial begin + if (intf.valDiv2 != valDiv4Upper) begin + $display("%%Error: param = %0d", intf.valDiv2); + end + end endmodule module t; - SimpleIntf intf(); + SimpleIntf intf (); - Core theCore (.intf); + Core theCore (.intf); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_mismodport_bad.out b/test_regress/t/t_interface_mismodport_bad.out index 598cdd3df..e57230e0a 100644 --- a/test_regress/t/t_interface_mismodport_bad.out +++ b/test_regress/t/t_interface_mismodport_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted variable/method: 'isub.bad' - 32 | isub.bad = i_value; - | ^~~ +%Error: t/t_interface_mismodport_bad.v:33:10: Can't find definition of 'bad' in dotted variable/method: 'isub.bad' + 33 | isub.bad = i_value; + | ^~~ ... Known scopes under 'isub': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_mismodport_bad.v b/test_regress/t/t_interface_mismodport_bad.v index 39747a7bf..f227feaa4 100644 --- a/test_regress/t/t_interface_mismodport_bad.v +++ b/test_regress/t/t_interface_mismodport_bad.v @@ -5,30 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - integer ok; - integer bad; - modport out_modport (output ok); + integer ok; + integer bad; + modport out_modport(output ok); endinterface module t; - integer cyc=1; + integer cyc = 1; - ifc itop(); + ifc itop (); - counter_ansi c1 (.isub(itop), - .i_value(4'h4)); + counter_ansi c1 ( + .isub(itop), + .i_value(4'h4) + ); endmodule -module counter_ansi - ( - ifc.out_modport isub, - input logic [3:0] i_value - ); +module counter_ansi ( + ifc.out_modport isub, + input logic [3:0] i_value +); - always @* begin - isub.ok = i_value; - isub.bad = i_value; // Illegal access - end + always @* begin + isub.ok = i_value; + isub.bad = i_value; // Illegal access + end endmodule diff --git a/test_regress/t/t_interface_missing_bad.out b/test_regress/t/t_interface_missing_bad.out index 2b5585d4b..2aa541eb0 100644 --- a/test_regress/t/t_interface_missing_bad.out +++ b/test_regress/t/t_interface_missing_bad.out @@ -1,11 +1,11 @@ -%Error: t/t_interface_missing_bad.v:14:4: Can't find typedef/interface: 'foo_intf' - 14 | foo_intf foo - | ^~~~~~~~ +%Error: t/t_interface_missing_bad.v:13:5: Can't find typedef/interface: 'foo_intf' + 13 | foo_intf foo + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_missing_bad.v:20:4: Cannot find file containing interface: 'foo_intf' - 20 | foo_intf the_foo (); - | ^~~~~~~~ -%Error: t/t_interface_missing_bad.v:25:15: Found definition of 'the_foo' as a CELL but expected a variable - 25 | .foo (the_foo) - | ^~~~~~~ +%Error: t/t_interface_missing_bad.v:19:3: Cannot find file containing interface: 'foo_intf' + 19 | foo_intf the_foo (); + | ^~~~~~~~ +%Error: t/t_interface_missing_bad.v:21:25: Found definition of 'the_foo' as a CELL but expected a variable + 21 | foo_mod foo_mod (.foo(the_foo)); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_missing_bad.v b/test_regress/t/t_interface_missing_bad.v index e546e14b1..98d58574a 100644 --- a/test_regress/t/t_interface_missing_bad.v +++ b/test_regress/t/t_interface_missing_bad.v @@ -9,25 +9,20 @@ // logic a; //endinterface -module foo_mod - ( - foo_intf foo - ); +module foo_mod ( + foo_intf foo +); endmodule module t; - foo_intf the_foo (); + foo_intf the_foo (); - foo_mod - foo_mod - ( - .foo (the_foo) - ); + foo_mod foo_mod (.foo(the_foo)); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_modport_bad.out b/test_regress/t/t_interface_modport_bad.out index c4da3517a..93332c514 100644 --- a/test_regress/t/t_interface_modport_bad.out +++ b/test_regress/t/t_interface_modport_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_modport_bad.v:23:8: Modport not found under interface 'ifc': 'oop_modport' +%Error: t/t_interface_modport_bad.v:24:9: Modport not found under interface 'ifc': 'oop_modport' : ... Suggested alternative: 'out_modport' - 23 | ifc.oop_modport isub, - | ^~~~~~~~~~~ + 24 | ifc.oop_modport isub, + | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_bad.v b/test_regress/t/t_interface_modport_bad.v index b846827ea..ee5dae697 100644 --- a/test_regress/t/t_interface_modport_bad.v +++ b/test_regress/t/t_interface_modport_bad.v @@ -5,22 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - integer ok; - modport out_modport (output ok); + integer ok; + modport out_modport(output ok); endinterface module t; - ifc itop(); + ifc itop (); - counter_ansi c1 (.isub(itop), - .i_value(4'h4)); + counter_ansi c1 ( + .isub(itop), + .i_value(4'h4) + ); endmodule -module counter_ansi - ( - ifc.oop_modport isub, // Bad - input logic [3:0] i_value - ); +module counter_ansi ( + ifc.oop_modport isub, // Bad + input logic [3:0] i_value +); endmodule diff --git a/test_regress/t/t_interface_modport_dir_bad.out b/test_regress/t/t_interface_modport_dir_bad.out index 979977a19..9c493e600 100644 --- a/test_regress/t/t_interface_modport_dir_bad.out +++ b/test_regress/t/t_interface_modport_dir_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_modport_dir_bad.v:52:25: Port connection 'ctrl' expected 'source' interface modport on pin connection but got 'sink' modport. +%Error: t/t_interface_modport_dir_bad.v:41:24: Port connection 'ctrl' expected 'source' interface modport on pin connection but got 'sink' modport. : ... note: In instance 't.source_i' - 52 | sourceMod source_i (.ctrl); - | ^~~~ + 41 | sourceMod source_i (.ctrl); + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_dir_bad.v b/test_regress/t/t_interface_modport_dir_bad.v index c682802b3..e3968277d 100644 --- a/test_regress/t/t_interface_modport_dir_bad.v +++ b/test_regress/t/t_interface_modport_dir_bad.v @@ -4,72 +4,68 @@ // SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 -interface validData - ( - input wire clk, - input wire rst - ); +interface validData ( + input wire clk, + input wire rst +); - logic data; - logic valid; + logic data; + logic valid; - modport sink - ( - input data, valid, clk, rst - ); + modport sink(input data, valid, clk, rst); - modport source - ( - input clk, rst, - output data, valid - ); + modport source(input clk, rst, output data, valid); endinterface -module sinkMod - ( - validData.sink ctrl, - output logic valid_data - ); - always_ff @(posedge ctrl.clk) begin - if (ctrl.valid) valid_data <= ctrl.data; - end +module sinkMod ( + validData.sink ctrl, + output logic valid_data +); + always_ff @(posedge ctrl.clk) begin + if (ctrl.valid) valid_data <= ctrl.data; + end endmodule -module sourceMod - ( - validData.source ctrl - ); - always_ff @(posedge ctrl.clk) begin - ctrl.data <= ~ctrl.data; - ctrl.valid <= ~ctrl.valid; - end +module sourceMod ( + validData.source ctrl +); + always_ff @(posedge ctrl.clk) begin + ctrl.data <= ~ctrl.data; + ctrl.valid <= ~ctrl.valid; + end endmodule -module parentSourceMod - ( - validData.sink ctrl - ); - sourceMod source_i (.ctrl); +module parentSourceMod ( + validData.sink ctrl +); + sourceMod source_i (.ctrl); endmodule -module t (/*AUTOARG*/ - // Outputs - data, - // Inputs - clk, rst - ); - input clk; - input rst; - output logic data; +module t ( /*AUTOARG*/ + // Outputs + data, + // Inputs + clk, + rst +); + input clk; + input rst; + output logic data; - validData ctrl(.clk, .rst); - sinkMod sink_i (.ctrl, .valid_data(data)); - parentSourceMod source_i (.ctrl); + validData ctrl ( + .clk, + .rst + ); + sinkMod sink_i ( + .ctrl, + .valid_data(data) + ); + parentSourceMod source_i (.ctrl); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_modport_export.out b/test_regress/t/t_interface_modport_export.out index 27cf64600..f138ab349 100644 --- a/test_regress/t/t_interface_modport_export.out +++ b/test_regress/t/t_interface_modport_export.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_interface_modport_export.v:12:4: Unsupported: extern function - 12 | extern function myfunc (input logic val); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_interface_modport_export.v:12:3: Unsupported: extern function + 12 | extern function myfunc (input logic val); + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_interface_modport_export.v:51:31: Unsupported: Out of block function declaration - 51 | function automatic logic ie.myfunc (input logic val); - | ^ +%Error-UNSUPPORTED: t/t_interface_modport_export.v:48:30: Unsupported: Out of block function declaration + 48 | function automatic logic ie.myfunc (input logic val); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_export.v b/test_regress/t/t_interface_modport_export.v index 313b4feaa..62570187b 100644 --- a/test_regress/t/t_interface_modport_export.v +++ b/test_regress/t/t_interface_modport_export.v @@ -8,68 +8,64 @@ interface test_if; - // Pre-declare function - extern function myfunc (input logic val); + // Pre-declare function + extern function myfunc (input logic val); - // Interface variable - logic data; + // Interface variable + logic data; - // Modport - modport mp_e( - export myfunc, - output data - ); + // Modport + modport mp_e( + export myfunc, + output data + ); - // Modport - modport mp_i( - import myfunc, - output data - ); + // Modport + modport mp_i( + import myfunc, + output data + ); endinterface // test_if -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - test_if i (); + test_if i (); - testmod_callee testmod_callee_i (.ie (i.mp_e)); - testmod_caller testmod_caller_i (.clk (clk), - .ii (i.mp_i)); + testmod_callee testmod_callee_i (.ie (i.mp_e)); + testmod_caller testmod_caller_i (.clk (clk), + .ii (i.mp_i)); endmodule -module testmod_callee - ( - test_if.mp_e ie - ); +module testmod_callee ( + test_if.mp_e ie +); - function automatic logic ie.myfunc (input logic val); - begin - myfunc = (val == 1'b0); - end - endfunction + function automatic logic ie.myfunc (input logic val); + begin + myfunc = (val == 1'b0); + end + endfunction endmodule // testmod_caller -module testmod_caller - ( - input clk, - test_if.mp_i ii - ); +module testmod_caller ( + input clk, + test_if.mp_i ii +); - always @(posedge clk) begin - ii.data = 1'b0; - if (ii.myfunc (1'b0)) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end + always @(posedge clk) begin + ii.data = 1'b0; + if (ii.myfunc (1'b0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_interface_modport_import.v b/test_regress/t/t_interface_modport_import.v index 681513633..56b11354a 100644 --- a/test_regress/t/t_interface_modport_import.v +++ b/test_regress/t/t_interface_modport_import.v @@ -8,52 +8,50 @@ interface test_if; - // Interface variable - logic data; + // Interface variable + logic data; - // Modport - modport mp( - import myfunc, - output data - ); + // Modport + modport mp(import myfunc, output data); - function automatic logic myfunc (input logic val); - begin - myfunc = (val == 1'b0); - end - endfunction + function automatic logic myfunc(input logic val); + begin + myfunc = (val == 1'b0); + end + endfunction -endinterface // test_if +endinterface // test_if -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - test_if i (); + test_if i (); - testmod testmod_i (.clk (clk), - .i (i.mp)); + testmod testmod_i ( + .clk(clk), + .i(i.mp) + ); endmodule -module testmod - ( - input clk, - test_if.mp i - ); +module testmod ( + input clk, + test_if.mp i +); - always @(posedge clk) begin - i.data = 1'b0; - if (i.myfunc (1'b0)) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end + always @(posedge clk) begin + i.data = 1'b0; + if (i.myfunc(1'b0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end endmodule diff --git a/test_regress/t/t_interface_modport_import_export_list.v b/test_regress/t/t_interface_modport_import_export_list.v index 398896f5e..4879552bb 100644 --- a/test_regress/t/t_interface_modport_import_export_list.v +++ b/test_regress/t/t_interface_modport_import_export_list.v @@ -7,50 +7,45 @@ // SPDX-License-Identifier: CC0-1.0 interface intf; - logic l; - function void f1(); - endfunction - function void f2(); - endfunction - function void f3(); - endfunction - function void f4(); - endfunction + logic l; + function void f1(); + endfunction + function void f2(); + endfunction + function void f3(); + endfunction + function void f4(); + endfunction - modport mpi - ( - import f1, f2, - input l, - import f3, f4 - ); - modport mpo - ( - output l, - import f1, f2, f3, f4 - ); + modport mpi(import f1, f2, input l, import f3, f4); + modport mpo(output l, import f1, f2, f3, f4); endinterface -module mo (intf.mpo intf0); - function void ef1(); - intf0.f1(); - intf0.f2(); - endfunction - function void ef2(); - intf0.f3(); - intf0.f4(); - endfunction +module mo ( + intf.mpo intf0 +); + function void ef1(); + intf0.f1(); + intf0.f2(); + endfunction + function void ef2(); + intf0.f3(); + intf0.f4(); + endfunction - initial begin - ef1(); - ef2(); - end + initial begin + ef1(); + ef2(); + end endmodule -module mi (intf.mpi intf0); +module mi ( + intf.mpi intf0 +); endmodule module t; - intf intf0(); - mi mi(.*); - mo mo(.*); + intf intf0 (); + mi mi (.*); + mo mo (.*); endmodule diff --git a/test_regress/t/t_interface_modportlist.v b/test_regress/t/t_interface_modportlist.v index dcab0b03b..199adb46c 100644 --- a/test_regress/t/t_interface_modportlist.v +++ b/test_regress/t/t_interface_modportlist.v @@ -6,19 +6,27 @@ //bug1246 -module t(input clk); - my_interface iface(); - my_module m(.clk(clk), .iface); +module t ( + input clk +); + my_interface iface (); + my_module m ( + .clk(clk), + .iface + ); endmodule -module my_module(input clk, my_interface.my_port iface); - always @(posedge clk) begin - iface.b <= iface.a; - iface.c <= iface.a; - end +module my_module ( + input clk, + my_interface.my_port iface +); + always @(posedge clk) begin + iface.b <= iface.a; + iface.c <= iface.a; + end endmodule interface my_interface; - logic a, b, c; - modport my_port(input a, output b, c); + logic a, b, c; + modport my_port(input a, output b, c); endinterface diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v index fe12a85c8..081330c37 100644 --- a/test_regress/t/t_interface_mp_func.v +++ b/test_regress/t/t_interface_mp_func.v @@ -4,32 +4,30 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface pads_if(); - modport mp_dig( - import fIn, - import fOut ); +interface pads_if (); + modport mp_dig(import fIn, import fOut); - integer exists[8]; - function automatic integer fIn (integer i); - fIn = exists[i]; - endfunction - task automatic fOut (integer i); - exists[i] = 33; - endtask + integer exists[8]; + function automatic integer fIn(integer i); + fIn = exists[i]; + endfunction + task automatic fOut(integer i); + exists[i] = 33; + endtask endinterface module t; - pads_if padsif[1:0](); - pads_if padsif_arr[1:0](); - initial begin - padsif[0].fOut(3); - if (padsif[0].fIn(3) != 33) $stop; + pads_if padsif[1:0] (); + pads_if padsif_arr[1:0] (); + initial begin + padsif[0].fOut(3); + if (padsif[0].fIn(3) != 33) $stop; - padsif_arr[0].fOut(3); - if (padsif_arr[0].fIn(3) != 33) $stop; - padsif_arr[1].fOut(3); - if (padsif_arr[1].fIn(3) != 33) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + padsif_arr[0].fOut(3); + if (padsif_arr[0].fIn(3) != 33) $stop; + padsif_arr[1].fOut(3); + if (padsif_arr[1].fIn(3) != 33) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_nansi.v b/test_regress/t/t_interface_nansi.v index 251b9af62..d8928ae1e 100644 --- a/test_regress/t/t_interface_nansi.v +++ b/test_regress/t/t_interface_nansi.v @@ -4,34 +4,40 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 -interface iface(input logic clk); - logic [31:0] d = 0; - logic [31:0] q = 0; +interface iface ( + input logic clk +); + logic [31:0] d = 0; + logic [31:0] q = 0; endinterface -module mod(a); - iface a; // This is not a CELL, it is a port declaration - always @(posedge a.clk) a.q <= a.d; +module mod ( + a +); + iface a; // This is not a CELL, it is a port declaration + always @(posedge a.clk) a.q <= a.d; endmodule -module t(clk); - input clk; +module t ( + clk +); + input clk; - iface iface_inst(clk); - mod mod_inst(iface_inst); + iface iface_inst (clk); + mod mod_inst (iface_inst); - int cyc = 0; + int cyc = 0; - always @(posedge clk) begin - iface_inst.d <= cyc; - if (cyc > 1 && iface_inst.q != cyc - 2) $stop; - end + always @(posedge clk) begin + iface_inst.d <= cyc; + if (cyc > 1 && iface_inst.q != cyc - 2) $stop; + end - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 100) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 100) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_interface_nest.v b/test_regress/t/t_interface_nest.v index 176bb5b45..d1cf6185e 100644 --- a/test_regress/t/t_interface_nest.v +++ b/test_regress/t/t_interface_nest.v @@ -5,71 +5,68 @@ // SPDX-License-Identifier: CC0-1.0 interface if1; - integer var1; + integer var1; endinterface interface if2; - if1 i1 (); - integer var2; + if1 i1 (); + integer var2; endinterface -module mod1 - ( - input clk, - input integer modnum, // Don't use parameter, want same module twice for better checking - if2 foo - ); +module mod1 ( + input clk, + input integer modnum, // Don't use parameter, want same module twice for better checking + if2 foo +); - logic l1, l2; + logic l1, l2; - always_ff @(posedge clk) begin - if (modnum==1) begin - if (foo.i1.var1 != 1) $stop; - if (foo.var2 != 2) $stop; - end - if (modnum==2) begin - if (foo.i1.var1 != 1) $stop; - if (foo.var2 != 2) $stop; - end - end + always_ff @(posedge clk) begin + if (modnum == 1) begin + if (foo.i1.var1 != 1) $stop; + if (foo.var2 != 2) $stop; + end + if (modnum == 2) begin + if (foo.i1.var1 != 1) $stop; + if (foo.var2 != 2) $stop; + end + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - if2 i2a (); - if2 i2b (); + if2 i2a (); + if2 i2b (); - assign i2a.i1.var1 = 1; - assign i2a.var2 = 2; - assign i2b.i1.var1 = 3; - assign i2b.var2 = 4; + assign i2a.i1.var1 = 1; + assign i2a.var2 = 2; + assign i2b.i1.var1 = 3; + assign i2b.var2 = 4; - mod1 mod1a - ( - .modnum (1), - .clk (clk), - .foo (i2a) - ); + mod1 mod1a ( + .modnum(1), + .clk(clk), + .foo(i2a) + ); - mod1 mod1b - ( - .modnum (2), - .clk (clk), - .foo (i2a) - ); + mod1 mod1b ( + .modnum(2), + .clk(clk), + .foo(i2a) + ); - integer cyc = 0; - always_ff @(posedge clk) begin - cyc <= cyc+1; - if (cyc==2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + integer cyc = 0; + always_ff @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_interface_notpublic.v b/test_regress/t/t_interface_notpublic.v index 83859db21..9c73c9d9f 100644 --- a/test_regress/t/t_interface_notpublic.v +++ b/test_regress/t/t_interface_notpublic.v @@ -4,26 +4,34 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -interface intf - (input wire clk, - input wire rst); - modport intf_modp (input clk, rst); +interface intf ( + input wire clk, + input wire rst +); + modport intf_modp(input clk, rst); endinterface module sub - // verilator public_on - (intf.intf_modp intf_port); +// verilator public_on +( + intf.intf_modp intf_port +); - always @ (posedge intf_port.clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end - // verilator public_off + always @(posedge intf_port.clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + // verilator public_off endmodule -module t(clk); - input clk /*verilator public*/ ; - logic rst; - intf the_intf (.clk, .rst); - sub the_sub (.intf_port (the_intf)); +module t ( + clk +); + input clk /*verilator public*/; + logic rst; + intf the_intf ( + .clk, + .rst + ); + sub the_sub (.intf_port(the_intf)); endmodule diff --git a/test_regress/t/t_interface_param1.v b/test_regress/t/t_interface_param1.v index d11e21b63..43530fb5d 100644 --- a/test_regress/t/t_interface_param1.v +++ b/test_regress/t/t_interface_param1.v @@ -6,47 +6,49 @@ //bug692 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input wire clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input wire clk; - wire [31:0] result; - test_if #(.ID(3)) s(); - sub_test U_SUB_TEST(s.a.b, result); // the line causing error + wire [31:0] result; + test_if #(.ID(3)) s (); + sub_test U_SUB_TEST ( + s.a.b, + result + ); // the line causing error endmodule : t // --------------------------------------------------------------------------- -module sub_test - ( - input [31:0] b, - output [31:0] c - ); - assign c = b; +module sub_test ( + input [31:0] b, + output [31:0] c +); + assign c = b; endmodule // --------------------------------------------------------------------------- -interface test_if - #(parameter ID = 0) - (); +interface test_if #( + parameter ID = 0 +) (); - typedef struct packed { - logic a; - logic [31:0] b; - } aType; + typedef struct packed { + logic a; + logic [31:0] b; + } aType; - aType a; + aType a; - typedef struct packed { - logic c; - logic [31:0] d; - } bType; + typedef struct packed { + logic c; + logic [31:0] d; + } bType; - bType b; + bType b; - modport master (input a, output b); + modport master(input a, output b); endinterface diff --git a/test_regress/t/t_interface_param2.v b/test_regress/t/t_interface_param2.v index ae08d1427..47a55651a 100644 --- a/test_regress/t/t_interface_param2.v +++ b/test_regress/t/t_interface_param2.v @@ -6,44 +6,49 @@ //bug1104 -module t (input clk); - simple_bus sb_intf(clk); - simple_bus #(.DWIDTH(16)) wide_intf(clk); - mem mem(sb_intf.slave); - cpu cpu(sb_intf.master); - mem memW(wide_intf.slave); - cpu cpuW(wide_intf.master); +module t ( + input clk +); + simple_bus sb_intf (clk); + simple_bus #(.DWIDTH(16)) wide_intf (clk); + mem mem (sb_intf.slave); + cpu cpu (sb_intf.master); + mem memW (wide_intf.slave); + cpu cpuW (wide_intf.master); endmodule -interface simple_bus #(AWIDTH = 8, DWIDTH = 8) - (input logic clk); // Define the interface +interface simple_bus #( + AWIDTH = 8, + DWIDTH = 8 +) ( + input logic clk +); // Define the interface - logic req, gnt; - logic [AWIDTH-1:0] addr; - logic [DWIDTH-1:0] data; + logic req, gnt; + logic [AWIDTH-1:0] addr; + logic [DWIDTH-1:0] data; - modport slave( input req, addr, clk, - output gnt, - input data); + modport slave(input req, addr, clk, output gnt, input data); - modport master(input gnt, clk, - output req, addr, - output data); + modport master(input gnt, clk, output req, addr, output data); - initial begin - if (DWIDTH != 8 && DWIDTH != 16) $stop; - end -endinterface: simple_bus + initial begin + if (DWIDTH != 8 && DWIDTH != 16) $stop; + end +endinterface : simple_bus -module mem(interface a); - logic avail; - always @(posedge a.clk) - a.gnt <= a.req & avail; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end +module mem ( + interface a +); + logic avail; + always @(posedge a.clk) a.gnt <= a.req & avail; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module cpu(interface b); +module cpu ( + interface b +); endmodule diff --git a/test_regress/t/t_interface_param_genblk.out b/test_regress/t/t_interface_param_genblk.out index d62918ec4..7e38eeeda 100644 --- a/test_regress/t/t_interface_param_genblk.out +++ b/test_regress/t/t_interface_param_genblk.out @@ -1,24 +1,24 @@ --Info: t/t_interface_param_genblk.v:35:9: correct +-Info: t/t_interface_param_genblk.v:32:5: correct : ... note: In instance 't.i_sub' - 35 | $info("correct"); - | ^~~~~ --Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 2 + 32 | $info("correct"); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:42:7: i = 98, j = 2 + : ... note: In instance 't.i_sub' + 42 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:42:7: i = 98, j = 1 + : ... note: In instance 't.i_sub' + 42 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:42:7: i = 100, j = 2 + : ... note: In instance 't.i_sub' + 42 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:42:7: i = 100, j = 1 + : ... note: In instance 't.i_sub' + 42 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:48:18: correct : ... note: In instance 't.i_sub' - 44 | $info("i = %0d, j = %0d", i, j); - | ^~~~~ --Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 1 - : ... note: In instance 't.i_sub' - 44 | $info("i = %0d, j = %0d", i, j); - | ^~~~~ --Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 2 - : ... note: In instance 't.i_sub' - 44 | $info("i = %0d, j = %0d", i, j); - | ^~~~~ --Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 1 - : ... note: In instance 't.i_sub' - 44 | $info("i = %0d, j = %0d", i, j); - | ^~~~~ --Info: t/t_interface_param_genblk.v:50:26: correct - : ... note: In instance 't.i_sub' - 50 | intf.B * 50: $info("correct"); - | ^~~~~ + 48 | intf.B * 50: $info("correct"); + | ^~~~~ diff --git a/test_regress/t/t_interface_param_genblk.v b/test_regress/t/t_interface_param_genblk.v index 9597e2034..c70986b4b 100644 --- a/test_regress/t/t_interface_param_genblk.v +++ b/test_regress/t/t_interface_param_genblk.v @@ -9,46 +9,46 @@ interface intf #( parameter A = 10 ); - localparam B = A / A + 1; // 2 + localparam B = A / A + 1; // 2 - logic [A/10-1:0] sig; + logic [A/10-1:0] sig; endinterface module t; - intf #( - .A(100) - ) intf(); + intf #(.A(100)) intf (); - sub i_sub ( - .intf - ); + sub i_sub (.intf); endmodule module sub ( - intf intf // Having this named same "intf intf" important for V3LinkDot coverage + intf intf // Having this named same "intf intf" important for V3LinkDot coverage ); - if (intf.A == 10) begin - $error("incorrect"); - end else if (intf.A / intf.B == 50) begin + if (intf.A == 10) begin + $error("incorrect"); + end + else if (intf.A / intf.B == 50) begin // end else if (intf.A / $bits(intf.sig) == 10) begin // TODO: support this - $info("correct"); - end else begin - $error("incorrect"); - end + $info("correct"); + end + else begin + $error("incorrect"); + end - for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin - for (genvar j = intf.B; j > intf.A - 100; j--) begin - if (i < intf.A - 2) $error("error"); - if (i > intf.A) $error("error"); - $info("i = %0d, j = %0d", i, j); - end + for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin + for (genvar j = intf.B; j > intf.A - 100; j--) begin + if (i < intf.A - 2) $error("error"); + if (i > intf.A) $error("error"); + $info("i = %0d, j = %0d", i, j); end + end - case (intf.A) - 10, intf.A - 10: $error("incorrect"); - intf.B * 50: $info("correct"); - 30: $error("incorrect"); - default: $error("incorrect"); - endcase + case (intf.A) + 10, intf.A - 10: $error("incorrect"); + intf.B * 50: $info("correct"); + 30: $error("incorrect"); + default: $error( + "incorrect" + ); + endcase endmodule diff --git a/test_regress/t/t_interface_parameter_access.v b/test_regress/t/t_interface_parameter_access.v index 3adf7a20c..3755bf84d 100644 --- a/test_regress/t/t_interface_parameter_access.v +++ b/test_regress/t/t_interface_parameter_access.v @@ -6,147 +6,145 @@ // SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 -interface test_if #(parameter integer FOO = 1); +interface test_if #( + parameter integer FOO = 1 +); - // Interface variable - logic data; + // Interface variable + logic data; - localparam integer BAR = FOO + 1; + localparam integer BAR = FOO + 1; - // Modport - modport mp( - import getFoo, - output data - ); + // Modport + modport mp(import getFoo, output data); - function integer getFoo (); - return FOO; - endfunction + function integer getFoo(); + return FOO; + endfunction -endinterface // test_if +endinterface // test_if -function integer identity (input integer x); - return x; +function integer identity(input integer x); + return x; endfunction -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - test_if #( .FOO (identity(5)) ) the_interface (); - test_if #( .FOO (identity(7)) ) array_interface [1:0] (); + test_if #(.FOO(identity(5))) the_interface (); + test_if #(.FOO(identity(7))) array_interface[1:0] (); - testmod testmod_i (.clk (clk), - .intf (the_interface), - .intf_no_mp (the_interface), - .intf_array (array_interface) - ); + testmod testmod_i ( + .clk(clk), + .intf(the_interface), + .intf_no_mp(the_interface), + .intf_array(array_interface) + ); - // verilator lint_off HIERPARAM - localparam THE_TOP_FOO = the_interface.FOO; - localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); - localparam THE_ARRAY_FOO = array_interface[0].FOO; - // verilator lint_on HIERPARAM + // verilator lint_off HIERPARAM + localparam THE_TOP_FOO = the_interface.FOO; + localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); + localparam THE_ARRAY_FOO = array_interface[0].FOO; + // verilator lint_on HIERPARAM - initial begin - if (THE_TOP_FOO != 5) begin - $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); - $stop; - end - if (THE_TOP_FOO_BITS != 64) begin - $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); - $stop; - end - if (THE_ARRAY_FOO != 7) begin - $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); - $stop; - end - end + initial begin + if (THE_TOP_FOO != 5) begin + $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); + $stop; + end + if (THE_TOP_FOO_BITS != 64) begin + $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); + $stop; + end + if (THE_ARRAY_FOO != 7) begin + $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); + $stop; + end + end endmodule -module testmod - #(parameter SOME_PARAM = 789) - ( - input clk, - test_if.mp intf, - test_if intf_no_mp, - test_if.mp intf_array [1:0] - ); +module testmod #( + parameter SOME_PARAM = 789 +) ( + input clk, + test_if.mp intf, + test_if intf_no_mp, + test_if.mp intf_array[1:0] +); - test_if #(.FOO (intf.FOO)) some_other_intf (); + test_if #(.FOO(intf.FOO)) some_other_intf (); - // verilator lint_off HIERPARAM - localparam THE_FOO = intf.FOO; - localparam THE_OTHER_FOO = intf_no_mp.FOO; - localparam THE_ARRAY_FOO = intf_array[0].FOO; - localparam THE_BAR = intf.BAR; - localparam THE_OTHER_BAR = intf_no_mp.BAR; - localparam THE_ARRAY_BAR = intf_array[0].BAR; - // verilator lint_on HIERPARAM + // verilator lint_off HIERPARAM + localparam THE_FOO = intf.FOO; + localparam THE_OTHER_FOO = intf_no_mp.FOO; + localparam THE_ARRAY_FOO = intf_array[0].FOO; + localparam THE_BAR = intf.BAR; + localparam THE_OTHER_BAR = intf_no_mp.BAR; + localparam THE_ARRAY_BAR = intf_array[0].BAR; + // verilator lint_on HIERPARAM - always @(posedge clk) begin - if (THE_FOO != 5) begin - $display("%%Error: THE_FOO = %0d", THE_FOO); - $stop; - end - if (some_other_intf.FOO != 5) begin - $display("%%Error: some_other_intf.FOO = %0d", some_other_intf.FOO); - $stop; - end - if (THE_OTHER_FOO != 5) begin - $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); - $stop; - end - if (THE_ARRAY_FOO != 7) begin - $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); - $stop; - end - if (intf.FOO != 5) begin - $display("%%Error: intf.FOO = %0d", intf.FOO); - $stop; - end - if (intf_no_mp.FOO != 5) begin - $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); - $stop; - end - if (intf_array[0].FOO != 7) begin - $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); - $stop; - end - // if (i.getFoo() != 5) begin - // $display("%%Error: i.getFoo() = %0d", i.getFoo()); - // $stop; - // end - if (THE_BAR != 6) begin - $display("%%Error: THE_BAR = %0d", THE_BAR); - $stop; - end - if (THE_OTHER_BAR != 6) begin - $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); - $stop; - end - if (THE_ARRAY_BAR != 8) begin - $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); - $stop; - end - if (intf.BAR != 6) begin - $display("%%Error: intf.BAR = %0d", intf.BAR); - $stop; - end - if (intf_no_mp.BAR != 6) begin - $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); - $stop; - end - if (intf_array[0].BAR != 8) begin - $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (THE_FOO != 5) begin + $display("%%Error: THE_FOO = %0d", THE_FOO); + $stop; + end + if (some_other_intf.FOO != 5) begin + $display("%%Error: some_other_intf.FOO = %0d", some_other_intf.FOO); + $stop; + end + if (THE_OTHER_FOO != 5) begin + $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); + $stop; + end + if (THE_ARRAY_FOO != 7) begin + $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); + $stop; + end + if (intf.FOO != 5) begin + $display("%%Error: intf.FOO = %0d", intf.FOO); + $stop; + end + if (intf_no_mp.FOO != 5) begin + $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); + $stop; + end + if (intf_array[0].FOO != 7) begin + $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); + $stop; + end + // if (i.getFoo() != 5) begin + // $display("%%Error: i.getFoo() = %0d", i.getFoo()); + // $stop; + // end + if (THE_BAR != 6) begin + $display("%%Error: THE_BAR = %0d", THE_BAR); + $stop; + end + if (THE_OTHER_BAR != 6) begin + $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); + $stop; + end + if (THE_ARRAY_BAR != 8) begin + $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); + $stop; + end + if (intf.BAR != 6) begin + $display("%%Error: intf.BAR = %0d", intf.BAR); + $stop; + end + if (intf_no_mp.BAR != 6) begin + $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); + $stop; + end + if (intf_array[0].BAR != 8) begin + $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_paren_missing_bad.out b/test_regress/t/t_interface_paren_missing_bad.out index 573097bdc..1ab8b865c 100644 --- a/test_regress/t/t_interface_paren_missing_bad.out +++ b/test_regress/t/t_interface_paren_missing_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_interface_paren_missing_bad.v:13:4: Interface 'intf' not connected as parent's interface not connected +%Error: t/t_interface_paren_missing_bad.v:13:3: Interface 'intf' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 13 | intf intf_i; - | ^~~~ + 13 | intf intf_i; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_paren_missing_bad.v b/test_regress/t/t_interface_paren_missing_bad.v index 07da0d1b1..d5a6be601 100644 --- a/test_regress/t/t_interface_paren_missing_bad.v +++ b/test_regress/t/t_interface_paren_missing_bad.v @@ -10,6 +10,6 @@ interface intf; endinterface module t; - intf intf_i; - initial $finish; + intf intf_i; + initial $finish; endmodule diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v index 211c2dbed..08b25dc5c 100644 --- a/test_regress/t/t_interface_ref_trace.v +++ b/test_regress/t/t_interface_ref_trace.v @@ -7,106 +7,109 @@ // Test for trace file interface aliasing typedef struct packed { - integer val100; - integer val200; + integer val100; + integer val200; } struct_t; // This interface is not connected to any cells -interface ifc_inner(input integer cyc); - integer value; +interface ifc_inner ( + input integer cyc +); + integer value; endinterface -interface ifc (input logic clk, - input integer cyc); - integer value; - struct_t the_struct; - ifc_inner inner (.*); +interface ifc ( + input logic clk, + input integer cyc +); + integer value; + struct_t the_struct; + ifc_inner inner (.*); endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc = 0; + integer cyc = 0; - ifc intf_1(.*); - ifc intf_2(.*); + ifc intf_1 (.*); + ifc intf_2 (.*); - always @(*) begin - intf_1.value = cyc + 1; - intf_2.value = cyc + 2; - end + always @(*) begin + intf_1.value = cyc + 1; + intf_2.value = cyc + 2; + end - sub_struct s1 (.intf_for_struct(intf_1)); - sub_struct s2 (.intf_for_struct(intf_2)); - sub_check c1 (.intf_for_check(intf_1)); - sub_check c2 (.intf_for_check(intf_2)); - sub_all a (.intf_one(intf_1), - .intf_two(intf_2)); - // Intentionally longer scope name - sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2), - .intf_two(intf_1)); + sub_struct s1 (.intf_for_struct(intf_1)); + sub_struct s2 (.intf_for_struct(intf_2)); + sub_check c1 (.intf_for_check(intf_1)); + sub_check c2 (.intf_for_check(intf_2)); + sub_all a ( + .intf_one(intf_1), + .intf_two(intf_2) + ); + // Intentionally longer scope name + sub_all abcdefghijklmnopqrstuvwxyz ( + .intf_one(intf_2), + .intf_two(intf_1) + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (intf_1.value != 21) $stop; - if (intf_2.value != 22) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (intf_1.value != 21) $stop; + if (intf_2.value != 22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module sub_struct - ( - ifc intf_for_struct - ); +module sub_struct ( + ifc intf_for_struct +); - always @(*) begin - intf_for_struct.the_struct.val100 = intf_for_struct.value + 100; - intf_for_struct.the_struct.val200 = intf_for_struct.value + 200; - end + always @(*) begin + intf_for_struct.the_struct.val100 = intf_for_struct.value + 100; + intf_for_struct.the_struct.val200 = intf_for_struct.value + 200; + end endmodule -module sub_check - ( - ifc intf_for_check - ); +module sub_check ( + ifc intf_for_check +); `ifdef NO_INLINE_A - //verilator no_inline_module + //verilator no_inline_module `endif - always @(posedge intf_for_check.clk) begin - if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop; - if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop; - end + always @(posedge intf_for_check.clk) begin + if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop; + if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop; + end endmodule -module sub_all - ( - ifc intf_one, - ifc intf_two - ); +module sub_all ( + ifc intf_one, + ifc intf_two +); `ifdef NO_INLINE_B - //verilator no_inline_module + //verilator no_inline_module `endif - ifc intf_in_sub_all ( - .clk(intf_one.clk), - .cyc(intf_one.cyc) - ); - assign intf_in_sub_all.value = intf_one.value + 1000; + ifc intf_in_sub_all ( + .clk(intf_one.clk), + .cyc(intf_one.cyc) + ); + assign intf_in_sub_all.value = intf_one.value + 1000; - sub_check ac1 (.intf_for_check(intf_one)); - sub_check ac2 (.intf_for_check(intf_two)); - sub_struct as3 (.intf_for_struct(intf_in_sub_all)); - sub_check ac3 (.intf_for_check(intf_in_sub_all)); + sub_check ac1 (.intf_for_check(intf_one)); + sub_check ac2 (.intf_for_check(intf_two)); + sub_struct as3 (.intf_for_struct(intf_in_sub_all)); + sub_check ac3 (.intf_for_check(intf_in_sub_all)); endmodule diff --git a/test_regress/t/t_interface_size_bad.out b/test_regress/t/t_interface_size_bad.out index 936b09eac..e4ce1eb32 100644 --- a/test_regress/t/t_interface_size_bad.out +++ b/test_regress/t/t_interface_size_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_interface_size_bad.v:16:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. +%Error: t/t_interface_size_bad.v:16:19: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. : ... note: In instance 't' - 16 | baz baz4_inst (.foo(foo4)); - | ^~~ + 16 | baz baz4_inst (.foo(foo4)); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_size_bad.v:17:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. +%Error: t/t_interface_size_bad.v:17:19: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. : ... note: In instance 't' - 17 | baz baz6_inst (.foo(foo6)); - | ^~~ + 17 | baz baz6_inst (.foo(foo6)); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_size_bad.v b/test_regress/t/t_interface_size_bad.v index b02af2043..1ea08d36e 100644 --- a/test_regress/t/t_interface_size_bad.v +++ b/test_regress/t/t_interface_size_bad.v @@ -5,18 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - logic a; + logic a; endinterface module t; - localparam N = 4; - foo_intf foo4 [N-1:0] (); - foo_intf foo6 [5:0] (); + localparam N = 4; + foo_intf foo4[N-1:0] (); + foo_intf foo6[5:0] (); - baz baz4_inst (.foo(foo4)); - baz baz6_inst (.foo(foo6)); + baz baz4_inst (.foo(foo4)); + baz baz6_inst (.foo(foo6)); endmodule -module baz(foo_intf foo[4:0] ); +module baz ( + foo_intf foo[4:0] +); endmodule diff --git a/test_regress/t/t_interface_star.v b/test_regress/t/t_interface_star.v index 0f540d3a4..57dc2fb30 100644 --- a/test_regress/t/t_interface_star.v +++ b/test_regress/t/t_interface_star.v @@ -4,41 +4,44 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc=1; + integer cyc = 1; - counter_io c_data(); + counter_io c_data (); - counter_ansi c1 (.clk, .*); + counter_ansi c1 ( + .clk, + .* + ); - counter_ansi c2 (.clk, .c_data); + counter_ansi c2 ( + .clk, + .c_data + ); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (c_data.value != 12345) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (c_data.value != 12345) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule interface counter_io; integer value; endinterface -module counter_ansi - ( - input clk, - counter_io c_data - ); +module counter_ansi ( + input clk, + counter_io c_data +); - always_ff @ (posedge clk) begin - c_data.value <= 12345; - end + always_ff @(posedge clk) begin + c_data.value <= 12345; + end endmodule : counter_ansi diff --git a/test_regress/t/t_interface_top_bad.out b/test_regress/t/t_interface_top_bad.out index 418f785fc..cea615259 100644 --- a/test_regress/t/t_interface_top_bad.out +++ b/test_regress/t/t_interface_top_bad.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module - 17 | ifc.counter_mp c_data - | ^~~~~~ +%Error-UNSUPPORTED: t/t_interface_top_bad.v:16:20: Unsupported: Interfaced port on top level module + 16 | ifc.counter_mp c_data + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_interface_top_bad.v:17:4: Interface 'ifc' not connected as parent's interface not connected +%Error: t/t_interface_top_bad.v:16:5: Interface 'ifc' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 17 | ifc.counter_mp c_data - | ^~~ + 16 | ifc.counter_mp c_data + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_top_bad.v b/test_regress/t/t_interface_top_bad.v index d7c74e7b8..79678987b 100644 --- a/test_regress/t/t_interface_top_bad.v +++ b/test_regress/t/t_interface_top_bad.v @@ -5,18 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - logic [3:0] value; - logic reset; - modport counter_mp (input reset, output value); - modport core_mp (output reset, input value); + logic [3:0] value; + logic reset; + modport counter_mp(input reset, output value); + modport core_mp(output reset, input value); endinterface -module t - (// Inputs - input clk, - ifc.counter_mp c_data - ); +module t ( // Inputs + input clk, + ifc.counter_mp c_data +); - integer cyc=1; + integer cyc = 1; endmodule diff --git a/test_regress/t/t_interface_twod.v b/test_regress/t/t_interface_twod.v index 95032d9d2..0545f93d5 100644 --- a/test_regress/t/t_interface_twod.v +++ b/test_regress/t/t_interface_twod.v @@ -5,44 +5,45 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - integer value; - modport i (output value); - modport o (input value); + integer value; + modport i(output value); + modport o(input value); endinterface -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc=1; +module t ( + input clk +); - ifc itop1a(), - itop1b(); + integer cyc = 1; - wrapper c1 (.isuba(itop1a), - .isubb(itop1b), - .i_valuea(14), - .i_valueb(15)); + ifc itop1a (), itop1b (); - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==20) begin - if (itop1a.value != 14) $stop; - if (itop1b.value != 15) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + wrapper c1 ( + .isuba(itop1a), + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15) + ); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module wrapper - ( - ifc.i isuba, isubb, - input integer i_valuea, i_valueb - ); - always @* begin - isuba.value = i_valuea; - isubb.value = i_valueb; - end +module wrapper ( + ifc.i isuba, + isubb, + input integer i_valuea, + i_valueb +); + always @* begin + isuba.value = i_valuea; + isubb.value = i_valueb; + end endmodule diff --git a/test_regress/t/t_interface_typo_bad.out b/test_regress/t/t_interface_typo_bad.out index 330ae193f..c9d4f54c3 100644 --- a/test_regress/t/t_interface_typo_bad.out +++ b/test_regress/t/t_interface_typo_bad.out @@ -1,13 +1,13 @@ -%Error: t/t_interface_typo_bad.v:14:4: Interface 'foo_intf' not connected as parent's interface not connected +%Error: t/t_interface_typo_bad.v:13:5: Interface 'foo_intf' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 14 | foo_intf foo - | ^~~~~~~~ + 13 | foo_intf foo + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' - 22 | fo_intf the_foo(); - | ^~~~~~~ -%Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable - 27 | .foo (the_foo) - | ^~~~~~~ +%Error: t/t_interface_typo_bad.v:21:3: Cannot find file containing interface: 'fo_intf' + 21 | fo_intf the_foo (); + | ^~~~~~~ +%Error: t/t_interface_typo_bad.v:23:28: Found definition of 'the_foo' as a CELL but expected a variable + 23 | submod submod_inst (.foo(the_foo)); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v index f7da3da16..d3f9c30ce 100644 --- a/test_regress/t/t_interface_typo_bad.v +++ b/test_regress/t/t_interface_typo_bad.v @@ -9,22 +9,17 @@ interface foo_intf; endinterface -module submod - ( - foo_intf foo - ); +module submod ( + foo_intf foo +); endmodule module t; - // Intentional typo, compiler should point this out, or that fo_intf does - // not match foo_intf on the submod port map - fo_intf the_foo(); + // Intentional typo, compiler should point this out, or that fo_intf does + // not match foo_intf on the submod port map + fo_intf the_foo (); - submod - submod_inst - ( - .foo (the_foo) - ); + submod submod_inst (.foo(the_foo)); endmodule diff --git a/test_regress/t/t_interface_virtual.v b/test_regress/t/t_interface_virtual.v index bbd93b75c..266465594 100644 --- a/test_regress/t/t_interface_virtual.v +++ b/test_regress/t/t_interface_virtual.v @@ -7,80 +7,86 @@ // See also t_interface_virtual_bad.v interface PBus; - logic req, grant; - logic [7:0] addr, data; - modport phy(input addr, ref data); + logic req, grant; + logic [7:0] addr, data; + modport phy(input addr, ref data); endinterface typedef virtual PBus vpbus_t; typedef vpbus_t vpbus2_t; class Cls; - vpbus2_t fa, fb; + vpbus2_t fa, fb; endclass -class Clsgen#(type T = logic); - T x[0:3]; +class Clsgen #( + type T = logic +); + T x[0:3]; endclass module t; - PBus ia(), ib(); - virtual PBus va, vb; - virtual PBus.phy pa, pb; - Cls ca, cb; - Clsgen#(virtual PBus) gen; + PBus ia (), ib (); + virtual PBus va, vb; + virtual PBus.phy pa, pb; + Cls ca, cb; + Clsgen #(virtual PBus) gen; - initial begin - va = ia; - vb = ia; + initial begin + va = ia; + vb = ia; - if (va == null) $stop; + if (va == null) $stop; - $display("va==vb? %b", va==vb); - $display("va!=vb? %b", va!=vb); - vb = ib; - $display("va==vb? %b", va==vb); - $display("va!=vb? %b", va!=vb); + $display("va==vb? %b", va == vb); + $display("va!=vb? %b", va != vb); + vb = ib; + $display("va==vb? %b", va == vb); + $display("va!=vb? %b", va != vb); - ca = new; - cb = new; - gen = new; + ca = new; + cb = new; + gen = new; - va.addr = 8'haa; - ia.data = 8'h11; + va.addr = 8'haa; + ia.data = 8'h11; - vb.addr = 8'hbb; - ib.data = 8'h22; + vb.addr = 8'hbb; + ib.data = 8'h22; - $display("va.addr=%x", va.addr, " va.data=%x", va.data, " ia.addr=%x", ia.addr, " ia.data=%x", ia.data); - $display("vb.addr=%x", vb.addr, " vb.data=%x", vb.data, " ib.addr=%x", ib.addr, " ib.data=%x", ib.data); + $display("va.addr=%x", va.addr, " va.data=%x", va.data, " ia.addr=%x", ia.addr, " ia.data=%x", + ia.data); + $display("vb.addr=%x", vb.addr, " vb.data=%x", vb.data, " ib.addr=%x", ib.addr, " ib.data=%x", + ib.data); - if (ca.fa) $stop; + if (ca.fa) $stop; - ca.fa = ia; - ca.fb = ib; - cb.fa = ib; - cb.fb = ia; - gen.x[0] = va; - gen.x[1] = vb; + ca.fa = ia; + ca.fb = ib; + cb.fa = ib; + cb.fb = ia; + gen.x[0] = va; + gen.x[1] = vb; - if (ca == null) $stop; - if (ca.fa == null) $stop; - if (!ca.fa ) $stop; + if (ca == null) $stop; + if (ca.fa == null) $stop; + if (!ca.fa) $stop; - pa = va; - pb = vb; + pa = va; + pb = vb; - pb.addr = 8'hb0; - pa.addr = 8'ha0; + pb.addr = 8'hb0; + pa.addr = 8'ha0; - $display("ca.fa.addr=%x", ca.fa.addr, " ca.fa.data=%x", ca.fa.data, " ca.fa.addr=%x", ca.fb.addr, " ca.fb.data=%x", ca.fb.data); - $display("cb.fa.addr=%x", cb.fa.addr, " cb.fa.data=%x", cb.fa.data, " cb.fa.addr=%x", cb.fb.addr, " cb.fb.data=%x", cb.fb.data); - $display("gen.x[0].addr=%x", gen.x[0].addr, " gen.x[1].addr=%x", gen.x[1].addr); - $display("gen=%p", gen); + $display("ca.fa.addr=%x", ca.fa.addr, " ca.fa.data=%x", ca.fa.data, " ca.fa.addr=%x", + ca.fb.addr, " ca.fb.data=%x", ca.fb.data); + $display("cb.fa.addr=%x", cb.fa.addr, " cb.fa.data=%x", cb.fa.data, " cb.fa.addr=%x", + cb.fb.addr, " cb.fb.data=%x", cb.fb.data); + $display("gen.x[0].addr=%x", gen.x[0].addr, " gen.x[1].addr=%x", gen.x[1].addr); + $display("gen=%p", gen); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_virtual_bad.out b/test_regress/t/t_interface_virtual_bad.out index 7631a10d3..e1bbe8819 100644 --- a/test_regress/t/t_interface_virtual_bad.out +++ b/test_regress/t/t_interface_virtual_bad.out @@ -1,35 +1,35 @@ -%Error: t/t_interface_virtual_bad.v:31:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'q8' is a different interface ('QBus'). +%Error: t/t_interface_virtual_bad.v:31:10: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'q8' is a different interface ('QBus'). : ... note: In instance 't' - 31 | v8 = q8; - | ^~ + 31 | v8 = q8; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_virtual_bad.v:35:12: Operator ASSIGN expected no interface modport on Assign RHS but got 'phy' modport. +%Error: t/t_interface_virtual_bad.v:35:10: Operator ASSIGN expected no interface modport on Assign RHS but got 'phy' modport. : ... note: In instance 't' - 35 | v8 = v8_phy; + 35 | v8 = v8_phy; + | ^~~~~~ +%Error: t/t_interface_virtual_bad.v:37:15: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. + : ... note: In instance 't' + 37 | data = p8.phy; + | ^~~ +%Error: t/t_interface_virtual_bad.v:38:12: Operator ASSIGN expected non-interface on Assign RHS but 'v8_phy' is an interface. + : ... note: In instance 't' + 38 | data = v8_phy; | ^~~~~~ -%Error: t/t_interface_virtual_bad.v:37:17: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. +%Error: t/t_interface_virtual_bad.v:39:12: Operator ASSIGN expected non-interface on Assign RHS but 'v8' is an interface. : ... note: In instance 't' - 37 | data = p8.phy; - | ^~~ -%Error: t/t_interface_virtual_bad.v:38:14: Operator ASSIGN expected non-interface on Assign RHS but 'v8_phy' is an interface. + 39 | data = v8; + | ^~ +%Error: t/t_interface_virtual_bad.v:40:12: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. : ... note: In instance 't' - 38 | data = v8_phy; - | ^~~~~~ -%Error: t/t_interface_virtual_bad.v:39:14: Operator ASSIGN expected non-interface on Assign RHS but 'v8' is an interface. + 40 | data = p8; + | ^~ +%Error: t/t_interface_virtual_bad.v:41:10: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'data' is not an interface. : ... note: In instance 't' - 39 | data = v8; - | ^~ -%Error: t/t_interface_virtual_bad.v:40:14: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. - : ... note: In instance 't' - 40 | data = p8; - | ^~ -%Error: t/t_interface_virtual_bad.v:41:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'data' is not an interface. - : ... note: In instance 't' - 41 | v8 = data; - | ^~~~ -%Error: t/t_interface_virtual_bad.v:44:79: Member 'gran' not found in interface 'PBus' + 41 | v8 = data; + | ^~~~ +%Error: t/t_interface_virtual_bad.v:44:77: Member 'gran' not found in interface 'PBus' : ... note: In instance 't' : ... Suggested alternative: 'grant' - 44 | $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); - | ^~~~ + 44 | $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_virtual_bad.v b/test_regress/t/t_interface_virtual_bad.v index 923a4352f..8c484e9c1 100644 --- a/test_regress/t/t_interface_virtual_bad.v +++ b/test_regress/t/t_interface_virtual_bad.v @@ -7,9 +7,9 @@ // See also t_interface_virtual.v interface PBus; - logic req, grant; - logic [7:0] addr, data; - modport phy(input addr, ref data); + logic req, grant; + logic [7:0] addr, data; + modport phy(input addr, ref data); endinterface interface QBus; @@ -19,31 +19,31 @@ typedef virtual PBus vpbus_t; module t; - PBus p8(); - QBus q8(); - vpbus_t v8; - virtual PBus.phy v8_phy; - logic data; + PBus p8 (); + QBus q8 (); + vpbus_t v8; + virtual PBus.phy v8_phy; + logic data; - initial begin - v8 = p8; - p8 = v8; // error - v8 = q8; // error - v8_phy = p8; - v8_phy = v8; - v8_phy = p8.phy; - v8 = v8_phy; // error - v8 = p8.phy; // error - data = p8.phy; // error - data = v8_phy; // error - data = v8; // error - data = p8; // error - v8 = data; // error - v8.grant = 1'b1; + initial begin + v8 = p8; + p8 = v8; // error + v8 = q8; // error + v8_phy = p8; + v8_phy = v8; + v8_phy = p8.phy; + v8 = v8_phy; // error + v8 = p8.phy; // error + data = p8.phy; // error + data = v8_phy; // error + data = v8; // error + data = p8; // error + v8 = data; // error + v8.grant = 1'b1; - $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); + $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_virtual_controlflow.v b/test_regress/t/t_interface_virtual_controlflow.v index 8a9423728..85740a0ba 100644 --- a/test_regress/t/t_interface_virtual_controlflow.v +++ b/test_regress/t/t_interface_virtual_controlflow.v @@ -5,69 +5,69 @@ // SPDX-License-Identifier: CC0-1.0 interface Bus1; - logic [15:0] data; + logic [15:0] data; endinterface interface Bus2; - logic [15:0] data; + logic [15:0] data; endinterface interface Bus3; - logic [15:0] data; + logic [15:0] data; endinterface module t_controlflow; - logic clk = 0; - integer cyc = 0; - Bus1 intf1(); - Bus2 intf2(); - Bus3 intf3(), intf4(); - virtual Bus1 vif1 = intf1; - virtual Bus2 vif2 = intf2; - virtual Bus3 vif3 = intf3, vif4 = intf4; + logic clk = 0; + integer cyc = 0; + Bus1 intf1 (); + Bus2 intf2 (); + Bus3 intf3 (), intf4 (); + virtual Bus1 vif1 = intf1; + virtual Bus2 vif2 = intf2; + virtual Bus3 vif3 = intf3, vif4 = intf4; - // Finish on negedge so that $finish is last - always @(negedge clk) begin - if (cyc >= 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Finish on negedge so that $finish is last + always @(negedge clk) begin + if (cyc >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; end + end - function void assign_to_intf3(); - intf3.data = 'hcafe; - endfunction + function void assign_to_intf3(); + intf3.data = 'hcafe; + endfunction - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead; - else vif2.data = 'hbeef; - if (cyc == 1 || cyc == 3 || cyc == 5) begin - if (cyc < 3) intf3.data = 'hfafa; - intf4.data = 'hface; - end - if (cyc == 7) begin - intf4.data = 'hcafe; - end - if (cyc == 9) begin - assign_to_intf3; - intf4.data = 'hdeaf; - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead; + else vif2.data = 'hbeef; + if (cyc == 1 || cyc == 3 || cyc == 5) begin + if (cyc < 3) intf3.data = 'hfafa; + intf4.data = 'hface; end + if (cyc == 7) begin + intf4.data = 'hcafe; + end + if (cyc == 9) begin + assign_to_intf3; + intf4.data = 'hdeaf; + end + end - always @(vif1.data) begin - $write("[%0t] vif1.data==%h\n", $time, vif1.data); - end - always @(intf2.data) begin - $write("[%0t] intf2.data==%h\n", $time, intf2.data); - end - always @(vif3.data) begin - $write("[%0t] vif3.data==%h\n", $time, vif3.data); - end - always @(intf4.data) begin - $write("[%0t] intf4.data==%h\n", $time, intf4.data); - end + always @(vif1.data) begin + $write("[%0t] vif1.data==%h\n", $time, vif1.data); + end + always @(intf2.data) begin + $write("[%0t] intf2.data==%h\n", $time, intf2.data); + end + always @(vif3.data) begin + $write("[%0t] vif3.data==%h\n", $time, vif3.data); + end + always @(intf4.data) begin + $write("[%0t] intf4.data==%h\n", $time, intf4.data); + end - initial begin - repeat (20) #5ns clk = ~clk; - end + initial begin + repeat (20) #5ns clk = ~clk; + end endmodule diff --git a/test_regress/t/t_interface_virtual_missing_bad.out b/test_regress/t/t_interface_virtual_missing_bad.out index c8d485e15..5f3622109 100644 --- a/test_regress/t/t_interface_virtual_missing_bad.out +++ b/test_regress/t/t_interface_virtual_missing_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_virtual_missing_bad.v:9:12: Cannot find file containing interface: 'foo' - 9 | virtual foo vif; - | ^~~ +%Error: t/t_interface_virtual_missing_bad.v:9:11: Cannot find file containing interface: 'foo' + 9 | virtual foo vif; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_virtual_missing_bad.v b/test_regress/t/t_interface_virtual_missing_bad.v index 2196f25ff..3b60433d4 100644 --- a/test_regress/t/t_interface_virtual_missing_bad.v +++ b/test_regress/t/t_interface_virtual_missing_bad.v @@ -6,10 +6,10 @@ module t; - virtual foo vif; + virtual foo vif; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_virtual_opt.v b/test_regress/t/t_interface_virtual_opt.v index c9e1a85f4..23192a766 100644 --- a/test_regress/t/t_interface_virtual_opt.v +++ b/test_regress/t/t_interface_virtual_opt.v @@ -5,38 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 interface Bus; - logic [7:0] data; + logic [7:0] data; endinterface class Cls; - virtual Bus vbus; + virtual Bus vbus; - function void check(logic [7:0] data); - if (vbus.data != data) $stop; - endfunction + function void check(logic [7:0] data); + if (vbus.data != data) $stop; + endfunction endclass -module t (clk); - input clk; - int cyc = 0; +module t ( + input clk +); - Bus bus(); - virtual Bus vbus; - Cls obj; + int cyc = 0; - assign bus.data = 'hFA; + Bus bus (); + virtual Bus vbus; + Cls obj; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - obj = new; - vbus = bus; - obj.vbus = bus; - end - else if (cyc == 2) begin - obj.check('hFA); - $write("*-* All Finished *-*\n"); - $finish; - end - end + assign bus.data = 'hFA; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + obj = new; + vbus = bus; + obj.vbus = bus; + end + else if (cyc == 2) begin + obj.check('hFA); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_interface_virtual_param.v b/test_regress/t/t_interface_virtual_param.v index 27eb0b0b5..700769e10 100644 --- a/test_regress/t/t_interface_virtual_param.v +++ b/test_regress/t/t_interface_virtual_param.v @@ -4,41 +4,47 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -interface Bus #(parameter int W = 1, X = 2); - logic [W-1:0] data; +interface Bus #( + parameter int W = 1, + X = 2 +); + logic [W-1:0] data; endinterface -interface BusTyped #(parameter type T); - T data; +interface BusTyped #( + parameter type T +); + T data; endinterface -typedef struct packed { - logic x; -} my_logic_t; +typedef struct packed {logic x;} my_logic_t; module t; - Bus#(6, 3) intf1(); - virtual Bus#(6, 3) vintf1 = intf1; + Bus #(6, 3) intf1 (); + virtual Bus #(6, 3) vintf1 = intf1; - Bus intf2(); - virtual Bus#(.W(1), .X(2)) vintf2 = intf2; + Bus intf2 (); + virtual Bus #( + .W(1), + .X(2) + ) vintf2 = intf2; - BusTyped#(my_logic_t) intf3(); - virtual BusTyped#(my_logic_t) vintf3 = intf3; + BusTyped #(my_logic_t) intf3 (); + virtual BusTyped #(my_logic_t) vintf3 = intf3; - initial begin - intf1.data = '1; - if (vintf1.data != 6'b111111) $stop; - if (vintf1.X != 3) $stop; + initial begin + intf1.data = '1; + if (vintf1.data != 6'b111111) $stop; + if (vintf1.X != 3) $stop; - intf2.data = '1; - if (vintf2.data != 1'b1) $stop; - if (vintf2.X != 2) $stop; + intf2.data = '1; + if (vintf2.data != 1'b1) $stop; + if (vintf2.X != 2) $stop; - intf3.data.x = '1; - if (vintf3.data.x != 1'b1) $stop; + intf3.data.x = '1; + if (vintf3.data.x != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_virtual_unused.v b/test_regress/t/t_interface_virtual_unused.v index ed3343e02..1b3a48b05 100644 --- a/test_regress/t/t_interface_virtual_unused.v +++ b/test_regress/t/t_interface_virtual_unused.v @@ -6,15 +6,15 @@ // See also t_interface_virtual.v -interface QBus(); +interface QBus (); endinterface module t; - virtual QBus q8; + virtual QBus q8; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_virtual_unused2.v b/test_regress/t/t_interface_virtual_unused2.v index d9ea25eba..0c239a344 100644 --- a/test_regress/t/t_interface_virtual_unused2.v +++ b/test_regress/t/t_interface_virtual_unused2.v @@ -4,24 +4,26 @@ // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -interface QBus(input logic k); - logic data; +interface QBus ( + input logic k +); + logic data; endinterface class cls; - virtual QBus vif1; + virtual QBus vif1; - function void foo(virtual QBus vif2); - vif2.data = 1; - endfunction + function void foo(virtual QBus vif2); + vif2.data = 1; + endfunction endclass module t; - cls bar; + cls bar; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_interface_wire_bad.out b/test_regress/t/t_interface_wire_bad.out index 72e215428..efd30e628 100644 --- a/test_regress/t/t_interface_wire_bad.out +++ b/test_regress/t/t_interface_wire_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. +%Error: t/t_interface_wire_bad.v:17:19: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. : ... note: In instance 't' - 17 | wire wbad = sub.a; - | ^ + 17 | wire wbad = sub.a; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_wire_bad.v b/test_regress/t/t_interface_wire_bad.v index f6d8067f6..1f420e3eb 100644 --- a/test_regress/t/t_interface_wire_bad.v +++ b/test_regress/t/t_interface_wire_bad.v @@ -8,11 +8,11 @@ interface Ifc; endinterface module Sub; - Ifc a(); + Ifc a (); endmodule module t; - Sub sub(); - // Issue #5649 - wire wbad = sub.a; + Sub sub (); + // Issue #5649 + wire wbad = sub.a; endmodule diff --git a/test_regress/t/t_interface_wire_bad_param.out b/test_regress/t/t_interface_wire_bad_param.out index 144b8372f..1b97396f5 100644 --- a/test_regress/t/t_interface_wire_bad_param.out +++ b/test_regress/t/t_interface_wire_bad_param.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_wire_bad_param.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. +%Error: t/t_interface_wire_bad_param.v:19:19: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. : ... note: In instance 't' - 17 | wire wbad = sub.a; - | ^ + 19 | wire wbad = sub.a; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_wire_bad_param.v b/test_regress/t/t_interface_wire_bad_param.v index e1660f0cc..3b403819a 100644 --- a/test_regress/t/t_interface_wire_bad_param.v +++ b/test_regress/t/t_interface_wire_bad_param.v @@ -7,12 +7,14 @@ interface Ifc; endinterface -module Sub #(parameter P); - Ifc a(); +module Sub #( + parameter P +); + Ifc a (); endmodule module t; - Sub #(0) sub(); - // Issue #5649 - wire wbad = sub.a; + Sub #(0) sub (); + // Issue #5649 + wire wbad = sub.a; endmodule diff --git a/test_regress/t/t_interface_wrong_bad.out b/test_regress/t/t_interface_wrong_bad.out index 4ede7fefb..e14dc6ba3 100644 --- a/test_regress/t/t_interface_wrong_bad.out +++ b/test_regress/t/t_interface_wrong_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_wrong_bad.v:32:8: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface - : ... note: In instance 't' - 32 | .foo_port (bar) - | ^~~~~~~~ +%Error: t/t_interface_wrong_bad.v:32:21: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface + : ... note: In instance 't' + 32 | foo_mod foo_mod (.foo_port(bar)); + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_wrong_bad.v b/test_regress/t/t_interface_wrong_bad.v index 58c455662..19fc431ed 100644 --- a/test_regress/t/t_interface_wrong_bad.v +++ b/test_regress/t/t_interface_wrong_bad.v @@ -6,35 +6,34 @@ // SPDX-License-Identifier: CC0-1.0 interface foo_intf; - logic [7:0] a; + logic [7:0] a; endinterface interface bar_intf; - logic [7:0] a; + logic [7:0] a; endinterface -module foo_mod (foo_intf foo_port); -// initial begin -// $display("a = %0d", foo_port.a); -// end +module foo_mod ( + foo_intf foo_port +); + // initial begin + // $display("a = %0d", foo_port.a); + // end endmodule module t; - foo_intf foo (); - bar_intf bar (); + foo_intf foo (); + bar_intf bar (); -// assign foo.a = 8'd1; -// assign bar.a = 8'd2; + // assign foo.a = 8'd1; + // assign bar.a = 8'd2; - foo_mod - foo_mod ( - .foo_port (bar) - ); + foo_mod foo_mod (.foo_port(bar)); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index 3a0e1aa16..9ae57eea6 100644 --- a/test_regress/t/t_json_only_begin_hier.out +++ b/test_regress/t/t_json_only_begin_hier.out @@ -1,48 +1,48 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","origName":"test","verilogName":"test","level":1,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"test","addr":"(E)","loc":"d,21:8,21:12","origName":"test","verilogName":"test","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","verilogName":"N","direction":"NONE","isUsedLoopIdx":true,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"genforp": [],"itemsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","genforp": [], + {"type":"VAR","name":"N","addr":"(F)","loc":"d,22:10,22:11","dtypep":"(G)","origName":"N","verilogName":"N","direction":"NONE","isUsedLoopIdx":true,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,24:5,24:8","implied":true,"genforp": [],"itemsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,25:14,25:24","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,27:21,27:31","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,28:19,28:24","unnamed":true,"genforp": [], + {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,25:14,25:24","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,26:14,26:19","unnamed":true,"genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,29:25,29:33","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,27:16,27:24","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,31:21,31:29","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,29:14,29:22","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,27:21,27:31","genforp": [], + {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,25:14,25:24","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,27:21,27:31","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,28:19,28:24","unnamed":true,"genforp": [], + {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,25:14,25:24","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,26:14,26:19","unnamed":true,"genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,29:25,29:33","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,27:16,27:24","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,29:14,29:22","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]} ]}, {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","origName":"submod","verilogName":"submod","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","genforp": [], + {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,11:18,11:28","genforp": [], "itemsp": [ - {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","verilogName":"l1_sig","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","genforp": [], + {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,12:10,12:16","dtypep":"(V)","origName":"l1_sig","verilogName":"l1_sig","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,13:20,13:30","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","verilogName":"submod_nested","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,14:15,14:28","origName":"submod_nested","verilogName":"submod_nested","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,17:17,17:26","origName":"submod_l1","verilogName":"submod_l1","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,16:13,16:22","origName":"submod_l1","verilogName":"submod_l1","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","verilogName":"submod_l0","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,18:11,18:20","origName":"submod_l0","verilogName":"submod_l0","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","origName":"submod2","verilogName":"submod2","level":3,"timeunit":"1ps","inlinesp": [],"stmtsp": []} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ - {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,24:12,24:13","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,13:14,13:20","dtypep":"(V)","keyword":"logic","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,22:10,22:11","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,12:10,12:16","dtypep":"(V)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ diff --git a/test_regress/t/t_json_only_begin_hier.v b/test_regress/t/t_json_only_begin_hier.v index dd0ed0c91..db7b051e1 100644 --- a/test_regress/t/t_json_only_begin_hier.v +++ b/test_regress/t/t_json_only_begin_hier.v @@ -7,27 +7,26 @@ module submod2 (); endmodule -module submod #( -)(); - if(1) begin : submod_gen - wire l1_sig; - if(1) begin : nested_gen - submod2 submod_nested(); - end - submod2 submod_l1(); +module submod #() (); + if (1) begin : submod_gen + wire l1_sig; + if (1) begin : nested_gen + submod2 submod_nested (); end - submod2 submod_l0(); + submod2 submod_l1 (); + end + submod2 submod_l0 (); endmodule -module test( -); - genvar N; - generate for(N=0; N<2; N=N+1) - begin : FOR_GENERATE - submod submod_for(); - if(1) begin - submod submod_2(); - end - submod submod_3(); - end endgenerate +module test (); + genvar N; + generate + for (N = 0; N < 2; N = N + 1) begin : FOR_GENERATE + submod submod_for (); + if (1) begin + submod submod_2 (); + end + submod submod_3 (); + end + endgenerate endmodule diff --git a/test_regress/t/t_json_only_first.out b/test_regress/t/t_json_only_first.out index 9fc577f6f..a4289bd8b 100644 --- a/test_regress/t/t_json_only_first.out +++ b/test_regress/t/t_json_only_first.out @@ -2,87 +2,87 @@ "modulesp": [ {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","verilogName":"between","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","verilogName":"cell1","modp":"(M)", + {"type":"VAR","name":"q","addr":"(F)","loc":"d,16:21,16:22","dtypep":"(G)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(H)","loc":"d,14:9,14:12","dtypep":"(I)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(J)","loc":"d,15:15,15:16","dtypep":"(G)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"between","addr":"(K)","loc":"d,18:15,18:22","dtypep":"(G)","origName":"between","verilogName":"between","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,22:5,22:10","origName":"cell1","verilogName":"cell1","modp":"(M)", "pinsp": [ - {"type":"PIN","name":"q","addr":"(N)","loc":"d,20:12,20:13","svDotName":true,"modVarp":"(O)","modPTypep":"UNLINKED", + {"type":"PIN","name":"q","addr":"(N)","loc":"d,23:8,23:9","svDotName":true,"modVarp":"(O)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"between","addr":"(P)","loc":"d,20:14,20:21","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"between","addr":"(P)","loc":"d,23:10,23:17","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"clk","addr":"(Q)","loc":"d,21:12,21:15","svDotName":true,"modVarp":"(R)","modPTypep":"UNLINKED", + {"type":"PIN","name":"clk","addr":"(Q)","loc":"d,24:8,24:11","svDotName":true,"modVarp":"(R)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"clk","addr":"(S)","loc":"d,21:42,21:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"clk","addr":"(S)","loc":"d,24:12,24:15","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"d","addr":"(T)","loc":"d,22:12,22:13","svDotName":true,"modVarp":"(U)","modPTypep":"UNLINKED", + {"type":"PIN","name":"d","addr":"(T)","loc":"d,25:8,25:9","svDotName":true,"modVarp":"(U)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"d","addr":"(V)","loc":"d,22:42,22:43","dtypep":"(G)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"d","addr":"(V)","loc":"d,25:10,25:11","dtypep":"(G)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"CELL","name":"cell2","addr":"(W)","loc":"d,25:6,25:11","origName":"cell2","verilogName":"cell2","modp":"(X)", + {"type":"CELL","name":"cell2","addr":"(W)","loc":"d,28:8,28:13","origName":"cell2","verilogName":"cell2","modp":"(X)", "pinsp": [ - {"type":"PIN","name":"d","addr":"(Y)","loc":"d,25:14,25:15","svDotName":true,"modVarp":"(Z)","modPTypep":"UNLINKED", + {"type":"PIN","name":"d","addr":"(Y)","loc":"d,29:8,29:9","svDotName":true,"modVarp":"(Z)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"between","addr":"(AB)","loc":"d,25:16,25:23","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"between","addr":"(AB)","loc":"d,29:10,29:17","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"q","addr":"(BB)","loc":"d,26:14,26:15","svDotName":true,"modVarp":"(CB)","modPTypep":"UNLINKED", + {"type":"PIN","name":"q","addr":"(BB)","loc":"d,30:8,30:9","svDotName":true,"modVarp":"(CB)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"q","addr":"(DB)","loc":"d,26:42,26:43","dtypep":"(G)","access":"WR","varp":"(F)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"q","addr":"(DB)","loc":"d,30:10,30:11","dtypep":"(G)","access":"WR","varp":"(F)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"clk","addr":"(EB)","loc":"d,27:14,27:17","svDotName":true,"modVarp":"(FB)","modPTypep":"UNLINKED", + {"type":"PIN","name":"clk","addr":"(EB)","loc":"d,31:8,31:11","svDotName":true,"modVarp":"(FB)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"clk","addr":"(GB)","loc":"d,27:42,27:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"clk","addr":"(GB)","loc":"d,31:12,31:15","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","origName":"mod2","verilogName":"mod2","level":2,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,50:8,50:12","origName":"mod2","verilogName":"mod2","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(CB)","loc":"d,50:22,50:23","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,53:13,53:14","keyword":"cont_assign","sentreep": [], + {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,51:11,51:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(Z)","loc":"d,52:17,52:18","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(CB)","loc":"d,53:23,53:24","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,56:12,56:13","keyword":"cont_assign","sentreep": [], "stmtsp": [ - {"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,53:13,53:14","dtypep":"(G)", + {"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,56:12,56:13","dtypep":"(G)", "rhsp": [ - {"type":"VARREF","name":"d","addr":"(JB)","loc":"d,49:16,49:17","dtypep":"(G)","access":"RD","varp":"(Z)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"d","addr":"(JB)","loc":"d,52:17,52:18","dtypep":"(G)","access":"RD","varp":"(Z)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"q","addr":"(KB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"q","addr":"(KB)","loc":"d,56:12,56:13","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ]}, - {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","origName":"mod1","verilogName":"mod1","level":2,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,36:8,36:12","origName":"mod1","verilogName":"mod1","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,32:15,32:20","dtypep":"(MB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,37:15,37:20","dtypep":"(MB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ - {"type":"CONST","name":"32'sh4","addr":"(NB)","loc":"d,19:18,19:19","dtypep":"(MB)"} + {"type":"CONST","name":"32'sh4","addr":"(NB)","loc":"d,21:14,21:15","dtypep":"(MB)"} ],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(R)","loc":"d,34:24,34:27","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(U)","loc":"d,35:30,35:31","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(O)","loc":"d,36:30,36:31","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,39:15,39:22","dtypep":"(MB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"clk","addr":"(R)","loc":"d,39:11,39:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(U)","loc":"d,40:23,40:24","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(O)","loc":"d,41:30,41:31","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,44:14,44:21","dtypep":"(MB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ - {"type":"CONST","name":"32'sh1","addr":"(PB)","loc":"d,39:25,39:26","dtypep":"(MB)"} + {"type":"CONST","name":"32'sh1","addr":"(PB)","loc":"d,44:24,44:25","dtypep":"(MB)"} ],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,41:4,41:10","keyword":"always", + {"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,46:3,46:9","keyword":"always", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(RB)","loc":"d,41:11,41:12", + {"type":"SENTREE","name":"","addr":"(RB)","loc":"d,46:10,46:11", "sensesp": [ - {"type":"SENITEM","name":"","addr":"(SB)","loc":"d,41:13,41:20","edgeType":"POS", + {"type":"SENITEM","name":"","addr":"(SB)","loc":"d,46:12,46:19","edgeType":"POS", "sensp": [ - {"type":"VARREF","name":"clk","addr":"(TB)","loc":"d,41:21,41:24","dtypep":"(I)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"clk","addr":"(TB)","loc":"d,46:20,46:23","dtypep":"(I)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"condp": []} ]} ], "stmtsp": [ - {"type":"ASSIGNDLY","name":"","addr":"(UB)","loc":"d,42:8,42:10","dtypep":"(G)", + {"type":"ASSIGNDLY","name":"","addr":"(UB)","loc":"d,46:27,46:29","dtypep":"(G)", "rhsp": [ - {"type":"VARREF","name":"d","addr":"(VB)","loc":"d,42:11,42:12","dtypep":"(G)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"d","addr":"(VB)","loc":"d,46:30,46:31","dtypep":"(G)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"q","addr":"(WB)","loc":"d,42:6,42:7","dtypep":"(G)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"q","addr":"(WB)","loc":"d,46:25,46:26","dtypep":"(G)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]} ]} @@ -90,9 +90,9 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(XB)", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,34:24,34:27","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,15:16,15:17","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,39:11,39:14","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,16:15,16:16","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,21:14,21:15","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_first.v b/test_regress/t/t_json_only_first.v index 634c08889..33f29175e 100644 --- a/test_regress/t/t_json_only_first.v +++ b/test_regress/t/t_json_only_first.v @@ -4,52 +4,55 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - q, - // Inputs - clk, d - ); - input clk; - input [3:0] d; - output wire [3:0] q; +module t ( /*AUTOARG*/ + // Outputs + q, + // Inputs + clk, + d +); + input clk; + input [3:0] d; + output wire [3:0] q; - logic [3:0] between; + logic [3:0] between; - mod1 #(.WIDTH(4)) - cell1 (.q(between), - .clk (clk), - .d (d[3:0])); + mod1 #( + .WIDTH(4) + ) cell1 ( + .q(between), + .clk(clk), + .d(d[3:0]) + ); - mod2 - cell2 (.d(between), - .q (q[3:0]), - .clk (clk)); + mod2 cell2 ( + .d(between), + .q(q[3:0]), + .clk(clk) + ); endmodule -module mod1 - #(parameter WIDTH = 32) - ( - input clk, - input [WIDTH-1:0] d, +module mod1 #( + parameter WIDTH = 32 +) ( + input clk, + input [WIDTH-1:0] d, output logic [WIDTH-1:0] q - ); +); - localparam IGNORED = 1; + localparam IGNORED = 1; - always @(posedge clk) - q <= d; + always @(posedge clk) q <= d; endmodule -module mod2 - ( - input clk, - input [3:0] d, - output wire [3:0] q - ); +module mod2 ( + input clk, + input [3:0] d, + output wire [3:0] q +); - assign q = d; + assign q = d; endmodule diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index 2bf01765b..41e0f1323 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -2,165 +2,165 @@ "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(G)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(I)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(K)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.q","addr":"(L)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.clk","addr":"(M)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.d","addr":"(N)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,17:22,17:29","dtypep":"(H)","origName":"between","verilogName":"between","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.WIDTH","addr":"(P)","loc":"d,32:15,32:20","dtypep":"(Q)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"q","addr":"(G)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(I)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(K)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.q","addr":"(L)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.clk","addr":"(M)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.d","addr":"(N)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,18:15,18:22","dtypep":"(H)","origName":"between","verilogName":"between","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.WIDTH","addr":"(P)","loc":"d,37:15,37:20","dtypep":"(Q)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ - {"type":"CONST","name":"32'sh4","addr":"(R)","loc":"d,19:18,19:19","dtypep":"(Q)"} + {"type":"CONST","name":"32'sh4","addr":"(R)","loc":"d,21:14,21:15","dtypep":"(Q)"} ],"attrsp": []}, - {"type":"VAR","name":"t.cell1.clk","addr":"(S)","loc":"d,34:24,34:27","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.d","addr":"(T)","loc":"d,35:30,35:31","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.q","addr":"(U)","loc":"d,36:30,36:31","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.IGNORED","addr":"(V)","loc":"d,39:15,39:22","dtypep":"(Q)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.cell1.clk","addr":"(S)","loc":"d,39:11,39:14","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.d","addr":"(T)","loc":"d,40:23,40:24","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.q","addr":"(U)","loc":"d,41:30,41:31","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.IGNORED","addr":"(V)","loc":"d,44:14,44:21","dtypep":"(Q)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ - 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{"type":"VARREF","name":"d","addr":"(FD)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"d","addr":"(FD)","loc":"d,46:30,46:31","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"t.between","addr":"(GD)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.between","addr":"(GD)","loc":"d,46:25,46:26","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, - {"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,53:13,53:14","keyword":"cont_assign","sentreep": [], + {"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,56:12,56:13","keyword":"cont_assign","sentreep": [], "stmtsp": [ - {"type":"ASSIGNW","name":"","addr":"(ID)","loc":"d,53:13,53:14","dtypep":"(H)", + {"type":"ASSIGNW","name":"","addr":"(ID)","loc":"d,56:12,56:13","dtypep":"(H)", "rhsp": [ - {"type":"VARREF","name":"t.between","addr":"(JD)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.between","addr":"(JD)","loc":"d,18:15,18:22","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"q","addr":"(KD)","loc":"d,53:13,53:14","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"q","addr":"(KD)","loc":"d,56:12,56:13","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"inlinesp": []} @@ -170,9 +170,9 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(LD)", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,34:24,34:27","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,15:16,15:17","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,39:11,39:14","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,16:15,16:16","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,21:14,21:15","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index 16f5bba1f..7b2964a10 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -2,46 +2,46 @@ "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","verilogName":"clk_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","verilogName":"rst_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","verilogName":"foo_op","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","childDTypep": [],"attrsp": []}, - {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","verilogName":"itop","modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","verilogName":"itop__Viftop","direction":"NONE","lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","verilogName":"this_struct","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","verilogName":"dotted","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:23,33:24","keyword":"cont_assign","sentreep": [], + {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,13:11,13:17","dtypep":"(G)","origName":"clk_ip","verilogName":"clk_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"rst_ip","verilogName":"rst_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,15:12,15:18","dtypep":"(G)","origName":"foo_op","verilogName":"foo_op","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:5,25:14","dtypep":"(K)","childDTypep": [],"attrsp": []}, + {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:7,29:11","origName":"itop","verilogName":"itop","modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:7,29:11","dtypep":"(O)","origName":"itop__Viftop","verilogName":"itop__Viftop","direction":"NONE","lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:13,31:24","dtypep":"(Q)","origName":"this_struct","verilogName":"this_struct","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:15,33:21","dtypep":"(S)","origName":"dotted","verilogName":"dotted","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:22,33:23","keyword":"cont_assign","sentreep": [], "stmtsp": [ - {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:23,33:24","dtypep":"(S)", + {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:22,33:23","dtypep":"(S)", "rhsp": [ - {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:30,33:35","dtypep":"(W)","dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:29,33:34","dtypep":"(W)","dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"dotted","addr":"(Y)","loc":"d,33:16,33:22","dtypep":"(S)","access":"WR","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"dotted","addr":"(Y)","loc":"d,33:15,33:21","dtypep":"(S)","access":"WR","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, - {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:18,35:19","cname":"f","fvarp": [],"classOrPackagep": [], + {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:17,35:18","cname":"f","fvarp": [],"classOrPackagep": [], "stmtsp": [ - {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:33,35:34","dtypep":"(BB)","origName":"m","verilogName":"m","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:7,36:15", + {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:32,35:33","dtypep":"(BB)","origName":"m","verilogName":"m","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:5,36:13", "fmtp": [ - {"type":"SFORMATF","name":"%@","addr":"(DB)","loc":"d,36:7,36:15","dtypep":"(BB)", + {"type":"SFORMATF","name":"%@","addr":"(DB)","loc":"d,36:5,36:13","dtypep":"(BB)", "exprsp": [ - {"type":"VARREF","name":"m","addr":"(EB)","loc":"d,36:22,36:23","dtypep":"(BB)","access":"RD","varp":"(AB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"m","addr":"(EB)","loc":"d,36:20,36:21","dtypep":"(BB)","access":"RD","varp":"(AB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []} ],"scopeNamep": []}, - {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:4,39:11", + {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:3,39:10", "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:12,39:17","unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:11,39:16","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"STMTEXPR","name":"","addr":"(HB)","loc":"d,41:7,41:8", + {"type":"STMTEXPR","name":"","addr":"(HB)","loc":"d,41:5,41:6", "exprp": [ - {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:7,41:8","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED", + {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:5,41:6","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED", "argsp": [ - {"type":"ARG","name":"","addr":"(KB)","loc":"d,41:9,41:736", + {"type":"ARG","name":"","addr":"(KB)","loc":"d,42:9,42:736", "exprp": [ - {"type":"CONST","name":"\\\"\\001\\002\\003\\004\\005\\006\\007\\010\\t\\n\\013\\014\\r\\016\\017\\020\\021\\022\\023\\024\\025\\026\\027\\030\\031\\032\\033\\034\\035\\036\\037 !\\\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\\177\\200\\201\\202\\203\\204\\205\\206\\207\\210\\211\\212\\213\\214\\215\\216\\217\\220\\221\\222\\223\\224\\225\\226\\227\\230\\231\\232\\233\\234\\235\\236\\237\\240\\241\\242\\243\\244\\245\\246\\247\\250\\251\\252\\253\\254\\255\\256\\257\\260\\261\\262\\263\\264\\265\\266\\267\\270\\271\\272\\273\\274\\275\\276\\277\\300\\301\\302\\303\\304\\305\\306\\307\\310\\311\\312\\313\\314\\315\\316\\317\\320\\321\\322\\323\\324\\325\\326\\327\\330\\331\\332\\333\\334\\335\\336\\337\\340\\341\\342\\343\\344\\345\\346\\347\\350\\351\\352\\353\\354\\355\\356\\357\\360\\361\\362\\363\\364\\365\\366\\367\\370\\371\\372\\373\\374\\375\\376\\377\\\"","addr":"(LB)","loc":"d,41:9,41:736","dtypep":"(BB)"} + {"type":"CONST","name":"\\\"\\001\\002\\003\\004\\005\\006\\007\\010\\t\\n\\013\\014\\r\\016\\017\\020\\021\\022\\023\\024\\025\\026\\027\\030\\031\\032\\033\\034\\035\\036\\037 !\\\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\\177\\200\\201\\202\\203\\204\\205\\206\\207\\210\\211\\212\\213\\214\\215\\216\\217\\220\\221\\222\\223\\224\\225\\226\\227\\230\\231\\232\\233\\234\\235\\236\\237\\240\\241\\242\\243\\244\\245\\246\\247\\250\\251\\252\\253\\254\\255\\256\\257\\260\\261\\262\\263\\264\\265\\266\\267\\270\\271\\272\\273\\274\\275\\276\\277\\300\\301\\302\\303\\304\\305\\306\\307\\310\\311\\312\\313\\314\\315\\316\\317\\320\\321\\322\\323\\324\\325\\326\\327\\330\\331\\332\\333\\334\\335\\336\\337\\340\\341\\342\\343\\344\\345\\346\\347\\350\\351\\352\\353\\354\\355\\356\\357\\360\\361\\362\\363\\364\\365\\366\\367\\370\\371\\372\\373\\374\\375\\376\\377\\\"","addr":"(LB)","loc":"d,42:9,42:736","dtypep":"(BB)"} ]} ],"withp": [],"scopeNamep": []} ]} @@ -50,44 +50,44 @@ ]}, {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","verilogName":"ifc","level":2,"inLibrary":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","verilogName":"value","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", + {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:11,8:16","dtypep":"(W)","origName":"value","verilogName":"value","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:11,9:22", "varsp": [ - {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)","exprp": []} + {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:30,9:35","direction":"OUTPUT","varp":"(X)","exprp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(JB)", "typesp": [ - {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)"}, - {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,14:11,14:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","rangep": []}, - {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"classOrPackagep":"UNLINKED", + {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:5,41:6","dtypep":"(JB)"}, + {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:3,8:10","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,13:11,13:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:5,21:10","dtypep":"(OB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:5,22:10","dtypep":"(PB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:5,23:10","dtypep":"(QB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:5,24:10","dtypep":"(RB)","keyword":"logic","rangep": []}, + {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:11,20:17","dtypep":"(K)","packed":true,"isFourstate":true,"classOrPackagep":"UNLINKED", "membersp": [ - {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","name":"clk","tag":"this is clk","refDTypep":"(OB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","name":"k","tag":"","refDTypep":"(PB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","name":"enable","tag":"enable","refDTypep":"(QB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","name":"data","tag":"data","refDTypep":"(RB)","childDTypep": [],"valuep": []} + {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:11,21:14","dtypep":"(OB)","name":"clk","tag":"this is clk","refDTypep":"(OB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:11,22:12","dtypep":"(PB)","name":"k","tag":"","refDTypep":"(PB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:11,23:17","dtypep":"(QB)","name":"enable","tag":"enable","refDTypep":"(QB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:11,24:15","dtypep":"(RB)","name":"data","tag":"data","refDTypep":"(RB)","childDTypep": [],"valuep": []} ]}, - {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","cellName":"itop","ifaceName":"ifc","modportName":"","ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","declRange":"[0:1]","refDTypep":"(WB)","childDTypep": [], + {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:7,29:11","dtypep":"(O)","cellName":"itop","ifaceName":"ifc","modportName":"","ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:25,31:26","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:3,31:12","dtypep":"(K)","typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:24,31:25","dtypep":"(Q)","declRange":"[0:1]","refDTypep":"(WB)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true, + {"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:24,31:25","ascending":true,"fromBracket":true, "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(YB)","loc":"d,31:27,31:28","dtypep":"(S)"} + {"type":"CONST","name":"32'h0","addr":"(YB)","loc":"d,31:25,31:26","dtypep":"(S)"} ], "rightp": [ - {"type":"CONST","name":"32'h1","addr":"(ZB)","loc":"d,31:27,31:28","dtypep":"(S)"} + {"type":"CONST","name":"32'h1","addr":"(ZB)","loc":"d,31:25,31:26","dtypep":"(S)"} ]} ]}, - {"type":"BASICDTYPE","name":"string","addr":"(BB)","loc":"d,35:26,35:32","dtypep":"(BB)","keyword":"string","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"string","addr":"(BB)","loc":"d,35:25,35:31","dtypep":"(BB)","keyword":"string","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ diff --git a/test_regress/t/t_json_only_tag.v b/test_regress/t/t_json_only_tag.v index 9bfd517d6..5cbb6db0c 100644 --- a/test_regress/t/t_json_only_tag.v +++ b/test_regress/t/t_json_only_tag.v @@ -5,40 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 interface ifc; - integer value; - modport out_modport (output value); + integer value; + modport out_modport(output value); endinterface -module m - ( - input clk_ip, // verilator tag clk_ip - input rst_ip, - output foo_op); // verilator tag foo_op +module m ( + input clk_ip, // verilator tag clk_ip + input rst_ip, + output foo_op +); // verilator tag foo_op - // This is a comment + // This is a comment - typedef struct packed { - logic clk; /* verilator tag this is clk */ - logic k; /* verilator lint_off UNUSED */ - logic enable; // verilator tag enable - logic data; // verilator tag data - } my_struct; // verilator tag my_struct + typedef struct packed { + logic clk; /* verilator tag this is clk */ + logic k; /* verilator lint_off UNUSED */ + logic enable; // verilator tag enable + logic data; // verilator tag data + } my_struct; // verilator tag my_struct - // This is a comment + // This is a comment - ifc itop(); + ifc itop (); - my_struct this_struct [2]; // verilator tag this_struct + my_struct this_struct[2]; // verilator tag this_struct - wire [31:0] dotted = itop.value; + wire [31:0] dotted = itop.value; - function void f(input string m); - $display("%s", m); - endfunction + function void f(input string m); + $display("%s", m); + endfunction - initial begin - // Contains all 256 characters except 0 (null character) - f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); - end + initial begin + // Contains all 256 characters except 0 (null character) + f( + "\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); + end endmodule diff --git a/test_regress/t/t_mailbox_class.v b/test_regress/t/t_mailbox_class.v index 83ea99d62..08f3161e7 100644 --- a/test_regress/t/t_mailbox_class.v +++ b/test_regress/t/t_mailbox_class.v @@ -4,60 +4,62 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class mailbox_cls #(type T=int); - // Test an implementation similar to what Verilator will do internally - int m_bound; - T m_q[$]; +class mailbox_cls #( + type T = int +); + // Test an implementation similar to what Verilator will do internally + int m_bound; + T m_q[$]; - function new(int bound = 0); - m_bound = bound; - endfunction + function new(int bound = 0); + m_bound = bound; + endfunction - function int num(); - return m_q.size(); - endfunction + function int num(); + return m_q.size(); + endfunction - task put(T message); - if (m_bound != 0) wait (m_q.size() < m_bound); + task put(T message); + if (m_bound != 0) wait (m_q.size() < m_bound); + m_q.push_back(message); + endtask + function int try_put(T message); + if (m_bound != 0 && m_q.size() < m_bound) begin m_q.push_back(message); - endtask - function int try_put(T message); - if (m_bound != 0 && m_q.size() < m_bound) begin - m_q.push_back(message); - return 1; - end - else begin - return 0; - end - endfunction + return 1; + end + else begin + return 0; + end + endfunction - task get(ref T message); - wait (m_q.size() != 0); + task get(ref T message); + wait (m_q.size() != 0); + message = m_q.pop_front(); + endtask + function int try_get(ref T message); + if (m_q.size() != 0) begin message = m_q.pop_front(); - endtask - function int try_get(ref T message); - if (m_q.size() != 0) begin - message = m_q.pop_front(); - return 1; - end - else begin - return 0; - end - endfunction + return 1; + end + else begin + return 0; + end + endfunction - task peek(ref T message); - wait (m_q.size() != 0); + task peek(ref T message); + wait (m_q.size() != 0); + message = m_q[0]; + endtask + function int try_peek(ref T message); + if (m_q.size() != 0) begin message = m_q[0]; - endtask - function int try_peek(ref T message); - if (m_q.size() != 0) begin - message = m_q[0]; - return 1; - end - else begin - return 0; - end - endfunction + return 1; + end + else begin + return 0; + end + endfunction endclass `define MAILBOX_T mailbox_cls diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v index 300ce5e92..b87b854f2 100644 --- a/test_regress/t/t_math_signed5.v +++ b/test_regress/t/t_math_signed5.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `ifdef VERILATOR @@ -11,181 +12,182 @@ `else `define c(v,vs) (v) `endif +// verilog_format: on - module t (/*AUTOARG*/ - // Outputs - ow4_u - ); +module t ( /*AUTOARG*/ + // Outputs + ow4_u +); - bit fail; + bit fail; - reg signed [3:0] w4_s; - reg signed [4:0] w5_s; - reg [2:0] w3_u; - reg [3:0] w4_u; - reg [4:0] w5_u; - reg [5:0] w6_u; - reg [15:0] w16a_u; - reg [15:0] w16_u; - reg [31:0] w32_u; - real r; + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [2:0] w3_u; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg [5:0] w6_u; + reg [15:0] w16a_u; + reg [15:0] w16_u; + reg [31:0] w32_u; + real r; - reg signed [4:0] bug754_a; + reg signed [4:0] bug754_a; - integer i; + integer i; - //verilator lint_off WIDTH - wire a = (5'b0 == (5'sb11111 >>> 3'd7)); - wire b = (5'sb11111 == (5'sb11111 >>> 3'd7)); - wire c = (1'b0+(5'sb11111 >>> 3'd7)); - wire d = (1'sb0+(5'sb11111 >>> 3'd7)); - wire e = (5'b0 == (5'sb11111 / 5'sd3)); - wire f = (5'sb0 == (5'sb11111 / 5'sd3)); - wire g = (5'b01010 == (5'b11111 / 5'sd3)); - initial begin - // verilator lint_off STMTDLY - #1; + //verilator lint_off WIDTH + wire a = (5'b0 == (5'sb11111 >>> 3'd7)); + wire b = (5'sb11111 == (5'sb11111 >>> 3'd7)); + wire c = (1'b0 + (5'sb11111 >>> 3'd7)); + wire d = (1'sb0 + (5'sb11111 >>> 3'd7)); + wire e = (5'b0 == (5'sb11111 / 5'sd3)); + wire f = (5'sb0 == (5'sb11111 / 5'sd3)); + wire g = (5'b01010 == (5'b11111 / 5'sd3)); + initial begin + // verilator lint_off STMTDLY + #1; `ifdef VCS // I-2014.03 - `checkh({a, b, c, d, e, f, g}, 7'b1101111); + `checkh({a, b, c, d, e, f, g}, 7'b1101111); `else - `checkh({a, b, c, d, e, f, g}, 7'b1101011); + `checkh({a, b, c, d, e, f, g}, 7'b1101011); `endif - //====================================================================== + //====================================================================== - if ((-1 >>> 3) != -1) $stop; // Decimals are signed + if ((-1 >>> 3) != -1) $stop; // Decimals are signed - i = 3'sb111 >>> 3; - `checkh(i, -1); - i = -1 >>> 3; - `checkh(i, -1); + i = 3'sb111 >>> 3; + `checkh(i, -1); + i = -1 >>> 3; + `checkh(i, -1); - bug754_a = -1; - w4_u = |0 != (bug754_a >>> 3'd7); - `checkh(w4_u, 4'b0); + bug754_a = -1; + w4_u = |0 != (bug754_a >>> 3'd7); + `checkh(w4_u, 4'b0); - // Sanity check: -1>>7 == -1 - w5_u = (5'sb11111 >>> 3'd7); - `checkh(w5_u, 5'b11111); + // Sanity check: -1>>7 == -1 + w5_u = (5'sb11111 >>> 3'd7); + `checkh(w5_u, 5'b11111); - // bug756 - w4_u = (5'b0 == (5'sb11111 >>> 3'd7)); - `checkh(w4_u, 4'b0001); - w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0 - `checkh(w4_u, 4'b0001); - w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>> + // bug756 + w4_u = (5'b0 == (5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b0001); + w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0 + `checkh(w4_u, 4'b0001); + w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>> `ifdef VCS // I-2014.03 - `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate + `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate `else - `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... + `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif - // Does == sign propagate from lhs to rhs? Yes, but not in VCS - w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero + // Does == sign propagate from lhs to rhs? Yes, but not in VCS + w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero `ifdef VCS // I-2014.03 - `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate - // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others + `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate + // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others `else - `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... + `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif - w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter - `checkh(w4_u, 4'b0000); + w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter + `checkh(w4_u, 4'b0000); - w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero - `checkh(w4_u, 4'b0001); - // Does == width propagate from lhs to rhs? Yes - w4_u = (3'b100==(3'b111 << 2)); - `checkh(w4_u, 4'b0001); - w4_u = (4'b100==(3'b111 << 2)); - `checkh(w4_u, 4'b0000); - w4_u = (4'b1100==(3'b111 << 2)); - `checkh(w4_u, 4'b0001); + w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero + `checkh(w4_u, 4'b0001); + // Does == width propagate from lhs to rhs? Yes + w4_u = (3'b100 == (3'b111 << 2)); + `checkh(w4_u, 4'b0001); + w4_u = (4'b100 == (3'b111 << 2)); + `checkh(w4_u, 4'b0000); + w4_u = (4'b1100 == (3'b111 << 2)); + `checkh(w4_u, 4'b0001); - // Does >>> sign propagate from input same as for +? Yes - w4_u = (1'b0+(5'sb11111 >>> 3'd7)); - `checkh(w4_u, 4'b0000); - w4_u = (1'sb0+(5'sb11111 >>> 3'd7)); - `checkh(w4_u, 4'b1111); + // Does >>> sign propagate from input same as for +? Yes + w4_u = (1'b0 + (5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b0000); + w4_u = (1'sb0 + (5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b1111); - // Does << width propagate from input same as for +? Yes - w4_u = (3'b0+(3'b111 << 2)); - `checkh(w4_u, 4'b1100); // width 4 =='s LHS - w4_u = (4'b0+(3'b111 << 2)); - `checkh(w4_u, 4'b1100); + // Does << width propagate from input same as for +? Yes + w4_u = (3'b0 + (3'b111 << 2)); + `checkh(w4_u, 4'b1100); // width 4 =='s LHS + w4_u = (4'b0 + (3'b111 << 2)); + `checkh(w4_u, 4'b1100); - w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==????? - `checkh(w4_u, 4'b0001); - w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); - `checkh(w4_u, 4'b0001); + w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==????? + `checkh(w4_u, 4'b0001); + w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); + `checkh(w4_u, 4'b0001); - // bug756 - w5_s = -1; - w3_u = 7; - w4_u = |0 != (w5_s >>> w3_u); - `checkh(w4_u, 4'b0000); + // bug756 + w5_s = -1; + w3_u = 7; + w4_u = |0 != (w5_s >>> w3_u); + `checkh(w4_u, 4'b0000); - // bug763 - w3_u = 2; - w4_u = (w3_u >> 2'b11) >> 1; - `checkh(w4_u, 4'b0000); + // bug763 + w3_u = 2; + w4_u = (w3_u >> 2'b11) >> 1; + `checkh(w4_u, 4'b0000); - // bug766 - w16a_u = 16'h1234; - w16_u = (w16a_u >> 16) >>> 32'h7ffffff1; - `checkh(w16_u, 16'h0000); + // bug766 + w16a_u = 16'h1234; + w16_u = (w16a_u >> 16) >>> 32'h7ffffff1; + `checkh(w16_u, 16'h0000); - // bug768 - w4_s = 4'sd4; - w4_u = $signed(5'd1 > w4_s-w4_s); - `checkh(w4_u, 4'b1111); - w4_s = `c(4,"4"); // Eval at runtime - w4_u = $signed(5'd1 > w4_s-w4_s); - `checkh(w4_u, 4'b1111); + // bug768 + w4_s = 4'sd4; + w4_u = $signed(5'd1 > w4_s - w4_s); + `checkh(w4_u, 4'b1111); + w4_s = `c(4, "4"); // Eval at runtime + w4_u = $signed(5'd1 > w4_s - w4_s); + `checkh(w4_u, 4'b1111); - // bug772 - w4_s = w4_u << 1 <<< 0/0; -`ifndef VERILATOR // In v4 can't check value as not 4-state - `checkh(w4_s, 4'bxxxx); + // bug772 + w4_s = w4_u << 1 <<< 0 / 0; +`ifndef VERILATOR // In v4 can't check value as not 4-state + `checkh(w4_s, 4'bxxxx); `endif - // bug773 - w5_u = `c(31, 31); - w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); - `checkh(w5_s, 5'b0); + // bug773 + w5_u = `c(31, 31); + w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); + `checkh(w5_s, 5'b0); - // bug774 - w4_u = `c(4, 5); - w6_u = `c(6, 35); - w4_u = 64'd0 | (w4_u << w6_u); - `checkh(w4_u, 0); + // bug774 + w4_u = `c(4, 5); + w6_u = `c(6, 35); + w4_u = 64'd0 | (w4_u << w6_u); + `checkh(w4_u, 0); - // bug776 - w4_u = `c(4, 1); - w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); - `checkh(w4_u, 4'b1111); + // bug776 + w4_u = `c(4, 1); + w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); + `checkh(w4_u, 4'b1111); - // bug828 - // verilator lint_off WIDTH - w32_u = 32'(signed'({4'b0001,5'b10000}) << 3); - `checkh(w32_u, 32'h0000_0180); - w32_u = 32'(signed'({4'b0011,5'b10000}) << 3); - `checkh(w32_u, 32'h0000_0380); - w32_u = signed'(32'({4'b0001,5'b10000}) << 3); - `checkh(w32_u, 32'h0000_0180); - w32_u = signed'(32'({4'b0011,5'b10000}) << 3); - `checkh(w32_u, 32'h0000_0380); - // verilator lint_on WIDTH - w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning - `checkh(w32_u, 32'h0000_0380); + // bug828 + // verilator lint_off WIDTH + w32_u = 32'(signed'({4'b0001, 5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0180); + w32_u = 32'(signed'({4'b0011, 5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0380); + w32_u = signed'(32'({4'b0001, 5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0180); + w32_u = signed'(32'({4'b0011, 5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0380); + // verilator lint_on WIDTH + w32_u = 32'(signed'({4'b0011, 5'b10000})) << 3; // Check no width warning + `checkh(w32_u, 32'h0000_0380); - if (fail) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (fail) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end - // bug775 - output [3:0] ow4_u; // Must be consumed - assign ow4_u = ((0/0) ? 1 : 2) % 0; + // bug775 + output [3:0] ow4_u; // Must be consumed + assign ow4_u = ((0 / 0) ? 1 : 2) % 0; endmodule diff --git a/test_regress/t/t_math_signed6.v b/test_regress/t/t_math_signed6.v index db22170bf..afcba375f 100644 --- a/test_regress/t/t_math_signed6.v +++ b/test_regress/t/t_math_signed6.v @@ -4,35 +4,37 @@ // SPDX-FileCopyrightText: 2015 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on - module t; +module t; - // signed source - logic signed [8-1:0] src; + // signed source + logic signed [8-1:0] src; - // destination structure - struct packed { - logic signed [16-1:0] s; - logic unsigned [16-1:0] u; - } dst; + // destination structure + struct packed { + logic signed [16-1:0] s; + logic unsigned [16-1:0] u; + } dst; - initial begin - // bug882 - // verilator lint_off WIDTH - src = 8'sh05; - dst = '{s: src, u: src}; - `checkh (dst.s, 16'h0005); - `checkh (dst.u, 16'h0005); + initial begin + // bug882 + // verilator lint_off WIDTH + src = 8'sh05; + dst = '{s: src, u: src}; + `checkh(dst.s, 16'h0005); + `checkh(dst.u, 16'h0005); - src = 8'shf5; - dst = '{s: src, u: src}; - `checkh (dst.s, 16'hfff5); - `checkh (dst.u, 16'hfff5); - // verilator lint_on WIDTH + src = 8'shf5; + dst = '{s: src, u: src}; + `checkh(dst.s, 16'hfff5); + `checkh(dst.u, 16'hfff5); + // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_param_type_id_bad.out b/test_regress/t/t_param_type_id_bad.out index a45cb5e12..8b9135ba1 100644 --- a/test_regress/t/t_param_type_id_bad.out +++ b/test_regress/t/t_param_type_id_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_type_id_bad.v:9:34: Expecting a data type, not VARREF: 'i' - 9 | class Cls #(parameter type P_T = i); - | ^ +%Error: t/t_param_type_id_bad.v:10:26: Expecting a data type, not VARREF: 'i' + 10 | parameter type P_T = i + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_param_type_id_bad.v b/test_regress/t/t_param_type_id_bad.v index aaf60e5a6..ed7e8d1e7 100644 --- a/test_regress/t/t_param_type_id_bad.v +++ b/test_regress/t/t_param_type_id_bad.v @@ -6,5 +6,7 @@ int i; -class Cls #(parameter type P_T = i); +class Cls #( + parameter type P_T = i +); endclass diff --git a/test_regress/t/t_pp_circdef_bad.v b/test_regress/t/t_pp_circdef_bad.v index d062e0bd2..1e3696a08 100644 --- a/test_regress/t/t_pp_circdef_bad.v +++ b/test_regress/t/t_pp_circdef_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // // bug445 - +// verilog_format: off `define WIDTH 12 `define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS diff --git a/test_regress/t/t_pp_defparen_bad.out b/test_regress/t/t_pp_defparen_bad.out index b8c787df9..f26bea610 100644 --- a/test_regress/t/t_pp_defparen_bad.out +++ b/test_regress/t/t_pp_defparen_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_pp_defparen_bad.v:10:2: Illegal text before '(' that starts define arguments - 10 | ( 1,2) +%Error: t/t_pp_defparen_bad.v:11:2: Illegal text before '(' that starts define arguments + 11 | ( 1,2) | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_pp_defparen_bad.v:10:1: syntax error, unexpected '(' - 10 | ((val 1) + (2)) +%Error: t/t_pp_defparen_bad.v:11:1: syntax error, unexpected '(' + 11 | ((val 1) + (2)) | ^ %Error: Exiting due to diff --git a/test_regress/t/t_pp_defparen_bad.v b/test_regress/t/t_pp_defparen_bad.v index fa3056129..8b509e786 100644 --- a/test_regress/t/t_pp_defparen_bad.v +++ b/test_regress/t/t_pp_defparen_bad.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define test(a1,a2) ((a1) + (a2)) `test val diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out index 785b37dd3..48eac7755 100644 --- a/test_regress/t/t_preproc.out +++ b/test_regress/t/t_preproc.out @@ -6,8 +6,7 @@ `line 6 "t/t_preproc.v" 0 - -`line 8 "t/t_preproc.v" 0 + diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index eac57cc0c..e1ebbbceb 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -3,8 +3,8 @@ // SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off // This file intentionally includes some tabs - //=========================================================================== // Includes `include "t_preproc_inc2.vh" diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out index 06438f836..162b31fd1 100644 --- a/test_regress/t/t_preproc_comments.out +++ b/test_regress/t/t_preproc_comments.out @@ -5,9 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc.v" 0 +// verilog_format: off // This file intentionally includes some tabs - -`line 8 "t/t_preproc.v" 0 //=========================================================================== // Includes diff --git a/test_regress/t/t_preproc_debugi.v b/test_regress/t/t_preproc_debugi.v index b35208387..7ea7cd0a9 100644 --- a/test_regress/t/t_preproc_debugi.v +++ b/test_regress/t/t_preproc_debugi.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define FOO `define BAR(aa,bb) aa bb `FOO diff --git a/test_regress/t/t_preproc_def09.out b/test_regress/t/t_preproc_def09.out index f6abcc305..3bdba2fce 100644 --- a/test_regress/t/t_preproc_def09.out +++ b/test_regress/t/t_preproc_def09.out @@ -6,7 +6,8 @@ - +`line 7 "t/t_preproc_def09.v" 0 + `line 9 "t/t_preproc_def09.v" 0 diff --git a/test_regress/t/t_preproc_def09.v b/test_regress/t/t_preproc_def09.v index 3163b8254..786f83e12 100644 --- a/test_regress/t/t_preproc_def09.v +++ b/test_regress/t/t_preproc_def09.v @@ -4,8 +4,8 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `undefineall - // Definitions as speced // Note there are trailing spaces, which spec doesn't show properly `define D(x,y) initial $display("start", x , y, "end"); diff --git a/test_regress/t/t_preproc_defarg_bad.v b/test_regress/t/t_preproc_defarg_bad.v index bb600a36f..0b9797347 100644 --- a/test_regress/t/t_preproc_defarg_bad.v +++ b/test_regress/t/t_preproc_defarg_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 //See bug289 - +// verilog_format: off `define A1(x) `define A2(x,y) diff --git a/test_regress/t/t_preproc_defines.out b/test_regress/t/t_preproc_defines.out index d57c0c08f..edccfaa9a 100644 --- a/test_regress/t/t_preproc_defines.out +++ b/test_regress/t/t_preproc_defines.out @@ -10,8 +10,7 @@ `line 6 "t/t_preproc.v" 0 - -`line 8 "t/t_preproc.v" 0 + diff --git a/test_regress/t/t_preproc_elsif_bad.v b/test_regress/t/t_preproc_elsif_bad.v index 7e19d15f2..18a7fb652 100644 --- a/test_regress/t/t_preproc_elsif_bad.v +++ b/test_regress/t/t_preproc_elsif_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 //See bug289 - +// verilog_format: off `elsif A `endif diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index 8df3a83ec..ef17bae5a 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; integer num; initial begin diff --git a/test_regress/t/t_preproc_ifexpr.out b/test_regress/t/t_preproc_ifexpr.out index 152f0a061..cd638ae7a 100644 --- a/test_regress/t/t_preproc_ifexpr.out +++ b/test_regress/t/t_preproc_ifexpr.out @@ -16,4 +16,4 @@ "ok ( ONE <-> ZERO)" "ok ( ONE <-> ONE)" "ok " -Line: 117 +Line: 118 diff --git a/test_regress/t/t_preproc_ifexpr.v b/test_regress/t/t_preproc_ifexpr.v index f57827e55..dfa0aba3b 100644 --- a/test_regress/t/t_preproc_ifexpr.v +++ b/test_regress/t/t_preproc_ifexpr.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `begin_keywords "1800-2023" `define ONE diff --git a/test_regress/t/t_preproc_ifexpr_bad.out b/test_regress/t/t_preproc_ifexpr_bad.out index e4ce3cf89..2fa6aefef 100644 --- a/test_regress/t/t_preproc_ifexpr_bad.out +++ b/test_regress/t/t_preproc_ifexpr_bad.out @@ -1,45 +1,45 @@ -%Error: t/t_preproc_ifexpr_bad.v:12:14: `elsif with no matching `if - 12 | `elsif ( ONE ) // BAD: elsif without if +%Error: t/t_preproc_ifexpr_bad.v:13:14: `elsif with no matching `if + 13 | `elsif ( ONE ) // BAD: elsif without if | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_preproc_ifexpr_bad.v:13:1: `endif with no matching `if - 13 | `endif +%Error: t/t_preproc_ifexpr_bad.v:14:1: `endif with no matching `if + 14 | `endif | ^~~~~~ -%Error: t/t_preproc_ifexpr_bad.v:15:10: Syntax error in `ifdef () expression - 15 | `ifdef ( ) // BAD: Missing value +%Error: t/t_preproc_ifexpr_bad.v:16:10: Syntax error in `ifdef () expression + 16 | `ifdef ( ) // BAD: Missing value | ^ -%Error: t/t_preproc_ifexpr_bad.v:18:17: Syntax error in `ifdef () expression - 18 | `ifdef ( && ZERO) // BAD: Expr +%Error: t/t_preproc_ifexpr_bad.v:19:17: Syntax error in `ifdef () expression + 19 | `ifdef ( && ZERO) // BAD: Expr | ^ -%Error: t/t_preproc_ifexpr_bad.v:21:18: Syntax error in `ifdef () expression - 21 | `ifdef ( ZERO && ) // BAD: Expr +%Error: t/t_preproc_ifexpr_bad.v:22:18: Syntax error in `ifdef () expression + 22 | `ifdef ( ZERO && ) // BAD: Expr | ^ -%Error: t/t_preproc_ifexpr_bad.v:24:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' - 24 | `ifdef ( 1 ) // BAD: Constant +%Error: t/t_preproc_ifexpr_bad.v:25:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' + 25 | `ifdef ( 1 ) // BAD: Constant | ^ -%Error: t/t_preproc_ifexpr_bad.v:24:12: Syntax error in `ifdef () expression - 24 | `ifdef ( 1 ) // BAD: Constant +%Error: t/t_preproc_ifexpr_bad.v:25:12: Syntax error in `ifdef () expression + 25 | `ifdef ( 1 ) // BAD: Constant | ^ -%Error: t/t_preproc_ifexpr_bad.v:27:14: Syntax error in `ifdef () expression; unexpected: 'TEXT' - 27 | `ifdef ( ONE & ZERO) // BAD: Operator +%Error: t/t_preproc_ifexpr_bad.v:28:14: Syntax error in `ifdef () expression; unexpected: 'TEXT' + 28 | `ifdef ( ONE & ZERO) // BAD: Operator | ^ -%Error: t/t_preproc_ifexpr_bad.v:30:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' - 30 | `ifdef ( % ) // BAD: % is syntax error +%Error: t/t_preproc_ifexpr_bad.v:31:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' + 31 | `ifdef ( % ) // BAD: % is syntax error | ^ -%Error: t/t_preproc_ifexpr_bad.v:30:12: Syntax error in `ifdef () expression - 30 | `ifdef ( % ) // BAD: % is syntax error +%Error: t/t_preproc_ifexpr_bad.v:31:12: Syntax error in `ifdef () expression + 31 | `ifdef ( % ) // BAD: % is syntax error | ^ -%Error: t/t_preproc_ifexpr_bad.v:34:1: Expecting define name. Found: ENDIF - 34 | `endif +%Error: t/t_preproc_ifexpr_bad.v:35:1: Expecting define name. Found: ENDIF + 35 | `endif | ^~~~~~ -%Error: t/t_preproc_ifexpr_bad.v:36:1: Expecting define name. Found: IFDEF - 36 | `ifdef ( ONE // BAD: Missing paren +%Error: t/t_preproc_ifexpr_bad.v:37:1: Expecting define name. Found: IFDEF + 37 | `ifdef ( ONE // BAD: Missing paren | ^~~~~~ -%Error: t/t_preproc_ifexpr_bad.v:37:1: Syntax error in `ifdef () expression; unexpected: 'TEXT' - 37 | `endif +%Error: t/t_preproc_ifexpr_bad.v:38:1: Syntax error in `ifdef () expression; unexpected: 'TEXT' + 38 | `endif | ^ -%Error: t/t_preproc_ifexpr_bad.v:40:1: EOF in unterminated preprocessor expression -%Error: t/t_preproc_ifexpr_bad.v:33:2: syntax error, unexpected ')' - 33 | ) +%Error: t/t_preproc_ifexpr_bad.v:41:1: EOF in unterminated preprocessor expression +%Error: t/t_preproc_ifexpr_bad.v:34:2: syntax error, unexpected ')' + 34 | ) | ^ %Error: Exiting due to diff --git a/test_regress/t/t_preproc_ifexpr_bad.v b/test_regress/t/t_preproc_ifexpr_bad.v index 329a32c76..a9abd8f6f 100644 --- a/test_regress/t/t_preproc_ifexpr_bad.v +++ b/test_regress/t/t_preproc_ifexpr_bad.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `begin_keywords "1800-2023" `define ONE diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index bae08217a..6108e5f4e 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -4,8 +4,8 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; - v95 v95 (); v01nc v01nc (); v01c v01c (); diff --git a/test_regress/t/t_preproc_noline.out b/test_regress/t/t_preproc_noline.out index 18da0f41d..49fa1956b 100644 --- a/test_regress/t/t_preproc_noline.out +++ b/test_regress/t/t_preproc_noline.out @@ -2,4 +2,4 @@ Hello in t_preproc_psl.v yes Multi text multiline line -Line: 21 +Line: 22 diff --git a/test_regress/t/t_preproc_noline.v b/test_regress/t/t_preproc_noline.v index 9a2360d65..bf78aef0d 100644 --- a/test_regress/t/t_preproc_noline.v +++ b/test_regress/t/t_preproc_noline.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define CHECK text \ multiline diff --git a/test_regress/t/t_preproc_persist.v b/test_regress/t/t_preproc_persist.v index 0bfd24252..3833eef7a 100644 --- a/test_regress/t/t_preproc_persist.v +++ b/test_regress/t/t_preproc_persist.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off Inside `__FILE__. `include "t_preproc_persist_inc.v" diff --git a/test_regress/t/t_preproc_persist2.v b/test_regress/t/t_preproc_persist2.v index 0bfd24252..3833eef7a 100644 --- a/test_regress/t/t_preproc_persist2.v +++ b/test_regress/t/t_preproc_persist2.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off Inside `__FILE__. `include "t_preproc_persist_inc.v" diff --git a/test_regress/t/t_preproc_persist_inc.v b/test_regress/t/t_preproc_persist_inc.v index 30e3b54aa..c63f1e71d 100644 --- a/test_regress/t/t_preproc_persist_inc.v +++ b/test_regress/t/t_preproc_persist_inc.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `ifndef COMMON_GUARD `define COMMON_GUARD 1 Inside `__FILE__. diff --git a/test_regress/t/t_preproc_preproczero_bad.out b/test_regress/t/t_preproc_preproczero_bad.out index 029f34613..b7e875f2f 100644 --- a/test_regress/t/t_preproc_preproczero_bad.out +++ b/test_regress/t/t_preproc_preproczero_bad.out @@ -1,6 +1,6 @@ -%Warning-PREPROCZERO: t/t_preproc_preproczero_bad.v:11:10: Preprocessor expression evaluates define with 0: 'ZERO' with value '0' +%Warning-PREPROCZERO: t/t_preproc_preproczero_bad.v:12:10: Preprocessor expression evaluates define with 0: 'ZERO' with value '0' ... Suggest change define 'ZERO' to non-zero value if used in preprocessor expression - 11 | `ifdef ( ZERO ) + 12 | `ifdef ( ZERO ) | ^~~~ ... For warning description see https://verilator.org/warn/PREPROCZERO?v=latest ... Use "/* verilator lint_off PREPROCZERO */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_preproc_preproczero_bad.v b/test_regress/t/t_preproc_preproczero_bad.v index 9a0130a50..1a5b46ae9 100644 --- a/test_regress/t/t_preproc_preproczero_bad.v +++ b/test_regress/t/t_preproc_preproczero_bad.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `begin_keywords "1800-2023" `define ZERO 0 diff --git a/test_regress/t/t_preproc_str_undef.v b/test_regress/t/t_preproc_str_undef.v index 5910ed3cb..ee30196c0 100644 --- a/test_regress/t/t_preproc_str_undef.v +++ b/test_regress/t/t_preproc_str_undef.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define PREFIX_ my_prefix_ `define SUFFIX my_suffix `define PREFIX_SUFFIX my_prefix_suffix @@ -13,15 +14,15 @@ `define stringify(text) `"text`" module t; - initial begin - // Another simulator gives: - // `PREFIX_my_suffix - // `name2(`PREFIX, my_suffix) - // `name3(PREFIX) - $display(`stringify(`name1)); - $display(`stringify(`name2(`PREFIX, `SUFFIX))); - $display(`stringify(`name3(PREFIX))); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Another simulator gives: + // `PREFIX_my_suffix + // `name2(`PREFIX, my_suffix) + // `name3(PREFIX) + $display(`stringify(`name1)); + $display(`stringify(`name2(`PREFIX, `SUFFIX))); + $display(`stringify(`name3(PREFIX))); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_preproc_undefineall.v b/test_regress/t/t_preproc_undefineall.v index 0fb666e3e..5bb9b73c6 100644 --- a/test_regress/t/t_preproc_undefineall.v +++ b/test_regress/t/t_preproc_undefineall.v @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t; `define UDALL @@ -15,6 +16,6 @@ module t; `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif initial begin - $finish; + $finish; end endmodule diff --git a/test_regress/t/t_program.v b/test_regress/t/t_program.v index 8f12edd40..2dfbd447d 100644 --- a/test_regress/t/t_program.v +++ b/test_regress/t/t_program.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 program t; - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endprogram diff --git a/test_regress/t/t_program_anonymous.v b/test_regress/t/t_program_anonymous.v index b16086ffa..0ba3f8b53 100644 --- a/test_regress/t/t_program_anonymous.v +++ b/test_regress/t/t_program_anonymous.v @@ -5,30 +5,30 @@ // SPDX-License-Identifier: CC0-1.0 program; - task atask; - endtask - function int afunc(input int i); - return i+1; - endfunction + task atask; + endtask + function int afunc(input int i); + return i+1; + endfunction class acls; - static int i = 10; + static int i = 10; endclass endprogram program t; - int i; + int i; - initial begin - atask(); + initial begin + atask(); - i = afunc(2); - if (i != 3) $stop; + i = afunc(2); + if (i != 3) $stop; - if (acls::i != 10) $stop; + if (acls::i != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endprogram diff --git a/test_regress/t/t_queue.v b/test_regress/t/t_queue.v index 3cbf98fc4..47c94e4c3 100644 --- a/test_regress/t/t_queue.v +++ b/test_regress/t/t_queue.v @@ -4,294 +4,316 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - typedef int q_t[$]; + typedef int q_t[$]; - function void set_val(ref int lhs, input int rhs); - lhs = rhs; - endfunction + function void set_val(ref int lhs, input int rhs); + lhs = rhs; + endfunction - initial begin - q_t iq; - iq.push_back(42); + initial begin + q_t iq; + iq.push_back(42); + + // Resize via [] + set_val(iq[0], 9000); + `checkh(iq.size(), 1); + `checks(iq[0], 9000); + iq[1]++; + `checkh(iq.size(), 2); + `checks(iq[1], 1); + iq[1000] = 1000; + `checkh(iq.size(), 2); + `checks(iq[1000], 0); + end + + always @(posedge clk) begin + cyc <= cyc + 1; + + begin + // Very simple test using bit + bit q[$]; + bit x; + + `checkh($left(q), 0); + `checkh($right(q), -1); + `checkh($increment(q), -1); + `checkh($low(q), 0); + `checkh($high(q), -1); + `checkh($size(q), 0); + `checkh($dimensions(q), 1); + // $bits is unsupported in several other simulators, see bug1646 + // Unsup: `checkh($bits(q), 0); + + q.push_back(1'b1); + `checkh($left(q), 0); + `checkh($right(q), 0); + `checkh($increment(q), -1); + `checkh($low(q), 0); + `checkh($high(q), 0); + `checkh($size(q), 1); + `checkh($dimensions(q), 1); + // Unsup: `checkh($bits(q), 2); + `checkh(q.size(), 1); + + q.push_back(1'b1); + q.push_back(1'b0); + q.push_back(1'b1); + `checkh($left(q), 0); + `checkh($right(q), 3); + `checkh($low(q), 0); + `checkh($high(q), 3); + `checkh($size(q), 4); + // Unsup: `checkh($bits(q), 4); + `checkh(q.size(), 4); + + x = q.pop_back(); + `checkh(x, 1'b1); + `checkh($left(q), 0); + `checkh($right(q), 2); + `checkh($low(q), 0); + `checkh($high(q), 2); + `checkh($size(q), 3); + // sure those are working now.. + + x = q.pop_front(); + `checkh(x, 1'b1); + x = q.pop_front(); + `checkh(x, 1'b1); + x = q.pop_front(); + `checkh(x, 1'b0); + `checkh(q.size(), 0); + end + + begin + // Simple test using integer + typedef bit [3:0] nibble_t; + nibble_t q[$]; + nibble_t v; + + `checkh($left(q), 0); + `checkh($right(q), -1); + `checkh($increment(q), -1); + `checkh($low(q), 0); + `checkh($high(q), -1); + `checkh($size(q), 0); + `checkh($dimensions(q), 2); + + i = q.size(); + `checkh(i, 0); + q.push_back(4'd1); // 1 + q.push_front(4'd2); // 2 1 + q.push_back(4'd3); // 2 1 3 + i = q.size; + `checkh(i, 3); // Also checks no parens + end + + begin + // Strings + string q[$]; + string p[$:3]; + string v; + int j; + + // Empty queue checks + `checkh($left(q), 0); + `checkh($right(q), -1); + `checkh($increment(q), -1); + `checkh($low(q), 0); + `checkh($high(q), -1); + `checkh($size(q), 0); + `checkh($dimensions(q), 2); + //Unsup: `checkh($bits(q), 0); + + q.push_front("f1"); + + //Unsup: `checkh($bits(q), 16); + + q.push_back("b1"); + q.push_front("f2"); + q.push_back("b2"); + i = q.size(); + `checkh(i, 4); + + v = q[0]; + `checks(v, "f2"); + v = q[1]; + `checks(v, "f1"); + v = q[2]; + `checks(v, "b1"); + v = q[3]; + `checks(v, "b2"); + v = q[4]; + `checks(v, ""); + //Unsup: `checkh(q[$], "b2"); + + `checkp(q, "'{\"f2\", \"f1\", \"b1\", \"b2\"}"); + `checkp(p, "'{}"); + + //Unsup: q.delete(1); + //Unsup: v = q[1]; `checks(v, "b1"); + + //Unsup: q.insert(0, "ins0"); + //Unsup: q.insert(3, "ins3"); + //v = q[0]; `checks(v, "ins0"); + //v = q[3]; `checks(v, "ins3"); + + j = 0; + foreach (q[i]) begin + j++; + v = q[i]; + if (i == 0) `checks(v, "f2"); + if (i == 1) `checks(v, "f1"); + if (i == 2) `checks(v, "b1"); + if (i == 3) `checks(v, "b2"); + end + `checkh(j, 4); + + q.pop_front(); + v = q.pop_front(); + `checks(v, "f1"); + v = q.pop_back(); + `checks(v, "b2"); + v = q.pop_back(); + `checks(v, "b1"); + i = q.size(); + `checkh(i, 0); + + // Empty queue, this should be 0 + foreach (q[i]) begin + j++; + end + `checkh(j, 4); + + q.push_front("non-empty"); + i = q.size(); + `checkh(i, 1); + q.delete(); + i = q.size(); + `checkh(i, 0); + v = q.pop_front(); + `checks(v, ""); // Was empty, optional warning + v = q.pop_back(); + `checks(v, ""); // Was empty, optional warning + + // Conversion of insert/delete with zero to operator + q.push_front("front"); + q.insert(0, "newfront"); + i = q.size(); + `checkh(i, 2); + q.delete(0); + i = q.size(); + `checkh(i, 1); + `checks(q[0], "front"); + //Unsup: `checks(q[$], "front"); // Resize via [] - set_val(iq[0], 9000); - `checkh(iq.size(), 1); - `checks(iq[0], 9000); - iq[1]++; - `checkh(iq.size(), 2); - `checks(iq[1], 1); - iq[1000] = 1000; - `checkh(iq.size(), 2); - `checks(iq[1000], 0); - end + q[0] = "long"; + `checkh(q.size(), 1); + `checks(q[0], "long"); + end - always @ (posedge clk) begin - cyc <= cyc + 1; + // Append to queue of queues using [] + begin + int q[$][$]; + q[0][0] = 1; + `checkh(q.size(), 1); + `checkh(q[0].size(), 1); + `checks(q[0][0], 1); + end - begin - // Very simple test using bit - bit q[$]; - bit x; + // Do not append with [] if used as index + begin + int p[$]; + int q[$]; + q[p[0]] = 1; + `checkh(p.size(), 0); + `checkh(q.size(), 1); + `checks(q[0], 1); + end - `checkh($left(q), 0); - `checkh($right(q), -1); - `checkh($increment(q), -1); - `checkh($low(q), 0); - `checkh($high(q), -1); - `checkh($size(q), 0); - `checkh($dimensions(q), 1); - // $bits is unsupported in several other simulators, see bug1646 - // Unsup: `checkh($bits(q), 0); + begin + typedef struct packed { + bit [7:0] opcode; + bit [23:0] addr; + } instruction; // named structure type - q.push_back(1'b1); - `checkh($left(q), 0); - `checkh($right(q), 0); - `checkh($increment(q), -1); - `checkh($low(q), 0); - `checkh($high(q), 0); - `checkh($size(q), 1); - `checkh($dimensions(q), 1); - // Unsup: `checkh($bits(q), 2); - `checkh(q.size(), 1); + instruction q[$]; - q.push_back(1'b1); - q.push_back(1'b0); - q.push_back(1'b1); - `checkh($left(q), 0); - `checkh($right(q), 3); - `checkh($low(q), 0); - `checkh($high(q), 3); - `checkh($size(q), 4); - // Unsup: `checkh($bits(q), 4); - `checkh(q.size(), 4); + `checkh($dimensions(q), 2); + //Unsup: `checkh($bits(q), 0); - x = q.pop_back(); `checkh(x, 1'b1); - `checkh($left(q), 0); - `checkh($right(q), 2); - `checkh($low(q), 0); - `checkh($high(q), 2); - `checkh($size(q), 3); - // sure those are working now.. + end - x = q.pop_front(); `checkh(x, 1'b1); - x = q.pop_front(); `checkh(x, 1'b1); - x = q.pop_front(); `checkh(x, 1'b0); - `checkh(q.size(), 0); - end + // testing a wide queue + begin + typedef struct packed { + bit [7:0] opcode; + bit [23:0] addr; + bit [127:0] data; + } instructionW; // named structure type - begin - // Simple test using integer - typedef bit [3:0] nibble_t; - nibble_t q[$]; - nibble_t v; + instructionW inst_push; + instructionW inst_pop; - `checkh($left(q), 0); - `checkh($right(q), -1); - `checkh($increment(q), -1); - `checkh($low(q), 0); - `checkh($high(q), -1); - `checkh($size(q), 0); - `checkh($dimensions(q), 2); + instructionW q[$]; + `checkh($dimensions(q), 2); - i = q.size(); `checkh(i, 0); - q.push_back(4'd1); // 1 - q.push_front(4'd2); // 2 1 - q.push_back(4'd3); // 2 1 3 - i = q.size; `checkh(i, 3); // Also checks no parens - end + `checkh(q[0].opcode, 0); + `checkh(q[0].addr, 0); + `checkh(q[0].data, 0); - begin - // Strings - string q[$]; - string p[$:3]; - string v; - int j; - - // Empty queue checks - `checkh($left(q), 0); - `checkh($right(q), -1); - `checkh($increment(q), -1); - `checkh($low(q), 0); - `checkh($high(q), -1); - `checkh($size(q), 0); - `checkh($dimensions(q), 2); - //Unsup: `checkh($bits(q), 0); - - q.push_front("f1"); - - //Unsup: `checkh($bits(q), 16); - - q.push_back("b1"); - q.push_front("f2"); - q.push_back("b2"); - i = q.size(); `checkh(i, 4); - - v = q[0]; `checks(v, "f2"); - v = q[1]; `checks(v, "f1"); - v = q[2]; `checks(v, "b1"); - v = q[3]; `checks(v, "b2"); - v = q[4]; `checks(v, ""); - //Unsup: `checkh(q[$], "b2"); - - `checkp(q, "'{\"f2\", \"f1\", \"b1\", \"b2\"}"); - `checkp(p, "'{}"); - - //Unsup: q.delete(1); - //Unsup: v = q[1]; `checks(v, "b1"); - - //Unsup: q.insert(0, "ins0"); - //Unsup: q.insert(3, "ins3"); - //v = q[0]; `checks(v, "ins0"); - //v = q[3]; `checks(v, "ins3"); - - j = 0; - foreach (q[i]) begin - j++; - v = q[i]; - if (i == 0) `checks(v, "f2"); - if (i == 1) `checks(v, "f1"); - if (i == 2) `checks(v, "b1"); - if (i == 3) `checks(v, "b2"); - end - `checkh(j,4); - - q.pop_front(); - v = q.pop_front(); `checks(v, "f1"); - v = q.pop_back(); `checks(v, "b2"); - v = q.pop_back(); `checks(v, "b1"); - i = q.size(); `checkh(i, 0); - - // Empty queue, this should be 0 - foreach (q[i]) begin - j++; - end - `checkh(j,4); - - q.push_front("non-empty"); - i = q.size(); `checkh(i, 1); - q.delete(); - i = q.size(); `checkh(i, 0); - v = q.pop_front(); `checks(v, ""); // Was empty, optional warning - v = q.pop_back(); `checks(v, ""); // Was empty, optional warning - - // Conversion of insert/delete with zero to operator - q.push_front("front"); - q.insert(0, "newfront"); - i = q.size(); `checkh(i, 2); - q.delete(0); - i = q.size(); `checkh(i, 1); - `checks(q[0], "front"); - //Unsup: `checks(q[$], "front"); - - // Resize via [] - q[0] = "long"; - `checkh(q.size(), 1); - `checks(q[0], "long"); - end - - // Append to queue of queues using [] - begin - int q[$][$]; - q[0][0] = 1; - `checkh(q.size(), 1); - `checkh(q[0].size(), 1); - `checks(q[0][0], 1); - end - - // Do not append with [] if used as index - begin - int p[$]; - int q[$]; - q[p[0]] = 1; - `checkh(p.size(), 0); - `checkh(q.size(), 1); - `checks(q[0], 1); - end - - begin - typedef struct packed { - bit [7:0] opcode; - bit [23:0] addr; - } instruction; // named structure type - - instruction q[$]; - - `checkh($dimensions(q), 2); - //Unsup: `checkh($bits(q), 0); - - end - - // testing a wide queue - begin - typedef struct packed { - bit [7:0] opcode; - bit [23:0] addr; - bit [127:0] data; - } instructionW; // named structure type - - instructionW inst_push; - instructionW inst_pop; - - instructionW q[$]; - `checkh($dimensions(q), 2); - - `checkh(q[0].opcode, 0); - `checkh(q[0].addr, 0); - `checkh(q[0].data, 0); - - inst_push.opcode = 1; - inst_push.addr = 42; - inst_push.data = {4{32'hdeadbeef}}; - q.push_back(inst_push); - `checkh(q[0].opcode, 1); - `checkh(q[0].addr, 42); - `checkh(q[0].data, {4{32'hdeadbeef}}); + inst_push.opcode = 1; + inst_push.addr = 42; + inst_push.data = {4{32'hdeadbeef}}; + q.push_back(inst_push); + `checkh(q[0].opcode, 1); + `checkh(q[0].addr, 42); + `checkh(q[0].data, {4{32'hdeadbeef}}); - inst_pop = q.pop_front(); - `checkh(inst_pop.opcode, 1); - `checkh(inst_pop.addr, 42); - `checkh(inst_pop.data, {4{32'hdeadbeef}}); + inst_pop = q.pop_front(); + `checkh(inst_pop.opcode, 1); + `checkh(inst_pop.addr, 42); + `checkh(inst_pop.data, {4{32'hdeadbeef}}); - `checkh(q.size(), 0); + `checkh(q.size(), 0); - `checkh(q[0].opcode, 0); - `checkh(q[0].addr, 0); - `checkh(q[0].data, 0); - end + `checkh(q[0].opcode, 0); + `checkh(q[0].addr, 0); + `checkh(q[0].data, 0); + end - /* Unsup: - begin - int q[4][$]; + /* Unsup: + begin + int q[4][$]; - q[0].push_back(0); - q[0].push_back(1); - q[1].push_back(2); - q[2].push_back(3); + q[0].push_back(0); + q[0].push_back(1); + q[1].push_back(2); + q[2].push_back(3); - end - */ + end + */ - // See t_queue_unsup_bad for more unsupported stuff + // See t_queue_unsup_bad for more unsupported stuff - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_arg.v b/test_regress/t/t_queue_arg.v index 25bd909e8..f1061bd41 100644 --- a/test_regress/t/t_queue_arg.v +++ b/test_regress/t/t_queue_arg.v @@ -10,37 +10,37 @@ // verilog_format: on typedef struct { - string name1; - string name2; + string name1; + string name2; } names_t; class uvm_queue; - names_t m_queue[$]; + names_t m_queue[$]; - virtual function void push_back(names_t item); - m_queue.push_back(item); - endfunction + virtual function void push_back(names_t item); + m_queue.push_back(item); + endfunction endclass module t; - uvm_queue q; + uvm_queue q; - initial begin - q = new; - // From uvm_queue#(uvm_acs_name_struct) __local_field_names__; - q.push_back('{"n1", "n2"}); - q.push_back('{"m1", "m2"}); - q.m_queue.push_back('{"o1", "o2"}); - $display("%p", q); - `checks(q.m_queue[0].name1, "n1"); - `checks(q.m_queue[0].name2, "n2"); - `checks(q.m_queue[1].name1, "m1"); - `checks(q.m_queue[1].name2, "m2"); - `checks(q.m_queue[2].name1, "o1"); - `checks(q.m_queue[2].name2, "o2"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + q = new; + // From uvm_queue#(uvm_acs_name_struct) __local_field_names__; + q.push_back('{"n1", "n2"}); + q.push_back('{"m1", "m2"}); + q.m_queue.push_back('{"o1", "o2"}); + $display("%p", q); + `checks(q.m_queue[0].name1, "n1"); + `checks(q.m_queue[0].name2, "n2"); + `checks(q.m_queue[1].name1, "m1"); + `checks(q.m_queue[1].name2, "m2"); + `checks(q.m_queue[2].name1, "o1"); + `checks(q.m_queue[2].name2, "o2"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_assignment.v b/test_regress/t/t_queue_assignment.v index cc9bd1c42..77fa72c92 100644 --- a/test_regress/t/t_queue_assignment.v +++ b/test_regress/t/t_queue_assignment.v @@ -5,37 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 module t_queue_assignment; - typedef int T_QI[$]; - T_QI jagged_array[$]; // int jagged_array[$][$]; - initial begin - jagged_array = '{ {1}, T_QI'{2,3,4}, {5,6} }; - // jagged_array[0][0] = 1 -- jagged_array[0] is a queue of 1 int - // jagged_array[1][0] = 2 -- jagged_array[1] is a queue of 3 ints - // jagged_array[1][1] = 3 - // jagged_array[1][2] = 4 - // jagged_array[2][0] = 5 -- jagged_array[2] is a queue of 2 ints - // jagged_array[2][1] = 6 - jagged_array.push_back('{7}); - jagged_array.push_back('{8, 9, 10}); - jagged_array.push_front('{0, 1}); - print_and_check(); + typedef int T_QI[$]; + T_QI jagged_array[$]; // int jagged_array[$][$]; + initial begin + jagged_array = '{{1}, T_QI'{2, 3, 4}, {5, 6}}; + // jagged_array[0][0] = 1 -- jagged_array[0] is a queue of 1 int + // jagged_array[1][0] = 2 -- jagged_array[1] is a queue of 3 ints + // jagged_array[1][1] = 3 + // jagged_array[1][2] = 4 + // jagged_array[2][0] = 5 -- jagged_array[2] is a queue of 2 ints + // jagged_array[2][1] = 6 + jagged_array.push_back('{7}); + jagged_array.push_back('{8, 9, 10}); + jagged_array.push_front('{0, 1}); + print_and_check(); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end - task automatic print_and_check(); - integer i, j; - int expected_values[][] = '{ '{0, 1}, '{1}, '{2, 3, 4}, '{5, 6}, '{7}, '{8, 9, 10} }; + task automatic print_and_check(); + integer i, j; + int expected_values[][] = '{'{0, 1}, '{1}, '{2, 3, 4}, '{5, 6}, '{7}, '{8, 9, 10}}; - for (i = 0; i < jagged_array.size(); i++) begin - for (j = 0; j < jagged_array[i].size(); j++) begin - // $display("jagged_array[%0d][%0d] = %0d", i, j, jagged_array[i][j]); - if (jagged_array[i][j] !== expected_values[i][j]) begin - $stop; - end - end + for (i = 0; i < jagged_array.size(); i++) begin + for (j = 0; j < jagged_array[i].size(); j++) begin + // $display("jagged_array[%0d][%0d] = %0d", i, j, jagged_array[i][j]); + if (jagged_array[i][j] !== expected_values[i][j]) begin + $stop; end - endtask + end + end + endtask endmodule diff --git a/test_regress/t/t_queue_back.v b/test_regress/t/t_queue_back.v index cb4036361..fc30a855c 100644 --- a/test_regress/t/t_queue_back.v +++ b/test_regress/t/t_queue_back.v @@ -6,37 +6,37 @@ module t; - int q[$]; - int r; + int q[$]; + int r; - function void set_val(ref int lhs, input int rhs); - lhs = rhs; - endfunction + function void set_val(ref int lhs, input int rhs); + lhs = rhs; + endfunction - initial begin - q = { 60, 50, 40 }; - set_val(q[$-1], 30); - q[$-2] = 20; + initial begin + q = {60, 50, 40}; + set_val(q[$-1], 30); + q[$-2] = 20; - r = q[$]; - if (r != 40) $stop; + r = q[$]; + if (r != 40) $stop; - r = q[$-1]; - if (r != 30) $stop; + r = q[$-1]; + if (r != 30) $stop; - q = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1) - if (q.size != 2) $stop; - if (q[0] != 20) $stop; - if (q[1] != 30) $stop; + q = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1) + if (q.size != 2) $stop; + if (q[0] != 20) $stop; + if (q[1] != 30) $stop; - q = { 20, 30, 40 }; - q = q[$-1:$]; - if (q.size != 2) $stop; - if (q[0] != 30) $stop; - if (q[1] != 40) $stop; + q = {20, 30, 40}; + q = q[$-1:$]; + if (q.size != 2) $stop; + if (q[0] != 30) $stop; + if (q[1] != 40) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_bounded.v b/test_regress/t/t_queue_bounded.v index 004fefb78..671d3687a 100644 --- a/test_regress/t/t_queue_bounded.v +++ b/test_regress/t/t_queue_bounded.v @@ -6,38 +6,38 @@ module t; - localparam TWO = 2; + localparam TWO = 2; - int q[$ : TWO]; // Shall not go higher than [2], i.e. size 3 + int q[$ : TWO]; // Shall not go higher than [2], i.e. size 3 - initial begin - q.push_front(3); - if (q.size() != 1) $stop; - q.push_front(2); - if (q.size() != 2) $stop; - q.push_front(1); - if (q.size() != 3) $stop; - q.push_front(0); - if (q.size() != 3) $stop; - q[3] = -1; - if (q.size() != 3) $stop; - if (q[0] != 0) $stop; - if (q[1] != 1) $stop; - if (q[2] != 2) $stop; + initial begin + q.push_front(3); + if (q.size() != 1) $stop; + q.push_front(2); + if (q.size() != 2) $stop; + q.push_front(1); + if (q.size() != 3) $stop; + q.push_front(0); + if (q.size() != 3) $stop; + q[3] = -1; + if (q.size() != 3) $stop; + if (q[0] != 0) $stop; + if (q[1] != 1) $stop; + if (q[2] != 2) $stop; - q.delete(); - q.push_back(0); - q.push_back(1); - q.push_back(2); - if (q.size() != 3) $stop; - q.push_back(3); - if (q.size() != 3) $stop; - if (q[0] != 0) $stop; - if (q[1] != 1) $stop; - if (q[2] != 2) $stop; + q.delete(); + q.push_back(0); + q.push_back(1); + q.push_back(2); + if (q.size() != 3) $stop; + q.push_back(3); + if (q.size() != 3) $stop; + if (q[0] != 0) $stop; + if (q[1] != 1) $stop; + if (q[2] != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_class.v b/test_regress/t/t_queue_class.v index ccd721d5e..e1e25595d 100644 --- a/test_regress/t/t_queue_class.v +++ b/test_regress/t/t_queue_class.v @@ -5,40 +5,40 @@ // SPDX-License-Identifier: CC0-1.0 module t; - class Cls; - int que[$]; + class Cls; + int que[$]; - task push_data(int val); - que.push_back(val); - endtask + task push_data(int val); + que.push_back(val); + endtask - function logic ok; - return '1; - endfunction - endclass + function logic ok; + return '1; + endfunction + endclass - initial begin - Cls c2 [1:0]; - Cls cq[$]; + initial begin + Cls c2[1:0]; + Cls cq[$]; - c2[0] = new(); + c2[0] = new(); - c2[0].push_data(20); // Works + c2[0].push_data(20); // Works - if (c2[0].que.size() != 1) $stop; + if (c2[0].que.size() != 1) $stop; - c2[0].que.push_back(10); // Unsupported - if (c2[0].que.size() != 2) $stop; + c2[0].que.push_back(10); // Unsupported + if (c2[0].que.size() != 2) $stop; - // Test there's no side effect warning on iteration - foreach (cq[i]) - case (cq[i].ok()) - '0: $stop; - '1: $stop; - endcase + // Test there's no side effect warning on iteration + foreach (cq[i]) + case (cq[i].ok()) + '0: $stop; + '1: $stop; + endcase - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_compare.v b/test_regress/t/t_queue_compare.v index eeaa1ddfa..cc03232c3 100644 --- a/test_regress/t/t_queue_compare.v +++ b/test_regress/t/t_queue_compare.v @@ -4,58 +4,60 @@ // SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) +// verilog_format: on class Cls; - int i; + int i; endclass module t; - initial begin - begin // integers - int q1[$]; - bit signed [31:0] q2[$]; - q1.push_back(1); - q2.push_back(1); - q1.push_back(-2); - q2.push_back(-2); - `check_eq(q1, q2) + initial begin + begin // integers + int q1[$]; + bit signed [31:0] q2[$]; + q1.push_back(1); + q2.push_back(1); + q1.push_back(-2); + q2.push_back(-2); + `check_eq(q1, q2) - q2.push_back(3); - `check_ne(q1, q2) - end - begin // strings - string q1[$]; - string q2[$]; - q1.push_back("one"); - q2.push_back("one"); - q1.push_back("two"); - q2.push_back("two"); - `check_eq(q1, q2) + q2.push_back(3); + `check_ne(q1, q2) + end + begin // strings + string q1[$]; + string q2[$]; + q1.push_back("one"); + q2.push_back("one"); + q1.push_back("two"); + q2.push_back("two"); + `check_eq(q1, q2) - q2.push_back("three"); - `check_ne(q1, q2) - end + q2.push_back("three"); + `check_ne(q1, q2) + end - begin // classes - automatic Cls a = new; - automatic Cls b = new; - Cls q1[$]; - Cls q2[$]; - q1.push_back(a); - q2.push_back(b); - `check_ne(q1, q2) + begin // classes + automatic Cls a = new; + automatic Cls b = new; + Cls q1[$]; + Cls q2[$]; + q1.push_back(a); + q2.push_back(b); + `check_ne(q1, q2) - q1.push_back(b); - q2.push_front(a); - `check_eq(q1, q2) - end + q1.push_back(b); + q2.push_front(a); + `check_eq(q1, q2) + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_empty_bad.out b/test_regress/t/t_queue_empty_bad.out index c8fe1528e..00130c436 100644 --- a/test_regress/t/t_queue_empty_bad.out +++ b/test_regress/t/t_queue_empty_bad.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_queue_empty_bad.v:11:11: Unsupported/Illegal: empty queue ('{}') in this context - : ... note: In instance 't' - 11 | i = {} + 1; - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_queue_empty_bad.v:13:9: Unsupported/Illegal: empty queue ('{}') in this assign context +%Error-UNSUPPORTED: t/t_queue_empty_bad.v:11:9: Unsupported/Illegal: empty queue ('{}') in this context : ... note: In instance 't' - 13 | i = {}; + 11 | i = {} + 1; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_queue_empty_bad.v:13:7: Unsupported/Illegal: empty queue ('{}') in this assign context + : ... note: In instance 't' + 13 | i = {}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_queue_empty_bad.v b/test_regress/t/t_queue_empty_bad.v index f0a356582..6e094f4e3 100644 --- a/test_regress/t/t_queue_empty_bad.v +++ b/test_regress/t/t_queue_empty_bad.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int i; + initial begin + int i; - i = {} + 1; + i = {} + 1; - i = {}; + i = {}; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_empty_pin.v b/test_regress/t/t_queue_empty_pin.v index db9c04f0f..be0f5a869 100644 --- a/test_regress/t/t_queue_empty_pin.v +++ b/test_regress/t/t_queue_empty_pin.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 module t; - task tsk(int q[] = {}); - if (q.size != 0) $stop; - endtask + task tsk(int q[] = {}); + if (q.size != 0) $stop; + endtask - initial begin - tsk(); + initial begin + tsk(); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v index ae59cfaa0..743bc4716 100644 --- a/test_regress/t/t_queue_method.v +++ b/test_regress/t/t_queue_method.v @@ -4,245 +4,257 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on class Cls; - int x; - function new(int a); - x = a; - endfunction + int x; + function new(int a); + x = a; + endfunction endclass module t; - typedef struct packed { int x, y; } point; - typedef struct packed { point p; int z; } point_3d; - initial begin - int q[$]; - int qe[$]; // Empty - int qv[$]; // Value returns - int qvunused[$]; // Value returns (unused) - int qi[$]; // Index returns - int i; - bit b; - string string_q[$]; - string string_qv[$]; - point_3d points_q[$]; // Same as q and qv, but complex value type - point_3d points_qv[$]; - Cls cls; - Cls cls_q[$]; - Cls cls_qv[$]; + typedef struct packed {int x, y;} point; + typedef struct packed { + point p; + int z; + } point_3d; - points_q.push_back(point_3d'{point'{1, 2}, 3}); - points_q.push_back(point_3d'{point'{2, 3}, 5}); - points_q.push_back(point_3d'{point'{1, 4}, 5}); + initial begin + int q[$]; + int qe[$]; // Empty + int qv[$]; // Value returns + int qvunused[$]; // Value returns (unused) + int qi[$]; // Index returns + int i; + bit b; + string string_q[$]; + string string_qv[$]; + point_3d points_q[$]; // Same as q and qv, but complex value type + point_3d points_qv[$]; + Cls cls; + Cls cls_q[$]; + Cls cls_qv[$]; + + points_q.push_back(point_3d'{point'{1, 2}, 3}); + points_q.push_back(point_3d'{point'{2, 3}, 5}); + points_q.push_back(point_3d'{point'{1, 4}, 5}); - cls = new(1); - cls_q.push_back(cls); - cls = new(2); - cls_q.push_back(cls); - cls = new(1); - cls_q.push_back(cls); + cls = new(1); + cls_q.push_back(cls); + cls = new(2); + cls_q.push_back(cls); + cls = new(1); + cls_q.push_back(cls); - string_q.push_back("a"); - string_q.push_back("A"); - string_q.push_back("b"); + string_q.push_back("a"); + string_q.push_back("A"); + string_q.push_back("b"); - q = '{1, 2, 2, 4, 3}; - `checkp(q, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); + q = '{1, 2, 2, 4, 3}; + `checkp(q, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); - // sort/rsort with clause is the field to use for the sorting - q.sort; - `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - q.sort with (10 - item); - `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - q.sort(x) with (10 - x); - `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - qe.sort(x) with (10 - x); - `checkp(qe, "'{}"); - q.rsort; - `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); - q.rsort with (10 - item); - `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - qe.rsort(x) with (10 - x); - `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + // sort/rsort with clause is the field to use for the sorting + q.sort; + `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + q.sort with (10 - item); + `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + q.sort(x) with (10 - x); + `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + qe.sort(x) with (10 - x); + `checkp(qe, "'{}"); + q.rsort; + `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); + q.rsort with (10 - item); + `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + qe.rsort(x) with (10 - x); + `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - q = '{2, 2, 4, 1, 3}; - qv = q.unique; - `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); - qv = qe.unique; - `checkh(qv.size(), 0); - qv = q.unique(x) with (x % 2); - `checkh(qv.size(), 2); - string_qv = string_q.unique(s) with (s.toupper); - `checkh(string_qv.size(), 2); - qi = q.unique_index; qv.sort; - // According to IEEE 1800-2023 7.12.1, it is not specified which index of duplicated value should be returned - `checkh(qi.size(), 4); - qi.delete(1); - `checkp(qi, "'{'h0, 'h3, 'h4}"); - qi = qe.unique_index; - `checkh(qi.size(), 0); - qi = q.unique_index(x) with (x % 3); qv.sort; - `checkh(qi.size(), 3); - cls_qv = cls_q.unique with (item.x); - `checkh(cls_qv.size(), 2); - cls_qv = cls_q.unique with (item.x < 10); - `checkh(cls_qv.size(), 1); - qi = cls_q.unique_index with (item.x % 2); - qi.sort; - `checkp(qi, "'{'h0, 'h1}"); + q = '{2, 2, 4, 1, 3}; + qv = q.unique; + `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); + qv = qe.unique; + `checkh(qv.size(), 0); + qv = q.unique(x) with (x % 2); + `checkh(qv.size(), 2); + string_qv = string_q.unique(s) with (s.toupper); + `checkh(string_qv.size(), 2); + qi = q.unique_index; + qv.sort; + // According to IEEE 1800-2023 7.12.1, it is not specified which index of duplicated value should be returned + `checkh(qi.size(), 4); + qi.delete(1); + `checkp(qi, "'{'h0, 'h3, 'h4}"); + qi = qe.unique_index; + `checkh(qi.size(), 0); + qi = q.unique_index (x) with (x % 3); + qv.sort; + `checkh(qi.size(), 3); + cls_qv = cls_q.unique with (item.x); + `checkh(cls_qv.size(), 2); + cls_qv = cls_q.unique with (item.x < 10); + `checkh(cls_qv.size(), 1); + qi = cls_q.unique_index with (item.x % 2); + qi.sort; + `checkp(qi, "'{'h0, 'h1}"); - q.reverse; - `checkp(q, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); - qe.reverse; - `checkh(qe.size(), 0); - q.shuffle(); q.sort; - `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); - qe.shuffle(); - `checkh(qe.size(), 0); + q.reverse; + `checkp(q, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); + qe.reverse; + `checkh(qe.size(), 0); + q.shuffle(); + q.sort; + `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); + qe.shuffle(); + `checkh(qe.size(), 0); - // These require an with clause or are illegal - // TODO add a lint check that with clause is provided - qv = q.find with (item == 2); - `checkp(qv, "'{'h2, 'h2}"); - qv = q.find with (item[0] == 1); - `checkp(qv, "'{'h1, 'h3}"); - qv = q.find_first with (item == 2); - `checkp(qv, "'{'h2}"); - points_qv = points_q.find_first with (item.z == 5); - `checkh(points_qv[0].p.y, 3); - points_qv = points_q.find_first with (item.p.x == 1); - `checkh(points_qv[0].p.y, 2); - qv = q.find_last with (item == 2); - `checkp(qv, "'{'h2}"); - string_qv = string_q.find_last(s) with (s.tolower() == "a"); - `checks(string_qv[0], "A"); + // These require an with clause or are illegal + // TODO add a lint check that with clause is provided + qv = q.find with (item == 2); + `checkp(qv, "'{'h2, 'h2}"); + qv = q.find with (item[0] == 1); + `checkp(qv, "'{'h1, 'h3}"); + qv = q.find_first with (item == 2); + `checkp(qv, "'{'h2}"); + points_qv = points_q.find_first with (item.z == 5); + `checkh(points_qv[0].p.y, 3); + points_qv = points_q.find_first with (item.p.x == 1); + `checkh(points_qv[0].p.y, 2); + qv = q.find_last with (item == 2); + `checkp(qv, "'{'h2}"); + string_qv = string_q.find_last(s) with (s.tolower() == "a"); + `checks(string_qv[0], "A"); - qv = q.find with (item == 20); - `checkh(qv.size, 0); - qv = q.find_first with (item == 20); - `checkh(qv.size, 0); - qv = q.find_last with (item == 20); - `checkh(qv.size, 0); + qv = q.find with (item == 20); + `checkh(qv.size, 0); + qv = q.find_first with (item == 20); + `checkh(qv.size, 0); + qv = q.find_last with (item == 20); + `checkh(qv.size, 0); - // Check gate eater with Lambda variable removal - qvunused = q.find with (item == 20); + // Check gate eater with Lambda variable removal + qvunused = q.find with (item == 20); - qi = q.find_index with (item == 2); - qi.sort; `checkp(qi, "'{'h1, 'h2}"); - qi = q.find_first_index with (item == 2); - `checkp(qi, "'{'h1}"); - qi = q.find_last_index with (item == 2); - `checkp(qi, "'{'h2}"); + qi = q.find_index with (item == 2); + qi.sort; + `checkp(qi, "'{'h1, 'h2}"); + qi = q.find_first_index with (item == 2); + `checkp(qi, "'{'h1}"); + qi = q.find_last_index with (item == 2); + `checkp(qi, "'{'h2}"); - i = 2; - qi = q.find_index with (item == i); - qi.sort; `checkp(qi, "'{'h1, 'h2}"); + i = 2; + qi = q.find_index with (item == i); + qi.sort; + `checkp(qi, "'{'h1, 'h2}"); - qi = q.find_index with (item == 20); qi.sort; - `checkh(qi.size, 0); - qi = q.find_first_index with (item == 20); - `checkh(qi.size, 0); - qi = q.find_last_index with (item == 20); - `checkh(qi.size, 0); + qi = q.find_index with (item == 20); + qi.sort; + `checkh(qi.size, 0); + qi = q.find_first_index with (item == 20); + `checkh(qi.size, 0); + qi = q.find_last_index with (item == 20); + `checkh(qi.size, 0); - qi = q.find_index with (item.index == 2); - `checkp(qi, "'{'h2}"); - qi = q.find_index with (item.index == item); - `checkp(qi, "'{'h2, 'h3, 'h4}"); + qi = q.find_index with (item.index == 2); + `checkp(qi, "'{'h2}"); + qi = q.find_index with (item.index == item); + `checkp(qi, "'{'h2, 'h3, 'h4}"); - qv = q.min; - `checkp(qv, "'{'h1}"); - qv = q.min(x) with (x + 1); - `checkp(qv, "'{'h1}"); - qv = q.max; - `checkp(qv, "'{'h4}"); - qv = q.max(x) with ((x % 4) + 100); - `checkp(qv, "'{'h3}"); - qv = qe.min; - `checkp(qv, "'{}"); - qv = qe.max; - `checkp(qv, "'{}"); + qv = q.min; + `checkp(qv, "'{'h1}"); + qv = q.min(x) with (x + 1); + `checkp(qv, "'{'h1}"); + qv = q.max; + `checkp(qv, "'{'h4}"); + qv = q.max(x) with ((x % 4) + 100); + `checkp(qv, "'{'h3}"); + qv = qe.min; + `checkp(qv, "'{}"); + qv = qe.max; + `checkp(qv, "'{}"); - // Reduction methods - i = q.sum; - `checkh(i, 32'hc); - i = q.sum with (item + 1); - `checkh(i, 32'h11); - i = q.sum(myi) with (myi + 1); - `checkh(i, 32'h11); - i = q.sum with (1); // unused 'index' - `checkh(i, 32'h5); - i = q.sum(unused) with (1); // unused 'unused' - `checkh(i, 32'h5); + // Reduction methods + i = q.sum; + `checkh(i, 32'hc); + i = q.sum with (item + 1); + `checkh(i, 32'h11); + i = q.sum(myi) with (myi + 1); + `checkh(i, 32'h11); + i = q.sum with (1); // unused 'index' + `checkh(i, 32'h5); + i = q.sum(unused) with (1); // unused 'unused' + `checkh(i, 32'h5); - i = q.product; - `checkh(i, 32'h30); - i = q.product with (item + 1); - `checkh(i, 32'h168); + i = q.product; + `checkh(i, 32'h30); + i = q.product with (item + 1); + `checkh(i, 32'h168); - i = qe.sum; - `checkh(i, 32'h0); - i = qe.sum with (item + 1); - `checkh(i, 32'h0); + i = qe.sum; + `checkh(i, 32'h0); + i = qe.sum with (item + 1); + `checkh(i, 32'h0); - i = qe.product; - `checkh(i, 32'h0); - i = qe.product with (item + 1); - `checkh(i, 32'h0); + i = qe.product; + `checkh(i, 32'h0); + i = qe.product with (item + 1); + `checkh(i, 32'h0); - q = '{32'b1100, 32'b1010}; - i = q.and; - `checkh(i, 32'b1000); - i = q.and with (item + 1); - `checkh(i, 32'b1001); - i = q.or; - `checkh(i, 32'b1110); - i = q.or with (item + 1); - `checkh(i, 32'b1111); - i = q.xor; - `checkh(i, 32'b0110); - i = q.xor with (item + 1); - `checkh(i, 32'b0110); + q = '{32'b1100, 32'b1010}; + i = q.and; + `checkh(i, 32'b1000); + i = q.and with (item + 1); + `checkh(i, 32'b1001); + i = q.or; + `checkh(i, 32'b1110); + i = q.or with (item + 1); + `checkh(i, 32'b1111); + i = q.xor; + `checkh(i, 32'b0110); + i = q.xor with (item + 1); + `checkh(i, 32'b0110); - i = qe.and; - `checkh(i, 32'b0); - i = qe.and with (item + 1); - `checkh(i, 32'b0); - i = qe.or; - `checkh(i, 32'b0); - i = qe.or with (item + 1); - `checkh(i, 32'b0); - i = qe.xor; - `checkh(i, 32'b0); - i = qe.xor with (item + 1); - `checkh(i, 32'b0); + i = qe.and; + `checkh(i, 32'b0); + i = qe.and with (item + 1); + `checkh(i, 32'b0); + i = qe.or; + `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); + i = qe.xor; + `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); - q = '{1, 2}; - qe = '{1, 2}; - `checkh(q == qe, 1'b1); - `checkh(q != qe, 1'b0); + q = '{1, 2}; + qe = '{1, 2}; + `checkh(q == qe, 1'b1); + `checkh(q != qe, 1'b0); - string_q = {"a", "bc", "def", "ghij"}; + string_q = {"a", "bc", "def", "ghij"}; - i = string_q.sum with (item.len); - `checkh(i, 10); - i = string_q.product with (item.len); - `checkh(i, 24); - b = string_q.sum with (item == "bc"); - `checkh(b, 1'b1); - b = string_q.sum with (item == ""); - `checkh(b, 1'b0); - b = string_q.product with (item inside {"a", "bc", "def"}); - `checkh(b, 1'b0); - b = string_q.product with (item inside {"a", "bc", "def", "ghij"}); - `checkh(b, 1'b1); + i = string_q.sum with (item.len); + `checkh(i, 10); + i = string_q.product with (item.len); + `checkh(i, 24); + b = string_q.sum with (item == "bc"); + `checkh(b, 1'b1); + b = string_q.sum with (item == ""); + `checkh(b, 1'b0); + b = string_q.product with (item inside {"a", "bc", "def"}); + `checkh(b, 1'b0); + b = string_q.product with (item inside {"a", "bc", "def", "ghij"}); + `checkh(b, 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_method2_bad.out b/test_regress/t/t_queue_method2_bad.out index a765361a4..6e7780f9e 100644 --- a/test_regress/t/t_queue_method2_bad.out +++ b/test_regress/t/t_queue_method2_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_queue_method2_bad.v:16:21: 'with' function expects only up to one argument - 16 | qi = q.find(a,b) with (0); - | ^ +%Error: t/t_queue_method2_bad.v:16:20: 'with' function expects only up to one argument + 16 | qi = q.find(a, b) with (0); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_queue_method2_bad.v:17:19: 'with' function expects simple variable name - 17 | qi = q.find(1) with (0); - | ^ +%Error: t/t_queue_method2_bad.v:17:17: 'with' function expects simple variable name + 17 | qi = q.find(1) with (0); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_queue_method2_bad.v b/test_regress/t/t_queue_method2_bad.v index b664a5033..ce6c6690f 100644 --- a/test_regress/t/t_queue_method2_bad.v +++ b/test_regress/t/t_queue_method2_bad.v @@ -5,18 +5,18 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int q[$]; - int qe[$]; // Empty - int qv[$]; // Value returns - int qi[$]; // Index returns + initial begin + int q[$]; + int qe[$]; // Empty + int qv[$]; // Value returns + int qi[$]; // Index returns - q = '{2, 2, 4, 1, 3}; + q = '{2, 2, 4, 1, 3}; - qi = q.find(a,b) with (0); // b is extra - qi = q.find(1) with (0); // 1 is illegal + qi = q.find(a, b) with (0); // b is extra + qi = q.find(1) with (0); // 1 is illegal - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_method3_bad.out b/test_regress/t/t_queue_method3_bad.out index 041af3fa2..d5ab8cb43 100644 --- a/test_regress/t/t_queue_method3_bad.out +++ b/test_regress/t/t_queue_method3_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_queue_method3_bad.v:16:52: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'int'' +%Error-UNSUPPORTED: t/t_queue_method3_bad.v:16:50: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'int'' : ... note: In instance 't' - 16 | points_qv = points_q.find_first(a) with (a.x.index == 0); - | ^~~~~ + 16 | points_qv = points_q.find_first(a) with (a.x.index == 0); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_queue_method3_bad.v b/test_regress/t/t_queue_method3_bad.v index d173f0ce8..8820e2c74 100644 --- a/test_regress/t/t_queue_method3_bad.v +++ b/test_regress/t/t_queue_method3_bad.v @@ -5,17 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 module t; - typedef struct packed { int x, y; } point; - initial begin - point points_q[$]; - point points_qv[$]; - points_q.push_back(point'{1, 2}); + typedef struct packed {int x, y;} point; + initial begin + point points_q[$]; + point points_qv[$]; + points_q.push_back(point'{1, 2}); - // `index` should be treated as normal member select, - // but the member is not present in the struct - points_qv = points_q.find_first(a) with (a.x.index == 0); + // `index` should be treated as normal member select, + // but the member is not present in the struct + points_qv = points_q.find_first(a) with (a.x.index == 0); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_method_bad.out b/test_regress/t/t_queue_method_bad.out index b2a213874..25e49ee98 100644 --- a/test_regress/t/t_queue_method_bad.out +++ b/test_regress/t/t_queue_method_bad.out @@ -1,38 +1,38 @@ -%Error: t/t_queue_method_bad.v:15:9: The 1 arguments passed to .reverse method does not match its requiring 0 arguments +%Error: t/t_queue_method_bad.v:15:7: The 1 arguments passed to .reverse method does not match its requiring 0 arguments : ... note: In instance 't' - 15 | q.reverse(1); - | ^~~~~~~ + 15 | q.reverse(1); + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_queue_method_bad.v:16:9: The 1 arguments passed to .shuffle method does not match its requiring 0 arguments +%Error: t/t_queue_method_bad.v:16:7: The 1 arguments passed to .shuffle method does not match its requiring 0 arguments : ... note: In instance 't' - 16 | q.shuffle(1); - | ^~~~~~~ -%Error: t/t_queue_method_bad.v:17:14: 'with' statement is required for .find method + 16 | q.shuffle(1); + | ^~~~~~~ +%Error: t/t_queue_method_bad.v:17:12: 'with' statement is required for .find method : ... note: In instance 't' - 17 | qv = q.find; - | ^~~~ -%Error: t/t_queue_method_bad.v:18:14: 'with' statement is required for .find_first method + 17 | qv = q.find; + | ^~~~ +%Error: t/t_queue_method_bad.v:18:12: 'with' statement is required for .find_first method : ... note: In instance 't' - 18 | qv = q.find_first; - | ^~~~~~~~~~ -%Error: t/t_queue_method_bad.v:19:14: 'with' statement is required for .find_last method + 18 | qv = q.find_first; + | ^~~~~~~~~~ +%Error: t/t_queue_method_bad.v:19:12: 'with' statement is required for .find_last method : ... note: In instance 't' - 19 | qv = q.find_last; - | ^~~~~~~~~ -%Error: t/t_queue_method_bad.v:20:14: 'with' statement is required for .find_index method + 19 | qv = q.find_last; + | ^~~~~~~~~ +%Error: t/t_queue_method_bad.v:20:12: 'with' statement is required for .find_index method : ... note: In instance 't' - 20 | qi = q.find_index; - | ^~~~~~~~~~ -%Error: t/t_queue_method_bad.v:21:14: 'with' statement is required for .find_first_index method + 20 | qi = q.find_index; + | ^~~~~~~~~~ +%Error: t/t_queue_method_bad.v:21:12: 'with' statement is required for .find_first_index method : ... note: In instance 't' - 21 | qi = q.find_first_index; - | ^~~~~~~~~~~~~~~~ -%Error: t/t_queue_method_bad.v:22:14: 'with' statement is required for .find_last_index method + 21 | qi = q.find_first_index; + | ^~~~~~~~~~~~~~~~ +%Error: t/t_queue_method_bad.v:22:12: 'with' statement is required for .find_last_index method : ... note: In instance 't' - 22 | qi = q.find_last_index; - | ^~~~~~~~~~~~~~~ -%Error: t/t_queue_method_bad.v:24:19: 'with' not legal on this method + 22 | qi = q.find_last_index; + | ^~~~~~~~~~~~~~~ +%Error: t/t_queue_method_bad.v:24:17: 'with' not legal on this method : ... note: In instance 't' - 24 | qi = q.size with (1); - | ^~~~ + 24 | qi = q.size with (1); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_queue_method_bad.v b/test_regress/t/t_queue_method_bad.v index f441ec850..8ec959b90 100644 --- a/test_regress/t/t_queue_method_bad.v +++ b/test_regress/t/t_queue_method_bad.v @@ -5,25 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int q[$]; - int qe[$]; // Empty - int qv[$]; // Value returns - int qi[$]; // Index returns + initial begin + int q[$]; + int qe[$]; // Empty + int qv[$]; // Value returns + int qi[$]; // Index returns - q = '{2, 2, 4, 1, 3}; - q.reverse(1); // Bad no args allowed - q.shuffle(1); // Bad no args allowed - qv = q.find; // Bad missing with - qv = q.find_first; // Bad missing with - qv = q.find_last; // Bad missing with - qi = q.find_index; // Bad missing with - qi = q.find_first_index; // Bad missing with - qi = q.find_last_index; // Bad missing with + q = '{2, 2, 4, 1, 3}; + q.reverse(1); // Bad no args allowed + q.shuffle(1); // Bad no args allowed + qv = q.find; // Bad missing with + qv = q.find_first; // Bad missing with + qv = q.find_last; // Bad missing with + qi = q.find_index; // Bad missing with + qi = q.find_first_index; // Bad missing with + qi = q.find_last_index; // Bad missing with - qi = q.size with (1); // with not allowed + qi = q.size with (1); // with not allowed - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_output_func.v b/test_regress/t/t_queue_output_func.v index b571b5aea..cf0ad79d5 100644 --- a/test_regress/t/t_queue_output_func.v +++ b/test_regress/t/t_queue_output_func.v @@ -5,23 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - int x = 1; + int x = 1; endclass -task init_set_2 (output Cls c); - c = new; - c.x = 2; +task init_set_2(output Cls c); + c = new; + c.x = 2; endtask module t; - initial begin - Cls cls_q[$]; - init_set_2(cls_q[0]); - if (cls_q[0].x != 2) $stop; + initial begin + Cls cls_q[$]; + init_set_2(cls_q[0]); + if (cls_q[0].x != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_persistence.v b/test_regress/t/t_queue_persistence.v index f6ac3698d..6da21306b 100644 --- a/test_regress/t/t_queue_persistence.v +++ b/test_regress/t/t_queue_persistence.v @@ -4,54 +4,56 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int qdel[$]; - int qkept[$]; + int qdel[$]; + int qkept[$]; - task automatic func(ref int vrefed); + task automatic func(ref int vrefed); `ifdef TEST_NOINLINE - // verilator no_inline_task + // verilator no_inline_task `endif - `checkd(vrefed, 2); - #100; - vrefed = 10; - #10; - `checkd(vrefed, 10); - endtask + `checkd(vrefed, 2); + #100; + vrefed = 10; + #10; + `checkd(vrefed, 10); + endtask - initial begin - qkept.push_back(1); - qkept.push_back(2); - qkept.push_back(3); - qdel = qkept; - $display("qkept=%p qdel=%p", qkept, qdel); - `checkd(qkept[0], 1); - `checkd(qkept[1], 2); - `checkd(qkept[2], 3); + initial begin + qkept.push_back(1); + qkept.push_back(2); + qkept.push_back(3); + qdel = qkept; + $display("qkept=%p qdel=%p", qkept, qdel); + `checkd(qkept[0], 1); + `checkd(qkept[1], 2); + `checkd(qkept[2], 3); - func(qdel[1]); - func(qkept[1]); + func(qdel[1]); + func(qkept[1]); - $display("qkept=%p qdel=%p", qkept, qdel); - `checkd(qdel.size, 0); - `checkd(qkept[0], 1); - `checkd(qkept[1], 10); - `checkd(qkept[2], 3); - end + $display("qkept=%p qdel=%p", qkept, qdel); + `checkd(qdel.size, 0); + `checkd(qkept[0], 1); + `checkd(qkept[1], 10); + `checkd(qkept[2], 3); + end - initial begin - #50; - `checkd(qdel[1], 2); - `checkd(qkept[1], 2); - qdel.delete(); - #100; + initial begin + #50; + `checkd(qdel[1], 2); + `checkd(qkept[1], 2); + qdel.delete(); + #100; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_pushpop.v b/test_regress/t/t_queue_pushpop.v index be21ae97c..cfb31ee91 100644 --- a/test_regress/t/t_queue_pushpop.v +++ b/test_regress/t/t_queue_pushpop.v @@ -4,39 +4,39 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - logic q [$]; - int cycle = 0; + logic q[$]; + int cycle = 0; - always @(posedge clk) begin - cycle <= cycle + 1'b1; - end + always @(posedge clk) begin + cycle <= cycle + 1'b1; + end - always @(posedge clk) begin - q.push_front(1'b1); - end + always @(posedge clk) begin + q.push_front(1'b1); + end - // Important this is a separate always to expose bug where "q" thought unused - always @(posedge clk) begin - if (cycle == 1) begin - if (q.pop_back() != 1) $stop; - end - end + // Important this is a separate always to expose bug where "q" thought unused + always @(posedge clk) begin + if (cycle == 1) begin + if (q.pop_back() != 1) $stop; + end + end - always @(posedge clk) begin - if (cycle == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cycle == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_queue_slice.v b/test_regress/t/t_queue_slice.v index 925dd6122..cae6faf09 100644 --- a/test_regress/t/t_queue_slice.v +++ b/test_regress/t/t_queue_slice.v @@ -4,120 +4,135 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - initial begin - typedef string q_t[$]; - q_t q; - string v; - int i; - int qi[$:5]; - int ri[$]; + initial begin + typedef string q_t[$]; + q_t q; + string v; + int i; + int qi[$:5]; + int ri[$]; - q.push_front("non-empty"); - i = q.size(); `checkh(i, 1); - `checkp(q, "'{\"non-empty\"}"); + q.push_front("non-empty"); + i = q.size(); + `checkh(i, 1); + `checkp(q, "'{\"non-empty\"}"); - q = '{}; - i = q.size(); `checkh(i, 0); + q = '{}; + i = q.size(); + `checkh(i, 0); - q = '{"q"}; - `checkp(q, "'{\"q\"}"); + q = '{"q"}; + `checkp(q, "'{\"q\"}"); - q = {}; - i = q.size(); `checkh(i, 0); + q = {}; + i = q.size(); + `checkh(i, 0); - q = '{"q", "b", "c", "d", "e", "f"}; - if (q[0] !== "q") $stop; - `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); + q = '{"q", "b", "c", "d", "e", "f"}; + if (q[0] !== "q") $stop; + `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); - q = {"q", "b", "c", "d", "e", "f"}; - `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); + q = {"q", "b", "c", "d", "e", "f"}; + `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); - q.delete(1); - v = q[1]; `checks(v, "c"); - `checkp(q, "'{\"q\", \"c\", \"d\", \"e\", \"f\"}"); + q.delete(1); + v = q[1]; + `checks(v, "c"); + `checkp(q, "'{\"q\", \"c\", \"d\", \"e\", \"f\"}"); - q.insert(0, "ins0"); - q.insert(2, "ins2"); - v = q[0]; `checks(v, "ins0"); - v = q[2]; `checks(v, "ins2"); - `checkp(q, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"}"); + q.insert(0, "ins0"); + q.insert(2, "ins2"); + v = q[0]; + `checks(v, "ins0"); + v = q[2]; + `checks(v, "ins2"); + `checkp(q, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"}"); - // Slicing - q = '{"q", "b", "c", "d", "e", "f"}; - q = q[-1:0]; - `checkp(q, "'{\"q\"}"); - q = '{"q", "b", "c", "d", "e", "f"}; - q = q[2:3]; - `checkp(q, "'{\"c\", \"d\"}"); - q = '{"q", "b", "c", "d", "e", "f"}; - q = q[3:$]; - `checkp(q, "'{\"d\", \"e\", \"f\"}"); - q = q[$:$]; - `checkp(q, "'{\"f\"}"); + // Slicing + q = '{"q", "b", "c", "d", "e", "f"}; + q = q[-1:0]; + `checkp(q, "'{\"q\"}"); + q = '{"q", "b", "c", "d", "e", "f"}; + q = q[2:3]; + `checkp(q, "'{\"c\", \"d\"}"); + q = '{"q", "b", "c", "d", "e", "f"}; + q = q[3:$]; + `checkp(q, "'{\"d\", \"e\", \"f\"}"); + q = q[$:$]; + `checkp(q, "'{\"f\"}"); - // Similar using implied notation - q = '{"f"}; - q = {q, "f1"}; // push_front - q = {q, "f2"}; // push_front - q = {"b1", q}; // push_back - q = {"b2", q}; // push_back - `checkp(q, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"}"); + // Similar using implied notation + q = '{"f"}; + q = {q, "f1"}; // push_front + q = {q, "f2"}; // push_front + q = {"b1", q}; // push_back + q = {"b2", q}; // push_back + `checkp(q, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"}"); - q = {q[0], q[2:$]}; // delete element 1 - `checkp(q, "'{\"b2\", \"f\", \"f1\", \"f2\"}"); + q = {q[0], q[2:$]}; // delete element 1 + `checkp(q, "'{\"b2\", \"f\", \"f1\", \"f2\"}"); - q = {"a", "b"}; - q = {q, q}; - `checkp(q, "'{\"a\", \"b\", \"a\", \"b\"}"); + q = {"a", "b"}; + q = {q, q}; + `checkp(q, "'{\"a\", \"b\", \"a\", \"b\"}"); - begin - static string ai[$] = '{ "Foo", "Bar" }; - q = ai; // Copy - i = q.size(); `checkh(i, 2); - v = q.pop_front(); `checks(v, "Foo"); - v = q.pop_front(); `checks(v, "Bar"); - q = '{ "BB", "CC" }; // Note '{} not {} - v = q.pop_front(); `checks(v, "BB"); - v = q.pop_front(); `checks(v, "CC"); - q = { "BB", "CC" }; // Note {} not '{} - v = q.pop_front(); `checks(v, "BB"); - v = q.pop_front(); `checks(v, "CC"); - end + begin + static string ai[$] = '{"Foo", "Bar"}; + q = ai; // Copy + i = q.size(); + `checkh(i, 2); + v = q.pop_front(); + `checks(v, "Foo"); + v = q.pop_front(); + `checks(v, "Bar"); + q = '{"BB", "CC"}; // Note '{} not {} + v = q.pop_front(); + `checks(v, "BB"); + v = q.pop_front(); + `checks(v, "CC"); + q = {"BB", "CC"}; // Note {} not '{} + v = q.pop_front(); + `checks(v, "BB"); + v = q.pop_front(); + `checks(v, "CC"); + end - begin - qi.push_back(0); - qi.push_back(1); - qi.push_back(2); - qi.push_back(3); - qi.push_back(4); - qi.push_back(5); + begin + qi.push_back(0); + qi.push_back(1); + qi.push_back(2); + qi.push_back(3); + qi.push_back(4); + qi.push_back(5); - // Assignment to unsized queue from sized queue - ri = qi[ 2 : 4 ]; - `checkh(ri.size, 3); - ri = qi[ 4 : 2 ]; - `checkh(ri.size, 0); - ri = qi[ 2 : 2 ]; - `checkh(ri.size, 1); - ri = qi[ -2 : 2 ]; // 2 - 0 + 1 = 3 - `checkh(ri.size, 3); - ri = qi[ 2 : 10 ]; // 5 - 2 + 1 = 4 - `checkh(ri.size, 4); + // Assignment to unsized queue from sized queue + ri = qi[2 : 4]; + `checkh(ri.size, 3); + ri = qi[4 : 2]; + `checkh(ri.size, 0); + ri = qi[2 : 2]; + `checkh(ri.size, 1); + ri = qi[-2 : 2]; // 2 - 0 + 1 = 3 + `checkh(ri.size, 3); + ri = qi[2 : 10]; // 5 - 2 + 1 = 4 + `checkh(ri.size, 4); - // Assignment from unsized to sized - ri = '{1,2,3,4,5,6,7,8,9}; - qi = ri; - `checkh(qi.size, 5); - end + // Assignment from unsized to sized + ri = '{1, 2, 3, 4, 5, 6, 7, 8, 9}; + qi = ri; + `checkh(qi.size, 5); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_struct.v b/test_regress/t/t_queue_struct.v index 77969a1b0..4c1f276c4 100644 --- a/test_regress/t/t_queue_struct.v +++ b/test_regress/t/t_queue_struct.v @@ -4,42 +4,40 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef struct { - int b[$]; - } st_t; + typedef struct {int b[$];} st_t; - typedef struct { - int v; - } st_in_t; + typedef struct {int v;} st_in_t; - function automatic st_t bar(); - // verilator no_inline_task - for (int i = 0; i < 4; ++i) begin - bar.b.push_back(i); - end - endfunction // bar + function automatic st_t bar(); + // verilator no_inline_task + for (int i = 0; i < 4; ++i) begin + bar.b.push_back(i); + end + endfunction // bar - st_t res; - st_in_t q[$]; + st_t res; + st_in_t q[$]; - initial begin - res = bar(); - `checkd(res.b[0], 0); - `checkd(res.b[1], 1); - `checkd(res.b[2], 2); - `checkd(res.b[3], 3); + initial begin + res = bar(); + `checkd(res.b[0], 0); + `checkd(res.b[1], 1); + `checkd(res.b[2], 2); + `checkd(res.b[3], 3); - q.push_back(st_in_t'{15}); - q[0].v++; - `checkd(q[0].v, 16); + q.push_back(st_in_t'{15}); + q[0].v++; + `checkd(q[0].v, 16); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_unknown_sel.v b/test_regress/t/t_queue_unknown_sel.v index 74c4033b7..3e21887b0 100644 --- a/test_regress/t/t_queue_unknown_sel.v +++ b/test_regress/t/t_queue_unknown_sel.v @@ -5,404 +5,428 @@ // SPDX-License-Identifier: CC0-1.0 package z_pkg; - localparam int OPCODEW=3; - localparam int CIDW=4; - localparam int SIDW=10; - localparam int CTAGW=7; - localparam int STAGW=9; - localparam int STATEW=3; - localparam int ADDRW=37; - localparam int DATAW=256; - localparam int MASKW=DATAW/8; - localparam int SIZEW=4; - typedef enum logic [OPCODEW-1:0] { - A = 3'h 0, - B = 3'h 1 - } a_op_t; - typedef enum logic [OPCODEW-1:0] { - C = 3'h 0, - D = 3'h 1 - } b_op_t; - typedef enum logic [OPCODEW-1:0] { - E = 3'h 0, - F = 3'h 1 - } c_op_t; - typedef enum logic [OPCODEW-1:0] { - G = 3'h 0, - H = 3'h 1 - } d_op_t; - typedef logic [CIDW-1:0] cid_t; - typedef logic [SIDW-1:0] sid_t; - typedef logic [CTAGW-1:0] ctag_t; - typedef logic [STAGW-1:0] stag_t; - typedef logic [STATEW-1:0] state_t; - typedef logic [ADDRW-1:0] address_t; - typedef logic [SIZEW-1:0] size_t; - typedef logic [DATAW-1:0] data_t; - typedef logic [MASKW-1:0] mask_t; - typedef struct packed { - cid_t cid; - a_op_t opcode; - address_t address; - } x1_ch_t; - typedef struct packed { - cid_t cid; - b_op_t opcode; - address_t address; - } x2_ch_t; - typedef struct packed { - cid_t cid; - sid_t sid; - ctag_t ctag; - stag_t stag; - c_op_t opcode; - state_t state2; - state_t state3; - address_t address; - logic f4; - size_t size; - logic f2; - } x3_ch_t; - typedef struct packed { - cid_t cid; - sid_t sid; - ctag_t ctag; - stag_t stag; - d_op_t opcode; - state_t state1; - logic f4; - logic f1; - size_t size; - logic f3; - } x4_ch_t; - typedef struct packed { - cid_t cid; - ctag_t ctag; - stag_t stag; - d_op_t opcode; - logic f1; - logic f3; - } x5_ch_t; - typedef struct packed { - logic last; - logic corrupt; - } x6_ch_t; - typedef struct packed { - sid_t sid; - stag_t stag; - } x7_ch_t; - typedef enum { - CH_X1, - CH_Y1, - CH_Y2, - CH_X2, - CH_X3, - CH_Y3, - CH_X4, - CH_X5, - CH_X6, - CH_X7 - } channel_t; - parameter channel_t CH_ALL[CH_X7+1] = '{CH_X1, CH_Y1, CH_Y2, CH_X2, CH_X3, CH_Y3, CH_X4, CH_X5, CH_X6, CH_X7}; - typedef enum { - TXN_0, - TXN_1, - TXN_2, - TXN_3, - TXN_4, - TXN_5, - TXN_6, - TXN_7 - } txn_type_t; - function txn_type_t txn_type(bit [2:0] opcode, channel_t ch); - case(opcode) - 3'd0: begin - case(ch) - CH_X1: txn_type = TXN_1; - CH_X2: txn_type = TXN_7; - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X4: txn_type = TXN_2; - CH_X6: txn_type = TXN_2; - default: txn_type = TXN_0; - endcase - end - 3'd1: begin - case(ch) - CH_Y1: txn_type = TXN_3; - CH_X2: txn_type = TXN_4; - CH_X3: txn_type = TXN_5; - CH_Y3: txn_type = TXN_5; - CH_X5: txn_type = TXN_6; - default: txn_type = TXN_0; - endcase - end - 3'd2: begin - case(ch) - CH_Y1: txn_type = TXN_7; - CH_X2: txn_type = TXN_7; - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X4: txn_type = TXN_7; - CH_X6: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - 3'd3: begin - case(ch) - CH_Y1: txn_type = TXN_7; - CH_X2: txn_type = TXN_7; - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X5: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - 3'd4: begin - case(ch) - CH_X1: txn_type = TXN_7; - CH_X2: txn_type = TXN_7; - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X4: txn_type = TXN_7; - CH_X6: txn_type = TXN_7; - CH_X7: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - 3'd5: begin - case(ch) - CH_Y1: txn_type = TXN_7; - CH_X2: txn_type = TXN_7; - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X5: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - 3'd6: begin - case(ch) - CH_X3: txn_type = TXN_7; - CH_Y3: txn_type = TXN_7; - CH_X5: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - 3'd7: begin - case(ch) - CH_Y2: txn_type = TXN_7; - default: txn_type = TXN_0; - endcase - end - endcase - endfunction + localparam int OPCODEW = 3; + localparam int CIDW = 4; + localparam int SIDW = 10; + localparam int CTAGW = 7; + localparam int STAGW = 9; + localparam int STATEW = 3; + localparam int ADDRW = 37; + localparam int DATAW = 256; + localparam int MASKW = DATAW / 8; + localparam int SIZEW = 4; + typedef enum logic [OPCODEW-1:0] { + A = 3'h0, + B = 3'h1 + } a_op_t; + typedef enum logic [OPCODEW-1:0] { + C = 3'h0, + D = 3'h1 + } b_op_t; + typedef enum logic [OPCODEW-1:0] { + E = 3'h0, + F = 3'h1 + } c_op_t; + typedef enum logic [OPCODEW-1:0] { + G = 3'h0, + H = 3'h1 + } d_op_t; + typedef logic [CIDW-1:0] cid_t; + typedef logic [SIDW-1:0] sid_t; + typedef logic [CTAGW-1:0] ctag_t; + typedef logic [STAGW-1:0] stag_t; + typedef logic [STATEW-1:0] state_t; + typedef logic [ADDRW-1:0] address_t; + typedef logic [SIZEW-1:0] size_t; + typedef logic [DATAW-1:0] data_t; + typedef logic [MASKW-1:0] mask_t; + typedef struct packed { + cid_t cid; + a_op_t opcode; + address_t address; + } x1_ch_t; + typedef struct packed { + cid_t cid; + b_op_t opcode; + address_t address; + } x2_ch_t; + typedef struct packed { + cid_t cid; + sid_t sid; + ctag_t ctag; + stag_t stag; + c_op_t opcode; + state_t state2; + state_t state3; + address_t address; + logic f4; + size_t size; + logic f2; + } x3_ch_t; + typedef struct packed { + cid_t cid; + sid_t sid; + ctag_t ctag; + stag_t stag; + d_op_t opcode; + state_t state1; + logic f4; + logic f1; + size_t size; + logic f3; + } x4_ch_t; + typedef struct packed { + cid_t cid; + ctag_t ctag; + stag_t stag; + d_op_t opcode; + logic f1; + logic f3; + } x5_ch_t; + typedef struct packed { + logic last; + logic corrupt; + } x6_ch_t; + typedef struct packed { + sid_t sid; + stag_t stag; + } x7_ch_t; + typedef enum { + CH_X1, + CH_Y1, + CH_Y2, + CH_X2, + CH_X3, + CH_Y3, + CH_X4, + CH_X5, + CH_X6, + CH_X7 + } channel_t; + parameter channel_t CH_ALL[CH_X7+1] = '{ + CH_X1, + CH_Y1, + CH_Y2, + CH_X2, + CH_X3, + CH_Y3, + CH_X4, + CH_X5, + CH_X6, + CH_X7 + }; + typedef enum { + TXN_0, + TXN_1, + TXN_2, + TXN_3, + TXN_4, + TXN_5, + TXN_6, + TXN_7 + } txn_type_t; + function txn_type_t txn_type(bit [2:0] opcode, channel_t ch); + case (opcode) + 3'd0: begin + case (ch) + CH_X1: txn_type = TXN_1; + CH_X2: txn_type = TXN_7; + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X4: txn_type = TXN_2; + CH_X6: txn_type = TXN_2; + default: txn_type = TXN_0; + endcase + end + 3'd1: begin + case (ch) + CH_Y1: txn_type = TXN_3; + CH_X2: txn_type = TXN_4; + CH_X3: txn_type = TXN_5; + CH_Y3: txn_type = TXN_5; + CH_X5: txn_type = TXN_6; + default: txn_type = TXN_0; + endcase + end + 3'd2: begin + case (ch) + CH_Y1: txn_type = TXN_7; + CH_X2: txn_type = TXN_7; + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X4: txn_type = TXN_7; + CH_X6: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + 3'd3: begin + case (ch) + CH_Y1: txn_type = TXN_7; + CH_X2: txn_type = TXN_7; + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X5: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + 3'd4: begin + case (ch) + CH_X1: txn_type = TXN_7; + CH_X2: txn_type = TXN_7; + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X4: txn_type = TXN_7; + CH_X6: txn_type = TXN_7; + CH_X7: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + 3'd5: begin + case (ch) + CH_Y1: txn_type = TXN_7; + CH_X2: txn_type = TXN_7; + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X5: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + 3'd6: begin + case (ch) + CH_X3: txn_type = TXN_7; + CH_Y3: txn_type = TXN_7; + CH_X5: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + 3'd7: begin + case (ch) + CH_Y2: txn_type = TXN_7; + default: txn_type = TXN_0; + endcase + end + endcase + endfunction endpackage interface z_if; - import z_pkg::*; - logic x1_valid; - x1_ch_t x1; - logic x2_valid; - x2_ch_t x2; - logic x3_valid; - x3_ch_t x3; - logic x4_valid; - x4_ch_t x4; - logic x5_valid; - x5_ch_t x5; - logic x6_valid; - x6_ch_t x6; - data_t x6_data; - logic x7_valid; - x7_ch_t x7; - function automatic logic x2_trig(); return x2_valid; endfunction - function automatic logic x4_trig(); return x4_valid; endfunction - function automatic logic x5_trig(); return x5_valid; endfunction - function automatic logic x6_trig(); return x6_valid; endfunction - modport sender ( - output x1_valid, - output x1, - input x2_valid, - input x2, - output x3_valid, - output x3, - input x4_valid, - input x4, - input x5_valid, - input x5, - input x6_valid, - input x6, - input x6_data, - output x7_valid, - output x7, - import x2_trig, - import x4_trig, - import x5_trig, - import x6_trig - ); - modport receiver ( - input x1_valid, - input x1, - output x2_valid, - output x2, - input x3_valid, - input x3, - output x4_valid, - output x4, - output x5_valid, - output x5, - output x6_valid, - output x6, - output x6_data, - input x7_valid, - input x7, - import x2_trig, - import x4_trig, - import x5_trig, - import x6_trig - ); + import z_pkg::*; + logic x1_valid; + x1_ch_t x1; + logic x2_valid; + x2_ch_t x2; + logic x3_valid; + x3_ch_t x3; + logic x4_valid; + x4_ch_t x4; + logic x5_valid; + x5_ch_t x5; + logic x6_valid; + x6_ch_t x6; + data_t x6_data; + logic x7_valid; + x7_ch_t x7; + function automatic logic x2_trig(); + return x2_valid; + endfunction + function automatic logic x4_trig(); + return x4_valid; + endfunction + function automatic logic x5_trig(); + return x5_valid; + endfunction + function automatic logic x6_trig(); + return x6_valid; + endfunction + modport sender( + output x1_valid, + output x1, + input x2_valid, + input x2, + output x3_valid, + output x3, + input x4_valid, + input x4, + input x5_valid, + input x5, + input x6_valid, + input x6, + input x6_data, + output x7_valid, + output x7, + import x2_trig, + import x4_trig, + import x5_trig, + import x6_trig + ); + modport receiver( + input x1_valid, + input x1, + output x2_valid, + output x2, + input x3_valid, + input x3, + output x4_valid, + output x4, + output x5_valid, + output x5, + output x6_valid, + output x6, + output x6_data, + input x7_valid, + input x7, + import x2_trig, + import x4_trig, + import x5_trig, + import x6_trig + ); endinterface class z_txn_class; - rand z_pkg::txn_type_t req_txn_type; - rand z_pkg::cid_t cid; - rand z_pkg::sid_t sid; - rand z_pkg::ctag_t ctag; - rand z_pkg::stag_t stag; - rand z_pkg::size_t size; - rand z_pkg::address_t address; - rand z_pkg::state_t state1; - rand z_pkg::state_t state2; - rand z_pkg::state_t state3; - rand logic f1; - rand logic f2; - rand logic f3; - rand logic f4; - z_pkg::data_t data[]; - z_pkg::mask_t mask[]; - bit corrupt[]; - logic [2:0] req_opcode; + rand z_pkg::txn_type_t req_txn_type; + rand z_pkg::cid_t cid; + rand z_pkg::sid_t sid; + rand z_pkg::ctag_t ctag; + rand z_pkg::stag_t stag; + rand z_pkg::size_t size; + rand z_pkg::address_t address; + rand z_pkg::state_t state1; + rand z_pkg::state_t state2; + rand z_pkg::state_t state3; + rand logic f1; + rand logic f2; + rand logic f3; + rand logic f4; + z_pkg::data_t data[]; + z_pkg::mask_t mask[]; + bit corrupt[]; + logic [2:0] req_opcode; endclass -module z_bfm_sender import z_pkg::*; - ( + +module z_bfm_sender + import z_pkg::*; +( input logic clk, input logic reset_l, z_if.sender z_if_sender - ); - channel_t ch; - typedef z_txn_class z_txn_q_t[$]; - z_txn_q_t z_txn_qs[ch.num()]; - z_txn_class z_txn[ch.num()]; - always @(posedge clk or negedge reset_l) begin - if (!reset_l) begin - z_if_sender.x1_valid <= '0; - z_if_sender.x3_valid <= '0; - z_if_sender.x7_valid <= '0; +); + channel_t ch; + typedef z_txn_class z_txn_q_t[$]; + z_txn_q_t z_txn_qs[ch.num()]; + z_txn_class z_txn[ch.num()]; + always @(posedge clk or negedge reset_l) begin + if (!reset_l) begin + z_if_sender.x1_valid <= '0; + z_if_sender.x3_valid <= '0; + z_if_sender.x7_valid <= '0; + end + else begin + foreach (CH_ALL[i]) begin + case (CH_ALL[i]) + CH_X1: begin + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x1_valid <= '1; + z_if_sender.x1.cid <= z_txn[i].cid; + z_if_sender.x1.opcode <= a_op_t'(z_txn[i].req_opcode); + z_if_sender.x1.address <= z_txn[i].address; + end + end + CH_X3: begin + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x3_valid <= '1; + z_if_sender.x3.cid <= z_txn[i].cid; + z_if_sender.x3.sid <= z_txn[i].sid; + z_if_sender.x3.ctag <= z_txn[i].ctag; + z_if_sender.x3.stag <= z_txn[i].stag; + z_if_sender.x3.opcode <= c_op_t'(z_txn[i].req_opcode); + z_if_sender.x3.state2 <= z_txn[i].state2; + z_if_sender.x3.state3 <= z_txn[i].state3; + z_if_sender.x3.address <= z_txn[i].address; + z_if_sender.x3.f4 <= z_txn[i].f4; + z_if_sender.x3.size <= z_txn[i].size; + z_if_sender.x3.f2 <= z_txn[i].f2; + end + end + CH_X7: begin + if (z_txn_qs[i].size() > 0) begin + z_txn[i] = z_txn_qs[i].pop_front(); + z_if_sender.x7.sid <= z_txn[i].sid; + z_if_sender.x7.stag <= z_txn[i].stag; + end + end + CH_X2: begin + if (z_if_sender.x2_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch); + z_txn[i].cid = z_if_sender.x2.cid; + z_txn[i].address = z_if_sender.x2.address; + z_txn_qs[i].push_back(z_txn[i]); + end + end + CH_X4: begin + if (z_if_sender.x4_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch); + z_txn[i].cid = z_if_sender.x4.cid; + z_txn[i].sid = z_if_sender.x4.sid; + z_txn[i].ctag = z_if_sender.x4.ctag; + z_txn[i].stag = z_if_sender.x4.stag; + z_txn[i].state1 = z_if_sender.x4.state1; + z_txn[i].f1 = z_if_sender.x4.f1; + z_txn[i].f4 = z_if_sender.x4.f4; + z_txn[i].size = z_if_sender.x4.size; + z_txn[i].f3 = z_if_sender.x4.f3; + z_txn_qs[i].push_back(z_txn[i]); + end + end + CH_X5: begin + if (z_if_sender.x5_trig()) begin + z_txn[i] = new; + z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch); + z_txn[i].cid = z_if_sender.x5.cid; + z_txn[i].ctag = z_if_sender.x5.ctag; + z_txn[i].f1 = z_if_sender.x5.f1; + z_txn_qs[i].push_back(z_txn[i]); + end + end + CH_X6: begin + if (z_if_sender.x6_trig()) begin + z_txn[i] = new; + z_txn[i].data = new[1]; + z_txn[i].corrupt = new[1]; + z_txn[i].data[0] = z_if_sender.x6_data; + z_txn[i].corrupt[0] = z_if_sender.x6.corrupt; + z_txn_qs[i].push_back(z_txn[i]); + end + end + endcase end - else begin - foreach (CH_ALL[i]) begin - case(CH_ALL[i]) - CH_X1: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x1_valid <= '1; - z_if_sender.x1.cid <= z_txn[i].cid; - z_if_sender.x1.opcode <= a_op_t'(z_txn[i].req_opcode); - z_if_sender.x1.address <= z_txn[i].address; - end - end - CH_X3: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x3_valid <= '1; - z_if_sender.x3.cid <= z_txn[i].cid; - z_if_sender.x3.sid <= z_txn[i].sid; - z_if_sender.x3.ctag <= z_txn[i].ctag; - z_if_sender.x3.stag <= z_txn[i].stag; - z_if_sender.x3.opcode <= c_op_t'(z_txn[i].req_opcode); - z_if_sender.x3.state2 <= z_txn[i].state2; - z_if_sender.x3.state3 <= z_txn[i].state3; - z_if_sender.x3.address <= z_txn[i].address; - z_if_sender.x3.f4 <= z_txn[i].f4; - z_if_sender.x3.size <= z_txn[i].size; - z_if_sender.x3.f2 <= z_txn[i].f2; - end - end - CH_X7: begin - if (z_txn_qs[i].size() > 0) begin - z_txn[i] = z_txn_qs[i].pop_front(); - z_if_sender.x7.sid <= z_txn[i].sid; - z_if_sender.x7.stag <= z_txn[i].stag; - end - end - CH_X2: begin - if (z_if_sender.x2_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch); - z_txn[i].cid = z_if_sender.x2.cid; - z_txn[i].address = z_if_sender.x2.address; - z_txn_qs[i].push_back(z_txn[i]); - end - end - CH_X4: begin - if (z_if_sender.x4_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch); - z_txn[i].cid = z_if_sender.x4.cid; - z_txn[i].sid = z_if_sender.x4.sid; - z_txn[i].ctag = z_if_sender.x4.ctag; - z_txn[i].stag = z_if_sender.x4.stag; - z_txn[i].state1 = z_if_sender.x4.state1; - z_txn[i].f1 = z_if_sender.x4.f1; - z_txn[i].f4 = z_if_sender.x4.f4; - z_txn[i].size = z_if_sender.x4.size; - z_txn[i].f3 = z_if_sender.x4.f3; - z_txn_qs[i].push_back(z_txn[i]); - end - end - CH_X5: begin - if (z_if_sender.x5_trig()) begin - z_txn[i] = new; - z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch); - z_txn[i].cid = z_if_sender.x5.cid; - z_txn[i].ctag = z_if_sender.x5.ctag; - z_txn[i].f1 = z_if_sender.x5.f1; - z_txn_qs[i].push_back(z_txn[i]); - end - end - CH_X6: begin - if (z_if_sender.x6_trig()) begin - z_txn[i] = new; - z_txn[i].data = new[1]; - z_txn[i].corrupt = new[1]; - z_txn[i].data[0] = z_if_sender.x6_data; - z_txn[i].corrupt[0] = z_if_sender.x6.corrupt; - z_txn_qs[i].push_back(z_txn[i]); - end - end - endcase - end - end - end + end + end endmodule -module test_core_wrapper - ( - input logic clk, - input logic reset_l, - z_if.sender z, - mmio_z - ); - z_bfm_sender mem_z_bfm( .z_if_sender(z), - .*); - z_bfm_sender mmio_z_bfm( .z_if_sender(mmio_z), - .*); +module test_core_wrapper ( + input logic clk, + input logic reset_l, + z_if.sender z, + mmio_z +); + z_bfm_sender mem_z_bfm ( + .z_if_sender(z), + .* + ); + z_bfm_sender mmio_z_bfm ( + .z_if_sender(mmio_z), + .* + ); endmodule -module t - ( - input clk, - input reset_l - ); - z_if z(), - mmio_z(); - test_core_wrapper tile( .z (z.sender), - .mmio_z(mmio_z.sender), - .*); +module t ( + input clk, + input reset_l +); + z_if z (), mmio_z (); + test_core_wrapper tile ( + .z(z.sender), + .mmio_z(mmio_z.sender), + .* + ); endmodule diff --git a/test_regress/t/t_queue_unpacked.v b/test_regress/t/t_queue_unpacked.v index 7004050b5..83200d7b1 100644 --- a/test_regress/t/t_queue_unpacked.v +++ b/test_regress/t/t_queue_unpacked.v @@ -4,68 +4,70 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef string sarray_t[2]; - typedef sarray_t q_sarray_t[$]; + typedef string sarray_t[2]; + typedef sarray_t q_sarray_t[$]; - typedef bit [95:0] wide_t; - typedef wide_t warray_t[2]; - typedef warray_t q_warray_t[$]; + typedef bit [95:0] wide_t; + typedef wide_t warray_t[2]; + typedef warray_t q_warray_t[$]; - initial begin - begin - q_sarray_t iq; - sarray_t a; - sarray_t b0; - sarray_t b1; + initial begin + begin + q_sarray_t iq; + sarray_t a; + sarray_t b0; + sarray_t b1; - a[0] = "hello"; - a[1] = "world"; - iq.push_back(a); - a[0] = "bye"; - a[1] = "world"; - iq.push_back(a); + a[0] = "hello"; + a[1] = "world"; + iq.push_back(a); + a[0] = "bye"; + a[1] = "world"; + iq.push_back(a); - b0 = iq[0]; - b1 = iq[1]; - `checks(b0[0], "hello"); - `checks(b0[1], "world"); - `checks(b1[0], "bye"); - `checks(b1[1], "world"); + b0 = iq[0]; + b1 = iq[1]; + `checks(b0[0], "hello"); + `checks(b0[1], "world"); + `checks(b1[0], "bye"); + `checks(b1[1], "world"); - iq[2][0] = "goodbye"; - iq[2][1] = "world"; - `checks(iq[2][0], "goodbye"); - `checks(iq[2][1], "world"); - end + iq[2][0] = "goodbye"; + iq[2][1] = "world"; + `checks(iq[2][0], "goodbye"); + `checks(iq[2][1], "world"); + end `ifndef verilator - // Need wide conversion into VlUnpacked types + // Need wide conversion into VlUnpacked types - // If we convert all arrays to VlUnpacked it works, so we need to track - // data types and insert conversions perhaps in V3Cast, but we currently - // don't know the output datatypes, so work needed. - begin - q_warray_t iq; - warray_t a; - warray_t b0; + // If we convert all arrays to VlUnpacked it works, so we need to track + // data types and insert conversions perhaps in V3Cast, but we currently + // don't know the output datatypes, so work needed. + begin + q_warray_t iq; + warray_t a; + warray_t b0; - a[0] = "abcdefg_ijkl"; - a[1] = "012123123128"; - iq.push_back(a); + a[0] = "abcdefg_ijkl"; + a[1] = "012123123128"; + iq.push_back(a); - b0 = iq[0]; - `checks(b0[0], "abcdefg_ijkl"); - `checks(b0[1], "012123123128"); - end + b0 = iq[0]; + `checks(b0[0], "abcdefg_ijkl"); + `checks(b0[1], "012123123128"); + end `endif - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_var_slice.v b/test_regress/t/t_queue_var_slice.v index 3e1501a39..277680016 100644 --- a/test_regress/t/t_queue_var_slice.v +++ b/test_regress/t/t_queue_var_slice.v @@ -4,22 +4,20 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer i = 0; - integer q[$] = {0, 1}; + integer i = 0; + integer q[$] = {0, 1}; - always @(posedge clk) begin - $display("%p", q[i:i+1]); - q.push_back(i+2); - i++; - if (i >= 3) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + $display("%p", q[i:i+1]); + q.push_back(i + 2); + i++; + if (i >= 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_queue_void_ops.v b/test_regress/t/t_queue_void_ops.v index 309862e28..b41eddae6 100644 --- a/test_regress/t/t_queue_void_ops.v +++ b/test_regress/t/t_queue_void_ops.v @@ -4,15 +4,11 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t - (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - int cyc = 0; + int cyc = 0; // Test for https://github.com/verilator/verilator/issues/3364 @@ -20,7 +16,7 @@ module t // compile-able C++ models for it. // simple queue - logic [31:0] my_int_queue [$]; + logic [31:0] my_int_queue[$]; // On the functions and tasks, the my_int_queue.pop_[front|back]() call will // have nodep->firstAbovep() != nullptr. Because the pop_front or pop_back is @@ -49,138 +45,138 @@ module t task automatic do_random_queue_operation(); bit [7:0] rand_op; - int rand_index; + int rand_index; logic [31:0] item; rand_op = 8'($urandom_range(32, 0)); - case(rand_op) - 8'd0: ; // nop + case (rand_op) + 8'd0: ; // nop - // pushes (2x of these) - 8'd1, 8'd2: my_int_queue.push_back($urandom); - 8'd3, 8'd4: my_int_queue.push_front($urandom); + // pushes (2x of these) + 8'd1, 8'd2: my_int_queue.push_back($urandom); + 8'd3, 8'd4: my_int_queue.push_front($urandom); - // delete: - 8'd5: my_int_queue.delete(); + // delete: + 8'd5: my_int_queue.delete(); - // insert(index, item): - 8'd6: begin - rand_index = $urandom_range(my_int_queue.size()); - my_int_queue.insert(rand_index, item); - end + // insert(index, item): + 8'd6: begin + rand_index = $urandom_range(my_int_queue.size()); + my_int_queue.insert(rand_index, item); + end - // shuffle - 8'd7: my_int_queue.shuffle(); + // shuffle + 8'd7: my_int_queue.shuffle(); - // Various pops for rand_op >= 8: - // pops to var - // V3Width debug -- firstAbovep()=ASSIGN (which I guess does the ; for us - // so we don't need the queue op to - // do it.) - // isStandalongStmt() will ignore ASSIGN, return false (NodeAssign is - // child of AstNodeStmt) - 8'd8: if (my_int_queue.size() > 0) item = my_int_queue.pop_front(); - 8'd9: if (my_int_queue.size() > 0) item = my_int_queue.pop_back(); + // Various pops for rand_op >= 8: + // pops to var + // V3Width debug -- firstAbovep()=ASSIGN (which I guess does the ; for us + // so we don't need the queue op to + // do it.) + // isStandalongStmt() will ignore ASSIGN, return false (NodeAssign is + // child of AstNodeStmt) + 8'd8: if (my_int_queue.size() > 0) item = my_int_queue.pop_front(); + 8'd9: if (my_int_queue.size() > 0) item = my_int_queue.pop_back(); - // pops to the void - // V3Width debug -- firstAbovep()=IF - // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True - 8'd10: if (my_int_queue.size() > 0) void'(my_int_queue.pop_front()); - 8'd11: if (my_int_queue.size() > 0) void'(my_int_queue.pop_back()); + // pops to the void + // V3Width debug -- firstAbovep()=IF + // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True + 8'd10: if (my_int_queue.size() > 0) void'(my_int_queue.pop_front()); + 8'd11: if (my_int_queue.size() > 0) void'(my_int_queue.pop_back()); - // pop result to the lhs of a condition, and do something with it. - 8'd12: + // pop result to the lhs of a condition, and do something with it. + 8'd12: if (my_int_queue.size() > 0) // V3Width debug -- firstAbovep()=LTE (good we don't want a ; here) if (my_int_queue.pop_front() <= 2022) - my_int_queue.push_front(3022); // living in the year 3022. + my_int_queue.push_front(3022); // living in the year 3022. - // pop result to the rhs of a condition, and do something with it. - 8'd13: + // pop result to the rhs of a condition, and do something with it. + 8'd13: if (my_int_queue.size() > 0) // V3Width debug -- firstAbovep()=GT (good we don't want a ; here) if (4022 > my_int_queue.pop_front()) - my_int_queue.push_front(3023); // living in the year 3023. + my_int_queue.push_front(3023); // living in the year 3023. - // pops to the void after yet another case: - // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) - // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True - 8'd14: + // pops to the void after yet another case: + // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) + // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True + 8'd14: case (my_int_queue.size() > 0) - 0: ; - 1: void'(my_int_queue.pop_front()); - default: ; - endcase // case (my_int_queue.size() > 0) + 0: ; + 1: void'(my_int_queue.pop_front()); + default: ; + endcase // case (my_int_queue.size() > 0) - // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) - // backp()->nextp()=CASEITEM (different one) - // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True - 8'd15: + // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) + // backp()->nextp()=CASEITEM (different one) + // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True + 8'd15: case (my_int_queue.size() > 0) - 0: ; - 1: void'(my_int_queue.pop_back()); - default; - endcase // case (my_int_queue.size() > 0) + 0: ; + 1: void'(my_int_queue.pop_back()); + default; + endcase // case (my_int_queue.size() > 0) - // pops in a function or task - 8'd16: if (my_int_queue.size() > 0) f_pop_back__my_int_queue(); - 8'd17: if (my_int_queue.size() > 0) f_pop_front__my_int_queue(); - 8'd18: if (my_int_queue.size() > 0) t_pop_back__my_int_queue(); - 8'd19: if (my_int_queue.size() > 0) t_pop_front__my_int_queue(); + // pops in a function or task + 8'd16: if (my_int_queue.size() > 0) f_pop_back__my_int_queue(); + 8'd17: if (my_int_queue.size() > 0) f_pop_front__my_int_queue(); + 8'd18: if (my_int_queue.size() > 0) t_pop_back__my_int_queue(); + 8'd19: if (my_int_queue.size() > 0) t_pop_front__my_int_queue(); - // But what if we put some dummy code before the pop_back() or pop_front(): - 8'd20: begin - if (my_int_queue.size() > 0) begin - ; // dummy line - // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). - // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True - void'(my_int_queue.pop_back()); + // But what if we put some dummy code before the pop_back() or pop_front(): + 8'd20: begin + if (my_int_queue.size() > 0) begin + ; // dummy line + // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). + // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True + void'(my_int_queue.pop_back()); + end end - end - 8'd21: begin - automatic int temp_int = 0; - if (my_int_queue.size() > 0) begin - temp_int = 5; // dummy line - // V3Width debug -- firstAbovep()=nullptr (good) - void'(my_int_queue.pop_back()); + 8'd21: begin + automatic int temp_int = 0; + if (my_int_queue.size() > 0) begin + temp_int = 5; // dummy line + // V3Width debug -- firstAbovep()=nullptr (good) + void'(my_int_queue.pop_back()); + end end - end - 8'd22: begin - if (my_int_queue.size() > 0) begin - automatic int some_temp_dummy_int; - some_temp_dummy_int = 42; - // V3Width debug -- firstAbovep()=nullptr (good) - void'(my_int_queue.pop_back()); + 8'd22: begin + if (my_int_queue.size() > 0) begin + automatic int some_temp_dummy_int; + some_temp_dummy_int = 42; + // V3Width debug -- firstAbovep()=nullptr (good) + void'(my_int_queue.pop_back()); + end end - end - 8'd23: begin - if (my_int_queue.size() > 0) begin - // no dummy here, just a 'begin' helper before it. - // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). - // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True - void'(my_int_queue.pop_back()); + 8'd23: begin + if (my_int_queue.size() > 0) begin + // no dummy here, just a 'begin' helper before it. + // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). + // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True + void'(my_int_queue.pop_back()); + end end - end - // What about an if of something else, followed by a pop_front? - 8'd24: begin - automatic int temp_int = 0; - if (my_int_queue.size() == 0) begin // dummy - temp_int = 1000; + // What about an if of something else, followed by a pop_front? + 8'd24: begin + automatic int temp_int = 0; + if (my_int_queue.size() == 0) begin // dummy + temp_int = 1000; + end + void'(my_int_queue.pop_front()); // firstAbovep() should be nullptr here. end - void'(my_int_queue.pop_front()); // firstAbovep() should be nullptr here. - end - default: ; // nop - endcase // case (rand_op) + default: ; // nop + endcase // case (rand_op) endtask : do_random_queue_operation - always @ (posedge clk) begin : main + always @(posedge clk) begin : main cyc <= cyc + 1; do_random_queue_operation(); diff --git a/test_regress/t/t_semaphore_class.v b/test_regress/t/t_semaphore_class.v index c07e58476..df9216c98 100644 --- a/test_regress/t/t_semaphore_class.v +++ b/test_regress/t/t_semaphore_class.v @@ -5,27 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; - // Test an implementation similar to what Verilator will do internally - int m_keys; - function new(int keyCount = 0); - m_keys = keyCount; - endfunction - function void put(int keyCount = 1); - m_keys += keyCount; - endfunction - task get(int keyCount = 1); - wait (m_keys >= keyCount); + // Test an implementation similar to what Verilator will do internally + int m_keys; + function new(int keyCount = 0); + m_keys = keyCount; + endfunction + function void put(int keyCount = 1); + m_keys += keyCount; + endfunction + task get(int keyCount = 1); + wait (m_keys >= keyCount); + m_keys -= keyCount; + endtask + function int try_get(int keyCount = 1); + if (m_keys >= keyCount) begin m_keys -= keyCount; - endtask - function int try_get(int keyCount = 1); - if (m_keys >= keyCount) begin - m_keys -= keyCount; - return 1; - end - else begin - return 0; - end - endfunction + return 1; + end + else begin + return 0; + end + endfunction endclass `define SEMAPHORE_T semaphore_cls diff --git a/test_regress/t/t_semaphore_class_nested.v b/test_regress/t/t_semaphore_class_nested.v index 2e2c0d86a..a93eb76d9 100644 --- a/test_regress/t/t_semaphore_class_nested.v +++ b/test_regress/t/t_semaphore_class_nested.v @@ -5,33 +5,33 @@ // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; - class InnerKeyClass; - int innerKeys; - function new(int keyCount = 0); - innerKeys = keyCount; - endfunction - endclass - // Test an implementation similar to what Verilator will do internally - InnerKeyClass m_keys; - function new(int keyCount = 0); - m_keys = new(keyCount); - endfunction - function void put(int keyCount = 1); - m_keys.innerKeys += keyCount; - endfunction - task get(int keyCount = 1); - wait (m_keys.innerKeys >= keyCount); + class InnerKeyClass; + int innerKeys; + function new(int keyCount = 0); + innerKeys = keyCount; + endfunction + endclass + // Test an implementation similar to what Verilator will do internally + InnerKeyClass m_keys; + function new(int keyCount = 0); + m_keys = new(keyCount); + endfunction + function void put(int keyCount = 1); + m_keys.innerKeys += keyCount; + endfunction + task get(int keyCount = 1); + wait (m_keys.innerKeys >= keyCount); + m_keys.innerKeys -= keyCount; + endtask + function int try_get(int keyCount = 1); + if (m_keys.innerKeys >= keyCount) begin m_keys.innerKeys -= keyCount; - endtask - function int try_get(int keyCount = 1); - if (m_keys.innerKeys >= keyCount) begin - m_keys.innerKeys -= keyCount; - return 1; - end - else begin - return 0; - end - endfunction + return 1; + end + else begin + return 0; + end + endfunction endclass `define SEMAPHORE_T semaphore_cls diff --git a/test_regress/t/t_timing_finish.v b/test_regress/t/t_timing_finish.v index 19811bc28..0e96bf2ba 100644 --- a/test_regress/t/t_timing_finish.v +++ b/test_regress/t/t_timing_finish.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 program t; - initial begin - $write("*-* All Finished *-*\n"); - // No $finish - end + initial begin + $write("*-* All Finished *-*\n"); + // No $finish + end endprogram diff --git a/test_regress/t/t_typedef.v b/test_regress/t/t_typedef.v index 59384da9d..5ab52a6e7 100644 --- a/test_regress/t/t_typedef.v +++ b/test_regress/t/t_typedef.v @@ -5,70 +5,72 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef bit pkg_bit_t; + typedef bit pkg_bit_t; endpackage program t; - parameter SIZE = 5; + parameter SIZE = 5; - typedef vec_t; // Forward - typedef vec_t; // Multi-forward is ok + typedef vec_t; // Forward + typedef vec_t; // Multi-forward is ok - typedef reg [SIZE-1:0] vec_t; - vec_t a; initial a =0; + typedef reg [SIZE-1:0] vec_t; + vec_t a; + initial a = 0; - typedef bit [SIZE-1:0] vec_bit_t; - vec_bit_t b; initial b =0; + typedef bit [SIZE-1:0] vec_bit_t; + vec_bit_t b; + initial b = 0; - typedef int array_t [3]; - typedef array_t array2_t [2]; - array2_t ar [1]; + typedef int array_t[3]; + typedef array_t array2_t[2]; + array2_t ar[1]; - typedef pkg::pkg_bit_t lcl_pkg_bit_t; + typedef pkg::pkg_bit_t lcl_pkg_bit_t; - // Define before use - // Not sure how well supported this is elsewhere - //UNSUP typedef preuse; - //UNSUP preuse p; - //UNSUP typedef int preuse; + // Define before use + // Not sure how well supported this is elsewhere + //UNSUP typedef preuse; + //UNSUP preuse p; + //UNSUP typedef int preuse; -//reg [SIZE-1:0] a; initial a =0; -//reg [SIZE-1:0] b; initial b =0; + //reg [SIZE-1:0] a; initial a =0; + //reg [SIZE-1:0] b; initial b =0; - initial begin - typedef logic [3:0][7:0] instr_mem_t; - instr_mem_t a; - a[0] = 8'h12; - if (a[0] != 8'h12) $stop; - end + initial begin + typedef logic [3:0][7:0] instr_mem_t; + instr_mem_t a; + a[0] = 8'h12; + if (a[0] != 8'h12) $stop; + end - integer j; - initial begin - for (j=0;j<=(1<