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verilator
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Apply 'make format'

This commit is contained in:
github action 2025-11-20 11:39:49 +00:00
parent a4e901135b
commit 0703159dbc
2 changed files with 5 additions and 5 deletions
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7
src/V3LinkCells.cpp
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@ -125,8 +125,7 @@ class LinkConfigsVisitor final : public VNVisitor {
} }
void visit(AstConfigRule* nodep) override { void visit(AstConfigRule* nodep) override {
if (!nodep->cellp()) { if (!nodep->cellp()) {
for (AstNode* usep = nodep->usep(); usep; for (AstNode* usep = nodep->usep(); usep; usep = usep->nextp()) {
usep = usep->nextp()) {
m_state.m_liblist.push_back(usep->name()); m_state.m_liblist.push_back(usep->name());
} }
} else { } else {
@ -210,8 +209,8 @@ class LinkCellsVisitor final : public VNVisitor {
// First search IEEE config library list // First search IEEE config library list
AstNodeModule* foundp; AstNodeModule* foundp;
for (auto const& l : m_state.m_liblist) { for (auto const& l : m_state.m_liblist) {
foundp = findModuleLibSym(modName, l); foundp = findModuleLibSym(modName, l);
if (foundp) return foundp; if (foundp) return foundp;
} }
// Then search local library // Then search local library
foundp = findModuleLibSym(modName, libname); foundp = findModuleLibSym(modName, libname);

3
test_regress/t/t_config_default.py
View File

@ -12,7 +12,8 @@ import vltest_bootstrap
test.scenarios('simulator') test.scenarios('simulator')
test.compile(verilator_flags2=[ test.compile(verilator_flags2=[
'--binary', '--top cfg1', '--work liba', 't/t_config_work__liba.v', '--work libb', 't/t_config_work__libb.v' '--binary', '--top cfg1', '--work liba', 't/t_config_work__liba.v', '--work libb',
't/t_config_work__libb.v'
]) ])
test.execute() test.execute()