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Tests: Reindent some tests. No functional change.

This commit is contained in:
Wilson Snyder 2025-11-12 19:40:59 -05:00
parent 59bc4cf66b
commit 03e5c3b2ff
16 changed files with 320 additions and 327 deletions
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80
test_regress/t/t_time.v
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@ -14,51 +14,51 @@
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (); module t;
timeunit 10ns; timeunit 10ns;
timeprecision 1ns; timeprecision 1ns;
longint should_be_2, should_be_3; longint should_be_2, should_be_3;
real should_be_1p6, should_be_3p2; real should_be_1p6, should_be_3p2;
initial begin : initial_blk1 initial begin : initial_blk1
should_be_2 = 0; should_be_2 = 0;
should_be_3 = 0; should_be_3 = 0;
#(16ns); #(16ns);
$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime()); $display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
should_be_2 = $time(); should_be_2 = $time();
should_be_1p6 = $realtime(); should_be_1p6 = $realtime();
#(16ns); #(16ns);
$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime()); $display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
should_be_3 = $time(); should_be_3 = $time();
should_be_3p2 = $realtime(); should_be_3p2 = $realtime();
#(16ns); #(16ns);
$finish(1); $finish(1);
end
initial begin : initial_blk2
#(100ns);
$display("%%Error: We should not get here");
$stop;
end end
function bit real_chk(input real tvar, input real evar); initial begin : initial_blk2
real diff; #(100ns);
diff = tvar - evar; $display("%%Error: We should not get here");
return (diff < 1e-9) && (diff > -1e-9); $stop;
endfunction end
final begin : last_blk function bit real_chk(input real tvar, input real evar);
$display("Info: should_be_2 = %0d", should_be_2); real diff;
$display("Info: should_be_3 = %0d", should_be_3); diff = tvar - evar;
`checkd(should_be_2, 2); return (diff < 1e-9) && (diff > -1e-9);
`checkd(should_be_3, 3); endfunction
chk_2 : assert(should_be_2 == 2); final begin : last_blk
chk_3 : assert(should_be_3 == 3); $display("Info: should_be_2 = %0d", should_be_2);
chk_1p6 : assert(real_chk(should_be_1p6, 1.6)); $display("Info: should_be_3 = %0d", should_be_3);
chk_3p2 : assert(real_chk(should_be_3p2, 3.2)); `checkd(should_be_2, 2);
$write("*-* All Finished *-*\n"); `checkd(should_be_3, 3);
end
chk_2 : assert(should_be_2 == 2);
chk_3 : assert(should_be_3 == 3);
chk_1p6 : assert(real_chk(should_be_1p6, 1.6));
chk_3p2 : assert(real_chk(should_be_3p2, 3.2));
$write("*-* All Finished *-*\n");
end
endmodule endmodule

34
test_regress/t/t_time_literals.v
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@ -10,24 +10,24 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module t; module t;
time t; time t;
// realtime value scaled to timeunit, rounded to timeprecision // realtime value scaled to timeunit, rounded to timeprecision
initial begin initial begin
// verilator lint_off REALCVT // verilator lint_off REALCVT
t = 1s; `checkd(t, 64'd1000000000); t = 1s; `checkd(t, 64'd1000000000);
t = 2ms; `checkd(t, 2000000); t = 2ms; `checkd(t, 2000000);
t = 1ms; `checkd(t, 1000000); t = 1ms; `checkd(t, 1000000);
t = 1us; `checkd(t, 1000); t = 1us; `checkd(t, 1000);
t = 1ns; `checkd(t, 1); t = 1ns; `checkd(t, 1);
t = 1ps; `checkd(t, 0); // Below precision t = 1ps; `checkd(t, 0); // Below precision
t = 1fs; `checkd(t, 0); t = 1fs; `checkd(t, 0);
t = 2.3ps; `checkd(t, 0); t = 2.3ps; `checkd(t, 0);
t = 2.4us; `checkd(t, 2400); t = 2.4us; `checkd(t, 2400);
// verilator lint_on REALCVT // verilator lint_on REALCVT
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

44
test_regress/t/t_time_param.v
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@ -4,36 +4,34 @@
// any use, without warranty, 2025 by Wilson Snyder. // any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ps `timescale 1ns / 1ps
module vip_snitch_cluster module vip_snitch_cluster #(
#(parameter realtime ClkPeriod = 10ns) parameter realtime ClkPeriod = 10ns
(output logic clk_o); ) (
output logic clk_o
);
initial begin initial begin
forever begin forever begin
clk_o = 1; clk_o = 1;
#(ClkPeriod/2); #(ClkPeriod / 2);
clk_o = 0; clk_o = 0;
#(ClkPeriod/2); #(ClkPeriod / 2);
end end
end end
initial begin initial begin
#(ClkPeriod*100); #(ClkPeriod * 100);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule
module t; module t;
logic clk; logic clk;
vip_snitch_cluster #( vip_snitch_cluster #(.ClkPeriod(1ns)) vip (.clk_o(clk));
.ClkPeriod(1ns)
) vip (
.clk_o(clk)
);
endmodule endmodule

90
test_regress/t/t_time_passed.v
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@ -4,61 +4,63 @@
// any use, without warranty, 2020 by Wilson Snyder. // any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ps `timescale 1ns / 1ps
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk clk
); );
input clk; input clk;
integer cyc = 0; integer cyc = 0;
time in; time in;
// verilator lint_off REALCVT // verilator lint_off REALCVT
initial in = 5432109876.543210ns; // Will round to time units initial in = 5432109876.543210ns; // Will round to time units
// verilator lint_on REALCVT // verilator lint_on REALCVT
// This shows time changes when passed between modules with different units // This shows time changes when passed between modules with different units
// See also discussion in uvm_tlm2_time.svh // See also discussion in uvm_tlm2_time.svh
ps ps (.*); ps ps (.*);
ns ns (.*); ns ns (.*);
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc == 60) begin if (cyc == 60) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end end
endmodule endmodule
`timescale 1ps/1ps `timescale 1ps / 1ps
module ps module ps (
(input clk, input clk,
input integer cyc, input integer cyc,
input time in); input time in
);
always @ (posedge clk) begin always @(posedge clk) begin
if (cyc == 10) begin if (cyc == 10) begin
$timeformat(-9, 6, "ns", 16); $timeformat(-9, 6, "ns", 16);
$write("%m: Input time %t %d\n", in, in); $write("%m: Input time %t %d\n", in, in);
end end
end end
endmodule endmodule
`timescale 1ns/1ps `timescale 1ns / 1ps
module ns module ns (
(input clk, input clk,
input integer cyc, input integer cyc,
input time in); input time in
);
always @ (posedge clk) begin always @(posedge clk) begin
if (cyc == 20) begin if (cyc == 20) begin
$timeformat(-9, 6, "ns", 16); $timeformat(-9, 6, "ns", 16);
$write("%m: Input time %t %d\n", in, in); $write("%m: Input time %t %d\n", in, in);
end end
end end
endmodule endmodule

49
test_regress/t/t_time_print.v
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@ -6,34 +6,33 @@
module t; module t;
timeunit 1ns; timeunit 1ns; timeprecision 1ps;
timeprecision 1ps;
time t; time t;
initial begin initial begin
t = 10ns; t = 10ns;
$write("[%0t] In %m: Hi\n", $time); $write("[%0t] In %m: Hi\n", $time);
$printtimescale; $printtimescale;
$printtimescale(); $printtimescale();
$printtimescale(t); $printtimescale(t);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-3, 0, "-my-ms", 8); $timeformat(-3, 0, "-my-ms", 8);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-3, 1, "-my-ms", 10); $timeformat(-3, 1, "-my-ms", 10);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-6, 2, "-my-us", 12); $timeformat(-6, 2, "-my-us", 12);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-9, 3, "-my-ns", 13); $timeformat(-9, 3, "-my-ns", 13);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-12, 3, "-my-ps", 13); $timeformat(-12, 3, "-my-ps", 13);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-15, 4, "-my-fs", 14); $timeformat(-15, 4, "-my-fs", 14);
$write("Time: '%t' 10ns=%0t\n", $time, t); $write("Time: '%t' 10ns=%0t\n", $time, t);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

36
test_regress/t/t_time_sc.v
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@ -4,28 +4,26 @@
// any use, without warranty, 2020 by Wilson Snyder. // any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
time texpect = `TEST_EXPECT; time texpect = `TEST_EXPECT;
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc == 1) begin if (cyc == 1) begin
$printtimescale; $printtimescale;
$write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect); $write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect);
if ($time != texpect) begin if ($time != texpect) begin
$write("[%0t] delta = %d\n", $time, $time - texpect); $write("[%0t] delta = %d\n", $time, $time - texpect);
$stop; $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end end
$write("*-* All Finished *-*\n");
$finish;
end
end end
endmodule endmodule

28
test_regress/t/t_time_stamp64.v
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@ -4,22 +4,20 @@
// any use, without warranty, 2020 by Wilson Snyder. // any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc == 1) begin if (cyc == 1) begin
$write("[%0t] In %m: Hi\n", $time); $write("[%0t] In %m: Hi\n", $time);
$printtimescale; $printtimescale;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end
end
endmodule endmodule

25
test_regress/t/t_time_timeunit.v
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@ -4,24 +4,25 @@
// any use, without warranty, 2022 by Wilson Snyder. // any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;
timeunit 1ns; timeunit 1ns; timeprecision 1ps;
timeprecision 1ps;
initial begin initial begin
`checkd($timeunit, -9); `checkd($timeunit, -9);
`checkd($timeunit(), -9); `checkd($timeunit(), -9);
`checkd($timeunit(t), -9); `checkd($timeunit(t), -9);
`checkd($timeprecision, -12); `checkd($timeprecision, -12);
`checkd($timeprecision(), -12); `checkd($timeprecision(), -12);
`checkd($timeprecision(t), -12); `checkd($timeprecision(t), -12);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

72
test_regress/t/t_time_vpi.v
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@ -8,46 +8,44 @@
import "DPI-C" function void dpii_check(); import "DPI-C" function void dpii_check();
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
// verilator lint_off REALCVT // verilator lint_off REALCVT
time digits = 5432109876.543210ns; // Will round to time units time digits = 5432109876.543210ns; // Will round to time units
realtime rdigits = 5432109876.543210ns; // Will round to time precision realtime rdigits = 5432109876.543210ns; // Will round to time precision
time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double
// verilator lint_on REALCVT // verilator lint_on REALCVT
always @ (posedge clk) begin always @ (posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write("- [%0t] tick\n", $time); $write("- [%0t] tick\n", $time);
`endif `endif
if ($time >= 60) begin if ($time >= 60) begin
$write(":: In %m\n"); $write(":: In %m\n");
$printtimescale; $printtimescale;
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$timeformat(-9, 6, "ns", 16); $timeformat(-9, 6, "ns", 16);
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n", $write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
$time, $stime, $stime, $stime); $time, $stime, $stime, $stime);
// verilator lint_off REALCVT // verilator lint_off REALCVT
$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n", $write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
$time, $realtime, $realtime, $realtime); $time, $realtime, $realtime, $realtime);
// verilator lint_on REALCVT // verilator lint_on REALCVT
dpii_check(); dpii_check();
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end
end
endmodule endmodule

12
test_regress/t/t_timescale_default.v
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@ -6,10 +6,10 @@
// Intentionally no timescale here, nor in driver file // Intentionally no timescale here, nor in driver file
module t; module t;
initial begin initial begin
// Unspecified, but general consensus is 1s is default timeunit // Unspecified, but general consensus is 1s is default timeunit
$printtimescale; $printtimescale;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

6
test_regress/t/t_timescale_lint.v
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@ -7,11 +7,11 @@
module pre_no_ts; module pre_no_ts;
endmodule endmodule
`timescale 1ns/1ns `timescale 1ns / 1ns
module t; module t;
pre_no_ts pre_no_ts(); pre_no_ts pre_no_ts ();
post_no_ts pst_no_ts(); post_no_ts pst_no_ts ();
endmodule endmodule
module post_no_ts; module post_no_ts;

98
test_regress/t/t_timescale_parse.v
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@ -51,61 +51,61 @@ endmodule
module r0; module r0;
timeunit 10ns / 1ns; timeunit 10ns / 1ns;
task check; $write("%m %0t\n", $time); endtask task check; $write("%m %0t\n", $time); endtask
endmodule endmodule
module r1; module r1;
timeunit 10ns; timeunit 10ns;
timeprecision 1ns; timeprecision 1ns;
task check; $write("%m %0t\n", $time); endtask task check; $write("%m %0t\n", $time); endtask
endmodule endmodule
module t; module t;
sp2 sp2(); sp2 sp2();
sp1 sp1(); sp1 sp1();
sp0 sp0(); sp0 sp0();
sm1 sm1(); sm1 sm1();
sm2 sm2(); sm2 sm2();
sm3 sm3(); sm3 sm3();
sm4 sm4(); sm4 sm4();
sm5 sm5(); sm5 sm5();
sm6 sm6(); sm6 sm6();
sm7 sm7(); sm7 sm7();
sm8 sm8(); sm8 sm8();
sm9 sm9(); sm9 sm9();
sm10 sm10(); sm10 sm10();
sm11 sm11(); sm11 sm11();
sm12 sm12(); sm12 sm12();
sm13 sm13(); sm13 sm13();
sm14 sm14(); sm14 sm14();
sm15 sm15(); sm15 sm15();
r0 r0(); r0 r0();
r1 r1(); r1 r1();
final begin final begin
sp2.check(); sp2.check();
sp1.check(); sp1.check();
sp0.check(); sp0.check();
sm1.check(); sm1.check();
sm2.check(); sm2.check();
sm3.check(); sm3.check();
sm4.check(); sm4.check();
sm5.check(); sm5.check();
sm6.check(); sm6.check();
sm7.check(); sm7.check();
sm8.check(); sm8.check();
sm9.check(); sm9.check();
sm10.check(); sm10.check();
sm11.check(); sm11.check();
sm12.check(); sm12.check();
sm13.check(); sm13.check();
sm14.check(); sm14.check();
sm15.check(); sm15.check();
r0.check(); r0.check();
r1.check(); r1.check();
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

12
test_regress/t/t_timescale_parse_bad.out
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@ -17,10 +17,10 @@
%Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra' %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra'
15 | `timescale 1ns / 1ps /extra 15 | `timescale 1ns / 1ps /extra
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value %Error: t/t_timescale_parse_bad.v:18:12: timeunit illegal value
18 | timeunit 2ps; 18 | timeunit 2ps;
| ^~~ | ^~~
%Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value %Error: t/t_timescale_parse_bad.v:19:17: timeprecision illegal value
19 | timeprecision 2ps; 19 | timeprecision 2ps;
| ^~~ | ^~~
%Error: Exiting due to %Error: Exiting due to

4
test_regress/t/t_timescale_parse_bad.v
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@ -15,6 +15,6 @@
`timescale 1ns / 1ps /extra `timescale 1ns / 1ps /extra
module t; module t;
timeunit 2ps; // Bad timeunit 2ps; // Bad
timeprecision 2ps; // Bad timeprecision 2ps; // Bad
endmodule endmodule

28
test_regress/t/t_timescale_udp.v
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@ -6,18 +6,18 @@
`timescale 1ns/1ns `timescale 1ns/1ns
module t; module t;
p p (); p p ();
// Also check not-found modules // Also check not-found modules
localparam NOT = 0; localparam NOT = 0;
if (NOT) begin if (NOT) begin
NotFound not_found(.*); NotFound not_found(.*);
end end
initial begin initial begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule
@ -34,10 +34,10 @@ input in;
reg out; reg out;
table table
0 : 1; 0 : 1;
1 : 0; 1 : 0;
? : ?; ? : ?;
x : x; x : x;
endtable endtable
endprimitive endprimitive
`endcelldefine `endcelldefine

29
test_regress/t/t_timescale_unit.v
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@ -4,27 +4,26 @@
// any use, without warranty, 2021 by Wilson Snyder. // any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
timeunit 10ps; timeunit 10ps; timeprecision 10ps;
timeprecision 10ps;
task show; task show;
$printtimescale; $printtimescale;
endtask endtask
module from_unit; module from_unit;
task show; task show;
$printtimescale; $printtimescale;
endtask endtask
endmodule endmodule
module t; module t;
from_unit from_unit(); from_unit from_unit ();
timeunit 100ps; timeunit 100ps;
initial begin initial begin
show(); show();
from_unit.show(); from_unit.show();
$printtimescale; $printtimescale;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule