Tests: Reindent some tests. No functional change.

test_regress/t/t_time.v

@@ -14,7 +14,7 @@
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 
-module t ();
+module t;
   timeunit 10ns;
   timeprecision 1ns;
 

test_regress/t/t_time_param.v

@@ -4,23 +4,25 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
 
-module vip_snitch_cluster
+module vip_snitch_cluster #(
-  #(parameter realtime ClkPeriod = 10ns)
+    parameter realtime ClkPeriod = 10ns
-  (output logic clk_o);
+) (
+    output logic clk_o
+);
 
   initial begin
     forever begin
       clk_o = 1;
-         #(ClkPeriod/2);
+      #(ClkPeriod / 2);
       clk_o = 0;
-         #(ClkPeriod/2);
+      #(ClkPeriod / 2);
     end
   end
 
   initial begin
-      #(ClkPeriod*100);
+    #(ClkPeriod * 100);
     $write("*-* All Finished *-*\n");
     $finish;
   end
@@ -30,10 +32,6 @@ endmodule
 module t;
   logic clk;
 
-    vip_snitch_cluster #(
+  vip_snitch_cluster #(.ClkPeriod(1ns)) vip (.clk_o(clk));
-        .ClkPeriod(1ns)
-    ) vip (
-        .clk_o(clk)
-    );
 
 endmodule

test_regress/t/t_time_passed.v

@@ -4,8 +4,8 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
-module t (/*AUTOARG*/
+module t (  /*AUTOARG*/
   // Inputs
   clk
   );
@@ -24,7 +24,7 @@ module t (/*AUTOARG*/
   ps ps (.*);
   ns ns (.*);
 
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
     cyc <= cyc + 1;
     if (cyc == 60) begin
       $write("*-* All Finished *-*\n");
@@ -33,14 +33,15 @@ module t (/*AUTOARG*/
   end
 endmodule
 
-`timescale 1ps/1ps
+`timescale 1ps / 1ps
 
-module ps
+module ps (
-  (input clk,
+    input clk,
     input integer cyc,
-   input time in);
+    input time in
+);
 
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
     if (cyc == 10) begin
       $timeformat(-9, 6, "ns", 16);
       $write("%m: Input time %t %d\n", in, in);
@@ -48,14 +49,15 @@ module ps
   end
 endmodule
 
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
 
-module ns
+module ns (
-  (input clk,
+    input clk,
     input integer cyc,
-   input time in);
+    input time in
+);
 
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
     if (cyc == 20) begin
       $timeformat(-9, 6, "ns", 16);
       $write("%m: Input time %t %d\n", in, in);

test_regress/t/t_time_print.v

@@ -6,8 +6,7 @@
 
 module t;
 
-   timeunit 1ns;
+  timeunit 1ns; timeprecision 1ps;
-   timeprecision 1ps;
 
   time t;
 

test_regress/t/t_time_sc.v

@@ -4,17 +4,15 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
+);
-   );
-   input clk;
 
   integer cyc = 0;
 
   time texpect = `TEST_EXPECT;
 
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
     cyc <= cyc + 1;
     if (cyc == 1) begin
       $printtimescale;

test_regress/t/t_time_stamp64.v

@@ -4,15 +4,13 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
+);
-   );
-   input clk;
 
   integer cyc = 0;
 
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
     cyc <= cyc + 1;
     if (cyc == 1) begin
       $write("[%0t] In %m: Hi\n", $time);
@@ -20,6 +18,6 @@ module t (/*AUTOARG*/
       $write("*-* All Finished *-*\n");
       $finish;
     end
-
   end
+
 endmodule

test_regress/t/t_time_timeunit.v

@@ -4,13 +4,14 @@
 // any use, without warranty, 2022 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 
-   timeunit 1ns;
+  timeunit 1ns; timeprecision 1ps;
-   timeprecision 1ps;
 
   initial begin
     `checkd($timeunit, -9);

test_regress/t/t_time_vpi.v

@@ -8,11 +8,9 @@
 
 import "DPI-C" function void dpii_check();
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+  input clk
-   clk
   );
-   input clk;
 
   integer cyc = 0;
   // verilator lint_off REALCVT
@@ -48,6 +46,6 @@ module t (/*AUTOARG*/
       $write("*-* All Finished *-*\n");
       $finish;
     end
-
   end
+
 endmodule

test_regress/t/t_timescale_lint.v

@@ -7,11 +7,11 @@
 module pre_no_ts;
 endmodule
 
-`timescale 1ns/1ns
+`timescale 1ns / 1ns
 
 module t;
-   pre_no_ts pre_no_ts();
+  pre_no_ts pre_no_ts ();
-   post_no_ts pst_no_ts();
+  post_no_ts pst_no_ts ();
 endmodule
 
 module post_no_ts;

test_regress/t/t_timescale_parse_bad.out

@@ -17,10 +17,10 @@
 %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra'
    15 | `timescale 1ns / 1ps /extra
       | ^~~~~~~~~~~~~~~~~~~~~~~~~~~
-%Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value
+%Error: t/t_timescale_parse_bad.v:18:12: timeunit illegal value
    18 |   timeunit 2ps;   
       |            ^~~
-%Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value
+%Error: t/t_timescale_parse_bad.v:19:17: timeprecision illegal value
    19 |   timeprecision 2ps;    
       |                 ^~~
 %Error: Exiting due to

test_regress/t/t_timescale_unit.v

@@ -4,8 +4,7 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-timeunit 10ps;
+timeunit 10ps; timeprecision 10ps;
-timeprecision 10ps;
 
 task show;
   $printtimescale;
@@ -18,7 +17,7 @@ module from_unit;
 endmodule
 
 module t;
-   from_unit from_unit();
+  from_unit from_unit ();
   timeunit 100ps;
   initial begin
     show();