luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Tests: Reindent some tests. No functional change.

This commit is contained in:
Wilson Snyder 2025-11-12 19:40:59 -05:00
parent 59bc4cf66b
commit 03e5c3b2ff
16 changed files with 320 additions and 327 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test_regress/t/t_time.v
View File

@ -14,7 +14,7 @@
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (); module t;
timeunit 10ns; timeunit 10ns;
timeprecision 1ns; timeprecision 1ns;

14
test_regress/t/t_time_param.v
View File

@ -6,9 +6,11 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module vip_snitch_cluster module vip_snitch_cluster #(
#(parameter realtime ClkPeriod = 10ns) parameter realtime ClkPeriod = 10ns
(output logic clk_o); ) (
output logic clk_o
);
initial begin initial begin
forever begin forever begin
@ -30,10 +32,6 @@ endmodule
module t; module t;
logic clk; logic clk;
vip_snitch_cluster #( vip_snitch_cluster #(.ClkPeriod(1ns)) vip (.clk_o(clk));
.ClkPeriod(1ns)
) vip (
.clk_o(clk)
);
endmodule endmodule

14
test_regress/t/t_time_passed.v
View File

@ -35,10 +35,11 @@ endmodule
`timescale 1ps / 1ps `timescale 1ps / 1ps
module ps module ps (
(input clk, input clk,
input integer cyc, input integer cyc,
input time in); input time in
);
always @(posedge clk) begin always @(posedge clk) begin
if (cyc == 10) begin if (cyc == 10) begin
@ -50,10 +51,11 @@ endmodule
`timescale 1ns / 1ps `timescale 1ns / 1ps
module ns module ns (
(input clk, input clk,
input integer cyc, input integer cyc,
input time in); input time in
);
always @(posedge clk) begin always @(posedge clk) begin
if (cyc == 20) begin if (cyc == 20) begin

3
test_regress/t/t_time_print.v
View File

@ -6,8 +6,7 @@
module t; module t;
timeunit 1ns; timeunit 1ns; timeprecision 1ps;
timeprecision 1ps;
time t; time t;

6
test_regress/t/t_time_sc.v
View File

@ -4,11 +4,9 @@
// any use, without warranty, 2020 by Wilson Snyder. // any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk
); );
input clk;
integer cyc = 0; integer cyc = 0;

8
test_regress/t/t_time_stamp64.v
View File

@ -4,11 +4,9 @@
// any use, without warranty, 2020 by Wilson Snyder. // any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk
); );
input clk;
integer cyc = 0; integer cyc = 0;
@ -20,6 +18,6 @@ module t (/*AUTOARG*/
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end end
endmodule endmodule

5
test_regress/t/t_time_timeunit.v
View File

@ -4,13 +4,14 @@
// any use, without warranty, 2022 by Wilson Snyder. // any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;
timeunit 1ns; timeunit 1ns; timeprecision 1ps;
timeprecision 1ps;
initial begin initial begin
`checkd($timeunit, -9); `checkd($timeunit, -9);

8
test_regress/t/t_time_vpi.v
View File

@ -8,11 +8,9 @@
import "DPI-C" function void dpii_check(); import "DPI-C" function void dpii_check();
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk
); );
input clk;
integer cyc = 0; integer cyc = 0;
// verilator lint_off REALCVT // verilator lint_off REALCVT
@ -48,6 +46,6 @@ module t (/*AUTOARG*/
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end end
endmodule endmodule

4
test_regress/t/t_timescale_parse_bad.out
View File

@ -17,10 +17,10 @@
%Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra' %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra'
15 | `timescale 1ns / 1ps /extra 15 | `timescale 1ns / 1ps /extra
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value %Error: t/t_timescale_parse_bad.v:18:12: timeunit illegal value
18 | timeunit 2ps; 18 | timeunit 2ps;
| ^~~ | ^~~
%Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value %Error: t/t_timescale_parse_bad.v:19:17: timeprecision illegal value
19 | timeprecision 2ps; 19 | timeprecision 2ps;
| ^~~ | ^~~
%Error: Exiting due to %Error: Exiting due to

3
test_regress/t/t_timescale_unit.v
View File

@ -4,8 +4,7 @@
// any use, without warranty, 2021 by Wilson Snyder. // any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
timeunit 10ps; timeunit 10ps; timeprecision 10ps;
timeprecision 10ps;
task show; task show;
$printtimescale; $printtimescale;