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Warn on not yet implemented and ignored iff in default or transition bins (#8406) (#8407)

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This commit is contained in:
Marco Bartoli
2026-09-18 21:34:54 -04:00
committed by GitHub
parent 1cefe95c85
commit 014c9820de
4 changed files with 72 additions and 0 deletions
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src/verilog.y
+6
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@@ -7226,14 +7226,17 @@ bins_or_options<nodep>: // ==IEEE: bins_or_options
| yBINS idAny/*bin_identifier*/ bins_orBraE '=' trans_list iffE
{ FileLine* isArray = $<fl>3;
$$ = new AstCoverBin{$<fl>2, *$2, static_cast<AstCoverTransSet*>($5), VCoverBinsType{VCoverBinsType::BINS_TRANSITION}, isArray != nullptr};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in transition cover bin (guard ignored)");
DEL($6); }
| yIGNORE_BINS idAny/*bin_identifier*/ bins_orBraE '=' trans_list iffE
{ FileLine* isArray = $<fl>3;
$$ = new AstCoverBin{$<fl>2, *$2, static_cast<AstCoverTransSet*>($5), VCoverBinsType{VCoverBinsType::BINS_IGNORE}, isArray != nullptr};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in transition cover bin (guard ignored)");
DEL($6); }
| yILLEGAL_BINS idAny/*bin_identifier*/ bins_orBraE '=' trans_list iffE
{ FileLine* isArray = $<fl>3;
$$ = new AstCoverBin{$<fl>2, *$2, static_cast<AstCoverTransSet*>($5), VCoverBinsType{VCoverBinsType::BINS_ILLEGAL}, isArray != nullptr};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in transition cover bin (guard ignored)");
DEL($6); }
| yWILDCARD yBINS idAny/*bin_identifier*/ bins_orBraE '=' trans_list iffE
{ $$ = nullptr; BBCOVERIGN($<fl>1, "Unsupported: 'wildcard' transition list in cover bin"); DEL($6, $7);}
@@ -7244,12 +7247,15 @@ bins_or_options<nodep>: // ==IEEE: bins_or_options
//
| yBINS idAny/*bin_identifier*/ bins_orBraE '=' yDEFAULT iffE
{ $$ = new AstCoverBin{$<fl>2, *$2, VCoverBinsType::BINS_DEFAULT};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in default cover bin (guard ignored)");
DEL($6); }
| yIGNORE_BINS idAny/*bin_identifier*/ bins_orBraE '=' yDEFAULT iffE
{ $$ = new AstCoverBin{$<fl>2, *$2, VCoverBinsType::BINS_IGNORE};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in default cover bin (guard ignored)");
DEL($6); }
| yILLEGAL_BINS idAny/*bin_identifier*/ bins_orBraE '=' yDEFAULT iffE
{ $$ = new AstCoverBin{$<fl>2, *$2, VCoverBinsType::BINS_ILLEGAL};
if ($6) BBCOVERIGN($6->fileline(), "Unsupported: 'iff' in default cover bin (guard ignored)");
DEL($6); }
| yBINS idAny/*bin_identifier*/ bins_orBraE '=' yDEFAULT ySEQUENCE iffE
{ $$ = nullptr; BBCOVERIGN($<fl>6, "Unsupported: 'sequence' in default cover bin"); DEL($7); }
test_regress/t/t_covergroup_iff_unsup.out
+21
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@@ -0,0 +1,21 @@
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:13:35: Unsupported: 'iff' in transition cover bin (guard ignored)
13 | bins normal = (0 => 1) iff (enabled);
| ^~~~~~~
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:14:43: Unsupported: 'iff' in transition cover bin (guard ignored)
14 | ignore_bins ignored = (1 => 2) iff (!enabled);
| ^
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:15:52: Unsupported: 'iff' in transition cover bin (guard ignored)
15 | illegal_bins illegal = (2 => 3) iff (enabled && value != 0);
| ^~
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:18:36: Unsupported: 'iff' in default cover bin (guard ignored)
18 | bins fallback = default iff (enabled);
| ^~~~~~~
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:21:43: Unsupported: 'iff' in default cover bin (guard ignored)
21 | ignore_bins fallback = default iff (!enabled);
| ^
%Warning-COVERIGN: t/t_covergroup_iff_unsup.v:24:52: Unsupported: 'iff' in default cover bin (guard ignored)
24 | illegal_bins fallback = default iff (enabled && value != 0);
| ^~
%Error: Exiting due to
test_regress/t/t_covergroup_iff_unsup.py
Executable
+16
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@@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()
test_regress/t/t_covergroup_iff_unsup.v
+29
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@@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
bit [1:0] value;
bit enabled;
covergroup cg;
transitions: coverpoint value {
bins normal = (0 => 1) iff (enabled);
ignore_bins ignored = (1 => 2) iff (!enabled);
illegal_bins illegal = (2 => 3) iff (enabled && value != 0);
}
normal_default: coverpoint value {
bins fallback = default iff (enabled);
}
ignored_default: coverpoint value {
ignore_bins fallback = default iff (!enabled);
}
illegal_default: coverpoint value {
illegal_bins fallback = default iff (enabled && value != 0);
}
endgroup
cg inst = new;
endmodule