2024-09-08 19:00:03 +02:00
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = test.obj_dir + "/t_gate_chained.v"
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def gen(filename):
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with open(filename, 'w', encoding="utf8") as fh:
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fh.write("// Generated by t_gate_chained.py\n")
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fh.write("module t (clk,i,sel,o);\n")
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fh.write(" input clk;\n")
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fh.write(" input [63:0] i;\n")
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fh.write(" input [15:0] sel;\n")
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fh.write(" output [63:0] o;\n")
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fh.write("\n")
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prev = "i"
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n = 9000
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for i in range(1, n):
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fh.write(
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(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : " + prev + ";\n") % (i, i))
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prev = "ass%04x" % i
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fh.write("\n")
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fh.write(" wire [63:0] o = " + prev + ";\n")
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fh.write("\n")
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fh.write(" always @ (posedge clk) begin\n")
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fh.write(' $write("*-* All Finished *-*\\n");' + "\n")
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fh.write(' $finish;' + "\n")
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fh.write(" end\n")
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fh.write("endmodule\n")
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gen(test.top_filename)
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test.compile(
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verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS -fno-dfg"])
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test.execute()
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# Must be <<9000 above to prove this worked
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Internals: Make AstAssignW a procedural statement (#6280) (#6556)
Initial idea was to remodel AssignW as Assign under Alway. Trying that
uncovered some issues, the most difficult of them was that a delay
attached to a continuous assignment behaves differently from a delay
attached to a blocking assignment statement, so we need to keep the
knowledge of which flavour an assignment was until V3Timing.
So instead of removing AstAssignW, we always wrap it in an AstAlways,
with a special `keyword()` type. This makes it into a proper procedural
statement, which is almost equivalent to AstAssign, except for the case
when they contain a delay. We still gain the benefits of #6280 and can
simplify some code. Every AstNodeStmt should now be under an
AstNodeProcedure - which we should rename to AstProcess, or an
AstNodeFTask). As a result, V3Table can now handle AssignW for free.
Also uncovered and fixed a bug in handling intra-assignment delays if
a function is present on the RHS of an AssignW.
There is more work to be done towards #6280, and potentially simplifying
AssignW handing, but this is the minimal change required to tick it off
the TODO list for #6280.
2025-10-14 10:05:19 +02:00
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test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8554)
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2024-09-08 19:00:03 +02:00
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test.passes()
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