2024-03-28 01:07:46 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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2024-03-28 01:07:46 +01:00
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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2026-03-10 02:38:29 +01:00
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class Cls #(
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parameter int PARAM
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);
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static int s_cls_static = 123;
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endclass
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2026-03-10 02:38:29 +01:00
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module top ();
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typedef Cls#(.PARAM(0)) Cls_t;
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2024-03-28 01:07:46 +01:00
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2026-03-10 02:38:29 +01:00
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Cls_t obj;
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2024-03-28 01:07:46 +01:00
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2026-03-10 02:38:29 +01:00
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initial begin
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obj = new;
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`ifdef verilator
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obj.s_cls_static = $c("100"); // no-opt
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2024-03-28 01:07:46 +01:00
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`else
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obj.s_cls_static = 100;
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`endif
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if (obj.s_cls_static != 100) $stop;
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if (obj.PARAM != 0) $stop;
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars(0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2024-03-28 01:07:46 +01:00
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endmodule
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