verilator/test_regress/t/t_sys_plusargs_bad.v

25 lines
556 B
Systemverilog
Raw Normal View History

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2009 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
2026-03-10 02:38:29 +01:00
integer p_i;
2026-03-10 02:38:29 +01:00
initial begin
// BAD: Missing argument
if ($value$plusargs("NOTTHERE", p_i) !== 0) $stop;
2026-03-10 02:38:29 +01:00
// BAD: Bad letter
if ($value$plusargs("INT=%z", p_i) !== 0) $stop;
2026-03-10 02:38:29 +01:00
// BAD: Multi letter
if ($value$plusargs("INT=%x%x", p_i) !== 0) $stop;
2026-03-10 02:38:29 +01:00
$write("*-* All Finished *-*\n");
$finish;
end
endmodule