verilator/test_regress/t/t_select_bad_width0.out

%Error: t/t_select_bad_width0.v:15:29: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
                                     : ... note: In instance 't'
   15 |     automatic int part = val[left+:ZERO];
      |                             ^
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:29: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
                                                   : ... note: In instance 't'
   15 |     automatic int part = val[left+:ZERO];
      |                             ^
                      ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
                      ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
%Error: t/t_select_bad_width0.v:17:15: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
                                     : ... note: In instance 't'
   17 |     part = val[left-:ZERO];
      |               ^
%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:17:10: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
                                                   : ... note: In instance 't'
   17 |     part = val[left-:ZERO];
      |          ^
%Error: Exiting due to