2024-03-02 15:06:22 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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2024-03-02 15:06:22 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2026-03-08 23:26:40 +01:00
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// verilog_format: off
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2024-03-02 15:06:22 +01:00
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`begin_keywords "1800-2023"
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`define ZERO 0
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`ifdef ( ZERO )
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// ...
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`endif
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