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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2017-09-15 03:20:20 +02:00
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2026-03-10 02:38:29 +01:00
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module m #(
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parameter int Foo
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);
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endmodule
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2025-09-13 15:28:43 +02:00
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module t;
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2026-03-10 02:38:29 +01:00
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m foo ();
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2017-09-15 03:20:20 +02:00
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endmodule
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