2015-05-09 20:01:54 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Wilson Snyder
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2015-05-09 20:01:54 +02:00
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module t;
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2026-03-10 02:38:29 +01:00
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function integer bottom_4bits;
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input [7:0] i;
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bottom_4bits = 0;
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bottom_4bits[3:0] = i[3:0];
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endfunction
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2015-05-09 20:01:54 +02:00
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2026-03-10 02:38:29 +01:00
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function integer bottom_2_unknown;
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input [7:0] i;
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// bottom_4bits = 0; 'x
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bottom_2_unknown[1:0] = i[1:0];
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endfunction
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2015-05-09 20:01:54 +02:00
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2026-03-10 02:38:29 +01:00
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localparam P = bottom_4bits(8'h13);
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localparam BU = bottom_2_unknown(8'h13);
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2015-05-09 20:01:54 +02:00
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2026-03-10 02:38:29 +01:00
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initial begin
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if (P != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2015-05-09 20:01:54 +02:00
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endmodule
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