2022-10-22 19:45:48 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2019 Todd Strader
|
2022-10-22 19:45:48 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
module secret_impl;
|
2026-03-10 02:38:29 +01:00
|
|
|
initial begin
|
|
|
|
|
#10;
|
|
|
|
|
$stop;
|
|
|
|
|
end
|
2022-10-22 19:45:48 +02:00
|
|
|
endmodule
|