2012-07-29 16:16:20 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2009 Wilson Snyder
|
2020-03-21 16:24:24 +01:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
2012-07-29 16:16:20 +02:00
|
|
|
|
|
|
|
|
module x;
|
|
|
|
|
|
2026-03-08 23:26:40 +01:00
|
|
|
typedef struct {int a;} notpacked_t;
|
2012-07-29 16:16:20 +02:00
|
|
|
|
2026-03-08 23:26:40 +01:00
|
|
|
typedef struct packed {notpacked_t b;} ispacked_t;
|
2012-07-29 16:16:20 +02:00
|
|
|
|
2026-03-08 23:26:40 +01:00
|
|
|
ispacked_t p;
|
2013-10-29 01:41:05 +01:00
|
|
|
|
2026-03-08 23:26:40 +01:00
|
|
|
initial begin
|
|
|
|
|
p.b = 1;
|
|
|
|
|
if (p.b != 1) $stop;
|
|
|
|
|
$write("*-* All Finished *-*\n");
|
|
|
|
|
$finish;
|
|
|
|
|
end
|
2012-07-29 16:16:20 +02:00
|
|
|
endmodule
|