2025-07-16 23:25:01 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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2025-07-16 23:25:01 +02:00
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// SPDX-License-Identifier: CC0-1.0
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class setup_coefficients;
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2026-03-08 23:26:40 +01:00
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static function int create();
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return 1;
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endfunction
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2025-07-16 23:25:01 +02:00
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endclass
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class biquad_vseq;
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2026-03-08 23:26:40 +01:00
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int c_setup = setup_coefficients::create();
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function void setup_coefficients();
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endfunction
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endclass : biquad_vseq
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